From 8550416724ae7be22d015180fc7693cd5af5412c Mon Sep 17 00:00:00 2001 From: sokolovstanislav Date: Wed, 3 May 2023 12:18:32 +0300 Subject: [PATCH] Added the compatibility another cores --- IP_AXI_ADC/IP_AXI_ADC_2.0/component.xml | 19 +- .../IP_AXI_INVERTER_1.0/component.xml | 14 +- IP_AXI_PWM/IP_AXI_PWM_1.0/component.xml | 16 +- .../362e20292c8426d9/362e20292c8426d9.xci | 37 + .../AckChecker_BusBlock16IN_0_0.dcp | Bin 0 -> 5520 bytes .../AckChecker_BusBlock16IN_0_0_sim_netlist.v | 142 + ...kChecker_BusBlock16IN_0_0_sim_netlist.vhdl | 69 + .../AckChecker_BusBlock16IN_0_0_stub.v | 37 + .../AckChecker_BusBlock16IN_0_0_stub.vhdl | 46 + .../ip/2019.1/362e20292c8426d9/stats.txt | 2 + .../620c0a6afb1e6b3a/620c0a6afb1e6b3a.xci | 37 + .../AckChecker_BusBlock16OUT_0_0.dcp | Bin 0 -> 8883 bytes ...AckChecker_BusBlock16OUT_0_0_sim_netlist.v | 319 ++ ...Checker_BusBlock16OUT_0_0_sim_netlist.vhdl | 247 + .../AckChecker_BusBlock16OUT_0_0_stub.v | 38 + .../AckChecker_BusBlock16OUT_0_0_stub.vhdl | 47 + .../ip/2019.1/620c0a6afb1e6b3a/stats.txt | 2 + .../9fc500b6c8c4592a/9fc500b6c8c4592a.xci | 38 + .../AckChecker_AckCheckerConcept_0_0.dcp | Bin 0 -> 19059 bytes ...hecker_AckCheckerConcept_0_0_sim_netlist.v | 764 +++ ...ker_AckCheckerConcept_0_0_sim_netlist.vhdl | 927 ++++ .../AckChecker_AckCheckerConcept_0_0_stub.v | 30 + ...AckChecker_AckCheckerConcept_0_0_stub.vhdl | 39 + .../ip/2019.1/9fc500b6c8c4592a/stats.txt | 2 + .../AckCheckerBlock.cache/wt/gui_handlers.wdf | 52 +- .../wt/java_command_handlers.wdf | 15 +- .../AckCheckerBlock.cache/wt/project.wpc | 2 +- .../AckCheckerBlock.cache/wt/synthesis.wdf | 8 +- .../AckCheckerBlock.cache/wt/webtalk_pa.xml | 69 +- .../.jobs/vrs_config_5.xml | 179 + .../.vivado.begin.rst | 2 +- .../AckChecker_AckCheckerConcept_0_0.dcp | Bin 19068 -> 19103 bytes .../AckChecker_AckCheckerConcept_0_0.tcl | 40 +- .../AckChecker_AckCheckerConcept_0_0.vds | 83 +- ...ckCheckerConcept_0_0_utilization_synth.rpt | 4 +- .../gen_run.xml | 6 +- .../project.wdf | 75 - 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Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5}/Inverter_3lvl_P0N_3lvl_0_5.dcp (99%) create mode 100644 LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5_sim_netlist.v create mode 100644 LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5_sim_netlist.vhdl create mode 100644 LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5_stub.v create mode 100644 LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5_stub.vhdl rename LIB/Inverter_3lvl/{Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1 => Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0}/Inverter_3lvl_P0N_3lvl_1_0.dcp (99%) create mode 100644 LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0_sim_netlist.v create mode 100644 LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0_sim_netlist.vhdl create mode 100644 LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0_stub.v create mode 100644 LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0_stub.vhdl rename LIB/Inverter_3lvl/{Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1 => Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1}/Inverter_3lvl_P0N_3lvl_1_1.dcp (99%) create mode 100644 LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1_sim_netlist.v create mode 100644 LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1_sim_netlist.vhdl create mode 100644 LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1_stub.v create mode 100644 LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1_stub.vhdl diff --git a/IP_AXI_ADC/IP_AXI_ADC_2.0/component.xml b/IP_AXI_ADC/IP_AXI_ADC_2.0/component.xml index edb16f8..b1f8971 100644 --- a/IP_AXI_ADC/IP_AXI_ADC_2.0/component.xml +++ b/IP_AXI_ADC/IP_AXI_ADC_2.0/component.xml @@ -993,13 +993,14 @@ zynq + artix7 AXI_Peripheral IP_AXI_ADC_v2.0 - 18 - 2021-09-10T09:11:34Z + 20 + 2023-04-27T15:23:05Z d:/GITEA/IP/IP_AXI_ADC/IP_AXI_ADC_2.0 d:/GITEA/IP/IP_AXI_ADC/IP_AXI_ADC_2.0 @@ -1199,6 +1200,20 @@ d:/GITEA/UPzynq20_test/IP/IP_AXI_ADC/IP_AXI_ADC_2.0 d:/GITEA/UPzynq20_test/IP/IP_AXI_ADC/IP_AXI_ADC_2.0 d:/GITEA/UPzynq20_test/IP/IP_AXI_ADC/IP_AXI_ADC_2.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_ADC/IP_AXI_ADC_2.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_ADC/IP_AXI_ADC_2.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_ADC/IP_AXI_ADC_2.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_ADC/IP_AXI_ADC_2.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_ADC/IP_AXI_ADC_2.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_ADC/IP_AXI_ADC_2.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_ADC/IP_AXI_ADC_2.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_ADC/IP_AXI_ADC_2.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_ADC/IP_AXI_ADC_2.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_ADC/IP_AXI_ADC_2.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_ADC/IP_AXI_ADC_2.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_ADC/IP_AXI_ADC_2.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_ADC/IP_AXI_ADC_2.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_ADC/IP_AXI_ADC_2.0 diff --git a/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0/component.xml b/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0/component.xml index f5d55ef..7f5cbd9 100644 --- a/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0/component.xml +++ b/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0/component.xml @@ -1451,6 +1451,7 @@ zynq + artix7 AXI_Peripheral @@ -1458,11 +1459,11 @@ IP_AXI_INVERTER_v1.0 S7DNRJ https://ssevendenergy.com - 5 + 6 setcorp:user:IP_AXI_INVERTER:1.0 - 2021-06-10T13:27:55Z + 2023-05-03T08:03:05Z d:/Projects/IP/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0 d:/Projects/IP/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0 @@ -1527,6 +1528,15 @@ d:/GITEA/UPzynq20_test/IP/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0 d:/GITEA/UPzynq20_test/IP/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0 d:/GITEA/UPzynq20_test/IP/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_INVERTER/IP_AXI_INVERTER_1.0 diff --git a/IP_AXI_PWM/IP_AXI_PWM_1.0/component.xml b/IP_AXI_PWM/IP_AXI_PWM_1.0/component.xml index d618256..e2eb96b 100644 --- a/IP_AXI_PWM/IP_AXI_PWM_1.0/component.xml +++ b/IP_AXI_PWM/IP_AXI_PWM_1.0/component.xml @@ -877,13 +877,14 @@ zynq + artix7 AXI_Peripheral IP_AXI_PWM_v1.0 - 7 - 2021-08-12T12:22:11Z + 8 + 2023-05-03T07:39:26Z d:/GITEA/UPzynq20_test/IP/IP_AXI_PWM/IP_AXI_PWM_1.0 d:/GITEA/UPzynq20_test/IP/IP_AXI_PWM/IP_AXI_PWM_1.0 @@ -946,6 +947,15 @@ d:/GITEA/UPzynq20_test/IP/IP_AXI_PWM/IP_AXI_PWM_1.0 d:/GITEA/UPzynq20_test/IP/IP_AXI_PWM/IP_AXI_PWM_1.0 d:/GITEA/UPzynq20_test/IP/IP_AXI_PWM/IP_AXI_PWM_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_PWM/IP_AXI_PWM_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_PWM/IP_AXI_PWM_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_PWM/IP_AXI_PWM_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_PWM/IP_AXI_PWM_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_PWM/IP_AXI_PWM_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_PWM/IP_AXI_PWM_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_PWM/IP_AXI_PWM_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_PWM/IP_AXI_PWM_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_PWM/IP_AXI_PWM_1.0 @@ -953,7 +963,7 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/362e20292c8426d9/362e20292c8426d9.xci b/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/362e20292c8426d9/362e20292c8426d9.xci new file mode 100644 index 0000000..15f58c5 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/362e20292c8426d9/362e20292c8426d9.xci @@ -0,0 +1,37 @@ + + + xilinx.com + ipcache + 362e20292c8426d9 + 0 + + + AckChecker_BusBlock16IN_0_0 + + + AckChecker_BusBlock16IN_0_0 + zynq + xc7z020 + clg484 + VHDL + + -3 + + + TRUE + TRUE + 362e20292c8426d9 + 8a237664 + 35 + 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All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:54 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ AckChecker_BusBlock16IN_0_0_sim_netlist.v +// Design : AckChecker_BusBlock16IN_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "AckChecker_BusBlock16IN_0_0,BusBlock16IN,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "BusBlock16IN,Vivado 2019.1" *) +(* NotValidForBitStream *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix + (Bus_16IN, + Out0, + Out1, + Out2, + Out3, + Out4, + Out5, + Out6, + Out7, + Out8, + Out9, + Out10, + Out11, + Out12, + Out13, + Out14, + Out15); + input [15:0]Bus_16IN; + output Out0; + output Out1; + output Out2; + output Out3; + output Out4; + output Out5; + output Out6; + output Out7; + output Out8; + output Out9; + output Out10; + output Out11; + output Out12; + output Out13; + output Out14; + output Out15; + + wire [15:0]Bus_16IN; + + assign Out0 = Bus_16IN[0]; + assign Out1 = Bus_16IN[1]; + assign Out10 = Bus_16IN[10]; + assign Out11 = Bus_16IN[11]; + assign Out12 = Bus_16IN[12]; + assign Out13 = Bus_16IN[13]; + assign Out14 = Bus_16IN[14]; + assign Out15 = Bus_16IN[15]; + assign Out2 = Bus_16IN[2]; + assign Out3 = Bus_16IN[3]; + assign Out4 = Bus_16IN[4]; + assign Out5 = Bus_16IN[5]; + assign Out6 = Bus_16IN[6]; + assign Out7 = Bus_16IN[7]; + assign Out8 = Bus_16IN[8]; + assign Out9 = Bus_16IN[9]; +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/362e20292c8426d9/AckChecker_BusBlock16IN_0_0_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/362e20292c8426d9/AckChecker_BusBlock16IN_0_0_sim_netlist.vhdl new file mode 100644 index 0000000..e6731a2 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/362e20292c8426d9/AckChecker_BusBlock16IN_0_0_sim_netlist.vhdl @@ -0,0 +1,69 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:54 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ AckChecker_BusBlock16IN_0_0_sim_netlist.vhdl +-- Design : AckChecker_BusBlock16IN_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + port ( + Bus_16IN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + Out0 : out STD_LOGIC; + Out1 : out STD_LOGIC; + Out2 : out STD_LOGIC; + Out3 : out STD_LOGIC; + Out4 : out STD_LOGIC; + Out5 : out STD_LOGIC; + Out6 : out STD_LOGIC; + Out7 : out STD_LOGIC; + Out8 : out STD_LOGIC; + Out9 : out STD_LOGIC; + Out10 : out STD_LOGIC; + Out11 : out STD_LOGIC; + Out12 : out STD_LOGIC; + Out13 : out STD_LOGIC; + Out14 : out STD_LOGIC; + Out15 : out STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "AckChecker_BusBlock16IN_0_0,BusBlock16IN,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "BusBlock16IN,Vivado 2019.1"; +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + signal \^bus_16in\ : STD_LOGIC_VECTOR ( 15 downto 0 ); +begin + Out0 <= \^bus_16in\(0); + Out1 <= \^bus_16in\(1); + Out10 <= \^bus_16in\(10); + Out11 <= \^bus_16in\(11); + Out12 <= \^bus_16in\(12); + Out13 <= \^bus_16in\(13); + Out14 <= \^bus_16in\(14); + Out15 <= \^bus_16in\(15); + Out2 <= \^bus_16in\(2); + Out3 <= \^bus_16in\(3); + Out4 <= \^bus_16in\(4); + Out5 <= \^bus_16in\(5); + Out6 <= \^bus_16in\(6); + Out7 <= \^bus_16in\(7); + Out8 <= \^bus_16in\(8); + Out9 <= \^bus_16in\(9); + \^bus_16in\(15 downto 0) <= Bus_16IN(15 downto 0); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/362e20292c8426d9/AckChecker_BusBlock16IN_0_0_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/362e20292c8426d9/AckChecker_BusBlock16IN_0_0_stub.v new file mode 100644 index 0000000..349d237 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/362e20292c8426d9/AckChecker_BusBlock16IN_0_0_stub.v @@ -0,0 +1,37 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:54 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ AckChecker_BusBlock16IN_0_0_stub.v +// Design : AckChecker_BusBlock16IN_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "BusBlock16IN,Vivado 2019.1" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(Bus_16IN, Out0, Out1, Out2, Out3, Out4, Out5, Out6, Out7, + Out8, Out9, Out10, Out11, Out12, Out13, Out14, Out15) +/* synthesis syn_black_box black_box_pad_pin="Bus_16IN[15:0],Out0,Out1,Out2,Out3,Out4,Out5,Out6,Out7,Out8,Out9,Out10,Out11,Out12,Out13,Out14,Out15" */; + input [15:0]Bus_16IN; + output Out0; + output Out1; + output Out2; + output Out3; + output Out4; + output Out5; + output Out6; + output Out7; + output Out8; + output Out9; + output Out10; + output Out11; + output Out12; + output Out13; + output Out14; + output Out15; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/362e20292c8426d9/AckChecker_BusBlock16IN_0_0_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/362e20292c8426d9/AckChecker_BusBlock16IN_0_0_stub.vhdl new file mode 100644 index 0000000..914eb57 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/362e20292c8426d9/AckChecker_BusBlock16IN_0_0_stub.vhdl @@ -0,0 +1,46 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:54 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ AckChecker_BusBlock16IN_0_0_stub.vhdl +-- Design : AckChecker_BusBlock16IN_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + Bus_16IN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + Out0 : out STD_LOGIC; + Out1 : out STD_LOGIC; + Out2 : out STD_LOGIC; + Out3 : out STD_LOGIC; + Out4 : out STD_LOGIC; + Out5 : out STD_LOGIC; + Out6 : out STD_LOGIC; + Out7 : out STD_LOGIC; + Out8 : out STD_LOGIC; + Out9 : out STD_LOGIC; + Out10 : out STD_LOGIC; + Out11 : out STD_LOGIC; + Out12 : out STD_LOGIC; + Out13 : out STD_LOGIC; + Out14 : out STD_LOGIC; + Out15 : out STD_LOGIC + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "Bus_16IN[15:0],Out0,Out1,Out2,Out3,Out4,Out5,Out6,Out7,Out8,Out9,Out10,Out11,Out12,Out13,Out14,Out15"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "BusBlock16IN,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/362e20292c8426d9/stats.txt b/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/362e20292c8426d9/stats.txt new file mode 100644 index 0000000..96023e5 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/362e20292c8426d9/stats.txt @@ -0,0 +1,2 @@ +NumberHits:7 +Timestamp: Wed May 03 08:37:41 UTC 2023 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/620c0a6afb1e6b3a/620c0a6afb1e6b3a.xci b/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/620c0a6afb1e6b3a/620c0a6afb1e6b3a.xci new file mode 100644 index 0000000..a3a973b --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/620c0a6afb1e6b3a/620c0a6afb1e6b3a.xci @@ -0,0 +1,37 @@ + + + xilinx.com + ipcache + 620c0a6afb1e6b3a + 0 + + + AckChecker_BusBlock16OUT_0_0 + + + AckChecker_BusBlock16OUT_0_0 + zynq + xc7z020 + clg484 + VHDL + + -3 + + + TRUE + TRUE + 620c0a6afb1e6b3a + 33b49d5e + 35 + IP_Unknown + 5 + TRUE + . + + . + 2019.1 + GLOBAL + + + + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/620c0a6afb1e6b3a/AckChecker_BusBlock16OUT_0_0.dcp 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z>!^_4dPvTw>t__kd8|)kFyeRB8aIDzHq{1MYgKABFtxy=*gs1|CKK|p`x{e#5c3(H z$j~n`=jrwS3dBA*nLT(O(wj^~r5Cl8u+?a89t4}&{%D@x+-BfeTskxt-@!H~>SYQ{ zF2Dj2QjM?+CMDVHN81z{(mz4}dq^oomTG*0!C&x18B@KURWRO^G3rGAz{+)|)^GSk$s>EzGtqhKPg89+V^IYrd);?Dx zyV%-b7Hd+>4!coPiIGD1O{YZ{o`IT&vaC+F{bh3(G={Gg=BhpeY}7|ZC=LHbj!_W} z1eUl)nO5zJ3XDj~q?K-Iq-=tE{Su_|%<%Asq&JA$=aA8}0)?U~fgjtP_ZZ1%BEnXdI@j!%irvU_5e5;^vs~%VUQ!(7Tyg|3`sf8HzdE?e zU{44$VsSm+Ub0;lyj){2_Zd;7PMT=dCKr@2=)cnAG<FDOXv zpc?%CJpG>&_m`bs9^U?O{io9s52qLAUpOH`%S*PGTF4)^KUaevG1gz$ zfVMBmUVaY#5dHJIrX>G=vKJqRm&7j@@&6DbzWxjGKTE_*!k4See+U~%|0_bsnxiBK zkMO4-3gm|lS*?sAS`rJ?2ToTub8#+tE`X!9guRNf2ak*MJ6 X"8" + ) + port map ( + I0 => In0, + I1 => Mask(0), + O => Bus_16OUT(0) + ); +\Bus_16OUT[10]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In10, + I1 => Mask(10), + O => Bus_16OUT(10) + ); +\Bus_16OUT[11]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In11, + I1 => Mask(11), + O => Bus_16OUT(11) + ); +\Bus_16OUT[12]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In12, + I1 => Mask(12), + O => Bus_16OUT(12) + ); +\Bus_16OUT[13]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In13, + I1 => Mask(13), + O => Bus_16OUT(13) + ); +\Bus_16OUT[14]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In14, + I1 => Mask(14), + O => Bus_16OUT(14) + ); +\Bus_16OUT[15]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In15, + I1 => Mask(15), + O => Bus_16OUT(15) + ); +\Bus_16OUT[1]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In1, + I1 => Mask(1), + O => Bus_16OUT(1) + ); +\Bus_16OUT[2]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In2, + I1 => Mask(2), + O => Bus_16OUT(2) + ); +\Bus_16OUT[3]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In3, + I1 => Mask(3), + O => Bus_16OUT(3) + ); +\Bus_16OUT[4]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In4, + I1 => Mask(4), + O => Bus_16OUT(4) + ); +\Bus_16OUT[5]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In5, + I1 => Mask(5), + O => Bus_16OUT(5) + ); +\Bus_16OUT[6]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In6, + I1 => Mask(6), + O => Bus_16OUT(6) + ); +\Bus_16OUT[7]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In7, + I1 => Mask(7), + O => Bus_16OUT(7) + ); +\Bus_16OUT[8]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In8, + I1 => Mask(8), + O => Bus_16OUT(8) + ); +\Bus_16OUT[9]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In9, + I1 => Mask(9), + O => Bus_16OUT(9) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + port ( + Bus_16OUT : out STD_LOGIC_VECTOR ( 15 downto 0 ); + In0 : in STD_LOGIC; + In1 : in STD_LOGIC; + In2 : in STD_LOGIC; + In3 : in STD_LOGIC; + In4 : in STD_LOGIC; + In5 : in STD_LOGIC; + In6 : in STD_LOGIC; + In7 : in STD_LOGIC; + In8 : in STD_LOGIC; + In9 : in STD_LOGIC; + In10 : in STD_LOGIC; + In11 : in STD_LOGIC; + In12 : in STD_LOGIC; + In13 : in STD_LOGIC; + In14 : in STD_LOGIC; + In15 : in STD_LOGIC; + Mask : in STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "AckChecker_BusBlock16OUT_0_0,BusBlock16OUT,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "BusBlock16OUT,Vivado 2019.1"; +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +begin +U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_BusBlock16OUT + port map ( + Bus_16OUT(15 downto 0) => Bus_16OUT(15 downto 0), + In0 => In0, + In1 => In1, + In10 => In10, + In11 => In11, + In12 => In12, + In13 => In13, + In14 => In14, + In15 => In15, + In2 => In2, + In3 => In3, + In4 => In4, + In5 => In5, + In6 => In6, + In7 => In7, + In8 => In8, + In9 => In9, + Mask(15 downto 0) => Mask(15 downto 0) + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/620c0a6afb1e6b3a/AckChecker_BusBlock16OUT_0_0_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/620c0a6afb1e6b3a/AckChecker_BusBlock16OUT_0_0_stub.v new file mode 100644 index 0000000..23428b1 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/620c0a6afb1e6b3a/AckChecker_BusBlock16OUT_0_0_stub.v @@ -0,0 +1,38 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:54 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ AckChecker_BusBlock16OUT_0_0_stub.v +// Design : AckChecker_BusBlock16OUT_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "BusBlock16OUT,Vivado 2019.1" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(Bus_16OUT, In0, In1, In2, In3, In4, In5, In6, In7, In8, In9, + In10, In11, In12, In13, In14, In15, Mask) +/* synthesis syn_black_box black_box_pad_pin="Bus_16OUT[15:0],In0,In1,In2,In3,In4,In5,In6,In7,In8,In9,In10,In11,In12,In13,In14,In15,Mask[15:0]" */; + output [15:0]Bus_16OUT; + input In0; + input In1; + input In2; + input In3; + input In4; + input In5; + input In6; + input In7; + input In8; + input In9; + input In10; + input In11; + input In12; + input In13; + input In14; + input In15; + input [15:0]Mask; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/620c0a6afb1e6b3a/AckChecker_BusBlock16OUT_0_0_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/620c0a6afb1e6b3a/AckChecker_BusBlock16OUT_0_0_stub.vhdl new file mode 100644 index 0000000..ebcf843 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/620c0a6afb1e6b3a/AckChecker_BusBlock16OUT_0_0_stub.vhdl @@ -0,0 +1,47 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:54 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ AckChecker_BusBlock16OUT_0_0_stub.vhdl +-- Design : AckChecker_BusBlock16OUT_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + Bus_16OUT : out STD_LOGIC_VECTOR ( 15 downto 0 ); + In0 : in STD_LOGIC; + In1 : in STD_LOGIC; + In2 : in STD_LOGIC; + In3 : in STD_LOGIC; + In4 : in STD_LOGIC; + In5 : in STD_LOGIC; + In6 : in STD_LOGIC; + In7 : in STD_LOGIC; + In8 : in STD_LOGIC; + In9 : in STD_LOGIC; + In10 : in STD_LOGIC; + In11 : in STD_LOGIC; + In12 : in STD_LOGIC; + In13 : in STD_LOGIC; + In14 : in STD_LOGIC; + In15 : in STD_LOGIC; + Mask : in STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "Bus_16OUT[15:0],In0,In1,In2,In3,In4,In5,In6,In7,In8,In9,In10,In11,In12,In13,In14,In15,Mask[15:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "BusBlock16OUT,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/620c0a6afb1e6b3a/stats.txt b/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/620c0a6afb1e6b3a/stats.txt new file mode 100644 index 0000000..51465ec --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/620c0a6afb1e6b3a/stats.txt @@ -0,0 +1,2 @@ +NumberHits:3 +Timestamp: Wed May 03 08:37:26 UTC 2023 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/9fc500b6c8c4592a/9fc500b6c8c4592a.xci b/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/9fc500b6c8c4592a/9fc500b6c8c4592a.xci new file mode 100644 index 0000000..926b241 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/9fc500b6c8c4592a/9fc500b6c8c4592a.xci @@ -0,0 +1,38 @@ + + + xilinx.com + ipcache + 9fc500b6c8c4592a + 0 + + + AckChecker_AckCheckerConcept_0_0 + + + 100000000 + AckChecker_AckCheckerConcept_0_0 + zynq + xc7z020 + clg484 + VHDL + + -3 + + + TRUE + TRUE + 9fc500b6c8c4592a + 29f83029 + 36 + IP_Unknown + 2 + TRUE + . + + . + 2019.1 + GLOBAL + + + + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/9fc500b6c8c4592a/AckChecker_AckCheckerConcept_0_0.dcp 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zrnOZ-z`R8$NheU=uvGS-ux}~vX^k$XaJ#wx6bj6QI9L32jxAQq>Urjwx@Ofh6+ttL zNh>zXss(x}Om%E8YV>pr4%%{Xn%I=c>805z&oiFSJbboi56fchH?PjMXx^QZy`HUh z_mA4^%j;M7mH+VwW<48T@OSwEPlLysJk1K~fNRGYff)w(SvA0%!~l#phHZ@?7WCvA zbWP|dpMaD?G(87Wh{I2CpM!#KBKjhBgo$|)M3@L#(vEH<`Vw@Iksz?Gkr_DQP0*3R z1?lJ}qOX1inFjIpEh%D5gsp`}Hy3?fGRRyI*w#2hnh0~jtCZ2rL|@?mG7sX`MZnUM zpznd}9neigUoHSL5d^k1F4rK!#ELw01JP?3kYNxf9(5vYAX X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "AckCheckerConcept,Vivado 2019.1"; +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/9fc500b6c8c4592a/AckChecker_AckCheckerConcept_0_0_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/9fc500b6c8c4592a/AckChecker_AckCheckerConcept_0_0_stub.v new file mode 100644 index 0000000..2e5c113 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/9fc500b6c8c4592a/AckChecker_AckCheckerConcept_0_0_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/9fc500b6c8c4592a/AckChecker_AckCheckerConcept_0_0_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/9fc500b6c8c4592a/AckChecker_AckCheckerConcept_0_0_stub.vhdl new file mode 100644 index 0000000..756ab3d --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/9fc500b6c8c4592a/AckChecker_AckCheckerConcept_0_0_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/9fc500b6c8c4592a/stats.txt b/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/9fc500b6c8c4592a/stats.txt new file mode 100644 index 0000000..2a1d486 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip/2019.1/9fc500b6c8c4592a/stats.txt @@ -0,0 +1,2 @@ +NumberHits:31 +Timestamp: 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73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a323573:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313031332e3537344d42:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3632332e3035354d42:00:00 -eof:3395228048 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a323873:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313032342e3830314d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3633302e3537384d42:00:00 +eof:3984491813 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt/webtalk_pa.xml b/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt/webtalk_pa.xml index ab1c3f7..67eb241 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt/webtalk_pa.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -18,45 +18,63 @@ This means code written to parse this file will need to be revisited each subseq - + + + - + - + + - + - + - - + + + + - - + + + + - - - + + + + + + + + + - - + + + + + - + + + @@ -67,19 +85,24 @@ This means code written to parse this file will need to be revisited each subseq - + - + + - - + + + + + - + + @@ -91,9 +114,9 @@ This means code written to parse this file will need to be revisited each subseq - + - +
diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/.jobs/vrs_config_5.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/.jobs/vrs_config_5.xml new file mode 100644 index 0000000..d107124 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/.jobs/vrs_config_5.xml @@ -0,0 +1,179 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/.vivado.begin.rst index 892025e..b6c14df 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/.vivado.begin.rst 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zzeb;&hCg5+g*XQokm-NLIkhPm98#b5NBG?y=;QgK^jaoE|I}ZsBfL!eyb4?X$rDU? z<=Z1lb&~!Y5IADR_=Ib{yr&m`r_Mfm6aoWQ?!`OlhOQHZg&!*~eDD~hvJ`}#dn+Ek zLOw<761YOf%iQ-*a}K~n=a#mH!yV3jQBiES+h^Lc@Y&>1Gu4DCvb9$TlVM~+d@x@A z5O!Zj2m`j-%2qTKm;O7al=LZ_{cqt}o=E1ug=dX?V#S~^|MNgS=}eps>7T*>K4?xN zmk|B8M9oeD7fc^JsTYqlsY>F@zg+KM?(SdiQv&(xKc)-f`OEHq6Ia=P<=bER=llEa z9i%y668AsGN|G3`|9`1ll7l1$SR~%x396(TNrZpBc1z-dWl{b|`Cal~um6?(`j5|l zo92KYRR2*_kV5*`*hmT&Y+Cp)N0O8$h4+6P{^jgN{=?0PK+`J9fP#U5{O{ZRhC;g* zgTH%Z0{?%vj3D+uMoF5|XsnImARzQ0VyvpNw#?$H99~LR+QPO<^2*E-Tp}{I3_|u6 X*0v(@Mn)EjE<&u5lEO~14t)O~ZJw0Z diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.tcl b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.tcl index 6b0fa46..758f85e 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.tcl +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.tcl @@ -24,15 +24,15 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] -set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] +set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] +set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/Projects/IP [current_project] +set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project] update_ip_catalog -set_property ip_output_repo d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] +set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0.xci +read_ip -quiet D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0.xci # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1 -new_name AckChecker_AckCheckerConcept_0_0 -ip [get_ips AckChecker_AckCheckerConcept_0_0]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1 -new_name AckChecker_AckCheckerConcept_0_0 -ip [get_ips AckChecker_AckCheckerConcept_0_0]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_AckCheckerConcept_0_0.dcp create_report "AckChecker_AckCheckerConcept_0_0_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_AckCheckerConcept_0_0_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_0_0_utilization_synth.pb" if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.v + write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.vhdl + write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_sim_netlist.v + write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,47 +120,47 @@ if { [catch { if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_sim_netlist.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_0]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_0]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_0 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_0 } } -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_0]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_0]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_0 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_0 } } file delete __synthesis_is_running__ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.vds index b905be8..fddb456 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.vds @@ -2,44 +2,47 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:04:37 2020 -# Process ID: 6832 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1 +# Start of session at: Wed May 3 11:35:16 2023 +# Process ID: 2788 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_0_0.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_0_0.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. Command: synth_design -top AckChecker_AckCheckerConcept_0_0 -part xc7z020clg484-3 -mode out_of_context Starting synth_design +WARNING: [Vivado_Tcl 4-393] The 'Synthesis' target of the following IPs are stale, please generate the output products using the generate_target or synth_ip command before running synth_design. +D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0.xci + Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020' INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 19012 +INFO: Helper process launched with PID 11448 --------------------------------------------------------------------------------- -Starting Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 574.430 ; gain = 182.664 +Starting Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 575.355 ; gain = 181.930 --------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_0_0' [d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/synth/AckChecker_AckCheckerConcept_0_0.vhd:71] -INFO: [Synth 8-3491] module 'AckCheckerConcept' declared at 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/d6cf/AckCheckerConcept.vhd:27' bound to instance 'U0' of component 'AckCheckerConcept' [d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/synth/AckChecker_AckCheckerConcept_0_0.vhd:101] -INFO: [Synth 8-638] synthesizing module 'AckCheckerConcept' [d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/d6cf/AckCheckerConcept.vhd:44] -INFO: [Synth 8-256] done synthesizing module 'AckCheckerConcept' (1#1) [d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/d6cf/AckCheckerConcept.vhd:44] -INFO: [Synth 8-256] done synthesizing module 'AckChecker_AckCheckerConcept_0_0' (2#1) [d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/synth/AckChecker_AckCheckerConcept_0_0.vhd:71] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_0_0' [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/synth/AckChecker_AckCheckerConcept_0_0.vhd:71] +INFO: [Synth 8-3491] module 'AckCheckerConcept' declared at 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/d6cf/AckCheckerConcept.vhd:27' bound to instance 'U0' of component 'AckCheckerConcept' [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/synth/AckChecker_AckCheckerConcept_0_0.vhd:101] +INFO: [Synth 8-638] synthesizing module 'AckCheckerConcept' [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/d6cf/AckCheckerConcept.vhd:44] +INFO: [Synth 8-256] done synthesizing module 'AckCheckerConcept' (1#1) [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/d6cf/AckCheckerConcept.vhd:44] +INFO: [Synth 8-256] done synthesizing module 'AckChecker_AckCheckerConcept_0_0' (2#1) [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/synth/AckChecker_AckCheckerConcept_0_0.vhd:71] --------------------------------------------------------------------------------- -Finished Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 638.086 ; gain = 246.320 +Finished Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.984 ; gain = 246.559 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 638.086 ; gain = 246.320 +Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.984 ; gain = 246.559 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg484-3 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 638.086 ; gain = 246.320 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.984 ; gain = 246.559 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg484-3 INFO: [Synth 8-802] inferred FSM for state register 'acknowledge_reg' in module 'AckCheckerConcept' @@ -53,7 +56,7 @@ INFO: [Synth 8-802] inferred FSM for state register 'acknowledge_reg' in module --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'acknowledge_reg' using encoding 'sequential' in module 'AckCheckerConcept' --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 638.086 ; gain = 246.320 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.984 ; gain = 246.559 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -117,7 +120,7 @@ Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 803.441 ; gain = 411.676 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 806.207 ; gain = 412.781 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -130,7 +133,7 @@ No constraint files found. Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 806.750 ; gain = 414.984 +Finished Timing Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 809.129 ; gain = 415.703 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -142,7 +145,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 806.930 ; gain = 415.164 +Finished Technology Mapping : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 809.309 ; gain = 415.883 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -166,7 +169,7 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 806.930 ; gain = 415.164 +Finished IO Insertion : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883 --------------------------------------------------------------------------------- Report Check Netlist: @@ -179,7 +182,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 806.930 ; gain = 415.164 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -191,25 +194,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 806.930 ; gain = 415.164 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 806.930 ; gain = 415.164 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 806.930 ; gain = 415.164 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 806.930 ; gain = 415.164 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -243,35 +246,35 @@ Report Instance Areas: |2 | U0 |AckCheckerConcept | 69| +------+---------+------------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 806.930 ; gain = 415.164 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 806.930 ; gain = 415.164 -Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 806.930 ; gain = 415.164 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883 +Synthesis Optimization Complete : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 924.840 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 928.266 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis -19 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +19 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 924.840 ; gain = 538.379 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 924.840 ; gain = 0.000 +synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 928.266 ; gain = 541.242 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 928.266 ; gain = 0.000 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Common 17-1381] The checkpoint 'D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.dcp' has been generated. -write_checkpoint: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1360.527 ; gain = 435.688 +INFO: [Common 17-1381] The checkpoint 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1366.223 ; gain = 437.957 WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP AckChecker_AckCheckerConcept_0_0, cache-ID = 75535be1b50c31fe -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1361.664 ; gain = 0.000 +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP AckChecker_AckCheckerConcept_0_0, cache-ID = 9fc500b6c8c4592a +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1367.215 ; gain = 0.000 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.dcp' has been generated. +INFO: [Common 17-1381] The checkpoint 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file AckChecker_AckCheckerConcept_0_0_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_0_0_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:05:08 2020... +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:35:55 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0_utilization_synth.rpt b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0_utilization_synth.rpt index c37db2d..ef62aeb 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0_utilization_synth.rpt +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0_utilization_synth.rpt @@ -1,8 +1,8 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 -| Date : Wed Apr 29 14:05:08 2020 -| Host : Stas running 64-bit major release (build 9200) +| Date : Wed May 3 11:35:55 2023 +| Host : STAS-W10 running 64-bit major release (build 9200) | Command : report_utilization -file AckChecker_AckCheckerConcept_0_0_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_0_0_utilization_synth.pb | Design : AckChecker_AckCheckerConcept_0_0 | Device : 7z020clg484-3 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/gen_run.xml index 25c2548..b495b86 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/gen_run.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/project.wdf deleted file mode 100644 index 1c85d85..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/runme.log similarity index 60% rename from LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/runme.log rename to LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/runme.log index 3f92930..a5748ba 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/runme.log +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/runme.log @@ -1,6 +1,6 @@ *** Running vivado - with args -log Inverter_3lvl_P0N_3lvl_0_4.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_4.tcl + with args -log AckChecker_AckCheckerConcept_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_0_0.tcl ****** Vivado v2019.1 (64-bit) @@ -8,57 +8,54 @@ **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -source Inverter_3lvl_P0N_3lvl_0_4.tcl -notrace +source AckChecker_AckCheckerConcept_0_0.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/UPzynq20_test/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/UPzynq20_test/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -Command: synth_design -top Inverter_3lvl_P0N_3lvl_0_4 -part xc7z020clg484-3 -mode out_of_context +Command: synth_design -top AckChecker_AckCheckerConcept_0_0 -part xc7z020clg484-3 -mode out_of_context Starting synth_design +WARNING: [Vivado_Tcl 4-393] The 'Synthesis' target of the following IPs are stale, please generate the output products using the generate_target or synth_ip command before running synth_design. +D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0.xci + Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020' INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 7672 +INFO: Helper process launched with PID 11448 --------------------------------------------------------------------------------- -Starting Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 575.129 ; gain = 182.785 +Starting Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 575.355 ; gain = 181.930 --------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_4' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/synth/Inverter_3lvl_P0N_3lvl_0_4.vhd:76] -INFO: [Synth 8-3491] module 'P0N_3lvl' declared at 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:36' bound to instance 'U0' of component 'P0N_3lvl' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/synth/Inverter_3lvl_P0N_3lvl_0_4.vhd:109] -INFO: [Synth 8-638] synthesizing module 'P0N_3lvl' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:61] -WARNING: [Synth 8-6014] Unused sequential element TKin0_prev_reg was removed. [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:154] -WARNING: [Synth 8-6014] Unused sequential element TKin1_prev_reg was removed. [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:155] -INFO: [Synth 8-256] done synthesizing module 'P0N_3lvl' (1#1) [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:61] -INFO: [Synth 8-256] done synthesizing module 'Inverter_3lvl_P0N_3lvl_0_4' (2#1) [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/synth/Inverter_3lvl_P0N_3lvl_0_4.vhd:76] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_0_0' [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/synth/AckChecker_AckCheckerConcept_0_0.vhd:71] +INFO: [Synth 8-3491] module 'AckCheckerConcept' declared at 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/d6cf/AckCheckerConcept.vhd:27' bound to instance 'U0' of component 'AckCheckerConcept' [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/synth/AckChecker_AckCheckerConcept_0_0.vhd:101] +INFO: [Synth 8-638] synthesizing module 'AckCheckerConcept' [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/d6cf/AckCheckerConcept.vhd:44] +INFO: [Synth 8-256] done synthesizing module 'AckCheckerConcept' (1#1) [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/d6cf/AckCheckerConcept.vhd:44] +INFO: [Synth 8-256] done synthesizing module 'AckChecker_AckCheckerConcept_0_0' (2#1) [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/synth/AckChecker_AckCheckerConcept_0_0.vhd:71] --------------------------------------------------------------------------------- -Finished Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.793 ; gain = 247.449 +Finished Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.984 ; gain = 246.559 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 639.793 ; gain = 247.449 +Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.984 ; gain = 246.559 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg484-3 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 639.793 ; gain = 247.449 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.984 ; gain = 246.559 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg484-3 -INFO: [Synth 8-4471] merging register 'minTimeEr_sig_reg' into 'minTimeEr_reg' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:98] -INFO: [Synth 8-802] inferred FSM for state register 'lineconfig_reg' in module 'P0N_3lvl' +INFO: [Synth 8-802] inferred FSM for state register 'acknowledge_reg' in module 'AckCheckerConcept' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- - closed | 0000001 | 000 - n | 0000010 | 110 - tech_closed | 0000100 | 001 - p | 0001000 | 101 - zero_p | 0010000 | 011 - zero | 0100000 | 010 - zero_n | 1000000 | 100 + waiting | 00 | 00 + check | 01 | 01 + waiting_strobe_end | 10 | 10 + iSTATE | 11 | 11 --------------------------------------------------------------------------------------------------- -INFO: [Synth 8-3354] encoded FSM with state register 'lineconfig_reg' using encoding 'one-hot' in module 'P0N_3lvl' +INFO: [Synth 8-3354] encoded FSM with state register 'acknowledge_reg' using encoding 'sequential' in module 'AckCheckerConcept' --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 639.793 ; gain = 247.449 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.984 ; gain = 246.559 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -71,13 +68,18 @@ No constraint files found. Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : ++---Adders : + 2 Input 8 Bit Adders := 1 +---Registers : - 1 Bit Registers := 19 + 8 Bit Registers := 1 + 1 Bit Registers := 3 +---Muxes : - 7 Input 7 Bit Muxes := 1 - 2 Input 7 Bit Muxes := 16 - 2 Input 1 Bit Muxes := 47 - 7 Input 1 Bit Muxes := 10 + 2 Input 8 Bit Muxes := 3 + 4 Input 8 Bit Muxes := 1 + 3 Input 2 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 3 + 2 Input 1 Bit Muxes := 2 + 4 Input 1 Bit Muxes := 5 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- @@ -85,15 +87,20 @@ Finished RTL Component Statistics Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report -Module P0N_3lvl +Module AckCheckerConcept Detailed RTL Component Info : ++---Adders : + 2 Input 8 Bit Adders := 1 +---Registers : - 1 Bit Registers := 19 + 8 Bit Registers := 1 + 1 Bit Registers := 3 +---Muxes : - 7 Input 7 Bit Muxes := 1 - 2 Input 7 Bit Muxes := 16 - 2 Input 1 Bit Muxes := 47 - 7 Input 1 Bit Muxes := 10 + 2 Input 8 Bit Muxes := 3 + 4 Input 8 Bit Muxes := 1 + 3 Input 2 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 3 + 2 Input 1 Bit Muxes := 2 + 4 Input 1 Bit Muxes := 5 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- @@ -112,7 +119,7 @@ Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 806.691 ; gain = 414.348 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 806.207 ; gain = 412.781 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -125,7 +132,7 @@ No constraint files found. Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 813.012 ; gain = 420.668 +Finished Timing Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 809.129 ; gain = 415.703 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -137,7 +144,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 813.207 ; gain = 420.863 +Finished Technology Mapping : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 809.309 ; gain = 415.883 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -161,7 +168,7 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 813.207 ; gain = 420.863 +Finished IO Insertion : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883 --------------------------------------------------------------------------------- Report Check Netlist: @@ -174,7 +181,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 813.207 ; gain = 420.863 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -186,25 +193,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 813.207 ; gain = 420.863 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 813.207 ; gain = 420.863 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 813.207 ; gain = 420.863 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 813.207 ; gain = 420.863 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -220,54 +227,53 @@ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ -|1 |CARRY4 | 36| -|2 |LUT1 | 4| -|3 |LUT2 | 7| -|4 |LUT3 | 4| -|5 |LUT4 | 108| -|6 |LUT5 | 7| -|7 |LUT6 | 23| -|8 |FDRE | 121| -|9 |FDSE | 1| +|1 |CARRY4 | 4| +|2 |LUT1 | 1| +|3 |LUT2 | 25| +|4 |LUT3 | 5| +|5 |LUT4 | 11| +|6 |LUT5 | 6| +|7 |LUT6 | 4| +|8 |FDRE | 13| +------+-------+------+ Report Instance Areas: -+------+---------+---------+------+ -| |Instance |Module |Cells | -+------+---------+---------+------+ -|1 |top | | 311| -|2 | U0 |P0N_3lvl | 311| -+------+---------+---------+------+ ++------+---------+------------------+------+ +| |Instance |Module |Cells | ++------+---------+------------------+------+ +|1 |top | | 69| +|2 | U0 |AckCheckerConcept | 69| ++------+---------+------------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 813.207 ; gain = 420.863 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 813.207 ; gain = 420.863 -Synthesis Optimization Complete : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 813.207 ; gain = 420.863 +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883 +Synthesis Optimization Complete : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 809.309 ; gain = 415.883 INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 36 Unisim elements for replacement +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 930.840 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 928.266 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis -20 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. +19 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 930.840 ; gain = 543.824 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 930.840 ; gain = 0.000 +synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 928.266 ; gain = 541.242 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 928.266 ; gain = 0.000 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Common 17-1381] The checkpoint 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/Inverter_3lvl_P0N_3lvl_0_4.dcp' has been generated. -write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1388.254 ; gain = 457.414 +INFO: [Common 17-1381] The checkpoint 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1366.223 ; gain = 437.957 WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP Inverter_3lvl_P0N_3lvl_0_4, cache-ID = fdc8b3b6ee8afc45 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1389.293 ; gain = 0.000 +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP AckChecker_AckCheckerConcept_0_0, cache-ID = 9fc500b6c8c4592a +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1367.215 ; gain = 0.000 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/Inverter_3lvl_P0N_3lvl_0_4.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file Inverter_3lvl_P0N_3lvl_0_4_utilization_synth.rpt -pb Inverter_3lvl_P0N_3lvl_0_4_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Fri Jun 11 07:49:58 2021... +INFO: [Common 17-1381] The checkpoint 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file AckChecker_AckCheckerConcept_0_0_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_0_0_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:35:55 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/runme.sh index d34b3b4..92047b9 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/vivado.jou index ece7bfd..772a82e 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:04:37 2020 -# Process ID: 6832 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1 +# Start of session at: Wed May 3 11:35:16 2023 +# Process ID: 2788 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_0_0.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/AckChecker_AckCheckerConcept_0_0.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_0_0.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_0_synth_1/vivado.pb index aa8c1768099ed072402813e53a2090dddcf79aed..2730e2880597d69150ae96a3d65a432d28cd58db 100644 GIT binary patch delta 1786 zcmb7_-EY%o6vlazCZTT_MXgH);+bRs+2;A*Htz{QZDdoPEC#08gpR6@I?nz%p$%D;f!6$(ge&4q2f*6%#$Igh2| z=g-mASLot5XuO@1K2PI;QZ~J3_(1;a^d8ImwpC2$N7KWFF~ez^F3dH1+rM{5E=Svc z&920@anImcgzL-c6%r}9UEe{IkqhYb)hM1u2dX9+O1VSC)0-93BTkuk{;RT6t2rkv zyF!KwF43DNaXr0eenlEJQ+G{LF>SM{d*%Y{w7f>kBaNn0Y8jqOT5eDn$h^hI-l{i= zJ865>F{?o|!>QMGyF`j+*&miPTecn4{Rfmx*Q(eoPPyyi8>76!ZSNen#`Tip88zs# z2Db=*BYYj@mI<$r$iepb7qCCRB|2ePFvIkGb|fb45H+#7su7=v({}U}f*;oQ!q(Wv z^)f5UGTBKgx@D7Hgjac16FJy-c(CJf1os2+ub*Riau4A@(efb&ecR|6+=-tfzao5Q z1^i)HO&$JOEp%L3a?=HUi6L@nLO z=itej0#e{amhtZeyRTmnHC9ulrF;cRVP#qK^PPs|+P$G*y6^B-MDKPbBBAg=o8Iis zCc@M6d?o_9kqvay<`+G1t0*u6msv6`@dBGs`32#5{z23yxb+)=gP%w{-ok@4l` z`EL4BJ&zV)k^2Z%)g_ot?fN&4M3^ZuNLmO^Z9Za!oRGr-BR>+J%JD(G=kSZ;^3Lwgje&TqOgJ>1_lEIl9*vNIRm?^UsBcK&^oPb z$Q)Nx4AqciP0(SkyBDS!bFmC7@bcnZr#``m|4*5u3AZ0HBl;vEBH{V0C};h3DsaA! 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z$+C}S7Dw31xkoN^hbW}3DzfcwhJOGEJpv`uDpYo=kuMaxC~<7ow*kk+c}gtT!W3$< zm8fCOIP9*;qbhp)R?`&f-s?VpqqNV-6fr3D^0F{F$`7D8zGQy3eZ1e$i{)=ANCSfa z0sTKdLjOKR{AU1vOQYXEGeKi(VT<^8F`9oH4{5}4Kx{GM5wS_)t;CW3<$S(55X^6m zG`>?D;a_h0n_I#9=4j)wB;W}DuU^G}T>sZ-^h?J6kHc$h@OT>uxPKjZN#KB#ko|{m zlR*5Bga2`y`QNL*vC*%B{6B{9lK-_kfg}z{o4_|m9Iq>h`(F;fIc>rJaEMZnNdNyR z#Ls-|UxfZkkHP=H-~aDWWP$?$LH^f<|3n7JH%H|AqkUrsdN*4e1!-`Ie>m9hD+m+_ Ks6gzWyZ;4l+Kh+* diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1.tcl b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1.tcl index f217c22..c839e42 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1.tcl +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1.tcl @@ -24,15 +24,15 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] -set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] +set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] +set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/Projects/IP [current_project] +set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project] update_ip_catalog -set_property ip_output_repo d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] +set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1.xci +read_ip -quiet D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1.xci # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1 -new_name AckChecker_AckCheckerConcept_0_1 -ip [get_ips AckChecker_AckCheckerConcept_0_1]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1 -new_name AckChecker_AckCheckerConcept_0_1 -ip [get_ips AckChecker_AckCheckerConcept_0_1]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_AckCheckerConcept_0_1.dcp create_report "AckChecker_AckCheckerConcept_0_1_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_AckCheckerConcept_0_1_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_0_1_utilization_synth.pb" if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.v + write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.vhdl + write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.v + write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,47 +120,47 @@ if { [catch { if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_1]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_1]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_1 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_1 } } -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_1]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_1]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_1 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_1 } } file delete __synthesis_is_running__ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1.vds index 531014c..2fb371f 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1.vds @@ -2,17 +2,17 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:11 2020 -# Process ID: 20660 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1 +# Start of session at: Wed May 3 11:35:58 2023 +# Process ID: 1000 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_0_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_0_1.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_0_1.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_0_1, cache-ID = 75535be1b50c31fe. -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:05:17 2020... +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_0_1, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:06 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/gen_run.xml index 93fc872..0cc7e29 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/gen_run.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/project.wdf deleted file mode 100644 index 1c85d85..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:95469607 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/runme.log new file mode 100644 index 0000000..de7e418 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_AckCheckerConcept_0_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_0_1.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_0_1.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_0_1, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:06 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/runme.sh index 4f2a800..944365d 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/vivado.jou index 7931be1..aa881f7 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:11 2020 -# Process ID: 20660 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1 +# Start of session at: Wed May 3 11:35:58 2023 +# Process ID: 1000 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_0_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_0_1.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/AckChecker_AckCheckerConcept_0_1.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_0_1.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_1_synth_1/vivado.pb index 6ac406bc0e7da667f5d891432a89ca97b99f9346..bc587491b56f98d5be87297fbd9208bb0af06437 100644 GIT binary patch delta 183 zcmZqYSkE!RnXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@x)GbrWwo= zH(d(Aug-`)B{eOvG^fN0#xQDRf}x3(fvJ_D Oxq^{_k-_9&%%%Vg>MYp+ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/.vivado.begin.rst index 9c715c9..6ef60d7 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/AckChecker_AckCheckerConcept_0_2.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/AckChecker_AckCheckerConcept_0_2.dcp index b8f6606fdfc6858fa76ae4e7b262564fae8e63f2..918e0337f524af8fffdb6e06a827f1a0272a3fcb 100644 GIT binary patch delta 16382 zcmZv@18`;A7B(8&w%M_5+qSJ8C!OqA9ot67HafQLbZonmPF~Kr_x<(XS8r8~Ip+HI zH^!W6RjsNyuzQn150gQ0l;yx7FhD>+U_gBJi!`yh@8Tt}KtO(+CiPNMCkVj+#}hwt zjSBV#hHJ)$efEcHs;dDYe4FP1$nh6ES>qZe@eT%NgK+jEzGv^xOVTjK2_06YkoJ>~ z6^S63x&FDixf!XYR&EE1U3!<_-)Fl#N01$V+Y563U0cmzBHWtWu~|o@d%1vupUJZ+ zEw%gOa(ABccA==XL%g|yEtJj=j6FJ^Sy(#U_mui^X#LvcRYuqiu?;w#P9L22b%UOm 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b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/AckChecker_AckCheckerConcept_0_2.tcl @@ -24,15 +24,15 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] -set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] +set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] +set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/Projects/IP [current_project] +set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project] update_ip_catalog -set_property ip_output_repo d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] +set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2.xci +read_ip -quiet D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2.xci # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1 -new_name AckChecker_AckCheckerConcept_0_2 -ip [get_ips AckChecker_AckCheckerConcept_0_2]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1 -new_name AckChecker_AckCheckerConcept_0_2 -ip [get_ips AckChecker_AckCheckerConcept_0_2]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_AckCheckerConcept_0_2.dcp create_report "AckChecker_AckCheckerConcept_0_2_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_AckCheckerConcept_0_2_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_0_2_utilization_synth.pb" if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/AckChecker_AckCheckerConcept_0_2.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/AckChecker_AckCheckerConcept_0_2.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_stub.v + write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_stub.vhdl + write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_sim_netlist.v + write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,47 +120,47 @@ if { [catch { if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/AckChecker_AckCheckerConcept_0_2.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/AckChecker_AckCheckerConcept_0_2.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/AckChecker_AckCheckerConcept_0_2_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_stub.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/AckChecker_AckCheckerConcept_0_2_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/AckChecker_AckCheckerConcept_0_2_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_stub.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/AckChecker_AckCheckerConcept_0_2_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/AckChecker_AckCheckerConcept_0_2_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_sim_netlist.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/AckChecker_AckCheckerConcept_0_2_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/AckChecker_AckCheckerConcept_0_2_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_sim_netlist.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/AckChecker_AckCheckerConcept_0_2_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_2]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_2]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_2 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_2 } } -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_2]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_2]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_2 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_2 } } file delete __synthesis_is_running__ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/AckChecker_AckCheckerConcept_0_2.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/AckChecker_AckCheckerConcept_0_2.vds index 6e9f7cf..c114465 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/AckChecker_AckCheckerConcept_0_2.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/AckChecker_AckCheckerConcept_0_2.vds @@ -2,17 +2,17 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:11 2020 -# Process ID: 10624 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1 +# Start of session at: Wed May 3 11:35:58 2023 +# Process ID: 6912 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_0_2.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_0_2.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/AckChecker_AckCheckerConcept_0_2.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/AckChecker_AckCheckerConcept_0_2.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_0_2.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_0_2, cache-ID = 75535be1b50c31fe. -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:05:18 2020... +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_0_2, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:06 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/gen_run.xml index 57573b7..4f755af 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/gen_run.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/project.wdf deleted file mode 100644 index 1c85d85..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 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AckChecker_AckCheckerConcept_0_2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_0_2.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_0_2.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_0_2, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:06 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/runme.sh index 869591e..e932d40 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/vivado.jou index 7705a77..43be974 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:11 2020 -# Process ID: 10624 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1 +# Start of session at: Wed May 3 11:35:58 2023 +# Process ID: 6912 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_0_2.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_0_2.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/AckChecker_AckCheckerConcept_0_2.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/AckChecker_AckCheckerConcept_0_2.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_0_2.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_2_synth_1/vivado.pb index 96330d049e121f8598037c8924d3983dfc603229..3f1f21fabddd0570f1c0668563e66779235c0a20 100644 GIT binary patch delta 183 zcmZqYSkE!RnXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@x)GbrWwo= zH(d(Aug-`)B{eOvG^fN0#xQDRf}x3(fvJ_D Og@TcRk-_9&%%%Vg^eox{ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/.vivado.begin.rst index 5e8ef50..5ed62b0 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/AckChecker_AckCheckerConcept_0_3.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/AckChecker_AckCheckerConcept_0_3.dcp index 52629b5466ea10927b19376708f2c52167996a98..5ba13ccc866c9d05ec17e5287f20d9f1204b7345 100644 GIT binary patch delta 16422 zcmZvDb980T)@^Ltwr$(CZ5y4O*tU(1?WAMdPCB;TNhdGAd++zgyWe;<#;R3&p1Ee# z`D2e!Rcr0u6yU=YU@RqBP%tzgARs6pU%g@tOs@L`aSR}!=(FTLa>_(OD8NM0XP#l< z{@_UM#E8$qaBWSE3lQ(tMF3*LC3p6Ox^aTNzUdH*-Kg*R$IG%5R7ql|Wf{2LltX0_ zP*$FQUS3{iTA8KWp+dLr)sK(4ZqHFfhu?Mr9Dmo>avAZr=Xb3)kZE5pAz)|ot;@=6 z|2W@Yq`qG&Xzmhjtzrsh@B!kEFJ>2)j}AN~qmQiKn!U>Ld%$*F&So-(7JS_xC+83J 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Any black boxes in the @@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1 -new_name AckChecker_BusBlock16OUT_0_0 -ip [get_ips AckChecker_BusBlock16OUT_0_0]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1 -new_name AckChecker_BusBlock16OUT_0_0 -ip [get_ips AckChecker_BusBlock16OUT_0_0]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_BusBlock16OUT_0_0.dcp create_report "AckChecker_BusBlock16OUT_0_0_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_BusBlock16OUT_0_0_utilization_synth.rpt -pb AckChecker_BusBlock16OUT_0_0_utilization_synth.pb" if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_stub.v + write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_stub.vhdl + write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_sim_netlist.v + write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,47 +120,47 @@ if { [catch { if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_stub.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_stub.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_sim_netlist.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_sim_netlist.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_0_0]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_0_0]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_0_0 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_0_0 } } -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_0_0]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_0_0]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_0_0 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_0_0 } } file delete __synthesis_is_running__ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0.vds index 3005c19..adee879 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0.vds @@ -2,48 +2,51 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:04:37 2020 -# Process ID: 8508 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1 +# Start of session at: Wed May 3 11:35:16 2023 +# Process ID: 15488 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1 # Command line: vivado.exe -log AckChecker_BusBlock16OUT_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16OUT_0_0.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_BusBlock16OUT_0_0.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. Command: synth_design -top AckChecker_BusBlock16OUT_0_0 -part xc7z020clg484-3 -mode out_of_context Starting synth_design +WARNING: [Vivado_Tcl 4-393] The 'Synthesis' target of the following IPs are stale, please generate the output products using the generate_target or synth_ip command before running synth_design. +D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0.xci + Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020' INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 14452 +INFO: Helper process launched with PID 8416 --------------------------------------------------------------------------------- -Starting Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 574.457 ; gain = 181.605 +Starting Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 576.051 ; gain = 182.172 --------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'AckChecker_BusBlock16OUT_0_0' [d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/synth/AckChecker_BusBlock16OUT_0_0.vhd:79] -INFO: [Synth 8-3491] module 'BusBlock16OUT' declared at 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/dbb3/BusBlock16OUT.vhd:34' bound to instance 'U0' of component 'BusBlock16OUT' [d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/synth/AckChecker_BusBlock16OUT_0_0.vhd:111] -INFO: [Synth 8-638] synthesizing module 'BusBlock16OUT' [d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/dbb3/BusBlock16OUT.vhd:55] -INFO: [Synth 8-256] done synthesizing module 'BusBlock16OUT' (1#1) [d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/dbb3/BusBlock16OUT.vhd:55] -INFO: [Synth 8-256] done synthesizing module 'AckChecker_BusBlock16OUT_0_0' (2#1) [d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/synth/AckChecker_BusBlock16OUT_0_0.vhd:79] +INFO: [Synth 8-638] synthesizing module 'AckChecker_BusBlock16OUT_0_0' [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/synth/AckChecker_BusBlock16OUT_0_0.vhd:79] +INFO: [Synth 8-3491] module 'BusBlock16OUT' declared at 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/dbb3/BusBlock16OUT.vhd:34' bound to instance 'U0' of component 'BusBlock16OUT' [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/synth/AckChecker_BusBlock16OUT_0_0.vhd:111] +INFO: [Synth 8-638] synthesizing module 'BusBlock16OUT' [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/dbb3/BusBlock16OUT.vhd:55] +INFO: [Synth 8-256] done synthesizing module 'BusBlock16OUT' (1#1) [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/dbb3/BusBlock16OUT.vhd:55] +INFO: [Synth 8-256] done synthesizing module 'AckChecker_BusBlock16OUT_0_0' (2#1) [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/synth/AckChecker_BusBlock16OUT_0_0.vhd:79] --------------------------------------------------------------------------------- -Finished Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 638.773 ; gain = 245.922 +Finished Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 640.426 ; gain = 246.547 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 638.773 ; gain = 245.922 +Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 640.426 ; gain = 246.547 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg484-3 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 638.773 ; gain = 245.922 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 640.426 ; gain = 246.547 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg484-3 --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 638.773 ; gain = 245.922 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 640.426 ; gain = 246.547 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -81,7 +84,7 @@ Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 804.895 ; gain = 412.043 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 806.660 ; gain = 412.781 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -94,7 +97,7 @@ No constraint files found. Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 804.895 ; gain = 412.043 +Finished Timing Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 807.594 ; gain = 413.715 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -106,7 +109,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 804.895 ; gain = 412.043 +Finished Technology Mapping : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 807.594 ; gain = 413.715 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -130,7 +133,7 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 807.813 ; gain = 414.961 +Finished IO Insertion : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 808.586 ; gain = 414.707 --------------------------------------------------------------------------------- Report Check Netlist: @@ -143,7 +146,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 807.813 ; gain = 414.961 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 808.586 ; gain = 414.707 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -155,25 +158,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 807.813 ; gain = 414.961 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 808.586 ; gain = 414.707 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 807.813 ; gain = 414.961 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 808.586 ; gain = 414.707 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 807.813 ; gain = 414.961 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 808.586 ; gain = 414.707 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 807.813 ; gain = 414.961 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 808.586 ; gain = 414.707 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -200,33 +203,33 @@ Report Instance Areas: |2 | U0 |BusBlock16OUT | 16| +------+---------+--------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 807.813 ; gain = 414.961 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 808.586 ; gain = 414.707 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 807.813 ; gain = 414.961 -Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 807.813 ; gain = 414.961 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 808.586 ; gain = 414.707 +Synthesis Optimization Complete : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 808.586 ; gain = 414.707 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 925.656 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 928.453 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis -15 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +15 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 925.656 ; gain = 539.355 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 925.656 ; gain = 0.000 +synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 928.453 ; gain = 538.527 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 928.453 ; gain = 0.000 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Common 17-1381] The checkpoint 'D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0.dcp' has been generated. -write_checkpoint: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1339.965 ; gain = 414.309 +INFO: [Common 17-1381] The checkpoint 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1344.508 ; gain = 416.055 WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP AckChecker_BusBlock16OUT_0_0, cache-ID = 6bbc64a1eef077bd -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1340.949 ; gain = 0.000 +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP AckChecker_BusBlock16OUT_0_0, cache-ID = 620c0a6afb1e6b3a +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1345.523 ; gain = 0.000 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0.dcp' has been generated. +INFO: [Common 17-1381] The checkpoint 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file AckChecker_BusBlock16OUT_0_0_utilization_synth.rpt -pb AckChecker_BusBlock16OUT_0_0_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:05:08 2020... +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:35:54 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0_utilization_synth.rpt b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0_utilization_synth.rpt index 1371e8b..46c3897 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0_utilization_synth.rpt +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0_utilization_synth.rpt @@ -1,8 +1,8 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 -| Date : Wed Apr 29 14:05:08 2020 -| Host : Stas running 64-bit major release (build 9200) +| Date : Wed May 3 11:35:54 2023 +| Host : STAS-W10 running 64-bit major release (build 9200) | Command : report_utilization -file AckChecker_BusBlock16OUT_0_0_utilization_synth.rpt -pb AckChecker_BusBlock16OUT_0_0_utilization_synth.pb | Design : AckChecker_BusBlock16OUT_0_0 | Device : 7z020clg484-3 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/gen_run.xml index 56a2915..2664d87 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/gen_run.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/project.wdf deleted file mode 100644 index 1c85d85..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:95469607 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/Inverter_3lvl_BUS_16IN_0_0.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/runme.log similarity index 68% rename from LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/Inverter_3lvl_BUS_16IN_0_0.vds rename to LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/runme.log index b1324a7..05af257 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/Inverter_3lvl_BUS_16IN_0_0.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/runme.log @@ -1,49 +1,51 @@ -#----------------------------------------------------------- -# Vivado v2019.1 (64-bit) -# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 -# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Fri Jun 11 07:49:21 2021 -# Process ID: 7204 -# Current directory: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1 -# Command line: vivado.exe -log Inverter_3lvl_BUS_16IN_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_BUS_16IN_0_0.tcl -# Log file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/Inverter_3lvl_BUS_16IN_0_0.vds -# Journal file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1\vivado.jou -#----------------------------------------------------------- -source Inverter_3lvl_BUS_16IN_0_0.tcl -notrace + +*** Running vivado + with args -log AckChecker_BusBlock16OUT_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16OUT_0_0.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_BusBlock16OUT_0_0.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/UPzynq20_test/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/UPzynq20_test/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -Command: synth_design -top Inverter_3lvl_BUS_16IN_0_0 -part xc7z020clg484-3 -mode out_of_context +Command: synth_design -top AckChecker_BusBlock16OUT_0_0 -part xc7z020clg484-3 -mode out_of_context Starting synth_design +WARNING: [Vivado_Tcl 4-393] The 'Synthesis' target of the following IPs are stale, please generate the output products using the generate_target or synth_ip command before running synth_design. +D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0.xci + Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020' INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 12572 +INFO: Helper process launched with PID 8416 --------------------------------------------------------------------------------- -Starting Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 573.934 ; gain = 182.871 +Starting Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 576.051 ; gain = 182.172 --------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_BUS_16IN_0_0' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_0_0/synth/Inverter_3lvl_BUS_16IN_0_0.vhd:78] -INFO: [Synth 8-3491] module 'BUS_16IN' declared at 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/f296/BUS_16IN.vhd:36' bound to instance 'U0' of component 'BUS_16IN' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_0_0/synth/Inverter_3lvl_BUS_16IN_0_0.vhd:109] -INFO: [Synth 8-638] synthesizing module 'BUS_16IN' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/f296/BUS_16IN.vhd:60] -INFO: [Synth 8-256] done synthesizing module 'BUS_16IN' (1#1) [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/f296/BUS_16IN.vhd:60] -INFO: [Synth 8-256] done synthesizing module 'Inverter_3lvl_BUS_16IN_0_0' (2#1) [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_0_0/synth/Inverter_3lvl_BUS_16IN_0_0.vhd:78] +INFO: [Synth 8-638] synthesizing module 'AckChecker_BusBlock16OUT_0_0' [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/synth/AckChecker_BusBlock16OUT_0_0.vhd:79] +INFO: [Synth 8-3491] module 'BusBlock16OUT' declared at 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/dbb3/BusBlock16OUT.vhd:34' bound to instance 'U0' of component 'BusBlock16OUT' [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/synth/AckChecker_BusBlock16OUT_0_0.vhd:111] +INFO: [Synth 8-638] synthesizing module 'BusBlock16OUT' [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/dbb3/BusBlock16OUT.vhd:55] +INFO: [Synth 8-256] done synthesizing module 'BusBlock16OUT' (1#1) [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/dbb3/BusBlock16OUT.vhd:55] +INFO: [Synth 8-256] done synthesizing module 'AckChecker_BusBlock16OUT_0_0' (2#1) [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/synth/AckChecker_BusBlock16OUT_0_0.vhd:79] --------------------------------------------------------------------------------- -Finished Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 637.832 ; gain = 246.770 +Finished Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 640.426 ; gain = 246.547 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 637.832 ; gain = 246.770 +Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 640.426 ; gain = 246.547 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg484-3 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 637.832 ; gain = 246.770 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 640.426 ; gain = 246.547 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg484-3 --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 637.832 ; gain = 246.770 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 640.426 ; gain = 246.547 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -80,9 +82,8 @@ No constraint files found. Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met -WARNING: [Synth 8-3330] design Inverter_3lvl_BUS_16IN_0_0 has an empty top module --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 794.504 ; gain = 403.441 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 806.660 ; gain = 412.781 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -95,7 +96,7 @@ No constraint files found. Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 794.504 ; gain = 403.441 +Finished Timing Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 807.594 ; gain = 413.715 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -107,7 +108,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 794.504 ; gain = 403.441 +Finished Technology Mapping : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 807.594 ; gain = 413.715 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -131,7 +132,7 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 794.504 ; gain = 403.441 +Finished IO Insertion : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 808.586 ; gain = 414.707 --------------------------------------------------------------------------------- Report Check Netlist: @@ -144,7 +145,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 794.504 ; gain = 403.441 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 808.586 ; gain = 414.707 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -156,25 +157,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 794.504 ; gain = 403.441 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 808.586 ; gain = 414.707 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 794.504 ; gain = 403.441 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 808.586 ; gain = 414.707 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 794.504 ; gain = 403.441 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 808.586 ; gain = 414.707 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 794.504 ; gain = 403.441 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 808.586 ; gain = 414.707 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -187,45 +188,47 @@ Report BlackBoxes: +-+--------------+----------+ Report Cell Usage: -+-+-----+------+ -| |Cell |Count | -+-+-----+------+ -+-+-----+------+ ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |LUT2 | 16| ++------+-----+------+ Report Instance Areas: -+------+---------+-------+------+ -| |Instance |Module |Cells | -+------+---------+-------+------+ -|1 |top | | 0| -+------+---------+-------+------+ ++------+---------+--------------+------+ +| |Instance |Module |Cells | ++------+---------+--------------+------+ +|1 |top | | 16| +|2 | U0 |BusBlock16OUT | 16| ++------+---------+--------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 794.504 ; gain = 403.441 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 808.586 ; gain = 414.707 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 794.504 ; gain = 403.441 -Synthesis Optimization Complete : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 794.504 ; gain = 403.441 +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 808.586 ; gain = 414.707 +Synthesis Optimization Complete : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 808.586 ; gain = 414.707 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 905.922 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 928.453 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 15 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 905.922 ; gain = 520.039 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 905.922 ; gain = 0.000 +synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 928.453 ; gain = 538.527 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 928.453 ; gain = 0.000 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Common 17-1381] The checkpoint 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/Inverter_3lvl_BUS_16IN_0_0.dcp' has been generated. -write_checkpoint: Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1292.023 ; gain = 386.102 +INFO: [Common 17-1381] The checkpoint 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1344.508 ; gain = 416.055 WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP Inverter_3lvl_BUS_16IN_0_0, cache-ID = 70127aa8275ccbbd -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1293.289 ; gain = 0.000 +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP AckChecker_BusBlock16OUT_0_0, cache-ID = 620c0a6afb1e6b3a +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1345.523 ; gain = 0.000 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/Inverter_3lvl_BUS_16IN_0_0.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file Inverter_3lvl_BUS_16IN_0_0_utilization_synth.rpt -pb Inverter_3lvl_BUS_16IN_0_0_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Fri Jun 11 07:49:57 2021... +INFO: [Common 17-1381] The checkpoint 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file AckChecker_BusBlock16OUT_0_0_utilization_synth.rpt -pb AckChecker_BusBlock16OUT_0_0_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:35:54 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/runme.sh index 3b5dae6..bc0cf5b 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/vivado.jou index 61b5b70..ce5149b 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:04:37 2020 -# Process ID: 8508 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1 +# Start of session at: Wed May 3 11:35:16 2023 +# Process ID: 15488 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1 # Command line: vivado.exe -log AckChecker_BusBlock16OUT_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16OUT_0_0.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_BusBlock16OUT_0_0.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/vivado.pb index 965ca9813ac07d28f35caecaed489f68d3a1d40b..8b071857719323fa37f3e3e120768f70ebe01473 100644 GIT binary patch delta 1803 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zJ1WQMM{|ENRfYRXe1Z7p=S@!WEz>r$L~CX|=2l((OV{_j&Uu`2==>PYOuLB*tK_$Q z=69qHsBE^yRalfo;4i0sa>;;W&)uNyNKJ?1v%9Q($Gpkya(dX!LcvBhL(FC}j9C8p zO5Da+7sl6;-$h#+tQ{jc9EL=3?OE5&p5t=CBEh zwtnPk1>fXSl`+k-^~m5+^b|hQBx#~NCMvCe$XoP3VAg#6#3U~{ak`Z>bsA6=ZMpY8 zdYnJOqoIt13f81cT!JW!UtD;QzfLLp1pRGa3Sg@&6k2=?VT7+tX7byHX$+U1AYE<=^6U z$AC6xBoJr<@z9L_DMTzm4S^(-2qQDc|9l^f=u%x9gkuo}1Y-Gb1-*&93__Cs?{h|Y pNYFqajQ`IA3UHaCPZ|MH4{tH@k{Fwj% diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/AckChecker_BusBlock16OUT_0_1.tcl b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/AckChecker_BusBlock16OUT_0_1.tcl index 628167c..9c7da6a 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/AckChecker_BusBlock16OUT_0_1.tcl +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/AckChecker_BusBlock16OUT_0_1.tcl @@ -24,15 +24,15 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] -set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] +set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] +set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/Projects/IP [current_project] +set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project] update_ip_catalog -set_property ip_output_repo d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] +set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1.xci +read_ip -quiet D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1.xci # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1 -new_name AckChecker_BusBlock16OUT_0_1 -ip [get_ips AckChecker_BusBlock16OUT_0_1]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1 -new_name AckChecker_BusBlock16OUT_0_1 -ip [get_ips AckChecker_BusBlock16OUT_0_1]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_BusBlock16OUT_0_1.dcp create_report "AckChecker_BusBlock16OUT_0_1_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_BusBlock16OUT_0_1_utilization_synth.rpt -pb AckChecker_BusBlock16OUT_0_1_utilization_synth.pb" if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/AckChecker_BusBlock16OUT_0_1.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/AckChecker_BusBlock16OUT_0_1.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_stub.v + write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_stub.vhdl + write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_sim_netlist.v + write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,47 +120,47 @@ if { [catch { if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/AckChecker_BusBlock16OUT_0_1.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/AckChecker_BusBlock16OUT_0_1.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/AckChecker_BusBlock16OUT_0_1_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_stub.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/AckChecker_BusBlock16OUT_0_1_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/AckChecker_BusBlock16OUT_0_1_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_stub.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/AckChecker_BusBlock16OUT_0_1_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/AckChecker_BusBlock16OUT_0_1_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_sim_netlist.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/AckChecker_BusBlock16OUT_0_1_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/AckChecker_BusBlock16OUT_0_1_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_sim_netlist.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/AckChecker_BusBlock16OUT_0_1_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_0_1]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_0_1]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_0_1 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_0_1 } } -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_0_1]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_0_1]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_0_1 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_0_1 } } file delete __synthesis_is_running__ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/AckChecker_BusBlock16OUT_0_1.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/AckChecker_BusBlock16OUT_0_1.vds index 1a35de7..8e64fe3 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/AckChecker_BusBlock16OUT_0_1.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/AckChecker_BusBlock16OUT_0_1.vds @@ -2,17 +2,17 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:06:00 2020 -# Process ID: 16060 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1 +# Start of session at: Wed May 3 11:36:39 2023 +# Process ID: 12568 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1 # Command line: vivado.exe -log AckChecker_BusBlock16OUT_0_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16OUT_0_1.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/AckChecker_BusBlock16OUT_0_1.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/AckChecker_BusBlock16OUT_0_1.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_BusBlock16OUT_0_1.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_BusBlock16OUT_0_1, cache-ID = 6bbc64a1eef077bd. -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:06:08 2020... +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_BusBlock16OUT_0_1, cache-ID = 620c0a6afb1e6b3a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:46 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/gen_run.xml index 31ee592..1573ec3 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/gen_run.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/project.wdf deleted file mode 100644 index 1c85d85..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:95469607 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/runme.log new file mode 100644 index 0000000..a6ffeee --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_BusBlock16OUT_0_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16OUT_0_1.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_BusBlock16OUT_0_1.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_BusBlock16OUT_0_1, cache-ID = 620c0a6afb1e6b3a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:46 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/runme.sh index b89f421..a1f99de 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/vivado.jou index a66c95e..20620e4 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:06:00 2020 -# Process ID: 16060 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1 +# Start of session at: Wed May 3 11:36:39 2023 +# Process ID: 12568 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1 # Command line: vivado.exe -log AckChecker_BusBlock16OUT_0_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16OUT_0_1.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/AckChecker_BusBlock16OUT_0_1.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/AckChecker_BusBlock16OUT_0_1.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_BusBlock16OUT_0_1.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_1_synth_1/vivado.pb index 1054f6f6744ce0ad75bf55b90e858852cb2cb57e..2c72b6219db192d435744185d492f860b5a3f6e6 100644 GIT binary patch delta 181 zcmey*zKmmnGh^9A7ZW*sF6k62eRt0gS4VyK%o2~%Bz@Oleb0dS zZo1@;U!4(qN@`kSX-`pGnL|0PolX(RTO z)U?FXoDwS-!>E8O2Gxko4;X70`IC~8%}f#vQ&ZCn%*~ThK;}-aV~!VbEGSYivQ#iM Tu`)2TGO$oEGB7d#N}2)y;IlBY diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/.vivado.begin.rst index 5a093c0..88c5896 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/AckChecker_BusBlock16OUT_0_2.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/AckChecker_BusBlock16OUT_0_2.dcp index f565ac4cb846ba96e60f1cf07c851617253418ae..7deb44d18d493910dfbe7ffa2dcb52e7ce32564e 100644 GIT binary patch delta 6426 zcmZvg1yGb-+sEndMN(ivK)NKQB&3vXP>>X9q*2(VL`q@-fd!G2uBD`xuB8@`TDn`1 z4!_msneUtTo$s2t=A8Nc|L2-BbDw+WIw$&R-cvfAXV^H@7#J7?81G)>8bwYM%E=R9 zV2Id4Sco5h>}>5(nQopdbu9RrI z;Oi}YN-`p;RH(@)o8Um}tZ2)IO`qBM&E{Cy==vN)zP9cUxZIr)f7deWc92o)`;#wd zJ~R8wle$Zo@J*bg2?Xj_x4?!J;93v|szu%(yj?m8Wbo=EUd$hp@% z$8I|GDCwL_zG^J z>YG4o`P%jMKiIznD#^$7C}DG4=u!yi4E`Ry6-_4t?F136jKuk(mNk8Ubwl0Qs&_xB zZld0E%?Pyy{SKl<_@Yo7!s(FAh$i2l?57gbGz-b!a+=-|uC9-99%iM;F(qQjxRM0b zXFTmXyz=!m`uspzCwrKl@!Z3m7Lh|+^9vi~#)!KMB>SRPEw1BlIA*B0G3XAP<+IR{ ze*a=IVe7$n@{T-x5rp#by*;+Ne`HOCgxU8I@$W!^h=8m%W^bk$Z2E2ELV zrIWUjOmVIS*GB41z!-Hec__f^g3I&+luO09a37yC?GdW0Sg;;x&@yUoOU)R|*&z

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zC&{rv(e-U5$3ZIRG*idrdL%bz)zq(909CIygG1>g3BOBziHgQG&!LU?T{VR}INN5@ zoz|+RI;_jaC9@sp@r(HvUS7vlwU_+TQQIU#0ee>HS>V^7)6!y+H%ab;MrMefj?7^O zbZ%5JH%uibS?Q?@tTgkNFntup^_k-&G^#HQBqKeBZqMdrV3{fx5o zU$(B^r7A?i>Oy2{hEw&U_V^SURzS@um6y7AWT>zL>=2@DmZwt8q}!e+&j?;;9v)`w ztkUq$N~|RJN%rz0m!bY?$MZt^74`0-bFXC|rC9HwuIZLm(2AO}8j$HfQ`v|* zh>nWEG0@%!MTx?(zg$jVZo)U{!UZQv(D0_Bb}WvNSPuP=XKTMMP8Gg_{#-tQ+$ceC z=GaX&T0c}%hfnhS>TbCf-$?dTz(d^ZE#05he*t8f_$dGY diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/AckChecker_BusBlock16OUT_0_2.tcl b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/AckChecker_BusBlock16OUT_0_2.tcl index b15a560..506c156 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/AckChecker_BusBlock16OUT_0_2.tcl +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/AckChecker_BusBlock16OUT_0_2.tcl @@ -24,15 +24,15 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] -set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] +set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] +set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/Projects/IP [current_project] +set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project] update_ip_catalog -set_property ip_output_repo d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] +set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2.xci +read_ip -quiet D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2.xci # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1 -new_name AckChecker_BusBlock16OUT_0_2 -ip [get_ips AckChecker_BusBlock16OUT_0_2]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1 -new_name AckChecker_BusBlock16OUT_0_2 -ip [get_ips AckChecker_BusBlock16OUT_0_2]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_BusBlock16OUT_0_2.dcp create_report "AckChecker_BusBlock16OUT_0_2_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_BusBlock16OUT_0_2_utilization_synth.rpt -pb AckChecker_BusBlock16OUT_0_2_utilization_synth.pb" if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/AckChecker_BusBlock16OUT_0_2.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/AckChecker_BusBlock16OUT_0_2.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_stub.v + write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_stub.vhdl + write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_sim_netlist.v + write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,47 +120,47 @@ if { [catch { if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/AckChecker_BusBlock16OUT_0_2.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/AckChecker_BusBlock16OUT_0_2.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/AckChecker_BusBlock16OUT_0_2_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_stub.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/AckChecker_BusBlock16OUT_0_2_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/AckChecker_BusBlock16OUT_0_2_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_stub.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/AckChecker_BusBlock16OUT_0_2_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/AckChecker_BusBlock16OUT_0_2_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_sim_netlist.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/AckChecker_BusBlock16OUT_0_2_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/AckChecker_BusBlock16OUT_0_2_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_sim_netlist.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/AckChecker_BusBlock16OUT_0_2_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_0_2]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_0_2]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_0_2 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_0_2 } } -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_0_2]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_0_2]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_0_2 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_0_2 } } file delete __synthesis_is_running__ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/AckChecker_BusBlock16OUT_0_2.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/AckChecker_BusBlock16OUT_0_2.vds index 5fb89f7..51f8271 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/AckChecker_BusBlock16OUT_0_2.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/AckChecker_BusBlock16OUT_0_2.vds @@ -2,17 +2,17 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:06:00 2020 -# Process ID: 14740 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1 +# Start of session at: Wed May 3 11:37:17 2023 +# Process ID: 15696 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1 # Command line: vivado.exe -log AckChecker_BusBlock16OUT_0_2.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16OUT_0_2.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/AckChecker_BusBlock16OUT_0_2.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/AckChecker_BusBlock16OUT_0_2.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_BusBlock16OUT_0_2.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_BusBlock16OUT_0_2, cache-ID = 6bbc64a1eef077bd. -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:06:08 2020... +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_BusBlock16OUT_0_2, cache-ID = 620c0a6afb1e6b3a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:37:24 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/gen_run.xml index f1514e0..f86719a 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/gen_run.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/project.wdf deleted file mode 100644 index 1c85d85..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:95469607 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/runme.log new file mode 100644 index 0000000..6bcab7c --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_BusBlock16OUT_0_2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16OUT_0_2.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_BusBlock16OUT_0_2.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_BusBlock16OUT_0_2, cache-ID = 620c0a6afb1e6b3a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:37:24 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/runme.sh index dfc09fd..f8cacd4 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/vivado.jou index 8069563..afaf70f 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:06:00 2020 -# Process ID: 14740 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1 +# Start of session at: Wed May 3 11:37:17 2023 +# Process ID: 15696 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1 # Command line: vivado.exe -log AckChecker_BusBlock16OUT_0_2.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16OUT_0_2.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/AckChecker_BusBlock16OUT_0_2.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/AckChecker_BusBlock16OUT_0_2.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_BusBlock16OUT_0_2.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_2_synth_1/vivado.pb index 85abbd2399ac108a6b9cd194fb08a75d6baace26..f9807a774537b5bbe7430b50150d1449feabb021 100644 GIT binary patch delta 181 zcmey*zKmmnGh^9A7ZW*sF6k62eRt0gS4VyK%o2~%Bz@Oleb0dS zZo1@;U!4(qN@`kSX-`pGnL|0PolX(RTO z)U?FXoDwS-!>E8O2Gxko4;X70`IC~8%}f#vQ&ZCn%*~ThK;}-aV~!VbEGSYivQ#iM Tu`)2TGO$oEGB7d#N}2)y;IlBY diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/.vivado.begin.rst index e4c7d2e..5f81ccd 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git 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z5tg;QUVm`@di>Lz)c`N1E#tPyeO$&jbeT!H)u`lw)xDiH2XliaVwLdw6Rl_Lq|)V% zC(j<0EsO0PUti#(B2syLjuzdKB!hAPw38vML$OQAV7*i1XQZ)G>-|uM3ix$C#bt&o zVjYDzl*Q>4Vq);W#Y|F^*4Vb`kSm&f47a(fN|M%3^Za69NPBQAzwOr8cNY;oZ^WE2yaA$*FPwF)nIScodAk%$6GGAM=H=4a~o+ zk(!YDPxYnjxx-)r>)(^W!8-P^@y`L9g6jPtSbv3BG&p~S|5c{_mHoTb`wL+I6&liD z|I1=eLkjOq0%Mf%g*0STf3j@Y`?Wg4ww-{z3ElrJ{+ERyeuIYRZvyqm5*;fTTtonY z82?MtL-uF0I9il=JzAXq^@Tgp64E$QfIx38oH#t~?bMZ!kpHYhhn-lkO>C+DJpBhk Ce+=;e diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/AckChecker_BusBlock16OUT_1_0.tcl b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/AckChecker_BusBlock16OUT_1_0.tcl index 49ad817..235dea9 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/AckChecker_BusBlock16OUT_1_0.tcl +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/AckChecker_BusBlock16OUT_1_0.tcl @@ -24,15 +24,15 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] -set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] +set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] +set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/Projects/IP [current_project] +set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project] update_ip_catalog -set_property ip_output_repo d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] +set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0.xci +read_ip -quiet D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0.xci # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1 -new_name AckChecker_BusBlock16OUT_1_0 -ip [get_ips AckChecker_BusBlock16OUT_1_0]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1 -new_name AckChecker_BusBlock16OUT_1_0 -ip [get_ips AckChecker_BusBlock16OUT_1_0]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_BusBlock16OUT_1_0.dcp create_report "AckChecker_BusBlock16OUT_1_0_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_BusBlock16OUT_1_0_utilization_synth.rpt -pb AckChecker_BusBlock16OUT_1_0_utilization_synth.pb" if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/AckChecker_BusBlock16OUT_1_0.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/AckChecker_BusBlock16OUT_1_0.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_stub.v + write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_stub.vhdl + write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_sim_netlist.v + write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,47 +120,47 @@ if { [catch { if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/AckChecker_BusBlock16OUT_1_0.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/AckChecker_BusBlock16OUT_1_0.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/AckChecker_BusBlock16OUT_1_0_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_stub.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/AckChecker_BusBlock16OUT_1_0_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/AckChecker_BusBlock16OUT_1_0_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_stub.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/AckChecker_BusBlock16OUT_1_0_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/AckChecker_BusBlock16OUT_1_0_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_sim_netlist.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/AckChecker_BusBlock16OUT_1_0_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/AckChecker_BusBlock16OUT_1_0_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_sim_netlist.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/AckChecker_BusBlock16OUT_1_0_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_1_0]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_1_0]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_1_0 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_1_0 } } -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_1_0]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_1_0]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_1_0 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16OUT_1_0 } } file delete __synthesis_is_running__ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/AckChecker_BusBlock16OUT_1_0.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/AckChecker_BusBlock16OUT_1_0.vds index c0d5b04..295a4ac 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/AckChecker_BusBlock16OUT_1_0.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/AckChecker_BusBlock16OUT_1_0.vds @@ -2,17 +2,17 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:06:01 2020 -# Process ID: 15432 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1 +# Start of session at: Wed May 3 11:37:19 2023 +# Process ID: 11088 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1 # Command line: vivado.exe -log AckChecker_BusBlock16OUT_1_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16OUT_1_0.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/AckChecker_BusBlock16OUT_1_0.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/AckChecker_BusBlock16OUT_1_0.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_BusBlock16OUT_1_0.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_BusBlock16OUT_1_0, cache-ID = 6bbc64a1eef077bd. -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:06:08 2020... +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_BusBlock16OUT_1_0, cache-ID = 620c0a6afb1e6b3a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:37:26 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/gen_run.xml index 7c45f7b..68d08d5 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/gen_run.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/project.wdf deleted file mode 100644 index 1c85d85..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3435:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3435:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:5648444c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:95469607 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/runme.log new file mode 100644 index 0000000..6472c38 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_BusBlock16OUT_1_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16OUT_1_0.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_BusBlock16OUT_1_0.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_BusBlock16OUT_1_0, cache-ID = 620c0a6afb1e6b3a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:37:26 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/runme.sh index d5ea6e1..c641e57 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/vivado.jou index 15696f3..0618c4d 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:06:01 2020 -# Process ID: 15432 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1 +# Start of session at: Wed May 3 11:37:19 2023 +# Process ID: 11088 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1 # Command line: vivado.exe -log AckChecker_BusBlock16OUT_1_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16OUT_1_0.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/AckChecker_BusBlock16OUT_1_0.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/AckChecker_BusBlock16OUT_1_0.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_BusBlock16OUT_1_0.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_1_0_synth_1/vivado.pb index d6e985c910acdd449f8b77222a149533f3a68dd1..6c9192d0a67032621636802f756d37bab69f1ff7 100644 GIT binary patch delta 181 zcmey*zKmmnGh^9A7ZW*sF6k62eRt0gS4VyK%o2~%Bz@Oleb0dS zZo1@;U!4(qN@`kSX-`pGnL|0PolX(RTO z)U?FXoDwS-!>E8O2Gxko4;X70`IC~8%}f#vQ&ZCn%*~ThK;}-aV~!VbEGSYivQ#iM Tu`)2TGO$oEGB7d#N}2)y;IlBY diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/.Vivado_Implementation.queue.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/.Vivado_Implementation.queue.rst deleted file mode 100644 index e69de29..0000000 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/.init_design.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/.init_design.begin.rst deleted file mode 100644 index dd68c54..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/.init_design.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/.init_design.end.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/.init_design.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/.opt_design.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/.opt_design.begin.rst deleted file mode 100644 index dd68c54..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/.opt_design.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/.opt_design.end.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/.opt_design.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/.place_design.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/.place_design.begin.rst deleted file mode 100644 index dd68c54..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/.place_design.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/.place_design.error.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/.place_design.error.rst deleted file mode 100644 index e69de29..0000000 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/.vivado.begin.rst deleted file mode 100644 index c7ce2d4..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/.vivado.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/.vivado.error.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/.vivado.error.rst deleted file mode 100644 index e69de29..0000000 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/AckChecker_wrapper.hwdef b/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/AckChecker_wrapper.hwdef deleted file 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z<)sndyfVQq diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/AckChecker_wrapper.tcl b/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/AckChecker_wrapper.tcl deleted file mode 100644 index 1e53b8d..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/AckChecker_wrapper.tcl +++ /dev/null @@ -1,160 +0,0 @@ -# -# Report generation script generated by Vivado -# - -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -proc start_step { step } { - set stopFile ".stop.rst" - if {[file isfile .stop.rst]} { - puts "" - puts "*** Halting run - EA reset detected ***" - puts "" - puts "" - return -code error - } - set beginFile ".$step.begin.rst" - set platform "$::tcl_platform(platform)" - set user "$::tcl_platform(user)" - set pid [pid] - set host "" - if { [string equal $platform unix] } { - if { [info exist ::env(HOSTNAME)] } { - set host $::env(HOSTNAME) - } - } else { - if { [info exist ::env(COMPUTERNAME)] } { - set host $::env(COMPUTERNAME) - } - } - set ch [open $beginFile w] - puts $ch "" - puts $ch "" - puts $ch " " - puts $ch " " - puts $ch "" - close $ch -} - -proc end_step { step } { - set endFile ".$step.end.rst" - set ch [open $endFile w] - close $ch -} - -proc step_failed { step } { - set endFile ".$step.error.rst" - set ch [open $endFile w] - close $ch -} - - -start_step init_design -set ACTIVE_STEP init_design -set rc [catch { - create_msg_db init_design.pb - set_param chipscope.maxJobs 3 - create_project -in_memory -part xc7z020clg484-3 - set_property design_mode GateLvl [current_fileset] - set_param project.singleFileAddWarning.threshold 0 - set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] - set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] - set_property ip_repo_paths D:/Projects/IP [current_project] - update_ip_catalog - set_property ip_output_repo D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] - set_property ip_cache_permissions {read write} [current_project] - add_files -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/AckChecker_wrapper.dcp - set_msg_config -source 4 -id {BD 41-1661} -limit 0 - set_param project.isImplRun true - add_files D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/AckChecker.bd - set_param project.isImplRun false - set_param project.isImplRun true - link_design -top AckChecker_wrapper -part xc7z020clg484-3 - set_param project.isImplRun false - write_hwdef -force -file AckChecker_wrapper.hwdef - close_msg_db -file init_design.pb -} RESULT] -if {$rc} { - step_failed init_design - return -code error $RESULT -} else { - end_step init_design - unset ACTIVE_STEP -} - -start_step opt_design -set ACTIVE_STEP opt_design -set rc [catch { - create_msg_db opt_design.pb - opt_design - write_checkpoint -force AckChecker_wrapper_opt.dcp - create_report "impl_1_opt_report_drc_0" "report_drc -file AckChecker_wrapper_drc_opted.rpt -pb AckChecker_wrapper_drc_opted.pb -rpx AckChecker_wrapper_drc_opted.rpx" - close_msg_db -file opt_design.pb -} RESULT] -if {$rc} { - step_failed opt_design - return -code error $RESULT -} else { - end_step opt_design - unset ACTIVE_STEP -} - -start_step place_design -set ACTIVE_STEP place_design -set rc [catch { - create_msg_db place_design.pb - if { [llength [get_debug_cores -quiet] ] > 0 } { - implement_debug_core - } - place_design - write_checkpoint -force AckChecker_wrapper_placed.dcp - create_report "impl_1_place_report_io_0" "report_io -file AckChecker_wrapper_io_placed.rpt" - create_report "impl_1_place_report_utilization_0" "report_utilization -file AckChecker_wrapper_utilization_placed.rpt -pb AckChecker_wrapper_utilization_placed.pb" - create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file AckChecker_wrapper_control_sets_placed.rpt" - close_msg_db -file place_design.pb -} RESULT] -if {$rc} { - step_failed place_design - return -code error $RESULT -} else { - end_step place_design - unset ACTIVE_STEP -} - -start_step route_design -set ACTIVE_STEP route_design -set rc [catch { - create_msg_db route_design.pb - route_design - write_checkpoint -force AckChecker_wrapper_routed.dcp - create_report "impl_1_route_report_drc_0" "report_drc -file AckChecker_wrapper_drc_routed.rpt -pb AckChecker_wrapper_drc_routed.pb -rpx AckChecker_wrapper_drc_routed.rpx" - create_report "impl_1_route_report_methodology_0" "report_methodology -file AckChecker_wrapper_methodology_drc_routed.rpt -pb AckChecker_wrapper_methodology_drc_routed.pb -rpx AckChecker_wrapper_methodology_drc_routed.rpx" - create_report "impl_1_route_report_power_0" "report_power -file AckChecker_wrapper_power_routed.rpt -pb AckChecker_wrapper_power_summary_routed.pb -rpx AckChecker_wrapper_power_routed.rpx" - create_report "impl_1_route_report_route_status_0" "report_route_status -file AckChecker_wrapper_route_status.rpt -pb AckChecker_wrapper_route_status.pb" - create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file AckChecker_wrapper_timing_summary_routed.rpt -pb AckChecker_wrapper_timing_summary_routed.pb -rpx AckChecker_wrapper_timing_summary_routed.rpx -warn_on_violation " - create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file AckChecker_wrapper_incremental_reuse_routed.rpt" - create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file AckChecker_wrapper_clock_utilization_routed.rpt" - create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file AckChecker_wrapper_bus_skew_routed.rpt -pb AckChecker_wrapper_bus_skew_routed.pb -rpx AckChecker_wrapper_bus_skew_routed.rpx" - close_msg_db -file route_design.pb -} RESULT] -if {$rc} { - write_checkpoint -force AckChecker_wrapper_routed_error.dcp - step_failed route_design - return -code error $RESULT -} else { - end_step route_design - unset ACTIVE_STEP -} - diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/AckChecker_wrapper.vdi b/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/AckChecker_wrapper.vdi deleted file mode 100644 index a3b75c3..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/AckChecker_wrapper.vdi +++ /dev/null @@ -1,716 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1 (64-bit) -# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 -# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:10:55 2020 -# Process ID: 19328 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1 -# Command line: vivado.exe -log AckChecker_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source AckChecker_wrapper.tcl -notrace -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/AckChecker_wrapper.vdi -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source AckChecker_wrapper.tcl -notrace -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1'.) -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -Command: link_design -top AckChecker_wrapper -part xc7z020clg484-3 -Design is defaulting to srcset: sources_1 -Design is defaulting to constrset: constrs_1 -INFO: [Device 21-403] Loading part xc7z020clg484-3 -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0.dcp' for cell 'AckChecker_i/AckCheckerConcept_0' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1.dcp' for cell 'AckChecker_i/AckCheckerConcept_1' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1.dcp' for cell 'AckChecker_i/AckCheckerConcept_10' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1.dcp' for cell 'AckChecker_i/AckCheckerConcept_11' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2.dcp' for cell 'AckChecker_i/AckCheckerConcept_12' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_2/AckChecker_AckCheckerConcept_5_2.dcp' for cell 'AckChecker_i/AckCheckerConcept_13' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2.dcp' for cell 'AckChecker_i/AckCheckerConcept_14' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2.dcp' for cell 'AckChecker_i/AckCheckerConcept_15' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0.dcp' for cell 'AckChecker_i/AckCheckerConcept_16' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_0/AckChecker_AckCheckerConcept_13_0.dcp' for cell 'AckChecker_i/AckCheckerConcept_17' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0.dcp' for cell 'AckChecker_i/AckCheckerConcept_18' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_0/AckChecker_AckCheckerConcept_15_0.dcp' for cell 'AckChecker_i/AckCheckerConcept_19' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2.dcp' for cell 'AckChecker_i/AckCheckerConcept_2' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1.dcp' for cell 'AckChecker_i/AckCheckerConcept_20' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1.dcp' for cell 'AckChecker_i/AckCheckerConcept_21' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1.dcp' for cell 'AckChecker_i/AckCheckerConcept_22' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1.dcp' for cell 'AckChecker_i/AckCheckerConcept_23' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2.dcp' for cell 'AckChecker_i/AckCheckerConcept_24' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_2/AckChecker_AckCheckerConcept_13_2.dcp' for cell 'AckChecker_i/AckCheckerConcept_25' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2.dcp' for cell 'AckChecker_i/AckCheckerConcept_26' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2.dcp' for cell 'AckChecker_i/AckCheckerConcept_27' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_3/AckChecker_AckCheckerConcept_12_3.dcp' for cell 'AckChecker_i/AckCheckerConcept_28' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_3/AckChecker_AckCheckerConcept_13_3.dcp' for cell 'AckChecker_i/AckCheckerConcept_29' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3.dcp' for cell 'AckChecker_i/AckCheckerConcept_3' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3.dcp' for cell 'AckChecker_i/AckCheckerConcept_30' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3.dcp' for cell 'AckChecker_i/AckCheckerConcept_31' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_4/AckChecker_AckCheckerConcept_0_4.dcp' for cell 'AckChecker_i/AckCheckerConcept_4' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_1_0/AckChecker_AckCheckerConcept_1_0.dcp' for cell 'AckChecker_i/AckCheckerConcept_5' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_2_0/AckChecker_AckCheckerConcept_2_0.dcp' for cell 'AckChecker_i/AckCheckerConcept_6' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_3_0/AckChecker_AckCheckerConcept_3_0.dcp' for cell 'AckChecker_i/AckCheckerConcept_7' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_1/AckChecker_AckCheckerConcept_4_1.dcp' for cell 'AckChecker_i/AckCheckerConcept_8' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1.dcp' for cell 'AckChecker_i/AckCheckerConcept_9' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_0/AckChecker_BusBlock16IN_0_0.dcp' for cell 'AckChecker_i/BusBlock16IN_0' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1.dcp' for cell 'AckChecker_i/BusBlock16IN_1' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_2/AckChecker_BusBlock16IN_0_2.dcp' for cell 'AckChecker_i/BusBlock16IN_2' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0.dcp' for cell 'AckChecker_i/BusBlock16IN_3' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_1_0/AckChecker_BusBlock16IN_1_0.dcp' for cell 'AckChecker_i/BusBlock16IN_4' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0.dcp' for cell 'AckChecker_i/BusBlock16IN_5' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_1/AckChecker_BusBlock16IN_4_1.dcp' for cell 'AckChecker_i/BusBlock16IN_6' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_6_0/AckChecker_BusBlock16IN_6_0.dcp' for cell 'AckChecker_i/BusBlock16IN_7' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0.dcp' for cell 'AckChecker_i/BusBlock16OUT_0' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1.dcp' for cell 'AckChecker_i/BusBlock16OUT_1' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2.dcp' for cell 'AckChecker_i/BusBlock16OUT_2' -INFO: [Project 1-454] Reading design checkpoint 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0.dcp' for cell 'AckChecker_i/BusBlock16OUT_3' -INFO: [Netlist 29-17] Analyzing 128 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-479] Netlist was created with Vivado 2019.1 -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 836.508 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -54 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. -link_design completed successfully -link_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 836.508 ; gain = 444.395 -Command: opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z020' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020' -Running DRC as a precondition to command opt_design - -Starting DRC Task -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Project 1-461] DRC finished with 0 Errors -INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.509 . Memory (MB): peak = 866.031 ; gain = 29.523 - -Starting Cache Timing Information Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -Ending Cache Timing Information Task | Checksum: b12fa2fa - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1409.840 ; gain = 543.809 - -Starting Logic Optimization Task - -Phase 1 Retarget -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: b12fa2fa - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.097 . Memory (MB): peak = 1554.492 ; gain = 0.000 -INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells - -Phase 2 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: b12fa2fa - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.114 . Memory (MB): peak = 1554.492 ; gain = 0.000 -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells - -Phase 3 Sweep -Phase 3 Sweep | Checksum: 7687dffe - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.168 . Memory (MB): peak = 1554.492 ; gain = 0.000 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells - -Phase 4 BUFG optimization -INFO: [Opt 31-194] Inserted BUFG Clk_0_IBUF_BUFG_inst to drive 416 load(s) on clock net Clk_0_IBUF_BUFG -INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets -Phase 4 BUFG optimization | Checksum: ebc243cf - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.235 . Memory (MB): peak = 1554.492 ; gain = 0.000 -INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 1 are BUFGs and removed 0 cells. - -Phase 5 Shift Register Optimization -INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs -Phase 5 Shift Register Optimization | Checksum: ebc243cf - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.264 . Memory (MB): peak = 1554.492 ; gain = 0.000 -INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells - -Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: ebc243cf - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.273 . Memory (MB): peak = 1554.492 ; gain = 0.000 -INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells -Opt_design Change Summary -========================= - - -------------------------------------------------------------------------------------------------------------------------- -| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | -------------------------------------------------------------------------------------------------------------------------- -| Retarget | 0 | 0 | 0 | -| Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 0 | 0 | -| BUFG optimization | 1 | 0 | 0 | -| Shift Register Optimization | 0 | 0 | 0 | -| Post Processing Netlist | 0 | 0 | 0 | -------------------------------------------------------------------------------------------------------------------------- - - - -Starting Connectivity Check Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1554.492 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: 17f78cb65 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.371 . Memory (MB): peak = 1554.492 ; gain = 0.000 - -Starting Power Optimization Task -INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 17f78cb65 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1554.492 ; gain = 0.000 - -Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 17f78cb65 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1554.492 ; gain = 0.000 - -Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1554.492 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 17f78cb65 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1554.492 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -73 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. -opt_design completed successfully -opt_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1554.492 ; gain = 717.984 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1554.492 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/AckChecker_wrapper_opt.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file AckChecker_wrapper_drc_opted.rpt -pb AckChecker_wrapper_drc_opted.pb -rpx AckChecker_wrapper_drc_opted.rpx -Command: report_drc -file AckChecker_wrapper_drc_opted.rpt -pb AckChecker_wrapper_drc_opted.pb -rpx AckChecker_wrapper_drc_opted.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/AckChecker_wrapper_drc_opted.rpt. -report_drc completed successfully -Command: place_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z020' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020' -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - -Starting Placer Task -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs - -Phase 1 Placer Initialization - -Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1554.492 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 90872012 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1554.492 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1554.492 ; gain = 0.000 - -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -INFO: [Timing 38-35] Done setting XDC timing constraints. -ERROR: [Place 30-58] IO placement is infeasible. Number of unplaced terminals (226) is greater than number of available sites (200). -The following are banks with available pins: - IO Group: 1 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: In RangeId: 1 has only 200 sites available on device, but needs 226 sites. - Term: ackTime_0[0] - Term: ackTime_0[1] - Term: ackTime_0[2] - Term: ackTime_0[3] - Term: ackTime_0[4] - Term: ackTime_0[5] - Term: ackTime_0[6] - Term: ackTime_0[7] - Term: ackTime_0[8] - Term: ackTime_0[9] - Term: ackTime_0[10] - Term: ackTime_0[11] - Term: ackTime_0[12] - Term: ackTime_0[13] - Term: ackTime_0[14] - Term: ackTime_0[15] - Term: ackTime_0[16] - Term: ackTime_0[17] - Term: ackTime_0[18] - Term: ackTime_0[19] - Term: ackTime_0[20] - Term: ackTime_0[21] - Term: ackTime_0[22] - Term: ackTime_0[23] - Term: ackTime_0[24] - Term: ackTime_0[25] - Term: ackTime_0[26] - Term: ackTime_0[27] - Term: ackTime_0[28] - Term: ackTime_0[29] - Term: ackTime_0[30] - Term: ackTime_0[31] - Term: AcknowledgeProtectionEnableGroup0[0] - Term: AcknowledgeProtectionEnableGroup0[1] - Term: AcknowledgeProtectionEnableGroup0[2] - Term: AcknowledgeProtectionEnableGroup0[3] - Term: AcknowledgeProtectionEnableGroup0[4] - Term: AcknowledgeProtectionEnableGroup0[5] - Term: AcknowledgeProtectionEnableGroup0[6] - Term: AcknowledgeProtectionEnableGroup0[7] - Term: AcknowledgeProtectionEnableGroup0[8] - Term: AcknowledgeProtectionEnableGroup0[9] - Term: AcknowledgeProtectionEnableGroup0[10] - Term: AcknowledgeProtectionEnableGroup0[11] - Term: AcknowledgeProtectionEnableGroup0[12] - Term: AcknowledgeProtectionEnableGroup0[13] - Term: AcknowledgeProtectionEnableGroup0[14] - Term: AcknowledgeProtectionEnableGroup0[15] - Term: AcknowledgeProtectionEnableGroup1[0] - Term: AcknowledgeProtectionEnableGroup1[1] - Term: AcknowledgeProtectionEnableGroup1[2] - Term: AcknowledgeProtectionEnableGroup1[3] - Term: AcknowledgeProtectionEnableGroup1[4] - Term: AcknowledgeProtectionEnableGroup1[5] - Term: AcknowledgeProtectionEnableGroup1[6] - Term: AcknowledgeProtectionEnableGroup1[7] - Term: AcknowledgeProtectionEnableGroup1[8] - Term: AcknowledgeProtectionEnableGroup1[9] - Term: AcknowledgeProtectionEnableGroup1[10] - Term: AcknowledgeProtectionEnableGroup1[11] - Term: AcknowledgeProtectionEnableGroup1[12] - Term: AcknowledgeProtectionEnableGroup1[13] - Term: AcknowledgeProtectionEnableGroup1[14] - Term: AcknowledgeProtectionEnableGroup1[15] - Term: CurrentProtectionEnableGroup0[0] - Term: CurrentProtectionEnableGroup0[1] - Term: CurrentProtectionEnableGroup0[2] - Term: CurrentProtectionEnableGroup0[3] - Term: CurrentProtectionEnableGroup0[4] - Term: CurrentProtectionEnableGroup0[5] - Term: CurrentProtectionEnableGroup0[6] - Term: CurrentProtectionEnableGroup0[7] - Term: CurrentProtectionEnableGroup0[8] - Term: CurrentProtectionEnableGroup0[9] - Term: CurrentProtectionEnableGroup0[10] - Term: CurrentProtectionEnableGroup0[11] - Term: CurrentProtectionEnableGroup0[12] - Term: CurrentProtectionEnableGroup0[13] - Term: CurrentProtectionEnableGroup0[14] - Term: CurrentProtectionEnableGroup0[15] - Term: CurrentProtectionEnableGroup1[0] - Term: CurrentProtectionEnableGroup1[1] - Term: CurrentProtectionEnableGroup1[2] - Term: CurrentProtectionEnableGroup1[3] - Term: CurrentProtectionEnableGroup1[4] - Term: CurrentProtectionEnableGroup1[5] - Term: CurrentProtectionEnableGroup1[6] - Term: CurrentProtectionEnableGroup1[7] - Term: CurrentProtectionEnableGroup1[8] - Term: CurrentProtectionEnableGroup1[9] - Term: CurrentProtectionEnableGroup1[10] - Term: CurrentProtectionEnableGroup1[11] - Term: CurrentProtectionEnableGroup1[12] - Term: CurrentProtectionEnableGroup1[13] - Term: CurrentProtectionEnableGroup1[14] - Term: CurrentProtectionEnableGroup1[15] - Term: MaskAcknowledgeGroup0[0] - Term: MaskAcknowledgeGroup0[1] - Term: MaskAcknowledgeGroup0[2] - Term: MaskAcknowledgeGroup0[3] - Term: MaskAcknowledgeGroup0[4] - Term: MaskAcknowledgeGroup0[5] - Term: MaskAcknowledgeGroup0[6] - Term: MaskAcknowledgeGroup0[7] - Term: MaskAcknowledgeGroup0[8] - Term: MaskAcknowledgeGroup0[9] - Term: MaskAcknowledgeGroup0[10] - Term: MaskAcknowledgeGroup0[11] - Term: MaskAcknowledgeGroup0[12] - Term: MaskAcknowledgeGroup0[13] - Term: MaskAcknowledgeGroup0[14] - Term: MaskAcknowledgeGroup0[15] - Term: MaskAcknowledgeGroup1[0] - Term: MaskAcknowledgeGroup1[1] - Term: MaskAcknowledgeGroup1[2] - Term: MaskAcknowledgeGroup1[3] - Term: MaskAcknowledgeGroup1[4] - Term: MaskAcknowledgeGroup1[5] - Term: MaskAcknowledgeGroup1[6] - Term: MaskAcknowledgeGroup1[7] - Term: MaskAcknowledgeGroup1[8] - Term: MaskAcknowledgeGroup1[9] - Term: MaskAcknowledgeGroup1[10] - Term: MaskAcknowledgeGroup1[11] - Term: MaskAcknowledgeGroup1[12] - Term: MaskAcknowledgeGroup1[13] - Term: MaskAcknowledgeGroup1[14] - Term: MaskAcknowledgeGroup1[15] - Term: MaskCurrentGroup0[0] - Term: MaskCurrentGroup0[1] - Term: MaskCurrentGroup0[2] - Term: MaskCurrentGroup0[3] - Term: MaskCurrentGroup0[4] - Term: MaskCurrentGroup0[5] - Term: MaskCurrentGroup0[6] - Term: MaskCurrentGroup0[7] - Term: MaskCurrentGroup0[8] - Term: MaskCurrentGroup0[9] - Term: MaskCurrentGroup0[10] - Term: MaskCurrentGroup0[11] - Term: MaskCurrentGroup0[12] - Term: MaskCurrentGroup0[13] - Term: MaskCurrentGroup0[14] - Term: MaskCurrentGroup0[15] - Term: MaskCurrentGroup1[0] - Term: MaskCurrentGroup1[1] - Term: MaskCurrentGroup1[2] - Term: MaskCurrentGroup1[3] - Term: MaskCurrentGroup1[4] - Term: MaskCurrentGroup1[5] - Term: MaskCurrentGroup1[6] - Term: MaskCurrentGroup1[7] - Term: MaskCurrentGroup1[8] - Term: MaskCurrentGroup1[9] - Term: MaskCurrentGroup1[10] - Term: MaskCurrentGroup1[11] - Term: MaskCurrentGroup1[12] - Term: MaskCurrentGroup1[13] - Term: MaskCurrentGroup1[14] - Term: MaskCurrentGroup1[15] - Term: ReceiverGroup0[0] - Term: ReceiverGroup0[1] - Term: ReceiverGroup0[2] - Term: ReceiverGroup0[3] - Term: ReceiverGroup0[4] - Term: ReceiverGroup0[5] - Term: ReceiverGroup0[6] - Term: ReceiverGroup0[7] - Term: ReceiverGroup0[8] - Term: ReceiverGroup0[9] - Term: ReceiverGroup0[10] - Term: ReceiverGroup0[11] - Term: ReceiverGroup0[12] - Term: ReceiverGroup0[13] - Term: ReceiverGroup0[14] - Term: ReceiverGroup0[15] - Term: ReceiverGroup1[0] - Term: ReceiverGroup1[1] - Term: ReceiverGroup1[2] - Term: ReceiverGroup1[3] - Term: ReceiverGroup1[4] - Term: ReceiverGroup1[5] - Term: ReceiverGroup1[6] - Term: ReceiverGroup1[7] - Term: ReceiverGroup1[8] - Term: ReceiverGroup1[9] - Term: ReceiverGroup1[10] - Term: ReceiverGroup1[11] - Term: ReceiverGroup1[12] - Term: ReceiverGroup1[13] - Term: ReceiverGroup1[14] - Term: ReceiverGroup1[15] - Term: TransmitterGroup0[0] - Term: TransmitterGroup0[1] - Term: TransmitterGroup0[2] - Term: TransmitterGroup0[3] - Term: TransmitterGroup0[4] - Term: TransmitterGroup0[5] - Term: TransmitterGroup0[6] - Term: TransmitterGroup0[7] - Term: TransmitterGroup0[8] - Term: TransmitterGroup0[9] - Term: TransmitterGroup0[10] - Term: TransmitterGroup0[11] - Term: TransmitterGroup0[12] - Term: TransmitterGroup0[13] - Term: TransmitterGroup0[14] - Term: TransmitterGroup0[15] - Term: TransmitterGroup1[0] - Term: TransmitterGroup1[1] - Term: TransmitterGroup1[2] - Term: TransmitterGroup1[3] - Term: TransmitterGroup1[4] - Term: TransmitterGroup1[5] - Term: TransmitterGroup1[6] - Term: TransmitterGroup1[7] - Term: TransmitterGroup1[8] - Term: TransmitterGroup1[9] - Term: TransmitterGroup1[10] - Term: TransmitterGroup1[11] - Term: TransmitterGroup1[12] - Term: TransmitterGroup1[13] - Term: TransmitterGroup1[14] - Term: TransmitterGroup1[15] - Term: Ready_0 - Term: reset_0 - - -ERROR: [Place 30-58] IO placement is infeasible. Number of unplaced terminals (290) is greater than number of available sites (200). -The following are banks with available pins: - IO Group: 1 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: In RangeId: 1 has only 200 sites available on device, but needs 226 sites. - Term: ackTime_0[0] - Term: ackTime_0[1] - Term: ackTime_0[2] - Term: ackTime_0[3] - Term: ackTime_0[4] - Term: ackTime_0[5] - Term: ackTime_0[6] - Term: ackTime_0[7] - Term: ackTime_0[8] - Term: ackTime_0[9] - Term: ackTime_0[10] - Term: ackTime_0[11] - Term: ackTime_0[12] - Term: ackTime_0[13] - Term: ackTime_0[14] - Term: ackTime_0[15] - Term: ackTime_0[16] - Term: ackTime_0[17] - Term: ackTime_0[18] - Term: ackTime_0[19] - Term: ackTime_0[20] - Term: ackTime_0[21] - Term: ackTime_0[22] - Term: ackTime_0[23] - Term: ackTime_0[24] - Term: ackTime_0[25] - Term: ackTime_0[26] - Term: ackTime_0[27] - Term: ackTime_0[28] - Term: ackTime_0[29] - Term: ackTime_0[30] - Term: ackTime_0[31] - Term: AcknowledgeProtectionEnableGroup0[0] - Term: AcknowledgeProtectionEnableGroup0[1] - Term: AcknowledgeProtectionEnableGroup0[2] - Term: AcknowledgeProtectionEnableGroup0[3] - Term: AcknowledgeProtectionEnableGroup0[4] - Term: AcknowledgeProtectionEnableGroup0[5] - Term: AcknowledgeProtectionEnableGroup0[6] - Term: AcknowledgeProtectionEnableGroup0[7] - Term: AcknowledgeProtectionEnableGroup0[8] - Term: AcknowledgeProtectionEnableGroup0[9] - Term: AcknowledgeProtectionEnableGroup0[10] - Term: AcknowledgeProtectionEnableGroup0[11] - Term: AcknowledgeProtectionEnableGroup0[12] - Term: AcknowledgeProtectionEnableGroup0[13] - Term: AcknowledgeProtectionEnableGroup0[14] - Term: AcknowledgeProtectionEnableGroup0[15] - Term: AcknowledgeProtectionEnableGroup1[0] - Term: AcknowledgeProtectionEnableGroup1[1] - Term: AcknowledgeProtectionEnableGroup1[2] - Term: AcknowledgeProtectionEnableGroup1[3] - Term: AcknowledgeProtectionEnableGroup1[4] - Term: AcknowledgeProtectionEnableGroup1[5] - Term: AcknowledgeProtectionEnableGroup1[6] - Term: AcknowledgeProtectionEnableGroup1[7] - Term: AcknowledgeProtectionEnableGroup1[8] - Term: AcknowledgeProtectionEnableGroup1[9] - Term: AcknowledgeProtectionEnableGroup1[10] - Term: AcknowledgeProtectionEnableGroup1[11] - Term: AcknowledgeProtectionEnableGroup1[12] - Term: AcknowledgeProtectionEnableGroup1[13] - Term: AcknowledgeProtectionEnableGroup1[14] - Term: AcknowledgeProtectionEnableGroup1[15] - Term: CurrentProtectionEnableGroup0[0] - Term: CurrentProtectionEnableGroup0[1] - Term: CurrentProtectionEnableGroup0[2] - Term: CurrentProtectionEnableGroup0[3] - Term: CurrentProtectionEnableGroup0[4] - Term: CurrentProtectionEnableGroup0[5] - Term: CurrentProtectionEnableGroup0[6] - Term: CurrentProtectionEnableGroup0[7] - Term: CurrentProtectionEnableGroup0[8] - Term: CurrentProtectionEnableGroup0[9] - Term: CurrentProtectionEnableGroup0[10] - Term: CurrentProtectionEnableGroup0[11] - Term: CurrentProtectionEnableGroup0[12] - Term: CurrentProtectionEnableGroup0[13] - Term: CurrentProtectionEnableGroup0[14] - Term: CurrentProtectionEnableGroup0[15] - Term: CurrentProtectionEnableGroup1[0] - Term: CurrentProtectionEnableGroup1[1] - Term: CurrentProtectionEnableGroup1[2] - Term: CurrentProtectionEnableGroup1[3] - Term: CurrentProtectionEnableGroup1[4] - Term: CurrentProtectionEnableGroup1[5] - Term: CurrentProtectionEnableGroup1[6] - Term: CurrentProtectionEnableGroup1[7] - Term: CurrentProtectionEnableGroup1[8] - Term: CurrentProtectionEnableGroup1[9] - Term: CurrentProtectionEnableGroup1[10] - Term: CurrentProtectionEnableGroup1[11] - Term: CurrentProtectionEnableGroup1[12] - Term: CurrentProtectionEnableGroup1[13] - Term: CurrentProtectionEnableGroup1[14] - Term: CurrentProtectionEnableGroup1[15] - Term: MaskAcknowledgeGroup0[0] - Term: MaskAcknowledgeGroup0[1] - Term: MaskAcknowledgeGroup0[2] - Term: MaskAcknowledgeGroup0[3] - Term: MaskAcknowledgeGroup0[4] - Term: MaskAcknowledgeGroup0[5] - Term: MaskAcknowledgeGroup0[6] - Term: MaskAcknowledgeGroup0[7] - Term: MaskAcknowledgeGroup0[8] - Term: MaskAcknowledgeGroup0[9] - Term: MaskAcknowledgeGroup0[10] - Term: MaskAcknowledgeGroup0[11] - Term: MaskAcknowledgeGroup0[12] - Term: MaskAcknowledgeGroup0[13] - Term: MaskAcknowledgeGroup0[14] - Term: MaskAcknowledgeGroup0[15] - Term: MaskAcknowledgeGroup1[0] - Term: MaskAcknowledgeGroup1[1] - Term: MaskAcknowledgeGroup1[2] - Term: MaskAcknowledgeGroup1[3] - Term: MaskAcknowledgeGroup1[4] - Term: MaskAcknowledgeGroup1[5] - Term: MaskAcknowledgeGroup1[6] - Term: MaskAcknowledgeGroup1[7] - Term: MaskAcknowledgeGroup1[8] - Term: MaskAcknowledgeGroup1[9] - Term: MaskAcknowledgeGroup1[10] - Term: MaskAcknowledgeGroup1[11] - Term: MaskAcknowledgeGroup1[12] - Term: MaskAcknowledgeGroup1[13] - Term: MaskAcknowledgeGroup1[14] - Term: MaskAcknowledgeGroup1[15] - Term: MaskCurrentGroup0[0] - Term: MaskCurrentGroup0[1] - Term: MaskCurrentGroup0[2] - Term: MaskCurrentGroup0[3] - Term: MaskCurrentGroup0[4] - Term: MaskCurrentGroup0[5] - Term: MaskCurrentGroup0[6] - Term: MaskCurrentGroup0[7] - Term: MaskCurrentGroup0[8] - Term: MaskCurrentGroup0[9] - Term: MaskCurrentGroup0[10] - Term: MaskCurrentGroup0[11] - Term: MaskCurrentGroup0[12] - Term: MaskCurrentGroup0[13] - Term: MaskCurrentGroup0[14] - Term: MaskCurrentGroup0[15] - Term: MaskCurrentGroup1[0] - Term: MaskCurrentGroup1[1] - Term: MaskCurrentGroup1[2] - Term: MaskCurrentGroup1[3] - Term: MaskCurrentGroup1[4] - Term: MaskCurrentGroup1[5] - Term: MaskCurrentGroup1[6] - Term: MaskCurrentGroup1[7] - Term: MaskCurrentGroup1[8] - Term: MaskCurrentGroup1[9] - Term: MaskCurrentGroup1[10] - Term: MaskCurrentGroup1[11] - Term: MaskCurrentGroup1[12] - Term: MaskCurrentGroup1[13] - Term: MaskCurrentGroup1[14] - Term: MaskCurrentGroup1[15] - Term: ReceiverGroup0[0] - Term: ReceiverGroup0[1] - Term: ReceiverGroup0[2] - Term: ReceiverGroup0[3] - Term: ReceiverGroup0[4] - Term: ReceiverGroup0[5] - Term: ReceiverGroup0[6] - Term: ReceiverGroup0[7] - Term: ReceiverGroup0[8] - Term: ReceiverGroup0[9] - Term: ReceiverGroup0[10] - Term: ReceiverGroup0[11] - Term: ReceiverGroup0[12] - Term: ReceiverGroup0[13] - Term: ReceiverGroup0[14] - Term: ReceiverGroup0[15] - Term: ReceiverGroup1[0] - Term: ReceiverGroup1[1] - Term: ReceiverGroup1[2] - Term: ReceiverGroup1[3] - Term: ReceiverGroup1[4] - Term: ReceiverGroup1[5] - Term: ReceiverGroup1[6] - Term: ReceiverGroup1[7] - Term: ReceiverGroup1[8] - Term: ReceiverGroup1[9] - Term: ReceiverGroup1[10] - Term: ReceiverGroup1[11] - Term: ReceiverGroup1[12] - Term: ReceiverGroup1[13] - Term: ReceiverGroup1[14] - Term: ReceiverGroup1[15] - Term: TransmitterGroup0[0] - Term: TransmitterGroup0[1] - Term: TransmitterGroup0[2] - Term: TransmitterGroup0[3] - Term: TransmitterGroup0[4] - Term: TransmitterGroup0[5] - Term: TransmitterGroup0[6] - Term: TransmitterGroup0[7] - Term: TransmitterGroup0[8] - Term: TransmitterGroup0[9] - Term: TransmitterGroup0[10] - Term: TransmitterGroup0[11] - Term: TransmitterGroup0[12] - Term: TransmitterGroup0[13] - Term: TransmitterGroup0[14] - Term: TransmitterGroup0[15] - Term: TransmitterGroup1[0] - Term: TransmitterGroup1[1] - Term: TransmitterGroup1[2] - Term: TransmitterGroup1[3] - Term: TransmitterGroup1[4] - Term: TransmitterGroup1[5] - Term: TransmitterGroup1[6] - Term: TransmitterGroup1[7] - Term: TransmitterGroup1[8] - Term: TransmitterGroup1[9] - Term: TransmitterGroup1[10] - Term: TransmitterGroup1[11] - Term: TransmitterGroup1[12] - Term: TransmitterGroup1[13] - Term: TransmitterGroup1[14] - Term: TransmitterGroup1[15] - Term: Ready_0 - Term: reset_0 - - -ERROR: [Place 30-374] IO placer failed to find a solution -Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve. - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| IO Placement : Bank Stats | -+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ -| Id | Pins | Terms | Standards | IDelayCtrls | VREF | VCCO | VR | DCI | -+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ -| 0 | 0 | 0 | | | | | | | -| 13 | 50 | 0 | | | | | | | -| 33 | 50 | 0 | | | | | | | -| 34 | 50 | 0 | | | | | | | -| 35 | 50 | 0 | | | | | | | -+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ -| | 200 | 0 | | | | | | | -+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ - -IO Placement: -+--------+----------------------+-----------------+----------------------+----------------------+----------------------+ -| BankId | Terminal | Standard | Site | Pin | Attributes | -+--------+----------------------+-----------------+----------------------+----------------------+----------------------+ - -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 03f5f044 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1554.492 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 03f5f044 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1554.492 ; gain = 0.000 -ERROR: [Place 30-99] Placer failed with error: 'IO Clock Placer failed' -Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure. -Ending Placer Task | Checksum: 03f5f044 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1554.492 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -88 Infos, 2 Warnings, 0 Critical Warnings and 5 Errors encountered. -place_design failed -ERROR: [Common 17-69] Command failed: Placer could not place all instances -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:11:23 2020... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/AckChecker_wrapper_drc_opted.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/AckChecker_wrapper_drc_opted.pb deleted file mode 100644 index fe118222139b02011a7d36ba0886c80902ae8f34..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 37 scmd;LGcqtV(KDRH% - Ruledeck: default - Max violations: - Violations found: 4 -+---------+------------------+----------------------------+------------+ -| Rule | Severity | Description | Violations | -+---------+------------------+----------------------------+------------+ -| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 | -| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 | -| IOCNT-1 | Warning | Number of IOs | 1 | -| ZPS7-1 | Warning | PS7 block required | 1 | -+---------+------------------+----------------------------+------------+ - -2. REPORT DETAILS ------------------ -NSTD-1#1 Critical Warning -Unspecified I/O Standard -291 out of 291 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: AcknowledgeErrorGroup0[15:0], AcknowledgeErrorGroup1[15:0], AcknowledgeProtectionEnableGroup0[15:0], AcknowledgeProtectionEnableGroup1[15:0], CurrentErrorGroup0[15:0], CurrentErrorGroup1[15:0], CurrentProtectionEnableGroup0[15:0], CurrentProtectionEnableGroup1[15:0], MaskAcknowledgeGroup0[15:0], MaskAcknowledgeGroup1[15:0], MaskCurrentGroup0[15:0], MaskCurrentGroup1[15:0], ReceiverGroup0[15:0], ReceiverGroup1[15:0], TransmitterGroup0[15:0] (the first 15 of 20 listed). -Related violations: - -UCIO-1#1 Critical Warning -Unconstrained Logical Port -291 out of 291 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: AcknowledgeErrorGroup0[15:0], AcknowledgeErrorGroup1[15:0], AcknowledgeProtectionEnableGroup0[15:0], AcknowledgeProtectionEnableGroup1[15:0], CurrentErrorGroup0[15:0], CurrentErrorGroup1[15:0], CurrentProtectionEnableGroup0[15:0], CurrentProtectionEnableGroup1[15:0], MaskAcknowledgeGroup0[15:0], MaskAcknowledgeGroup1[15:0], MaskCurrentGroup0[15:0], MaskCurrentGroup1[15:0], ReceiverGroup0[15:0], ReceiverGroup1[15:0], TransmitterGroup0[15:0] (the first 15 of 20 listed). -Related violations: - -IOCNT-1#1 Warning -Number of IOs -The design contains 291 unplaced I/O ports while the target device, xc7z020clg484-3, has 200 remaining available user I/O pins. This DRC assumes that all ports which do not drive MGT pins should be placed on user I/O pins. To correct this issue: -1. Ensure you are targeting the correct device and package. Select a larger device or different package if necessary. -2. Check the top-level ports of the design to ensure the correct number of ports are specified. -3. Consider design changes to reduce the number of user I/O pins needed. - -Related violations: - -ZPS7-1#1 Warning -PS7 block required -The PS7 cell must be used in this Zynq design in order to enable correct default configuration. -Related violations: - - diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/AckChecker_wrapper_drc_opted.rpx b/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/AckChecker_wrapper_drc_opted.rpx deleted file mode 100644 index d90437aa45860686ff6e446d1d39accd9ee60d05..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8253 zcmeHMJ!~9B6h6ns*%*a55kW~vq?b^{iR|U>oL_f|eMF8DJF+i{NEDsMyK{FV@6Bvx zXU{eW2`L2>6bL~{6A1|+K}iWE1qCf-T1rxY1O>dev$wgk_l`6cC|ruzp7%3v-+S|B z-uqrJ6bjDa$-~FS%f-?KclOl&TUTp$gj(TI9GK`jk|#z>Zut;g@z&>?+*{|mwxL-V z;!j_DH5D4}yE@!F@)!O)&>Ra3n}zpB_Ix<9=i`yWC!;Sftjt5It+F3C8=2g5Y;s-; zBRm$sU8bdwjZ@=GtJQ^>(%B=oWfXEx)CKop@y%seHB998ND(-nw%8M)mYG2pJj9 zeA2~8Rs)M7(U53CYKv!uT&Olh1TD4&9_wu4DQUPgLP<~>b$O~4G9%VRAj}qQ2-5`9 zen>wrlG8<<19_ADHj^kG6E+e9l2FsY=mK135-xTVz^ zE@IN+p_-!tAk{{|{RXdSt@Jgm;;?wXbbhY*U^<^#%AulGL)ormMKaXiS4}Qsrg1*T zY?UU*k{y)oGP#Pg4@t#ynKDf`S+w5ekKS*{Blbw9TkMqTCS(#T+~cCnxB0tgHRG*n zCZm=xrk5S2D8_Z6BLk)LNzp7qATR^`Gw$`ThShXfO^4O=KT=Km)lw`_=LXPb2hhp` zXr%$PzIDBL|8jq^OZ`a~`;#v8C!Oz48sL!u4jJT+2RXHp9++vdd^|pi?@jyv)A8TN zCQdqEk4%mpd#&p>=(>}jaJGOf-}PrHB`njAvX!24J|*&rLD!;HH06BpkDOK~INuWI;k=8|>H_D7z8qG^apz~^I7m9W zuT3j|-1#M!YGsc)e-ibTo;%bE9(6t%-9hT?_&Jdd?zm%hS$$)#G^SDo*Px{rD5 zRng)#yV)V<53*zL3U(h`+1eB0+^adgJ}uv*^D9O0rTJjpu8a(5q;AhIE@LBg>^62H z*w|=BFJ`!rHb}SdEmw9dPtr<#Ir#EVp5{{ZYl{Nq*#~2`mw~Ap%kyW_-r#@SDuqH~ zTWa02+pSWBFMB|@Q%7e*ZXoNGsJDCmW~s;Q-D#6-_PsD|(y&k3(avT4NN$DiG=+J@ z9?71%-YwNl$Rv8Jd567cHRIh;!!3Kx-QU$GeK0JQyE9elsX4nmRT`Gce{rJp+@-Sr zi+|Vz?U=v~o1k3Y)ed^T3aS!fDc;CtC%gA^qoQY^!Oc`5E>kt9S*aJo*zQ^Pb)`%#Xd zm1)@YF1}MN7rmfy?$WuL*=cApR8lM=rqDu#H1cO{1Vd=TZJQ?ov+$zpv;qW+A#S|_}oOv zg^G*_Y}isUF#Kshse?{*;GYycB19p?b`@bI7gl*d$Phz>0==M9FA%`w3&gHy5Z_@2 zQ3ph}5a?lg%bh5@kf4Uvhbo*2c$;@V6vIQVO=E$O2Db*%V#gerMbbKl49_qkcVZUx zW6vY}#Hs{{@|sLG$g2v2;m7!7A$`yE^tcOc(MHu$pmVDSbAGoG8<#}>YlETtCB-raSgzKsOuZu>E$ScBY?)BZ? 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zq5PW@1W1togkoW9ifZ};zr{)3|Bonc|GQzwiw2Ji z)qw%_-z(aGHOarFX*>9j81A> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var wbemFlagReturnImmediately = 0x10; - var wbemFlagForwardOnly = 0x20; - var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); - var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); - var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); - var NOC = 0; - var NOLP = 0; - var TPM = 0; - - var cpuInfos = new Enumerator(processor); - for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { - var cpuInfo = cpuInfos.item(); - NOC += cpuInfo.NumberOfCores; - NOLP += cpuInfo.NumberOfLogicalProcessors; - } - var csInfos = new Enumerator(computerSystem); - for(;!csInfos.atEnd(); csInfos.moveNext()) { - var csInfo = csInfos.item(); - TPM += csInfo.TotalPhysicalMemory; - } - - var ISEHOSTCORE = NOLP - var ISEMEMTOTAL = TPM - - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/ISEWrap.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/ISEWrap.sh deleted file mode 100644 index f679f2e..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/ISEWrap.sh +++ /dev/null @@ -1,67 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -# - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! -if [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi -ISE_USER=$USER - -ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) -ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) - -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 ] -then - /bin/touch .$ISE_STEP.end.rst -else - /bin/touch .$ISE_STEP.error.rst -fi - -exit $RETVAL - diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/gen_run.xml deleted file mode 100644 index f75d651..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/gen_run.xml +++ /dev/null @@ -1,164 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/htr.txt b/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/htr.txt deleted file mode 100644 index 447ab02..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -REM -REM Vivado(TM) -REM htr.txt: a Vivado-generated description of how-to-repeat the -REM the basic steps of a run. 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:32:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:32:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:3533903437 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/rundef.js b/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/rundef.js deleted file mode 100644 index deb94fd..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/rundef.js +++ /dev/null @@ -1,40 +0,0 @@ -// -// Vivado(TM) -// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.1/bin;"; -} else { - PathVal = "D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.1/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; -eval( EAInclude(ISEJScriptLib) ); - - -// pre-commands: -ISETouchFile( "init_design", "begin" ); -ISEStep( "vivado", - "-log AckChecker_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source AckChecker_wrapper.tcl -notrace" ); - - - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/runme.bat b/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/runme.bat deleted file mode 100644 index 1760626..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/runme.bat +++ /dev/null @@ -1,10 +0,0 @@ -@echo off - -rem Vivado (TM) -rem runme.bat: a Vivado-generated Script -rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/runme.sh deleted file mode 100644 index 086f734..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/runme.sh +++ /dev/null @@ -1,47 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# runme.sh: a Vivado-generated Runs Script for UNIX -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# - -echo "This script was generated under a different operating system." -echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" -exit - -if [ -z "$PATH" ]; then - PATH=D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.1/bin -else - PATH=D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.1/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH= -else - LD_LIBRARY_PATH=:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1' -cd "$HD_PWD" - -HD_LOG=runme.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrap.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -# pre-commands: -/bin/touch .init_design.begin.rst -EAStep vivado -log AckChecker_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source AckChecker_wrapper.tcl -notrace - - diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/vivado.jou deleted file mode 100644 index ef1b8bf..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1 (64-bit) -# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 -# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:10:55 2020 -# Process ID: 19328 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1 -# Command line: vivado.exe -log AckChecker_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source AckChecker_wrapper.tcl -notrace -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/AckChecker_wrapper.vdi -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source AckChecker_wrapper.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/vivado.pb deleted file mode 100644 index b155e40..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/impl_1/vivado.pb +++ /dev/null @@ -1,4 +0,0 @@ - - - -End Record \ No newline at end of file diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.vivado.begin.rst index 5ec84c4..13d565e 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git 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zU)`Ne939_#7gvxei(6`nc=QSzdg$3Jj*BgY;xRMx+Nl-NXhXOJVj;FX5|$_CN5&)q zNcMPF-42Lo1@qw6^nC1YJ*G4q@1suE-q@uIKfQgI&wE%JUdy@UC-7Ix^O6DL)6^gk zfTy9MQtaDXA)8KQ5pyOqiA{HevPsVr&Bm61LG!ypi}8 z^FcYmOBoqaFtjKv*E6ug#6xeqFD8|;5f(*H=1(e>8MuRZQ?OoR4=~@zv=7R0?`}B8 zUK7+4Ba!EzSG_qGI^ylZyJ?_Q#d1)NQIve1NN?n4_=I-dZF`@nxU$1JOg`mQm4R}^ z$P*`pe_P;GPG6&>whjaz)`X`sb6W8dlKqaFXk?{BVXZV@A@Y&bN1G>P%09dfTE9XQ zV)nFF)XD1$ua-;jDcdB7lh0dYv-VDzFs!hGsEbe%d6xWvh{V`ucXeG^mVp$H{(QSQ zuz6+l6nt3uPHC)02j1BPb-q#IE9~3zFEh6P;U%A5UN{xhdmtp{FNen9FDodSrI&nz zhDY^nD2sBMsC6p_m03mas2lH}*PnN9I2sZ9%ARq|>>kz8KB4@-_J-e7ER21(H#9r| zK>Yu+H_+U+M&pZ3uNZpgU+uAa37pw*4VNUY2xC<>hK^80j^8v#_8GQw&rkMJT-G79 z*UfAjHX>;UZatb-;yz9D#%LSxYvrB7Ar369tD?Oc(!%&3q5P1ByN8giqMar&g{Y9ahUG0szKPt5v2^6=VQ=1^fTvx zJvbWa%G_>`P}0OAB(Ts)AEHL>Ce!O~+i07E>@8!zHCoZ+F$8!FFK_cwJ>5!a~d6fOiGD?T8nT*#-(1NG_M{euGU<XABcA4k9q9=s`81zkUc(%@$y=1j zvD8^!Y|caCI9&r5$XI}Cn;3 z1L_~cnXUPc3>Tn@qs2cdOl)G|&hKv~|GzZ(_i$M5|0Biye@<+RnCOXi2mm1azT^DY zl>B=%bN`v)VgFAx{^`yCCH`+UjC`T~gMI(YxBnCKPbcx;7$yJz59ZxvsC - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/runme.log new file mode 100644 index 0000000..36f0bcf --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/runme.log @@ -0,0 +1,571 @@ + +*** Running vivado + with args -log AckChecker_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_wrapper.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_wrapper.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +Command: synth_design -top AckChecker_wrapper -part xc7z020clg484-3 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020' +INFO: [Device 21-403] Loading part xc7z020clg484-3 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 13212 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 839.273 ; gain = 178.031 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'AckChecker_wrapper' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/hdl/AckChecker_wrapper.vhd:39] +INFO: [Synth 8-3491] module 'AckChecker' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:14' bound to instance 'AckChecker_i' of component 'AckChecker' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/hdl/AckChecker_wrapper.vhd:65] +INFO: [Synth 8-638] synthesizing module 'AckChecker' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:43] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_0_0' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_0_0_stub.vhdl:5' bound to instance 'AckCheckerConcept_0' of component 'AckChecker_AckCheckerConcept_0_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:987] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_0_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_0_0_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_0_1' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_0_1_stub.vhdl:5' bound to instance 'AckCheckerConcept_1' of component 'AckChecker_AckCheckerConcept_0_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1000] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_0_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_0_1_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_6_1' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_6_1_stub.vhdl:5' bound to instance 'AckCheckerConcept_10' of component 'AckChecker_AckCheckerConcept_6_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1013] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_6_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_6_1_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_7_1' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_7_1_stub.vhdl:5' bound to instance 'AckCheckerConcept_11' of component 'AckChecker_AckCheckerConcept_7_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1026] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_7_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_7_1_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_4_2' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_4_2_stub.vhdl:5' bound to instance 'AckCheckerConcept_12' of component 'AckChecker_AckCheckerConcept_4_2' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1039] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_4_2' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_4_2_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_5_2' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_5_2_stub.vhdl:5' bound to instance 'AckCheckerConcept_13' of component 'AckChecker_AckCheckerConcept_5_2' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1052] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_5_2' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_5_2_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_6_2' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_6_2_stub.vhdl:5' bound to instance 'AckCheckerConcept_14' of component 'AckChecker_AckCheckerConcept_6_2' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1065] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_6_2' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_6_2_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_7_2' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_7_2_stub.vhdl:5' bound to instance 'AckCheckerConcept_15' of component 'AckChecker_AckCheckerConcept_7_2' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1078] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_7_2' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_7_2_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_12_0' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_12_0_stub.vhdl:5' bound to instance 'AckCheckerConcept_16' of component 'AckChecker_AckCheckerConcept_12_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1091] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_12_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_12_0_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_13_0' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_13_0_stub.vhdl:5' bound to instance 'AckCheckerConcept_17' of component 'AckChecker_AckCheckerConcept_13_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1104] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_13_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_13_0_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_14_0' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_14_0_stub.vhdl:5' bound to instance 'AckCheckerConcept_18' of component 'AckChecker_AckCheckerConcept_14_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1117] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_14_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_14_0_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_15_0' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_15_0_stub.vhdl:5' bound to instance 'AckCheckerConcept_19' of component 'AckChecker_AckCheckerConcept_15_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1130] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_15_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_15_0_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_0_2' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_0_2_stub.vhdl:5' bound to instance 'AckCheckerConcept_2' of component 'AckChecker_AckCheckerConcept_0_2' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1143] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_0_2' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_0_2_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_12_1' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_12_1_stub.vhdl:5' bound to instance 'AckCheckerConcept_20' of component 'AckChecker_AckCheckerConcept_12_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1156] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_12_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_12_1_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_13_1' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_13_1_stub.vhdl:5' bound to instance 'AckCheckerConcept_21' of component 'AckChecker_AckCheckerConcept_13_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1169] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_13_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_13_1_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_14_1' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_14_1_stub.vhdl:5' bound to instance 'AckCheckerConcept_22' of component 'AckChecker_AckCheckerConcept_14_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1182] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_14_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_14_1_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_15_1' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_15_1_stub.vhdl:5' bound to instance 'AckCheckerConcept_23' of component 'AckChecker_AckCheckerConcept_15_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1195] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_15_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_15_1_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_12_2' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_12_2_stub.vhdl:5' bound to instance 'AckCheckerConcept_24' of component 'AckChecker_AckCheckerConcept_12_2' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1208] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_12_2' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_12_2_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_13_2' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_13_2_stub.vhdl:5' bound to instance 'AckCheckerConcept_25' of component 'AckChecker_AckCheckerConcept_13_2' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1221] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_13_2' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_13_2_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_14_2' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_14_2_stub.vhdl:5' bound to instance 'AckCheckerConcept_26' of component 'AckChecker_AckCheckerConcept_14_2' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1234] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_14_2' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_14_2_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_15_2' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_15_2_stub.vhdl:5' bound to instance 'AckCheckerConcept_27' of component 'AckChecker_AckCheckerConcept_15_2' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1247] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_15_2' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_15_2_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_12_3' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_12_3_stub.vhdl:5' bound to instance 'AckCheckerConcept_28' of component 'AckChecker_AckCheckerConcept_12_3' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1260] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_12_3' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_12_3_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_13_3' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_13_3_stub.vhdl:5' bound to instance 'AckCheckerConcept_29' of component 'AckChecker_AckCheckerConcept_13_3' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1273] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_13_3' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_13_3_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_0_3' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_0_3_stub.vhdl:5' bound to instance 'AckCheckerConcept_3' of component 'AckChecker_AckCheckerConcept_0_3' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1286] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_0_3' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_0_3_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_14_3' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_14_3_stub.vhdl:5' bound to instance 'AckCheckerConcept_30' of component 'AckChecker_AckCheckerConcept_14_3' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1299] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_14_3' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_14_3_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_15_3' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_15_3_stub.vhdl:5' bound to instance 'AckCheckerConcept_31' of component 'AckChecker_AckCheckerConcept_15_3' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1312] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_15_3' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_15_3_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_0_4' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_0_4_stub.vhdl:5' bound to instance 'AckCheckerConcept_4' of component 'AckChecker_AckCheckerConcept_0_4' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1325] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_0_4' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_0_4_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_1_0' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_1_0_stub.vhdl:5' bound to instance 'AckCheckerConcept_5' of component 'AckChecker_AckCheckerConcept_1_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1338] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_1_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_1_0_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_2_0' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_2_0_stub.vhdl:5' bound to instance 'AckCheckerConcept_6' of component 'AckChecker_AckCheckerConcept_2_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1351] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_2_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_2_0_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_3_0' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_3_0_stub.vhdl:5' bound to instance 'AckCheckerConcept_7' of component 'AckChecker_AckCheckerConcept_3_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1364] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_3_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_3_0_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_4_1' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_4_1_stub.vhdl:5' bound to instance 'AckCheckerConcept_8' of component 'AckChecker_AckCheckerConcept_4_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1377] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_4_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_4_1_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_AckCheckerConcept_5_1' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_5_1_stub.vhdl:5' bound to instance 'AckCheckerConcept_9' of component 'AckChecker_AckCheckerConcept_5_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1390] +INFO: [Synth 8-638] synthesizing module 'AckChecker_AckCheckerConcept_5_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_AckCheckerConcept_5_1_stub.vhdl:21] +INFO: [Synth 8-3491] module 'AckChecker_BusBlock16IN_0_0' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_BusBlock16IN_0_0_stub.vhdl:5' bound to instance 'BusBlock16IN_0' of component 'AckChecker_BusBlock16IN_0_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1403] +INFO: [Synth 8-638] synthesizing module 'AckChecker_BusBlock16IN_0_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_BusBlock16IN_0_0_stub.vhdl:28] +INFO: [Synth 8-3491] module 'AckChecker_BusBlock16IN_0_1' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_BusBlock16IN_0_1_stub.vhdl:5' bound to instance 'BusBlock16IN_1' of component 'AckChecker_BusBlock16IN_0_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1423] +INFO: [Synth 8-638] synthesizing module 'AckChecker_BusBlock16IN_0_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_BusBlock16IN_0_1_stub.vhdl:28] +INFO: [Synth 8-3491] module 'AckChecker_BusBlock16IN_0_2' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_BusBlock16IN_0_2_stub.vhdl:5' bound to instance 'BusBlock16IN_2' of component 'AckChecker_BusBlock16IN_0_2' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1443] +INFO: [Synth 8-638] synthesizing module 'AckChecker_BusBlock16IN_0_2' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_BusBlock16IN_0_2_stub.vhdl:28] +INFO: [Synth 8-3491] module 'AckChecker_BusBlock16IN_2_0' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_BusBlock16IN_2_0_stub.vhdl:5' bound to instance 'BusBlock16IN_3' of component 'AckChecker_BusBlock16IN_2_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1463] +INFO: [Synth 8-638] synthesizing module 'AckChecker_BusBlock16IN_2_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_BusBlock16IN_2_0_stub.vhdl:28] +INFO: [Synth 8-3491] module 'AckChecker_BusBlock16IN_1_0' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_BusBlock16IN_1_0_stub.vhdl:5' bound to instance 'BusBlock16IN_4' of component 'AckChecker_BusBlock16IN_1_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1483] +INFO: [Synth 8-638] synthesizing module 'AckChecker_BusBlock16IN_1_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_BusBlock16IN_1_0_stub.vhdl:28] +INFO: [Synth 8-3491] module 'AckChecker_BusBlock16IN_4_0' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_BusBlock16IN_4_0_stub.vhdl:5' bound to instance 'BusBlock16IN_5' of component 'AckChecker_BusBlock16IN_4_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1503] +INFO: [Synth 8-638] synthesizing module 'AckChecker_BusBlock16IN_4_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_BusBlock16IN_4_0_stub.vhdl:28] +INFO: [Synth 8-3491] module 'AckChecker_BusBlock16IN_4_1' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_BusBlock16IN_4_1_stub.vhdl:5' bound to instance 'BusBlock16IN_6' of component 'AckChecker_BusBlock16IN_4_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1523] +INFO: [Synth 8-638] synthesizing module 'AckChecker_BusBlock16IN_4_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_BusBlock16IN_4_1_stub.vhdl:28] +INFO: [Synth 8-3491] module 'AckChecker_BusBlock16IN_6_0' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_BusBlock16IN_6_0_stub.vhdl:5' bound to instance 'BusBlock16IN_7' of component 'AckChecker_BusBlock16IN_6_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1543] +INFO: [Synth 8-638] synthesizing module 'AckChecker_BusBlock16IN_6_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_BusBlock16IN_6_0_stub.vhdl:28] +INFO: [Synth 8-3491] module 'AckChecker_BusBlock16OUT_0_0' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_BusBlock16OUT_0_0_stub.vhdl:5' bound to instance 'BusBlock16OUT_0' of component 'AckChecker_BusBlock16OUT_0_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1563] +INFO: [Synth 8-638] synthesizing module 'AckChecker_BusBlock16OUT_0_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_BusBlock16OUT_0_0_stub.vhdl:29] +INFO: [Synth 8-3491] module 'AckChecker_BusBlock16OUT_0_1' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_BusBlock16OUT_0_1_stub.vhdl:5' bound to instance 'BusBlock16OUT_1' of component 'AckChecker_BusBlock16OUT_0_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1584] +INFO: [Synth 8-638] synthesizing module 'AckChecker_BusBlock16OUT_0_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_BusBlock16OUT_0_1_stub.vhdl:29] +INFO: [Synth 8-3491] module 'AckChecker_BusBlock16OUT_0_2' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_BusBlock16OUT_0_2_stub.vhdl:5' bound to instance 'BusBlock16OUT_2' of component 'AckChecker_BusBlock16OUT_0_2' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1605] +INFO: [Synth 8-638] synthesizing module 'AckChecker_BusBlock16OUT_0_2' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_BusBlock16OUT_0_2_stub.vhdl:29] +INFO: [Synth 8-3491] module 'AckChecker_BusBlock16OUT_1_0' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_BusBlock16OUT_1_0_stub.vhdl:5' bound to instance 'BusBlock16OUT_3' of component 'AckChecker_BusBlock16OUT_1_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:1626] +INFO: [Synth 8-638] synthesizing module 'AckChecker_BusBlock16OUT_1_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/.Xil/Vivado-10520-STAS-W10/realtime/AckChecker_BusBlock16OUT_1_0_stub.vhdl:29] +INFO: [Synth 8-256] done synthesizing module 'AckChecker' (1#1) [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/synth/AckChecker.vhd:43] +INFO: [Synth 8-256] done synthesizing module 'AckChecker_wrapper' (2#1) [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/hdl/AckChecker_wrapper.vhd:39] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 905.359 ; gain = 244.117 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 905.359 ; gain = 244.117 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 905.359 ; gain = 244.117 +--------------------------------------------------------------------------------- +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_0' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_0' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_1' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_1' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_2' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_2' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_3' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_3' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_4/AckChecker_AckCheckerConcept_0_4/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_4' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_4/AckChecker_AckCheckerConcept_0_4/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_4' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_1_0/AckChecker_AckCheckerConcept_1_0/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_5' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_1_0/AckChecker_AckCheckerConcept_1_0/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_5' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_2_0/AckChecker_AckCheckerConcept_2_0/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_6' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_2_0/AckChecker_AckCheckerConcept_2_0/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_6' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_3_0/AckChecker_AckCheckerConcept_3_0/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_7' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_3_0/AckChecker_AckCheckerConcept_3_0/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_7' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_1/AckChecker_AckCheckerConcept_4_1/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_8' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_1/AckChecker_AckCheckerConcept_4_1/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_8' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_9' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_9' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_10' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_10' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_11' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_11' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_12' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_12' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_2/AckChecker_AckCheckerConcept_5_2/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_13' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_2/AckChecker_AckCheckerConcept_5_2/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_13' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_14' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_14' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_15' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_15' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_16' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_16' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_0/AckChecker_AckCheckerConcept_13_0/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_17' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_0/AckChecker_AckCheckerConcept_13_0/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_17' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_18' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_18' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_0/AckChecker_AckCheckerConcept_15_0/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_19' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_0/AckChecker_AckCheckerConcept_15_0/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_19' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_20' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_20' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_21' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_21' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_22' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_22' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_23' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_23' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_24' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_24' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_2/AckChecker_AckCheckerConcept_13_2/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_25' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_2/AckChecker_AckCheckerConcept_13_2/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_25' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_26' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_26' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_27' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_27' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_3/AckChecker_AckCheckerConcept_12_3/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_28' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_3/AckChecker_AckCheckerConcept_12_3/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_28' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_3/AckChecker_AckCheckerConcept_13_3/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_29' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_3/AckChecker_AckCheckerConcept_13_3/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_29' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_30' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_30' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_31' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_0_0_in_context.xdc] for cell 'AckChecker_i/AckCheckerConcept_31' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_in_context.xdc] for cell 'AckChecker_i/BusBlock16OUT_0' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_in_context.xdc] for cell 'AckChecker_i/BusBlock16OUT_0' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_0_in_context.xdc] for cell 'AckChecker_i/BusBlock16OUT_1' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_0_in_context.xdc] for cell 'AckChecker_i/BusBlock16OUT_1' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_0_in_context.xdc] for cell 'AckChecker_i/BusBlock16OUT_2' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_0_in_context.xdc] for cell 'AckChecker_i/BusBlock16OUT_2' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_0_0_in_context.xdc] for cell 'AckChecker_i/BusBlock16OUT_3' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_0_0_in_context.xdc] for cell 'AckChecker_i/BusBlock16OUT_3' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_0/AckChecker_BusBlock16IN_0_0/AckChecker_BusBlock16IN_0_0_in_context.xdc] for cell 'AckChecker_i/BusBlock16IN_0' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_0/AckChecker_BusBlock16IN_0_0/AckChecker_BusBlock16IN_0_0_in_context.xdc] for cell 'AckChecker_i/BusBlock16IN_0' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_0_in_context.xdc] for cell 'AckChecker_i/BusBlock16IN_1' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_0_in_context.xdc] for cell 'AckChecker_i/BusBlock16IN_1' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_2/AckChecker_BusBlock16IN_0_2/AckChecker_BusBlock16IN_0_0_in_context.xdc] for cell 'AckChecker_i/BusBlock16IN_2' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_2/AckChecker_BusBlock16IN_0_2/AckChecker_BusBlock16IN_0_0_in_context.xdc] for cell 'AckChecker_i/BusBlock16IN_2' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_0_0_in_context.xdc] for cell 'AckChecker_i/BusBlock16IN_3' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_0_0_in_context.xdc] for cell 'AckChecker_i/BusBlock16IN_3' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_1_0/AckChecker_BusBlock16IN_1_0/AckChecker_BusBlock16IN_0_0_in_context.xdc] for cell 'AckChecker_i/BusBlock16IN_4' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_1_0/AckChecker_BusBlock16IN_1_0/AckChecker_BusBlock16IN_0_0_in_context.xdc] for cell 'AckChecker_i/BusBlock16IN_4' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_0_0_in_context.xdc] for cell 'AckChecker_i/BusBlock16IN_5' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_0_0_in_context.xdc] for cell 'AckChecker_i/BusBlock16IN_5' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_1/AckChecker_BusBlock16IN_4_1/AckChecker_BusBlock16IN_0_0_in_context.xdc] for cell 'AckChecker_i/BusBlock16IN_6' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_1/AckChecker_BusBlock16IN_4_1/AckChecker_BusBlock16IN_0_0_in_context.xdc] for cell 'AckChecker_i/BusBlock16IN_6' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_6_0/AckChecker_BusBlock16IN_6_0/AckChecker_BusBlock16IN_0_0_in_context.xdc] for cell 'AckChecker_i/BusBlock16IN_7' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_6_0/AckChecker_BusBlock16IN_6_0/AckChecker_BusBlock16IN_0_0_in_context.xdc] for cell 'AckChecker_i/BusBlock16IN_7' +Parsing XDC File [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/dont_touch.xdc] +Finished Parsing XDC File [D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1024.801 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1024.801 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1024.801 ; gain = 363.559 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z020clg484-3 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1024.801 ; gain = 363.559 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property DONT_TOUCH = true for AckChecker_i. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_0. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_1. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_2. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_3. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_4. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_5. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_6. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_7. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_8. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_9. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_10. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_11. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_12. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_13. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_14. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_15. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_16. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_17. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_18. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_19. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_20. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_21. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_22. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_23. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_24. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_25. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_26. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_27. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_28. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_29. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_30. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/AckCheckerConcept_31. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/BusBlock16OUT_0. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/BusBlock16OUT_1. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/BusBlock16OUT_2. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/BusBlock16OUT_3. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/BusBlock16IN_0. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/BusBlock16IN_1. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/BusBlock16IN_2. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/BusBlock16IN_3. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/BusBlock16IN_4. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/BusBlock16IN_5. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/BusBlock16IN_6. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for AckChecker_i/BusBlock16IN_7. (constraint file auto generated constraint, line ). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1024.801 ; gain = 363.559 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1024.801 ; gain = 363.559 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 220 (col length:60) +BRAMs: 280 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1024.801 ; gain = 363.559 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 1024.801 ; gain = 363.559 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 1024.801 ; gain = 363.559 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 1024.801 ; gain = 363.559 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 1024.801 ; gain = 363.559 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 1024.801 ; gain = 363.559 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 1024.801 ; gain = 363.559 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 1024.801 ; gain = 363.559 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 1024.801 ; gain = 363.559 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 1024.801 ; gain = 363.559 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++------+----------------------------------+----------+ +| |BlackBox name |Instances | ++------+----------------------------------+----------+ +|1 |AckChecker_AckCheckerConcept_0_0 | 1| +|2 |AckChecker_AckCheckerConcept_0_1 | 1| +|3 |AckChecker_AckCheckerConcept_6_1 | 1| +|4 |AckChecker_AckCheckerConcept_7_1 | 1| +|5 |AckChecker_AckCheckerConcept_4_2 | 1| +|6 |AckChecker_AckCheckerConcept_5_2 | 1| +|7 |AckChecker_AckCheckerConcept_6_2 | 1| +|8 |AckChecker_AckCheckerConcept_7_2 | 1| +|9 |AckChecker_AckCheckerConcept_12_0 | 1| +|10 |AckChecker_AckCheckerConcept_13_0 | 1| +|11 |AckChecker_AckCheckerConcept_14_0 | 1| +|12 |AckChecker_AckCheckerConcept_15_0 | 1| +|13 |AckChecker_AckCheckerConcept_0_2 | 1| +|14 |AckChecker_AckCheckerConcept_12_1 | 1| +|15 |AckChecker_AckCheckerConcept_13_1 | 1| +|16 |AckChecker_AckCheckerConcept_14_1 | 1| +|17 |AckChecker_AckCheckerConcept_15_1 | 1| +|18 |AckChecker_AckCheckerConcept_12_2 | 1| +|19 |AckChecker_AckCheckerConcept_13_2 | 1| +|20 |AckChecker_AckCheckerConcept_14_2 | 1| +|21 |AckChecker_AckCheckerConcept_15_2 | 1| +|22 |AckChecker_AckCheckerConcept_12_3 | 1| +|23 |AckChecker_AckCheckerConcept_13_3 | 1| +|24 |AckChecker_AckCheckerConcept_0_3 | 1| +|25 |AckChecker_AckCheckerConcept_14_3 | 1| +|26 |AckChecker_AckCheckerConcept_15_3 | 1| +|27 |AckChecker_AckCheckerConcept_0_4 | 1| +|28 |AckChecker_AckCheckerConcept_1_0 | 1| +|29 |AckChecker_AckCheckerConcept_2_0 | 1| +|30 |AckChecker_AckCheckerConcept_3_0 | 1| +|31 |AckChecker_AckCheckerConcept_4_1 | 1| +|32 |AckChecker_AckCheckerConcept_5_1 | 1| +|33 |AckChecker_BusBlock16IN_0_0 | 1| +|34 |AckChecker_BusBlock16IN_0_1 | 1| +|35 |AckChecker_BusBlock16IN_0_2 | 1| +|36 |AckChecker_BusBlock16IN_2_0 | 1| +|37 |AckChecker_BusBlock16IN_1_0 | 1| +|38 |AckChecker_BusBlock16IN_4_0 | 1| +|39 |AckChecker_BusBlock16IN_4_1 | 1| +|40 |AckChecker_BusBlock16IN_6_0 | 1| +|41 |AckChecker_BusBlock16OUT_0_0 | 1| +|42 |AckChecker_BusBlock16OUT_0_1 | 1| +|43 |AckChecker_BusBlock16OUT_0_2 | 1| +|44 |AckChecker_BusBlock16OUT_1_0 | 1| ++------+----------------------------------+----------+ + +Report Cell Usage: ++------+------------------------------------------+------+ +| |Cell |Count | ++------+------------------------------------------+------+ +|1 |AckChecker_AckCheckerConcept_0_0_bbox_0 | 1| +|2 |AckChecker_AckCheckerConcept_0_1_bbox_1 | 1| +|3 |AckChecker_AckCheckerConcept_0_2_bbox_12 | 1| +|4 |AckChecker_AckCheckerConcept_0_3_bbox_23 | 1| +|5 |AckChecker_AckCheckerConcept_0_4_bbox_26 | 1| +|6 |AckChecker_AckCheckerConcept_12_0_bbox_8 | 1| +|7 |AckChecker_AckCheckerConcept_12_1_bbox_13 | 1| +|8 |AckChecker_AckCheckerConcept_12_2_bbox_17 | 1| +|9 |AckChecker_AckCheckerConcept_12_3_bbox_21 | 1| +|10 |AckChecker_AckCheckerConcept_13_0_bbox_9 | 1| +|11 |AckChecker_AckCheckerConcept_13_1_bbox_14 | 1| +|12 |AckChecker_AckCheckerConcept_13_2_bbox_18 | 1| +|13 |AckChecker_AckCheckerConcept_13_3_bbox_22 | 1| +|14 |AckChecker_AckCheckerConcept_14_0_bbox_10 | 1| +|15 |AckChecker_AckCheckerConcept_14_1_bbox_15 | 1| +|16 |AckChecker_AckCheckerConcept_14_2_bbox_19 | 1| +|17 |AckChecker_AckCheckerConcept_14_3_bbox_24 | 1| +|18 |AckChecker_AckCheckerConcept_15_0_bbox_11 | 1| +|19 |AckChecker_AckCheckerConcept_15_1_bbox_16 | 1| +|20 |AckChecker_AckCheckerConcept_15_2_bbox_20 | 1| +|21 |AckChecker_AckCheckerConcept_15_3_bbox_25 | 1| +|22 |AckChecker_AckCheckerConcept_1_0_bbox_27 | 1| +|23 |AckChecker_AckCheckerConcept_2_0_bbox_28 | 1| +|24 |AckChecker_AckCheckerConcept_3_0_bbox_29 | 1| +|25 |AckChecker_AckCheckerConcept_4_1_bbox_30 | 1| +|26 |AckChecker_AckCheckerConcept_4_2_bbox_4 | 1| +|27 |AckChecker_AckCheckerConcept_5_1_bbox_31 | 1| +|28 |AckChecker_AckCheckerConcept_5_2_bbox_5 | 1| +|29 |AckChecker_AckCheckerConcept_6_1_bbox_2 | 1| +|30 |AckChecker_AckCheckerConcept_6_2_bbox_6 | 1| +|31 |AckChecker_AckCheckerConcept_7_1_bbox_3 | 1| +|32 |AckChecker_AckCheckerConcept_7_2_bbox_7 | 1| +|33 |AckChecker_BusBlock16IN_0_0_bbox_32 | 1| +|34 |AckChecker_BusBlock16IN_0_1_bbox_33 | 1| +|35 |AckChecker_BusBlock16IN_0_2_bbox_34 | 1| +|36 |AckChecker_BusBlock16IN_1_0_bbox_36 | 1| +|37 |AckChecker_BusBlock16IN_2_0_bbox_35 | 1| +|38 |AckChecker_BusBlock16IN_4_0_bbox_37 | 1| +|39 |AckChecker_BusBlock16IN_4_1_bbox_38 | 1| +|40 |AckChecker_BusBlock16IN_6_0_bbox_39 | 1| +|41 |AckChecker_BusBlock16OUT_0_0_bbox_40 | 1| +|42 |AckChecker_BusBlock16OUT_0_1_bbox_41 | 1| +|43 |AckChecker_BusBlock16OUT_0_2_bbox_42 | 1| +|44 |AckChecker_BusBlock16OUT_1_0_bbox_43 | 1| +|45 |IBUF | 227| +|46 |OBUF | 64| ++------+------------------------------------------+------+ + +Report Instance Areas: ++------+---------------+-----------+------+ +| |Instance |Module |Cells | ++------+---------------+-----------+------+ +|1 |top | | 547| +|2 | AckChecker_i |AckChecker | 256| ++------+---------------+-----------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 1024.801 ; gain = 363.559 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:19 . Memory (MB): peak = 1024.801 ; gain = 244.117 +Synthesis Optimization Complete : Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 1024.801 ; gain = 363.559 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1025.113 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +105 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:29 . Memory (MB): peak = 1025.113 ; gain = 636.340 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1025.113 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/AckChecker_wrapper.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file AckChecker_wrapper_utilization_synth.rpt -pb AckChecker_wrapper_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:38:19 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/runme.sh index 012ff2c..148d3fa 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/vivado.jou index 10cd141..2cfda93 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:10:07 2020 -# Process ID: 23472 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1 +# Start of session at: Wed May 3 11:37:44 2023 +# Process ID: 10520 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1 # Command line: vivado.exe -log AckChecker_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_wrapper.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/AckChecker_wrapper.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/AckChecker_wrapper.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_wrapper.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/synth_1/vivado.pb index 54ce9ba50c30e9f23700b23a74e5643026af2633..5315dbdaf1a7eed3f633ded0e52b3c426296636e 100644 GIT binary patch literal 113025 zcmeHQYm6MpUB6j-*IdO)R(Tv3-{n$whtKxj?My%BwR2n&@7iZCXP=Gjd*J98dS}|Z zeV(13bobc1){+MYL7?Px5h4i*$_G%8AR#Z1A`}n;gb*JQpO7MfgphzwKoAJT2makX zJ<~N^)73rQyIs?}E6elfn*LY)>i7HC>)%!ABj~Xk>K#Khx3umiUcZhFwWph!r5l=R zqQ&`B$0WJDbfTpj>ZaPgy&$eE!xvi*_2zfx-zhw_IEU^bd_`BTwr($bM#XUoRQ*Bw#xgQj33*XU=QK{T4;caCXZ>TMO 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b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/component.xml index 3b9dc65..a839929 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/component.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/component.xml @@ -45,7 +45,7 @@ viewChecksum - 27c989f9 + 4ecd37b6 @@ -70,7 +70,7 @@ viewChecksum - 02d5dd00 + 6ec1c393 @@ -84,7 +84,7 @@ viewChecksum - f64a5dae + abd1bb30 @@ -832,7 +832,7 @@ hdl/AckChecker_wrapper.vhd vhdlSource - CHECKSUM_8962cb65 + CHECKSUM_28fbc17d @@ -1311,7 +1311,7 @@ xgui/AckChecker_wrapper_v1_0.tcl tclSource - CHECKSUM_f64a5dae + CHECKSUM_abd1bb30 XGUI_VERSION_2 @@ -1326,17 +1326,19 @@ - zynq + zynq + artix7 /UserIP AckChecker_wrapper_v1_0 + level_0 package_project S7DNRJ https://ssevendenergy.com - 3 - 2020-04-29T11:13:04Z + 4 + 2023-05-03T08:41:24Z d:/projects/ip/ackcheckerblock/ackcheckerblock.srcs/sources_1/bd/ackchecker d:/projects/ip/ackcheckerblock/ackcheckerblock.srcs/sources_1/bd/ackchecker @@ -1362,12 +1364,23 @@ d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/ackchecker d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/ackchecker d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/ackchecker + d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/ackchecker + d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/ackchecker + d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/ackchecker + d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/ackchecker + d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/ackchecker + d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/ackchecker + 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a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0.xml index 632ba4f..c433e09 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:35:55 UTC 2023 + + + outputProductCRC + 9:84c219ec + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_0_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_0_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_0_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_sim_netlist.v new file mode 100644 index 0000000..86aa5d7 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_sim_netlist.v @@ -0,0 +1,765 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim +// D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_0_0 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_0_0_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule + +(* ORIG_REF_NAME = "AckCheckerConcept" *) +module AckChecker_AckCheckerConcept_0_0_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl new file mode 100644 index 0000000..84f4563 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl @@ -0,0 +1,929 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim +-- D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_0_0_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of AckChecker_AckCheckerConcept_0_0_AckCheckerConcept : entity is "AckCheckerConcept"; +end AckChecker_AckCheckerConcept_0_0_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_0_0_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_0_0 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_0_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_0_0 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_0_0 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_0_0 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_0_0 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_0_0; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_0_0 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_0_0_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.v new file mode 100644 index 0000000..5ffa8f7 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub +// D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_0_0(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.vhdl new file mode 100644 index 0000000..c03a01c --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub +-- D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_0/AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_0_0 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_0_0; + +architecture stub of AckChecker_AckCheckerConcept_0_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1.dcp new file mode 100644 index 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100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:36:05 UTC 2023 + + + outputProductCRC + 9:13f31fed + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_0_1.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_0_1_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_0_1_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_0_1_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_0_1_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.v new file mode 100644 index 0000000..65e31c6 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_0_1 -prefix +// AckChecker_AckCheckerConcept_0_1_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_0_1_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_0_1 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_0_1_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.vhdl new file mode 100644 index 0000000..8877ce7 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_0_1 -prefix +-- AckChecker_AckCheckerConcept_0_1_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_0_1_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_0_1_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_0_1_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_0_1 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_0_1 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_0_1 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_0_1 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_0_1 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_0_1 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_0_1; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_0_1 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_0_1_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.v new file mode 100644 index 0000000..7ef864c --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_0_1 -prefix +// AckChecker_AckCheckerConcept_0_1_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_0_1(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.vhdl new file mode 100644 index 0000000..d875baf --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_1/AckChecker_AckCheckerConcept_0_1_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_0_1 -prefix +-- AckChecker_AckCheckerConcept_0_1_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_0_1 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_0_1; + +architecture stub of AckChecker_AckCheckerConcept_0_1 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2.dcp new file mode 100644 index 0000000000000000000000000000000000000000..918e0337f524af8fffdb6e06a827f1a0272a3fcb GIT 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a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:36:06 UTC 2023 + + + outputProductCRC + 9:71d113af + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_0_2.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_0_2_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_0_2_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_0_2_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_0_2_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_sim_netlist.v new file mode 100644 index 0000000..bf404d0 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_0_2 -prefix +// AckChecker_AckCheckerConcept_0_2_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_0_2_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_0_2 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_0_2_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_sim_netlist.vhdl new file mode 100644 index 0000000..a655314 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_0_2 -prefix +-- AckChecker_AckCheckerConcept_0_2_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_0_2_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_0_2_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_0_2_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_0_2 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_0_2 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_0_2 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_0_2 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_0_2 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_0_2 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_0_2; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_0_2 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_0_2_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_stub.v new file mode 100644 index 0000000..55a9d92 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_0_2 -prefix +// AckChecker_AckCheckerConcept_0_2_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_0_2(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_stub.vhdl new file mode 100644 index 0000000..55b57cb --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_2/AckChecker_AckCheckerConcept_0_2_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_0_2 -prefix +-- AckChecker_AckCheckerConcept_0_2_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_0_2 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_0_2; + +architecture stub of AckChecker_AckCheckerConcept_0_2 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3.dcp new file mode 100644 index 0000000000000000000000000000000000000000..5ba13ccc866c9d05ec17e5287f20d9f1204b7345 GIT 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a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3.xci +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3.xci @@ -26,7 +26,6 @@ MIXED -3 - TRUE TRUE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3.xml index e239486..1e94596 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:36:06 UTC 2023 + + + outputProductCRC + 9:e6e015ae + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_0_3.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_0_3_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_0_3_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_0_3_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_0_3_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_sim_netlist.v new file mode 100644 index 0000000..7ac3075 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_0_3 -prefix +// AckChecker_AckCheckerConcept_0_3_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_0_3_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_0_3 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_0_3_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_sim_netlist.vhdl new file mode 100644 index 0000000..893cd35 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_0_3 -prefix +-- AckChecker_AckCheckerConcept_0_3_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_0_3_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_0_3_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_0_3_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_0_3 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_0_3 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_0_3 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_0_3 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_0_3 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_0_3 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_0_3; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_0_3 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_0_3_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_stub.v new file mode 100644 index 0000000..c843be2 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_0_3 -prefix +// AckChecker_AckCheckerConcept_0_3_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_0_3(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_stub.vhdl new file mode 100644 index 0000000..29f68fe --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_0_3 -prefix +-- AckChecker_AckCheckerConcept_0_3_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_0_3 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_0_3; + +architecture stub of AckChecker_AckCheckerConcept_0_3 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_4/AckChecker_AckCheckerConcept_0_4.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_4/AckChecker_AckCheckerConcept_0_4.dcp new file mode 100644 index 0000000000000000000000000000000000000000..b80c688390fdcd5856c4e9f20430231a942b717e GIT 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b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_4/AckChecker_AckCheckerConcept_0_4.xci index d9ac7af..a7da09e 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_4/AckChecker_AckCheckerConcept_0_4.xci +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_4/AckChecker_AckCheckerConcept_0_4.xci @@ -26,7 +26,6 @@ MIXED -3 - TRUE TRUE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_4/AckChecker_AckCheckerConcept_0_4.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_4/AckChecker_AckCheckerConcept_0_4.xml index c70260e..0a9e5e2 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_4/AckChecker_AckCheckerConcept_0_4.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_4/AckChecker_AckCheckerConcept_0_4.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:36:06 UTC 2023 + + + outputProductCRC + 9:b5950b2b + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_0_4.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_0_4_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_0_4_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_0_4_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_0_4_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_4/AckChecker_AckCheckerConcept_0_4_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_4/AckChecker_AckCheckerConcept_0_4_sim_netlist.v new file mode 100644 index 0000000..7fdbe6a --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_4/AckChecker_AckCheckerConcept_0_4_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_0_4 -prefix +// AckChecker_AckCheckerConcept_0_4_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_0_4_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_0_4 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_0_4_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_4/AckChecker_AckCheckerConcept_0_4_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_4/AckChecker_AckCheckerConcept_0_4_sim_netlist.vhdl new file mode 100644 index 0000000..35bc372 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_4/AckChecker_AckCheckerConcept_0_4_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_0_4 -prefix +-- AckChecker_AckCheckerConcept_0_4_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_0_4_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_0_4_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_0_4_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_0_4 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_0_4 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_0_4 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_0_4 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_0_4 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_0_4 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_0_4; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_0_4 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_0_4_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_4/AckChecker_AckCheckerConcept_0_4_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_4/AckChecker_AckCheckerConcept_0_4_stub.v new file mode 100644 index 0000000..6ea0351 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_4/AckChecker_AckCheckerConcept_0_4_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_0_4 -prefix +// AckChecker_AckCheckerConcept_0_4_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_0_4(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_4/AckChecker_AckCheckerConcept_0_4_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_4/AckChecker_AckCheckerConcept_0_4_stub.vhdl new file mode 100644 index 0000000..4bbf480 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_4/AckChecker_AckCheckerConcept_0_4_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_0_4 -prefix +-- AckChecker_AckCheckerConcept_0_4_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_0_4 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_0_4; + +architecture stub of AckChecker_AckCheckerConcept_0_4 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0.dcp new file mode 100644 index 0000000000000000000000000000000000000000..6de44a32ddaef2336e2eedb50e9e76fa516b6b26 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zXSQ4l;au_8Iks3atLK?#>Y7#4R0Pc|Cau^ks}|^`Fx9cWsL|6gIB3hkX<}0%r6*-d0-n;j`SbgRD#psD4kJUHiWX@!cWV2w_c08z7%{qZZJYu7pJqWs$G&*$xlk~?a)y??WM zwxfTA>QmOb%Gnb+zEqZ29A1(&AyY9qgM+m;EXU|xwbG$qyKis>UGTfg%Ud?#+RcS3 z-P<0-E#H;5Jm=i2(_C3yo-B3k$hP)3 z@oQpUtPSBUnIxWdWv+B(-H(n(DzU3B1>W7l{&!89z)X-IMPF+UG8Y84 zHEskhw;_72 literal 0 HcmV?d00001 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0.xci b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0.xci index 3d7eb53..3abc873 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0.xci +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0.xci @@ -26,7 +26,6 @@ MIXED -3 - TRUE TRUE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0.xml index eef0f74..52d8259 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:36:37 UTC 2023 + + + outputProductCRC + 9:8d238fb3 + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_12_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_12_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_12_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_12_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_12_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_sim_netlist.v new file mode 100644 index 0000000..0d3edb8 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_12_0 -prefix +// AckChecker_AckCheckerConcept_12_0_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_12_0_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_12_0 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_12_0_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_sim_netlist.vhdl new file mode 100644 index 0000000..3669a8d --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_12_0 -prefix +-- AckChecker_AckCheckerConcept_12_0_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_12_0_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_12_0_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_12_0_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_12_0 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_12_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_12_0 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_12_0 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_12_0 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_12_0 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_12_0; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_12_0 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_12_0_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_stub.v new file mode 100644 index 0000000..ceda061 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_12_0 -prefix +// AckChecker_AckCheckerConcept_12_0_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_12_0(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_stub.vhdl new file mode 100644 index 0000000..3c20aac --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_12_0 -prefix +-- AckChecker_AckCheckerConcept_12_0_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_12_0 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_12_0; + +architecture stub of AckChecker_AckCheckerConcept_12_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1.dcp new file mode 100644 index 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zDP*^X&(-e7IjyyCyT0F!<2bxF_sU<<{|yqEQT$4`?j8Ihz}<6e!{v6*XsN4j4)7WU zXSQ4l;au_8Iks3atLK?#>Y7#4R0Pc|Cau^ks}|^`Fx9cWsL|6gIB3hkX<}0%rVV|uHUq26K6fw3JzKo8_{dN1vmBxc-xo$o-4HnS!^e2b&lk5#W>(p`IPQwv zCCIT!cwXkUiX6#g@7?=etiJO7V)Vq2$Lbq$JVO~G*(6xC{SK&Avrgmn`F(HRo!eqJ z4zNVDSxOq*)@WHd+2dH>oXt&*pIxu}e)xNBpOwHz=V@s%CwA%m|9N{u&z`Dn@87JR z?dTt&`_%Q{Co|<|FFwC8nDsbH;j+`S1P;r}FcZlW5;lU%{>J85>Ul1|#mgJ!G3!mh zLs#t?;(E6?y?Gy}bdPzflFsirOy%z;PIl6#qaK%_<#==lFLJQU$Xiw;ZZeto^^vmZ_3I&C$22;52(Fcw{l(dlVgceNAuRq6E|P; z)H3hi%&MxtKfj!FUu+-X%?KLL&WPolW`igdtX%I(#mLSGN*!p&KbJ5qDgUkhi zZH*g&%Pk0c9=!4#-AwdVD MIXED -3 - TRUE TRUE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1.xml index 3c09870..546665b 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:36:56 UTC 2023 + + + outputProductCRC + 9:29ef96ab + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_12_1.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_12_1_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_12_1_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_12_1_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_12_1_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_sim_netlist.v new file mode 100644 index 0000000..9c4f545 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_12_1 -prefix +// AckChecker_AckCheckerConcept_12_1_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_12_1_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_12_1 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_12_1_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_sim_netlist.vhdl new file mode 100644 index 0000000..241f52b --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_12_1 -prefix +-- AckChecker_AckCheckerConcept_12_1_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_12_1_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_12_1_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_12_1_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_12_1 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_12_1 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_12_1 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_12_1 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_12_1 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_12_1 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_12_1; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_12_1 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_12_1_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_stub.v new file mode 100644 index 0000000..b6c9926 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_12_1 -prefix +// AckChecker_AckCheckerConcept_12_1_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_12_1(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_stub.vhdl new file mode 100644 index 0000000..5c0116d --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_12_1 -prefix +-- AckChecker_AckCheckerConcept_12_1_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_12_1 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_12_1; + +architecture stub of AckChecker_AckCheckerConcept_12_1 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2.dcp new file mode 100644 index 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a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:37:05 UTC 2023 + + + outputProductCRC + 9:1fcabbc2 + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_12_2.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_12_2_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_12_2_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_12_2_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_12_2_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_sim_netlist.v new file mode 100644 index 0000000..d99cdbf --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_12_2 -prefix +// AckChecker_AckCheckerConcept_12_2_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_12_2_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_12_2 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_12_2_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_sim_netlist.vhdl new file mode 100644 index 0000000..232a6f2 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_12_2 -prefix +-- AckChecker_AckCheckerConcept_12_2_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_12_2_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_12_2_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_12_2_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_12_2 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_12_2 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_12_2 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_12_2 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_12_2 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_12_2 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_12_2; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_12_2 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_12_2_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_stub.v new file mode 100644 index 0000000..f59029a --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_12_2 -prefix +// AckChecker_AckCheckerConcept_12_2_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_12_2(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_stub.vhdl new file mode 100644 index 0000000..5cc2c30 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_12_2 -prefix +-- AckChecker_AckCheckerConcept_12_2_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_12_2 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_12_2; + +architecture stub of AckChecker_AckCheckerConcept_12_2 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_3/AckChecker_AckCheckerConcept_12_3.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_3/AckChecker_AckCheckerConcept_12_3.dcp new file mode 100644 index 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b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_3/AckChecker_AckCheckerConcept_12_3.xci index bf35d4a..427f598 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_3/AckChecker_AckCheckerConcept_12_3.xci +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_3/AckChecker_AckCheckerConcept_12_3.xci @@ -26,7 +26,6 @@ MIXED -3 - TRUE TRUE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_3/AckChecker_AckCheckerConcept_12_3.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_3/AckChecker_AckCheckerConcept_12_3.xml index aec88cf..fb0ea1a 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_3/AckChecker_AckCheckerConcept_12_3.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_3/AckChecker_AckCheckerConcept_12_3.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:37:15 UTC 2023 + + + outputProductCRC + 9:bb06a2da + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_12_3.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_12_3_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_12_3_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_12_3_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_12_3_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_3/AckChecker_AckCheckerConcept_12_3_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_3/AckChecker_AckCheckerConcept_12_3_sim_netlist.v new file mode 100644 index 0000000..da9c99a --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_3/AckChecker_AckCheckerConcept_12_3_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_12_3 -prefix +// AckChecker_AckCheckerConcept_12_3_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_12_3_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_12_3 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_12_3_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_3/AckChecker_AckCheckerConcept_12_3_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_3/AckChecker_AckCheckerConcept_12_3_sim_netlist.vhdl new file mode 100644 index 0000000..43bb57d --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_3/AckChecker_AckCheckerConcept_12_3_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_12_3 -prefix +-- AckChecker_AckCheckerConcept_12_3_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_12_3_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_12_3_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_12_3_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_12_3 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_12_3 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_12_3 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_12_3 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_12_3 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_12_3 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_12_3; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_12_3 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_12_3_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_3/AckChecker_AckCheckerConcept_12_3_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_3/AckChecker_AckCheckerConcept_12_3_stub.v new file mode 100644 index 0000000..620bcad --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_3/AckChecker_AckCheckerConcept_12_3_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_12_3 -prefix +// AckChecker_AckCheckerConcept_12_3_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_12_3(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_3/AckChecker_AckCheckerConcept_12_3_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_3/AckChecker_AckCheckerConcept_12_3_stub.vhdl new file mode 100644 index 0000000..27bd8f7 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_3/AckChecker_AckCheckerConcept_12_3_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_12_3 -prefix +-- AckChecker_AckCheckerConcept_12_3_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_12_3 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_12_3; + +architecture stub of AckChecker_AckCheckerConcept_12_3 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_0/AckChecker_AckCheckerConcept_13_0.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_0/AckChecker_AckCheckerConcept_13_0.dcp new file mode 100644 index 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zDP*^X&(-e7IjyyCyT0F!<2bxF_sU<<{|yqEQT$4`?j8Ihz}<6e!{v6*XsN4j4)7WU zXSQ4l;au_8Iks3atLK?#>Y7#4R0Pc|Cau^ks}|^`Fx9cWsL|6gIB3hkX<}0%r;f^5H7o)BoP79-7h^B{;3tuW@(3=h8=46;CgoW|!DisaEi@{4v|RRX$UC=07dB zd^jsaLM6ZS|7X4nj&Tih3_R{QFIt)MzTK^5Q4PnEa@TwBIkbg}V%a{wtILtPc4b@p zoBD{I7ot~7z1X2~bw#!Lr#~M!k9zJ3TDsV6i~HY2X#)Avtiz|SF<-vsSk{BTY`^{s z{|*VsVrzG>EOWm)A?|_8sQ{S5DRgj4eqmT&`m_&m;f>dVq!b+ z)Et5)g0?B38;QQH0AwTxY-^MeC&EbJCIfU6(O0yCOoKS`vjj0F!q&H=n~T2I9AqvC zY-`*ITy8CKTp&--#ELw0 z1JPRzAj2R|yyrmJK(saly5Z8w1P~9 egakvwVHXBiK^x%B$_A3)2EtZgRe8n@!~*~aOsvEJ literal 0 HcmV?d00001 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_0/AckChecker_AckCheckerConcept_13_0.xci b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_0/AckChecker_AckCheckerConcept_13_0.xci index 28f11be..0d9691f 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_0/AckChecker_AckCheckerConcept_13_0.xci +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_0/AckChecker_AckCheckerConcept_13_0.xci @@ -26,7 +26,6 @@ MIXED -3 - TRUE TRUE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_0/AckChecker_AckCheckerConcept_13_0.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_0/AckChecker_AckCheckerConcept_13_0.xml index dc4bfdd..e74380d 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_0/AckChecker_AckCheckerConcept_13_0.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_0/AckChecker_AckCheckerConcept_13_0.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:36:47 UTC 2023 + + + outputProductCRC + 9:6b531be6 + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_13_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_13_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_13_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_13_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_13_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_0/AckChecker_AckCheckerConcept_13_0_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_0/AckChecker_AckCheckerConcept_13_0_sim_netlist.v new file mode 100644 index 0000000..3891512 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_0/AckChecker_AckCheckerConcept_13_0_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_13_0 -prefix +// AckChecker_AckCheckerConcept_13_0_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_13_0_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_13_0 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_13_0_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_0/AckChecker_AckCheckerConcept_13_0_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_0/AckChecker_AckCheckerConcept_13_0_sim_netlist.vhdl new file mode 100644 index 0000000..48b02ae --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_0/AckChecker_AckCheckerConcept_13_0_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_13_0 -prefix +-- AckChecker_AckCheckerConcept_13_0_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_13_0_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_13_0_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_13_0_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_13_0 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_13_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_13_0 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_13_0 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_13_0 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_13_0 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_13_0; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_13_0 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_13_0_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_0/AckChecker_AckCheckerConcept_13_0_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_0/AckChecker_AckCheckerConcept_13_0_stub.v new file mode 100644 index 0000000..abeaa5b --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_0/AckChecker_AckCheckerConcept_13_0_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_13_0 -prefix +// AckChecker_AckCheckerConcept_13_0_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_13_0(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_0/AckChecker_AckCheckerConcept_13_0_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_0/AckChecker_AckCheckerConcept_13_0_stub.vhdl new file mode 100644 index 0000000..9f81590 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_0/AckChecker_AckCheckerConcept_13_0_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_13_0 -prefix +-- AckChecker_AckCheckerConcept_13_0_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_13_0 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_13_0; + +architecture stub of AckChecker_AckCheckerConcept_13_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1.dcp new file mode 100644 index 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b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1.xci index ac2b173..bf0e73f 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1.xci +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1.xci @@ -26,7 +26,6 @@ MIXED -3 - TRUE TRUE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1.xml index df730e6..9ae60ac 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:36:58 UTC 2023 + + + outputProductCRC + 9:cf9f02fe + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_13_1.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_13_1_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_13_1_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_13_1_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_13_1_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_sim_netlist.v new file mode 100644 index 0000000..6962c71 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_13_1 -prefix +// AckChecker_AckCheckerConcept_13_1_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_13_1_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_13_1 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_13_1_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_sim_netlist.vhdl new file mode 100644 index 0000000..6405810 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_13_1 -prefix +-- AckChecker_AckCheckerConcept_13_1_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_13_1_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_13_1_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_13_1_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_13_1 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_13_1 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_13_1 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_13_1 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_13_1 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_13_1 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_13_1; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_13_1 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_13_1_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_stub.v new file mode 100644 index 0000000..6de9b40 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_13_1 -prefix +// AckChecker_AckCheckerConcept_13_1_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_13_1(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_stub.vhdl new file mode 100644 index 0000000..3c9b0fc --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_13_1 -prefix +-- AckChecker_AckCheckerConcept_13_1_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_13_1 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_13_1; + +architecture stub of AckChecker_AckCheckerConcept_13_1 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_2/AckChecker_AckCheckerConcept_13_2.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_2/AckChecker_AckCheckerConcept_13_2.dcp new file mode 100644 index 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zDP*^X&(-e7IjyyCyT0F!<2bxF_sU<<{|yqEQT$4`?j8Ihz}<6e!{v6*XsN4j4)7WU zXSQ4l;au_8Iks3atLK?#>Y7#4R0Pc|Cau^ks}|^`Fx9cWsL|6gIB3hkX<}0%rYaaZm1-zsie!Sw8cW98Z)79P4BoO=|4INZ zuo6y?d{%Pc%_4zieoB(nMJKt~^ulA!4_>$a{mkQtdE~4@#n-$3{N_Jw^y$^necSVo zHP71+b?Wq=ugPv_E=!{f&KNq35~$Ra;w_$E-II z4^y>gh_Ab~>CO8%r85haa$F<6S+c&X^VJev&lf4T^$Tb48RN$8{nF+I;i-#K{^;yK zy(K#+al)SKf6rSxuvan`9a1Rd?_4%%ue_9C*C)jZ_e3lAE3ff5Q7U<6_wS9F5y7|R zHvLb0>Xg4WYr*41A&cMLJ@NUlx`_Hquc>`f7v;Wo&vM)o`7S1O)4e&Hq*gb6mwxfz z|4neLL&Wq@uX`jU2#X%I(#mLSGN*aCNSbI})@gUkhi zZH*g&>n#X+9=!A%-AwdlD1j*+3H9K-dbbE6=)tcmP*EqBj5l literal 0 HcmV?d00001 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_2/AckChecker_AckCheckerConcept_13_2.xci b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_2/AckChecker_AckCheckerConcept_13_2.xci index ea40085..247da3e 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_2/AckChecker_AckCheckerConcept_13_2.xci +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_2/AckChecker_AckCheckerConcept_13_2.xci @@ -26,7 +26,6 @@ MIXED -3 - TRUE TRUE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_2/AckChecker_AckCheckerConcept_13_2.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_2/AckChecker_AckCheckerConcept_13_2.xml index c8e46ce..c01857c 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_2/AckChecker_AckCheckerConcept_13_2.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_2/AckChecker_AckCheckerConcept_13_2.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:37:07 UTC 2023 + + + outputProductCRC + 9:f9ba2f97 + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_13_2.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_13_2_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_13_2_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_13_2_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_13_2_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_2/AckChecker_AckCheckerConcept_13_2_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_2/AckChecker_AckCheckerConcept_13_2_sim_netlist.v new file mode 100644 index 0000000..07ffcc0 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_2/AckChecker_AckCheckerConcept_13_2_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_13_2 -prefix +// AckChecker_AckCheckerConcept_13_2_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_13_2_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_13_2 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_13_2_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_2/AckChecker_AckCheckerConcept_13_2_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_2/AckChecker_AckCheckerConcept_13_2_sim_netlist.vhdl new file mode 100644 index 0000000..8b94223 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_2/AckChecker_AckCheckerConcept_13_2_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_13_2 -prefix +-- AckChecker_AckCheckerConcept_13_2_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_13_2_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_13_2_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_13_2_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_13_2 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_13_2 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_13_2 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_13_2 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_13_2 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_13_2 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_13_2; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_13_2 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_13_2_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_2/AckChecker_AckCheckerConcept_13_2_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_2/AckChecker_AckCheckerConcept_13_2_stub.v new file mode 100644 index 0000000..6a3607c --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_2/AckChecker_AckCheckerConcept_13_2_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_13_2 -prefix +// AckChecker_AckCheckerConcept_13_2_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_13_2(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_2/AckChecker_AckCheckerConcept_13_2_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_2/AckChecker_AckCheckerConcept_13_2_stub.vhdl new file mode 100644 index 0000000..a88a4d8 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_2/AckChecker_AckCheckerConcept_13_2_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_13_2 -prefix +-- AckChecker_AckCheckerConcept_13_2_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_13_2 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_13_2; + +architecture stub of AckChecker_AckCheckerConcept_13_2 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_3/AckChecker_AckCheckerConcept_13_3.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_3/AckChecker_AckCheckerConcept_13_3.dcp new file mode 100644 index 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b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_3/AckChecker_AckCheckerConcept_13_3.xci index b910e57..bd30691 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_3/AckChecker_AckCheckerConcept_13_3.xci +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_3/AckChecker_AckCheckerConcept_13_3.xci @@ -26,7 +26,6 @@ MIXED -3 - TRUE TRUE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_3/AckChecker_AckCheckerConcept_13_3.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_3/AckChecker_AckCheckerConcept_13_3.xml index 1b121ca..41e7c6c 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_3/AckChecker_AckCheckerConcept_13_3.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_3/AckChecker_AckCheckerConcept_13_3.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:37:17 UTC 2023 + + + outputProductCRC + 9:5d76368f + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_13_3.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_13_3_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_13_3_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_13_3_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_13_3_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_3/AckChecker_AckCheckerConcept_13_3_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_3/AckChecker_AckCheckerConcept_13_3_sim_netlist.v new file mode 100644 index 0000000..e18af0e --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_3/AckChecker_AckCheckerConcept_13_3_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_13_3 -prefix +// AckChecker_AckCheckerConcept_13_3_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_13_3_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_13_3 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_13_3_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_3/AckChecker_AckCheckerConcept_13_3_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_3/AckChecker_AckCheckerConcept_13_3_sim_netlist.vhdl new file mode 100644 index 0000000..0e7ab32 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_3/AckChecker_AckCheckerConcept_13_3_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_13_3 -prefix +-- AckChecker_AckCheckerConcept_13_3_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_13_3_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_13_3_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_13_3_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_13_3 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_13_3 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_13_3 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_13_3 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_13_3 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_13_3 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_13_3; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_13_3 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_13_3_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_3/AckChecker_AckCheckerConcept_13_3_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_3/AckChecker_AckCheckerConcept_13_3_stub.v new file mode 100644 index 0000000..c9d95d7 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_3/AckChecker_AckCheckerConcept_13_3_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_13_3 -prefix +// AckChecker_AckCheckerConcept_13_3_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_13_3(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_3/AckChecker_AckCheckerConcept_13_3_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_3/AckChecker_AckCheckerConcept_13_3_stub.vhdl new file mode 100644 index 0000000..23613e8 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_3/AckChecker_AckCheckerConcept_13_3_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_13_3 -prefix +-- AckChecker_AckCheckerConcept_13_3_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_13_3 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_13_3; + +architecture stub of AckChecker_AckCheckerConcept_13_3 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0.dcp new file mode 100644 index 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a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0.xci b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0.xci index 5fb3ed3..5572321 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0.xci +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0.xci @@ -26,7 +26,6 @@ MIXED -3 - TRUE TRUE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0.xml index ffa99d9..027b233 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:36:47 UTC 2023 + + + outputProductCRC + 9:b593fc8e + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_14_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_14_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_14_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_14_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_14_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_sim_netlist.v new file mode 100644 index 0000000..a9ac21f --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_14_0 -prefix +// AckChecker_AckCheckerConcept_14_0_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_14_0_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_14_0 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_14_0_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_sim_netlist.vhdl new file mode 100644 index 0000000..62bf6aa --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_14_0 -prefix +-- AckChecker_AckCheckerConcept_14_0_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_14_0_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_14_0_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_14_0_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_14_0 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_14_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_14_0 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_14_0 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_14_0 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_14_0 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_14_0; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_14_0 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_14_0_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_stub.v new file mode 100644 index 0000000..1f56782 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_14_0 -prefix +// AckChecker_AckCheckerConcept_14_0_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_14_0(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_stub.vhdl new file mode 100644 index 0000000..78961ed --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_14_0 -prefix +-- AckChecker_AckCheckerConcept_14_0_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_14_0 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_14_0; + +architecture stub of AckChecker_AckCheckerConcept_14_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1.dcp new file mode 100644 index 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b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1.xci @@ -26,7 +26,6 @@ MIXED -3 - TRUE TRUE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1.xml index 362f0c8..fdc6485 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:36:58 UTC 2023 + + + outputProductCRC + 9:115fe596 + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_14_1.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_14_1_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_14_1_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_14_1_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_14_1_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_sim_netlist.v new file mode 100644 index 0000000..ad4a6f6 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_14_1 -prefix +// AckChecker_AckCheckerConcept_14_1_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_14_1_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_14_1 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_14_1_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_sim_netlist.vhdl new file mode 100644 index 0000000..18682f3 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_14_1 -prefix +-- AckChecker_AckCheckerConcept_14_1_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_14_1_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_14_1_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_14_1_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_14_1 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_14_1 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_14_1 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_14_1 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_14_1 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_14_1 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_14_1; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_14_1 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_14_1_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_stub.v new file mode 100644 index 0000000..7eb38d5 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_14_1 -prefix +// AckChecker_AckCheckerConcept_14_1_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_14_1(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_stub.vhdl new file mode 100644 index 0000000..1b9a4f7 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_14_1 -prefix +-- AckChecker_AckCheckerConcept_14_1_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_14_1 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_14_1; + +architecture stub of AckChecker_AckCheckerConcept_14_1 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2.dcp new file mode 100644 index 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a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2.xml index a1e5cfa..a9d13ac 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:37:07 UTC 2023 + + + outputProductCRC + 9:277ac8ff + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_14_2.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_14_2_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_14_2_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_14_2_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_14_2_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_sim_netlist.v new file mode 100644 index 0000000..0b6e9c4 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_14_2 -prefix +// AckChecker_AckCheckerConcept_14_2_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_14_2_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_14_2 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_14_2_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_sim_netlist.vhdl new file mode 100644 index 0000000..7197304 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_14_2 -prefix +-- AckChecker_AckCheckerConcept_14_2_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_14_2_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_14_2_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_14_2_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_14_2 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_14_2 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_14_2 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_14_2 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_14_2 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_14_2 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_14_2; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_14_2 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_14_2_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_stub.v new file mode 100644 index 0000000..d366a5a --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_14_2 -prefix +// AckChecker_AckCheckerConcept_14_2_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_14_2(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_stub.vhdl new file mode 100644 index 0000000..9b5aa25 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_14_2 -prefix +-- AckChecker_AckCheckerConcept_14_2_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_14_2 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_14_2; + +architecture stub of AckChecker_AckCheckerConcept_14_2 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3.dcp new file mode 100644 index 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b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3.xml index d2e7c4b..c6889d5 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:37:17 UTC 2023 + + + outputProductCRC + 9:83b6d1e7 + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_14_3.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_14_3_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_14_3_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_14_3_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_14_3_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_sim_netlist.v new file mode 100644 index 0000000..88eea6c --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_14_3 -prefix +// AckChecker_AckCheckerConcept_14_3_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_14_3_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_14_3 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_14_3_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_sim_netlist.vhdl new file mode 100644 index 0000000..60dab8b --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_14_3 -prefix +-- AckChecker_AckCheckerConcept_14_3_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_14_3_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_14_3_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_14_3_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_14_3 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_14_3 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_14_3 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_14_3 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_14_3 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_14_3 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_14_3; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_14_3 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_14_3_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_stub.v new file mode 100644 index 0000000..8b9e77d --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_14_3 -prefix +// AckChecker_AckCheckerConcept_14_3_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_14_3(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_stub.vhdl new file mode 100644 index 0000000..8840125 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_14_3 -prefix +-- AckChecker_AckCheckerConcept_14_3_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_14_3 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_14_3; + +architecture stub of AckChecker_AckCheckerConcept_14_3 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_0/AckChecker_AckCheckerConcept_15_0.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_0/AckChecker_AckCheckerConcept_15_0.dcp new file mode 100644 index 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a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_0/AckChecker_AckCheckerConcept_15_0.xci b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_0/AckChecker_AckCheckerConcept_15_0.xci index b2b6862..90bc4fa 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_0/AckChecker_AckCheckerConcept_15_0.xci +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_0/AckChecker_AckCheckerConcept_15_0.xci @@ -26,7 +26,6 @@ MIXED -3 - TRUE TRUE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_0/AckChecker_AckCheckerConcept_15_0.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_0/AckChecker_AckCheckerConcept_15_0.xml index 95b392f..2a772a2 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_0/AckChecker_AckCheckerConcept_15_0.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_0/AckChecker_AckCheckerConcept_15_0.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:36:47 UTC 2023 + + + outputProductCRC + 9:53e368db + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_15_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_15_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_15_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_15_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_15_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_0/AckChecker_AckCheckerConcept_15_0_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_0/AckChecker_AckCheckerConcept_15_0_sim_netlist.v new file mode 100644 index 0000000..e0cdc16 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_0/AckChecker_AckCheckerConcept_15_0_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_15_0 -prefix +// AckChecker_AckCheckerConcept_15_0_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_15_0_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_15_0 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_15_0_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_0/AckChecker_AckCheckerConcept_15_0_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_0/AckChecker_AckCheckerConcept_15_0_sim_netlist.vhdl new file mode 100644 index 0000000..7f55b04 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_0/AckChecker_AckCheckerConcept_15_0_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_15_0 -prefix +-- AckChecker_AckCheckerConcept_15_0_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_15_0_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_15_0_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_15_0_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_15_0 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_15_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_15_0 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_15_0 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_15_0 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_15_0 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_15_0; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_15_0 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_15_0_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_0/AckChecker_AckCheckerConcept_15_0_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_0/AckChecker_AckCheckerConcept_15_0_stub.v new file mode 100644 index 0000000..0d0d805 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_0/AckChecker_AckCheckerConcept_15_0_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_15_0 -prefix +// AckChecker_AckCheckerConcept_15_0_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_15_0(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_0/AckChecker_AckCheckerConcept_15_0_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_0/AckChecker_AckCheckerConcept_15_0_stub.vhdl new file mode 100644 index 0000000..5e4ca0b --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_0/AckChecker_AckCheckerConcept_15_0_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_15_0 -prefix +-- AckChecker_AckCheckerConcept_15_0_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_15_0 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_15_0; + +architecture stub of AckChecker_AckCheckerConcept_15_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1.dcp new file mode 100644 index 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a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:36:58 UTC 2023 + + + outputProductCRC + 9:f72f71c3 + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_15_1.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_15_1_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_15_1_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_15_1_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_15_1_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_sim_netlist.v new file mode 100644 index 0000000..8b7571a --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_15_1 -prefix +// AckChecker_AckCheckerConcept_15_1_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_15_1_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_15_1 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_15_1_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_sim_netlist.vhdl new file mode 100644 index 0000000..dee0f6c --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_15_1 -prefix +-- AckChecker_AckCheckerConcept_15_1_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_15_1_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_15_1_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_15_1_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_15_1 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_15_1 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_15_1 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_15_1 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_15_1 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_15_1 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_15_1; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_15_1 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_15_1_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_stub.v new file mode 100644 index 0000000..31ae4ad --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_15_1 -prefix +// AckChecker_AckCheckerConcept_15_1_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_15_1(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_stub.vhdl new file mode 100644 index 0000000..0e217d3 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_15_1 -prefix +-- AckChecker_AckCheckerConcept_15_1_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_15_1 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_15_1; + +architecture stub of AckChecker_AckCheckerConcept_15_1 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2.dcp new file mode 100644 index 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zDP*^X&(-e7IjyyCyT0F!<2bxF_sU<<{|yqEQT$4`?j8Ihz}<6e!{v6*XsN4j4)7WU zXSQ4l;au_8Iks3atLK?#>Y7#4R0Pc|Cau^ks}|^`Fx9cWsL|6gIB3hkX<}0%ryo#SK}nVVAYjE3cNy%9rI1ByCp71sG1q6E&cq(xoi1b9k)$s>4oq9p4<8C z)aCYfA&th*coR#O&D^!n_KbV*^Nx$&XE{U@zAucFx*>4thmY}=pD%8g%>3ENeK=?H zmn4B_>Nc0xe7s?FY+70E#qdah1K*Was`)3}oV1Ez6ORE`*qjF6e{4F^GrsM$-ML+N zLt$`&&2t{yf3ZXb#UQTRo}W5 z9~Oz8>7SMx`K?@E@L7Q1Rwb?9bC}BO)uwjEyYn2?tvw?0Ip)Em_s6#GURxAsR5$5< z>MhZg1|Iic{d@j4mi?Dv$s&WV-&QW0v{znAi0h(&$9t|T?>V%CiXz!Qe|vY#WKCx- z|IPgomFxBgnO-OiToqUz_lEtVvd^WQm0s<=8T`K@&niUfZ=0tTncr90d-cHXt z<)O3o!T#&*=imF8@kKhon-N%a;y%s>6#c-Y!LY3n#6p~CgZpqBbQ95cCVe(;$xgEJ2Kkum$eu=Ath)2bl{3 z+Zs0l*IN+uJb39jx|!(9RzT)K+`1dM^Mjz7z(p+RCZewa0htH_+Zqo5SI84Iu_6!M zK=ft<$S{Z#?>P`Q5Umk`Za8|Kk1)K>kqE;fbqu MIXED -3 - TRUE TRUE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2.xml index 4b2564b..af3055d 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:37:08 UTC 2023 + + + outputProductCRC + 9:c10a5caa + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_15_2.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_15_2_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_15_2_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_15_2_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_15_2_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_sim_netlist.v new file mode 100644 index 0000000..7d347ea --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_15_2 -prefix +// AckChecker_AckCheckerConcept_15_2_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_15_2_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_15_2 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_15_2_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_sim_netlist.vhdl new file mode 100644 index 0000000..712fe67 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_15_2 -prefix +-- AckChecker_AckCheckerConcept_15_2_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_15_2_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_15_2_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_15_2_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_15_2 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_15_2 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_15_2 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_15_2 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_15_2 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_15_2 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_15_2; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_15_2 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_15_2_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_stub.v new file mode 100644 index 0000000..01babb8 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_15_2 -prefix +// AckChecker_AckCheckerConcept_15_2_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_15_2(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_stub.vhdl new file mode 100644 index 0000000..89069e4 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_15_2 -prefix +-- AckChecker_AckCheckerConcept_15_2_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_15_2 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_15_2; + +architecture stub of AckChecker_AckCheckerConcept_15_2 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3.dcp new file mode 100644 index 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zDP*^X&(-e7IjyyCyT0F!<2bxF_sU<<{|yqEQT$4`?j8Ihz}<6e!{v6*XsN4j4)7WU zXSQ4l;au_8Iks3atLK?#>Y7#4R0Pc|Cau^ks}|^`Fx9cWsL|6gIB3hkX<}0%rtL&RAfuf|D!!Ky2T6nKRiJLa2McS~H3P&G4BTl)EnbJy~>I&PcN(hJ}HJ-74O zsmtx}LK=;q@g|lmo4ISD?HTvr=N%Wl&vJ++d|wzTbwl9P4usIFB|JZb-XMEdhyK}ql zhQi=X)-FbY0N7&|BW{sEzoJAG-_R=B7Yuq<=GI-%~xky8Oqg5igcy>ps*syl}F*OOK2Z?Ar}>u8)%YT+Z*SCxf_ zqxuRypTBbX_4(!Hc2a-Y0=yZ4MJMj#Y(UWuOd1T^8bK_?i8ilG?fjd74nh9LQf^H)E8W50)Ah50R0C0soK@%(T z&<#XyHh>I+IPsnXVFS?`5$J}a*ZBy;>l}$N98$-i8;V|4AqG!XZ literal 0 HcmV?d00001 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3.xci b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3.xci index e531f1c..5c663f6 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3.xci +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3.xci @@ -26,7 +26,6 @@ MIXED -3 - TRUE TRUE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3.xml index 4365e4e..c59c0b8 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:37:18 UTC 2023 + + + outputProductCRC + 9:65c645b2 + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_15_3.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_15_3_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_15_3_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_15_3_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_15_3_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_sim_netlist.v new file mode 100644 index 0000000..79430d6 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_15_3 -prefix +// AckChecker_AckCheckerConcept_15_3_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_15_3_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_15_3 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_15_3_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_sim_netlist.vhdl new file mode 100644 index 0000000..d32bb09 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_15_3 -prefix +-- AckChecker_AckCheckerConcept_15_3_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_15_3_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_15_3_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_15_3_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_15_3 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_15_3 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_15_3 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_15_3 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_15_3 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_15_3 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_15_3; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_15_3 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_15_3_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_stub.v new file mode 100644 index 0000000..b2e2ed2 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_15_3 -prefix +// AckChecker_AckCheckerConcept_15_3_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_15_3(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_stub.vhdl new file mode 100644 index 0000000..4974d90 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_15_3 -prefix +-- AckChecker_AckCheckerConcept_15_3_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_15_3 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_15_3; + +architecture stub of AckChecker_AckCheckerConcept_15_3 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_1_0/AckChecker_AckCheckerConcept_1_0.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_1_0/AckChecker_AckCheckerConcept_1_0.dcp new file mode 100644 index 0000000000000000000000000000000000000000..86686818c5878fc990df4f603ae36b6e5f060b7e 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320dc70..7fa4bd0 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_1_0/AckChecker_AckCheckerConcept_1_0.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_1_0/AckChecker_AckCheckerConcept_1_0.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:36:17 UTC 2023 + + + outputProductCRC + 9:74ba1aa9 + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_1_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_1_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_1_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_1_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_1_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_1_0/AckChecker_AckCheckerConcept_1_0_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_1_0/AckChecker_AckCheckerConcept_1_0_sim_netlist.v new file mode 100644 index 0000000..1f32361 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_1_0/AckChecker_AckCheckerConcept_1_0_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_1_0 -prefix +// AckChecker_AckCheckerConcept_1_0_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_1_0_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_1_0 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_1_0_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_1_0/AckChecker_AckCheckerConcept_1_0_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_1_0/AckChecker_AckCheckerConcept_1_0_sim_netlist.vhdl new file mode 100644 index 0000000..e6d6528 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_1_0/AckChecker_AckCheckerConcept_1_0_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_1_0 -prefix +-- AckChecker_AckCheckerConcept_1_0_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_1_0_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_1_0_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_1_0_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_1_0 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_1_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_1_0 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_1_0 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_1_0 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_1_0 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_1_0; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_1_0 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_1_0_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_1_0/AckChecker_AckCheckerConcept_1_0_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_1_0/AckChecker_AckCheckerConcept_1_0_stub.v new file mode 100644 index 0000000..587ddd0 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_1_0/AckChecker_AckCheckerConcept_1_0_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_1_0 -prefix +// AckChecker_AckCheckerConcept_1_0_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_1_0(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_1_0/AckChecker_AckCheckerConcept_1_0_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_1_0/AckChecker_AckCheckerConcept_1_0_stub.vhdl new file mode 100644 index 0000000..402a56f --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_1_0/AckChecker_AckCheckerConcept_1_0_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_1_0 -prefix +-- AckChecker_AckCheckerConcept_1_0_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_1_0 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_1_0; + +architecture stub of AckChecker_AckCheckerConcept_1_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_2_0/AckChecker_AckCheckerConcept_2_0.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_2_0/AckChecker_AckCheckerConcept_2_0.dcp new file mode 100644 index 0000000000000000000000000000000000000000..b6bf09f85bd1f8d344de0ef2c2a8d0e5ee87bac4 GIT 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b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_2_0/AckChecker_AckCheckerConcept_2_0.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:36:17 UTC 2023 + + + outputProductCRC + 9:bf431927 + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_2_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_2_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_2_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_2_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_2_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_2_0/AckChecker_AckCheckerConcept_2_0_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_2_0/AckChecker_AckCheckerConcept_2_0_sim_netlist.v new file mode 100644 index 0000000..d672786 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_2_0/AckChecker_AckCheckerConcept_2_0_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_2_0 -prefix +// AckChecker_AckCheckerConcept_2_0_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_2_0_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_2_0 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_2_0_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_2_0/AckChecker_AckCheckerConcept_2_0_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_2_0/AckChecker_AckCheckerConcept_2_0_sim_netlist.vhdl new file mode 100644 index 0000000..8034fac --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_2_0/AckChecker_AckCheckerConcept_2_0_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_2_0 -prefix +-- AckChecker_AckCheckerConcept_2_0_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_2_0_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_2_0_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_2_0_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_2_0 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_2_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_2_0 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_2_0 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_2_0 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_2_0 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_2_0; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_2_0 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_2_0_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_2_0/AckChecker_AckCheckerConcept_2_0_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_2_0/AckChecker_AckCheckerConcept_2_0_stub.v new file mode 100644 index 0000000..d46a324 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_2_0/AckChecker_AckCheckerConcept_2_0_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_2_0 -prefix +// AckChecker_AckCheckerConcept_2_0_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_2_0(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_2_0/AckChecker_AckCheckerConcept_2_0_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_2_0/AckChecker_AckCheckerConcept_2_0_stub.vhdl new file mode 100644 index 0000000..43dc876 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_2_0/AckChecker_AckCheckerConcept_2_0_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_2_0 -prefix +-- AckChecker_AckCheckerConcept_2_0_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_2_0 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_2_0; + +architecture stub of AckChecker_AckCheckerConcept_2_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_3_0/AckChecker_AckCheckerConcept_3_0.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_3_0/AckChecker_AckCheckerConcept_3_0.dcp new file mode 100644 index 0000000000000000000000000000000000000000..a2fba236045a12445ee2ac744a444e4f5070f585 GIT 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zXSQ4l;au_8Iks3atLK?#>Y7#4R0Pc|Cau^ks}|^`Fx9cWsL|6gIB3hkX<}0%r&8{P;rgSYI}zY>58 ztb`LJpOqYVvq)f>pOR#C(Mc{gz3^D`gV(KpKl3GF&hFWiuJCr9{-|Fqn$Kn)IC{TVddF&`K%=^8_n$Uo z2PIC}bM^0fYX|m9#-c+Ch5Vh%g!ayt6zuw>IN_dX<$lFA9w$mg&+PuaF*73gw%n%w ziBFyK*JdqvyeMSxySpboA66Gpf9W-~PwJxF*X~)4dm`V(gl@VwXOqZ7W=-CyTKYz&FN{Otx67}3Ew;08hTBHz)z6ReW>@yj zu3t9qZk^qp?u##g*_9DkaN<791{C?ggu$?_5yV2AXM_7_8*~%V_a%VLftc71JT!-( ziJ)By=tiRNDgYS?0^1s8#ECExxW@q9MDzviAk!d@{47C?iLmAE=;op?H3yjs0^1rl z0#{oQ^gMXsIl7tXi&jA9LEO3 MIXED -3 - TRUE TRUE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_3_0/AckChecker_AckCheckerConcept_3_0.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_3_0/AckChecker_AckCheckerConcept_3_0.xml index 77b9bd4..bdb880d 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_3_0/AckChecker_AckCheckerConcept_3_0.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_3_0/AckChecker_AckCheckerConcept_3_0.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:36:17 UTC 2023 + + + outputProductCRC + 9:4f3b1a62 + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_3_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_3_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_3_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_3_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_3_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_3_0/AckChecker_AckCheckerConcept_3_0_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_3_0/AckChecker_AckCheckerConcept_3_0_sim_netlist.v new file mode 100644 index 0000000..b82e1ef --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_3_0/AckChecker_AckCheckerConcept_3_0_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_3_0 -prefix +// AckChecker_AckCheckerConcept_3_0_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_3_0_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_3_0 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_3_0_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_3_0/AckChecker_AckCheckerConcept_3_0_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_3_0/AckChecker_AckCheckerConcept_3_0_sim_netlist.vhdl new file mode 100644 index 0000000..88754b2 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_3_0/AckChecker_AckCheckerConcept_3_0_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_3_0 -prefix +-- AckChecker_AckCheckerConcept_3_0_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_3_0_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_3_0_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_3_0_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_3_0 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_3_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_3_0 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_3_0 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_3_0 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_3_0 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_3_0; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_3_0 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_3_0_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_3_0/AckChecker_AckCheckerConcept_3_0_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_3_0/AckChecker_AckCheckerConcept_3_0_stub.v new file mode 100644 index 0000000..0b03502 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_3_0/AckChecker_AckCheckerConcept_3_0_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_3_0 -prefix +// AckChecker_AckCheckerConcept_3_0_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_3_0(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_3_0/AckChecker_AckCheckerConcept_3_0_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_3_0/AckChecker_AckCheckerConcept_3_0_stub.vhdl new file mode 100644 index 0000000..2f65d10 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_3_0/AckChecker_AckCheckerConcept_3_0_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_3_0 -prefix +-- AckChecker_AckCheckerConcept_3_0_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_3_0 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_3_0; + +architecture stub of AckChecker_AckCheckerConcept_3_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_1/AckChecker_AckCheckerConcept_4_1.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_1/AckChecker_AckCheckerConcept_4_1.dcp new file mode 100644 index 0000000000000000000000000000000000000000..c7721d8c9b489158e9a09bfdce06475ba77c492c GIT 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b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_1/AckChecker_AckCheckerConcept_4_1.xci index 4215d98..3004026 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_1/AckChecker_AckCheckerConcept_4_1.xci +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_1/AckChecker_AckCheckerConcept_4_1.xci @@ -26,7 +26,6 @@ MIXED -3 - TRUE TRUE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_1/AckChecker_AckCheckerConcept_4_1.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_1/AckChecker_AckCheckerConcept_4_1.xml index e12757b..23825c4 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_1/AckChecker_AckCheckerConcept_4_1.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_1/AckChecker_AckCheckerConcept_4_1.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:36:17 UTC 2023 + + + outputProductCRC + 9:64f11e7b + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_4_1.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_4_1_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_4_1_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_4_1_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_4_1_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_1/AckChecker_AckCheckerConcept_4_1_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_1/AckChecker_AckCheckerConcept_4_1_sim_netlist.v new file mode 100644 index 0000000..ab9a2cc --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_1/AckChecker_AckCheckerConcept_4_1_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_4_1 -prefix +// AckChecker_AckCheckerConcept_4_1_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_4_1_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_4_1 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_4_1_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_1/AckChecker_AckCheckerConcept_4_1_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_1/AckChecker_AckCheckerConcept_4_1_sim_netlist.vhdl new file mode 100644 index 0000000..19cbe49 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_1/AckChecker_AckCheckerConcept_4_1_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_4_1 -prefix +-- AckChecker_AckCheckerConcept_4_1_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_4_1_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_4_1_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_4_1_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_4_1 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_4_1 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_4_1 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_4_1 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_4_1 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_4_1 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_4_1; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_4_1 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_4_1_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_1/AckChecker_AckCheckerConcept_4_1_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_1/AckChecker_AckCheckerConcept_4_1_stub.v new file mode 100644 index 0000000..6b1733f --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_1/AckChecker_AckCheckerConcept_4_1_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_4_1 -prefix +// AckChecker_AckCheckerConcept_4_1_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_4_1(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_1/AckChecker_AckCheckerConcept_4_1_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_1/AckChecker_AckCheckerConcept_4_1_stub.vhdl new file mode 100644 index 0000000..7aec9bd --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_1/AckChecker_AckCheckerConcept_4_1_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_4_1 -prefix +-- AckChecker_AckCheckerConcept_4_1_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_4_1 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_4_1; + +architecture stub of AckChecker_AckCheckerConcept_4_1 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2.dcp new file mode 100644 index 0000000000000000000000000000000000000000..0bf97df1366674b0af3169c76d2ad2232a72b836 GIT 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a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2.xci b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2.xci index 16a1bdb..f34a8dd 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2.xci +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2.xci @@ -26,7 +26,6 @@ MIXED -3 - TRUE TRUE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2.xml index ac68ce3..092bc01 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:36:27 UTC 2023 + + + outputProductCRC + 9:06d31239 + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_4_2.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_4_2_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_4_2_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_4_2_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_4_2_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_sim_netlist.v new file mode 100644 index 0000000..9bf0d1d --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_4_2 -prefix +// AckChecker_AckCheckerConcept_4_2_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_4_2_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_4_2 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_4_2_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_sim_netlist.vhdl new file mode 100644 index 0000000..94dffca --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_4_2 -prefix +-- AckChecker_AckCheckerConcept_4_2_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_4_2_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_4_2_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_4_2_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_4_2 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_4_2 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_4_2 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_4_2 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_4_2 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_4_2 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_4_2; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_4_2 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_4_2_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_stub.v new file mode 100644 index 0000000..95ea050 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_4_2 -prefix +// AckChecker_AckCheckerConcept_4_2_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_4_2(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_stub.vhdl new file mode 100644 index 0000000..e374635 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_4_2 -prefix +-- AckChecker_AckCheckerConcept_4_2_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_4_2 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_4_2; + +architecture stub of AckChecker_AckCheckerConcept_4_2 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1.dcp new file mode 100644 index 0000000000000000000000000000000000000000..26a07b9decb8aa77cf7b2a2f300612be48fe71ee GIT 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b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1.xci @@ -26,7 +26,6 @@ MIXED -3 - TRUE TRUE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1.xml index 7384e3e..39e3e80 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:36:27 UTC 2023 + + + outputProductCRC + 9:94891d3e + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_5_1.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_5_1_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_5_1_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_5_1_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_5_1_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_sim_netlist.v new file mode 100644 index 0000000..a097b91 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_5_1 -prefix +// AckChecker_AckCheckerConcept_5_1_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_5_1_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_5_1 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_5_1_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_sim_netlist.vhdl new file mode 100644 index 0000000..7c1ca9d --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_5_1 -prefix +-- AckChecker_AckCheckerConcept_5_1_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_5_1_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_5_1_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_5_1_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_5_1 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_5_1 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_5_1 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_5_1 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_5_1 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_5_1 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_5_1; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_5_1 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_5_1_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_stub.v new file mode 100644 index 0000000..ea7da3a --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_5_1 -prefix +// AckChecker_AckCheckerConcept_5_1_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_5_1(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_stub.vhdl new file mode 100644 index 0000000..ac8621a --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_5_1 -prefix +-- AckChecker_AckCheckerConcept_5_1_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_5_1 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_5_1; + +architecture stub of AckChecker_AckCheckerConcept_5_1 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_2/AckChecker_AckCheckerConcept_5_2.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_2/AckChecker_AckCheckerConcept_5_2.dcp new file mode 100644 index 0000000000000000000000000000000000000000..b9c6075ebde42c1c4bcef88280f333e67c64366a GIT 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b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_2/AckChecker_AckCheckerConcept_5_2.xci index cce29a3..c66a5b1 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_2/AckChecker_AckCheckerConcept_5_2.xci +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_2/AckChecker_AckCheckerConcept_5_2.xci @@ -26,7 +26,6 @@ MIXED -3 - TRUE TRUE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_2/AckChecker_AckCheckerConcept_5_2.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_2/AckChecker_AckCheckerConcept_5_2.xml index 99b48e1..4beed5e 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_2/AckChecker_AckCheckerConcept_5_2.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_2/AckChecker_AckCheckerConcept_5_2.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:36:37 UTC 2023 + + + outputProductCRC + 9:f6ab117c + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_5_2.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_5_2_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_5_2_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_5_2_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_5_2_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_2/AckChecker_AckCheckerConcept_5_2_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_2/AckChecker_AckCheckerConcept_5_2_sim_netlist.v new file mode 100644 index 0000000..be671d0 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_2/AckChecker_AckCheckerConcept_5_2_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_5_2 -prefix +// AckChecker_AckCheckerConcept_5_2_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_5_2_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_5_2 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_5_2_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_2/AckChecker_AckCheckerConcept_5_2_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_2/AckChecker_AckCheckerConcept_5_2_sim_netlist.vhdl new file mode 100644 index 0000000..b622a5c --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_2/AckChecker_AckCheckerConcept_5_2_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_5_2 -prefix +-- AckChecker_AckCheckerConcept_5_2_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_5_2_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_5_2_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_5_2_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_5_2 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_5_2 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_5_2 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_5_2 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_5_2 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_5_2 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_5_2; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_5_2 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_5_2_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_2/AckChecker_AckCheckerConcept_5_2_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_2/AckChecker_AckCheckerConcept_5_2_stub.v new file mode 100644 index 0000000..8f6374d --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_2/AckChecker_AckCheckerConcept_5_2_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_5_2 -prefix +// AckChecker_AckCheckerConcept_5_2_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_5_2(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_2/AckChecker_AckCheckerConcept_5_2_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_2/AckChecker_AckCheckerConcept_5_2_stub.vhdl new file mode 100644 index 0000000..803d391 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_2/AckChecker_AckCheckerConcept_5_2_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_5_2 -prefix +-- AckChecker_AckCheckerConcept_5_2_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_5_2 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_5_2; + +architecture stub of AckChecker_AckCheckerConcept_5_2 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1.dcp new file mode 100644 index 0000000000000000000000000000000000000000..6ebb201f8bfc2e2df75d15a842641d345a452e42 GIT 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a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1.xci +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1.xci @@ -26,7 +26,6 @@ MIXED -3 - TRUE TRUE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1.xml index 2976b95..6a0322d 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:36:27 UTC 2023 + + + outputProductCRC + 9:5f701eb0 + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_6_1.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_6_1_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_6_1_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_6_1_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_6_1_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_sim_netlist.v new file mode 100644 index 0000000..4283284 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_6_1 -prefix +// AckChecker_AckCheckerConcept_6_1_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_6_1_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_6_1 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_6_1_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_sim_netlist.vhdl new file mode 100644 index 0000000..19c049a --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_6_1 -prefix +-- AckChecker_AckCheckerConcept_6_1_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_6_1_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_6_1_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_6_1_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_6_1 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_6_1 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_6_1 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_6_1 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_6_1 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_6_1 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_6_1; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_6_1 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_6_1_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_stub.v new file mode 100644 index 0000000..22d2f19 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_6_1 -prefix +// AckChecker_AckCheckerConcept_6_1_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_6_1(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_stub.vhdl new file mode 100644 index 0000000..7bdade7 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_6_1 -prefix +-- AckChecker_AckCheckerConcept_6_1_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_6_1 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_6_1; + +architecture stub of AckChecker_AckCheckerConcept_6_1 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2.dcp new file mode 100644 index 0000000000000000000000000000000000000000..ce074f6c050ec44dfede3f2696be4fa2d83e90f1 GIT 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a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:36:37 UTC 2023 + + + outputProductCRC + 9:3d5212f2 + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_6_2.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_6_2_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_6_2_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_6_2_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_6_2_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_sim_netlist.v new file mode 100644 index 0000000..c99b319 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_6_2 -prefix +// AckChecker_AckCheckerConcept_6_2_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_6_2_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_6_2 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_6_2_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_sim_netlist.vhdl new file mode 100644 index 0000000..af1d415 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_6_2 -prefix +-- AckChecker_AckCheckerConcept_6_2_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_6_2_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_6_2_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_6_2_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_6_2 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_6_2 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_6_2 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_6_2 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_6_2 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_6_2 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_6_2; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_6_2 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_6_2_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_stub.v new file mode 100644 index 0000000..4e17371 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_6_2 -prefix +// AckChecker_AckCheckerConcept_6_2_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_6_2(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_stub.vhdl new file mode 100644 index 0000000..4e6643e --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_6_2 -prefix +-- AckChecker_AckCheckerConcept_6_2_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_6_2 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_6_2; + +architecture stub of AckChecker_AckCheckerConcept_6_2 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1.dcp new file mode 100644 index 0000000000000000000000000000000000000000..1de3b06ce21233b1f4087b549f90b1ce18b98884 GIT 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b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1.xci index b3a820a..37d90f3 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1.xci +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1.xci @@ -26,7 +26,6 @@ MIXED -3 - TRUE TRUE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1.xml index a6c28fc..0aa8226 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:36:27 UTC 2023 + + + outputProductCRC + 9:af081df5 + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_7_1.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_7_1_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_7_1_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_7_1_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_7_1_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_sim_netlist.v new file mode 100644 index 0000000..ed89ad5 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_7_1 -prefix +// AckChecker_AckCheckerConcept_7_1_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_7_1_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_7_1 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_7_1_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_sim_netlist.vhdl new file mode 100644 index 0000000..9819ed7 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_7_1 -prefix +-- AckChecker_AckCheckerConcept_7_1_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_7_1_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_7_1_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_7_1_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_7_1 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_7_1 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_7_1 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_7_1 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_7_1 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_7_1 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_7_1; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_7_1 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_7_1_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_stub.v new file mode 100644 index 0000000..8b4a21b --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_7_1 -prefix +// AckChecker_AckCheckerConcept_7_1_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_7_1(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_stub.vhdl new file mode 100644 index 0000000..a189b11 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_7_1 -prefix +-- AckChecker_AckCheckerConcept_7_1_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_7_1 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_7_1; + +architecture stub of AckChecker_AckCheckerConcept_7_1 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2.dcp new file mode 100644 index 0000000000000000000000000000000000000000..4358249a98350d6c5fffc444c639066056f946af GIT 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zXSQ4l;au_8Iks3atLK?#>Y7#4R0Pc|Cau^ks}|^`Fx9cWsL|6gIB3hkX<}0%rM;O89|v(IvfCVXEQDRo2O)DIuyEk9q}E}8kWk^6AY z<}XPC&(v)$ulabx=-9Nf+Kb_l0tdb;tyDXoaC6cshD|&MTw!w>eE+fONYD7zY+JcO zcSB)tg5e-I|k-AS=t7_*97XPR$k#OB1_JQvdr;=ZsNHtFekDTGMzo9vndY;QO*xLQ3oBUjO zs5{KSK5AR)&HH;)W;nZE>00q7nCs5pnZa6hvW6ntzi@DH>y^p?6rJm8pizoTHXiy zjs31m(>Cx=O)d}NecA4}hDTMT&@|_b-jtPlPF!7Ze%-HKe?wxo-|$|fI}S%Mf7Ve8w`%|%~p4l)-6 zwl!`9F1H})dGN|}bTiRct$@sfxOF#h;|D=AfooXMO+;S;0x}T MIXED -3 - TRUE TRUE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2.xml index 047868a..5fe1dfd 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2.xml @@ -200,6 +200,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:36:37 UTC 2023 + + + outputProductCRC + 9:cd2a11b7 + + + @@ -393,6 +411,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_AckCheckerConcept_7_2.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_AckCheckerConcept_7_2_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_7_2_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_AckCheckerConcept_7_2_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_AckCheckerConcept_7_2_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + AckCheckerConcept_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_sim_netlist.v new file mode 100644 index 0000000..a3e9c40 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_sim_netlist.v @@ -0,0 +1,764 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_7_2 -prefix +// AckChecker_AckCheckerConcept_7_2_ AckChecker_AckCheckerConcept_0_0_sim_netlist.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module AckChecker_AckCheckerConcept_7_2_AckCheckerConcept + (AckPr, + currentPr, + reset, + acknowledge_in, + Clk, + line, + currentPr_en, + Ready, + ackTime, + AckPr_en); + output AckPr; + output currentPr; + input reset; + input acknowledge_in; + input Clk; + input line; + input currentPr_en; + input Ready; + input [31:0]ackTime; + input AckPr_en; + + wire AckPr; + wire AckPr_en; + wire AckPr_i_1_n_0; + wire Clk; + wire \FSM_sequential_acknowledge[0]_i_1_n_0 ; + wire \FSM_sequential_acknowledge[1]_i_1_n_0 ; + wire Ready; + wire \TimeCnt[0]_i_1_n_0 ; + wire \TimeCnt[1]_i_1_n_0 ; + wire \TimeCnt[3]_i_1_n_0 ; + wire \TimeCnt[3]_i_2_n_0 ; + wire \TimeCnt[5]_i_1_n_0 ; + wire \TimeCnt[7]_i_1_n_0 ; + wire \TimeCnt[7]_i_2_n_0 ; + wire \TimeCnt[7]_i_4_n_0 ; + wire \TimeCnt_reg_n_0_[0] ; + wire \TimeCnt_reg_n_0_[1] ; + wire \TimeCnt_reg_n_0_[2] ; + wire \TimeCnt_reg_n_0_[3] ; + wire \TimeCnt_reg_n_0_[4] ; + wire \TimeCnt_reg_n_0_[5] ; + wire \TimeCnt_reg_n_0_[6] ; + wire \TimeCnt_reg_n_0_[7] ; + wire [31:0]ackTime; + wire [1:0]acknowledge; + wire acknowledge_in; + wire currentPr; + wire currentPr1__0; + wire currentPr_en; + wire currentPr_i_1_n_0; + wire currentPr_i_2_n_0; + wire currentPr_i_3_n_0; + wire currentPr_i_4_n_0; + wire line; + wire line_prev; + wire ltOp__15; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1__0_n_0; + wire ltOp_carry_i_1__1_n_0; + wire ltOp_carry_i_1__2_n_0; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2__0_n_0; + wire ltOp_carry_i_2__1_n_0; + wire ltOp_carry_i_2__2_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3__0_n_0; + wire ltOp_carry_i_3__1_n_0; + wire ltOp_carry_i_3__2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4__0_n_0; + wire ltOp_carry_i_4__1_n_0; + wire ltOp_carry_i_4__2_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5__0_n_0; + wire ltOp_carry_i_5__1_n_0; + wire ltOp_carry_i_5__2_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6__0_n_0; + wire ltOp_carry_i_6__1_n_0; + wire ltOp_carry_i_6__2_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7__0_n_0; + wire ltOp_carry_i_7__1_n_0; + wire ltOp_carry_i_7__2_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8__0_n_0; + wire ltOp_carry_i_8__1_n_0; + wire ltOp_carry_i_8__2_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [7:2]plusOp; + wire reset; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hFFFF0400)) + AckPr_i_1 + (.I0(ltOp__15), + .I1(acknowledge[0]), + .I2(acknowledge[1]), + .I3(AckPr_en), + .I4(AckPr), + .O(AckPr_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + AckPr_reg + (.C(Clk), + .CE(1'b1), + .D(AckPr_i_1_n_0), + .Q(AckPr), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hD3D0C3C0)) + \FSM_sequential_acknowledge[0]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(currentPr1__0), + .I4(ltOp__15), + .O(\FSM_sequential_acknowledge[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h48)) + \FSM_sequential_acknowledge[0]_i_2 + (.I0(line_prev), + .I1(Ready), + .I2(line), + .O(currentPr1__0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hE8C0)) + \FSM_sequential_acknowledge[1]_i_1 + (.I0(acknowledge_in), + .I1(acknowledge[1]), + .I2(acknowledge[0]), + .I3(ltOp__15), + .O(\FSM_sequential_acknowledge[1]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[0] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[0]_i_1_n_0 ), + .Q(acknowledge[0]), + .R(reset)); + (* FSM_ENCODED_STATES = "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_acknowledge_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\FSM_sequential_acknowledge[1]_i_1_n_0 ), + .Q(acknowledge[1]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \TimeCnt[0]_i_1 + (.I0(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[1]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[1] ), + .O(\TimeCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[2]_i_1 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .O(plusOp[2])); + LUT6 #( + .INIT(64'h00D0FFFFD0000000)) + \TimeCnt[3]_i_1 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(ltOp__15), + .I3(\TimeCnt[3]_i_2_n_0 ), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[3] ), + .O(\TimeCnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h80)) + \TimeCnt[3]_i_2 + (.I0(\TimeCnt_reg_n_0_[2] ), + .I1(\TimeCnt_reg_n_0_[1] ), + .I2(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \TimeCnt[4]_i_1 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(\TimeCnt_reg_n_0_[0] ), + .I4(\TimeCnt_reg_n_0_[4] ), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h4044FFFF80880000)) + \TimeCnt[5]_i_1 + (.I0(\TimeCnt[7]_i_4_n_0 ), + .I1(ltOp__15), + .I2(acknowledge_in), + .I3(acknowledge[1]), + .I4(\TimeCnt[7]_i_2_n_0 ), + .I5(\TimeCnt_reg_n_0_[5] ), + .O(\TimeCnt[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \TimeCnt[6]_i_1 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[6] ), + .O(plusOp[6])); + LUT5 #( + .INIT(32'h01110404)) + \TimeCnt[7]_i_1 + (.I0(reset), + .I1(acknowledge[0]), + .I2(ltOp__15), + .I3(acknowledge_in), + .I4(acknowledge[1]), + .O(\TimeCnt[7]_i_1_n_0 )); + LUT3 #( + .INIT(8'h06)) + \TimeCnt[7]_i_2 + (.I0(acknowledge[1]), + .I1(acknowledge[0]), + .I2(reset), + .O(\TimeCnt[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7F80)) + \TimeCnt[7]_i_3 + (.I0(\TimeCnt_reg_n_0_[6] ), + .I1(\TimeCnt[7]_i_4_n_0 ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(\TimeCnt_reg_n_0_[7] ), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h80000000)) + \TimeCnt[7]_i_4 + (.I0(\TimeCnt_reg_n_0_[4] ), + .I1(\TimeCnt_reg_n_0_[3] ), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(\TimeCnt_reg_n_0_[1] ), + .I4(\TimeCnt_reg_n_0_[0] ), + .O(\TimeCnt[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[0] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(\TimeCnt[0]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[0] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[1] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[1]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[2] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[2]), + .Q(\TimeCnt_reg_n_0_[2] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[3] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[3]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[4] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[4]), + .Q(\TimeCnt_reg_n_0_[4] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[5] + (.C(Clk), + .CE(1'b1), + .D(\TimeCnt[5]_i_1_n_0 ), + .Q(\TimeCnt_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[6] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[6]), + .Q(\TimeCnt_reg_n_0_[6] ), + .R(\TimeCnt[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCnt_reg[7] + (.C(Clk), + .CE(\TimeCnt[7]_i_2_n_0 ), + .D(plusOp[7]), + .Q(\TimeCnt_reg_n_0_[7] ), + .R(\TimeCnt[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBFFBF88880080)) + currentPr_i_1 + (.I0(currentPr_i_2_n_0), + .I1(currentPr_i_3_n_0), + .I2(acknowledge[1]), + .I3(ltOp__15), + .I4(currentPr_i_4_n_0), + .I5(currentPr), + .O(currentPr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hC888)) + currentPr_i_2 + (.I0(acknowledge[1]), + .I1(currentPr_en), + .I2(acknowledge_in), + .I3(Ready), + .O(currentPr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + currentPr_i_3 + (.I0(currentPr_en), + .I1(acknowledge[0]), + .O(currentPr_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40000400)) + currentPr_i_4 + (.I0(acknowledge[1]), + .I1(acknowledge_in), + .I2(line), + .I3(Ready), + .I4(line_prev), + .O(currentPr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + currentPr_reg + (.C(Clk), + .CE(1'b1), + .D(currentPr_i_1_n_0), + .Q(currentPr), + .R(reset)); + FDRE #( + .INIT(1'b0)) + line_prev_reg + (.C(Clk), + .CE(1'b1), + .D(line), + .Q(line_prev), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__0_n_0,ltOp_carry_i_2__0_n_0,ltOp_carry_i_3__0_n_0,ltOp_carry_i_4__0_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__0_n_0,ltOp_carry_i_6__0_n_0,ltOp_carry_i_7__0_n_0,ltOp_carry_i_8__0_n_0})); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__1_n_0,ltOp_carry_i_2__1_n_0,ltOp_carry_i_3__1_n_0,ltOp_carry_i_4__1_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__1_n_0,ltOp_carry_i_6__1_n_0,ltOp_carry_i_7__1_n_0,ltOp_carry_i_8__1_n_0})); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({ltOp__15,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1__2_n_0,ltOp_carry_i_2__2_n_0,ltOp_carry_i_3__2_n_0,ltOp_carry_i_4__2_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5__2_n_0,ltOp_carry_i_6__2_n_0,ltOp_carry_i_7__2_n_0,ltOp_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(ackTime[6]), + .I1(\TimeCnt_reg_n_0_[6] ), + .I2(\TimeCnt_reg_n_0_[7] ), + .I3(ackTime[7]), + .O(ltOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__0 + (.I0(ackTime[14]), + .I1(ackTime[15]), + .O(ltOp_carry_i_1__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__1 + (.I0(ackTime[22]), + .I1(ackTime[23]), + .O(ltOp_carry_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_1__2 + (.I0(ackTime[30]), + .I1(ackTime[31]), + .O(ltOp_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(ackTime[4]), + .I1(\TimeCnt_reg_n_0_[4] ), + .I2(\TimeCnt_reg_n_0_[5] ), + .I3(ackTime[5]), + .O(ltOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__0 + (.I0(ackTime[12]), + .I1(ackTime[13]), + .O(ltOp_carry_i_2__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__1 + (.I0(ackTime[20]), + .I1(ackTime[21]), + .O(ltOp_carry_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_2__2 + (.I0(ackTime[28]), + .I1(ackTime[29]), + .O(ltOp_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(ackTime[2]), + .I1(\TimeCnt_reg_n_0_[2] ), + .I2(\TimeCnt_reg_n_0_[3] ), + .I3(ackTime[3]), + .O(ltOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__0 + (.I0(ackTime[10]), + .I1(ackTime[11]), + .O(ltOp_carry_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__1 + (.I0(ackTime[18]), + .I1(ackTime[19]), + .O(ltOp_carry_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_3__2 + (.I0(ackTime[26]), + .I1(ackTime[27]), + .O(ltOp_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(ackTime[0]), + .I1(\TimeCnt_reg_n_0_[0] ), + .I2(\TimeCnt_reg_n_0_[1] ), + .I3(ackTime[1]), + .O(ltOp_carry_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__0 + (.I0(ackTime[8]), + .I1(ackTime[9]), + .O(ltOp_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__1 + (.I0(ackTime[16]), + .I1(ackTime[17]), + .O(ltOp_carry_i_4__1_n_0)); + LUT2 #( + .INIT(4'hE)) + ltOp_carry_i_4__2 + (.I0(ackTime[24]), + .I1(ackTime[25]), + .O(ltOp_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(\TimeCnt_reg_n_0_[7] ), + .I1(ackTime[7]), + .I2(\TimeCnt_reg_n_0_[6] ), + .I3(ackTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__0 + (.I0(ackTime[15]), + .I1(ackTime[14]), + .O(ltOp_carry_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__1 + (.I0(ackTime[23]), + .I1(ackTime[22]), + .O(ltOp_carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_5__2 + (.I0(ackTime[31]), + .I1(ackTime[30]), + .O(ltOp_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(\TimeCnt_reg_n_0_[5] ), + .I1(ackTime[5]), + .I2(\TimeCnt_reg_n_0_[4] ), + .I3(ackTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__0 + (.I0(ackTime[13]), + .I1(ackTime[12]), + .O(ltOp_carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__1 + (.I0(ackTime[21]), + .I1(ackTime[20]), + .O(ltOp_carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_6__2 + (.I0(ackTime[29]), + .I1(ackTime[28]), + .O(ltOp_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(\TimeCnt_reg_n_0_[3] ), + .I1(ackTime[3]), + .I2(\TimeCnt_reg_n_0_[2] ), + .I3(ackTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__0 + (.I0(ackTime[11]), + .I1(ackTime[10]), + .O(ltOp_carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__1 + (.I0(ackTime[19]), + .I1(ackTime[18]), + .O(ltOp_carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_7__2 + (.I0(ackTime[27]), + .I1(ackTime[26]), + .O(ltOp_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(\TimeCnt_reg_n_0_[1] ), + .I1(ackTime[1]), + .I2(\TimeCnt_reg_n_0_[0] ), + .I3(ackTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__0 + (.I0(ackTime[9]), + .I1(ackTime[8]), + .O(ltOp_carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__1 + (.I0(ackTime[17]), + .I1(ackTime[16]), + .O(ltOp_carry_i_8__1_n_0)); + LUT2 #( + .INIT(4'h1)) + ltOp_carry_i_8__2 + (.I0(ackTime[25]), + .I1(ackTime[24]), + .O(ltOp_carry_i_8__2_n_0)); +endmodule + +(* CHECK_LICENSE_TYPE = "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_AckCheckerConcept_7_2 + (ackTime, + AckPr_en, + AckPr, + acknowledge_in, + Clk, + currentPr_en, + currentPr, + line, + Ready, + reset); + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + (* x_interface_info = "xilinx.com:signal:clock:1.0 Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0" *) input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + + wire AckPr; + wire AckPr_en; + wire Clk; + wire Ready; + wire [31:0]ackTime; + wire acknowledge_in; + wire currentPr; + wire currentPr_en; + wire line; + wire reset; + + AckChecker_AckCheckerConcept_7_2_AckCheckerConcept U0 + (.AckPr(AckPr), + .AckPr_en(AckPr_en), + .Clk(Clk), + .Ready(Ready), + .ackTime(ackTime), + .acknowledge_in(acknowledge_in), + .currentPr(currentPr), + .currentPr_en(currentPr_en), + .line(line), + .reset(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_sim_netlist.vhdl new file mode 100644 index 0000000..11a268b --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_sim_netlist.vhdl @@ -0,0 +1,927 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_AckCheckerConcept_7_2 -prefix +-- AckChecker_AckCheckerConcept_7_2_ AckChecker_AckCheckerConcept_0_0_sim_netlist.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_7_2_AckCheckerConcept is + port ( + AckPr : out STD_LOGIC; + currentPr : out STD_LOGIC; + reset : in STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + line : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + Ready : in STD_LOGIC; + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC + ); +end AckChecker_AckCheckerConcept_7_2_AckCheckerConcept; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_7_2_AckCheckerConcept is + signal \^ackpr\ : STD_LOGIC; + signal AckPr_i_1_n_0 : STD_LOGIC; + signal \FSM_sequential_acknowledge[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_acknowledge[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[3]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[5]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_1_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_2_n_0\ : STD_LOGIC; + signal \TimeCnt[7]_i_4_n_0\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[5]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[6]\ : STD_LOGIC; + signal \TimeCnt_reg_n_0_[7]\ : STD_LOGIC; + signal acknowledge : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^currentpr\ : STD_LOGIC; + signal \currentPr1__0\ : STD_LOGIC; + signal currentPr_i_1_n_0 : STD_LOGIC; + signal currentPr_i_2_n_0 : STD_LOGIC; + signal currentPr_i_3_n_0 : STD_LOGIC; + signal currentPr_i_4_n_0 : STD_LOGIC; + signal line_prev : STD_LOGIC; + signal \ltOp__15\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal \ltOp_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_1__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal \ltOp_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_2__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal \ltOp_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_3__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal \ltOp_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_4__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal \ltOp_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_5__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal \ltOp_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_6__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_7__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal \ltOp_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp_carry_i_8__2_n_0\ : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_acknowledge[1]_i_1\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[0]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_acknowledge_reg[1]\ : label is "check:01,waiting_strobe_end:10,waiting:00,iSTATE:11"; + attribute SOFT_HLUTNM of \TimeCnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \TimeCnt[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \TimeCnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_3\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \TimeCnt[7]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of currentPr_i_2 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_3 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of currentPr_i_4 : label is "soft_lutpair2"; +begin + AckPr <= \^ackpr\; + currentPr <= \^currentpr\; +AckPr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0400" + ) + port map ( + I0 => \ltOp__15\, + I1 => acknowledge(0), + I2 => acknowledge(1), + I3 => AckPr_en, + I4 => \^ackpr\, + O => AckPr_i_1_n_0 + ); +AckPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => AckPr_i_1_n_0, + Q => \^ackpr\, + R => reset + ); +\FSM_sequential_acknowledge[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D3D0C3C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \currentPr1__0\, + I4 => \ltOp__15\, + O => \FSM_sequential_acknowledge[0]_i_1_n_0\ + ); +\FSM_sequential_acknowledge[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => line_prev, + I1 => Ready, + I2 => line, + O => \currentPr1__0\ + ); +\FSM_sequential_acknowledge[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E8C0" + ) + port map ( + I0 => acknowledge_in, + I1 => acknowledge(1), + I2 => acknowledge(0), + I3 => \ltOp__15\, + O => \FSM_sequential_acknowledge[1]_i_1_n_0\ + ); +\FSM_sequential_acknowledge_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[0]_i_1_n_0\, + Q => acknowledge(0), + R => reset + ); +\FSM_sequential_acknowledge_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \FSM_sequential_acknowledge[1]_i_1_n_0\, + Q => acknowledge(1), + R => reset + ); +\TimeCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[0]_i_1_n_0\ + ); +\TimeCnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[1]\, + O => \TimeCnt[1]_i_1_n_0\ + ); +\TimeCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[2]\, + O => plusOp(2) + ); +\TimeCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00D0FFFFD0000000" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => \ltOp__15\, + I3 => \TimeCnt[3]_i_2_n_0\, + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[3]\, + O => \TimeCnt[3]_i_1_n_0\ + ); +\TimeCnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[2]\, + I1 => \TimeCnt_reg_n_0_[1]\, + I2 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[3]_i_2_n_0\ + ); +\TimeCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => \TimeCnt_reg_n_0_[0]\, + I4 => \TimeCnt_reg_n_0_[4]\, + O => plusOp(4) + ); +\TimeCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF80880000" + ) + port map ( + I0 => \TimeCnt[7]_i_4_n_0\, + I1 => \ltOp__15\, + I2 => acknowledge_in, + I3 => acknowledge(1), + I4 => \TimeCnt[7]_i_2_n_0\, + I5 => \TimeCnt_reg_n_0_[5]\, + O => \TimeCnt[5]_i_1_n_0\ + ); +\TimeCnt[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[6]\, + O => plusOp(6) + ); +\TimeCnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01110404" + ) + port map ( + I0 => reset, + I1 => acknowledge(0), + I2 => \ltOp__15\, + I3 => acknowledge_in, + I4 => acknowledge(1), + O => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge(0), + I2 => reset, + O => \TimeCnt[7]_i_2_n_0\ + ); +\TimeCnt[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[6]\, + I1 => \TimeCnt[7]_i_4_n_0\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => \TimeCnt_reg_n_0_[7]\, + O => plusOp(7) + ); +\TimeCnt[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[4]\, + I1 => \TimeCnt_reg_n_0_[3]\, + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => \TimeCnt_reg_n_0_[1]\, + I4 => \TimeCnt_reg_n_0_[0]\, + O => \TimeCnt[7]_i_4_n_0\ + ); +\TimeCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => \TimeCnt[0]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[0]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[1]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[1]\, + R => '0' + ); +\TimeCnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(2), + Q => \TimeCnt_reg_n_0_[2]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[3]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[3]\, + R => '0' + ); +\TimeCnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(4), + Q => \TimeCnt_reg_n_0_[4]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => \TimeCnt[5]_i_1_n_0\, + Q => \TimeCnt_reg_n_0_[5]\, + R => '0' + ); +\TimeCnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(6), + Q => \TimeCnt_reg_n_0_[6]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +\TimeCnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => \TimeCnt[7]_i_2_n_0\, + D => plusOp(7), + Q => \TimeCnt_reg_n_0_[7]\, + R => \TimeCnt[7]_i_1_n_0\ + ); +currentPr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBFFBF88880080" + ) + port map ( + I0 => currentPr_i_2_n_0, + I1 => currentPr_i_3_n_0, + I2 => acknowledge(1), + I3 => \ltOp__15\, + I4 => currentPr_i_4_n_0, + I5 => \^currentpr\, + O => currentPr_i_1_n_0 + ); +currentPr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"C888" + ) + port map ( + I0 => acknowledge(1), + I1 => currentPr_en, + I2 => acknowledge_in, + I3 => Ready, + O => currentPr_i_2_n_0 + ); +currentPr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => currentPr_en, + I1 => acknowledge(0), + O => currentPr_i_3_n_0 + ); +currentPr_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000400" + ) + port map ( + I0 => acknowledge(1), + I1 => acknowledge_in, + I2 => line, + I3 => Ready, + I4 => line_prev, + O => currentPr_i_4_n_0 + ); +currentPr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => currentPr_i_1_n_0, + Q => \^currentpr\, + R => reset + ); +line_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => '1', + D => line, + Q => line_prev, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__0_n_0\, + DI(2) => \ltOp_carry_i_2__0_n_0\, + DI(1) => \ltOp_carry_i_3__0_n_0\, + DI(0) => \ltOp_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__0_n_0\, + S(2) => \ltOp_carry_i_6__0_n_0\, + S(1) => \ltOp_carry_i_7__0_n_0\, + S(0) => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__1_n_0\, + DI(2) => \ltOp_carry_i_2__1_n_0\, + DI(1) => \ltOp_carry_i_3__1_n_0\, + DI(0) => \ltOp_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__1_n_0\, + S(2) => \ltOp_carry_i_6__1_n_0\, + S(1) => \ltOp_carry_i_7__1_n_0\, + S(0) => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => \ltOp__15\, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry_i_1__2_n_0\, + DI(2) => \ltOp_carry_i_2__2_n_0\, + DI(1) => \ltOp_carry_i_3__2_n_0\, + DI(0) => \ltOp_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry_i_5__2_n_0\, + S(2) => \ltOp_carry_i_6__2_n_0\, + S(1) => \ltOp_carry_i_7__2_n_0\, + S(0) => \ltOp_carry_i_8__2_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(6), + I1 => \TimeCnt_reg_n_0_[6]\, + I2 => \TimeCnt_reg_n_0_[7]\, + I3 => ackTime(7), + O => ltOp_carry_i_1_n_0 + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(14), + I1 => ackTime(15), + O => \ltOp_carry_i_1__0_n_0\ + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(22), + I1 => ackTime(23), + O => \ltOp_carry_i_1__1_n_0\ + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(30), + I1 => ackTime(31), + O => \ltOp_carry_i_1__2_n_0\ + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(4), + I1 => \TimeCnt_reg_n_0_[4]\, + I2 => \TimeCnt_reg_n_0_[5]\, + I3 => ackTime(5), + O => ltOp_carry_i_2_n_0 + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(12), + I1 => ackTime(13), + O => \ltOp_carry_i_2__0_n_0\ + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(20), + I1 => ackTime(21), + O => \ltOp_carry_i_2__1_n_0\ + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(28), + I1 => ackTime(29), + O => \ltOp_carry_i_2__2_n_0\ + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(2), + I1 => \TimeCnt_reg_n_0_[2]\, + I2 => \TimeCnt_reg_n_0_[3]\, + I3 => ackTime(3), + O => ltOp_carry_i_3_n_0 + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(10), + I1 => ackTime(11), + O => \ltOp_carry_i_3__0_n_0\ + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(18), + I1 => ackTime(19), + O => \ltOp_carry_i_3__1_n_0\ + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(26), + I1 => ackTime(27), + O => \ltOp_carry_i_3__2_n_0\ + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => ackTime(0), + I1 => \TimeCnt_reg_n_0_[0]\, + I2 => \TimeCnt_reg_n_0_[1]\, + I3 => ackTime(1), + O => ltOp_carry_i_4_n_0 + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(8), + I1 => ackTime(9), + O => \ltOp_carry_i_4__0_n_0\ + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(16), + I1 => ackTime(17), + O => \ltOp_carry_i_4__1_n_0\ + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ackTime(24), + I1 => ackTime(25), + O => \ltOp_carry_i_4__2_n_0\ + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[7]\, + I1 => ackTime(7), + I2 => \TimeCnt_reg_n_0_[6]\, + I3 => ackTime(6), + O => ltOp_carry_i_5_n_0 + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(15), + I1 => ackTime(14), + O => \ltOp_carry_i_5__0_n_0\ + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(23), + I1 => ackTime(22), + O => \ltOp_carry_i_5__1_n_0\ + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(31), + I1 => ackTime(30), + O => \ltOp_carry_i_5__2_n_0\ + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[5]\, + I1 => ackTime(5), + I2 => \TimeCnt_reg_n_0_[4]\, + I3 => ackTime(4), + O => ltOp_carry_i_6_n_0 + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(13), + I1 => ackTime(12), + O => \ltOp_carry_i_6__0_n_0\ + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(21), + I1 => ackTime(20), + O => \ltOp_carry_i_6__1_n_0\ + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(29), + I1 => ackTime(28), + O => \ltOp_carry_i_6__2_n_0\ + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[3]\, + I1 => ackTime(3), + I2 => \TimeCnt_reg_n_0_[2]\, + I3 => ackTime(2), + O => ltOp_carry_i_7_n_0 + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(11), + I1 => ackTime(10), + O => \ltOp_carry_i_7__0_n_0\ + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(19), + I1 => ackTime(18), + O => \ltOp_carry_i_7__1_n_0\ + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(27), + I1 => ackTime(26), + O => \ltOp_carry_i_7__2_n_0\ + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \TimeCnt_reg_n_0_[1]\, + I1 => ackTime(1), + I2 => \TimeCnt_reg_n_0_[0]\, + I3 => ackTime(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(9), + I1 => ackTime(8), + O => \ltOp_carry_i_8__0_n_0\ + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(17), + I1 => ackTime(16), + O => \ltOp_carry_i_8__1_n_0\ + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => ackTime(25), + I1 => ackTime(24), + O => \ltOp_carry_i_8__2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_AckCheckerConcept_7_2 is + port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_AckCheckerConcept_7_2 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_AckCheckerConcept_7_2 : entity is "AckChecker_AckCheckerConcept_0_0,AckCheckerConcept,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_AckCheckerConcept_7_2 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_AckCheckerConcept_7_2 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_AckCheckerConcept_7_2 : entity is "AckCheckerConcept,Vivado 2019.1"; +end AckChecker_AckCheckerConcept_7_2; + +architecture STRUCTURE of AckChecker_AckCheckerConcept_7_2 is + attribute x_interface_info : string; + attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 Clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME Clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN AckChecker_Clk_0, INSERT_VIP 0"; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.AckChecker_AckCheckerConcept_7_2_AckCheckerConcept + port map ( + AckPr => AckPr, + AckPr_en => AckPr_en, + Clk => Clk, + Ready => Ready, + ackTime(31 downto 0) => ackTime(31 downto 0), + acknowledge_in => acknowledge_in, + currentPr => currentPr, + currentPr_en => currentPr_en, + line => line, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_stub.v new file mode 100644 index 0000000..a294cca --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:55 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_7_2 -prefix +// AckChecker_AckCheckerConcept_7_2_ AckChecker_AckCheckerConcept_0_0_stub.v +// Design : AckChecker_AckCheckerConcept_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "AckCheckerConcept,Vivado 2019.1" *) +module AckChecker_AckCheckerConcept_7_2(ackTime, AckPr_en, AckPr, acknowledge_in, Clk, + currentPr_en, currentPr, line, Ready, reset) +/* synthesis syn_black_box black_box_pad_pin="ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset" */; + input [31:0]ackTime; + input AckPr_en; + output AckPr; + input acknowledge_in; + input Clk; + input currentPr_en; + output currentPr; + input line; + input Ready; + input reset; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_stub.vhdl new file mode 100644 index 0000000..2302ae0 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:55 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_AckCheckerConcept_7_2 -prefix +-- AckChecker_AckCheckerConcept_7_2_ AckChecker_AckCheckerConcept_0_0_stub.vhdl +-- Design : AckChecker_AckCheckerConcept_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_AckCheckerConcept_7_2 is + Port ( + ackTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + AckPr_en : in STD_LOGIC; + AckPr : out STD_LOGIC; + acknowledge_in : in STD_LOGIC; + Clk : in STD_LOGIC; + currentPr_en : in STD_LOGIC; + currentPr : out STD_LOGIC; + line : in STD_LOGIC; + Ready : in STD_LOGIC; + reset : in STD_LOGIC + ); + +end AckChecker_AckCheckerConcept_7_2; + +architecture stub of AckChecker_AckCheckerConcept_7_2 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ackTime[31:0],AckPr_en,AckPr,acknowledge_in,Clk,currentPr_en,currentPr,line,Ready,reset"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "AckCheckerConcept,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_0/AckChecker_BusBlock16IN_0_0.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_0/AckChecker_BusBlock16IN_0_0.dcp new file mode 100644 index 0000000000000000000000000000000000000000..db73a600bad5c528cc31e78372fb5938f6f21d95 GIT binary patch literal 5512 zcmai&1yodB*T+Ys8wBN{y9en;x@PDY1RRH!9=b&kQ4o;sPDy3xl#Zd{p_N8D73uiK z?|IkzELrQ-bJt$yuDkB}t$ps^_kZ>|THw3rWB>pF8{qpS7s8ehAXIz@0LViJ0I*O` zEzF&Gyd3P~=YG@oKsGiIg9T>hh^^m~v zy-mv6+^6+Zu^xYx;k^ra0u4Q3wS#)o=Qts6@1|27d)ap&9Gy*FQvB%{ONBB)XA2NBgB#?pt=Ii-C4fJq_ZP%EJ6 zv*VB_E9m<{`LkrsfwbMHxN2I7kS2w@cKjN7w0yE)nk;TSsd<61*$dCPW;TDyb=9r+ z;(Dr7qpEVLEfvqETCOv@tdH(#{SwX$EXzJ2R4CQ&0|0cWaLSt7$y-~R+gZB6LPBWad82GTO_yPz(bJgMj}l?9Q%_%uoft7cw}dMUkAx(nX7zDnj3LtMf$V%E zTLPIiVPiEW($lO!T-&QtkAPY)cdw_*S3FsJvxJ(v6WNVVV{@n9iD(n7(y%y(Ki?yX z70T#57Drc~pv)4MbpXhXSj*{Zn!Of0C~U^u#G9FQq!094jS?hx-;dVQ+(|QO?)Jym zfy+bq%C8$W<66U-vDC5hq&McUph1Z}98N6~n<-QFM4tNslWyKEP2Gqq!pwodY_yK| zohLFbba8C1wtjjUDwj>k9Nh|hFd$o&s1Bx;Cen&OxhpespJ_`0L}p(Y#DvEoU{J25 z!Y&CdeMP!^<>lPJ?BD1Vi&Hceb4bt|KI=wg&ylcm<}!FnY4U6dtEBaF&<=c3K#lG& z?UZ>fHcgEum95EWZkDM?v5AOJ@-KOF`{TbC?W?ip=Z;tJhpvw#5e^`a7Lk6Tbmro< zH26IR_R{Erm@@@&z*02?{3Bm^(*4MuL_UYB&=jIAm=29r31J18-6Lixsbi{^Tb42k zlcC^{Hldwy|9%_pu<+g^)h7@G7cn#P_n{Uym219agsoB#lYEmne+-7C`q9)nF`stYnG!Sy&LOvVY%5l zo-pUf>Gc@s<4U-Shs~hUvz!Rr5|2;TxnsoO1O8M?o={O>sAHJNa<;PQ{ ztBP=z&Yg`#_!rInNHGD-1P>8-d{TCJ5F1suAZ(p@DCA-cu4C+^9W%=9I8?5&7kmx$289 z0tqTHGkiVbkx=snXmuSi_sTW*vX;u}TjWjAR7JxA#W3IJd)(WC0h?&@nFb9?u3oJ3 zXv%!d)%+ZWoHJb{hnL0^rOdiIcq@&IuNitvsswv>z1;U?k_omfc`H6qtb~eD8g5j8qRP=%AD)9A)%>P#haaa~C}1z~BHl(o>aNHQclR;oFk|Fb`-@eUM9az_}m! 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All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:54 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim +// D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_0/AckChecker_BusBlock16IN_0_0_sim_netlist.v +// Design : AckChecker_BusBlock16IN_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "AckChecker_BusBlock16IN_0_0,BusBlock16IN,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "BusBlock16IN,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_BusBlock16IN_0_0 + (Bus_16IN, + Out0, + Out1, + Out2, + Out3, + Out4, + Out5, + Out6, + Out7, + Out8, + Out9, + Out10, + Out11, + Out12, + Out13, + Out14, + Out15); + input [15:0]Bus_16IN; + output Out0; + output Out1; + output Out2; + output Out3; + output Out4; + output Out5; + output Out6; + output Out7; + output Out8; + output Out9; + output Out10; + output Out11; + output Out12; + output Out13; + output Out14; + output Out15; + + wire [15:0]Bus_16IN; + + assign Out0 = Bus_16IN[0]; + assign Out1 = Bus_16IN[1]; + assign Out10 = Bus_16IN[10]; + assign Out11 = Bus_16IN[11]; + assign Out12 = Bus_16IN[12]; + assign Out13 = Bus_16IN[13]; + assign Out14 = Bus_16IN[14]; + assign Out15 = Bus_16IN[15]; + assign Out2 = Bus_16IN[2]; + assign Out3 = Bus_16IN[3]; + assign Out4 = Bus_16IN[4]; + assign Out5 = Bus_16IN[5]; + assign Out6 = Bus_16IN[6]; + assign Out7 = Bus_16IN[7]; + assign Out8 = Bus_16IN[8]; + assign Out9 = Bus_16IN[9]; +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_0/AckChecker_BusBlock16IN_0_0_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_0/AckChecker_BusBlock16IN_0_0_sim_netlist.vhdl new file mode 100644 index 0000000..f3ae878 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_0/AckChecker_BusBlock16IN_0_0_sim_netlist.vhdl @@ -0,0 +1,69 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:54 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim +-- D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_0/AckChecker_BusBlock16IN_0_0_sim_netlist.vhdl +-- Design : AckChecker_BusBlock16IN_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_BusBlock16IN_0_0 is + port ( + Bus_16IN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + Out0 : out STD_LOGIC; + Out1 : out STD_LOGIC; + Out2 : out STD_LOGIC; + Out3 : out STD_LOGIC; + Out4 : out STD_LOGIC; + Out5 : out STD_LOGIC; + Out6 : out STD_LOGIC; + Out7 : out STD_LOGIC; + Out8 : out STD_LOGIC; + Out9 : out STD_LOGIC; + Out10 : out STD_LOGIC; + Out11 : out STD_LOGIC; + Out12 : out STD_LOGIC; + Out13 : out STD_LOGIC; + Out14 : out STD_LOGIC; + Out15 : out STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_BusBlock16IN_0_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_BusBlock16IN_0_0 : entity is "AckChecker_BusBlock16IN_0_0,BusBlock16IN,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_BusBlock16IN_0_0 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_BusBlock16IN_0_0 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_BusBlock16IN_0_0 : entity is "BusBlock16IN,Vivado 2019.1"; +end AckChecker_BusBlock16IN_0_0; + +architecture STRUCTURE of AckChecker_BusBlock16IN_0_0 is + signal \^bus_16in\ : STD_LOGIC_VECTOR ( 15 downto 0 ); +begin + Out0 <= \^bus_16in\(0); + Out1 <= \^bus_16in\(1); + Out10 <= \^bus_16in\(10); + Out11 <= \^bus_16in\(11); + Out12 <= \^bus_16in\(12); + Out13 <= \^bus_16in\(13); + Out14 <= \^bus_16in\(14); + Out15 <= \^bus_16in\(15); + Out2 <= \^bus_16in\(2); + Out3 <= \^bus_16in\(3); + Out4 <= \^bus_16in\(4); + Out5 <= \^bus_16in\(5); + Out6 <= \^bus_16in\(6); + Out7 <= \^bus_16in\(7); + Out8 <= \^bus_16in\(8); + Out9 <= \^bus_16in\(9); + \^bus_16in\(15 downto 0) <= Bus_16IN(15 downto 0); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_0/AckChecker_BusBlock16IN_0_0_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_0/AckChecker_BusBlock16IN_0_0_stub.v new file mode 100644 index 0000000..b4073f6 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_0/AckChecker_BusBlock16IN_0_0_stub.v @@ -0,0 +1,37 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:54 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub +// D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_0/AckChecker_BusBlock16IN_0_0_stub.v +// Design : AckChecker_BusBlock16IN_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "BusBlock16IN,Vivado 2019.1" *) +module AckChecker_BusBlock16IN_0_0(Bus_16IN, Out0, Out1, Out2, Out3, Out4, Out5, Out6, Out7, + Out8, Out9, Out10, Out11, Out12, Out13, Out14, Out15) +/* synthesis syn_black_box black_box_pad_pin="Bus_16IN[15:0],Out0,Out1,Out2,Out3,Out4,Out5,Out6,Out7,Out8,Out9,Out10,Out11,Out12,Out13,Out14,Out15" */; + input [15:0]Bus_16IN; + output Out0; + output Out1; + output Out2; + output Out3; + output Out4; + output Out5; + output Out6; + output Out7; + output Out8; + output Out9; + output Out10; + output Out11; + output Out12; + output Out13; + output Out14; + output Out15; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_0/AckChecker_BusBlock16IN_0_0_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_0/AckChecker_BusBlock16IN_0_0_stub.vhdl new file mode 100644 index 0000000..f825672 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_0/AckChecker_BusBlock16IN_0_0_stub.vhdl @@ -0,0 +1,46 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:54 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub +-- D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_0/AckChecker_BusBlock16IN_0_0_stub.vhdl +-- Design : AckChecker_BusBlock16IN_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_BusBlock16IN_0_0 is + Port ( + Bus_16IN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + Out0 : out STD_LOGIC; + Out1 : out STD_LOGIC; + Out2 : out STD_LOGIC; + Out3 : out STD_LOGIC; + Out4 : out STD_LOGIC; + Out5 : out STD_LOGIC; + Out6 : out STD_LOGIC; + Out7 : out STD_LOGIC; + Out8 : out STD_LOGIC; + Out9 : out STD_LOGIC; + Out10 : out STD_LOGIC; + Out11 : out STD_LOGIC; + Out12 : out STD_LOGIC; + Out13 : out STD_LOGIC; + Out14 : out STD_LOGIC; + Out15 : out STD_LOGIC + ); + +end AckChecker_BusBlock16IN_0_0; + +architecture stub of AckChecker_BusBlock16IN_0_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "Bus_16IN[15:0],Out0,Out1,Out2,Out3,Out4,Out5,Out6,Out7,Out8,Out9,Out10,Out11,Out12,Out13,Out14,Out15"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "BusBlock16IN,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1.dcp new file mode 100644 index 0000000000000000000000000000000000000000..1040a174a0608e530a2e9e67a8924c6009400c2b GIT binary patch literal 5505 zcma)=bySq^w#P@LI|Y&M?hff3I))Ml>8>FLLf~%EH0Q9W3h!k#%&jaNreE(E#&+dAO`Bt(#L!AUVp!y-U}`|3EQ7L#X6ONp)j9 z7~+b$_661s4#~2%l}aeZGLhnfOD`H_@+rHG3XPw}1wT#(gU`I5Tkgh*`gtT>qj)8y z7&og=n4k<3ei+QoH@3%-UKcV^qbEFj7l3Jhedgs~2la$LUA^Xdw?Bugxi^{J_%uFu zCQ4WvXN{84E#k#KLA+pQ*NGUi`Xu=~AsHut?5M4*uBLggz+quC>K4}QoHI>;-&%|S ziRVGAp5|`4S#!@zY#kRl5O2lLM$Lq_@Mbi1v^=TJ1vJyZ6Xz z%?esc+vmVtmnnWV>Z9~ChV}S#HLf(~CgX)U`XYrUJYI>1au$v!pOzgzpf4_*tUU)hb=ec`H&LME551I$ejR;%$Redso~Uuo9a3?ps0N9(j4^=}cE>&oWL>5o&}|KI6vlBFGa8X6T8^>9 z$4eQ2C2<^ks#P9r@bNMRtm4fteNJdj7hB3$Ictsg;Z@XM2yn zwqxq}=1_qT1~0#u$m*OFS0f1YxMLLTJNB>9Q(mCxSv#;=*{W2`;P&f&ejvfVq#-8CBAz1cfHV z%ET9tcg{vM9!xWZ73LdQLTu$T8*!$F)h^0jc0-CbIgywpUM;q{oliSv9ed&`DjIwRoSR33k@cx$srD_W_0PzKH;~+`x<{_xqHl_(s~VQbMtDCH zaqI~AZz0KL88j$DpiGNMO1umo_*jkDX1fWFu1qFN8FY29zBDce)Ap6r2=wkjJ@=(y zINMe{RV`#+LPg1qJL{4&d54*pOa)7xr^jX$ta?gZEcgnbyzMnt7#OI}9(tLa-q9?+ z_exLQ6O_3)_R1k|y=m=?TkAK)8T~LUuY*vU2t?5QMRDw$E!?r-gF}PBXm1q`l?d+v z?y%EAAeZWp`VhOypxXePn;Xc;%KpS_4_cb?$E54J1PD}!S`D?>&O za9=h~NJ;`V=bI|XR@kXXOVU{S?Ae)@5h7_9uZdFP*gMK$skf`*p zJyq_RU+3n_+B2JgaAfr?Tf@MpSNpLBFhf%z8j#s+kT>aE$mGh~XcV9kxzd~ZOWZU} z(T1~A3&Kdo_+`C?v5?*57P(2J1rlln4BtAN~^BDv|ZZ5j-`Q}U6KR&P|;j!dBm z$~PsxGv%Lwn!e7wDnhHrw34bp@1sYe@D`bmABMIFJ*f8x^`_Yx9$Q|kI(?O)2A5~U zLYgGs%srdtf?e;VeeefiC}qWkI((c;oQ&G1q8KNA({R|TJ(I8ukV-QS)y5d~@swoC z0$cR#j&JA+l56BB6{6enE2Z%iBTctp3l}l10&`VcDeOUt;0Fb8DS(X z*HcD?iEn3Ao>f22*$tknY$Il#nauw z3Zma%i5tj+jXb&lwur-Lt7X6sokJ_HHSTYVo*Q-0s zANlSnrE~=aj(TXk=F_;yHCT(ZXP>5VQPH{2DYK;$af!@7X?uTuo9WwQ*+tgxje_SG!pS~uhgQzhg)gWj}Tlw zA?+<2u`26F2YsKw&YjRCZEBKRV?!~(u8rEv02GGqCi(|fhxTo|`fR3+oU zdYg$AKj>oL4M)gOtZQa-42Aj4cch{83Vw`h*`*!bVH3JjyyxBXi7UAp)Q|d7zLZs2 zvs=A{y;1JvQPN5wA_#hskMzlZ@`;*NtC{Io>aZJRmRx)Peax=9hgeLv8--UI88!h4 z1z-H7}l{7H-+YRy@lkcg@jrpjGnm%1voSG zpkYn4Bc({cB`!m$d7rPBr8m(xCl>V&r)oPW(mniCDl;2b$CK!d1^UxszqQ&v73%MJ z%@XD3RR2bk$5k$-hDlxAXHyIu#I!%bi66F#?0{o{ z71fee;5r|=0yIZ5>hR;1%gGpOc7bKcntfYlnZI#Tn6x#CZ_z^JmLBy`O$g^(CmfzY z*DphY+HRP24QKZ~-3-u@JixK?_O(XF*TUOJVl*Zuu3u9VN?pS3Z6U!%OIZA=J2$~N zOHU1iToUr9oODQBiFvPHzwN7|M7{WFAhF_lm|7$zf7G+dsC;4r)W_eROzzhQ2Hw|t z1rHdp*kZDiD#9}b!&*t-J&%HQw!2;p`GX|d3)_F%VuJMBXeCKR(e3%W&nq@o`-U}a zPG;#{kmuUG2C7+Cos%TOOIO!ZX_()&(wnaqmh`~@uTKic^5$0(yIhhnbsIkZgfn=w z1SSF~W;-?x&!3((kukbWdnxz}sVYnFE0so)PI;oiVJl$oOYC+1>B4a+rzx2lE@rmp z7MoT)s?I$TZiJ+o&=|$R1XLPqRML*!3HZB zdn!R5Qj}jP<|6RYw8rO>5Vo+2SyBr0?wAsoW$U4>;@rmjf}e9!^dgds!9SHyra<9$ z*-Lqg5@UoAC`&}J{aL8McFtf67iSMEs0SC+(t=%sGnAX9pIe!etw?W_lVeDYQ~MA* z>J&TV^wc}b+v~@XHaZ5Tr+$bA8k?HN5S$e>I;0usiuEmA)qlR}>MSm&t7;-=RWAiY zBftA7*gEs&7;0r@<&!%~>Tr?2X^q$=tRi*^bbm<@;^Aq|IEPr|)M!+u3 z7>UKn8G=%=jf(FptBkJD^N|r0NjZyK^D27pSVbgFd-zAj5d%!a&849^F{=#Cgp<^! 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All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:54 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_BusBlock16IN_0_1 -prefix +// AckChecker_BusBlock16IN_0_1_ AckChecker_BusBlock16IN_0_0_sim_netlist.v +// Design : AckChecker_BusBlock16IN_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "AckChecker_BusBlock16IN_0_0,BusBlock16IN,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "BusBlock16IN,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_BusBlock16IN_0_1 + (Bus_16IN, + Out0, + Out1, + Out2, + Out3, + Out4, + Out5, + Out6, + Out7, + Out8, + Out9, + Out10, + Out11, + Out12, + Out13, + Out14, + Out15); + input [15:0]Bus_16IN; + output Out0; + output Out1; + output Out2; + output Out3; + output Out4; + output Out5; + output Out6; + output Out7; + output Out8; + output Out9; + output Out10; + output Out11; + output Out12; + output Out13; + output Out14; + output Out15; + + wire [15:0]Bus_16IN; + + assign Out0 = Bus_16IN[0]; + assign Out1 = Bus_16IN[1]; + assign Out10 = Bus_16IN[10]; + assign Out11 = Bus_16IN[11]; + assign Out12 = Bus_16IN[12]; + assign Out13 = Bus_16IN[13]; + assign Out14 = Bus_16IN[14]; + assign Out15 = Bus_16IN[15]; + assign Out2 = Bus_16IN[2]; + assign Out3 = Bus_16IN[3]; + assign Out4 = Bus_16IN[4]; + assign Out5 = Bus_16IN[5]; + assign Out6 = Bus_16IN[6]; + assign Out7 = Bus_16IN[7]; + assign Out8 = Bus_16IN[8]; + assign Out9 = Bus_16IN[9]; +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_sim_netlist.vhdl new file mode 100644 index 0000000..1f6d682 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_sim_netlist.vhdl @@ -0,0 +1,69 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:54 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_BusBlock16IN_0_1 -prefix +-- AckChecker_BusBlock16IN_0_1_ AckChecker_BusBlock16IN_0_0_sim_netlist.vhdl +-- Design : AckChecker_BusBlock16IN_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_BusBlock16IN_0_1 is + port ( + Bus_16IN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + Out0 : out STD_LOGIC; + Out1 : out STD_LOGIC; + Out2 : out STD_LOGIC; + Out3 : out STD_LOGIC; + Out4 : out STD_LOGIC; + Out5 : out STD_LOGIC; + Out6 : out STD_LOGIC; + Out7 : out STD_LOGIC; + Out8 : out STD_LOGIC; + Out9 : out STD_LOGIC; + Out10 : out STD_LOGIC; + Out11 : out STD_LOGIC; + Out12 : out STD_LOGIC; + Out13 : out STD_LOGIC; + Out14 : out STD_LOGIC; + Out15 : out STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_BusBlock16IN_0_1 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_BusBlock16IN_0_1 : entity is "AckChecker_BusBlock16IN_0_0,BusBlock16IN,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_BusBlock16IN_0_1 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_BusBlock16IN_0_1 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_BusBlock16IN_0_1 : entity is "BusBlock16IN,Vivado 2019.1"; +end AckChecker_BusBlock16IN_0_1; + +architecture STRUCTURE of AckChecker_BusBlock16IN_0_1 is + signal \^bus_16in\ : STD_LOGIC_VECTOR ( 15 downto 0 ); +begin + Out0 <= \^bus_16in\(0); + Out1 <= \^bus_16in\(1); + Out10 <= \^bus_16in\(10); + Out11 <= \^bus_16in\(11); + Out12 <= \^bus_16in\(12); + Out13 <= \^bus_16in\(13); + Out14 <= \^bus_16in\(14); + Out15 <= \^bus_16in\(15); + Out2 <= \^bus_16in\(2); + Out3 <= \^bus_16in\(3); + Out4 <= \^bus_16in\(4); + Out5 <= \^bus_16in\(5); + Out6 <= \^bus_16in\(6); + Out7 <= \^bus_16in\(7); + Out8 <= \^bus_16in\(8); + Out9 <= \^bus_16in\(9); + \^bus_16in\(15 downto 0) <= Bus_16IN(15 downto 0); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_stub.v new file mode 100644 index 0000000..c93f51c --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_stub.v @@ -0,0 +1,37 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:54 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_BusBlock16IN_0_1 -prefix +// AckChecker_BusBlock16IN_0_1_ AckChecker_BusBlock16IN_0_0_stub.v +// Design : AckChecker_BusBlock16IN_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "BusBlock16IN,Vivado 2019.1" *) +module AckChecker_BusBlock16IN_0_1(Bus_16IN, Out0, Out1, Out2, Out3, Out4, Out5, Out6, Out7, + Out8, Out9, Out10, Out11, Out12, Out13, Out14, Out15) +/* synthesis syn_black_box black_box_pad_pin="Bus_16IN[15:0],Out0,Out1,Out2,Out3,Out4,Out5,Out6,Out7,Out8,Out9,Out10,Out11,Out12,Out13,Out14,Out15" */; + input [15:0]Bus_16IN; + output Out0; + output Out1; + output Out2; + output Out3; + output Out4; + output Out5; + output Out6; + output Out7; + output Out8; + output Out9; + output Out10; + output Out11; + output Out12; + output Out13; + output Out14; + output Out15; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_stub.vhdl new file mode 100644 index 0000000..7d184ca --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_stub.vhdl @@ -0,0 +1,46 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:54 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_BusBlock16IN_0_1 -prefix +-- AckChecker_BusBlock16IN_0_1_ AckChecker_BusBlock16IN_0_0_stub.vhdl +-- Design : AckChecker_BusBlock16IN_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_BusBlock16IN_0_1 is + Port ( + Bus_16IN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + Out0 : out STD_LOGIC; + Out1 : out STD_LOGIC; + Out2 : out STD_LOGIC; + Out3 : out STD_LOGIC; + Out4 : out STD_LOGIC; + Out5 : out STD_LOGIC; + Out6 : out STD_LOGIC; + Out7 : out STD_LOGIC; + Out8 : out STD_LOGIC; + Out9 : out STD_LOGIC; + Out10 : out STD_LOGIC; + Out11 : out STD_LOGIC; + Out12 : out STD_LOGIC; + Out13 : out STD_LOGIC; + Out14 : out STD_LOGIC; + Out15 : out STD_LOGIC + ); + +end AckChecker_BusBlock16IN_0_1; + +architecture stub of AckChecker_BusBlock16IN_0_1 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "Bus_16IN[15:0],Out0,Out1,Out2,Out3,Out4,Out5,Out6,Out7,Out8,Out9,Out10,Out11,Out12,Out13,Out14,Out15"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "BusBlock16IN,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_2/AckChecker_BusBlock16IN_0_2.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_2/AckChecker_BusBlock16IN_0_2.dcp new file mode 100644 index 0000000000000000000000000000000000000000..979afff1f92bbfe390fd1563114d5c1b1b237c52 GIT binary patch literal 5506 zcma)=bySq^w#NsgI|jiK=^Plk73my0h7yOC?idi2kx;t3B!3_vDIg&o1CkC1C@IpZ zC@p6=-m}hmV<9QAc_M3XkG^Z z7%|_dcx&>yyTtTtephK)U@CNZ~;DB8@tvtGp~GAVBh>X@E-&rYzPmu zpVBZUKzLhO-?7-v$thLdzFGzMrCjuF(fLQsaz(d#OiE1eCxqQig~N~h9@=arNCtYR zoa6eYq?xvAqRnuJsb0U!D>8K?m0b}t(_p1KdVwTzJU{XcYC!lP?k}D5z1W!{)83xQ zYrdaYFcl-NOS*iE-6QJJ4rQWfPWKNf9L)*P3o$ttfc&VvyuP+on8;p9E8aTs^o%PL zGH^LggvMt#-avaR%c8aSF^Qg=0!*;#XR~%vdt@uVCVrvJ+AO|#aB3g7d)w{xj1SJ_ ze!Iex-u`VZz18Prx$ls9*j@j0AIf?%CUJT>1{&n3p0%WN_bLj)A)GHH^ziJoQFcP< zJ-NBNtQ(5zK*~$Ib4Egry%6_DTDrX1vLrxl^`| zJ%^4!77rHj%i2E%Z@EnhYcTF-9kHz>W@+$ca<-Vx&ajp$wU7(mxuIa~{Nw$C^J{{+ z*&oZ-!&gVs$ljq27EpoVjMh>Ow@CVooMmuC@TQBCAmtj>Zk2*nY1d=>QUzVk!!yV? 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z8u~2$CfA@!>P<)OOt-dcRliyZ|+|mx!_Iosi ze%LqW$T=GS3lJiHbZ{mbwH=K$RLZ`3)(7GH3L|pP1{Q(bHXugfA>~b5tsO=9-C1ZDY~SdxD%+Q01C@$i+^cT;UoIEvpSizO{VMOO zFZ`D`O!oibVO-)r$p2l+E`h&Z9T4P-5wrghHXSG~rse MIXED -3 - TRUE TRUE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_2/AckChecker_BusBlock16IN_0_2.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_2/AckChecker_BusBlock16IN_0_2.xml index 23cc2f4..8f242b6 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_2/AckChecker_BusBlock16IN_0_2.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_2/AckChecker_BusBlock16IN_0_2.xml @@ -95,6 +95,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:37:27 UTC 2023 + + + outputProductCRC + 9:60f2efd2 + + + @@ -355,6 +373,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_BusBlock16IN_0_2.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_BusBlock16IN_0_2_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_BusBlock16IN_0_2_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_BusBlock16IN_0_2_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_BusBlock16IN_0_2_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + BusBlock16IN_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_2/AckChecker_BusBlock16IN_0_2_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_2/AckChecker_BusBlock16IN_0_2_sim_netlist.v new file mode 100644 index 0000000..6b3bdb6 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_2/AckChecker_BusBlock16IN_0_2_sim_netlist.v @@ -0,0 +1,142 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:54 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_BusBlock16IN_0_2 -prefix +// AckChecker_BusBlock16IN_0_2_ AckChecker_BusBlock16IN_0_0_sim_netlist.v +// Design : AckChecker_BusBlock16IN_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "AckChecker_BusBlock16IN_0_0,BusBlock16IN,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "BusBlock16IN,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_BusBlock16IN_0_2 + (Bus_16IN, + Out0, + Out1, + Out2, + Out3, + Out4, + Out5, + Out6, + Out7, + Out8, + Out9, + Out10, + Out11, + Out12, + Out13, + Out14, + Out15); + input [15:0]Bus_16IN; + output Out0; + output Out1; + output Out2; + output Out3; + output Out4; + output Out5; + output Out6; + output Out7; + output Out8; + output Out9; + output Out10; + output Out11; + output Out12; + output Out13; + output Out14; + output Out15; + + wire [15:0]Bus_16IN; + + assign Out0 = Bus_16IN[0]; + assign Out1 = Bus_16IN[1]; + assign Out10 = Bus_16IN[10]; + assign Out11 = Bus_16IN[11]; + assign Out12 = Bus_16IN[12]; + assign Out13 = Bus_16IN[13]; + assign Out14 = Bus_16IN[14]; + assign Out15 = Bus_16IN[15]; + assign Out2 = Bus_16IN[2]; + assign Out3 = Bus_16IN[3]; + assign Out4 = Bus_16IN[4]; + assign Out5 = Bus_16IN[5]; + assign Out6 = Bus_16IN[6]; + assign Out7 = Bus_16IN[7]; + assign Out8 = Bus_16IN[8]; + assign Out9 = Bus_16IN[9]; +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_2/AckChecker_BusBlock16IN_0_2_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_2/AckChecker_BusBlock16IN_0_2_sim_netlist.vhdl new file mode 100644 index 0000000..969b775 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_2/AckChecker_BusBlock16IN_0_2_sim_netlist.vhdl @@ -0,0 +1,69 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:54 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_BusBlock16IN_0_2 -prefix +-- AckChecker_BusBlock16IN_0_2_ AckChecker_BusBlock16IN_0_0_sim_netlist.vhdl +-- Design : AckChecker_BusBlock16IN_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_BusBlock16IN_0_2 is + port ( + Bus_16IN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + Out0 : out STD_LOGIC; + Out1 : out STD_LOGIC; + Out2 : out STD_LOGIC; + Out3 : out STD_LOGIC; + Out4 : out STD_LOGIC; + Out5 : out STD_LOGIC; + Out6 : out STD_LOGIC; + Out7 : out STD_LOGIC; + Out8 : out STD_LOGIC; + Out9 : out STD_LOGIC; + Out10 : out STD_LOGIC; + Out11 : out STD_LOGIC; + Out12 : out STD_LOGIC; + Out13 : out STD_LOGIC; + Out14 : out STD_LOGIC; + Out15 : out STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_BusBlock16IN_0_2 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_BusBlock16IN_0_2 : entity is "AckChecker_BusBlock16IN_0_0,BusBlock16IN,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_BusBlock16IN_0_2 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_BusBlock16IN_0_2 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_BusBlock16IN_0_2 : entity is "BusBlock16IN,Vivado 2019.1"; +end AckChecker_BusBlock16IN_0_2; + +architecture STRUCTURE of AckChecker_BusBlock16IN_0_2 is + signal \^bus_16in\ : STD_LOGIC_VECTOR ( 15 downto 0 ); +begin + Out0 <= \^bus_16in\(0); + Out1 <= \^bus_16in\(1); + Out10 <= \^bus_16in\(10); + Out11 <= \^bus_16in\(11); + Out12 <= \^bus_16in\(12); + Out13 <= \^bus_16in\(13); + Out14 <= \^bus_16in\(14); + Out15 <= \^bus_16in\(15); + Out2 <= \^bus_16in\(2); + Out3 <= \^bus_16in\(3); + Out4 <= \^bus_16in\(4); + Out5 <= \^bus_16in\(5); + Out6 <= \^bus_16in\(6); + Out7 <= \^bus_16in\(7); + Out8 <= \^bus_16in\(8); + Out9 <= \^bus_16in\(9); + \^bus_16in\(15 downto 0) <= Bus_16IN(15 downto 0); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_2/AckChecker_BusBlock16IN_0_2_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_2/AckChecker_BusBlock16IN_0_2_stub.v new file mode 100644 index 0000000..fe388e6 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_2/AckChecker_BusBlock16IN_0_2_stub.v @@ -0,0 +1,37 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:54 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_BusBlock16IN_0_2 -prefix +// AckChecker_BusBlock16IN_0_2_ AckChecker_BusBlock16IN_0_0_stub.v +// Design : AckChecker_BusBlock16IN_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "BusBlock16IN,Vivado 2019.1" *) +module AckChecker_BusBlock16IN_0_2(Bus_16IN, Out0, Out1, Out2, Out3, Out4, Out5, Out6, Out7, + Out8, Out9, Out10, Out11, Out12, Out13, Out14, Out15) +/* synthesis syn_black_box black_box_pad_pin="Bus_16IN[15:0],Out0,Out1,Out2,Out3,Out4,Out5,Out6,Out7,Out8,Out9,Out10,Out11,Out12,Out13,Out14,Out15" */; + input [15:0]Bus_16IN; + output Out0; + output Out1; + output Out2; + output Out3; + output Out4; + output Out5; + output Out6; + output Out7; + output Out8; + output Out9; + output Out10; + output Out11; + output Out12; + output Out13; + output Out14; + output Out15; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_2/AckChecker_BusBlock16IN_0_2_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_2/AckChecker_BusBlock16IN_0_2_stub.vhdl new file mode 100644 index 0000000..e69d7b6 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_2/AckChecker_BusBlock16IN_0_2_stub.vhdl @@ -0,0 +1,46 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:54 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_BusBlock16IN_0_2 -prefix +-- AckChecker_BusBlock16IN_0_2_ AckChecker_BusBlock16IN_0_0_stub.vhdl +-- Design : AckChecker_BusBlock16IN_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_BusBlock16IN_0_2 is + Port ( + Bus_16IN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + Out0 : out STD_LOGIC; + Out1 : out STD_LOGIC; + Out2 : out STD_LOGIC; + Out3 : out STD_LOGIC; + Out4 : out STD_LOGIC; + Out5 : out STD_LOGIC; + Out6 : out STD_LOGIC; + Out7 : out STD_LOGIC; + Out8 : out STD_LOGIC; + Out9 : out STD_LOGIC; + Out10 : out STD_LOGIC; + Out11 : out STD_LOGIC; + Out12 : out STD_LOGIC; + Out13 : out STD_LOGIC; + Out14 : out STD_LOGIC; + Out15 : out STD_LOGIC + ); + +end AckChecker_BusBlock16IN_0_2; + +architecture stub of AckChecker_BusBlock16IN_0_2 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "Bus_16IN[15:0],Out0,Out1,Out2,Out3,Out4,Out5,Out6,Out7,Out8,Out9,Out10,Out11,Out12,Out13,Out14,Out15"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "BusBlock16IN,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_1_0/AckChecker_BusBlock16IN_1_0.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_1_0/AckChecker_BusBlock16IN_1_0.dcp new file mode 100644 index 0000000000000000000000000000000000000000..cae46ea67764ce6ae08b4a4bbfe561ae93d7942a GIT binary patch literal 5508 zcma)=cQl;s*2X8I*APMwy$+)rB@sP?(aUHNUG#1YkuVVwz4sRNC5ReCiC#wM9fIgY zuZig5jFa!IvtoVUo9}+sUe7%9$8YUt_MYpy_pJ%NiA@Or0Pq3N9_PX`@vM7Au>ku2SKp1x~YJv0H3v$O;fV5M~)I@_uK{LUkC!& z050u*V(o|k!Tm=%_60T$4oPyh6%d?vvJv-1=bksn=HKfyEHru&8~iZI)b!Z;>W^1ZG5WD>ZV?ywGoR8uJ7&RH3V#a|e{&>8oIppGG)fid!RJM6%A(cUjg4cnf2B zjo1xo6RbvfP@^Sm(BfF$ZIwz-AZoOfjp*IlQrXHTWX$hpVd^fU9xGt&Qa3;+aK=Bm zf)Qe9HQBxYwUtoYH;2J=Pkzr>#&2s}BNJMN z5)aKwVz&=f7-&;CUmc;6e?i6tMN@|7~!6xBVs`<$KX(5QqWaPoJpfC(vamivde!PDUeM6wUldH3Lir4U)h=L7b@LqU*Nc zk5;f7?x&r09OaZes_52o-d~X7Rx<3!!b_3Y;A-+y>a$Y@Z5hZnQ2cf2cpzQXXFW%w zPV8{nT^tkCpoKnhP24z(nm%T$p4O>AsT5ln1`op%YhHtFen!l^^2j}}rE~ojby@Ve zvVM+cNbt*T-c6B!bu9TT{rX292##4Sh#=bsA#Ow9WGDIlx$#&Dn~pZoQp0>Ob5C)# zNcT3vYey!9WW!pZ@)ONchy<-sdu>vt;2;NwiD>b&^q8!IMXv{^Grl4?ue&W2`}*p# z2VNwlw>910_SaSOf@RK*_&emSG%g?WYyPG4 z<*m%C9PZu6A9~aedCKU7tz!mBda z!wc0D5YZFR1ei0m;YMg7XhylBi2%Rn6B;$JoOS~M0Au}G0o|?4pGUVkqXljS+ZE}S zq6p1Pv9Xcv^G5NBiLj=86GgdlJ7pOuCM%z9JB!lWkV8bncEaj>1%ffXBwF095^~w^ zcPZ@=nf|q_(mnI*)O2ZUW+N1Zt(IkL5E$vd6QiGEU;<`>nN0?HQ%}7aTX-FX12v?D zysA4RO(T@3KR&Xgh+vPK*PR)8vz7Eoehh0y*-q`SuJoQYGPk-&{&VRD69L%~?a)xO zH*U(NY@spEH;B-&($7E*UuQvO@ZtfpluFS1sG&%*SO4cdnbrqK=9epv z{4-Qh3P2*PG1|4<D?tk@8TkK+krkvk0ZqtvhJ_nNgP;^zUN0;{2?EI2flD;?1)Cb1jd?Z(9++SOkaGld*i-$bkosw^{&M7|nr)-L390CKs0BfZD}HQg*?>QD6b;Qhke3jb4L_@wwqmPmrxdIIN(Rh^(O z3Eo8~?xZ3NDJMxD5*fD#pgg)Hx*hE+~)Iw)utV$2&x>c)Oq2 zvM@tjSP$E=&(QIYjQk2U<<#uXeC_OTrtEcD7nxn3>`TkkJHA%?A01DccP-&9-AJ7ccUqabxY1 z&JW@qD6o&`YE`TqI6dZQzH16?!P8dg+_fkQVnA}=HoKwfvaxw~LS|(s?&DseNq-Av zt;IS-e)gEUyL8C9v=<-t9Zj4&z4>qfJIK|moM}k(c~Y?@YC~G_@U2wF{0Yc=vEW3E zv_e8TW7lSbgZoy{>5dx-*g&#lVr>M6^VN5(f%I}=f(yC1O`SnwmLsxfozn>mx$2B` zJ;_U@l{P%qFH&A9bqhc=lW&s;JJYy zBAh`Zyc7rPACKu)!`ax!Mz*Py1XRUNtWuX8Gb&ps{!Yp|N4jouNoL(&=4&gX1XA&K zz4~@%YGN{n)xdsOR-Qb*&{XFKQJ#X4FF36U32dp*{b5qgq(qywEh66|!l>#^$wBW8 zm98nG<}0s~sx+wL*-jE6S1z#I8glt z^xBC;AkcMbKvc_(u(tmArk9&OUZSUIjDmfQq0xod#=azzv9asd)c6vYFne2%V8b~g z;ndB`V3N5f`e2v%{Bb93DpyLu^OvuCYVYBm{?vc4;JTMuB&o39wZ^V=_!O#lYhx^_ zR}UI^Q_~-X9I{;Ju#+w#GciqRrhfY@GNrxM^?V=z_Mo+}^`|W%Os|Dmib?|CUbyq5 ze08yBQ2puQB&!SdR13VXihI#H@j+P0;z}wL=i6phi^am?o)o~#!@`lg>4k(2mn1@+ z`j0N>h}rP4B<`03<5i1taiK z5wr^jrWA}kc|iN7D8EqBMdXD^wa*zv%FH5RaS7DBZCqp$*u`84+8|rHm2+A2Jc5QT zAeBP4K=F6kOMZ$fO!T<2A$EIOw?DX`aB{^SDF&hGD(8H{I`_HZ9|RINhTG?HA>K_5 zI*%MDEiMFnV&)nJ-pr7l zdEfKG@{(>-z9H*-Rosf$BfH_KWG0VICp2-sEJ>5U;~OOgZhkj=DfY(W?=!@$JH_;d zkyZ3V9*sS2nM*9)ee_8Z?;nYFeR$L~QAk54YME=#>&ZGpd|7mi^Lra9(Kd;hV5-z{ z^N*fy`m0K|R*ui(v>e(5D1+v{^YA@X8y*$kMnAOEe^2@?!L% zt#z0SayLCLt$n~1Kjy*bP(}^fJx5w%$ivK5G5(Krq)g=KKt;p00&?AQb1EI`#Ak)e zDJps-%JkjLLR1bKv+yHz*k%+P3k{y7ONCJozF_vp_vW%;YaO<&l!mGHhAKw$Oebs) z_mTSe^H3lOznKOACQD1`F^{!VaV9=hDh3PUjP7I1WjA(4?qd9vUKG`I62+`+`{~&eqRak1J1das(g<7tK49K zR|OfXs>5D{#R1aBBA2#<-w`bMAh*>cqq4gGn$mm9Fnn?Hl-~bn`WZ-L=Zidnx`J+e zRguj`FkG5Wb(;F+5k%dP1ne&Yy~)#Cmuw#lrt?b^FKT|prKBH8jbyqXU1US@I#IB? zdb8@2QWEsQIoAFhJ3Tm2A{yLs*8raoHc40RXg1}2csy9sLdek~)bAE$2w_&8Q4j(j z#DAqvAFOwNxyyQH57}fKO${+RH9G&EWPZ2Kuf}D&IPHnXu~x4~qyKIU{<27dj(ejR zSb0UDNdDDDX>y)hv3NETe#{UaPOKKy?IdzTggv zJIoac#345m59)r8)_sOA5C)^t^HOfvv#kXN7naPo8=c72SzLi~cc zV>Y}01iKn4uhXs%fmgJvRfELBwCX?6FeBl0*!9Wd3iK#p z`)4F(NVpEWJ{4TSu2v0l_75_vZuIu`WK7~ BKmPy# literal 0 HcmV?d00001 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_1_0/AckChecker_BusBlock16IN_1_0.xci b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_1_0/AckChecker_BusBlock16IN_1_0.xci index 3d56261..410023b 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_1_0/AckChecker_BusBlock16IN_1_0.xci +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_1_0/AckChecker_BusBlock16IN_1_0.xci @@ -19,7 +19,6 @@ MIXED -3 - TRUE TRUE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_1_0/AckChecker_BusBlock16IN_1_0.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_1_0/AckChecker_BusBlock16IN_1_0.xml index 210a16f..a46f42c 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_1_0/AckChecker_BusBlock16IN_1_0.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_1_0/AckChecker_BusBlock16IN_1_0.xml @@ -95,6 +95,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:37:35 UTC 2023 + + + outputProductCRC + 9:060e4c57 + + + @@ -355,6 +373,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_BusBlock16IN_1_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_BusBlock16IN_1_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_BusBlock16IN_1_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_BusBlock16IN_1_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_BusBlock16IN_1_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + BusBlock16IN_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_1_0/AckChecker_BusBlock16IN_1_0_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_1_0/AckChecker_BusBlock16IN_1_0_sim_netlist.v new file mode 100644 index 0000000..8f7d7f6 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_1_0/AckChecker_BusBlock16IN_1_0_sim_netlist.v @@ -0,0 +1,142 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:54 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_BusBlock16IN_1_0 -prefix +// AckChecker_BusBlock16IN_1_0_ AckChecker_BusBlock16IN_0_0_sim_netlist.v +// Design : AckChecker_BusBlock16IN_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "AckChecker_BusBlock16IN_0_0,BusBlock16IN,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "BusBlock16IN,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_BusBlock16IN_1_0 + (Bus_16IN, + Out0, + Out1, + Out2, + Out3, + Out4, + Out5, + Out6, + Out7, + Out8, + Out9, + Out10, + Out11, + Out12, + Out13, + Out14, + Out15); + input [15:0]Bus_16IN; + output Out0; + output Out1; + output Out2; + output Out3; + output Out4; + output Out5; + output Out6; + output Out7; + output Out8; + output Out9; + output Out10; + output Out11; + output Out12; + output Out13; + output Out14; + output Out15; + + wire [15:0]Bus_16IN; + + assign Out0 = Bus_16IN[0]; + assign Out1 = Bus_16IN[1]; + assign Out10 = Bus_16IN[10]; + assign Out11 = Bus_16IN[11]; + assign Out12 = Bus_16IN[12]; + assign Out13 = Bus_16IN[13]; + assign Out14 = Bus_16IN[14]; + assign Out15 = Bus_16IN[15]; + assign Out2 = Bus_16IN[2]; + assign Out3 = Bus_16IN[3]; + assign Out4 = Bus_16IN[4]; + assign Out5 = Bus_16IN[5]; + assign Out6 = Bus_16IN[6]; + assign Out7 = Bus_16IN[7]; + assign Out8 = Bus_16IN[8]; + assign Out9 = Bus_16IN[9]; +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_1_0/AckChecker_BusBlock16IN_1_0_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_1_0/AckChecker_BusBlock16IN_1_0_sim_netlist.vhdl new file mode 100644 index 0000000..2feb8d5 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_1_0/AckChecker_BusBlock16IN_1_0_sim_netlist.vhdl @@ -0,0 +1,69 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:54 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_BusBlock16IN_1_0 -prefix +-- AckChecker_BusBlock16IN_1_0_ AckChecker_BusBlock16IN_0_0_sim_netlist.vhdl +-- Design : AckChecker_BusBlock16IN_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_BusBlock16IN_1_0 is + port ( + Bus_16IN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + Out0 : out STD_LOGIC; + Out1 : out STD_LOGIC; + Out2 : out STD_LOGIC; + Out3 : out STD_LOGIC; + Out4 : out STD_LOGIC; + Out5 : out STD_LOGIC; + Out6 : out STD_LOGIC; + Out7 : out STD_LOGIC; + Out8 : out STD_LOGIC; + Out9 : out STD_LOGIC; + Out10 : out STD_LOGIC; + Out11 : out STD_LOGIC; + Out12 : out STD_LOGIC; + Out13 : out STD_LOGIC; + Out14 : out STD_LOGIC; + Out15 : out STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_BusBlock16IN_1_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_BusBlock16IN_1_0 : entity is "AckChecker_BusBlock16IN_0_0,BusBlock16IN,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_BusBlock16IN_1_0 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_BusBlock16IN_1_0 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_BusBlock16IN_1_0 : entity is "BusBlock16IN,Vivado 2019.1"; +end AckChecker_BusBlock16IN_1_0; + +architecture STRUCTURE of AckChecker_BusBlock16IN_1_0 is + signal \^bus_16in\ : STD_LOGIC_VECTOR ( 15 downto 0 ); +begin + Out0 <= \^bus_16in\(0); + Out1 <= \^bus_16in\(1); + Out10 <= \^bus_16in\(10); + Out11 <= \^bus_16in\(11); + Out12 <= \^bus_16in\(12); + Out13 <= \^bus_16in\(13); + Out14 <= \^bus_16in\(14); + Out15 <= \^bus_16in\(15); + Out2 <= \^bus_16in\(2); + Out3 <= \^bus_16in\(3); + Out4 <= \^bus_16in\(4); + Out5 <= \^bus_16in\(5); + Out6 <= \^bus_16in\(6); + Out7 <= \^bus_16in\(7); + Out8 <= \^bus_16in\(8); + Out9 <= \^bus_16in\(9); + \^bus_16in\(15 downto 0) <= Bus_16IN(15 downto 0); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_1_0/AckChecker_BusBlock16IN_1_0_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_1_0/AckChecker_BusBlock16IN_1_0_stub.v new file mode 100644 index 0000000..33d1e5a --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_1_0/AckChecker_BusBlock16IN_1_0_stub.v @@ -0,0 +1,37 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:54 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_BusBlock16IN_1_0 -prefix +// AckChecker_BusBlock16IN_1_0_ AckChecker_BusBlock16IN_0_0_stub.v +// Design : AckChecker_BusBlock16IN_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "BusBlock16IN,Vivado 2019.1" *) +module AckChecker_BusBlock16IN_1_0(Bus_16IN, Out0, Out1, Out2, Out3, Out4, Out5, Out6, Out7, + Out8, Out9, Out10, Out11, Out12, Out13, Out14, Out15) +/* synthesis syn_black_box black_box_pad_pin="Bus_16IN[15:0],Out0,Out1,Out2,Out3,Out4,Out5,Out6,Out7,Out8,Out9,Out10,Out11,Out12,Out13,Out14,Out15" */; + input [15:0]Bus_16IN; + output Out0; + output Out1; + output Out2; + output Out3; + output Out4; + output Out5; + output Out6; + output Out7; + output Out8; + output Out9; + output Out10; + output Out11; + output Out12; + output Out13; + output Out14; + output Out15; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_1_0/AckChecker_BusBlock16IN_1_0_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_1_0/AckChecker_BusBlock16IN_1_0_stub.vhdl new file mode 100644 index 0000000..00e32fe --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_1_0/AckChecker_BusBlock16IN_1_0_stub.vhdl @@ -0,0 +1,46 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:54 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_BusBlock16IN_1_0 -prefix +-- AckChecker_BusBlock16IN_1_0_ AckChecker_BusBlock16IN_0_0_stub.vhdl +-- Design : AckChecker_BusBlock16IN_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_BusBlock16IN_1_0 is + Port ( + Bus_16IN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + Out0 : out STD_LOGIC; + Out1 : out STD_LOGIC; + Out2 : out STD_LOGIC; + Out3 : out STD_LOGIC; + Out4 : out STD_LOGIC; + Out5 : out STD_LOGIC; + Out6 : out STD_LOGIC; + Out7 : out STD_LOGIC; + Out8 : out STD_LOGIC; + Out9 : out STD_LOGIC; + Out10 : out STD_LOGIC; + Out11 : out STD_LOGIC; + Out12 : out STD_LOGIC; + Out13 : out STD_LOGIC; + Out14 : out STD_LOGIC; + Out15 : out STD_LOGIC + ); + +end AckChecker_BusBlock16IN_1_0; + +architecture stub of AckChecker_BusBlock16IN_1_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "Bus_16IN[15:0],Out0,Out1,Out2,Out3,Out4,Out5,Out6,Out7,Out8,Out9,Out10,Out11,Out12,Out13,Out14,Out15"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "BusBlock16IN,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0.dcp new file mode 100644 index 0000000000000000000000000000000000000000..692ab15f557f3b012e1764eda423c667206b6df8 GIT binary patch literal 5508 zcma)=cT`i`w#FmUs~`vh(rX}eLQ$kk3B80S(vjW?0a1t)rT5-M$^ikX0#c-x(8CD` zNC)Xvk&fJOeRtd;9a40Dup8_Baokjc3y*iVXm$ z-vIy^G2hBsIm+AFSUK8wn8|s2$~n1OISPVRG|U9d1o&*MZJSd~Jl`r)_RL*S{skw1 z4&u`8C)c3_2<|`9bttrTbWD-6t5m{yCmVHNbnbbhY{9)Qqax!c@u3e>%*>8`o>_0j zOZa;wU*N!!Q;nO|(Iz-U6dwk13yd8|WLCf?YOEB;ZxDnI7ss%`I=DCd$>Igyo1H0A z&F!(=#wQ7R6VYPYB+K{M-6NmxkSB;{cOFV&tB=vX0n0iA!l}$p@J1Z8#NPKBbxEl@$#kDX7EgdQhK=ETJEo> ze|94C*%co5@@;AAuDl@489?M>b^O(NB;&!D$m!|eua~WS-jv4OtsrOy;(Q~ngKMja zv=vJ0%E{Sf-B3`abSesBCE^w~sL)d8dSF@_OtF0dckf?((dd>yQ2aT5pQJZ(%8Sg2 zJ9+EGWAK>P{OJN-N$Z!OE!S~jHOBqSW44uqOf|j?&L-oTDb`}eCNjYXcjc{|4*#Ba z`hY(>bGUpbY;`1+bO3oUkMs{?w34j5N8DrJB#kYCJ6V_rDpjj=Ef=gvy%W=uBItY( zmQJ=|rgKlLgtQ961&d!u?f6{BD@z-T%Urn6klfC)d#8t_hy!h!YaPB}dkZZA@ zwHJhw6qFUit=z;p^TMFrdCUvIP>rr}$s1Jhps$8XenN3T6}M1dL~_nDcUjg4d5hwC zjoFQ8ldMrZ$k9?ZNJ%{JwrZ6Z5II`LM)YoNseENqY0Up;QTi^UJ}Y4DQZG<9XeJ=F zl2OUXda`H#Ya5}C-&+Q=J^4Ko8UL+u&1|gMF{Z5=YSOi3uZNwtx|7rZU7oR@Q_U2G zu+fyEEHvM$b+&FzwXn&tkOS57S1EF<6w;ORsW=>#DeP^+Xj!!L1mcn*Xf8;8go2+1 zOClsch20@sVX$4{d=*6{|ALGQf~E*FRt#(SC{tD?<4j&;N?DXZgythclOrS*5mO&! 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All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:54 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_BusBlock16IN_2_0 -prefix +// AckChecker_BusBlock16IN_2_0_ AckChecker_BusBlock16IN_0_0_sim_netlist.v +// Design : AckChecker_BusBlock16IN_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "AckChecker_BusBlock16IN_0_0,BusBlock16IN,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "BusBlock16IN,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_BusBlock16IN_2_0 + (Bus_16IN, + Out0, + Out1, + Out2, + Out3, + Out4, + Out5, + Out6, + Out7, + Out8, + Out9, + Out10, + Out11, + Out12, + Out13, + Out14, + Out15); + input [15:0]Bus_16IN; + output Out0; + output Out1; + output Out2; + output Out3; + output Out4; + output Out5; + output Out6; + output Out7; + output Out8; + output Out9; + output Out10; + output Out11; + output Out12; + output Out13; + output Out14; + output Out15; + + wire [15:0]Bus_16IN; + + assign Out0 = Bus_16IN[0]; + assign Out1 = Bus_16IN[1]; + assign Out10 = Bus_16IN[10]; + assign Out11 = Bus_16IN[11]; + assign Out12 = Bus_16IN[12]; + assign Out13 = Bus_16IN[13]; + assign Out14 = Bus_16IN[14]; + assign Out15 = Bus_16IN[15]; + assign Out2 = Bus_16IN[2]; + assign Out3 = Bus_16IN[3]; + assign Out4 = Bus_16IN[4]; + assign Out5 = Bus_16IN[5]; + assign Out6 = Bus_16IN[6]; + assign Out7 = Bus_16IN[7]; + assign Out8 = Bus_16IN[8]; + assign Out9 = Bus_16IN[9]; +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_sim_netlist.vhdl new file mode 100644 index 0000000..5f6da68 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_sim_netlist.vhdl @@ -0,0 +1,69 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:54 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_BusBlock16IN_2_0 -prefix +-- AckChecker_BusBlock16IN_2_0_ AckChecker_BusBlock16IN_0_0_sim_netlist.vhdl +-- Design : AckChecker_BusBlock16IN_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_BusBlock16IN_2_0 is + port ( + Bus_16IN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + Out0 : out STD_LOGIC; + Out1 : out STD_LOGIC; + Out2 : out STD_LOGIC; + Out3 : out STD_LOGIC; + Out4 : out STD_LOGIC; + Out5 : out STD_LOGIC; + Out6 : out STD_LOGIC; + Out7 : out STD_LOGIC; + Out8 : out STD_LOGIC; + Out9 : out STD_LOGIC; + Out10 : out STD_LOGIC; + Out11 : out STD_LOGIC; + Out12 : out STD_LOGIC; + Out13 : out STD_LOGIC; + Out14 : out STD_LOGIC; + Out15 : out STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_BusBlock16IN_2_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_BusBlock16IN_2_0 : entity is "AckChecker_BusBlock16IN_0_0,BusBlock16IN,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_BusBlock16IN_2_0 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_BusBlock16IN_2_0 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_BusBlock16IN_2_0 : entity is "BusBlock16IN,Vivado 2019.1"; +end AckChecker_BusBlock16IN_2_0; + +architecture STRUCTURE of AckChecker_BusBlock16IN_2_0 is + signal \^bus_16in\ : STD_LOGIC_VECTOR ( 15 downto 0 ); +begin + Out0 <= \^bus_16in\(0); + Out1 <= \^bus_16in\(1); + Out10 <= \^bus_16in\(10); + Out11 <= \^bus_16in\(11); + Out12 <= \^bus_16in\(12); + Out13 <= \^bus_16in\(13); + Out14 <= \^bus_16in\(14); + Out15 <= \^bus_16in\(15); + Out2 <= \^bus_16in\(2); + Out3 <= \^bus_16in\(3); + Out4 <= \^bus_16in\(4); + Out5 <= \^bus_16in\(5); + Out6 <= \^bus_16in\(6); + Out7 <= \^bus_16in\(7); + Out8 <= \^bus_16in\(8); + Out9 <= \^bus_16in\(9); + \^bus_16in\(15 downto 0) <= Bus_16IN(15 downto 0); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_stub.v new file mode 100644 index 0000000..b4b27f5 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_stub.v @@ -0,0 +1,37 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:54 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_BusBlock16IN_2_0 -prefix +// AckChecker_BusBlock16IN_2_0_ AckChecker_BusBlock16IN_0_0_stub.v +// Design : AckChecker_BusBlock16IN_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "BusBlock16IN,Vivado 2019.1" *) +module AckChecker_BusBlock16IN_2_0(Bus_16IN, Out0, Out1, Out2, Out3, Out4, Out5, Out6, Out7, + Out8, Out9, Out10, Out11, Out12, Out13, Out14, Out15) +/* synthesis syn_black_box black_box_pad_pin="Bus_16IN[15:0],Out0,Out1,Out2,Out3,Out4,Out5,Out6,Out7,Out8,Out9,Out10,Out11,Out12,Out13,Out14,Out15" */; + input [15:0]Bus_16IN; + output Out0; + output Out1; + output Out2; + output Out3; + output Out4; + output Out5; + output Out6; + output Out7; + output Out8; + output Out9; + output Out10; + output Out11; + output Out12; + output Out13; + output Out14; + output Out15; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_stub.vhdl new file mode 100644 index 0000000..0b75027 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_stub.vhdl @@ -0,0 +1,46 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:54 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_BusBlock16IN_2_0 -prefix +-- AckChecker_BusBlock16IN_2_0_ AckChecker_BusBlock16IN_0_0_stub.vhdl +-- Design : AckChecker_BusBlock16IN_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_BusBlock16IN_2_0 is + Port ( + Bus_16IN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + Out0 : out STD_LOGIC; + Out1 : out STD_LOGIC; + Out2 : out STD_LOGIC; + Out3 : out STD_LOGIC; + Out4 : out STD_LOGIC; + Out5 : out STD_LOGIC; + Out6 : out STD_LOGIC; + Out7 : out STD_LOGIC; + Out8 : out STD_LOGIC; + Out9 : out STD_LOGIC; + Out10 : out STD_LOGIC; + Out11 : out STD_LOGIC; + Out12 : out STD_LOGIC; + Out13 : out STD_LOGIC; + Out14 : out STD_LOGIC; + Out15 : out STD_LOGIC + ); + +end AckChecker_BusBlock16IN_2_0; + +architecture stub of AckChecker_BusBlock16IN_2_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "Bus_16IN[15:0],Out0,Out1,Out2,Out3,Out4,Out5,Out6,Out7,Out8,Out9,Out10,Out11,Out12,Out13,Out14,Out15"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "BusBlock16IN,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0.dcp new file mode 100644 index 0000000000000000000000000000000000000000..a91967868a7deeb715bf5e298211613ae18daecb GIT binary patch literal 5508 zcma)=cT`i`w#FmUs~`vh(mRAsD2j9`p_kA^I?_8KAPSM9^iJrAlmh}%1*AwXp@$O? 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zynjYwhJ@>|>r=rM>}u7*Xa4|$xn5^oH|{IWuXlY#{EvxUv+?WP>wf!RE*Hr^bARdj zb>4Mn_%CmW^#8-d_{4vZ|GSu70e`(ZAjlOXXa6H@+F%?^%>e*H%!Q3{B}a;@r+)zv Ccs`o| literal 0 HcmV?d00001 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0.xci b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0.xci index ba08fc2..915568e 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0.xci +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0.xci @@ -19,7 +19,6 @@ MIXED -3 - TRUE TRUE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0.xml index 05c88ee..194bdbd 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0.xml @@ -95,6 +95,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:37:35 UTC 2023 + + + outputProductCRC + 9:9bd53dde + + + @@ -355,6 +373,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_BusBlock16IN_4_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_BusBlock16IN_4_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_BusBlock16IN_4_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_BusBlock16IN_4_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_BusBlock16IN_4_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + BusBlock16IN_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_sim_netlist.v new file mode 100644 index 0000000..d8d0850 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_sim_netlist.v @@ -0,0 +1,142 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:54 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_BusBlock16IN_4_0 -prefix +// AckChecker_BusBlock16IN_4_0_ AckChecker_BusBlock16IN_0_0_sim_netlist.v +// Design : AckChecker_BusBlock16IN_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "AckChecker_BusBlock16IN_0_0,BusBlock16IN,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "BusBlock16IN,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_BusBlock16IN_4_0 + (Bus_16IN, + Out0, + Out1, + Out2, + Out3, + Out4, + Out5, + Out6, + Out7, + Out8, + Out9, + Out10, + Out11, + Out12, + Out13, + Out14, + Out15); + input [15:0]Bus_16IN; + output Out0; + output Out1; + output Out2; + output Out3; + output Out4; + output Out5; + output Out6; + output Out7; + output Out8; + output Out9; + output Out10; + output Out11; + output Out12; + output Out13; + output Out14; + output Out15; + + wire [15:0]Bus_16IN; + + assign Out0 = Bus_16IN[0]; + assign Out1 = Bus_16IN[1]; + assign Out10 = Bus_16IN[10]; + assign Out11 = Bus_16IN[11]; + assign Out12 = Bus_16IN[12]; + assign Out13 = Bus_16IN[13]; + assign Out14 = Bus_16IN[14]; + assign Out15 = Bus_16IN[15]; + assign Out2 = Bus_16IN[2]; + assign Out3 = Bus_16IN[3]; + assign Out4 = Bus_16IN[4]; + assign Out5 = Bus_16IN[5]; + assign Out6 = Bus_16IN[6]; + assign Out7 = Bus_16IN[7]; + assign Out8 = Bus_16IN[8]; + assign Out9 = Bus_16IN[9]; +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_sim_netlist.vhdl new file mode 100644 index 0000000..5f1cb38 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_sim_netlist.vhdl @@ -0,0 +1,69 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:54 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_BusBlock16IN_4_0 -prefix +-- AckChecker_BusBlock16IN_4_0_ AckChecker_BusBlock16IN_0_0_sim_netlist.vhdl +-- Design : AckChecker_BusBlock16IN_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_BusBlock16IN_4_0 is + port ( + Bus_16IN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + Out0 : out STD_LOGIC; + Out1 : out STD_LOGIC; + Out2 : out STD_LOGIC; + Out3 : out STD_LOGIC; + Out4 : out STD_LOGIC; + Out5 : out STD_LOGIC; + Out6 : out STD_LOGIC; + Out7 : out STD_LOGIC; + Out8 : out STD_LOGIC; + Out9 : out STD_LOGIC; + Out10 : out STD_LOGIC; + Out11 : out STD_LOGIC; + Out12 : out STD_LOGIC; + Out13 : out STD_LOGIC; + Out14 : out STD_LOGIC; + Out15 : out STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_BusBlock16IN_4_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_BusBlock16IN_4_0 : entity is "AckChecker_BusBlock16IN_0_0,BusBlock16IN,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_BusBlock16IN_4_0 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_BusBlock16IN_4_0 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_BusBlock16IN_4_0 : entity is "BusBlock16IN,Vivado 2019.1"; +end AckChecker_BusBlock16IN_4_0; + +architecture STRUCTURE of AckChecker_BusBlock16IN_4_0 is + signal \^bus_16in\ : STD_LOGIC_VECTOR ( 15 downto 0 ); +begin + Out0 <= \^bus_16in\(0); + Out1 <= \^bus_16in\(1); + Out10 <= \^bus_16in\(10); + Out11 <= \^bus_16in\(11); + Out12 <= \^bus_16in\(12); + Out13 <= \^bus_16in\(13); + Out14 <= \^bus_16in\(14); + Out15 <= \^bus_16in\(15); + Out2 <= \^bus_16in\(2); + Out3 <= \^bus_16in\(3); + Out4 <= \^bus_16in\(4); + Out5 <= \^bus_16in\(5); + Out6 <= \^bus_16in\(6); + Out7 <= \^bus_16in\(7); + Out8 <= \^bus_16in\(8); + Out9 <= \^bus_16in\(9); + \^bus_16in\(15 downto 0) <= Bus_16IN(15 downto 0); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_stub.v new file mode 100644 index 0000000..50da4c4 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_stub.v @@ -0,0 +1,37 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:54 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_BusBlock16IN_4_0 -prefix +// AckChecker_BusBlock16IN_4_0_ AckChecker_BusBlock16IN_0_0_stub.v +// Design : AckChecker_BusBlock16IN_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "BusBlock16IN,Vivado 2019.1" *) +module AckChecker_BusBlock16IN_4_0(Bus_16IN, Out0, Out1, Out2, Out3, Out4, Out5, Out6, Out7, + Out8, Out9, Out10, Out11, Out12, Out13, Out14, Out15) +/* synthesis syn_black_box black_box_pad_pin="Bus_16IN[15:0],Out0,Out1,Out2,Out3,Out4,Out5,Out6,Out7,Out8,Out9,Out10,Out11,Out12,Out13,Out14,Out15" */; + input [15:0]Bus_16IN; + output Out0; + output Out1; + output Out2; + output Out3; + output Out4; + output Out5; + output Out6; + output Out7; + output Out8; + output Out9; + output Out10; + output Out11; + output Out12; + output Out13; + output Out14; + output Out15; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_stub.vhdl new file mode 100644 index 0000000..059761f --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_stub.vhdl @@ -0,0 +1,46 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:54 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_BusBlock16IN_4_0 -prefix +-- AckChecker_BusBlock16IN_4_0_ AckChecker_BusBlock16IN_0_0_stub.vhdl +-- Design : AckChecker_BusBlock16IN_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_BusBlock16IN_4_0 is + Port ( + Bus_16IN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + Out0 : out STD_LOGIC; + Out1 : out STD_LOGIC; + Out2 : out STD_LOGIC; + Out3 : out STD_LOGIC; + Out4 : out STD_LOGIC; + Out5 : out STD_LOGIC; + Out6 : out STD_LOGIC; + Out7 : out STD_LOGIC; + Out8 : out STD_LOGIC; + Out9 : out STD_LOGIC; + Out10 : out STD_LOGIC; + Out11 : out STD_LOGIC; + Out12 : out STD_LOGIC; + Out13 : out STD_LOGIC; + Out14 : out STD_LOGIC; + Out15 : out STD_LOGIC + ); + +end AckChecker_BusBlock16IN_4_0; + +architecture stub of AckChecker_BusBlock16IN_4_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "Bus_16IN[15:0],Out0,Out1,Out2,Out3,Out4,Out5,Out6,Out7,Out8,Out9,Out10,Out11,Out12,Out13,Out14,Out15"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "BusBlock16IN,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_1/AckChecker_BusBlock16IN_4_1.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_1/AckChecker_BusBlock16IN_4_1.dcp new file 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a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_1/AckChecker_BusBlock16IN_4_1.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_1/AckChecker_BusBlock16IN_4_1.xml index 292802e..3c1b360 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_1/AckChecker_BusBlock16IN_4_1.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_1/AckChecker_BusBlock16IN_4_1.xml @@ -95,6 +95,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:37:36 UTC 2023 + + + outputProductCRC + 9:be9db422 + + + @@ -355,6 +373,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_BusBlock16IN_4_1.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_BusBlock16IN_4_1_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_BusBlock16IN_4_1_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_BusBlock16IN_4_1_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_BusBlock16IN_4_1_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + BusBlock16IN_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_1/AckChecker_BusBlock16IN_4_1_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_1/AckChecker_BusBlock16IN_4_1_sim_netlist.v new file mode 100644 index 0000000..aeda48d --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_1/AckChecker_BusBlock16IN_4_1_sim_netlist.v @@ -0,0 +1,142 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:54 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_BusBlock16IN_4_1 -prefix +// AckChecker_BusBlock16IN_4_1_ AckChecker_BusBlock16IN_0_0_sim_netlist.v +// Design : AckChecker_BusBlock16IN_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "AckChecker_BusBlock16IN_0_0,BusBlock16IN,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "BusBlock16IN,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_BusBlock16IN_4_1 + (Bus_16IN, + Out0, + Out1, + Out2, + Out3, + Out4, + Out5, + Out6, + Out7, + Out8, + Out9, + Out10, + Out11, + Out12, + Out13, + Out14, + Out15); + input [15:0]Bus_16IN; + output Out0; + output Out1; + output Out2; + output Out3; + output Out4; + output Out5; + output Out6; + output Out7; + output Out8; + output Out9; + output Out10; + output Out11; + output Out12; + output Out13; + output Out14; + output Out15; + + wire [15:0]Bus_16IN; + + assign Out0 = Bus_16IN[0]; + assign Out1 = Bus_16IN[1]; + assign Out10 = Bus_16IN[10]; + assign Out11 = Bus_16IN[11]; + assign Out12 = Bus_16IN[12]; + assign Out13 = Bus_16IN[13]; + assign Out14 = Bus_16IN[14]; + assign Out15 = Bus_16IN[15]; + assign Out2 = Bus_16IN[2]; + assign Out3 = Bus_16IN[3]; + assign Out4 = Bus_16IN[4]; + assign Out5 = Bus_16IN[5]; + assign Out6 = Bus_16IN[6]; + assign Out7 = Bus_16IN[7]; + assign Out8 = Bus_16IN[8]; + assign Out9 = Bus_16IN[9]; +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_1/AckChecker_BusBlock16IN_4_1_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_1/AckChecker_BusBlock16IN_4_1_sim_netlist.vhdl new file mode 100644 index 0000000..542326e --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_1/AckChecker_BusBlock16IN_4_1_sim_netlist.vhdl @@ -0,0 +1,69 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:54 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_BusBlock16IN_4_1 -prefix +-- AckChecker_BusBlock16IN_4_1_ AckChecker_BusBlock16IN_0_0_sim_netlist.vhdl +-- Design : AckChecker_BusBlock16IN_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_BusBlock16IN_4_1 is + port ( + Bus_16IN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + Out0 : out STD_LOGIC; + Out1 : out STD_LOGIC; + Out2 : out STD_LOGIC; + Out3 : out STD_LOGIC; + Out4 : out STD_LOGIC; + Out5 : out STD_LOGIC; + Out6 : out STD_LOGIC; + Out7 : out STD_LOGIC; + Out8 : out STD_LOGIC; + Out9 : out STD_LOGIC; + Out10 : out STD_LOGIC; + Out11 : out STD_LOGIC; + Out12 : out STD_LOGIC; + Out13 : out STD_LOGIC; + Out14 : out STD_LOGIC; + Out15 : out STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_BusBlock16IN_4_1 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_BusBlock16IN_4_1 : entity is "AckChecker_BusBlock16IN_0_0,BusBlock16IN,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_BusBlock16IN_4_1 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_BusBlock16IN_4_1 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_BusBlock16IN_4_1 : entity is "BusBlock16IN,Vivado 2019.1"; +end AckChecker_BusBlock16IN_4_1; + +architecture STRUCTURE of AckChecker_BusBlock16IN_4_1 is + signal \^bus_16in\ : STD_LOGIC_VECTOR ( 15 downto 0 ); +begin + Out0 <= \^bus_16in\(0); + Out1 <= \^bus_16in\(1); + Out10 <= \^bus_16in\(10); + Out11 <= \^bus_16in\(11); + Out12 <= \^bus_16in\(12); + Out13 <= \^bus_16in\(13); + Out14 <= \^bus_16in\(14); + Out15 <= \^bus_16in\(15); + Out2 <= \^bus_16in\(2); + Out3 <= \^bus_16in\(3); + Out4 <= \^bus_16in\(4); + Out5 <= \^bus_16in\(5); + Out6 <= \^bus_16in\(6); + Out7 <= \^bus_16in\(7); + Out8 <= \^bus_16in\(8); + Out9 <= \^bus_16in\(9); + \^bus_16in\(15 downto 0) <= Bus_16IN(15 downto 0); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_1/AckChecker_BusBlock16IN_4_1_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_1/AckChecker_BusBlock16IN_4_1_stub.v new file mode 100644 index 0000000..0bd1ee2 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_1/AckChecker_BusBlock16IN_4_1_stub.v @@ -0,0 +1,37 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:54 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_BusBlock16IN_4_1 -prefix +// AckChecker_BusBlock16IN_4_1_ AckChecker_BusBlock16IN_0_0_stub.v +// Design : AckChecker_BusBlock16IN_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "BusBlock16IN,Vivado 2019.1" *) +module AckChecker_BusBlock16IN_4_1(Bus_16IN, Out0, Out1, Out2, Out3, Out4, Out5, Out6, Out7, + Out8, Out9, Out10, Out11, Out12, Out13, Out14, Out15) +/* synthesis syn_black_box black_box_pad_pin="Bus_16IN[15:0],Out0,Out1,Out2,Out3,Out4,Out5,Out6,Out7,Out8,Out9,Out10,Out11,Out12,Out13,Out14,Out15" */; + input [15:0]Bus_16IN; + output Out0; + output Out1; + output Out2; + output Out3; + output Out4; + output Out5; + output Out6; + output Out7; + output Out8; + output Out9; + output Out10; + output Out11; + output Out12; + output Out13; + output Out14; + output Out15; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_1/AckChecker_BusBlock16IN_4_1_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_1/AckChecker_BusBlock16IN_4_1_stub.vhdl new file mode 100644 index 0000000..4fcf221 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_1/AckChecker_BusBlock16IN_4_1_stub.vhdl @@ -0,0 +1,46 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:54 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_BusBlock16IN_4_1 -prefix +-- AckChecker_BusBlock16IN_4_1_ AckChecker_BusBlock16IN_0_0_stub.vhdl +-- Design : AckChecker_BusBlock16IN_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_BusBlock16IN_4_1 is + Port ( + Bus_16IN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + Out0 : out STD_LOGIC; + Out1 : out STD_LOGIC; + Out2 : out STD_LOGIC; + Out3 : out STD_LOGIC; + Out4 : out STD_LOGIC; + Out5 : out STD_LOGIC; + Out6 : out STD_LOGIC; + Out7 : out STD_LOGIC; + Out8 : out STD_LOGIC; + Out9 : out STD_LOGIC; + Out10 : out STD_LOGIC; + Out11 : out STD_LOGIC; + Out12 : out STD_LOGIC; + Out13 : out STD_LOGIC; + Out14 : out STD_LOGIC; + Out15 : out STD_LOGIC + ); + +end AckChecker_BusBlock16IN_4_1; + +architecture stub of AckChecker_BusBlock16IN_4_1 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "Bus_16IN[15:0],Out0,Out1,Out2,Out3,Out4,Out5,Out6,Out7,Out8,Out9,Out10,Out11,Out12,Out13,Out14,Out15"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "BusBlock16IN,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_6_0/AckChecker_BusBlock16IN_6_0.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_6_0/AckChecker_BusBlock16IN_6_0.dcp new file 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b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_6_0/AckChecker_BusBlock16IN_6_0.xci index 3d41c7b..261b3a0 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_6_0/AckChecker_BusBlock16IN_6_0.xci +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_6_0/AckChecker_BusBlock16IN_6_0.xci @@ -19,7 +19,6 @@ MIXED -3 - TRUE TRUE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_6_0/AckChecker_BusBlock16IN_6_0.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_6_0/AckChecker_BusBlock16IN_6_0.xml index 04cd742..2c0b819 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_6_0/AckChecker_BusBlock16IN_6_0.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_6_0/AckChecker_BusBlock16IN_6_0.xml @@ -95,6 +95,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:37:41 UTC 2023 + + + outputProductCRC + 9:c30e5d24 + + + @@ -355,6 +373,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_BusBlock16IN_6_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_BusBlock16IN_6_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_BusBlock16IN_6_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_BusBlock16IN_6_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_BusBlock16IN_6_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + BusBlock16IN_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_6_0/AckChecker_BusBlock16IN_6_0_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_6_0/AckChecker_BusBlock16IN_6_0_sim_netlist.v new file mode 100644 index 0000000..db59c0d --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_6_0/AckChecker_BusBlock16IN_6_0_sim_netlist.v @@ -0,0 +1,142 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:54 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_BusBlock16IN_6_0 -prefix +// AckChecker_BusBlock16IN_6_0_ AckChecker_BusBlock16IN_0_0_sim_netlist.v +// Design : AckChecker_BusBlock16IN_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "AckChecker_BusBlock16IN_0_0,BusBlock16IN,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "BusBlock16IN,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_BusBlock16IN_6_0 + (Bus_16IN, + Out0, + Out1, + Out2, + Out3, + Out4, + Out5, + Out6, + Out7, + Out8, + Out9, + Out10, + Out11, + Out12, + Out13, + Out14, + Out15); + input [15:0]Bus_16IN; + output Out0; + output Out1; + output Out2; + output Out3; + output Out4; + output Out5; + output Out6; + output Out7; + output Out8; + output Out9; + output Out10; + output Out11; + output Out12; + output Out13; + output Out14; + output Out15; + + wire [15:0]Bus_16IN; + + assign Out0 = Bus_16IN[0]; + assign Out1 = Bus_16IN[1]; + assign Out10 = Bus_16IN[10]; + assign Out11 = Bus_16IN[11]; + assign Out12 = Bus_16IN[12]; + assign Out13 = Bus_16IN[13]; + assign Out14 = Bus_16IN[14]; + assign Out15 = Bus_16IN[15]; + assign Out2 = Bus_16IN[2]; + assign Out3 = Bus_16IN[3]; + assign Out4 = Bus_16IN[4]; + assign Out5 = Bus_16IN[5]; + assign Out6 = Bus_16IN[6]; + assign Out7 = Bus_16IN[7]; + assign Out8 = Bus_16IN[8]; + assign Out9 = Bus_16IN[9]; +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_6_0/AckChecker_BusBlock16IN_6_0_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_6_0/AckChecker_BusBlock16IN_6_0_sim_netlist.vhdl new file mode 100644 index 0000000..36e88aa --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_6_0/AckChecker_BusBlock16IN_6_0_sim_netlist.vhdl @@ -0,0 +1,69 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:54 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_BusBlock16IN_6_0 -prefix +-- AckChecker_BusBlock16IN_6_0_ AckChecker_BusBlock16IN_0_0_sim_netlist.vhdl +-- Design : AckChecker_BusBlock16IN_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_BusBlock16IN_6_0 is + port ( + Bus_16IN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + Out0 : out STD_LOGIC; + Out1 : out STD_LOGIC; + Out2 : out STD_LOGIC; + Out3 : out STD_LOGIC; + Out4 : out STD_LOGIC; + Out5 : out STD_LOGIC; + Out6 : out STD_LOGIC; + Out7 : out STD_LOGIC; + Out8 : out STD_LOGIC; + Out9 : out STD_LOGIC; + Out10 : out STD_LOGIC; + Out11 : out STD_LOGIC; + Out12 : out STD_LOGIC; + Out13 : out STD_LOGIC; + Out14 : out STD_LOGIC; + Out15 : out STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_BusBlock16IN_6_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_BusBlock16IN_6_0 : entity is "AckChecker_BusBlock16IN_0_0,BusBlock16IN,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_BusBlock16IN_6_0 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_BusBlock16IN_6_0 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_BusBlock16IN_6_0 : entity is "BusBlock16IN,Vivado 2019.1"; +end AckChecker_BusBlock16IN_6_0; + +architecture STRUCTURE of AckChecker_BusBlock16IN_6_0 is + signal \^bus_16in\ : STD_LOGIC_VECTOR ( 15 downto 0 ); +begin + Out0 <= \^bus_16in\(0); + Out1 <= \^bus_16in\(1); + Out10 <= \^bus_16in\(10); + Out11 <= \^bus_16in\(11); + Out12 <= \^bus_16in\(12); + Out13 <= \^bus_16in\(13); + Out14 <= \^bus_16in\(14); + Out15 <= \^bus_16in\(15); + Out2 <= \^bus_16in\(2); + Out3 <= \^bus_16in\(3); + Out4 <= \^bus_16in\(4); + Out5 <= \^bus_16in\(5); + Out6 <= \^bus_16in\(6); + Out7 <= \^bus_16in\(7); + Out8 <= \^bus_16in\(8); + Out9 <= \^bus_16in\(9); + \^bus_16in\(15 downto 0) <= Bus_16IN(15 downto 0); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_6_0/AckChecker_BusBlock16IN_6_0_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_6_0/AckChecker_BusBlock16IN_6_0_stub.v new file mode 100644 index 0000000..8dca78f --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_6_0/AckChecker_BusBlock16IN_6_0_stub.v @@ -0,0 +1,37 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:54 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_BusBlock16IN_6_0 -prefix +// AckChecker_BusBlock16IN_6_0_ AckChecker_BusBlock16IN_0_0_stub.v +// Design : AckChecker_BusBlock16IN_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "BusBlock16IN,Vivado 2019.1" *) +module AckChecker_BusBlock16IN_6_0(Bus_16IN, Out0, Out1, Out2, Out3, Out4, Out5, Out6, Out7, + Out8, Out9, Out10, Out11, Out12, Out13, Out14, Out15) +/* synthesis syn_black_box black_box_pad_pin="Bus_16IN[15:0],Out0,Out1,Out2,Out3,Out4,Out5,Out6,Out7,Out8,Out9,Out10,Out11,Out12,Out13,Out14,Out15" */; + input [15:0]Bus_16IN; + output Out0; + output Out1; + output Out2; + output Out3; + output Out4; + output Out5; + output Out6; + output Out7; + output Out8; + output Out9; + output Out10; + output Out11; + output Out12; + output Out13; + output Out14; + output Out15; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_6_0/AckChecker_BusBlock16IN_6_0_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_6_0/AckChecker_BusBlock16IN_6_0_stub.vhdl new file mode 100644 index 0000000..1805f51 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_6_0/AckChecker_BusBlock16IN_6_0_stub.vhdl @@ -0,0 +1,46 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:54 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_BusBlock16IN_6_0 -prefix +-- AckChecker_BusBlock16IN_6_0_ AckChecker_BusBlock16IN_0_0_stub.vhdl +-- Design : AckChecker_BusBlock16IN_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_BusBlock16IN_6_0 is + Port ( + Bus_16IN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + Out0 : out STD_LOGIC; + Out1 : out STD_LOGIC; + Out2 : out STD_LOGIC; + Out3 : out STD_LOGIC; + Out4 : out STD_LOGIC; + Out5 : out STD_LOGIC; + Out6 : out STD_LOGIC; + Out7 : out STD_LOGIC; + Out8 : out STD_LOGIC; + Out9 : out STD_LOGIC; + Out10 : out STD_LOGIC; + Out11 : out STD_LOGIC; + Out12 : out STD_LOGIC; + Out13 : out STD_LOGIC; + Out14 : out STD_LOGIC; + Out15 : out STD_LOGIC + ); + +end AckChecker_BusBlock16IN_6_0; + +architecture stub of AckChecker_BusBlock16IN_6_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "Bus_16IN[15:0],Out0,Out1,Out2,Out3,Out4,Out5,Out6,Out7,Out8,Out9,Out10,Out11,Out12,Out13,Out14,Out15"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "BusBlock16IN,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0.dcp new 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a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0.xml index 94f880d..d9f407b 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0.xml @@ -95,6 +95,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:35:54 UTC 2023 + + + outputProductCRC + 9:cfa95452 + + + @@ -372,6 +390,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_BusBlock16OUT_0_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_BusBlock16OUT_0_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_BusBlock16OUT_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_BusBlock16OUT_0_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_BusBlock16OUT_0_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + BusBlock16OUT_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_sim_netlist.v new file mode 100644 index 0000000..2b870df --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_sim_netlist.v @@ -0,0 +1,320 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:54 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim +// D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_sim_netlist.v +// Design : AckChecker_BusBlock16OUT_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "AckChecker_BusBlock16OUT_0_0,BusBlock16OUT,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "BusBlock16OUT,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_BusBlock16OUT_0_0 + (Bus_16OUT, + In0, + In1, + In2, + In3, + In4, + In5, + In6, + In7, + In8, + In9, + In10, + In11, + In12, + In13, + In14, + In15, + Mask); + output [15:0]Bus_16OUT; + input In0; + input In1; + input In2; + input In3; + input In4; + input In5; + input In6; + input In7; + input In8; + input In9; + input In10; + input In11; + input In12; + input In13; + input In14; + input In15; + input [15:0]Mask; + + wire [15:0]Bus_16OUT; + wire In0; + wire In1; + wire In10; + wire In11; + wire In12; + wire In13; + wire In14; + wire In15; + wire In2; + wire In3; + wire In4; + wire In5; + wire In6; + wire In7; + wire In8; + wire In9; + wire [15:0]Mask; + + AckChecker_BusBlock16OUT_0_0_BusBlock16OUT U0 + (.Bus_16OUT(Bus_16OUT), + .In0(In0), + .In1(In1), + .In10(In10), + .In11(In11), + .In12(In12), + .In13(In13), + .In14(In14), + .In15(In15), + .In2(In2), + .In3(In3), + .In4(In4), + .In5(In5), + .In6(In6), + .In7(In7), + .In8(In8), + .In9(In9), + .Mask(Mask)); +endmodule + +(* ORIG_REF_NAME = "BusBlock16OUT" *) +module AckChecker_BusBlock16OUT_0_0_BusBlock16OUT + (Bus_16OUT, + In0, + Mask, + In1, + In2, + In3, + In4, + In5, + In6, + In7, + In8, + In9, + In10, + In11, + In12, + In13, + In14, + In15); + output [15:0]Bus_16OUT; + input In0; + input [15:0]Mask; + input In1; + input In2; + input In3; + input In4; + input In5; + input In6; + input In7; + input In8; + input In9; + input In10; + input In11; + input In12; + input In13; + input In14; + input In15; + + wire [15:0]Bus_16OUT; + wire In0; + wire In1; + wire In10; + wire In11; + wire In12; + wire In13; + wire In14; + wire In15; + wire In2; + wire In3; + wire In4; + wire In5; + wire In6; + wire In7; + wire In8; + wire In9; + wire [15:0]Mask; + + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[0]_INST_0 + (.I0(In0), + .I1(Mask[0]), + .O(Bus_16OUT[0])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[10]_INST_0 + (.I0(In10), + .I1(Mask[10]), + .O(Bus_16OUT[10])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[11]_INST_0 + (.I0(In11), + .I1(Mask[11]), + .O(Bus_16OUT[11])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[12]_INST_0 + (.I0(In12), + .I1(Mask[12]), + .O(Bus_16OUT[12])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[13]_INST_0 + (.I0(In13), + .I1(Mask[13]), + .O(Bus_16OUT[13])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[14]_INST_0 + (.I0(In14), + .I1(Mask[14]), + .O(Bus_16OUT[14])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[15]_INST_0 + (.I0(In15), + .I1(Mask[15]), + .O(Bus_16OUT[15])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[1]_INST_0 + (.I0(In1), + .I1(Mask[1]), + .O(Bus_16OUT[1])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[2]_INST_0 + (.I0(In2), + .I1(Mask[2]), + .O(Bus_16OUT[2])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[3]_INST_0 + (.I0(In3), + .I1(Mask[3]), + .O(Bus_16OUT[3])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[4]_INST_0 + (.I0(In4), + .I1(Mask[4]), + .O(Bus_16OUT[4])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[5]_INST_0 + (.I0(In5), + .I1(Mask[5]), + .O(Bus_16OUT[5])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[6]_INST_0 + (.I0(In6), + .I1(Mask[6]), + .O(Bus_16OUT[6])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[7]_INST_0 + (.I0(In7), + .I1(Mask[7]), + .O(Bus_16OUT[7])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[8]_INST_0 + (.I0(In8), + .I1(Mask[8]), + .O(Bus_16OUT[8])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[9]_INST_0 + (.I0(In9), + .I1(Mask[9]), + .O(Bus_16OUT[9])); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_sim_netlist.vhdl new file mode 100644 index 0000000..241c109 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_sim_netlist.vhdl @@ -0,0 +1,249 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:54 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim +-- D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_sim_netlist.vhdl +-- Design : AckChecker_BusBlock16OUT_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_BusBlock16OUT_0_0_BusBlock16OUT is + port ( + Bus_16OUT : out STD_LOGIC_VECTOR ( 15 downto 0 ); + In0 : in STD_LOGIC; + Mask : in STD_LOGIC_VECTOR ( 15 downto 0 ); + In1 : in STD_LOGIC; + In2 : in STD_LOGIC; + In3 : in STD_LOGIC; + In4 : in STD_LOGIC; + In5 : in STD_LOGIC; + In6 : in STD_LOGIC; + In7 : in STD_LOGIC; + In8 : in STD_LOGIC; + In9 : in STD_LOGIC; + In10 : in STD_LOGIC; + In11 : in STD_LOGIC; + In12 : in STD_LOGIC; + In13 : in STD_LOGIC; + In14 : in STD_LOGIC; + In15 : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of AckChecker_BusBlock16OUT_0_0_BusBlock16OUT : entity is "BusBlock16OUT"; +end AckChecker_BusBlock16OUT_0_0_BusBlock16OUT; + +architecture STRUCTURE of AckChecker_BusBlock16OUT_0_0_BusBlock16OUT is +begin +\Bus_16OUT[0]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In0, + I1 => Mask(0), + O => Bus_16OUT(0) + ); +\Bus_16OUT[10]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In10, + I1 => Mask(10), + O => Bus_16OUT(10) + ); +\Bus_16OUT[11]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In11, + I1 => Mask(11), + O => Bus_16OUT(11) + ); +\Bus_16OUT[12]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In12, + I1 => Mask(12), + O => Bus_16OUT(12) + ); +\Bus_16OUT[13]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In13, + I1 => Mask(13), + O => Bus_16OUT(13) + ); +\Bus_16OUT[14]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In14, + I1 => Mask(14), + O => Bus_16OUT(14) + ); +\Bus_16OUT[15]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In15, + I1 => Mask(15), + O => Bus_16OUT(15) + ); +\Bus_16OUT[1]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In1, + I1 => Mask(1), + O => Bus_16OUT(1) + ); +\Bus_16OUT[2]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In2, + I1 => Mask(2), + O => Bus_16OUT(2) + ); +\Bus_16OUT[3]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In3, + I1 => Mask(3), + O => Bus_16OUT(3) + ); +\Bus_16OUT[4]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In4, + I1 => Mask(4), + O => Bus_16OUT(4) + ); +\Bus_16OUT[5]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In5, + I1 => Mask(5), + O => Bus_16OUT(5) + ); +\Bus_16OUT[6]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In6, + I1 => Mask(6), + O => Bus_16OUT(6) + ); +\Bus_16OUT[7]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In7, + I1 => Mask(7), + O => Bus_16OUT(7) + ); +\Bus_16OUT[8]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In8, + I1 => Mask(8), + O => Bus_16OUT(8) + ); +\Bus_16OUT[9]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In9, + I1 => Mask(9), + O => Bus_16OUT(9) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_BusBlock16OUT_0_0 is + port ( + Bus_16OUT : out STD_LOGIC_VECTOR ( 15 downto 0 ); + In0 : in STD_LOGIC; + In1 : in STD_LOGIC; + In2 : in STD_LOGIC; + In3 : in STD_LOGIC; + In4 : in STD_LOGIC; + In5 : in STD_LOGIC; + In6 : in STD_LOGIC; + In7 : in STD_LOGIC; + In8 : in STD_LOGIC; + In9 : in STD_LOGIC; + In10 : in STD_LOGIC; + In11 : in STD_LOGIC; + In12 : in STD_LOGIC; + In13 : in STD_LOGIC; + In14 : in STD_LOGIC; + In15 : in STD_LOGIC; + Mask : in STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_BusBlock16OUT_0_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_BusBlock16OUT_0_0 : entity is "AckChecker_BusBlock16OUT_0_0,BusBlock16OUT,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_BusBlock16OUT_0_0 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_BusBlock16OUT_0_0 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_BusBlock16OUT_0_0 : entity is "BusBlock16OUT,Vivado 2019.1"; +end AckChecker_BusBlock16OUT_0_0; + +architecture STRUCTURE of AckChecker_BusBlock16OUT_0_0 is +begin +U0: entity work.AckChecker_BusBlock16OUT_0_0_BusBlock16OUT + port map ( + Bus_16OUT(15 downto 0) => Bus_16OUT(15 downto 0), + In0 => In0, + In1 => In1, + In10 => In10, + In11 => In11, + In12 => In12, + In13 => In13, + In14 => In14, + In15 => In15, + In2 => In2, + In3 => In3, + In4 => In4, + In5 => In5, + In6 => In6, + In7 => In7, + In8 => In8, + In9 => In9, + Mask(15 downto 0) => Mask(15 downto 0) + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_stub.v new file mode 100644 index 0000000..880562e --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_stub.v @@ -0,0 +1,38 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:54 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub +// D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_stub.v +// Design : AckChecker_BusBlock16OUT_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "BusBlock16OUT,Vivado 2019.1" *) +module AckChecker_BusBlock16OUT_0_0(Bus_16OUT, In0, In1, In2, In3, In4, In5, In6, In7, In8, In9, + In10, In11, In12, In13, In14, In15, Mask) +/* synthesis syn_black_box black_box_pad_pin="Bus_16OUT[15:0],In0,In1,In2,In3,In4,In5,In6,In7,In8,In9,In10,In11,In12,In13,In14,In15,Mask[15:0]" */; + output [15:0]Bus_16OUT; + input In0; + input In1; + input In2; + input In3; + input In4; + input In5; + input In6; + input In7; + input In8; + input In9; + input In10; + input In11; + input In12; + input In13; + input In14; + input In15; + input [15:0]Mask; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_stub.vhdl new file mode 100644 index 0000000..ad604b5 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_stub.vhdl @@ -0,0 +1,47 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:54 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub +-- D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_0/AckChecker_BusBlock16OUT_0_0_stub.vhdl +-- Design : AckChecker_BusBlock16OUT_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_BusBlock16OUT_0_0 is + Port ( + Bus_16OUT : out STD_LOGIC_VECTOR ( 15 downto 0 ); + In0 : in STD_LOGIC; + In1 : in STD_LOGIC; + In2 : in STD_LOGIC; + In3 : in STD_LOGIC; + In4 : in STD_LOGIC; + In5 : in STD_LOGIC; + In6 : in STD_LOGIC; + In7 : in STD_LOGIC; + In8 : in STD_LOGIC; + In9 : in STD_LOGIC; + In10 : in STD_LOGIC; + In11 : in STD_LOGIC; + In12 : in STD_LOGIC; + In13 : in STD_LOGIC; + In14 : in STD_LOGIC; + In15 : in STD_LOGIC; + Mask : in STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + +end AckChecker_BusBlock16OUT_0_0; + +architecture stub of AckChecker_BusBlock16OUT_0_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "Bus_16OUT[15:0],In0,In1,In2,In3,In4,In5,In6,In7,In8,In9,In10,In11,In12,In13,In14,In15,Mask[15:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "BusBlock16OUT,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1.dcp 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a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1.xci b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1.xci index 1f48854..07b9504 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1.xci +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1.xci @@ -19,7 +19,6 @@ MIXED -3 - TRUE TRUE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1.xml b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1.xml index 82384b0..3165f7b 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1.xml @@ -95,6 +95,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:36:46 UTC 2023 + + + outputProductCRC + 9:3046c02a + + + @@ -372,6 +390,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_BusBlock16OUT_0_1.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_BusBlock16OUT_0_1_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_BusBlock16OUT_0_1_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_BusBlock16OUT_0_1_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_BusBlock16OUT_0_1_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + BusBlock16OUT_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_sim_netlist.v new file mode 100644 index 0000000..e8428ca --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_sim_netlist.v @@ -0,0 +1,319 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:54 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_BusBlock16OUT_0_1 -prefix +// AckChecker_BusBlock16OUT_0_1_ AckChecker_BusBlock16OUT_0_0_sim_netlist.v +// Design : AckChecker_BusBlock16OUT_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "AckChecker_BusBlock16OUT_0_0,BusBlock16OUT,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "BusBlock16OUT,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_BusBlock16OUT_0_1 + (Bus_16OUT, + In0, + In1, + In2, + In3, + In4, + In5, + In6, + In7, + In8, + In9, + In10, + In11, + In12, + In13, + In14, + In15, + Mask); + output [15:0]Bus_16OUT; + input In0; + input In1; + input In2; + input In3; + input In4; + input In5; + input In6; + input In7; + input In8; + input In9; + input In10; + input In11; + input In12; + input In13; + input In14; + input In15; + input [15:0]Mask; + + wire [15:0]Bus_16OUT; + wire In0; + wire In1; + wire In10; + wire In11; + wire In12; + wire In13; + wire In14; + wire In15; + wire In2; + wire In3; + wire In4; + wire In5; + wire In6; + wire In7; + wire In8; + wire In9; + wire [15:0]Mask; + + AckChecker_BusBlock16OUT_0_1_BusBlock16OUT U0 + (.Bus_16OUT(Bus_16OUT), + .In0(In0), + .In1(In1), + .In10(In10), + .In11(In11), + .In12(In12), + .In13(In13), + .In14(In14), + .In15(In15), + .In2(In2), + .In3(In3), + .In4(In4), + .In5(In5), + .In6(In6), + .In7(In7), + .In8(In8), + .In9(In9), + .Mask(Mask)); +endmodule + +module AckChecker_BusBlock16OUT_0_1_BusBlock16OUT + (Bus_16OUT, + In0, + Mask, + In1, + In2, + In3, + In4, + In5, + In6, + In7, + In8, + In9, + In10, + In11, + In12, + In13, + In14, + In15); + output [15:0]Bus_16OUT; + input In0; + input [15:0]Mask; + input In1; + input In2; + input In3; + input In4; + input In5; + input In6; + input In7; + input In8; + input In9; + input In10; + input In11; + input In12; + input In13; + input In14; + input In15; + + wire [15:0]Bus_16OUT; + wire In0; + wire In1; + wire In10; + wire In11; + wire In12; + wire In13; + wire In14; + wire In15; + wire In2; + wire In3; + wire In4; + wire In5; + wire In6; + wire In7; + wire In8; + wire In9; + wire [15:0]Mask; + + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[0]_INST_0 + (.I0(In0), + .I1(Mask[0]), + .O(Bus_16OUT[0])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[10]_INST_0 + (.I0(In10), + .I1(Mask[10]), + .O(Bus_16OUT[10])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[11]_INST_0 + (.I0(In11), + .I1(Mask[11]), + .O(Bus_16OUT[11])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[12]_INST_0 + (.I0(In12), + .I1(Mask[12]), + .O(Bus_16OUT[12])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[13]_INST_0 + (.I0(In13), + .I1(Mask[13]), + .O(Bus_16OUT[13])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[14]_INST_0 + (.I0(In14), + .I1(Mask[14]), + .O(Bus_16OUT[14])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[15]_INST_0 + (.I0(In15), + .I1(Mask[15]), + .O(Bus_16OUT[15])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[1]_INST_0 + (.I0(In1), + .I1(Mask[1]), + .O(Bus_16OUT[1])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[2]_INST_0 + (.I0(In2), + .I1(Mask[2]), + .O(Bus_16OUT[2])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[3]_INST_0 + (.I0(In3), + .I1(Mask[3]), + .O(Bus_16OUT[3])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[4]_INST_0 + (.I0(In4), + .I1(Mask[4]), + .O(Bus_16OUT[4])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[5]_INST_0 + (.I0(In5), + .I1(Mask[5]), + .O(Bus_16OUT[5])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[6]_INST_0 + (.I0(In6), + .I1(Mask[6]), + .O(Bus_16OUT[6])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[7]_INST_0 + (.I0(In7), + .I1(Mask[7]), + .O(Bus_16OUT[7])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[8]_INST_0 + (.I0(In8), + .I1(Mask[8]), + .O(Bus_16OUT[8])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[9]_INST_0 + (.I0(In9), + .I1(Mask[9]), + .O(Bus_16OUT[9])); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_sim_netlist.vhdl new file mode 100644 index 0000000..bc573ec --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_sim_netlist.vhdl @@ -0,0 +1,247 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:54 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_BusBlock16OUT_0_1 -prefix +-- AckChecker_BusBlock16OUT_0_1_ AckChecker_BusBlock16OUT_0_0_sim_netlist.vhdl +-- Design : AckChecker_BusBlock16OUT_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_BusBlock16OUT_0_1_BusBlock16OUT is + port ( + Bus_16OUT : out STD_LOGIC_VECTOR ( 15 downto 0 ); + In0 : in STD_LOGIC; + Mask : in STD_LOGIC_VECTOR ( 15 downto 0 ); + In1 : in STD_LOGIC; + In2 : in STD_LOGIC; + In3 : in STD_LOGIC; + In4 : in STD_LOGIC; + In5 : in STD_LOGIC; + In6 : in STD_LOGIC; + In7 : in STD_LOGIC; + In8 : in STD_LOGIC; + In9 : in STD_LOGIC; + In10 : in STD_LOGIC; + In11 : in STD_LOGIC; + In12 : in STD_LOGIC; + In13 : in STD_LOGIC; + In14 : in STD_LOGIC; + In15 : in STD_LOGIC + ); +end AckChecker_BusBlock16OUT_0_1_BusBlock16OUT; + +architecture STRUCTURE of AckChecker_BusBlock16OUT_0_1_BusBlock16OUT is +begin +\Bus_16OUT[0]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In0, + I1 => Mask(0), + O => Bus_16OUT(0) + ); +\Bus_16OUT[10]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In10, + I1 => Mask(10), + O => Bus_16OUT(10) + ); +\Bus_16OUT[11]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In11, + I1 => Mask(11), + O => Bus_16OUT(11) + ); +\Bus_16OUT[12]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In12, + I1 => Mask(12), + O => Bus_16OUT(12) + ); +\Bus_16OUT[13]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In13, + I1 => Mask(13), + O => Bus_16OUT(13) + ); +\Bus_16OUT[14]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In14, + I1 => Mask(14), + O => Bus_16OUT(14) + ); +\Bus_16OUT[15]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In15, + I1 => Mask(15), + O => Bus_16OUT(15) + ); +\Bus_16OUT[1]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In1, + I1 => Mask(1), + O => Bus_16OUT(1) + ); +\Bus_16OUT[2]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In2, + I1 => Mask(2), + O => Bus_16OUT(2) + ); +\Bus_16OUT[3]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In3, + I1 => Mask(3), + O => Bus_16OUT(3) + ); +\Bus_16OUT[4]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In4, + I1 => Mask(4), + O => Bus_16OUT(4) + ); +\Bus_16OUT[5]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In5, + I1 => Mask(5), + O => Bus_16OUT(5) + ); +\Bus_16OUT[6]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In6, + I1 => Mask(6), + O => Bus_16OUT(6) + ); +\Bus_16OUT[7]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In7, + I1 => Mask(7), + O => Bus_16OUT(7) + ); +\Bus_16OUT[8]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In8, + I1 => Mask(8), + O => Bus_16OUT(8) + ); +\Bus_16OUT[9]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In9, + I1 => Mask(9), + O => Bus_16OUT(9) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_BusBlock16OUT_0_1 is + port ( + Bus_16OUT : out STD_LOGIC_VECTOR ( 15 downto 0 ); + In0 : in STD_LOGIC; + In1 : in STD_LOGIC; + In2 : in STD_LOGIC; + In3 : in STD_LOGIC; + In4 : in STD_LOGIC; + In5 : in STD_LOGIC; + In6 : in STD_LOGIC; + In7 : in STD_LOGIC; + In8 : in STD_LOGIC; + In9 : in STD_LOGIC; + In10 : in STD_LOGIC; + In11 : in STD_LOGIC; + In12 : in STD_LOGIC; + In13 : in STD_LOGIC; + In14 : in STD_LOGIC; + In15 : in STD_LOGIC; + Mask : in STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_BusBlock16OUT_0_1 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_BusBlock16OUT_0_1 : entity is "AckChecker_BusBlock16OUT_0_0,BusBlock16OUT,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_BusBlock16OUT_0_1 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_BusBlock16OUT_0_1 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_BusBlock16OUT_0_1 : entity is "BusBlock16OUT,Vivado 2019.1"; +end AckChecker_BusBlock16OUT_0_1; + +architecture STRUCTURE of AckChecker_BusBlock16OUT_0_1 is +begin +U0: entity work.AckChecker_BusBlock16OUT_0_1_BusBlock16OUT + port map ( + Bus_16OUT(15 downto 0) => Bus_16OUT(15 downto 0), + In0 => In0, + In1 => In1, + In10 => In10, + In11 => In11, + In12 => In12, + In13 => In13, + In14 => In14, + In15 => In15, + In2 => In2, + In3 => In3, + In4 => In4, + In5 => In5, + In6 => In6, + In7 => In7, + In8 => In8, + In9 => In9, + Mask(15 downto 0) => Mask(15 downto 0) + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_stub.v new file mode 100644 index 0000000..9ad7c46 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_stub.v @@ -0,0 +1,38 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:54 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_BusBlock16OUT_0_1 -prefix +// AckChecker_BusBlock16OUT_0_1_ AckChecker_BusBlock16OUT_0_0_stub.v +// Design : AckChecker_BusBlock16OUT_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "BusBlock16OUT,Vivado 2019.1" *) +module AckChecker_BusBlock16OUT_0_1(Bus_16OUT, In0, In1, In2, In3, In4, In5, In6, In7, In8, In9, + In10, In11, In12, In13, In14, In15, Mask) +/* synthesis syn_black_box black_box_pad_pin="Bus_16OUT[15:0],In0,In1,In2,In3,In4,In5,In6,In7,In8,In9,In10,In11,In12,In13,In14,In15,Mask[15:0]" */; + output [15:0]Bus_16OUT; + input In0; + input In1; + input In2; + input In3; + input In4; + input In5; + input In6; + input In7; + input In8; + input In9; + input In10; + input In11; + input In12; + input In13; + input In14; + input In15; + input [15:0]Mask; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_stub.vhdl new file mode 100644 index 0000000..81f343e --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_1/AckChecker_BusBlock16OUT_0_1_stub.vhdl @@ -0,0 +1,47 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:54 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_BusBlock16OUT_0_1 -prefix +-- AckChecker_BusBlock16OUT_0_1_ AckChecker_BusBlock16OUT_0_0_stub.vhdl +-- Design : AckChecker_BusBlock16OUT_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_BusBlock16OUT_0_1 is + Port ( + Bus_16OUT : out STD_LOGIC_VECTOR ( 15 downto 0 ); + In0 : in STD_LOGIC; + In1 : in STD_LOGIC; + In2 : in STD_LOGIC; + In3 : in STD_LOGIC; + In4 : in STD_LOGIC; + In5 : in STD_LOGIC; + In6 : in STD_LOGIC; + In7 : in STD_LOGIC; + In8 : in STD_LOGIC; + In9 : in STD_LOGIC; + In10 : in STD_LOGIC; + In11 : in STD_LOGIC; + In12 : in STD_LOGIC; + In13 : in STD_LOGIC; + In14 : in STD_LOGIC; + In15 : in STD_LOGIC; + Mask : in STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + +end AckChecker_BusBlock16OUT_0_1; + +architecture stub of AckChecker_BusBlock16OUT_0_1 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "Bus_16OUT[15:0],In0,In1,In2,In3,In4,In5,In6,In7,In8,In9,In10,In11,In12,In13,In14,In15,Mask[15:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "BusBlock16OUT,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2.dcp new file mode 100644 index 0000000000000000000000000000000000000000..7deb44d18d493910dfbe7ffa2dcb52e7ce32564e GIT binary patch literal 8868 zcma)>1yG#LviEU!m!M$@Zb5@faCawYAb5~Pg1ZHG2u^Uz)(X~adTTq zYfE!m%a0}!ZY~mbj^?(Uyee9nCLAUlY?c;QkZebnjV7Y7)t?&H9`zhEY$?w$D?p`` z<7vFQ#JKF0)|mquU0A+%B%5@Z?st%CK#+YuSHkCd%Ejyjgqp2Y7rNUl^Lze=2&(0R zoE>ap1uj48c;Hiupo#qsb_>u=@DgK!U$R7rTsYpE*iOQN7M?V__pAB2l=l5K_SUv1 z{_Vj6uXo3y<8f9a@QlTGIXmylg`kfU)h3o-H!;(rX@z!%gVln6s0L?X=wqCDy^liy zm^PzQ?ZEbw`+|>kR>Y}65x(ujxx9A~%y+iCF_3*1(%iOHq|)5{gYJuuq-gAbBs}0o4Tnv2^m+1;I|Iva-xqCT zA{Gc)R|5X(&vc}%JNPW~6Y_~+fuqy+*_Rj$gg|yUGZM4I+JL@!Z~5klR+7Kww|S#( zZcovl0|K>EUka+`jgyjJJ3A4B^NAaN!8?*89#CU_k*(uZ z_0*culGqt_s$XO=Ru%kYxEjCvvK70hP=gC>cbAw>S58Q_sto>R`A`SgopIu7r!*?` zmLpOY`=Tbhp;Z$#1FV>{;HQXnD8AR0Yom^qa}~|RcfDcI3(aJZ)+sqc#!Y_>=__Mz zp3&@>w6Y)|kD>43y^+m)M87J3w`hHSiOD+Zk0mAJpH$(er1bp0K8rsPxv67(`Qw2c z7eVzR6UNX%sl!A*gEPfZcyK*Wp5U+P?8ds(=l*fz&1-Gsbz>P0?%UHTAL&fihz;Uj zs;6`lqu|J8;o~Rb8^1^1FAqC0GKqOIvGZMt9Zh@_G!d#%4st$O?|>@OA9`tRB3OSM z3d~Vl=-dlnBPwXI^v)#HmGc;5Zf@IM`|JODKet9vz+YO6|Dwl?^mIN(q8=8r92T<; z7V|4?j4?dfBN8_frgaOZ_1eivH(osbXV>Mvyw92Z-<|Q11)o04cwf;92*{F!IcKC4 zQz4puB*LfPlVIeO{pje(-74oxtbwq3{TRm0FvU$rd+nJo?Lu-Vp3zh_Z5QENvo*b; z44WunF%UyvU_*&_1RNE&tSKi$o*58!c!5^nGi%7wK%CPFg0Fuch%q1$bhbyne2__E zR>R0WFXS0yWbS{D6U3Sa`o2eQ*ESzWVuy~|q_X<%2Zv!e==0>epR<@v80h5GUjYr* zvtSjIhK1FoedS258j zRg*r~qDpKKyMvWS8JRk6okhh z189tJ_tD{6C<{l$eRyDqgIrll*b&#{5}bd#WSzYO6{KYNy1D7aigL)nypT!CO}u zlNrHqB0I_s4T>rsah~2_#OdLI5XX447Piuq80z~v(9>Gm4PqBI(pVYl>8MfCl=$nx zoJ*=!awxbQF7KKzx1la?ne25fn2gf~4&9l+pt!kd7%1C2}LYX$*h( ztynlHUe*2BptuSbm6HmMlb>irIc0Q~$Bbqthz3bUa$&(O{hKs*-zWaQH4g?s3U&?K zK}qch&!N7(%okc;f@iK+o~@FzxV}o3XZO1^y`dN=%W;1#zyD#{OM{~*KT(dckpiQj zuqs4tBuk#BC|~2ZfCd$Up@J+_!2d0vK!qTvAPp5}WT65QR0xC$QcxjLmQfrlaC;+&7I-X>w7FOUU222gGSbv)22RI^1PfJDT^=T_4u<&Q!0c1yUpY9HSz6} z%)RJ##Ciu!GDW@4LR7&-BII}`(#PxaP7Vkf3_%mW`{ZM3^lnaZ{xifS^0iu8B)3r# z;r$f2zu~lr7WGrxhR8QPCAETJB{MomRY|F7@tCrkBoB+Qae99fb7a{MGr7o%dH1(! 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All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:54 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_BusBlock16OUT_0_2 -prefix +// AckChecker_BusBlock16OUT_0_2_ AckChecker_BusBlock16OUT_0_0_sim_netlist.v +// Design : AckChecker_BusBlock16OUT_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "AckChecker_BusBlock16OUT_0_0,BusBlock16OUT,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "BusBlock16OUT,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_BusBlock16OUT_0_2 + (Bus_16OUT, + In0, + In1, + In2, + In3, + In4, + In5, + In6, + In7, + In8, + In9, + In10, + In11, + In12, + In13, + In14, + In15, + Mask); + output [15:0]Bus_16OUT; + input In0; + input In1; + input In2; + input In3; + input In4; + input In5; + input In6; + input In7; + input In8; + input In9; + input In10; + input In11; + input In12; + input In13; + input In14; + input In15; + input [15:0]Mask; + + wire [15:0]Bus_16OUT; + wire In0; + wire In1; + wire In10; + wire In11; + wire In12; + wire In13; + wire In14; + wire In15; + wire In2; + wire In3; + wire In4; + wire In5; + wire In6; + wire In7; + wire In8; + wire In9; + wire [15:0]Mask; + + AckChecker_BusBlock16OUT_0_2_BusBlock16OUT U0 + (.Bus_16OUT(Bus_16OUT), + .In0(In0), + .In1(In1), + .In10(In10), + .In11(In11), + .In12(In12), + .In13(In13), + .In14(In14), + .In15(In15), + .In2(In2), + .In3(In3), + .In4(In4), + .In5(In5), + .In6(In6), + .In7(In7), + .In8(In8), + .In9(In9), + .Mask(Mask)); +endmodule + +module AckChecker_BusBlock16OUT_0_2_BusBlock16OUT + (Bus_16OUT, + In0, + Mask, + In1, + In2, + In3, + In4, + In5, + In6, + In7, + In8, + In9, + In10, + In11, + In12, + In13, + In14, + In15); + output [15:0]Bus_16OUT; + input In0; + input [15:0]Mask; + input In1; + input In2; + input In3; + input In4; + input In5; + input In6; + input In7; + input In8; + input In9; + input In10; + input In11; + input In12; + input In13; + input In14; + input In15; + + wire [15:0]Bus_16OUT; + wire In0; + wire In1; + wire In10; + wire In11; + wire In12; + wire In13; + wire In14; + wire In15; + wire In2; + wire In3; + wire In4; + wire In5; + wire In6; + wire In7; + wire In8; + wire In9; + wire [15:0]Mask; + + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[0]_INST_0 + (.I0(In0), + .I1(Mask[0]), + .O(Bus_16OUT[0])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[10]_INST_0 + (.I0(In10), + .I1(Mask[10]), + .O(Bus_16OUT[10])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[11]_INST_0 + (.I0(In11), + .I1(Mask[11]), + .O(Bus_16OUT[11])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[12]_INST_0 + (.I0(In12), + .I1(Mask[12]), + .O(Bus_16OUT[12])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[13]_INST_0 + (.I0(In13), + .I1(Mask[13]), + .O(Bus_16OUT[13])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[14]_INST_0 + (.I0(In14), + .I1(Mask[14]), + .O(Bus_16OUT[14])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[15]_INST_0 + (.I0(In15), + .I1(Mask[15]), + .O(Bus_16OUT[15])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[1]_INST_0 + (.I0(In1), + .I1(Mask[1]), + .O(Bus_16OUT[1])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[2]_INST_0 + (.I0(In2), + .I1(Mask[2]), + .O(Bus_16OUT[2])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[3]_INST_0 + (.I0(In3), + .I1(Mask[3]), + .O(Bus_16OUT[3])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[4]_INST_0 + (.I0(In4), + .I1(Mask[4]), + .O(Bus_16OUT[4])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[5]_INST_0 + (.I0(In5), + .I1(Mask[5]), + .O(Bus_16OUT[5])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[6]_INST_0 + (.I0(In6), + .I1(Mask[6]), + .O(Bus_16OUT[6])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[7]_INST_0 + (.I0(In7), + .I1(Mask[7]), + .O(Bus_16OUT[7])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[8]_INST_0 + (.I0(In8), + .I1(Mask[8]), + .O(Bus_16OUT[8])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[9]_INST_0 + (.I0(In9), + .I1(Mask[9]), + .O(Bus_16OUT[9])); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_sim_netlist.vhdl new file mode 100644 index 0000000..e809967 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_sim_netlist.vhdl @@ -0,0 +1,247 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:54 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_BusBlock16OUT_0_2 -prefix +-- AckChecker_BusBlock16OUT_0_2_ AckChecker_BusBlock16OUT_0_0_sim_netlist.vhdl +-- Design : AckChecker_BusBlock16OUT_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_BusBlock16OUT_0_2_BusBlock16OUT is + port ( + Bus_16OUT : out STD_LOGIC_VECTOR ( 15 downto 0 ); + In0 : in STD_LOGIC; + Mask : in STD_LOGIC_VECTOR ( 15 downto 0 ); + In1 : in STD_LOGIC; + In2 : in STD_LOGIC; + In3 : in STD_LOGIC; + In4 : in STD_LOGIC; + In5 : in STD_LOGIC; + In6 : in STD_LOGIC; + In7 : in STD_LOGIC; + In8 : in STD_LOGIC; + In9 : in STD_LOGIC; + In10 : in STD_LOGIC; + In11 : in STD_LOGIC; + In12 : in STD_LOGIC; + In13 : in STD_LOGIC; + In14 : in STD_LOGIC; + In15 : in STD_LOGIC + ); +end AckChecker_BusBlock16OUT_0_2_BusBlock16OUT; + +architecture STRUCTURE of AckChecker_BusBlock16OUT_0_2_BusBlock16OUT is +begin +\Bus_16OUT[0]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In0, + I1 => Mask(0), + O => Bus_16OUT(0) + ); +\Bus_16OUT[10]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In10, + I1 => Mask(10), + O => Bus_16OUT(10) + ); +\Bus_16OUT[11]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In11, + I1 => Mask(11), + O => Bus_16OUT(11) + ); +\Bus_16OUT[12]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In12, + I1 => Mask(12), + O => Bus_16OUT(12) + ); +\Bus_16OUT[13]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In13, + I1 => Mask(13), + O => Bus_16OUT(13) + ); +\Bus_16OUT[14]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In14, + I1 => Mask(14), + O => Bus_16OUT(14) + ); +\Bus_16OUT[15]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In15, + I1 => Mask(15), + O => Bus_16OUT(15) + ); +\Bus_16OUT[1]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In1, + I1 => Mask(1), + O => Bus_16OUT(1) + ); +\Bus_16OUT[2]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In2, + I1 => Mask(2), + O => Bus_16OUT(2) + ); +\Bus_16OUT[3]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In3, + I1 => Mask(3), + O => Bus_16OUT(3) + ); +\Bus_16OUT[4]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In4, + I1 => Mask(4), + O => Bus_16OUT(4) + ); +\Bus_16OUT[5]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In5, + I1 => Mask(5), + O => Bus_16OUT(5) + ); +\Bus_16OUT[6]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In6, + I1 => Mask(6), + O => Bus_16OUT(6) + ); +\Bus_16OUT[7]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In7, + I1 => Mask(7), + O => Bus_16OUT(7) + ); +\Bus_16OUT[8]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In8, + I1 => Mask(8), + O => Bus_16OUT(8) + ); +\Bus_16OUT[9]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In9, + I1 => Mask(9), + O => Bus_16OUT(9) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_BusBlock16OUT_0_2 is + port ( + Bus_16OUT : out STD_LOGIC_VECTOR ( 15 downto 0 ); + In0 : in STD_LOGIC; + In1 : in STD_LOGIC; + In2 : in STD_LOGIC; + In3 : in STD_LOGIC; + In4 : in STD_LOGIC; + In5 : in STD_LOGIC; + In6 : in STD_LOGIC; + In7 : in STD_LOGIC; + In8 : in STD_LOGIC; + In9 : in STD_LOGIC; + In10 : in STD_LOGIC; + In11 : in STD_LOGIC; + In12 : in STD_LOGIC; + In13 : in STD_LOGIC; + In14 : in STD_LOGIC; + In15 : in STD_LOGIC; + Mask : in STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_BusBlock16OUT_0_2 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_BusBlock16OUT_0_2 : entity is "AckChecker_BusBlock16OUT_0_0,BusBlock16OUT,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_BusBlock16OUT_0_2 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_BusBlock16OUT_0_2 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_BusBlock16OUT_0_2 : entity is "BusBlock16OUT,Vivado 2019.1"; +end AckChecker_BusBlock16OUT_0_2; + +architecture STRUCTURE of AckChecker_BusBlock16OUT_0_2 is +begin +U0: entity work.AckChecker_BusBlock16OUT_0_2_BusBlock16OUT + port map ( + Bus_16OUT(15 downto 0) => Bus_16OUT(15 downto 0), + In0 => In0, + In1 => In1, + In10 => In10, + In11 => In11, + In12 => In12, + In13 => In13, + In14 => In14, + In15 => In15, + In2 => In2, + In3 => In3, + In4 => In4, + In5 => In5, + In6 => In6, + In7 => In7, + In8 => In8, + In9 => In9, + Mask(15 downto 0) => Mask(15 downto 0) + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_stub.v new file mode 100644 index 0000000..b7c662b --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_stub.v @@ -0,0 +1,38 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:54 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_BusBlock16OUT_0_2 -prefix +// AckChecker_BusBlock16OUT_0_2_ AckChecker_BusBlock16OUT_0_0_stub.v +// Design : AckChecker_BusBlock16OUT_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "BusBlock16OUT,Vivado 2019.1" *) +module AckChecker_BusBlock16OUT_0_2(Bus_16OUT, In0, In1, In2, In3, In4, In5, In6, In7, In8, In9, + In10, In11, In12, In13, In14, In15, Mask) +/* synthesis syn_black_box black_box_pad_pin="Bus_16OUT[15:0],In0,In1,In2,In3,In4,In5,In6,In7,In8,In9,In10,In11,In12,In13,In14,In15,Mask[15:0]" */; + output [15:0]Bus_16OUT; + input In0; + input In1; + input In2; + input In3; + input In4; + input In5; + input In6; + input In7; + input In8; + input In9; + input In10; + input In11; + input In12; + input In13; + input In14; + input In15; + input [15:0]Mask; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_stub.vhdl new file mode 100644 index 0000000..7db3bb4 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_0_2/AckChecker_BusBlock16OUT_0_2_stub.vhdl @@ -0,0 +1,47 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:54 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_BusBlock16OUT_0_2 -prefix +-- AckChecker_BusBlock16OUT_0_2_ AckChecker_BusBlock16OUT_0_0_stub.vhdl +-- Design : AckChecker_BusBlock16OUT_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_BusBlock16OUT_0_2 is + Port ( + Bus_16OUT : out STD_LOGIC_VECTOR ( 15 downto 0 ); + In0 : in STD_LOGIC; + In1 : in STD_LOGIC; + In2 : in STD_LOGIC; + In3 : in STD_LOGIC; + In4 : in STD_LOGIC; + In5 : in STD_LOGIC; + In6 : in STD_LOGIC; + In7 : in STD_LOGIC; + In8 : in STD_LOGIC; + In9 : in STD_LOGIC; + In10 : in STD_LOGIC; + In11 : in STD_LOGIC; + In12 : in STD_LOGIC; + In13 : in STD_LOGIC; + In14 : in STD_LOGIC; + In15 : in STD_LOGIC; + Mask : in STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + +end AckChecker_BusBlock16OUT_0_2; + +architecture stub of AckChecker_BusBlock16OUT_0_2 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "Bus_16OUT[15:0],In0,In1,In2,In3,In4,In5,In6,In7,In8,In9,In10,In11,In12,In13,In14,In15,Mask[15:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "BusBlock16OUT,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0.dcp 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a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0.xml @@ -95,6 +95,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:37:26 UTC 2023 + + + outputProductCRC + 9:df2d0f1e + + + @@ -372,6 +390,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + AckChecker_BusBlock16OUT_1_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + AckChecker_BusBlock16OUT_1_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_BusBlock16OUT_1_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + AckChecker_BusBlock16OUT_1_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + AckChecker_BusBlock16OUT_1_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + BusBlock16OUT_v1_0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_sim_netlist.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_sim_netlist.v new file mode 100644 index 0000000..2edae4c --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_sim_netlist.v @@ -0,0 +1,319 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:54 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top AckChecker_BusBlock16OUT_1_0 -prefix +// AckChecker_BusBlock16OUT_1_0_ AckChecker_BusBlock16OUT_0_0_sim_netlist.v +// Design : AckChecker_BusBlock16OUT_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "AckChecker_BusBlock16OUT_0_0,BusBlock16OUT,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "BusBlock16OUT,Vivado 2019.1" *) +(* NotValidForBitStream *) +module AckChecker_BusBlock16OUT_1_0 + (Bus_16OUT, + In0, + In1, + In2, + In3, + In4, + In5, + In6, + In7, + In8, + In9, + In10, + In11, + In12, + In13, + In14, + In15, + Mask); + output [15:0]Bus_16OUT; + input In0; + input In1; + input In2; + input In3; + input In4; + input In5; + input In6; + input In7; + input In8; + input In9; + input In10; + input In11; + input In12; + input In13; + input In14; + input In15; + input [15:0]Mask; + + wire [15:0]Bus_16OUT; + wire In0; + wire In1; + wire In10; + wire In11; + wire In12; + wire In13; + wire In14; + wire In15; + wire In2; + wire In3; + wire In4; + wire In5; + wire In6; + wire In7; + wire In8; + wire In9; + wire [15:0]Mask; + + AckChecker_BusBlock16OUT_1_0_BusBlock16OUT U0 + (.Bus_16OUT(Bus_16OUT), + .In0(In0), + .In1(In1), + .In10(In10), + .In11(In11), + .In12(In12), + .In13(In13), + .In14(In14), + .In15(In15), + .In2(In2), + .In3(In3), + .In4(In4), + .In5(In5), + .In6(In6), + .In7(In7), + .In8(In8), + .In9(In9), + .Mask(Mask)); +endmodule + +module AckChecker_BusBlock16OUT_1_0_BusBlock16OUT + (Bus_16OUT, + In0, + Mask, + In1, + In2, + In3, + In4, + In5, + In6, + In7, + In8, + In9, + In10, + In11, + In12, + In13, + In14, + In15); + output [15:0]Bus_16OUT; + input In0; + input [15:0]Mask; + input In1; + input In2; + input In3; + input In4; + input In5; + input In6; + input In7; + input In8; + input In9; + input In10; + input In11; + input In12; + input In13; + input In14; + input In15; + + wire [15:0]Bus_16OUT; + wire In0; + wire In1; + wire In10; + wire In11; + wire In12; + wire In13; + wire In14; + wire In15; + wire In2; + wire In3; + wire In4; + wire In5; + wire In6; + wire In7; + wire In8; + wire In9; + wire [15:0]Mask; + + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[0]_INST_0 + (.I0(In0), + .I1(Mask[0]), + .O(Bus_16OUT[0])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[10]_INST_0 + (.I0(In10), + .I1(Mask[10]), + .O(Bus_16OUT[10])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[11]_INST_0 + (.I0(In11), + .I1(Mask[11]), + .O(Bus_16OUT[11])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[12]_INST_0 + (.I0(In12), + .I1(Mask[12]), + .O(Bus_16OUT[12])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[13]_INST_0 + (.I0(In13), + .I1(Mask[13]), + .O(Bus_16OUT[13])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[14]_INST_0 + (.I0(In14), + .I1(Mask[14]), + .O(Bus_16OUT[14])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[15]_INST_0 + (.I0(In15), + .I1(Mask[15]), + .O(Bus_16OUT[15])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[1]_INST_0 + (.I0(In1), + .I1(Mask[1]), + .O(Bus_16OUT[1])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[2]_INST_0 + (.I0(In2), + .I1(Mask[2]), + .O(Bus_16OUT[2])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[3]_INST_0 + (.I0(In3), + .I1(Mask[3]), + .O(Bus_16OUT[3])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[4]_INST_0 + (.I0(In4), + .I1(Mask[4]), + .O(Bus_16OUT[4])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[5]_INST_0 + (.I0(In5), + .I1(Mask[5]), + .O(Bus_16OUT[5])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[6]_INST_0 + (.I0(In6), + .I1(Mask[6]), + .O(Bus_16OUT[6])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[7]_INST_0 + (.I0(In7), + .I1(Mask[7]), + .O(Bus_16OUT[7])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[8]_INST_0 + (.I0(In8), + .I1(Mask[8]), + .O(Bus_16OUT[8])); + LUT2 #( + .INIT(4'h8)) + \Bus_16OUT[9]_INST_0 + (.I0(In9), + .I1(Mask[9]), + .O(Bus_16OUT[9])); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_sim_netlist.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_sim_netlist.vhdl new file mode 100644 index 0000000..1a1d210 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_sim_netlist.vhdl @@ -0,0 +1,247 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:54 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top AckChecker_BusBlock16OUT_1_0 -prefix +-- AckChecker_BusBlock16OUT_1_0_ AckChecker_BusBlock16OUT_0_0_sim_netlist.vhdl +-- Design : AckChecker_BusBlock16OUT_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_BusBlock16OUT_1_0_BusBlock16OUT is + port ( + Bus_16OUT : out STD_LOGIC_VECTOR ( 15 downto 0 ); + In0 : in STD_LOGIC; + Mask : in STD_LOGIC_VECTOR ( 15 downto 0 ); + In1 : in STD_LOGIC; + In2 : in STD_LOGIC; + In3 : in STD_LOGIC; + In4 : in STD_LOGIC; + In5 : in STD_LOGIC; + In6 : in STD_LOGIC; + In7 : in STD_LOGIC; + In8 : in STD_LOGIC; + In9 : in STD_LOGIC; + In10 : in STD_LOGIC; + In11 : in STD_LOGIC; + In12 : in STD_LOGIC; + In13 : in STD_LOGIC; + In14 : in STD_LOGIC; + In15 : in STD_LOGIC + ); +end AckChecker_BusBlock16OUT_1_0_BusBlock16OUT; + +architecture STRUCTURE of AckChecker_BusBlock16OUT_1_0_BusBlock16OUT is +begin +\Bus_16OUT[0]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In0, + I1 => Mask(0), + O => Bus_16OUT(0) + ); +\Bus_16OUT[10]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In10, + I1 => Mask(10), + O => Bus_16OUT(10) + ); +\Bus_16OUT[11]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In11, + I1 => Mask(11), + O => Bus_16OUT(11) + ); +\Bus_16OUT[12]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In12, + I1 => Mask(12), + O => Bus_16OUT(12) + ); +\Bus_16OUT[13]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In13, + I1 => Mask(13), + O => Bus_16OUT(13) + ); +\Bus_16OUT[14]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In14, + I1 => Mask(14), + O => Bus_16OUT(14) + ); +\Bus_16OUT[15]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In15, + I1 => Mask(15), + O => Bus_16OUT(15) + ); +\Bus_16OUT[1]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In1, + I1 => Mask(1), + O => Bus_16OUT(1) + ); +\Bus_16OUT[2]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In2, + I1 => Mask(2), + O => Bus_16OUT(2) + ); +\Bus_16OUT[3]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In3, + I1 => Mask(3), + O => Bus_16OUT(3) + ); +\Bus_16OUT[4]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In4, + I1 => Mask(4), + O => Bus_16OUT(4) + ); +\Bus_16OUT[5]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In5, + I1 => Mask(5), + O => Bus_16OUT(5) + ); +\Bus_16OUT[6]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In6, + I1 => Mask(6), + O => Bus_16OUT(6) + ); +\Bus_16OUT[7]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In7, + I1 => Mask(7), + O => Bus_16OUT(7) + ); +\Bus_16OUT[8]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In8, + I1 => Mask(8), + O => Bus_16OUT(8) + ); +\Bus_16OUT[9]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => In9, + I1 => Mask(9), + O => Bus_16OUT(9) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AckChecker_BusBlock16OUT_1_0 is + port ( + Bus_16OUT : out STD_LOGIC_VECTOR ( 15 downto 0 ); + In0 : in STD_LOGIC; + In1 : in STD_LOGIC; + In2 : in STD_LOGIC; + In3 : in STD_LOGIC; + In4 : in STD_LOGIC; + In5 : in STD_LOGIC; + In6 : in STD_LOGIC; + In7 : in STD_LOGIC; + In8 : in STD_LOGIC; + In9 : in STD_LOGIC; + In10 : in STD_LOGIC; + In11 : in STD_LOGIC; + In12 : in STD_LOGIC; + In13 : in STD_LOGIC; + In14 : in STD_LOGIC; + In15 : in STD_LOGIC; + Mask : in STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of AckChecker_BusBlock16OUT_1_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of AckChecker_BusBlock16OUT_1_0 : entity is "AckChecker_BusBlock16OUT_0_0,BusBlock16OUT,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of AckChecker_BusBlock16OUT_1_0 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of AckChecker_BusBlock16OUT_1_0 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of AckChecker_BusBlock16OUT_1_0 : entity is "BusBlock16OUT,Vivado 2019.1"; +end AckChecker_BusBlock16OUT_1_0; + +architecture STRUCTURE of AckChecker_BusBlock16OUT_1_0 is +begin +U0: entity work.AckChecker_BusBlock16OUT_1_0_BusBlock16OUT + port map ( + Bus_16OUT(15 downto 0) => Bus_16OUT(15 downto 0), + In0 => In0, + In1 => In1, + In10 => In10, + In11 => In11, + In12 => In12, + In13 => In13, + In14 => In14, + In15 => In15, + In2 => In2, + In3 => In3, + In4 => In4, + In5 => In5, + In6 => In6, + In7 => In7, + In8 => In8, + In9 => In9, + Mask(15 downto 0) => Mask(15 downto 0) + ); +end STRUCTURE; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_stub.v b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_stub.v new file mode 100644 index 0000000..f0424bd --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_stub.v @@ -0,0 +1,38 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed May 3 11:35:54 2023 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top AckChecker_BusBlock16OUT_1_0 -prefix +// AckChecker_BusBlock16OUT_1_0_ AckChecker_BusBlock16OUT_0_0_stub.v +// Design : AckChecker_BusBlock16OUT_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "BusBlock16OUT,Vivado 2019.1" *) +module AckChecker_BusBlock16OUT_1_0(Bus_16OUT, In0, In1, In2, In3, In4, In5, In6, In7, In8, In9, + In10, In11, In12, In13, In14, In15, Mask) +/* synthesis syn_black_box black_box_pad_pin="Bus_16OUT[15:0],In0,In1,In2,In3,In4,In5,In6,In7,In8,In9,In10,In11,In12,In13,In14,In15,Mask[15:0]" */; + output [15:0]Bus_16OUT; + input In0; + input In1; + input In2; + input In3; + input In4; + input In5; + input In6; + input In7; + input In8; + input In9; + input In10; + input In11; + input In12; + input In13; + input In14; + input In15; + input [15:0]Mask; +endmodule diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_stub.vhdl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_stub.vhdl new file mode 100644 index 0000000..eb4ef2c --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16OUT_1_0/AckChecker_BusBlock16OUT_1_0_stub.vhdl @@ -0,0 +1,47 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed May 3 11:35:54 2023 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top AckChecker_BusBlock16OUT_1_0 -prefix +-- AckChecker_BusBlock16OUT_1_0_ AckChecker_BusBlock16OUT_0_0_stub.vhdl +-- Design : AckChecker_BusBlock16OUT_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity AckChecker_BusBlock16OUT_1_0 is + Port ( + Bus_16OUT : out STD_LOGIC_VECTOR ( 15 downto 0 ); + In0 : in STD_LOGIC; + In1 : in STD_LOGIC; + In2 : in STD_LOGIC; + In3 : in STD_LOGIC; + In4 : in STD_LOGIC; + In5 : in STD_LOGIC; + In6 : in STD_LOGIC; + In7 : in STD_LOGIC; + In8 : in STD_LOGIC; + In9 : in STD_LOGIC; + In10 : in STD_LOGIC; + In11 : in STD_LOGIC; + In12 : in STD_LOGIC; + In13 : in STD_LOGIC; + In14 : in STD_LOGIC; + In15 : in STD_LOGIC; + Mask : in STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + +end AckChecker_BusBlock16OUT_1_0; + +architecture stub of AckChecker_BusBlock16OUT_1_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "Bus_16OUT[15:0],In0,In1,In2,In3,In4,In5,In6,In7,In8,In9,In10,In11,In12,In13,In14,In15,Mask[15:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "BusBlock16OUT,Vivado 2019.1"; +begin +end; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/xgui/AckChecker_wrapper_v1_0.tcl b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/xgui/AckChecker_wrapper_v1_0.tcl index 0db18e9..2ecca33 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/xgui/AckChecker_wrapper_v1_0.tcl +++ b/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/xgui/AckChecker_wrapper_v1_0.tcl @@ -1,9 +1,6 @@ # Definitional proc to organize widgets for parameters. proc init_gui { IPINST } { ipgui::add_param $IPINST -name "Component_Name" - #Adding Page - ipgui::add_page $IPINST -name "Page 0" - } diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.xpr b/LIB/AckCheckerBlock/AckCheckerBlock.xpr index 0519b87..e62aeff 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.xpr +++ b/LIB/AckCheckerBlock/AckCheckerBlock.xpr @@ -3,7 +3,7 @@ - + @@ -534,9 +534,7 @@ - - Vivado Synthesis Defaults - + @@ -545,9 +543,7 @@ - - Vivado Synthesis Defaults - + @@ -556,9 +552,7 @@ - - Vivado Synthesis Defaults - + @@ -567,9 +561,7 @@ - - Vivado Synthesis Defaults - + @@ -578,9 +570,7 @@ - - Vivado Synthesis Defaults - + @@ -589,9 +579,7 @@ - - Vivado Synthesis Defaults - + @@ -600,9 +588,7 @@ - - Vivado Synthesis Defaults - + @@ -611,9 +597,7 @@ - - Vivado Synthesis Defaults - + @@ -622,9 +606,7 @@ - - Vivado Synthesis Defaults - + @@ -633,9 +615,7 @@ - - Vivado Synthesis Defaults - + @@ -644,9 +624,7 @@ - - Vivado Synthesis Defaults - + @@ -655,9 +633,7 @@ - - Vivado Synthesis Defaults - + @@ -666,9 +642,7 @@ - - Vivado Synthesis Defaults - + @@ -677,9 +651,7 @@ - - Vivado Synthesis Defaults - + @@ -688,9 +660,7 @@ - - Vivado Synthesis Defaults - + @@ -699,9 +669,7 @@ - - Vivado Synthesis Defaults - + @@ -710,9 +678,7 @@ - - Vivado Synthesis Defaults - + @@ -721,9 +687,7 @@ - - Vivado Synthesis Defaults - + @@ -732,9 +696,7 @@ - - Vivado Synthesis Defaults - + @@ -743,9 +705,7 @@ - - Vivado Synthesis Defaults - + @@ -754,9 +714,7 @@ - - Vivado Synthesis Defaults - + @@ -765,9 +723,7 @@ - - Vivado Synthesis Defaults - + @@ -776,9 +732,7 @@ - - Vivado Synthesis Defaults - + @@ -787,9 +741,7 @@ - - Vivado Synthesis Defaults - + @@ -798,9 +750,7 @@ - - Vivado Synthesis Defaults - + @@ -809,9 +759,7 @@ - - Vivado Synthesis Defaults - + @@ -820,9 +768,7 @@ - - Vivado Synthesis Defaults - + @@ -831,9 +777,7 @@ - - Vivado Synthesis Defaults - + @@ -842,9 +786,7 @@ - - Vivado Synthesis Defaults - + @@ -853,9 +795,7 @@ - - Vivado Synthesis Defaults - + @@ -864,9 +804,7 @@ - - Vivado Synthesis Defaults - + @@ -875,9 +813,7 @@ - - Vivado Synthesis Defaults - + @@ -886,9 +822,7 @@ - - Vivado Synthesis Defaults - + @@ -897,9 +831,7 @@ - - Vivado Synthesis Defaults - + @@ -908,9 +840,7 @@ - - Vivado Synthesis Defaults - + @@ -919,9 +849,7 @@ - - Vivado Synthesis Defaults - + @@ -930,9 +858,7 @@ - - Vivado Synthesis Defaults - + @@ -941,9 +867,7 @@ - - Vivado Synthesis Defaults - + @@ -952,9 +876,7 @@ - - Vivado Synthesis Defaults - + @@ -963,9 +885,7 @@ - - Vivado Synthesis Defaults - + @@ -974,9 +894,7 @@ - - Vivado Synthesis Defaults - + @@ -985,9 +903,7 @@ - - Vivado Synthesis Defaults - + @@ -996,9 +912,7 @@ - - Vivado Synthesis Defaults - + @@ -1007,16 +921,14 @@ - - Vivado Synthesis Defaults - + - + @@ -1029,15 +941,12 @@ - - - Default settings for Implementation. - + @@ -1053,9 +962,7 @@ - - Default settings for Implementation. - + @@ -1071,9 +978,7 @@ - - Default settings for Implementation. - + @@ -1089,9 +994,7 @@ - - Default settings for Implementation. - + @@ -1107,9 +1010,7 @@ - - Default settings for Implementation. - + @@ -1125,9 +1026,7 @@ - - Default settings for Implementation. - + @@ -1143,9 +1042,7 @@ - - Default settings for Implementation. - + @@ -1161,9 +1058,7 @@ - - Default settings for Implementation. - + @@ -1179,9 +1074,7 @@ - - Default settings for Implementation. - + @@ -1197,9 +1090,7 @@ - - Default settings for Implementation. - + @@ -1215,9 +1106,7 @@ - - Default settings for Implementation. - + @@ -1233,9 +1122,7 @@ - - Default settings for Implementation. - + @@ -1251,9 +1138,7 @@ - - Default settings for Implementation. - + @@ -1269,9 +1154,7 @@ - - Default settings for Implementation. - + @@ -1287,9 +1170,7 @@ - - Default settings for Implementation. - + @@ -1305,9 +1186,7 @@ - - Default settings for Implementation. - + @@ -1323,9 +1202,7 @@ - - Default settings for Implementation. - + @@ -1341,9 +1218,7 @@ - - Default settings for Implementation. - + @@ -1359,9 +1234,7 @@ - - Default settings for Implementation. - + @@ -1377,9 +1250,7 @@ - - Default settings for Implementation. - + @@ -1395,9 +1266,7 @@ - - Default settings for Implementation. - + @@ -1413,9 +1282,7 @@ - - Default settings for Implementation. - + @@ -1431,9 +1298,7 @@ - - Default settings for Implementation. - + @@ -1449,9 +1314,7 @@ - - Default settings for Implementation. - + @@ -1467,9 +1330,7 @@ - - Default settings for Implementation. - + @@ -1485,9 +1346,7 @@ - - Default settings for Implementation. - + @@ -1503,9 +1362,7 @@ - - Default settings for Implementation. - + @@ -1521,9 +1378,7 @@ - - Default settings for Implementation. - + @@ -1539,9 +1394,7 @@ - - Default settings for Implementation. - + @@ -1557,9 +1410,7 @@ - - Default settings for Implementation. - + @@ -1575,9 +1426,7 @@ - - Default settings for Implementation. - + @@ -1593,9 +1442,7 @@ - - Default settings for Implementation. - + @@ -1611,9 +1458,7 @@ - - Default settings for Implementation. - + @@ -1629,9 +1474,7 @@ - - Default settings for Implementation. - + @@ -1647,9 +1490,7 @@ - - Default settings for Implementation. - + @@ -1665,9 +1506,7 @@ - - Default settings for Implementation. - + @@ -1683,9 +1522,7 @@ - - Default settings for Implementation. - + @@ -1701,9 +1538,7 @@ - - Default settings for Implementation. - + @@ -1719,9 +1554,7 @@ - - Default settings for Implementation. - + @@ -1737,9 +1570,7 @@ - - Default settings for Implementation. - + @@ -1755,9 +1586,7 @@ - - Default settings for Implementation. - + @@ -1773,9 +1602,7 @@ - - Default settings for Implementation. - + @@ -1791,9 +1618,7 @@ - - Default settings for Implementation. - + @@ -1809,9 +1634,7 @@ - - Default settings for Implementation. - + diff --git a/LIB/AckCheckerConcept/AckCheckerConcept.cache/wt/gui_handlers.wdf b/LIB/AckCheckerConcept/AckCheckerConcept.cache/wt/gui_handlers.wdf index 9339290..4717312 100644 --- a/LIB/AckCheckerConcept/AckCheckerConcept.cache/wt/gui_handlers.wdf +++ b/LIB/AckCheckerConcept/AckCheckerConcept.cache/wt/gui_handlers.wdf @@ -1,6 +1,6 @@ version:1 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:36:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f6e616d65:31:00:00 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70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f656469745f696e5f69705f7061636b61676572:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f69705f7061636b616765725f77697a617264:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6e65775f70726f6a656374:32:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f70726f6a656374:32:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f636f6465:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f70726f6a656374:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f636f6465:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:31:00:00 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70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6372656174655f66696c65:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73797374656d6275696c6465726d656e755f69705f646f63756d656e746174696f6e:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73797374656d6275696c646572766965775f6f7269656e746174696f6e:31:00:00 -eof:1422222190 +eof:3407141147 diff --git a/LIB/AckCheckerConcept/AckCheckerConcept.cache/wt/java_command_handlers.wdf b/LIB/AckCheckerConcept/AckCheckerConcept.cache/wt/java_command_handlers.wdf index 70f7fd4..e5f90f3 100644 --- a/LIB/AckCheckerConcept/AckCheckerConcept.cache/wt/java_command_handlers.wdf +++ b/LIB/AckCheckerConcept/AckCheckerConcept.cache/wt/java_command_handlers.wdf @@ -1,12 +1,12 @@ version:1 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:31:00:00 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a/LIB/AckCheckerConcept/AckCheckerConcept.cache/wt/project.wpc +++ b/LIB/AckCheckerConcept/AckCheckerConcept.cache/wt/project.wpc @@ -1,3 +1,3 @@ version:1 -6d6f64655f636f756e7465727c4755494d6f6465:4 +6d6f64655f636f756e7465727c4755494d6f6465:5 eof: diff --git a/LIB/AckCheckerConcept/AckCheckerConcept.cache/wt/webtalk_pa.xml b/LIB/AckCheckerConcept/AckCheckerConcept.cache/wt/webtalk_pa.xml index 4c3ea3a..ffa3a49 100644 --- a/LIB/AckCheckerConcept/AckCheckerConcept.cache/wt/webtalk_pa.xml +++ b/LIB/AckCheckerConcept/AckCheckerConcept.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +

    @@ -18,19 +18,19 @@ This means code written to parse this file will need to be revisited each subseq - - + + - - + + - + @@ -38,16 +38,17 @@ This means code written to parse this file will need to be revisited each subseq - - + + - + - + + @@ -58,22 +59,24 @@ This means code written to parse this file will need to be revisited each subseq - - + + + + - + - +
    diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.cache/ip/2019.1/70127aa8275ccbbd/stats.txt b/LIB/Inverter_3lvl/Inverter_3lvl.cache/ip/2019.1/70127aa8275ccbbd/stats.txt index 5cca4c0..8877e98 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.cache/ip/2019.1/70127aa8275ccbbd/stats.txt +++ b/LIB/Inverter_3lvl/Inverter_3lvl.cache/ip/2019.1/70127aa8275ccbbd/stats.txt @@ -1,2 +1,2 @@ -NumberHits:1 -Timestamp: Fri Jun 11 04:50:06 UTC 2021 +NumberHits:3 +Timestamp: Wed May 03 08:44:45 UTC 2023 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.cache/ip/2019.1/d13ae47df47f67fc/stats.txt b/LIB/Inverter_3lvl/Inverter_3lvl.cache/ip/2019.1/d13ae47df47f67fc/stats.txt index 0903f41..28c2d7c 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.cache/ip/2019.1/d13ae47df47f67fc/stats.txt +++ b/LIB/Inverter_3lvl/Inverter_3lvl.cache/ip/2019.1/d13ae47df47f67fc/stats.txt @@ -1,2 +1,2 @@ -NumberHits:4 -Timestamp: Fri Jun 11 04:48:56 UTC 2021 +NumberHits:7 +Timestamp: Wed May 03 08:44:45 UTC 2023 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.cache/ip/2019.1/fdc8b3b6ee8afc45/stats.txt b/LIB/Inverter_3lvl/Inverter_3lvl.cache/ip/2019.1/fdc8b3b6ee8afc45/stats.txt index 5cb1f60..70c2610 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.cache/ip/2019.1/fdc8b3b6ee8afc45/stats.txt +++ b/LIB/Inverter_3lvl/Inverter_3lvl.cache/ip/2019.1/fdc8b3b6ee8afc45/stats.txt @@ -1,2 +1,2 @@ -NumberHits:5 -Timestamp: Fri Jun 11 04:50:17 UTC 2021 +NumberHits:13 +Timestamp: Wed May 03 08:44:46 UTC 2023 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.cache/wt/gui_handlers.wdf b/LIB/Inverter_3lvl/Inverter_3lvl.cache/wt/gui_handlers.wdf index 97de28e..d58fc95 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.cache/wt/gui_handlers.wdf +++ b/LIB/Inverter_3lvl/Inverter_3lvl.cache/wt/gui_handlers.wdf @@ -1,9 +1,10 @@ version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6162737472616374636f6d62696e656470616e656c5f6164645f656c656d656e74:31:00:00 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+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:69707061636b6167657268616e646c6572:38:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:69707061636b6167657277697a61726468616e646c6572:36:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616b65727362636f6e6e656374696f6e:33:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:33:00:00 @@ -24,7 +24,7 @@ version:1 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:726567656e65726174657273626c61796f7574:33:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265706f72746970737461747573:33:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:36:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:3131:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:3132:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7361766572736264657369676e:3136:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:32:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f6f6c7373657474696e6773:31:00:00 @@ -32,4 +32,4 @@ version:1 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:757067726164656970:36:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:76616c696461746572736264657369676e:35:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b696d706c656d656e746174696f6e:31:00:00 -eof:475999047 +eof:1111550484 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.cache/wt/project.wpc b/LIB/Inverter_3lvl/Inverter_3lvl.cache/wt/project.wpc index dd6e20d..c59b8fc 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.cache/wt/project.wpc +++ b/LIB/Inverter_3lvl/Inverter_3lvl.cache/wt/project.wpc @@ -1,3 +1,3 @@ version:1 -6d6f64655f636f756e7465727c4755494d6f6465:23 +6d6f64655f636f756e7465727c4755494d6f6465:24 eof: diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.cache/wt/synthesis.wdf b/LIB/Inverter_3lvl/Inverter_3lvl.cache/wt/synthesis.wdf index de471fc..c983717 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.cache/wt/synthesis.wdf +++ b/LIB/Inverter_3lvl/Inverter_3lvl.cache/wt/synthesis.wdf @@ -33,7 +33,7 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a323973:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:3939372e3233344d42:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3630352e3033354d42:00:00 -eof:3280944734 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a323673:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313030302e3932364d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3630372e3631374d42:00:00 +eof:226082966 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.cache/wt/webtalk_pa.xml b/LIB/Inverter_3lvl/Inverter_3lvl.cache/wt/webtalk_pa.xml index ce69eb8..d50ebfe 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.cache/wt/webtalk_pa.xml +++ b/LIB/Inverter_3lvl/Inverter_3lvl.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
    @@ -18,18 +18,18 @@ This means code written to parse this file will need to be revisited each subseq - - + + - + - + @@ -42,7 +42,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -52,11 +52,12 @@ This means code written to parse this file will need to be revisited each subseq + - + - - + + @@ -65,10 +66,11 @@ This means code written to parse this file will need to be revisited each subseq - + - + + @@ -87,10 +89,12 @@ This means code written to parse this file will need to be revisited each subseq - + + + - - + + @@ -101,8 +105,9 @@ This means code written to parse this file will need to be revisited each subseq - - + + + @@ -126,7 +131,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -134,8 +139,10 @@ This means code written to parse this file will need to be revisited each subseq - + + + @@ -149,9 +156,9 @@ This means code written to parse this file will need to be revisited each subseq - + - + @@ -177,9 +184,9 @@ This means code written to parse this file will need to be revisited each subseq - + - +
    diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/.jobs/vrs_config_17.xml b/LIB/Inverter_3lvl/Inverter_3lvl.runs/.jobs/vrs_config_17.xml new file mode 100644 index 0000000..a367716 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.runs/.jobs/vrs_config_17.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/.Vivado_Synthesis.queue.rst b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/.Vivado_Synthesis.queue.rst deleted file mode 100644 index e69de29..0000000 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/.vivado.begin.rst b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/.vivado.begin.rst deleted file mode 100644 index 5ef5048..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/.vivado.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/.vivado.end.rst b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/.vivado.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/ISEWrap.js b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/ISEWrap.js deleted file mode 100644 index 97a2ecb..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/ISEWrap.js +++ /dev/null @@ -1,270 +0,0 @@ -// -// Vivado(TM) -// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 -// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. -// - -// GLOBAL VARIABLES -var ISEShell = new ActiveXObject( "WScript.Shell" ); -var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); -var ISERunDir = ""; -var ISELogFile = "runme.log"; -var ISELogFileStr = null; -var ISELogEcho = true; -var ISEOldVersionWSH = false; - - - -// BOOTSTRAP -ISEInit(); - - - -// -// ISE FUNCTIONS -// -function ISEInit() { - - // 1. RUN DIR setup - var ISEScrFP = WScript.ScriptFullName; - var ISEScrN = WScript.ScriptName; - ISERunDir = - ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); - - // 2. LOG file setup - ISELogFileStr = ISEOpenFile( ISELogFile ); - - // 3. LOG echo? - var ISEScriptArgs = WScript.Arguments; - for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var wbemFlagReturnImmediately = 0x10; - var wbemFlagForwardOnly = 0x20; - var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); - var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); - var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); - var NOC = 0; - var NOLP = 0; - var TPM = 0; - - var cpuInfos = new Enumerator(processor); - for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { - var cpuInfo = cpuInfos.item(); - NOC += cpuInfo.NumberOfCores; - NOLP += cpuInfo.NumberOfLogicalProcessors; - } - var csInfos = new Enumerator(computerSystem); - for(;!csInfos.atEnd(); csInfos.moveNext()) { - var csInfo = csInfos.item(); - TPM += csInfo.TotalPhysicalMemory; - } - - var ISEHOSTCORE = NOLP - var ISEMEMTOTAL = TPM - - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/ISEWrap.sh b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/ISEWrap.sh deleted file mode 100644 index f679f2e..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/ISEWrap.sh +++ /dev/null @@ -1,67 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -# - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! -if [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi -ISE_USER=$USER - -ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) -ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) - -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 ] -then - /bin/touch .$ISE_STEP.end.rst -else - /bin/touch .$ISE_STEP.error.rst -fi - -exit $RETVAL - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/Inverter_3lvl_BUS_16IN_0_0.dcp b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/Inverter_3lvl_BUS_16IN_0_0.dcp deleted file mode 100644 index 3e91c775a3b7d2007ade2883f0fd8f203ddd3563..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 5488 zcmai&2T&7T*T<3GqzH)8ksd+_B@&uI03nn}2k96(NN>`lSCJArf&xnDy(l7}(n9D` z1nGiw5Jc(n#qas%eMV+J-n(;VcXoDvb9T?U|8wruQYRp!$HT)T#gn;%)oE*TqARw;!+0g&=J(+6Fr1I}Y==^ecY!@n-J^pYeLnBG@K+&25=?3!{poX+M5&qypmz4fy zSkm@%Q%Z;dWN3%JP1GnkM8`0=EAEJN$}qk@)eR0w^acUC5Qg;vkE+0 z@~f%W^?n7{v7r+;mSSJMtBnC6@6Xc$K~9i*_U2uvK41O3WBZL+f$x4Y^AAPw(yT?HyFr^fX=(b5PLDveP7nk(2ZP{5W%E*3$R!S(vX$qNE^Ju5l*F_Z=@uK0{?VQ;*5r z4>Y<9v?&a1(c`@&`r5So59Lqa5*Sk(=kgZ~wh+}Ba0Kx(V|Tfes9914}##Ic3gm~jBe+|iIfoKekav6X)PD0jDr>v)-gs>1Nl zlG2L^dWXyFN{Z*ip}ofbLBiUnMAoxPfNe~8wUrEn_->oKXad@>=}KMr-T8{F1OhsU zEut&?5G{c)$fw=3f8FxH?d^T3Vbf8k;UQw{E?^@;E4lFLap0SdePjS!cEV&+zG!2N zvW`TCFE!#paN(n6-3YUT-tCyHA952H3h#_QPdI_zw%`kEGGvWZSb~o75g=tIr9BK` zZ?My~A}lVu3G+2H*6|{(1)?8EjjdLz!do{cg>MxZeOy`>bes`*4EL7blIo$d`uvpG zhVpq4yZ{RR5jgNVJYy8#nvoZ8w=wU!czP;&BUpr_OG~2D;IK2icQ*Y2ams4!!Ca&p zGY?x&m`SN))g&#q+IIn8=aKZQtt|GVLj{X$2!$9nxg5=)N=1Z@FUb99zw zw+eK8&r#v`S??wl=$p1YB}}5-RINCu(fRs>H)27uM-WKGk5(;CV>0hGTD5ED8Vjal z?H$R7c^QLP0g7nbwNaQ?zo}FMrJ0!e1W*b6Z3KcHa=0&5LBrbn>QnDfL#G7`>i@=VOVlkFXo@B^m0$$;sW#Kms1x_0pt#y3?=-p7*;iaTAU3%j1+omLPJ@mFJS)3!i>eK z<}bwF%XiXqJ+DfA@InkDA1TgdAv)CNc=uhpXvmV~x}Qn2WqNq*J(l2JZqKmXicbFg zc#e{WO}8WyrALs5iB_ngHyKctUe%q&Y)ic%X?lF&j@Rce=g!|#_Z%F%mFJ-3p6_$( z1qZFqh+qdT-sH!+N_EF&-JJN9GT&;`W<=ra@x%3$<2m#4Lz2T)mB2A4_{`qTL6N!Z zG8-M?m}?*3@lPat`yLBShmvvv4&lS(7%HlsF!K_Oa%@3Zp3zC5bkfZ0X8t~yPuLqWl}A z<>>WmW+KPOf}Og)6+Aem{#$c~8U~bfa9Z;OXY7}2j)M!*g96jn->07F3kSlV_+o|Q z4*JwVYWuS}2Y6Cq$b$zh7K3EIS zisJ)ug0|m{5&k3!yuaP?mf4-l#+5Wh{QoL}9@bXgS{6>D@-$5iS}uK@AQDIUNfHae zHTJUot$kAZclEsKcVa*RlW(l8P*>lgHr8_3J6xAZJWz@>@6j_^bA3C5KyG-lG2dRN z4CI$f`1Tl#dh4fAmX;#qbAt*a}!dth)@tP;07;e1G^sK>M3+Cy{e6m5AIM}Ct;_8ekL2Xs=K8H7z{{^+sdW9JL`SM&ZV2lzg5lsPQgd` z_Z#ZEwukY=n6;6*Xz*@=c#&II-B}^>7hxv#xrwItQ?|A63NOi93ZB}gi9G=wE?Q*S z4R@O~s-of)=&4##zvwkKqTL0e?hDA;rjN{K_JMq&Z`25|RC=WiW=Joi!Pw((MczgZ z?3JPGQ&M{bo|c%TyKApz3#Q06$MfDJEusm3fxuVkJjsU*WEV)=LRJ!}XiLhq`_ll& zWBSpE6z?WuZP}C#UB9HqKqXa{zN5#zbALy*g;I&m6PH|BIOD!N$vkX4UA;Y!HlF&u zHB{kXO2VNT3uFonpplyP{O^J))=hIqGpK!K#$fsrR07LW#M zf9ADq$$31-{(>}2j2W)9 z8{v%g@;~6`a>a-cePZP7XCMMqhH?BEl9FQodlnZ5SM6{{riZPm`{)Un)E82+ba-=r zG#9ARt9N1?$!GNy>wgrPWR3z1Qcv@92Q-;ZWs^{7d&smt|4LcbtWtWN;fCxjhp+v= zj4;Dw?A6;70~V-AG^vC<)f;Y+G+?I#!K{ej{ml#!?-PL)YOV1XB6Tmo7p3X4nE18WzTLZwnU2Qr}BE~l_ciSxEiRcU`V-7*K{^hA`xP((;7qMBpix@u-ba{VBTYW3EQ z39cmP($U`5s+1>#D`X>ThD?gF&v_>#(T88Dc~nhUt105t_+vXJWmhzfQ`;4tSFnxS zuG|#Yj2mH@n-!Ma?^;~&f1UC!Fi2HV*1IqA#mChWqXO>4Z>#K*DP0}uHC%pe1*x&; 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All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------ -| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 -| Date : Fri Jun 11 07:49:57 2021 -| Host : STAS-W10 running 64-bit major release (build 9200) -| Command : report_utilization -file Inverter_3lvl_BUS_16IN_0_0_utilization_synth.rpt -pb Inverter_3lvl_BUS_16IN_0_0_utilization_synth.pb -| Design : Inverter_3lvl_BUS_16IN_0_0 -| Device : 7z020clg484-3 -| Design State : Fully Placed ------------------------------------------------------------------------------------------------------------------------------------------------ - -Utilization Design Information - -Table of Contents ------------------ -1. Slice Logic -1.1 Summary of Registers by Type -2. Slice Logic Distribution -3. Memory -4. DSP -5. IO and GT Specific -6. Clocking -7. Specific Feature -8. Primitives -9. Black Boxes -10. Instantiated Netlists - -1. Slice Logic --------------- - -+-------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------------+------+-------+-----------+-------+ -| Slice LUTs | 0 | 0 | 53200 | 0.00 | -| LUT as Logic | 0 | 0 | 53200 | 0.00 | -| LUT as Memory | 0 | 0 | 17400 | 0.00 | -| Slice Registers | 0 | 0 | 106400 | 0.00 | -| Register as Flip Flop | 0 | 0 | 106400 | 0.00 | -| Register as Latch | 0 | 0 | 106400 | 0.00 | -| F7 Muxes | 0 | 0 | 26600 | 0.00 | -| F8 Muxes | 0 | 0 | 13300 | 0.00 | -+-------------------------+------+-------+-----------+-------+ - - -1.1 Summary of Registers by Type --------------------------------- - -+-------+--------------+-------------+--------------+ -| Total | Clock Enable | Synchronous | Asynchronous | -+-------+--------------+-------------+--------------+ -| 0 | _ | - | - | -| 0 | _ | - | Set | -| 0 | _ | - | Reset | -| 0 | _ | Set | - | -| 0 | _ | Reset | - | -| 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 0 | Yes | - | Reset | -| 0 | Yes | Set | - | -| 0 | Yes | Reset | - | -+-------+--------------+-------------+--------------+ - - -2. Slice Logic Distribution ---------------------------- - -+------------------------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+------------------------------------------+------+-------+-----------+-------+ -| Slice | 0 | 0 | 13300 | 0.00 | -| SLICEL | 0 | 0 | | | -| SLICEM | 0 | 0 | | | -| LUT as Logic | 0 | 0 | 53200 | 0.00 | -| LUT as Memory | 0 | 0 | 17400 | 0.00 | -| LUT as Distributed RAM | 0 | 0 | | | -| LUT as Shift Register | 0 | 0 | | | -| Slice Registers | 0 | 0 | 106400 | 0.00 | -| Register driven from within the Slice | 0 | | | | -| Register driven from outside the Slice | 0 | | | | -| Unique Control Sets | 0 | | 13300 | 0.00 | -+------------------------------------------+------+-------+-----------+-------+ -* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets. - - -3. Memory ---------- - -+----------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------+------+-------+-----------+-------+ -| Block RAM Tile | 0 | 0 | 140 | 0.00 | -| RAMB36/FIFO* | 0 | 0 | 140 | 0.00 | -| RAMB18 | 0 | 0 | 280 | 0.00 | -+----------------+------+-------+-----------+-------+ -* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 - - -4. DSP ------- - -+-----------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------+------+-------+-----------+-------+ -| DSPs | 0 | 0 | 220 | 0.00 | -+-----------+------+-------+-----------+-------+ - - -5. IO and GT Specific ---------------------- - -+-----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 0 | 0 | 200 | 0.00 | -| Bonded IPADs | 0 | 0 | 2 | 0.00 | -| Bonded IOPADs | 0 | 0 | 130 | 0.00 | -| PHY_CONTROL | 0 | 0 | 4 | 0.00 | -| PHASER_REF | 0 | 0 | 4 | 0.00 | -| OUT_FIFO | 0 | 0 | 16 | 0.00 | -| IN_FIFO | 0 | 0 | 16 | 0.00 | -| IDELAYCTRL | 0 | 0 | 4 | 0.00 | -| IBUFDS | 0 | 0 | 192 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 16 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 16 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 200 | 0.00 | -| ILOGIC | 0 | 0 | 200 | 0.00 | -| OLOGIC | 0 | 0 | 200 | 0.00 | -+-----------------------------+------+-------+-----------+-------+ - - -6. Clocking ------------ - -+------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+------------+------+-------+-----------+-------+ -| BUFGCTRL | 0 | 0 | 32 | 0.00 | -| BUFIO | 0 | 0 | 16 | 0.00 | -| MMCME2_ADV | 0 | 0 | 4 | 0.00 | -| PLLE2_ADV | 0 | 0 | 4 | 0.00 | -| BUFMRCE | 0 | 0 | 8 | 0.00 | -| BUFHCE | 0 | 0 | 72 | 0.00 | -| BUFR | 0 | 0 | 16 | 0.00 | -+------------+------+-------+-----------+-------+ - - -7. Specific Feature -------------------- - -+-------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------+------+-------+-----------+-------+ -| BSCANE2 | 0 | 0 | 4 | 0.00 | -| CAPTUREE2 | 0 | 0 | 1 | 0.00 | -| DNA_PORT | 0 | 0 | 1 | 0.00 | -| EFUSE_USR | 0 | 0 | 1 | 0.00 | -| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | -| ICAPE2 | 0 | 0 | 2 | 0.00 | -| STARTUPE2 | 0 | 0 | 1 | 0.00 | -| XADC | 0 | 0 | 1 | 0.00 | -+-------------+------+-------+-----------+-------+ - - -8. Primitives -------------- - -+----------+------+---------------------+ -| Ref Name | Used | Functional Category | -+----------+------+---------------------+ - - -9. Black Boxes --------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - -10. Instantiated Netlists -------------------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/__synthesis_is_complete__ b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/__synthesis_is_complete__ deleted file mode 100644 index e69de29..0000000 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/gen_run.xml b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/gen_run.xml deleted file mode 100644 index 85e9894..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/gen_run.xml +++ /dev/null @@ -1,54 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Vivado Synthesis Defaults - - - - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/htr.txt b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/htr.txt deleted file mode 100644 index e2e5c97..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -REM -REM Vivado(TM) -REM htr.txt: a Vivado-generated description of how-to-repeat the -REM the basic steps of a run. Note that runme.bat/sh needs -REM to be invoked for Vivado to track run status. -REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -REM - -vivado -log Inverter_3lvl_BUS_16IN_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_BUS_16IN_0_0.tcl diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/rundef.js b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/rundef.js deleted file mode 100644 index d51c94c..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/rundef.js +++ /dev/null @@ -1,36 +0,0 @@ -// -// Vivado(TM) -// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.1/bin;"; -} else { - PathVal = "D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.1/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; -eval( EAInclude(ISEJScriptLib) ); - - -ISEStep( "vivado", - "-log Inverter_3lvl_BUS_16IN_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_BUS_16IN_0_0.tcl" ); - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/runme.bat b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/runme.bat deleted file mode 100644 index 1760626..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/runme.bat +++ /dev/null @@ -1,10 +0,0 @@ -@echo off - -rem Vivado (TM) -rem runme.bat: a Vivado-generated Script -rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/runme.sh b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/runme.sh deleted file mode 100644 index f7de9af..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/runme.sh +++ /dev/null @@ -1,43 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# runme.sh: a Vivado-generated Runs Script for UNIX -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# - -echo "This script was generated under a different operating system." -echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" -exit - -if [ -z "$PATH" ]; then - PATH=D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.1/bin -else - PATH=D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.1/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH= -else - LD_LIBRARY_PATH=:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1' -cd "$HD_PWD" - -HD_LOG=runme.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrap.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -EAStep vivado -log Inverter_3lvl_BUS_16IN_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_BUS_16IN_0_0.tcl diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/vivado.jou b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/vivado.jou deleted file mode 100644 index a3b1a52..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1 (64-bit) -# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 -# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Fri Jun 11 07:49:21 2021 -# Process ID: 7204 -# Current directory: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1 -# Command line: vivado.exe -log Inverter_3lvl_BUS_16IN_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_BUS_16IN_0_0.tcl -# Log file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/Inverter_3lvl_BUS_16IN_0_0.vds -# Journal file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1\vivado.jou -#----------------------------------------------------------- -source Inverter_3lvl_BUS_16IN_0_0.tcl -notrace diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/vivado.pb b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/vivado.pb deleted file mode 100644 index c19e2d5e262eeca28f07479e84504ae26798eacb..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 25123 zcmeHQ>2n-M70<|)Od3}ZM?&I+&~Xs4W$*4Bdy`9-Z6%f?WXles!q#ZEB~3g#v&v#3* z*T0}=(W5J5!zRv_Zf@emWo(nK<>;%>8m<0p>DN_qO2X4zzum}?VKqW}$C_jSj2 z#@`d}n;b(f!WS*IP1@LVh|P7ei=Ucuo+{FAj!KeJiTaTX=#h4_bbj&5!c1v(`R1%ssGOH*ClGTD=~PsR~o$S%HN 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qJQGV27HiFNqgkn8S(FnTy>AIcYGWcI9zbXTmg6h%KS;0vq5FUO`88bt diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/.Vivado_Synthesis.queue.rst b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/.Vivado_Synthesis.queue.rst deleted file mode 100644 index e69de29..0000000 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/.vivado.begin.rst b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/.vivado.begin.rst deleted file mode 100644 index 684625c..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/.vivado.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/.vivado.end.rst b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/.vivado.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/ISEWrap.js b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/ISEWrap.js deleted file mode 100644 index 97a2ecb..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/ISEWrap.js +++ /dev/null @@ -1,270 +0,0 @@ -// -// Vivado(TM) -// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 -// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. -// - -// GLOBAL VARIABLES -var ISEShell = new ActiveXObject( "WScript.Shell" ); -var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); -var ISERunDir = ""; -var ISELogFile = "runme.log"; -var ISELogFileStr = null; -var ISELogEcho = true; -var ISEOldVersionWSH = false; - - - -// BOOTSTRAP -ISEInit(); - - - -// -// ISE FUNCTIONS -// -function ISEInit() { - - // 1. RUN DIR setup - var ISEScrFP = WScript.ScriptFullName; - var ISEScrN = WScript.ScriptName; - ISERunDir = - ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); - - // 2. LOG file setup - ISELogFileStr = ISEOpenFile( ISELogFile ); - - // 3. LOG echo? - var ISEScriptArgs = WScript.Arguments; - for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var wbemFlagReturnImmediately = 0x10; - var wbemFlagForwardOnly = 0x20; - var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); - var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); - var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); - var NOC = 0; - var NOLP = 0; - var TPM = 0; - - var cpuInfos = new Enumerator(processor); - for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { - var cpuInfo = cpuInfos.item(); - NOC += cpuInfo.NumberOfCores; - NOLP += cpuInfo.NumberOfLogicalProcessors; - } - var csInfos = new Enumerator(computerSystem); - for(;!csInfos.atEnd(); csInfos.moveNext()) { - var csInfo = csInfos.item(); - TPM += csInfo.TotalPhysicalMemory; - } - - var ISEHOSTCORE = NOLP - var ISEMEMTOTAL = TPM - - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/ISEWrap.sh b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/ISEWrap.sh deleted file mode 100644 index f679f2e..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/ISEWrap.sh +++ /dev/null @@ -1,67 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -# - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! -if [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi -ISE_USER=$USER - -ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) -ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) - -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 ] -then - /bin/touch .$ISE_STEP.end.rst -else - /bin/touch .$ISE_STEP.error.rst -fi - -exit $RETVAL - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/Inverter_3lvl_BUS_16IN_1_0.tcl b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/Inverter_3lvl_BUS_16IN_1_0.tcl deleted file mode 100644 index bbdca67..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/Inverter_3lvl_BUS_16IN_1_0.tcl +++ /dev/null @@ -1,167 +0,0 @@ -# -# Synthesis run script generated by Vivado -# - -set TIME_start [clock seconds] -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -set_param project.vivado.isBlockSynthRun true -create_project -in_memory -part xc7z020clg484-3 - -set_param project.singleFileAddWarning.threshold 0 -set_param project.compositeFile.enableAutoGeneration 0 -set_param synth.vivado.isSynthRun true -set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.cache/wt [current_project] -set_property parent.project_path D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.xpr [current_project] -set_property default_lib xil_defaultlib [current_project] -set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/GITEA/UPzynq20_test/IP [current_project] -update_ip_catalog -set_property ip_output_repo d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.cache/ip [current_project] -set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0.xci - -# Mark all dcp files as not used in implementation to prevent them from being -# stitched into the results of this synthesis run. Any black boxes in the -# design are intentionally left as such for best results. Dcp files will be -# stitched into the design at a later time, either when this synthesis run is -# opened, or when it is stitched into a dependent implementation run. -foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { - set_property used_in_implementation false $dcp -} -set_param ips.enableIPCacheLiteLoad 1 - -set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1 -new_name Inverter_3lvl_BUS_16IN_1_0 -ip [get_ips Inverter_3lvl_BUS_16IN_1_0]] - -if { $cached_ip eq {} } { -close [open __synthesis_is_running__ w] - -synth_design -top Inverter_3lvl_BUS_16IN_1_0 -part xc7z020clg484-3 -mode out_of_context - -#--------------------------------------------------------- -# Generate Checkpoint/Stub/Simulation Files For IP Cache -#--------------------------------------------------------- -# disable binary constraint mode for IPCache checkpoints -set_param constraints.enableBinaryConstraints false - -catch { - write_checkpoint -force -noxdef -rename_prefix Inverter_3lvl_BUS_16IN_1_0_ Inverter_3lvl_BUS_16IN_1_0.dcp - - set ipCachedFiles {} - write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_BUS_16IN_1_0_stub.v - lappend ipCachedFiles Inverter_3lvl_BUS_16IN_1_0_stub.v - - write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_BUS_16IN_1_0_stub.vhdl - lappend ipCachedFiles Inverter_3lvl_BUS_16IN_1_0_stub.vhdl - - write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_BUS_16IN_1_0_sim_netlist.v - lappend ipCachedFiles Inverter_3lvl_BUS_16IN_1_0_sim_netlist.v - - write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_BUS_16IN_1_0_sim_netlist.vhdl - lappend ipCachedFiles Inverter_3lvl_BUS_16IN_1_0_sim_netlist.vhdl -set TIME_taken [expr [clock seconds] - $TIME_start] - - config_ip_cache -add -dcp Inverter_3lvl_BUS_16IN_1_0.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips Inverter_3lvl_BUS_16IN_1_0] -} - -rename_ref -prefix_all Inverter_3lvl_BUS_16IN_1_0_ - -# disable binary constraint mode for synth run checkpoints -set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef Inverter_3lvl_BUS_16IN_1_0.dcp -create_report "Inverter_3lvl_BUS_16IN_1_0_synth_1_synth_report_utilization_0" "report_utilization -file Inverter_3lvl_BUS_16IN_1_0_utilization_synth.rpt -pb Inverter_3lvl_BUS_16IN_1_0_utilization_synth.pb" - -if { [catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/Inverter_3lvl_BUS_16IN_1_0.dcp D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0.dcp -} _RESULT ] } { - send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." - error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." -} - -if { [catch { - write_verilog -force -mode synth_stub D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode synth_stub D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_verilog -force -mode funcsim D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode funcsim D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - - -} else { - - -if { [catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/Inverter_3lvl_BUS_16IN_1_0.dcp D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0.dcp -} _RESULT ] } { - send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." - error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/Inverter_3lvl_BUS_16IN_1_0_stub.v D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/Inverter_3lvl_BUS_16IN_1_0_stub.vhdl D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/Inverter_3lvl_BUS_16IN_1_0_sim_netlist.v D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/Inverter_3lvl_BUS_16IN_1_0_sim_netlist.vhdl D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -}; # end if cached_ip - -if {[file isdir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_BUS_16IN_1_0]} { - catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0_stub.v D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_BUS_16IN_1_0 - } -} - -if {[file isdir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_BUS_16IN_1_0]} { - catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0_stub.vhdl D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_BUS_16IN_1_0 - } -} -file delete __synthesis_is_running__ -close [open __synthesis_is_complete__ w] diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/Inverter_3lvl_BUS_16IN_1_0.vds b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/Inverter_3lvl_BUS_16IN_1_0.vds deleted file mode 100644 index 76a75ca..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/Inverter_3lvl_BUS_16IN_1_0.vds +++ /dev/null @@ -1,18 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1 (64-bit) -# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 -# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Fri Jun 11 07:49:59 2021 -# Process ID: 11172 -# Current directory: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1 -# Command line: vivado.exe -log Inverter_3lvl_BUS_16IN_1_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_BUS_16IN_1_0.tcl -# Log file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/Inverter_3lvl_BUS_16IN_1_0.vds -# Journal file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1\vivado.jou -#----------------------------------------------------------- -source Inverter_3lvl_BUS_16IN_1_0.tcl -notrace -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/UPzynq20_test/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/UPzynq20_test/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1'.) -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP Inverter_3lvl_BUS_16IN_1_0, cache-ID = 70127aa8275ccbbd. -INFO: [Common 17-206] Exiting Vivado at Fri Jun 11 07:50:06 2021... diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/__synthesis_is_complete__ b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/__synthesis_is_complete__ deleted file mode 100644 index e69de29..0000000 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/gen_run.xml b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/gen_run.xml deleted file mode 100644 index afed652..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/gen_run.xml +++ /dev/null @@ -1,54 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Vivado Synthesis Defaults - - - - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/htr.txt b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/htr.txt deleted file mode 100644 index 87441ff..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -REM -REM Vivado(TM) -REM htr.txt: a Vivado-generated description of how-to-repeat the -REM the basic steps of a run. Note that runme.bat/sh needs -REM to be invoked for Vivado to track run status. -REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -REM - -vivado -log Inverter_3lvl_BUS_16IN_1_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_BUS_16IN_1_0.tcl diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/rundef.js b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/rundef.js deleted file mode 100644 index f0bc053..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/rundef.js +++ /dev/null @@ -1,36 +0,0 @@ -// -// Vivado(TM) -// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.1/bin;"; -} else { - PathVal = "D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.1/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; -eval( EAInclude(ISEJScriptLib) ); - - -ISEStep( "vivado", - "-log Inverter_3lvl_BUS_16IN_1_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_BUS_16IN_1_0.tcl" ); - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/runme.bat b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/runme.bat deleted file mode 100644 index 1760626..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/runme.bat +++ /dev/null @@ -1,10 +0,0 @@ -@echo off - -rem Vivado (TM) -rem runme.bat: a Vivado-generated Script -rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/runme.log b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/runme.log deleted file mode 100644 index c794524..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/runme.log +++ /dev/null @@ -1,17 +0,0 @@ - -*** Running vivado - with args -log Inverter_3lvl_BUS_16IN_1_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_BUS_16IN_1_0.tcl - - -****** Vivado v2019.1 (64-bit) - **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 - **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source Inverter_3lvl_BUS_16IN_1_0.tcl -notrace -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/UPzynq20_test/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/UPzynq20_test/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1'.) -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP Inverter_3lvl_BUS_16IN_1_0, cache-ID = 70127aa8275ccbbd. -INFO: [Common 17-206] Exiting Vivado at Fri Jun 11 07:50:06 2021... diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/runme.sh b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/runme.sh deleted file mode 100644 index 0ce629b..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/runme.sh +++ /dev/null @@ -1,43 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# runme.sh: a Vivado-generated Runs Script for UNIX -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# - -echo "This script was generated under a different operating system." -echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" -exit - -if [ -z "$PATH" ]; then - PATH=D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.1/bin -else - PATH=D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.1/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH= -else - LD_LIBRARY_PATH=:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1' -cd "$HD_PWD" - -HD_LOG=runme.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrap.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -EAStep vivado -log Inverter_3lvl_BUS_16IN_1_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_BUS_16IN_1_0.tcl diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/vivado.jou b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/vivado.jou deleted file mode 100644 index 1041227..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1 (64-bit) -# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 -# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Fri Jun 11 07:49:59 2021 -# Process ID: 11172 -# Current directory: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1 -# Command line: vivado.exe -log Inverter_3lvl_BUS_16IN_1_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_BUS_16IN_1_0.tcl -# Log file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/Inverter_3lvl_BUS_16IN_1_0.vds -# Journal file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1\vivado.jou -#----------------------------------------------------------- -source Inverter_3lvl_BUS_16IN_1_0.tcl -notrace diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/vivado.pb b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/vivado.pb deleted file mode 100644 index 70fa00bfe083efb04f23793762f2ff49300cd0c4..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1048 zcmbVLO>fgc5N#-Rr9Ge=I6ycsLR5t+vAyf&qd_3Gv>>AjMTH>Li?#J`nysAOu)7Wk z;=q*~zlIzCjdff|qLK?2%QK#N^XAPndVwCC@qy-MDC8x?J zz3o(Ke#zyzhYuPqG29q$O}BnjHmbLfMR2Mp;|y}c^$Nrcc6ZFKU%=ePIBNdIAq{k& zb%WRO`;)_<-}^F?pGcTkZfp?u$Ts5xnrF8A=jD9cjm7OST%P-V6aA{h1DL5CMry*r z4mpgqy5gy=mjSgy7%08isU!p=I)e+Isu2evCo~hxheMaK)-8~!lv<(WytBZZE8+y1 z!Dp3c%+o04ORE$9uPh`-bghcP zX?zsKa>BJ+Dv7d5wi@|5mu5AU9QEHNxD~%ma1thFChai6YpxNsnk{z?Z|apU_=+A~ zyWoSEP^Q-VAd1Lh;RroE?gk%4Cge0II|CBp10M&BS{jJ)n)xKc(XtzUR?xG)DLkCg zbm+|JtUTX<8>csO&&%?nF27^yWmO|ShUYFU9ZEECN8O? rd#|*BH@O6iA#8V>VK;063CX_>=;3z5Aup4-gV2d&aOVCB&8n5(z@$2$ diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/.Vivado_Synthesis.queue.rst b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/.Vivado_Synthesis.queue.rst deleted file mode 100644 index e69de29..0000000 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/.vivado.begin.rst b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/.vivado.begin.rst deleted file mode 100644 index 52213ea..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/.vivado.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/.vivado.end.rst b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/.vivado.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/ISEWrap.js b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/ISEWrap.js deleted file mode 100644 index 97a2ecb..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/ISEWrap.js +++ /dev/null @@ -1,270 +0,0 @@ -// -// Vivado(TM) -// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 -// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. -// - -// GLOBAL VARIABLES -var ISEShell = new ActiveXObject( "WScript.Shell" ); -var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); -var ISERunDir = ""; -var ISELogFile = "runme.log"; -var ISELogFileStr = null; -var ISELogEcho = true; -var ISEOldVersionWSH = false; - - - -// BOOTSTRAP -ISEInit(); - - - -// -// ISE FUNCTIONS -// -function ISEInit() { - - // 1. RUN DIR setup - var ISEScrFP = WScript.ScriptFullName; - var ISEScrN = WScript.ScriptName; - ISERunDir = - ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); - - // 2. LOG file setup - ISELogFileStr = ISEOpenFile( ISELogFile ); - - // 3. LOG echo? - var ISEScriptArgs = WScript.Arguments; - for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var wbemFlagReturnImmediately = 0x10; - var wbemFlagForwardOnly = 0x20; - var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); - var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); - var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); - var NOC = 0; - var NOLP = 0; - var TPM = 0; - - var cpuInfos = new Enumerator(processor); - for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { - var cpuInfo = cpuInfos.item(); - NOC += cpuInfo.NumberOfCores; - NOLP += cpuInfo.NumberOfLogicalProcessors; - } - var csInfos = new Enumerator(computerSystem); - for(;!csInfos.atEnd(); csInfos.moveNext()) { - var csInfo = csInfos.item(); - TPM += csInfo.TotalPhysicalMemory; - } - - var ISEHOSTCORE = NOLP - var ISEMEMTOTAL = TPM - - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/ISEWrap.sh b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/ISEWrap.sh deleted file mode 100644 index f679f2e..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/ISEWrap.sh +++ /dev/null @@ -1,67 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -# - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! -if [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi -ISE_USER=$USER - -ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) -ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) - -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 ] -then - /bin/touch .$ISE_STEP.end.rst -else - /bin/touch .$ISE_STEP.error.rst -fi - -exit $RETVAL - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0.dcp b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0.dcp deleted file mode 100644 index 025e582f768bcab573d651f634c02268bf513597..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 53801 zcmZsCV|X5I&~}_Owr$(CZ98dfHBMvOw#~-2Z99$Cu;1N2&+G5UwKH?hIl4Bx$Gyj9 z6=gudP=SDepnwGVCzM}xXDaG}fq*W-fPf$YsHuqqy@#z$@}iD?CL<=q?!}RYrmihU zaY$TFQW110t0WjPyyX=whEq3s@VB&*Um+Z7G_N zfoN~l<>+0(xv)|g5!cn-_VGndb8)Ad=faBjkcww)we*AqW^%6W%Bm?~?*<47 zH-p~t&L)?X zRg1snqZp{W3d7Vu3||TN9hlV&^L0?CJ`{LL)u)PTWqE{yj5`i!>+c@tK0LfW$J+2? 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z@=2@T%&gn`GP`~0d9M+?#!l6x#vv`bTeolHEMr^O2MtpX2Ss?9aj33Xgs}cX_8U}@ z^IWWeSKIyOMyW+P*`O3iV=|Y?xjTH1_{%>TVX~ZV!Y@OXz}*5|*p{3>EZj<(H6mtT z*l-aN5Iv`>U#89HS=WnkziU*$d`NKmlHHIH{^#M^Px;u36>|E@dA*%7Jn?@?Tv*K3LZq2GHQaYB(VSimjo!6hrG=MR;`2_^>)74avqi!}O zqZGGX`^WK-#dENO!;F2+$o_HM%&S*7DreoY1l1Q8$7O!+EQ;=U5$3J^`C3=wS0B7Z60z{}RO82vlaeg;(cwmY&sJ4m}G_PjCZRxjZfI zLZj{T(W$ISgeTo+=P}gtyFXXTBB92oI?nD-g(+(G2eqY;m+^z-NnNdW-hePmtr%EZ z$ren`E`+|>s*}VB$$`haKQQ0{v&G>~CDu!u+^_6@b*6wDi&E$iDwj^C`#ighNTZ>W zG#N1-W==Bb+Vi_SCLOvbd4Y>6lj^l8KV$ZcB#5N>Y);{+)@yn&-pALNblLTjA0g?g}!=`A1;h}Z&s#_rLDcyHr<`a{M&N9In3mfq=JH?&kVbQ}_O z*9)`5J~zV0mKnGg?WVgCPKcRmV~81HYlS3>{+{C0z4Yc~ z#caT2OQO?V)Jo1DIBI^zs z?nenD^33FB0^WMS8vhY?1Z=veU~(eN58+D5niyfCDlZ z)Z{enkryLy7z3H_$p8o>3o=mha_|fEu`=+2ng+UC={N>p6zr``u%3QCDsapdb9H}j QML9#M+n75Tw87QC0WH5xH2?qr diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0.tcl b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0.tcl deleted file mode 100644 index 44d0a83..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0.tcl +++ /dev/null @@ -1,167 +0,0 @@ -# -# Synthesis run script generated by Vivado -# - -set TIME_start [clock seconds] -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -set_param project.vivado.isBlockSynthRun true -create_project -in_memory -part xc7z020clg484-3 - -set_param project.singleFileAddWarning.threshold 0 -set_param project.compositeFile.enableAutoGeneration 0 -set_param synth.vivado.isSynthRun true -set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.cache/wt [current_project] -set_property parent.project_path D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.xpr [current_project] -set_property default_lib xil_defaultlib [current_project] -set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/GITEA/UPzynq20_test/IP [current_project] -update_ip_catalog -set_property ip_output_repo d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.cache/ip [current_project] -set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0.xci - -# Mark all dcp files as not used in implementation to prevent them from being -# stitched into the results of this synthesis run. Any black boxes in the -# design are intentionally left as such for best results. Dcp files will be -# stitched into the design at a later time, either when this synthesis run is -# opened, or when it is stitched into a dependent implementation run. -foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { - set_property used_in_implementation false $dcp -} -set_param ips.enableIPCacheLiteLoad 1 - -set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1 -new_name Inverter_3lvl_P0N_3lvl_0_0 -ip [get_ips Inverter_3lvl_P0N_3lvl_0_0]] - -if { $cached_ip eq {} } { -close [open __synthesis_is_running__ w] - -synth_design -top Inverter_3lvl_P0N_3lvl_0_0 -part xc7z020clg484-3 -mode out_of_context - -#--------------------------------------------------------- -# Generate Checkpoint/Stub/Simulation Files For IP Cache -#--------------------------------------------------------- -# disable binary constraint mode for IPCache checkpoints -set_param constraints.enableBinaryConstraints false - -catch { - write_checkpoint -force -noxdef -rename_prefix Inverter_3lvl_P0N_3lvl_0_0_ Inverter_3lvl_P0N_3lvl_0_0.dcp - - set ipCachedFiles {} - write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_0_stub.v - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_0_0_stub.v - - write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_0_stub.vhdl - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_0_0_stub.vhdl - - write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_0_sim_netlist.v - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_0_0_sim_netlist.v - - write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_0_sim_netlist.vhdl - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_0_0_sim_netlist.vhdl -set TIME_taken [expr [clock seconds] - $TIME_start] - - config_ip_cache -add -dcp Inverter_3lvl_P0N_3lvl_0_0.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips Inverter_3lvl_P0N_3lvl_0_0] -} - -rename_ref -prefix_all Inverter_3lvl_P0N_3lvl_0_0_ - -# disable binary constraint mode for synth run checkpoints -set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef Inverter_3lvl_P0N_3lvl_0_0.dcp -create_report "Inverter_3lvl_P0N_3lvl_0_0_synth_1_synth_report_utilization_0" "report_utilization -file Inverter_3lvl_P0N_3lvl_0_0_utilization_synth.rpt -pb Inverter_3lvl_P0N_3lvl_0_0_utilization_synth.pb" - -if { [catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0.dcp D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0.dcp -} _RESULT ] } { - send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." - error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." -} - -if { [catch { - write_verilog -force -mode synth_stub D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode synth_stub D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_verilog -force -mode funcsim D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode funcsim D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - - -} else { - - -if { [catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0.dcp D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0.dcp -} _RESULT ] } { - send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." - error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0_stub.v D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0_stub.vhdl D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0_sim_netlist.v D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0_sim_netlist.vhdl D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -}; # end if cached_ip - -if {[file isdir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_0_0]} { - catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0_stub.v D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_0_0 - } -} - -if {[file isdir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_0_0]} { - catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0_stub.vhdl D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_0_0 - } -} -file delete __synthesis_is_running__ -close [open __synthesis_is_complete__ w] diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0.vds b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0.vds deleted file mode 100644 index 7aee048..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0.vds +++ /dev/null @@ -1,273 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1 (64-bit) -# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 -# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Fri Jun 11 07:49:21 2021 -# Process ID: 13028 -# Current directory: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1 -# Command line: vivado.exe -log Inverter_3lvl_P0N_3lvl_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_0.tcl -# Log file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0.vds -# Journal file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1\vivado.jou -#----------------------------------------------------------- -source Inverter_3lvl_P0N_3lvl_0_0.tcl -notrace -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/UPzynq20_test/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/UPzynq20_test/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1'.) -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -Command: synth_design -top Inverter_3lvl_P0N_3lvl_0_0 -part xc7z020clg484-3 -mode out_of_context -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020' -INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 2708 ---------------------------------------------------------------------------------- -Starting Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 575.207 ; gain = 183.516 ---------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_0' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/synth/Inverter_3lvl_P0N_3lvl_0_0.vhd:76] -INFO: [Synth 8-3491] module 'P0N_3lvl' declared at 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:36' bound to instance 'U0' of component 'P0N_3lvl' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/synth/Inverter_3lvl_P0N_3lvl_0_0.vhd:109] -INFO: [Synth 8-638] synthesizing module 'P0N_3lvl' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:61] -WARNING: [Synth 8-6014] Unused sequential element TKin0_prev_reg was removed. [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:154] -WARNING: [Synth 8-6014] Unused sequential element TKin1_prev_reg was removed. [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:155] -INFO: [Synth 8-256] done synthesizing module 'P0N_3lvl' (1#1) [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:61] -INFO: [Synth 8-256] done synthesizing module 'Inverter_3lvl_P0N_3lvl_0_0' (2#1) [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/synth/Inverter_3lvl_P0N_3lvl_0_0.vhd:76] ---------------------------------------------------------------------------------- -Finished Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.098 ; gain = 247.406 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.098 ; gain = 247.406 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Loading Part and Timing Information ---------------------------------------------------------------------------------- -Loading part: xc7z020clg484-3 ---------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.098 ; gain = 247.406 ---------------------------------------------------------------------------------- -INFO: [Device 21-403] Loading part xc7z020clg484-3 -INFO: [Synth 8-4471] merging register 'minTimeEr_sig_reg' into 'minTimeEr_reg' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:98] -INFO: [Synth 8-802] inferred FSM for state register 'lineconfig_reg' in module 'P0N_3lvl' ---------------------------------------------------------------------------------------------------- - State | New Encoding | Previous Encoding ---------------------------------------------------------------------------------------------------- - closed | 0000001 | 000 - n | 0000010 | 110 - tech_closed | 0000100 | 001 - p | 0001000 | 101 - zero_p | 0010000 | 011 - zero | 0100000 | 010 - zero_n | 1000000 | 100 ---------------------------------------------------------------------------------------------------- -INFO: [Synth 8-3354] encoded FSM with state register 'lineconfig_reg' using encoding 'one-hot' in module 'P0N_3lvl' ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 639.098 ; gain = 247.406 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ -No constraint files found. ---------------------------------------------------------------------------------- -Start RTL Component Statistics ---------------------------------------------------------------------------------- -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 19 -+---Muxes : - 7 Input 7 Bit Muxes := 1 - 2 Input 7 Bit Muxes := 16 - 2 Input 1 Bit Muxes := 47 - 7 Input 1 Bit Muxes := 10 ---------------------------------------------------------------------------------- -Finished RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- -Hierarchical RTL Component report -Module P0N_3lvl -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 19 -+---Muxes : - 7 Input 7 Bit Muxes := 1 - 2 Input 7 Bit Muxes := 16 - 2 Input 1 Bit Muxes := 47 - 7 Input 1 Bit Muxes := 10 ---------------------------------------------------------------------------------- -Finished RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Part Resource Summary ---------------------------------------------------------------------------------- -Part Resources: -DSPs: 220 (col length:60) -BRAMs: 280 (col length: RAMB18 60 RAMB36 30) ---------------------------------------------------------------------------------- -Finished Part Resource Summary ---------------------------------------------------------------------------------- -No constraint files found. ---------------------------------------------------------------------------------- -Start Cross Boundary and Area Optimization ---------------------------------------------------------------------------------- -Warning: Parallel synthesis criteria is not met ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 805.633 ; gain = 413.941 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ -No constraint files found. ---------------------------------------------------------------------------------- -Start Timing Optimization ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 810.586 ; gain = 418.895 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Technology Mapping ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 810.766 ; gain = 419.074 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 810.766 ; gain = 419.074 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Renaming Generated Instances ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 810.766 ; gain = 419.074 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Rebuilding User Hierarchy ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 810.766 ; gain = 419.074 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Ports ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 810.766 ; gain = 419.074 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 810.766 ; gain = 419.074 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Nets ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 810.766 ; gain = 419.074 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Writing Synthesis Report ---------------------------------------------------------------------------------- - -Report BlackBoxes: -+-+--------------+----------+ -| |BlackBox name |Instances | -+-+--------------+----------+ -+-+--------------+----------+ - -Report Cell Usage: -+------+-------+------+ -| |Cell |Count | -+------+-------+------+ -|1 |CARRY4 | 36| -|2 |LUT1 | 4| -|3 |LUT2 | 7| -|4 |LUT3 | 4| -|5 |LUT4 | 108| -|6 |LUT5 | 7| -|7 |LUT6 | 23| -|8 |FDRE | 121| -|9 |FDSE | 1| -+------+-------+------+ - -Report Instance Areas: -+------+---------+---------+------+ -| |Instance |Module |Cells | -+------+---------+---------+------+ -|1 |top | | 311| -|2 | U0 |P0N_3lvl | 311| -+------+---------+---------+------+ ---------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 810.766 ; gain = 419.074 ---------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 810.766 ; gain = 419.074 -Synthesis Optimization Complete : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 810.766 ; gain = 419.074 -INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 36 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 929.500 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -INFO: [Common 17-83] Releasing license: Synthesis -20 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. -synth_design completed successfully -synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 929.500 ; gain = 542.844 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 929.500 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Common 17-1381] The checkpoint 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0.dcp' has been generated. -write_checkpoint: Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1387.441 ; gain = 457.941 -WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1388.527 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file Inverter_3lvl_P0N_3lvl_0_0_utilization_synth.rpt -pb Inverter_3lvl_P0N_3lvl_0_0_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Fri Jun 11 07:50:00 2021... diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0_utilization_synth.pb b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0_utilization_synth.pb deleted file mode 100644 index 8641ec5bc586b56d5651fdc89efd9a3e48bd2460..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 224 zcmd;LGcqu=)H9sKtPxzAo10ivsgR$hP+F3ilUbEml9`_e;%28-Dioy_=a&{Grxxp- z;xw0+;lg?Mr@Xr_zp{NR#K3UCX|FKD1%LNe5xo-@cD<4eKyX)*;X}LIQYjF7 ztvrbQ3nV?9k1BxJXH`MuTr~y;9_Ob(l7XSu2t?imk}=LpjX~_S79jF3h;%w?31UyO o;&2Leb9W92@;Pe<5}0exz|i3E6i6~KymbMQdtE^yt!^MT0GGTwl>h($ diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0_utilization_synth.rpt b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0_utilization_synth.rpt deleted file mode 100644 index 8f445a0..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0_utilization_synth.rpt +++ /dev/null @@ -1,176 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------ -| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 -| Date : Fri Jun 11 07:50:00 2021 -| Host : STAS-W10 running 64-bit major release (build 9200) -| Command : report_utilization -file Inverter_3lvl_P0N_3lvl_0_0_utilization_synth.rpt -pb Inverter_3lvl_P0N_3lvl_0_0_utilization_synth.pb -| Design : Inverter_3lvl_P0N_3lvl_0_0 -| Device : 7z020clg484-3 -| Design State : Synthesized ------------------------------------------------------------------------------------------------------------------------------------------------ - -Utilization Design Information - -Table of Contents ------------------ -1. Slice Logic -1.1 Summary of Registers by Type -2. Memory -3. DSP -4. IO and GT Specific -5. Clocking -6. Specific Feature -7. Primitives -8. Black Boxes -9. Instantiated Netlists - -1. Slice Logic --------------- - -+-------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 96 | 0 | 53200 | 0.18 | -| LUT as Logic | 96 | 0 | 53200 | 0.18 | -| LUT as Memory | 0 | 0 | 17400 | 0.00 | -| Slice Registers | 122 | 0 | 106400 | 0.11 | -| Register as Flip Flop | 122 | 0 | 106400 | 0.11 | -| Register as Latch | 0 | 0 | 106400 | 0.00 | -| F7 Muxes | 0 | 0 | 26600 | 0.00 | -| F8 Muxes | 0 | 0 | 13300 | 0.00 | -+-------------------------+------+-------+-----------+-------+ -* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. - - -1.1 Summary of Registers by Type --------------------------------- - -+-------+--------------+-------------+--------------+ -| Total | Clock Enable | Synchronous | Asynchronous | -+-------+--------------+-------------+--------------+ -| 0 | _ | - | - | -| 0 | _ | - | Set | -| 0 | _ | - | Reset | -| 0 | _ | Set | - | -| 0 | _ | Reset | - | -| 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 0 | Yes | - | Reset | -| 1 | Yes | Set | - | -| 121 | Yes | Reset | - | -+-------+--------------+-------------+--------------+ - - -2. Memory ---------- - -+----------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------+------+-------+-----------+-------+ -| Block RAM Tile | 0 | 0 | 140 | 0.00 | -| RAMB36/FIFO* | 0 | 0 | 140 | 0.00 | -| RAMB18 | 0 | 0 | 280 | 0.00 | -+----------------+------+-------+-----------+-------+ -* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 - - -3. DSP ------- - -+-----------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------+------+-------+-----------+-------+ -| DSPs | 0 | 0 | 220 | 0.00 | -+-----------+------+-------+-----------+-------+ - - -4. IO and GT Specific ---------------------- - -+-----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 0 | 0 | 200 | 0.00 | -| Bonded IPADs | 0 | 0 | 2 | 0.00 | -| Bonded IOPADs | 0 | 0 | 130 | 0.00 | -| PHY_CONTROL | 0 | 0 | 4 | 0.00 | -| PHASER_REF | 0 | 0 | 4 | 0.00 | -| OUT_FIFO | 0 | 0 | 16 | 0.00 | -| IN_FIFO | 0 | 0 | 16 | 0.00 | -| IDELAYCTRL | 0 | 0 | 4 | 0.00 | -| IBUFDS | 0 | 0 | 192 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 16 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 16 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 200 | 0.00 | -| ILOGIC | 0 | 0 | 200 | 0.00 | -| OLOGIC | 0 | 0 | 200 | 0.00 | -+-----------------------------+------+-------+-----------+-------+ - - -5. Clocking ------------ - -+------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+------------+------+-------+-----------+-------+ -| BUFGCTRL | 0 | 0 | 32 | 0.00 | -| BUFIO | 0 | 0 | 16 | 0.00 | -| MMCME2_ADV | 0 | 0 | 4 | 0.00 | -| PLLE2_ADV | 0 | 0 | 4 | 0.00 | -| BUFMRCE | 0 | 0 | 8 | 0.00 | -| BUFHCE | 0 | 0 | 72 | 0.00 | -| BUFR | 0 | 0 | 16 | 0.00 | -+------------+------+-------+-----------+-------+ - - -6. Specific Feature -------------------- - -+-------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------+------+-------+-----------+-------+ -| BSCANE2 | 0 | 0 | 4 | 0.00 | -| CAPTUREE2 | 0 | 0 | 1 | 0.00 | -| DNA_PORT | 0 | 0 | 1 | 0.00 | -| EFUSE_USR | 0 | 0 | 1 | 0.00 | -| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | -| ICAPE2 | 0 | 0 | 2 | 0.00 | -| STARTUPE2 | 0 | 0 | 1 | 0.00 | -| XADC | 0 | 0 | 1 | 0.00 | -+-------------+------+-------+-----------+-------+ - - -7. Primitives -------------- - -+----------+------+---------------------+ -| Ref Name | Used | Functional Category | -+----------+------+---------------------+ -| FDRE | 121 | Flop & Latch | -| LUT4 | 108 | LUT | -| CARRY4 | 36 | CarryLogic | -| LUT6 | 23 | LUT | -| LUT5 | 7 | LUT | -| LUT2 | 7 | LUT | -| LUT3 | 4 | LUT | -| LUT1 | 4 | LUT | -| FDSE | 1 | Flop & Latch | -+----------+------+---------------------+ - - -8. Black Boxes --------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - -9. Instantiated Netlists ------------------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/__synthesis_is_complete__ b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/__synthesis_is_complete__ deleted file mode 100644 index e69de29..0000000 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/gen_run.xml b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/gen_run.xml deleted file mode 100644 index 0942e87..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/gen_run.xml +++ /dev/null @@ -1,54 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Vivado Synthesis Defaults - - - - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/htr.txt b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/htr.txt deleted file mode 100644 index 9da35a8..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -REM -REM Vivado(TM) -REM htr.txt: a Vivado-generated description of how-to-repeat the -REM the basic steps of a run. Note that runme.bat/sh needs -REM to be invoked for Vivado to track run status. -REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -REM - -vivado -log Inverter_3lvl_P0N_3lvl_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_0.tcl diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/rundef.js b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/rundef.js deleted file mode 100644 index af106f0..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/rundef.js +++ /dev/null @@ -1,36 +0,0 @@ -// -// Vivado(TM) -// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.1/bin;"; -} else { - PathVal = "D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.1/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; -eval( EAInclude(ISEJScriptLib) ); - - -ISEStep( "vivado", - "-log Inverter_3lvl_P0N_3lvl_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_0.tcl" ); - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/runme.bat b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/runme.bat deleted file mode 100644 index 1760626..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/runme.bat +++ /dev/null @@ -1,10 +0,0 @@ -@echo off - -rem Vivado (TM) -rem runme.bat: a Vivado-generated Script -rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/runme.log b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/runme.log deleted file mode 100644 index c07974c..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/runme.log +++ /dev/null @@ -1,272 +0,0 @@ - -*** Running vivado - with args -log Inverter_3lvl_P0N_3lvl_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_0.tcl - - -****** Vivado v2019.1 (64-bit) - **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 - **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source Inverter_3lvl_P0N_3lvl_0_0.tcl -notrace -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/UPzynq20_test/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/UPzynq20_test/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1'.) -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -Command: synth_design -top Inverter_3lvl_P0N_3lvl_0_0 -part xc7z020clg484-3 -mode out_of_context -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020' -INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 2708 ---------------------------------------------------------------------------------- -Starting Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 575.207 ; gain = 183.516 ---------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_0' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/synth/Inverter_3lvl_P0N_3lvl_0_0.vhd:76] -INFO: [Synth 8-3491] module 'P0N_3lvl' declared at 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:36' bound to instance 'U0' of component 'P0N_3lvl' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/synth/Inverter_3lvl_P0N_3lvl_0_0.vhd:109] -INFO: [Synth 8-638] synthesizing module 'P0N_3lvl' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:61] -WARNING: [Synth 8-6014] Unused sequential element TKin0_prev_reg was removed. [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:154] -WARNING: [Synth 8-6014] Unused sequential element TKin1_prev_reg was removed. [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:155] -INFO: [Synth 8-256] done synthesizing module 'P0N_3lvl' (1#1) [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:61] -INFO: [Synth 8-256] done synthesizing module 'Inverter_3lvl_P0N_3lvl_0_0' (2#1) [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/synth/Inverter_3lvl_P0N_3lvl_0_0.vhd:76] ---------------------------------------------------------------------------------- -Finished Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.098 ; gain = 247.406 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.098 ; gain = 247.406 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Loading Part and Timing Information ---------------------------------------------------------------------------------- -Loading part: xc7z020clg484-3 ---------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.098 ; gain = 247.406 ---------------------------------------------------------------------------------- -INFO: [Device 21-403] Loading part xc7z020clg484-3 -INFO: [Synth 8-4471] merging register 'minTimeEr_sig_reg' into 'minTimeEr_reg' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:98] -INFO: [Synth 8-802] inferred FSM for state register 'lineconfig_reg' in module 'P0N_3lvl' ---------------------------------------------------------------------------------------------------- - State | New Encoding | Previous Encoding ---------------------------------------------------------------------------------------------------- - closed | 0000001 | 000 - n | 0000010 | 110 - tech_closed | 0000100 | 001 - p | 0001000 | 101 - zero_p | 0010000 | 011 - zero | 0100000 | 010 - zero_n | 1000000 | 100 ---------------------------------------------------------------------------------------------------- -INFO: [Synth 8-3354] encoded FSM with state register 'lineconfig_reg' using encoding 'one-hot' in module 'P0N_3lvl' ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 639.098 ; gain = 247.406 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ -No constraint files found. ---------------------------------------------------------------------------------- -Start RTL Component Statistics ---------------------------------------------------------------------------------- -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 19 -+---Muxes : - 7 Input 7 Bit Muxes := 1 - 2 Input 7 Bit Muxes := 16 - 2 Input 1 Bit Muxes := 47 - 7 Input 1 Bit Muxes := 10 ---------------------------------------------------------------------------------- -Finished RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- -Hierarchical RTL Component report -Module P0N_3lvl -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 19 -+---Muxes : - 7 Input 7 Bit Muxes := 1 - 2 Input 7 Bit Muxes := 16 - 2 Input 1 Bit Muxes := 47 - 7 Input 1 Bit Muxes := 10 ---------------------------------------------------------------------------------- -Finished RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Part Resource Summary ---------------------------------------------------------------------------------- -Part Resources: -DSPs: 220 (col length:60) -BRAMs: 280 (col length: RAMB18 60 RAMB36 30) ---------------------------------------------------------------------------------- -Finished Part Resource Summary ---------------------------------------------------------------------------------- -No constraint files found. ---------------------------------------------------------------------------------- -Start Cross Boundary and Area Optimization ---------------------------------------------------------------------------------- -Warning: Parallel synthesis criteria is not met ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 805.633 ; gain = 413.941 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ -No constraint files found. ---------------------------------------------------------------------------------- -Start Timing Optimization ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 810.586 ; gain = 418.895 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Technology Mapping ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 810.766 ; gain = 419.074 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 810.766 ; gain = 419.074 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Renaming Generated Instances ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 810.766 ; gain = 419.074 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Rebuilding User Hierarchy ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 810.766 ; gain = 419.074 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Ports ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 810.766 ; gain = 419.074 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 810.766 ; gain = 419.074 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Nets ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 810.766 ; gain = 419.074 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Writing Synthesis Report ---------------------------------------------------------------------------------- - -Report BlackBoxes: -+-+--------------+----------+ -| |BlackBox name |Instances | -+-+--------------+----------+ -+-+--------------+----------+ - -Report Cell Usage: -+------+-------+------+ -| |Cell |Count | -+------+-------+------+ -|1 |CARRY4 | 36| -|2 |LUT1 | 4| -|3 |LUT2 | 7| -|4 |LUT3 | 4| -|5 |LUT4 | 108| -|6 |LUT5 | 7| -|7 |LUT6 | 23| -|8 |FDRE | 121| -|9 |FDSE | 1| -+------+-------+------+ - -Report Instance Areas: -+------+---------+---------+------+ -| |Instance |Module |Cells | -+------+---------+---------+------+ -|1 |top | | 311| -|2 | U0 |P0N_3lvl | 311| -+------+---------+---------+------+ ---------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 810.766 ; gain = 419.074 ---------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 810.766 ; gain = 419.074 -Synthesis Optimization Complete : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 810.766 ; gain = 419.074 -INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 36 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 929.500 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -INFO: [Common 17-83] Releasing license: Synthesis -20 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. -synth_design completed successfully -synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 929.500 ; gain = 542.844 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 929.500 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Common 17-1381] The checkpoint 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0.dcp' has been generated. -write_checkpoint: Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1387.441 ; gain = 457.941 -WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1388.527 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file Inverter_3lvl_P0N_3lvl_0_0_utilization_synth.rpt -pb Inverter_3lvl_P0N_3lvl_0_0_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Fri Jun 11 07:50:00 2021... diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/runme.sh b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/runme.sh deleted file mode 100644 index 6d9efbe..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/runme.sh +++ /dev/null @@ -1,43 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# runme.sh: a Vivado-generated Runs Script for UNIX -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# - -echo "This script was generated under a different operating system." -echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" -exit - -if [ -z "$PATH" ]; then - PATH=D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.1/bin -else - PATH=D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.1/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH= -else - LD_LIBRARY_PATH=:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1' -cd "$HD_PWD" - -HD_LOG=runme.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrap.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -EAStep vivado -log Inverter_3lvl_P0N_3lvl_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_0.tcl diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/vivado.jou b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/vivado.jou deleted file mode 100644 index 73f85af..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1 (64-bit) -# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 -# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Fri Jun 11 07:49:21 2021 -# Process ID: 13028 -# Current directory: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1 -# Command line: vivado.exe -log Inverter_3lvl_P0N_3lvl_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_0.tcl -# Log file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0.vds -# Journal file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1\vivado.jou -#----------------------------------------------------------- -source Inverter_3lvl_P0N_3lvl_0_0.tcl -notrace diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/vivado.pb b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/vivado.pb deleted file mode 100644 index 57830889038c3b92931f9701978e8b9ee09f4d68..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 29990 zcmeHQ>vJ5(arc1)7)=Ho!i}800MKMc#ulE z+uiH!>FMt2?&;|!pCcdN(sv!*-8ZZ~y1q#ry>GjQXFG=Ok}LC9FDPnd=~Bmb^gZ3$ zS&*AWT-g6efBta({lZ7C%n^^!+qTx#yL8~{jsW6_zOd-NP-0*%%CcIG;3!4%Ot)2j zdHwF%a(R36!IAYy_6xl}lZHR~wjKEBvr?39pswk`#aM_b!nCEUfR+BYQx5 z_JK~leVz6l`z^iWz36|@ynVWBJEJlA2+^K)MDOVxyQfpbI?zm`TcXRj;&~W=X?HZw zur2;e29r|+1UaJj?Sa|FbNCh2XrF=Cx^HP6-SVhs#}O#eYpVmtVK)MlMsN++C(HFK z3m{9aA)S^i%7AE@R4m_KUn#F!2fBknwN>-L6u*_6f#r&q+MCjA{K>Y2f7~O>+i%Mm zv!T|iHO$7s;eyWvL-Jg}1#cJ!TG!6z165T<16IkWZ??)`GEBodEc?GKE0WwS$>px* zX=S6I@qR^>)i^i&v_LMe+P$7;bz5{1oO|)=Tvc6q;(%l0bxh@L@}@teuI?Ip7A<;q zp9%yL#!riV&GG1Ar~W`vq>i~)X;g|TE%xlLPVIr$ws+ed+w$~7F9pT1At)awmx943Z$b~$ zi)y7FNAX7mBE4*TCqoJPMU|y9M5!5PioYw6xkdNN<)wK}apgM&;zpAYj{Sj7TlB60 zU2x64-lCoUfWAZ}sm1=S(m$lSsr6lGx9DPpmgt7wV+!Hg#tMGY*R{8CyIQZ76seA% z>}gOCFHyOnma1}%B^dJW+^9k=Y-1E-_AZMl4}E2;|!r+7h-pE4iQga=9o``s&r6s(^n zbM@Mlx#XQj;R}VG`9={GiO=${E|OPbGy~6fOwGZJX&z(z7M37-&mLG^rlSqZ^)xFG z32N_B2t(htn4)HD6rwk=q1UFzyz9Y7Wg&4k|5drT}AU3y=0VFfWG3x*P5W=lm?YN3ogN1nXCZOX5XD7bHZCMi9vb$uf zc-DXEmMS?UzNPw)W9Iaq705dgnO1FBRt^kbkG{b?YTt*>w5%TwicNpc-VnLwb7YA- zKs;o_oQ+N9AW06&nlH;L|h7>vCa54}h zM9kLO%_QYSTapD1059(Sz3De!XC&=1Ct^2ndkH>z?IkZ z`*h9f*jy7P9@&JGX4nIF^hgdu=aNd_AES~>+DTe;Oq=<%2@;H+l=z=K=@IrYp2{K8 zvGC#VwI;pHM@O3U2m>O^9~2)?@9ejaM;}?r#Yd9lGow#`(%?ZKpp%P_d^Y$z&>g#- zgAYR|7avJJBl<9mCenwaa}0bwDF1L)=Jc7!&ptZ2_~5Y|{yCRQ=)Vi(Wt}P7U}3v& zU_&r%WgEE6Zs3oy4}sk+Ws(I(EN$#slBA+}zi&@ug(jylf{Xv3XPfusP*xq7#ITb+Uym ze0X(?V$4}E*lxDlqB$b=rU>ZsA`rGxi^ut{5Ks9s`SQ<0iY5gI-gF z4lk0Sw=p=>PmNlgu3P;9$A{8-h#JEs01MREw>;F+2d*3gdhKkWM`UH-BHSzWQ$rUh zlMY>$jsbo8Lh`!EHg)oR6kigB67)#B3YM7aimROF?2_BI{R4M%tutUCb>o! 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All Rights Reserved. -// - -// GLOBAL VARIABLES -var ISEShell = new ActiveXObject( "WScript.Shell" ); -var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); -var ISERunDir = ""; -var ISELogFile = "runme.log"; -var ISELogFileStr = null; -var ISELogEcho = true; -var ISEOldVersionWSH = false; - - - -// BOOTSTRAP -ISEInit(); - - - -// -// ISE FUNCTIONS -// -function ISEInit() { - - // 1. RUN DIR setup - var ISEScrFP = WScript.ScriptFullName; - var ISEScrN = WScript.ScriptName; - ISERunDir = - ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); - - // 2. LOG file setup - ISELogFileStr = ISEOpenFile( ISELogFile ); - - // 3. LOG echo? - var ISEScriptArgs = WScript.Arguments; - for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var wbemFlagReturnImmediately = 0x10; - var wbemFlagForwardOnly = 0x20; - var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); - var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); - var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); - var NOC = 0; - var NOLP = 0; - var TPM = 0; - - var cpuInfos = new Enumerator(processor); - for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { - var cpuInfo = cpuInfos.item(); - NOC += cpuInfo.NumberOfCores; - NOLP += cpuInfo.NumberOfLogicalProcessors; - } - var csInfos = new Enumerator(computerSystem); - for(;!csInfos.atEnd(); csInfos.moveNext()) { - var csInfo = csInfos.item(); - TPM += csInfo.TotalPhysicalMemory; - } - - var ISEHOSTCORE = NOLP - var ISEMEMTOTAL = TPM - - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/ISEWrap.sh b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/ISEWrap.sh deleted file mode 100644 index f679f2e..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/ISEWrap.sh +++ /dev/null @@ -1,67 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -# - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! -if [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi -ISE_USER=$USER - -ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) -ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) - -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 ] -then - /bin/touch .$ISE_STEP.end.rst -else - /bin/touch .$ISE_STEP.error.rst -fi - -exit $RETVAL - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/Inverter_3lvl_P0N_3lvl_0_1.tcl b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/Inverter_3lvl_P0N_3lvl_0_1.tcl deleted file mode 100644 index c4135d1..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/Inverter_3lvl_P0N_3lvl_0_1.tcl +++ /dev/null @@ -1,167 +0,0 @@ -# -# Synthesis run script generated by Vivado -# - -set TIME_start [clock seconds] -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -set_param project.vivado.isBlockSynthRun true -create_project -in_memory -part xc7z020clg484-3 - -set_param project.singleFileAddWarning.threshold 0 -set_param project.compositeFile.enableAutoGeneration 0 -set_param synth.vivado.isSynthRun true -set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.cache/wt [current_project] -set_property parent.project_path D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.xpr [current_project] -set_property default_lib xil_defaultlib [current_project] -set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/GITEA/UPzynq20_test/IP [current_project] -update_ip_catalog -set_property ip_output_repo d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.cache/ip [current_project] -set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1.xci - -# Mark all dcp files as not used in implementation to prevent them from being -# stitched into the results of this synthesis run. Any black boxes in the -# design are intentionally left as such for best results. Dcp files will be -# stitched into the design at a later time, either when this synthesis run is -# opened, or when it is stitched into a dependent implementation run. -foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { - set_property used_in_implementation false $dcp -} -set_param ips.enableIPCacheLiteLoad 1 - -set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1 -new_name Inverter_3lvl_P0N_3lvl_0_1 -ip [get_ips Inverter_3lvl_P0N_3lvl_0_1]] - -if { $cached_ip eq {} } { -close [open __synthesis_is_running__ w] - -synth_design -top Inverter_3lvl_P0N_3lvl_0_1 -part xc7z020clg484-3 -mode out_of_context - -#--------------------------------------------------------- -# Generate Checkpoint/Stub/Simulation Files For IP Cache -#--------------------------------------------------------- -# disable binary constraint mode for IPCache checkpoints -set_param constraints.enableBinaryConstraints false - -catch { - write_checkpoint -force -noxdef -rename_prefix Inverter_3lvl_P0N_3lvl_0_1_ Inverter_3lvl_P0N_3lvl_0_1.dcp - - set ipCachedFiles {} - write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_1_stub.v - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_0_1_stub.v - - write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_1_stub.vhdl - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_0_1_stub.vhdl - - write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_1_sim_netlist.v - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_0_1_sim_netlist.v - - write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_1_sim_netlist.vhdl - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_0_1_sim_netlist.vhdl -set TIME_taken [expr [clock seconds] - $TIME_start] - - config_ip_cache -add -dcp Inverter_3lvl_P0N_3lvl_0_1.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips Inverter_3lvl_P0N_3lvl_0_1] -} - -rename_ref -prefix_all Inverter_3lvl_P0N_3lvl_0_1_ - -# disable binary constraint mode for synth run checkpoints -set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef Inverter_3lvl_P0N_3lvl_0_1.dcp -create_report "Inverter_3lvl_P0N_3lvl_0_1_synth_1_synth_report_utilization_0" "report_utilization -file Inverter_3lvl_P0N_3lvl_0_1_utilization_synth.rpt -pb Inverter_3lvl_P0N_3lvl_0_1_utilization_synth.pb" - -if { [catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/Inverter_3lvl_P0N_3lvl_0_1.dcp D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1.dcp -} _RESULT ] } { - send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." - error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." -} - -if { [catch { - write_verilog -force -mode synth_stub D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode synth_stub D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_verilog -force -mode funcsim D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode funcsim D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - - -} else { - - -if { [catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/Inverter_3lvl_P0N_3lvl_0_1.dcp D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1.dcp -} _RESULT ] } { - send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." - error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/Inverter_3lvl_P0N_3lvl_0_1_stub.v D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/Inverter_3lvl_P0N_3lvl_0_1_stub.vhdl D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/Inverter_3lvl_P0N_3lvl_0_1_sim_netlist.v D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/Inverter_3lvl_P0N_3lvl_0_1_sim_netlist.vhdl D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -}; # end if cached_ip - -if {[file isdir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_0_1]} { - catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1_stub.v D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_0_1 - } -} - -if {[file isdir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_0_1]} { - catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1_stub.vhdl D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_0_1 - } -} -file delete __synthesis_is_running__ -close [open __synthesis_is_complete__ w] diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/Inverter_3lvl_P0N_3lvl_0_1.vds b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/Inverter_3lvl_P0N_3lvl_0_1.vds deleted file mode 100644 index 577ae42..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/Inverter_3lvl_P0N_3lvl_0_1.vds +++ /dev/null @@ -1,18 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1 (64-bit) -# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 -# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Fri Jun 11 07:50:03 2021 -# Process ID: 7576 -# Current directory: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1 -# Command line: vivado.exe -log Inverter_3lvl_P0N_3lvl_0_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_1.tcl -# Log file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/Inverter_3lvl_P0N_3lvl_0_1.vds -# Journal file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1\vivado.jou -#----------------------------------------------------------- -source Inverter_3lvl_P0N_3lvl_0_1.tcl -notrace -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/UPzynq20_test/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/UPzynq20_test/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1'.) -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP Inverter_3lvl_P0N_3lvl_0_1, cache-ID = fdc8b3b6ee8afc45. -INFO: [Common 17-206] Exiting Vivado at Fri Jun 11 07:50:09 2021... diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/__synthesis_is_complete__ b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/__synthesis_is_complete__ deleted file mode 100644 index e69de29..0000000 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/gen_run.xml b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/gen_run.xml deleted file mode 100644 index d80953e..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/gen_run.xml +++ /dev/null @@ -1,54 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Vivado Synthesis Defaults - - - - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/htr.txt b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/htr.txt deleted file mode 100644 index c666fc5..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -REM -REM Vivado(TM) -REM htr.txt: a Vivado-generated description of how-to-repeat the -REM the basic steps of a run. Note that runme.bat/sh needs -REM to be invoked for Vivado to track run status. -REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -REM - -vivado -log Inverter_3lvl_P0N_3lvl_0_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_1.tcl diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/rundef.js b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/rundef.js deleted file mode 100644 index 5401dc2..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/rundef.js +++ /dev/null @@ -1,36 +0,0 @@ -// -// Vivado(TM) -// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.1/bin;"; -} else { - PathVal = "D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.1/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; -eval( EAInclude(ISEJScriptLib) ); - - -ISEStep( "vivado", - "-log Inverter_3lvl_P0N_3lvl_0_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_1.tcl" ); - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/runme.bat b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/runme.bat deleted file mode 100644 index 1760626..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/runme.bat +++ /dev/null @@ -1,10 +0,0 @@ -@echo off - -rem Vivado (TM) -rem runme.bat: a Vivado-generated Script -rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/runme.log b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/runme.log deleted file mode 100644 index e909bcd..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/runme.log +++ /dev/null @@ -1,17 +0,0 @@ - -*** Running vivado - with args -log Inverter_3lvl_P0N_3lvl_0_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_1.tcl - - -****** Vivado v2019.1 (64-bit) - **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 - **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source Inverter_3lvl_P0N_3lvl_0_1.tcl -notrace -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/UPzynq20_test/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/UPzynq20_test/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1'.) -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP Inverter_3lvl_P0N_3lvl_0_1, cache-ID = fdc8b3b6ee8afc45. -INFO: [Common 17-206] Exiting Vivado at Fri Jun 11 07:50:09 2021... diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/runme.sh b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/runme.sh deleted file mode 100644 index 673e8db..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/runme.sh +++ /dev/null @@ -1,43 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# runme.sh: a Vivado-generated Runs Script for UNIX -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# - -echo "This script was generated under a different operating system." -echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" -exit - -if [ -z "$PATH" ]; then - PATH=D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.1/bin -else - PATH=D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.1/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH= -else - LD_LIBRARY_PATH=:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1' -cd "$HD_PWD" - -HD_LOG=runme.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrap.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -EAStep vivado -log Inverter_3lvl_P0N_3lvl_0_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_1.tcl diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/vivado.jou b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/vivado.jou deleted file mode 100644 index f41cfc1..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1 (64-bit) -# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 -# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Fri Jun 11 07:50:03 2021 -# Process ID: 7576 -# Current directory: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1 -# Command line: vivado.exe -log Inverter_3lvl_P0N_3lvl_0_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_1.tcl -# Log file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/Inverter_3lvl_P0N_3lvl_0_1.vds -# Journal file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1\vivado.jou -#----------------------------------------------------------- -source Inverter_3lvl_P0N_3lvl_0_1.tcl -notrace diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/vivado.pb b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/vivado.pb deleted file mode 100644 index d74da488f01b9cebffb98e2138d090f127bca30d..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1048 zcmbVL!EVz)5N#-Rr9Ge=I6yftLPUkCvAydgO@lxxG$5l2MHNM;7i;6)BwIPVVRs!8 z#DOa}zJ?qB#yTz}QOSjiX@BBdpSb8&uud+a^)t zU^i8o54pVb@NwNGMq87e+0Kv3R`nLL2+kB`oI!55UW1s!e$DLr1@q%}d1gC*UM_dtSbP+Qt8>3^qhFPH0CSbYSWP+D z5r>IZS3I?cWkBr+21+k?Dha`u&Y{m!HRd4XlxBkYaN;u7x&<v|7FluQaCL89H2uG`K_*p^EE==L!l%^wR zMrY;42HZHknR^b)i@JQx9F|q}_!OSIuyiOPZM - - - - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/.vivado.end.rst b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/.vivado.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/ISEWrap.js b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/ISEWrap.js deleted file mode 100644 index 97a2ecb..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/ISEWrap.js +++ /dev/null @@ -1,270 +0,0 @@ -// -// Vivado(TM) -// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 -// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. -// - -// GLOBAL VARIABLES -var ISEShell = new ActiveXObject( "WScript.Shell" ); -var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); -var ISERunDir = ""; -var ISELogFile = "runme.log"; -var ISELogFileStr = null; -var ISELogEcho = true; -var ISEOldVersionWSH = false; - - - -// BOOTSTRAP -ISEInit(); - - - -// -// ISE FUNCTIONS -// -function ISEInit() { - - // 1. RUN DIR setup - var ISEScrFP = WScript.ScriptFullName; - var ISEScrN = WScript.ScriptName; - ISERunDir = - ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); - - // 2. LOG file setup - ISELogFileStr = ISEOpenFile( ISELogFile ); - - // 3. LOG echo? - var ISEScriptArgs = WScript.Arguments; - for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var wbemFlagReturnImmediately = 0x10; - var wbemFlagForwardOnly = 0x20; - var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); - var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); - var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); - var NOC = 0; - var NOLP = 0; - var TPM = 0; - - var cpuInfos = new Enumerator(processor); - for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { - var cpuInfo = cpuInfos.item(); - NOC += cpuInfo.NumberOfCores; - NOLP += cpuInfo.NumberOfLogicalProcessors; - } - var csInfos = new Enumerator(computerSystem); - for(;!csInfos.atEnd(); csInfos.moveNext()) { - var csInfo = csInfos.item(); - TPM += csInfo.TotalPhysicalMemory; - } - - var ISEHOSTCORE = NOLP - var ISEMEMTOTAL = TPM - - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/ISEWrap.sh b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/ISEWrap.sh deleted file mode 100644 index f679f2e..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/ISEWrap.sh +++ /dev/null @@ -1,67 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -# - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! -if [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi -ISE_USER=$USER - -ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) -ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) - -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 ] -then - /bin/touch .$ISE_STEP.end.rst -else - /bin/touch .$ISE_STEP.error.rst -fi - -exit $RETVAL - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/Inverter_3lvl_P0N_3lvl_0_2.tcl b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/Inverter_3lvl_P0N_3lvl_0_2.tcl deleted file mode 100644 index 02fc4a5..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/Inverter_3lvl_P0N_3lvl_0_2.tcl +++ /dev/null @@ -1,167 +0,0 @@ -# -# Synthesis run script generated by Vivado -# - -set TIME_start [clock seconds] -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -set_param project.vivado.isBlockSynthRun true -create_project -in_memory -part xc7z020clg484-3 - -set_param project.singleFileAddWarning.threshold 0 -set_param project.compositeFile.enableAutoGeneration 0 -set_param synth.vivado.isSynthRun true -set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.cache/wt [current_project] -set_property parent.project_path D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.xpr [current_project] -set_property default_lib xil_defaultlib [current_project] -set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/GITEA/UPzynq20_test/IP [current_project] -update_ip_catalog -set_property ip_output_repo d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.cache/ip [current_project] -set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2.xci - -# Mark all dcp files as not used in implementation to prevent them from being -# stitched into the results of this synthesis run. Any black boxes in the -# design are intentionally left as such for best results. Dcp files will be -# stitched into the design at a later time, either when this synthesis run is -# opened, or when it is stitched into a dependent implementation run. -foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { - set_property used_in_implementation false $dcp -} -set_param ips.enableIPCacheLiteLoad 1 - -set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1 -new_name Inverter_3lvl_P0N_3lvl_0_2 -ip [get_ips Inverter_3lvl_P0N_3lvl_0_2]] - -if { $cached_ip eq {} } { -close [open __synthesis_is_running__ w] - -synth_design -top Inverter_3lvl_P0N_3lvl_0_2 -part xc7z020clg484-3 -mode out_of_context - -#--------------------------------------------------------- -# Generate Checkpoint/Stub/Simulation Files For IP Cache -#--------------------------------------------------------- -# disable binary constraint mode for IPCache checkpoints -set_param constraints.enableBinaryConstraints false - -catch { - write_checkpoint -force -noxdef -rename_prefix Inverter_3lvl_P0N_3lvl_0_2_ Inverter_3lvl_P0N_3lvl_0_2.dcp - - set ipCachedFiles {} - write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_2_stub.v - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_0_2_stub.v - - write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_2_stub.vhdl - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_0_2_stub.vhdl - - write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_2_sim_netlist.v - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_0_2_sim_netlist.v - - write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_2_sim_netlist.vhdl - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_0_2_sim_netlist.vhdl -set TIME_taken [expr [clock seconds] - $TIME_start] - - config_ip_cache -add -dcp Inverter_3lvl_P0N_3lvl_0_2.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips Inverter_3lvl_P0N_3lvl_0_2] -} - -rename_ref -prefix_all Inverter_3lvl_P0N_3lvl_0_2_ - -# disable binary constraint mode for synth run checkpoints -set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef Inverter_3lvl_P0N_3lvl_0_2.dcp -create_report "Inverter_3lvl_P0N_3lvl_0_2_synth_1_synth_report_utilization_0" "report_utilization -file Inverter_3lvl_P0N_3lvl_0_2_utilization_synth.rpt -pb Inverter_3lvl_P0N_3lvl_0_2_utilization_synth.pb" - -if { [catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/Inverter_3lvl_P0N_3lvl_0_2.dcp D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2.dcp -} _RESULT ] } { - send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." - error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." -} - -if { [catch { - write_verilog -force -mode synth_stub D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode synth_stub D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_verilog -force -mode funcsim D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode funcsim D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - - -} else { - - -if { [catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/Inverter_3lvl_P0N_3lvl_0_2.dcp D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2.dcp -} _RESULT ] } { - send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." - error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/Inverter_3lvl_P0N_3lvl_0_2_stub.v D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/Inverter_3lvl_P0N_3lvl_0_2_stub.vhdl D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/Inverter_3lvl_P0N_3lvl_0_2_sim_netlist.v D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/Inverter_3lvl_P0N_3lvl_0_2_sim_netlist.vhdl D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -}; # end if cached_ip - -if {[file isdir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_0_2]} { - catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2_stub.v D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_0_2 - } -} - -if {[file isdir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_0_2]} { - catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2_stub.vhdl D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_0_2 - } -} -file delete __synthesis_is_running__ -close [open __synthesis_is_complete__ w] diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/Inverter_3lvl_P0N_3lvl_0_2.vds b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/Inverter_3lvl_P0N_3lvl_0_2.vds deleted file mode 100644 index 45c05f4..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/Inverter_3lvl_P0N_3lvl_0_2.vds +++ /dev/null @@ -1,18 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1 (64-bit) -# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 -# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Fri Jun 11 07:50:08 2021 -# Process ID: 13100 -# Current directory: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1 -# Command line: vivado.exe -log Inverter_3lvl_P0N_3lvl_0_2.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_2.tcl -# Log file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/Inverter_3lvl_P0N_3lvl_0_2.vds -# Journal file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1\vivado.jou -#----------------------------------------------------------- -source Inverter_3lvl_P0N_3lvl_0_2.tcl -notrace -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/UPzynq20_test/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/UPzynq20_test/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1'.) -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP Inverter_3lvl_P0N_3lvl_0_2, cache-ID = fdc8b3b6ee8afc45. -INFO: [Common 17-206] Exiting Vivado at Fri Jun 11 07:50:13 2021... diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/__synthesis_is_complete__ b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/__synthesis_is_complete__ deleted file mode 100644 index e69de29..0000000 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/gen_run.xml b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/gen_run.xml deleted file mode 100644 index 3012fa6..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/gen_run.xml +++ /dev/null @@ -1,54 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Vivado Synthesis Defaults - - - - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/htr.txt b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/htr.txt deleted file mode 100644 index c0a161c..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -REM -REM Vivado(TM) -REM htr.txt: a Vivado-generated description of how-to-repeat the -REM the basic steps of a run. Note that runme.bat/sh needs -REM to be invoked for Vivado to track run status. -REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -REM - -vivado -log Inverter_3lvl_P0N_3lvl_0_2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_2.tcl diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/rundef.js b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/rundef.js deleted file mode 100644 index 80882c7..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/rundef.js +++ /dev/null @@ -1,36 +0,0 @@ -// -// Vivado(TM) -// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.1/bin;"; -} else { - PathVal = "D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.1/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; -eval( EAInclude(ISEJScriptLib) ); - - -ISEStep( "vivado", - "-log Inverter_3lvl_P0N_3lvl_0_2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_2.tcl" ); - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/runme.bat b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/runme.bat deleted file mode 100644 index 1760626..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/runme.bat +++ /dev/null @@ -1,10 +0,0 @@ -@echo off - -rem Vivado (TM) -rem runme.bat: a Vivado-generated Script -rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/runme.log b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/runme.log deleted file mode 100644 index 44b4e15..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/runme.log +++ /dev/null @@ -1,17 +0,0 @@ - -*** Running vivado - with args -log Inverter_3lvl_P0N_3lvl_0_2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_2.tcl - - -****** Vivado v2019.1 (64-bit) - **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 - **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source Inverter_3lvl_P0N_3lvl_0_2.tcl -notrace -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/UPzynq20_test/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/UPzynq20_test/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1'.) -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP Inverter_3lvl_P0N_3lvl_0_2, cache-ID = fdc8b3b6ee8afc45. -INFO: [Common 17-206] Exiting Vivado at Fri Jun 11 07:50:13 2021... diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/runme.sh b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/runme.sh deleted file mode 100644 index d71c39a..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/runme.sh +++ /dev/null @@ -1,43 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# runme.sh: a Vivado-generated Runs Script for UNIX -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# - -echo "This script was generated under a different operating system." -echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" -exit - -if [ -z "$PATH" ]; then - PATH=D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.1/bin -else - PATH=D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.1/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH= -else - LD_LIBRARY_PATH=:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1' -cd "$HD_PWD" - -HD_LOG=runme.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrap.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -EAStep vivado -log Inverter_3lvl_P0N_3lvl_0_2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_2.tcl diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/vivado.jou b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/vivado.jou deleted file mode 100644 index f3c64ed..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1 (64-bit) -# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 -# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Fri Jun 11 07:50:08 2021 -# Process ID: 13100 -# Current directory: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1 -# Command line: vivado.exe -log Inverter_3lvl_P0N_3lvl_0_2.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_2.tcl -# Log file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/Inverter_3lvl_P0N_3lvl_0_2.vds -# Journal file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1\vivado.jou -#----------------------------------------------------------- -source Inverter_3lvl_P0N_3lvl_0_2.tcl -notrace diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/vivado.pb b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/vivado.pb deleted file mode 100644 index 90f9d5d094ee8a75298c510063137adc0a2aac02..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1048 zcmbVL!EVz)5N#-Nr9Ge=I6yftLR5vSvAydgO@lxxv>>AjMHNM;7i;6)BwIPVVRs!8 z#DOa}zJ?qB#yTz}QOJdhw_3TK!Sks@*~s!MUQ0Gsq3sD-bi--!uDu0dpJUsQDL%)X{y` z3Esr-&rX8N?w6VTM8d>!V}rO$b{Ox|JhPoYFIPKmEItau<+m1|vmxS_Pb6{eKsY0Y!8wA$hS%0hBPH>wz% z$1j6ePPleUB~doXRwG~M(yXSEZuo9qnS=>R%uL#0f;U_vYBgK#8s5|^UGNn>x^ck= zF`-Ot_CXYp#ljJKc-jd*icH99P<93+#K%4k7_~GI;|=pkgrj9Q{H&m7m!|M=O4Fe; zqqFjS18$t&%smI?MO}W+9F|q}_!OSIuyiOPZMWB+MINJCpQY_y)N66x zrv0?hT(6oNxzUc=%hbPB(A~4Cum$-&1Jo9b{5hv>61EOJXVj6BWEXj*LhHEX5Z!yN p1-#8AU<~0=rx|u|1SBN?I-rM->JE9C#2tjrB!dh0S7=tN{047JJPrT= diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/.Vivado_Synthesis.queue.rst b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/.Vivado_Synthesis.queue.rst deleted file mode 100644 index e69de29..0000000 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/.vivado.begin.rst b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/.vivado.begin.rst deleted file mode 100644 index 267b4ff..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/.vivado.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/.vivado.end.rst b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/.vivado.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/ISEWrap.js b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/ISEWrap.js deleted file mode 100644 index 97a2ecb..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/ISEWrap.js +++ /dev/null @@ -1,270 +0,0 @@ -// -// Vivado(TM) -// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 -// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. -// - -// GLOBAL VARIABLES -var ISEShell = new ActiveXObject( "WScript.Shell" ); -var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); -var ISERunDir = ""; -var ISELogFile = "runme.log"; -var ISELogFileStr = null; -var ISELogEcho = true; -var ISEOldVersionWSH = false; - - - -// BOOTSTRAP -ISEInit(); - - - -// -// ISE FUNCTIONS -// -function ISEInit() { - - // 1. RUN DIR setup - var ISEScrFP = WScript.ScriptFullName; - var ISEScrN = WScript.ScriptName; - ISERunDir = - ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); - - // 2. LOG file setup - ISELogFileStr = ISEOpenFile( ISELogFile ); - - // 3. LOG echo? - var ISEScriptArgs = WScript.Arguments; - for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var wbemFlagReturnImmediately = 0x10; - var wbemFlagForwardOnly = 0x20; - var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); - var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); - var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); - var NOC = 0; - var NOLP = 0; - var TPM = 0; - - var cpuInfos = new Enumerator(processor); - for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { - var cpuInfo = cpuInfos.item(); - NOC += cpuInfo.NumberOfCores; - NOLP += cpuInfo.NumberOfLogicalProcessors; - } - var csInfos = new Enumerator(computerSystem); - for(;!csInfos.atEnd(); csInfos.moveNext()) { - var csInfo = csInfos.item(); - TPM += csInfo.TotalPhysicalMemory; - } - - var ISEHOSTCORE = NOLP - var ISEMEMTOTAL = TPM - - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/ISEWrap.sh b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/ISEWrap.sh deleted file mode 100644 index f679f2e..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/ISEWrap.sh +++ /dev/null @@ -1,67 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -# - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! -if [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi -ISE_USER=$USER - -ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) -ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) - -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 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mode 100644 index ce86c6f..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/Inverter_3lvl_P0N_3lvl_0_4.tcl +++ /dev/null @@ -1,167 +0,0 @@ -# -# Synthesis run script generated by Vivado -# - -set TIME_start [clock seconds] -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -set_param project.vivado.isBlockSynthRun true -create_project -in_memory -part xc7z020clg484-3 - -set_param project.singleFileAddWarning.threshold 0 -set_param project.compositeFile.enableAutoGeneration 0 -set_param synth.vivado.isSynthRun true -set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.cache/wt [current_project] -set_property parent.project_path D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.xpr [current_project] -set_property default_lib xil_defaultlib [current_project] -set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/GITEA/UPzynq20_test/IP [current_project] -update_ip_catalog -set_property ip_output_repo d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.cache/ip [current_project] -set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4.xci - -# Mark all dcp files as not used in implementation to prevent them from being -# stitched into the results of this synthesis run. Any black boxes in the -# design are intentionally left as such for best results. Dcp files will be -# stitched into the design at a later time, either when this synthesis run is -# opened, or when it is stitched into a dependent implementation run. -foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { - set_property used_in_implementation false $dcp -} -set_param ips.enableIPCacheLiteLoad 1 - -set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1 -new_name Inverter_3lvl_P0N_3lvl_0_4 -ip [get_ips Inverter_3lvl_P0N_3lvl_0_4]] - -if { $cached_ip eq {} } { -close [open __synthesis_is_running__ w] - -synth_design -top Inverter_3lvl_P0N_3lvl_0_4 -part xc7z020clg484-3 -mode out_of_context - -#--------------------------------------------------------- -# Generate Checkpoint/Stub/Simulation Files For IP Cache -#--------------------------------------------------------- -# disable binary constraint mode for IPCache checkpoints -set_param constraints.enableBinaryConstraints false - -catch { - write_checkpoint -force -noxdef -rename_prefix Inverter_3lvl_P0N_3lvl_0_4_ Inverter_3lvl_P0N_3lvl_0_4.dcp - - set ipCachedFiles {} - write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_4_stub.v - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_0_4_stub.v - - write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_4_stub.vhdl - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_0_4_stub.vhdl - - write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.v - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.v - - write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.vhdl - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.vhdl -set TIME_taken [expr [clock seconds] - $TIME_start] - - config_ip_cache -add -dcp Inverter_3lvl_P0N_3lvl_0_4.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips Inverter_3lvl_P0N_3lvl_0_4] -} - -rename_ref -prefix_all Inverter_3lvl_P0N_3lvl_0_4_ - -# disable binary constraint mode for synth run checkpoints -set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef Inverter_3lvl_P0N_3lvl_0_4.dcp -create_report "Inverter_3lvl_P0N_3lvl_0_4_synth_1_synth_report_utilization_0" "report_utilization -file Inverter_3lvl_P0N_3lvl_0_4_utilization_synth.rpt -pb Inverter_3lvl_P0N_3lvl_0_4_utilization_synth.pb" - -if { [catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/Inverter_3lvl_P0N_3lvl_0_4.dcp D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4.dcp -} _RESULT ] } { - send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." - error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." -} - -if { [catch { - write_verilog -force -mode synth_stub D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode synth_stub D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_verilog -force -mode funcsim D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode funcsim D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - - -} else { - - -if { [catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/Inverter_3lvl_P0N_3lvl_0_4.dcp D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4.dcp -} _RESULT ] } { - send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." - error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/Inverter_3lvl_P0N_3lvl_0_4_stub.v D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/Inverter_3lvl_P0N_3lvl_0_4_stub.vhdl D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.v D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.vhdl D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -}; # end if cached_ip - -if {[file isdir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_0_4]} { - catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_stub.v D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_0_4 - } -} - -if {[file isdir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_0_4]} { - catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_stub.vhdl D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_0_4 - } -} -file delete __synthesis_is_running__ -close [open __synthesis_is_complete__ w] diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/Inverter_3lvl_P0N_3lvl_0_4.vds b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/Inverter_3lvl_P0N_3lvl_0_4.vds deleted file mode 100644 index 72c4476..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/Inverter_3lvl_P0N_3lvl_0_4.vds +++ /dev/null @@ -1,274 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1 (64-bit) -# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 -# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Fri Jun 11 07:49:17 2021 -# Process ID: 13240 -# Current directory: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1 -# Command line: vivado.exe -log Inverter_3lvl_P0N_3lvl_0_4.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_4.tcl -# Log file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/Inverter_3lvl_P0N_3lvl_0_4.vds -# Journal file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1\vivado.jou -#----------------------------------------------------------- -source Inverter_3lvl_P0N_3lvl_0_4.tcl -notrace -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/UPzynq20_test/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/UPzynq20_test/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1'.) -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -Command: synth_design -top Inverter_3lvl_P0N_3lvl_0_4 -part xc7z020clg484-3 -mode out_of_context -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020' -INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 7672 ---------------------------------------------------------------------------------- -Starting Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 575.129 ; gain = 182.785 ---------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_4' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/synth/Inverter_3lvl_P0N_3lvl_0_4.vhd:76] -INFO: [Synth 8-3491] module 'P0N_3lvl' declared at 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:36' bound to instance 'U0' of component 'P0N_3lvl' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/synth/Inverter_3lvl_P0N_3lvl_0_4.vhd:109] -INFO: [Synth 8-638] synthesizing module 'P0N_3lvl' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:61] -WARNING: [Synth 8-6014] Unused sequential element TKin0_prev_reg was removed. [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:154] -WARNING: [Synth 8-6014] Unused sequential element TKin1_prev_reg was removed. [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:155] -INFO: [Synth 8-256] done synthesizing module 'P0N_3lvl' (1#1) [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:61] -INFO: [Synth 8-256] done synthesizing module 'Inverter_3lvl_P0N_3lvl_0_4' (2#1) [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/synth/Inverter_3lvl_P0N_3lvl_0_4.vhd:76] ---------------------------------------------------------------------------------- -Finished Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.793 ; gain = 247.449 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 639.793 ; gain = 247.449 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Loading Part and Timing Information ---------------------------------------------------------------------------------- -Loading part: xc7z020clg484-3 ---------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 639.793 ; gain = 247.449 ---------------------------------------------------------------------------------- -INFO: [Device 21-403] Loading part xc7z020clg484-3 -INFO: [Synth 8-4471] merging register 'minTimeEr_sig_reg' into 'minTimeEr_reg' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:98] -INFO: [Synth 8-802] inferred FSM for state register 'lineconfig_reg' in module 'P0N_3lvl' ---------------------------------------------------------------------------------------------------- - State | New Encoding | Previous Encoding ---------------------------------------------------------------------------------------------------- - closed | 0000001 | 000 - n | 0000010 | 110 - tech_closed | 0000100 | 001 - p | 0001000 | 101 - zero_p | 0010000 | 011 - zero | 0100000 | 010 - zero_n | 1000000 | 100 ---------------------------------------------------------------------------------------------------- -INFO: [Synth 8-3354] encoded FSM with state register 'lineconfig_reg' using encoding 'one-hot' in module 'P0N_3lvl' ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 639.793 ; gain = 247.449 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ -No constraint files found. ---------------------------------------------------------------------------------- -Start RTL Component Statistics ---------------------------------------------------------------------------------- -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 19 -+---Muxes : - 7 Input 7 Bit Muxes := 1 - 2 Input 7 Bit Muxes := 16 - 2 Input 1 Bit Muxes := 47 - 7 Input 1 Bit Muxes := 10 ---------------------------------------------------------------------------------- -Finished RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- -Hierarchical RTL Component report -Module P0N_3lvl -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 19 -+---Muxes : - 7 Input 7 Bit Muxes := 1 - 2 Input 7 Bit Muxes := 16 - 2 Input 1 Bit Muxes := 47 - 7 Input 1 Bit Muxes := 10 ---------------------------------------------------------------------------------- -Finished RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Part Resource Summary ---------------------------------------------------------------------------------- -Part Resources: -DSPs: 220 (col length:60) -BRAMs: 280 (col length: RAMB18 60 RAMB36 30) ---------------------------------------------------------------------------------- -Finished Part Resource Summary ---------------------------------------------------------------------------------- -No constraint files found. ---------------------------------------------------------------------------------- -Start Cross Boundary and Area Optimization ---------------------------------------------------------------------------------- -Warning: Parallel synthesis criteria is not met ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 806.691 ; gain = 414.348 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ -No constraint files found. ---------------------------------------------------------------------------------- -Start Timing Optimization ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 813.012 ; gain = 420.668 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Technology Mapping ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 813.207 ; gain = 420.863 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 813.207 ; gain = 420.863 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Renaming Generated Instances ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 813.207 ; gain = 420.863 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Rebuilding User Hierarchy ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 813.207 ; gain = 420.863 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Ports ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 813.207 ; gain = 420.863 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 813.207 ; gain = 420.863 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Nets ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 813.207 ; gain = 420.863 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Writing Synthesis Report ---------------------------------------------------------------------------------- - -Report BlackBoxes: -+-+--------------+----------+ -| |BlackBox name |Instances | -+-+--------------+----------+ -+-+--------------+----------+ - -Report Cell Usage: -+------+-------+------+ -| |Cell |Count | -+------+-------+------+ -|1 |CARRY4 | 36| -|2 |LUT1 | 4| -|3 |LUT2 | 7| -|4 |LUT3 | 4| -|5 |LUT4 | 108| -|6 |LUT5 | 7| -|7 |LUT6 | 23| -|8 |FDRE | 121| -|9 |FDSE | 1| -+------+-------+------+ - -Report Instance Areas: -+------+---------+---------+------+ -| |Instance |Module |Cells | -+------+---------+---------+------+ -|1 |top | | 311| -|2 | U0 |P0N_3lvl | 311| -+------+---------+---------+------+ ---------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 813.207 ; gain = 420.863 ---------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 813.207 ; gain = 420.863 -Synthesis Optimization Complete : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 813.207 ; gain = 420.863 -INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 36 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 930.840 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -INFO: [Common 17-83] Releasing license: Synthesis -20 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. -synth_design completed successfully -synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 930.840 ; gain = 543.824 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 930.840 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Common 17-1381] The checkpoint 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/Inverter_3lvl_P0N_3lvl_0_4.dcp' has been generated. -write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1388.254 ; gain = 457.414 -WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP Inverter_3lvl_P0N_3lvl_0_4, cache-ID = fdc8b3b6ee8afc45 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1389.293 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/Inverter_3lvl_P0N_3lvl_0_4.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file Inverter_3lvl_P0N_3lvl_0_4_utilization_synth.rpt -pb Inverter_3lvl_P0N_3lvl_0_4_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Fri Jun 11 07:49:58 2021... diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/Inverter_3lvl_P0N_3lvl_0_4_utilization_synth.pb b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/Inverter_3lvl_P0N_3lvl_0_4_utilization_synth.pb deleted file mode 100644 index 8641ec5bc586b56d5651fdc89efd9a3e48bd2460..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 224 zcmd;LGcqu=)H9sKtPxzAo10ivsgR$hP+F3ilUbEml9`_e;%28-Dioy_=a&{Grxxp- z;xw0+;lg?Mr@Xr_zp{NR#K3UCX|FKD1%LNe5xo-@cD<4eKyX)*;X}LIQYjF7 ztvrbQ3nV?9k1BxJXH`MuTr~y;9_Ob(l7XSu2t?imk}=LpjX~_S79jF3h;%w?31UyO o;&2Leb9W92@;Pe<5}0exz|i3E6i6~KymbMQdtE^yt!^MT0GGTwl>h($ diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/Inverter_3lvl_P0N_3lvl_0_4_utilization_synth.rpt b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/Inverter_3lvl_P0N_3lvl_0_4_utilization_synth.rpt deleted file mode 100644 index d8dbcdc..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/Inverter_3lvl_P0N_3lvl_0_4_utilization_synth.rpt +++ /dev/null @@ -1,176 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------ -| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 -| Date : Fri Jun 11 07:49:57 2021 -| Host : STAS-W10 running 64-bit major release (build 9200) -| Command : report_utilization -file Inverter_3lvl_P0N_3lvl_0_4_utilization_synth.rpt -pb Inverter_3lvl_P0N_3lvl_0_4_utilization_synth.pb -| Design : Inverter_3lvl_P0N_3lvl_0_4 -| Device : 7z020clg484-3 -| Design State : Synthesized ------------------------------------------------------------------------------------------------------------------------------------------------ - -Utilization Design Information - -Table of Contents ------------------ -1. Slice Logic -1.1 Summary of Registers by Type -2. Memory -3. DSP -4. IO and GT Specific -5. Clocking -6. Specific Feature -7. Primitives -8. Black Boxes -9. Instantiated Netlists - -1. Slice Logic --------------- - -+-------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 96 | 0 | 53200 | 0.18 | -| LUT as Logic | 96 | 0 | 53200 | 0.18 | -| LUT as Memory | 0 | 0 | 17400 | 0.00 | -| Slice Registers | 122 | 0 | 106400 | 0.11 | -| Register as Flip Flop | 122 | 0 | 106400 | 0.11 | -| Register as Latch | 0 | 0 | 106400 | 0.00 | -| F7 Muxes | 0 | 0 | 26600 | 0.00 | -| F8 Muxes | 0 | 0 | 13300 | 0.00 | -+-------------------------+------+-------+-----------+-------+ -* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. - - -1.1 Summary of Registers by Type --------------------------------- - -+-------+--------------+-------------+--------------+ -| Total | Clock Enable | Synchronous | Asynchronous | -+-------+--------------+-------------+--------------+ -| 0 | _ | - | - | -| 0 | _ | - | Set | -| 0 | _ | - | Reset | -| 0 | _ | Set | - | -| 0 | _ | Reset | - | -| 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 0 | Yes | - | Reset | -| 1 | Yes | Set | - | -| 121 | Yes | Reset | - | -+-------+--------------+-------------+--------------+ - - -2. Memory ---------- - -+----------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------+------+-------+-----------+-------+ -| Block RAM Tile | 0 | 0 | 140 | 0.00 | -| RAMB36/FIFO* | 0 | 0 | 140 | 0.00 | -| RAMB18 | 0 | 0 | 280 | 0.00 | -+----------------+------+-------+-----------+-------+ -* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 - - -3. DSP ------- - -+-----------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------+------+-------+-----------+-------+ -| DSPs | 0 | 0 | 220 | 0.00 | -+-----------+------+-------+-----------+-------+ - - -4. IO and GT Specific ---------------------- - -+-----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 0 | 0 | 200 | 0.00 | -| Bonded IPADs | 0 | 0 | 2 | 0.00 | -| Bonded IOPADs | 0 | 0 | 130 | 0.00 | -| PHY_CONTROL | 0 | 0 | 4 | 0.00 | -| PHASER_REF | 0 | 0 | 4 | 0.00 | -| OUT_FIFO | 0 | 0 | 16 | 0.00 | -| IN_FIFO | 0 | 0 | 16 | 0.00 | -| IDELAYCTRL | 0 | 0 | 4 | 0.00 | -| IBUFDS | 0 | 0 | 192 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 16 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 16 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 200 | 0.00 | -| ILOGIC | 0 | 0 | 200 | 0.00 | -| OLOGIC | 0 | 0 | 200 | 0.00 | -+-----------------------------+------+-------+-----------+-------+ - - -5. Clocking ------------ - -+------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+------------+------+-------+-----------+-------+ -| BUFGCTRL | 0 | 0 | 32 | 0.00 | -| BUFIO | 0 | 0 | 16 | 0.00 | -| MMCME2_ADV | 0 | 0 | 4 | 0.00 | -| PLLE2_ADV | 0 | 0 | 4 | 0.00 | -| BUFMRCE | 0 | 0 | 8 | 0.00 | -| BUFHCE | 0 | 0 | 72 | 0.00 | -| BUFR | 0 | 0 | 16 | 0.00 | -+------------+------+-------+-----------+-------+ - - -6. Specific Feature -------------------- - -+-------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------+------+-------+-----------+-------+ -| BSCANE2 | 0 | 0 | 4 | 0.00 | -| CAPTUREE2 | 0 | 0 | 1 | 0.00 | -| DNA_PORT | 0 | 0 | 1 | 0.00 | -| EFUSE_USR | 0 | 0 | 1 | 0.00 | -| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | -| ICAPE2 | 0 | 0 | 2 | 0.00 | -| STARTUPE2 | 0 | 0 | 1 | 0.00 | -| XADC | 0 | 0 | 1 | 0.00 | -+-------------+------+-------+-----------+-------+ - - -7. Primitives -------------- - -+----------+------+---------------------+ -| Ref Name | Used | Functional Category | -+----------+------+---------------------+ -| FDRE | 121 | Flop & Latch | -| LUT4 | 108 | LUT | -| CARRY4 | 36 | CarryLogic | -| LUT6 | 23 | LUT | -| LUT5 | 7 | LUT | -| LUT2 | 7 | LUT | -| LUT3 | 4 | LUT | -| LUT1 | 4 | LUT | -| FDSE | 1 | Flop & Latch | -+----------+------+---------------------+ - - -8. Black Boxes --------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - -9. Instantiated Netlists ------------------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/__synthesis_is_complete__ b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/__synthesis_is_complete__ deleted file mode 100644 index e69de29..0000000 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/gen_run.xml b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/gen_run.xml deleted file mode 100644 index 53a3081..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/gen_run.xml +++ /dev/null @@ -1,54 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Vivado Synthesis Defaults - - - - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/htr.txt b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/htr.txt deleted file mode 100644 index 370c149..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -REM -REM Vivado(TM) -REM htr.txt: a Vivado-generated description of how-to-repeat the -REM the basic steps of a run. Note that runme.bat/sh needs -REM to be invoked for Vivado to track run status. -REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -REM - -vivado -log Inverter_3lvl_P0N_3lvl_0_4.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_4.tcl diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/project.wdf b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/project.wdf deleted file mode 100644 index 66cddab..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/project.wdf +++ /dev/null @@ -1,44 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:35:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3535323030373536376161373461663938353435666431303963343433336437:506172656e742050412070726f6a656374204944:00 -eof:2238049497 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/rundef.js b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/rundef.js deleted file mode 100644 index 3be9288..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/rundef.js +++ /dev/null @@ -1,36 +0,0 @@ -// -// Vivado(TM) -// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.1/bin;"; -} else { - PathVal = "D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.1/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; -eval( EAInclude(ISEJScriptLib) ); - - -ISEStep( "vivado", - "-log Inverter_3lvl_P0N_3lvl_0_4.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_4.tcl" ); - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/runme.bat b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/runme.bat deleted file mode 100644 index 1760626..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/runme.bat +++ /dev/null @@ -1,10 +0,0 @@ -@echo off - -rem Vivado (TM) -rem runme.bat: a Vivado-generated Script -rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/runme.sh b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/runme.sh deleted file mode 100644 index 8b9a70b..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/runme.sh +++ /dev/null @@ -1,43 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# runme.sh: a Vivado-generated Runs Script for UNIX -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# - -echo "This script was generated under a different operating system." -echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" -exit - -if [ -z "$PATH" ]; then - PATH=D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.1/bin -else - PATH=D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.1/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH= -else - LD_LIBRARY_PATH=:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1' -cd "$HD_PWD" - -HD_LOG=runme.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrap.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -EAStep vivado -log Inverter_3lvl_P0N_3lvl_0_4.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_4.tcl diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/vivado.jou b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/vivado.jou deleted file mode 100644 index 961d4b8..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1 (64-bit) -# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 -# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Fri Jun 11 07:49:17 2021 -# Process ID: 13240 -# Current directory: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1 -# Command line: vivado.exe -log Inverter_3lvl_P0N_3lvl_0_4.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_4.tcl -# Log file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/Inverter_3lvl_P0N_3lvl_0_4.vds -# Journal file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1\vivado.jou -#----------------------------------------------------------- -source Inverter_3lvl_P0N_3lvl_0_4.tcl -notrace diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/vivado.pb b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/vivado.pb deleted file mode 100644 index 58533763edefdf6faae94ab6860903d3177dd7e2..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 30180 zcmeHQ>vJSmb!W6IExy^94G+g&2wdAJ-qm_$`ZZ55AZfL>@X8k2l?|d`Xw9^wwtKpV z?jEhQOgRvW3YeEGR1%6J3Gj(jQap-+4?w=A@*m{`U-;eIkLjN7o|a@OqxFu;<(=v7 zIeqTA=bU@ax#ylkK0!XXq3zh3v!|Q8bakEDTF-KH*RplZAy;OvUXWyE;ZobOwO!5J zniCsET-bY8Z}wpJt-`ym%n+B*+m_nVI<)U-b_~QJeP-Tyro_Np6h*lb!jX#PiB7Zp z{OaA6#q#F*{X_H1lF)KB$1Sg}OP4y@j@mceX7FL_5?(9T1R?s~Z(Sh&U0B_rhgP3< zt$mHUdm8Q8)@xeZeb)P;x_flTvWH{x5Taf6kZx;jtE*An+*b{~Q=*Hw;<^}sVYO9P zw@m&^29r|+1UaPltiI8~bNCfiX^(+dJFls2&2*`2MG+{`Ys-DxW;cA4hH!PqBg^$G zb0AB#E}WDsQlF@qR4m_KT`I4d`*Q5$NFB}5cTHM! ztsadLC^mjt?5Va(58Ac+f+Vz!U8SxRWm@c79gSLjw`J|L+Lq~R2W|?Avq}*R4+JkB zT=WRkB#+&30g;JW6c2{!1yN~4P~F0>Wl41v+Zgwc+k+ne2&I> zbw^X(zO8ZQqM$<=oZr#*@dUrbUnC3lg*h;O*D|HQA&=Z)a}07g$stG|B$xcbCvQRz z)QYlFi=z0w0ui3K+~c7H{UVFPDWcSfGR02{WMhv{hDbX?W+ zMS@y86vEK6Os1&WTE$i>S#C%H#Xm&e9Vo>lKGHV}#63&$I(uv!WwoQ$$^jaTY$>Qb zMrPz{`t?mA<@)%6J(!I11i2szjZDs&t3zcqm|6{Om#-aN_Qn(J%?WWrmH<`7Ofn<| z=wD~ZjZG8QTZcN@m-~L!99@>eLQY$G+BgamBgWIwsuw{41 zM)9=&(lH(W=4NA3C0nU-}b#cJ;~icNmbUWs$f zC&&VKfOyD;IUDQD$%V7XJRlwcG7&K8^2y8LhRKiZ)A6xMfE$_A7)el297P`MJ@ z#+|%5|H~2c_n!;oYeVyQdVKdX4+QF*7 zOXJYNu|c09)~5z~^1^mIKHCbRUR;393ii?cEiq{1ST zjW~38kqo`H{(*L4)M|9q?DaW5l-2^&7%o0opvJ!Cp_V>y=?KuPrvp7CD+3qeuGCHp zJw};y=%R20=#v+cm*Z?xBTt9%rMQqhNRmH!vVJa3)^jh08sG*s=?q0JhTqjE#i)-vwJ${Sg@{(AmRe^t!t5n9r$$b}u=EJS#$_ku=>!Hut$7;vYr=bU!PQ?+ycWN14UUV4WzX1nY1y zJ=3}_R7=%{ILx3?M5QDv^>hk`nbwn+fN8J}Tk_$4>)D1F-$B8;TXEfjls`{#`Z+t% zuz0!%oTGJh@-z=rm7&f`Q1qB8 zOU|;hpt2-^?W0CiR=p~xBRjRTjwPWE6%Mzv zjr4ThpBh+^;LT^^WNeUmkBqkr6-StvPfV9Iq?v1UO4z9Jle-GsjT83cI}%XYj28 z>4yp+s!FrXze-w|EvukG{XsSVZpQWGv*ht0CvJI9Yrh^yb8Ze$KMv;$WYzb;B92%v zmBFRp-=Qryyb?TH%=6xoFZPqz2dk(7;%$2d{~xT_wq+wz&W|_a6P8;S8UBNtnu9CuV`><=U$xmF;@5)@% z*O8~`Oc(UruuIOtq@=aP2|E=9W(9?t{Syf1uEpKA3VG5Kg%?oo0*A?W>2lw3tu94j zMO)wQqx|Sp7;=T-*CPwV4-4e$!-XN6v{P}Iv^XTorDU!Q2zO3p0oHYnKKR9mETGiI zSBJ8Y;^{HEP6c7of{ z!l}UAU}sW2jB^q59L^*(>~06xP{fx|y(A1O<(~3QLOWgD-VQX6_+gFV2=SLS!=Rgv zx~pXoKTMhMBGw@gM65@mkipk<;#&DzZ(_!u|=0`U-N1{;il6NGh_ z7dJLOr+BekxtbA|9tTI_QQ*Pt&ATj6>n0USAm!ytNaYA1lBgm4(dljBnf;V_5{ zjwsYmfDb=ROBsC_#FLMUADiWH7(@<7l23q79lyr!Z{6Hj@!^P)cmg>5bTor=Cx8PA z9Usog_&Ga587MQ#jxOYD+x580u9J_BAT-=R3O{8CTbO&2gz3%tP}9{hECm)9+FYiK3z1f^nm0U&{*)EzctpQQpn=EKi@-}BA_Is9;wgo4`qXpmFN zkv_lTY8XUe6<3GvjpqH+4J_-di9uGyRq+hB{zEDJFV7(g@%=%8{9OjV?6|3+p@`i? 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All Rights Reserved. -// - -// GLOBAL VARIABLES -var ISEShell = new ActiveXObject( "WScript.Shell" ); -var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); -var ISERunDir = ""; -var ISELogFile = "runme.log"; -var ISELogFileStr = null; -var ISELogEcho = true; -var ISEOldVersionWSH = false; - - - -// BOOTSTRAP -ISEInit(); - - - -// -// ISE FUNCTIONS -// -function ISEInit() { - - // 1. RUN DIR setup - var ISEScrFP = WScript.ScriptFullName; - var ISEScrN = WScript.ScriptName; - ISERunDir = - ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); - - // 2. LOG file setup - ISELogFileStr = ISEOpenFile( ISELogFile ); - - // 3. LOG echo? - var ISEScriptArgs = WScript.Arguments; - for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var wbemFlagReturnImmediately = 0x10; - var wbemFlagForwardOnly = 0x20; - var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); - var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); - var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); - var NOC = 0; - var NOLP = 0; - var TPM = 0; - - var cpuInfos = new Enumerator(processor); - for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { - var cpuInfo = cpuInfos.item(); - NOC += cpuInfo.NumberOfCores; - NOLP += cpuInfo.NumberOfLogicalProcessors; - } - var csInfos = new Enumerator(computerSystem); - for(;!csInfos.atEnd(); csInfos.moveNext()) { - var csInfo = csInfos.item(); - TPM += csInfo.TotalPhysicalMemory; - } - - var ISEHOSTCORE = NOLP - var ISEMEMTOTAL = TPM - - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/ISEWrap.sh b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/ISEWrap.sh deleted file mode 100644 index f679f2e..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/ISEWrap.sh +++ /dev/null @@ -1,67 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -# - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! -if [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi -ISE_USER=$USER - -ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) -ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) - -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 ] -then - /bin/touch .$ISE_STEP.end.rst -else - /bin/touch .$ISE_STEP.error.rst -fi - -exit $RETVAL - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/Inverter_3lvl_P0N_3lvl_0_5.tcl b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/Inverter_3lvl_P0N_3lvl_0_5.tcl deleted file mode 100644 index f174d93..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/Inverter_3lvl_P0N_3lvl_0_5.tcl +++ /dev/null @@ -1,167 +0,0 @@ -# -# Synthesis run script generated by Vivado -# - -set TIME_start [clock seconds] -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -set_param project.vivado.isBlockSynthRun true -create_project -in_memory -part xc7z020clg484-3 - -set_param project.singleFileAddWarning.threshold 0 -set_param project.compositeFile.enableAutoGeneration 0 -set_param synth.vivado.isSynthRun true -set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.cache/wt [current_project] -set_property parent.project_path D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.xpr [current_project] -set_property default_lib xil_defaultlib [current_project] -set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/GITEA/UPzynq20_test/IP [current_project] -update_ip_catalog -set_property ip_output_repo d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.cache/ip [current_project] -set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5.xci - -# Mark all dcp files as not used in implementation to prevent them from being -# stitched into the results of this synthesis run. Any black boxes in the -# design are intentionally left as such for best results. Dcp files will be -# stitched into the design at a later time, either when this synthesis run is -# opened, or when it is stitched into a dependent implementation run. -foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { - set_property used_in_implementation false $dcp -} -set_param ips.enableIPCacheLiteLoad 1 - -set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1 -new_name Inverter_3lvl_P0N_3lvl_0_5 -ip [get_ips Inverter_3lvl_P0N_3lvl_0_5]] - -if { $cached_ip eq {} } { -close [open __synthesis_is_running__ w] - -synth_design -top Inverter_3lvl_P0N_3lvl_0_5 -part xc7z020clg484-3 -mode out_of_context - -#--------------------------------------------------------- -# Generate Checkpoint/Stub/Simulation Files For IP Cache -#--------------------------------------------------------- -# disable binary constraint mode for IPCache checkpoints -set_param constraints.enableBinaryConstraints false - -catch { - write_checkpoint -force -noxdef -rename_prefix Inverter_3lvl_P0N_3lvl_0_5_ Inverter_3lvl_P0N_3lvl_0_5.dcp - - set ipCachedFiles {} - write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_5_stub.v - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_0_5_stub.v - - write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_5_stub.vhdl - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_0_5_stub.vhdl - - write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_5_sim_netlist.v - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_0_5_sim_netlist.v - - write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_5_sim_netlist.vhdl - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_0_5_sim_netlist.vhdl -set TIME_taken [expr [clock seconds] - $TIME_start] - - config_ip_cache -add -dcp Inverter_3lvl_P0N_3lvl_0_5.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips Inverter_3lvl_P0N_3lvl_0_5] -} - -rename_ref -prefix_all Inverter_3lvl_P0N_3lvl_0_5_ - -# disable binary constraint mode for synth run checkpoints -set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef Inverter_3lvl_P0N_3lvl_0_5.dcp -create_report "Inverter_3lvl_P0N_3lvl_0_5_synth_1_synth_report_utilization_0" "report_utilization -file Inverter_3lvl_P0N_3lvl_0_5_utilization_synth.rpt -pb Inverter_3lvl_P0N_3lvl_0_5_utilization_synth.pb" - -if { [catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/Inverter_3lvl_P0N_3lvl_0_5.dcp D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5.dcp -} _RESULT ] } { - send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." - error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." -} - -if { [catch { - write_verilog -force -mode synth_stub D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode synth_stub D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_verilog -force -mode funcsim D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode funcsim D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - - -} else { - - -if { [catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/Inverter_3lvl_P0N_3lvl_0_5.dcp D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5.dcp -} _RESULT ] } { - send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." - error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/Inverter_3lvl_P0N_3lvl_0_5_stub.v D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/Inverter_3lvl_P0N_3lvl_0_5_stub.vhdl D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/Inverter_3lvl_P0N_3lvl_0_5_sim_netlist.v D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/Inverter_3lvl_P0N_3lvl_0_5_sim_netlist.vhdl D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -}; # end if cached_ip - -if {[file isdir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_0_5]} { - catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5_stub.v D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_0_5 - } -} - -if {[file isdir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_0_5]} { - catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5_stub.vhdl D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_0_5 - } -} -file delete __synthesis_is_running__ -close [open __synthesis_is_complete__ w] diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/Inverter_3lvl_P0N_3lvl_0_5.vds b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/Inverter_3lvl_P0N_3lvl_0_5.vds deleted file mode 100644 index 8301604..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/Inverter_3lvl_P0N_3lvl_0_5.vds +++ /dev/null @@ -1,18 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1 (64-bit) -# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 -# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Fri Jun 11 07:50:12 2021 -# Process ID: 11572 -# Current directory: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1 -# Command line: vivado.exe -log Inverter_3lvl_P0N_3lvl_0_5.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_5.tcl -# Log file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/Inverter_3lvl_P0N_3lvl_0_5.vds -# Journal file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1\vivado.jou -#----------------------------------------------------------- -source Inverter_3lvl_P0N_3lvl_0_5.tcl -notrace -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/UPzynq20_test/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/UPzynq20_test/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1'.) -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP Inverter_3lvl_P0N_3lvl_0_5, cache-ID = fdc8b3b6ee8afc45. -INFO: [Common 17-206] Exiting Vivado at Fri Jun 11 07:50:17 2021... diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/__synthesis_is_complete__ b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/__synthesis_is_complete__ deleted file mode 100644 index e69de29..0000000 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/gen_run.xml b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/gen_run.xml deleted file mode 100644 index e857a73..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/gen_run.xml +++ /dev/null @@ -1,54 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Vivado Synthesis Defaults - - - - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/htr.txt b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/htr.txt deleted file mode 100644 index 4d253bb..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -REM -REM Vivado(TM) -REM htr.txt: a Vivado-generated description of how-to-repeat the -REM the basic steps of a run. Note that runme.bat/sh needs -REM to be invoked for Vivado to track run status. -REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -REM - -vivado -log Inverter_3lvl_P0N_3lvl_0_5.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_5.tcl diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/rundef.js b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/rundef.js deleted file mode 100644 index ca25bd8..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/rundef.js +++ /dev/null @@ -1,36 +0,0 @@ -// -// Vivado(TM) -// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.1/bin;"; -} else { - PathVal = "D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.1/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; -eval( EAInclude(ISEJScriptLib) ); - - -ISEStep( "vivado", - "-log Inverter_3lvl_P0N_3lvl_0_5.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_5.tcl" ); - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/runme.bat b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/runme.bat deleted file mode 100644 index 1760626..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/runme.bat +++ /dev/null @@ -1,10 +0,0 @@ -@echo off - -rem Vivado (TM) -rem runme.bat: a Vivado-generated Script -rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/runme.log b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/runme.log deleted file mode 100644 index a1cc222..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/runme.log +++ /dev/null @@ -1,17 +0,0 @@ - -*** Running vivado - with args -log Inverter_3lvl_P0N_3lvl_0_5.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_5.tcl - - -****** Vivado v2019.1 (64-bit) - **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 - **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source Inverter_3lvl_P0N_3lvl_0_5.tcl -notrace -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/UPzynq20_test/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/UPzynq20_test/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1'.) -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP Inverter_3lvl_P0N_3lvl_0_5, cache-ID = fdc8b3b6ee8afc45. -INFO: [Common 17-206] Exiting Vivado at Fri Jun 11 07:50:17 2021... diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/runme.sh b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/runme.sh deleted file mode 100644 index c725804..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/runme.sh +++ /dev/null @@ -1,43 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# runme.sh: a Vivado-generated Runs Script for UNIX -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# - -echo "This script was generated under a different operating system." -echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" -exit - -if [ -z "$PATH" ]; then - PATH=D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.1/bin -else - PATH=D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.1/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH= -else - LD_LIBRARY_PATH=:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1' -cd "$HD_PWD" - -HD_LOG=runme.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrap.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -EAStep vivado -log Inverter_3lvl_P0N_3lvl_0_5.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_5.tcl diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/vivado.jou b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/vivado.jou deleted file mode 100644 index 7fe01cd..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1 (64-bit) -# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 -# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Fri Jun 11 07:50:12 2021 -# Process ID: 11572 -# Current directory: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1 -# Command line: vivado.exe -log Inverter_3lvl_P0N_3lvl_0_5.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_5.tcl -# Log file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/Inverter_3lvl_P0N_3lvl_0_5.vds -# Journal file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1\vivado.jou -#----------------------------------------------------------- -source Inverter_3lvl_P0N_3lvl_0_5.tcl -notrace diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/vivado.pb b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/vivado.pb deleted file mode 100644 index 4f9a0f55d305d29436060919a0fea0da37314546..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1048 zcmbVLO>fgc5N#-Nr9Ge=I6yftLR5t+vAyf&qd_1Q8jw+iqKYEai?#J`nysAOu)7Wk z;=q*~zlIzCjdff|qL2$0%QK#N^XAPndVwCC@qy-MDC8Byeb9WYjIc@zZcwedyG^3Q zgPl}qe#Pa5hmRUAG29wgr_~>ot=cVQ5u7T@ID_19y#g_V{XMhq7cjRmj+%dQNCVwx z-QZ39zIPm)_rJ{KClV%>8ym!Zvcvd*=9%sOdAZneV{tnSm*;-pM!zcY0A?zOk(zL@ zLk?rDu6b(fWkBr^21+k>Dha`e&ft=#YQ#av3C#ra;n-!Ybqi!FrB*08?<_Fqia0@L z@LA;|T3rmL*(!mR6KH6PTZ$+GSQsgnJ4OrT_j4oT8 zcjzEJY_3<$jeOXNI?L3*RnXnuRM>+2o&jnLM*f`BHVIn?o-^u5NwSN)QlWKRQb+e* pYXNU_2^d4z?l!|NZUYI)zYgf(cEcerlemLWPck@je}!hX%5QkuJQx4~ diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/.Vivado_Synthesis.queue.rst b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/.Vivado_Synthesis.queue.rst deleted file mode 100644 index e69de29..0000000 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/.vivado.begin.rst b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/.vivado.begin.rst deleted file mode 100644 index d41f8b8..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/.vivado.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/.vivado.end.rst b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/.vivado.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/ISEWrap.js b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/ISEWrap.js deleted file mode 100644 index 97a2ecb..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/ISEWrap.js +++ /dev/null @@ -1,270 +0,0 @@ -// -// Vivado(TM) -// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 -// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. -// - -// GLOBAL VARIABLES -var ISEShell = new ActiveXObject( "WScript.Shell" ); -var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); -var ISERunDir = ""; -var ISELogFile = "runme.log"; -var ISELogFileStr = null; -var ISELogEcho = true; -var ISEOldVersionWSH = false; - - - -// BOOTSTRAP -ISEInit(); - - - -// -// ISE FUNCTIONS -// -function ISEInit() { - - // 1. RUN DIR setup - var ISEScrFP = WScript.ScriptFullName; - var ISEScrN = WScript.ScriptName; - ISERunDir = - ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); - - // 2. LOG file setup - ISELogFileStr = ISEOpenFile( ISELogFile ); - - // 3. LOG echo? - var ISEScriptArgs = WScript.Arguments; - for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var wbemFlagReturnImmediately = 0x10; - var wbemFlagForwardOnly = 0x20; - var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); - var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); - var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); - var NOC = 0; - var NOLP = 0; - var TPM = 0; - - var cpuInfos = new Enumerator(processor); - for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { - var cpuInfo = cpuInfos.item(); - NOC += cpuInfo.NumberOfCores; - NOLP += cpuInfo.NumberOfLogicalProcessors; - } - var csInfos = new Enumerator(computerSystem); - for(;!csInfos.atEnd(); csInfos.moveNext()) { - var csInfo = csInfos.item(); - TPM += csInfo.TotalPhysicalMemory; - } - - var ISEHOSTCORE = NOLP - var ISEMEMTOTAL = TPM - - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/ISEWrap.sh b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/ISEWrap.sh deleted file mode 100644 index f679f2e..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/ISEWrap.sh +++ /dev/null @@ -1,67 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -# - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! -if [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi -ISE_USER=$USER - -ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) -ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) - -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 ] -then - /bin/touch .$ISE_STEP.end.rst -else - /bin/touch .$ISE_STEP.error.rst -fi - -exit $RETVAL - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/Inverter_3lvl_P0N_3lvl_1_0.tcl b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/Inverter_3lvl_P0N_3lvl_1_0.tcl deleted file mode 100644 index 620f42e..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/Inverter_3lvl_P0N_3lvl_1_0.tcl +++ /dev/null @@ -1,167 +0,0 @@ -# -# Synthesis run script generated by Vivado -# - -set TIME_start [clock seconds] -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -set_param project.vivado.isBlockSynthRun true -create_project -in_memory -part xc7z020clg484-3 - -set_param project.singleFileAddWarning.threshold 0 -set_param project.compositeFile.enableAutoGeneration 0 -set_param synth.vivado.isSynthRun true -set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.cache/wt [current_project] -set_property parent.project_path D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.xpr [current_project] -set_property default_lib xil_defaultlib [current_project] -set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/GITEA/UPzynq20_test/IP [current_project] -update_ip_catalog -set_property ip_output_repo d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.cache/ip [current_project] -set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0.xci - -# Mark all dcp files as not used in implementation to prevent them from being -# stitched into the results of this synthesis run. Any black boxes in the -# design are intentionally left as such for best results. Dcp files will be -# stitched into the design at a later time, either when this synthesis run is -# opened, or when it is stitched into a dependent implementation run. -foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { - set_property used_in_implementation false $dcp -} -set_param ips.enableIPCacheLiteLoad 1 - -set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1 -new_name Inverter_3lvl_P0N_3lvl_1_0 -ip [get_ips Inverter_3lvl_P0N_3lvl_1_0]] - -if { $cached_ip eq {} } { -close [open __synthesis_is_running__ w] - -synth_design -top Inverter_3lvl_P0N_3lvl_1_0 -part xc7z020clg484-3 -mode out_of_context - -#--------------------------------------------------------- -# Generate Checkpoint/Stub/Simulation Files For IP Cache -#--------------------------------------------------------- -# disable binary constraint mode for IPCache checkpoints -set_param constraints.enableBinaryConstraints false - -catch { - write_checkpoint -force -noxdef -rename_prefix Inverter_3lvl_P0N_3lvl_1_0_ Inverter_3lvl_P0N_3lvl_1_0.dcp - - set ipCachedFiles {} - write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_1_0_stub.v - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_1_0_stub.v - - write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_1_0_stub.vhdl - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_1_0_stub.vhdl - - write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_1_0_sim_netlist.v - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_1_0_sim_netlist.v - - write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_1_0_sim_netlist.vhdl - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_1_0_sim_netlist.vhdl -set TIME_taken [expr [clock seconds] - $TIME_start] - - config_ip_cache -add -dcp Inverter_3lvl_P0N_3lvl_1_0.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips Inverter_3lvl_P0N_3lvl_1_0] -} - -rename_ref -prefix_all Inverter_3lvl_P0N_3lvl_1_0_ - -# disable binary constraint mode for synth run checkpoints -set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef Inverter_3lvl_P0N_3lvl_1_0.dcp -create_report "Inverter_3lvl_P0N_3lvl_1_0_synth_1_synth_report_utilization_0" "report_utilization -file Inverter_3lvl_P0N_3lvl_1_0_utilization_synth.rpt -pb Inverter_3lvl_P0N_3lvl_1_0_utilization_synth.pb" - -if { [catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/Inverter_3lvl_P0N_3lvl_1_0.dcp D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0.dcp -} _RESULT ] } { - send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." - error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." -} - -if { [catch { - write_verilog -force -mode synth_stub D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode synth_stub D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_verilog -force -mode funcsim D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode funcsim D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - - -} else { - - -if { [catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/Inverter_3lvl_P0N_3lvl_1_0.dcp D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0.dcp -} _RESULT ] } { - send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." - error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/Inverter_3lvl_P0N_3lvl_1_0_stub.v D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/Inverter_3lvl_P0N_3lvl_1_0_stub.vhdl D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/Inverter_3lvl_P0N_3lvl_1_0_sim_netlist.v D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/Inverter_3lvl_P0N_3lvl_1_0_sim_netlist.vhdl D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -}; # end if cached_ip - -if {[file isdir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_1_0]} { - catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0_stub.v D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_1_0 - } -} - -if {[file isdir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_1_0]} { - catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0_stub.vhdl D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_1_0 - } -} -file delete __synthesis_is_running__ -close [open __synthesis_is_complete__ w] diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/Inverter_3lvl_P0N_3lvl_1_0.vds b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/Inverter_3lvl_P0N_3lvl_1_0.vds deleted file mode 100644 index 9bc30f0..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/Inverter_3lvl_P0N_3lvl_1_0.vds +++ /dev/null @@ -1,18 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1 (64-bit) -# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 -# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Fri Jun 11 07:50:03 2021 -# Process ID: 11260 -# Current directory: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1 -# Command line: vivado.exe -log Inverter_3lvl_P0N_3lvl_1_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_1_0.tcl -# Log file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/Inverter_3lvl_P0N_3lvl_1_0.vds -# Journal file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1\vivado.jou -#----------------------------------------------------------- -source Inverter_3lvl_P0N_3lvl_1_0.tcl -notrace -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/UPzynq20_test/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/UPzynq20_test/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1'.) -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP Inverter_3lvl_P0N_3lvl_1_0, cache-ID = fdc8b3b6ee8afc45. -INFO: [Common 17-206] Exiting Vivado at Fri Jun 11 07:50:09 2021... diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/__synthesis_is_complete__ b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/__synthesis_is_complete__ deleted file mode 100644 index e69de29..0000000 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/gen_run.xml b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/gen_run.xml deleted file mode 100644 index f9ce13f..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/gen_run.xml +++ /dev/null @@ -1,54 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Vivado Synthesis Defaults - - - - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/htr.txt b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/htr.txt deleted file mode 100644 index 7a79c2d..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -REM -REM Vivado(TM) -REM htr.txt: a Vivado-generated description of how-to-repeat the -REM the basic steps of a run. Note that runme.bat/sh needs -REM to be invoked for Vivado to track run status. -REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -REM - -vivado -log Inverter_3lvl_P0N_3lvl_1_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_1_0.tcl diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/rundef.js b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/rundef.js deleted file mode 100644 index 90df737..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/rundef.js +++ /dev/null @@ -1,36 +0,0 @@ -// -// Vivado(TM) -// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.1/bin;"; -} else { - PathVal = "D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.1/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; -eval( EAInclude(ISEJScriptLib) ); - - -ISEStep( "vivado", - "-log Inverter_3lvl_P0N_3lvl_1_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_1_0.tcl" ); - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/runme.bat b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/runme.bat deleted file mode 100644 index 1760626..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/runme.bat +++ /dev/null @@ -1,10 +0,0 @@ -@echo off - -rem Vivado (TM) -rem runme.bat: a Vivado-generated Script -rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/runme.log b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/runme.log deleted file mode 100644 index 4953ac3..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/runme.log +++ /dev/null @@ -1,17 +0,0 @@ - -*** Running vivado - with args -log Inverter_3lvl_P0N_3lvl_1_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_1_0.tcl - - -****** Vivado v2019.1 (64-bit) - **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 - **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source Inverter_3lvl_P0N_3lvl_1_0.tcl -notrace -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/UPzynq20_test/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/UPzynq20_test/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1'.) -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP Inverter_3lvl_P0N_3lvl_1_0, cache-ID = fdc8b3b6ee8afc45. -INFO: [Common 17-206] Exiting Vivado at Fri Jun 11 07:50:09 2021... diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/runme.sh b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/runme.sh deleted file mode 100644 index 29e35db..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/runme.sh +++ /dev/null @@ -1,43 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# runme.sh: a Vivado-generated Runs Script for UNIX -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# - -echo "This script was generated under a different operating system." -echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" -exit - -if [ -z "$PATH" ]; then - PATH=D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.1/bin -else - PATH=D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.1/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH= -else - LD_LIBRARY_PATH=:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1' -cd "$HD_PWD" - -HD_LOG=runme.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrap.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -EAStep vivado -log Inverter_3lvl_P0N_3lvl_1_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_1_0.tcl diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/vivado.jou b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/vivado.jou deleted file mode 100644 index f25e468..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1 (64-bit) -# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 -# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Fri Jun 11 07:50:03 2021 -# Process ID: 11260 -# Current directory: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1 -# Command line: vivado.exe -log Inverter_3lvl_P0N_3lvl_1_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_1_0.tcl -# Log file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/Inverter_3lvl_P0N_3lvl_1_0.vds -# Journal file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1\vivado.jou -#----------------------------------------------------------- -source Inverter_3lvl_P0N_3lvl_1_0.tcl -notrace diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/vivado.pb b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/vivado.pb deleted file mode 100644 index 15b8bea4fb705e85348b2b8157bae21978aec33e..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1048 zcmbVL!EVz)5N#-Rr9Ge=I6yftLPUkCvAydgO@lxxG$5l2MHNM;7i;6)BwIPVVRs!8 z#DOa}zJ?qB#yTz}QOSjiX@BBdpSb8&uud+a^)t zU^i8o54pVb@NwNGMq87e+0Kv3R`nLL2+kB`oI!55UW1s!e$DLr1@q%}d1gC*UM_dtSbP+Qt8>3^qhFPH0CSbYSWP+D z5r>IZS3I?cWkBr+21+k?Dha`u&Y{m!HRd4XlxBkYaN;u7x&<v|7FluQaCL89H2uG`K_*p^EE==L!l%^wR zMrY;42HZHknR^b)i@JQx9F|q}_!OSIuyiOPZM - - - - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/.vivado.end.rst b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/.vivado.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/ISEWrap.js b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/ISEWrap.js deleted file mode 100644 index 97a2ecb..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/ISEWrap.js +++ /dev/null @@ -1,270 +0,0 @@ -// -// Vivado(TM) -// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 -// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. -// - -// GLOBAL VARIABLES -var ISEShell = new ActiveXObject( "WScript.Shell" ); -var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); -var ISERunDir = ""; -var ISELogFile = "runme.log"; -var ISELogFileStr = null; -var ISELogEcho = true; -var ISEOldVersionWSH = false; - - - -// BOOTSTRAP -ISEInit(); - - - -// -// ISE FUNCTIONS -// -function ISEInit() { - - // 1. RUN DIR setup - var ISEScrFP = WScript.ScriptFullName; - var ISEScrN = WScript.ScriptName; - ISERunDir = - ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); - - // 2. LOG file setup - ISELogFileStr = ISEOpenFile( ISELogFile ); - - // 3. LOG echo? - var ISEScriptArgs = WScript.Arguments; - for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var wbemFlagReturnImmediately = 0x10; - var wbemFlagForwardOnly = 0x20; - var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); - var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); - var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); - var NOC = 0; - var NOLP = 0; - var TPM = 0; - - var cpuInfos = new Enumerator(processor); - for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { - var cpuInfo = cpuInfos.item(); - NOC += cpuInfo.NumberOfCores; - NOLP += cpuInfo.NumberOfLogicalProcessors; - } - var csInfos = new Enumerator(computerSystem); - for(;!csInfos.atEnd(); csInfos.moveNext()) { - var csInfo = csInfos.item(); - TPM += csInfo.TotalPhysicalMemory; - } - - var ISEHOSTCORE = NOLP - var ISEMEMTOTAL = TPM - - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/ISEWrap.sh b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/ISEWrap.sh deleted file mode 100644 index f679f2e..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/ISEWrap.sh +++ /dev/null @@ -1,67 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -# - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! -if [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi -ISE_USER=$USER - -ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) -ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) - -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 ] -then - /bin/touch .$ISE_STEP.end.rst -else - /bin/touch .$ISE_STEP.error.rst -fi - -exit $RETVAL - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/Inverter_3lvl_P0N_3lvl_1_1.tcl b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/Inverter_3lvl_P0N_3lvl_1_1.tcl deleted file mode 100644 index 1c0e023..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/Inverter_3lvl_P0N_3lvl_1_1.tcl +++ /dev/null @@ -1,167 +0,0 @@ -# -# Synthesis run script generated by Vivado -# - -set TIME_start [clock seconds] -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -set_param project.vivado.isBlockSynthRun true -create_project -in_memory -part xc7z020clg484-3 - -set_param project.singleFileAddWarning.threshold 0 -set_param project.compositeFile.enableAutoGeneration 0 -set_param synth.vivado.isSynthRun true -set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.cache/wt [current_project] -set_property parent.project_path D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.xpr [current_project] -set_property default_lib xil_defaultlib [current_project] -set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/GITEA/UPzynq20_test/IP [current_project] -update_ip_catalog -set_property ip_output_repo d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.cache/ip [current_project] -set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1.xci - -# Mark all dcp files as not used in implementation to prevent them from being -# stitched into the results of this synthesis run. Any black boxes in the -# design are intentionally left as such for best results. Dcp files will be -# stitched into the design at a later time, either when this synthesis run is -# opened, or when it is stitched into a dependent implementation run. -foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { - set_property used_in_implementation false $dcp -} -set_param ips.enableIPCacheLiteLoad 1 - -set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1 -new_name Inverter_3lvl_P0N_3lvl_1_1 -ip [get_ips Inverter_3lvl_P0N_3lvl_1_1]] - -if { $cached_ip eq {} } { -close [open __synthesis_is_running__ w] - -synth_design -top Inverter_3lvl_P0N_3lvl_1_1 -part xc7z020clg484-3 -mode out_of_context - -#--------------------------------------------------------- -# Generate Checkpoint/Stub/Simulation Files For IP Cache -#--------------------------------------------------------- -# disable binary constraint mode for IPCache checkpoints -set_param constraints.enableBinaryConstraints false - -catch { - write_checkpoint -force -noxdef -rename_prefix Inverter_3lvl_P0N_3lvl_1_1_ Inverter_3lvl_P0N_3lvl_1_1.dcp - - set ipCachedFiles {} - write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_1_1_stub.v - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_1_1_stub.v - - write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_1_1_stub.vhdl - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_1_1_stub.vhdl - - write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_1_1_sim_netlist.v - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_1_1_sim_netlist.v - - write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_1_1_sim_netlist.vhdl - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_1_1_sim_netlist.vhdl -set TIME_taken [expr [clock seconds] - $TIME_start] - - config_ip_cache -add -dcp Inverter_3lvl_P0N_3lvl_1_1.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips Inverter_3lvl_P0N_3lvl_1_1] -} - -rename_ref -prefix_all Inverter_3lvl_P0N_3lvl_1_1_ - -# disable binary constraint mode for synth run checkpoints -set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef Inverter_3lvl_P0N_3lvl_1_1.dcp -create_report "Inverter_3lvl_P0N_3lvl_1_1_synth_1_synth_report_utilization_0" "report_utilization -file Inverter_3lvl_P0N_3lvl_1_1_utilization_synth.rpt -pb Inverter_3lvl_P0N_3lvl_1_1_utilization_synth.pb" - -if { [catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/Inverter_3lvl_P0N_3lvl_1_1.dcp D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1.dcp -} _RESULT ] } { - send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." - error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." -} - -if { [catch { - write_verilog -force -mode synth_stub D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode synth_stub D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_verilog -force -mode funcsim D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode funcsim D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - - -} else { - - -if { [catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/Inverter_3lvl_P0N_3lvl_1_1.dcp D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1.dcp -} _RESULT ] } { - send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." - error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/Inverter_3lvl_P0N_3lvl_1_1_stub.v D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/Inverter_3lvl_P0N_3lvl_1_1_stub.vhdl D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/Inverter_3lvl_P0N_3lvl_1_1_sim_netlist.v D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/Inverter_3lvl_P0N_3lvl_1_1_sim_netlist.vhdl D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -}; # end if cached_ip - -if {[file isdir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_1_1]} { - catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1_stub.v D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_1_1 - } -} - -if {[file isdir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_1_1]} { - catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1_stub.vhdl D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_1_1 - } -} -file delete __synthesis_is_running__ -close [open __synthesis_is_complete__ w] diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/Inverter_3lvl_P0N_3lvl_1_1.vds b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/Inverter_3lvl_P0N_3lvl_1_1.vds deleted file mode 100644 index a369e69..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/Inverter_3lvl_P0N_3lvl_1_1.vds +++ /dev/null @@ -1,18 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1 (64-bit) -# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 -# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Fri Jun 11 07:50:03 2021 -# Process ID: 12956 -# Current directory: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1 -# Command line: vivado.exe -log Inverter_3lvl_P0N_3lvl_1_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_1_1.tcl -# Log file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/Inverter_3lvl_P0N_3lvl_1_1.vds -# Journal file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1\vivado.jou -#----------------------------------------------------------- -source Inverter_3lvl_P0N_3lvl_1_1.tcl -notrace -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/UPzynq20_test/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/UPzynq20_test/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1'.) -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP Inverter_3lvl_P0N_3lvl_1_1, cache-ID = fdc8b3b6ee8afc45. -INFO: [Common 17-206] Exiting Vivado at Fri Jun 11 07:50:09 2021... diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/__synthesis_is_complete__ b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/__synthesis_is_complete__ deleted file mode 100644 index e69de29..0000000 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/gen_run.xml b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/gen_run.xml deleted file mode 100644 index 8f6c6c9..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/gen_run.xml +++ /dev/null @@ -1,54 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Vivado Synthesis Defaults - - - - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/htr.txt b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/htr.txt deleted file mode 100644 index f6de376..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -REM -REM Vivado(TM) -REM htr.txt: a Vivado-generated description of how-to-repeat the -REM the basic steps of a run. Note that runme.bat/sh needs -REM to be invoked for Vivado to track run status. -REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -REM - -vivado -log Inverter_3lvl_P0N_3lvl_1_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_1_1.tcl diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/rundef.js b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/rundef.js deleted file mode 100644 index 151c7d5..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/rundef.js +++ /dev/null @@ -1,36 +0,0 @@ -// -// Vivado(TM) -// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.1/bin;"; -} else { - PathVal = "D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.1/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; -eval( EAInclude(ISEJScriptLib) ); - - -ISEStep( "vivado", - "-log Inverter_3lvl_P0N_3lvl_1_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_1_1.tcl" ); - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/runme.bat b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/runme.bat deleted file mode 100644 index 1760626..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/runme.bat +++ /dev/null @@ -1,10 +0,0 @@ -@echo off - -rem Vivado (TM) -rem runme.bat: a Vivado-generated Script -rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/runme.log b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/runme.log deleted file mode 100644 index 2a92916..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/runme.log +++ /dev/null @@ -1,17 +0,0 @@ - -*** Running vivado - with args -log Inverter_3lvl_P0N_3lvl_1_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_1_1.tcl - - -****** Vivado v2019.1 (64-bit) - **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 - **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source Inverter_3lvl_P0N_3lvl_1_1.tcl -notrace -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/UPzynq20_test/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/UPzynq20_test/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1'.) -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP Inverter_3lvl_P0N_3lvl_1_1, cache-ID = fdc8b3b6ee8afc45. -INFO: [Common 17-206] Exiting Vivado at Fri Jun 11 07:50:09 2021... diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/runme.sh b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/runme.sh deleted file mode 100644 index 9a50ae2..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/runme.sh +++ /dev/null @@ -1,43 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# runme.sh: a Vivado-generated Runs Script for UNIX -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# - -echo "This script was generated under a different operating system." -echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" -exit - -if [ -z "$PATH" ]; then - PATH=D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.1/bin -else - PATH=D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.1/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH= -else - LD_LIBRARY_PATH=:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1' -cd "$HD_PWD" - -HD_LOG=runme.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrap.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -EAStep vivado -log Inverter_3lvl_P0N_3lvl_1_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_1_1.tcl diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/vivado.jou b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/vivado.jou deleted file mode 100644 index 824e7b8..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1 (64-bit) -# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 -# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Fri Jun 11 07:50:03 2021 -# Process ID: 12956 -# Current directory: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1 -# Command line: vivado.exe -log Inverter_3lvl_P0N_3lvl_1_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source 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    l)7J9a@A|9=n*;GIL6 zQ$!6N0jGkTe~SFC39KE`DuV7>3HiJaGAxt; diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/Inverter_3lvl_wrapper.tcl b/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/Inverter_3lvl_wrapper.tcl index 5d18b1f..05e4746 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/Inverter_3lvl_wrapper.tcl +++ b/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/Inverter_3lvl_wrapper.tcl @@ -23,17 +23,17 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.cache/wt [current_project] -set_property parent.project_path D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.xpr [current_project] +set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.cache/wt [current_project] +set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/GITEA/UPzynq20_test/IP [current_project] +set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project] update_ip_catalog -set_property ip_output_repo d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.cache/ip [current_project] +set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_vhdl -library xil_defaultlib D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/hdl/Inverter_3lvl_wrapper.vhd -add_files D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/Inverter_3lvl.bd -set_property used_in_implementation false [get_files -all D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/Inverter_3lvl_ooc.xdc] +read_vhdl -library xil_defaultlib D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/hdl/Inverter_3lvl_wrapper.vhd +add_files D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/Inverter_3lvl.bd +set_property used_in_implementation false [get_files -all D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/Inverter_3lvl_ooc.xdc] # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/Inverter_3lvl_wrapper.vds b/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/Inverter_3lvl_wrapper.vds index 64f7cc5..ce7e638 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/Inverter_3lvl_wrapper.vds +++ b/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/Inverter_3lvl_wrapper.vds @@ -2,17 +2,17 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Fri Jun 11 07:50:20 2021 -# Process ID: 1640 -# Current directory: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1 +# Start of session at: Wed May 3 11:44:56 2023 +# Process ID: 9860 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1 # Command line: vivado.exe -log Inverter_3lvl_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_wrapper.tcl -# Log file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/Inverter_3lvl_wrapper.vds -# Journal file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/Inverter_3lvl_wrapper.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1\vivado.jou #----------------------------------------------------------- source Inverter_3lvl_wrapper.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/UPzynq20_test/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/UPzynq20_test/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. Command: synth_design -top Inverter_3lvl_wrapper -part xc7z020clg484-3 Starting synth_design @@ -20,43 +20,43 @@ Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020' INFO: [Device 21-403] Loading part xc7z020clg484-3 INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 2984 +INFO: Helper process launched with PID 1824 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 833.910 ; gain = 178.008 +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 835.906 ; gain = 178.555 --------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_wrapper' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/hdl/Inverter_3lvl_wrapper.vhd:34] -INFO: [Synth 8-3491] module 'Inverter_3lvl' declared at 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:14' bound to instance 'Inverter_3lvl_i' of component 'Inverter_3lvl' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/hdl/Inverter_3lvl_wrapper.vhd:55] -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:38] -INFO: [Synth 8-3491] module 'Inverter_3lvl_BUS_16IN_0_0' declared at 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_BUS_16IN_0_0_stub.vhdl:5' bound to instance 'BUS_16IN_0' of component 'Inverter_3lvl_BUS_16IN_0_0' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:416] -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_BUS_16IN_0_0' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_BUS_16IN_0_0_stub.vhdl:28] -INFO: [Synth 8-3491] module 'Inverter_3lvl_BUS_16IN_1_0' declared at 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_BUS_16IN_1_0_stub.vhdl:5' bound to instance 'BUS_16IN_1' of component 'Inverter_3lvl_BUS_16IN_1_0' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:436] -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_BUS_16IN_1_0' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_BUS_16IN_1_0_stub.vhdl:28] -INFO: [Synth 8-3491] module 'Inverter_3lvl_BUS_16OUT_0_0' declared at 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_BUS_16OUT_0_0_stub.vhdl:5' bound to instance 'BUS_16OUT_0' of component 'Inverter_3lvl_BUS_16OUT_0_0' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:456] -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_BUS_16OUT_0_0' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_BUS_16OUT_0_0_stub.vhdl:29] -INFO: [Synth 8-3491] module 'Inverter_3lvl_BUS_16OUT_0_1' declared at 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_BUS_16OUT_0_1_stub.vhdl:5' bound to instance 'BUS_16OUT_1' of component 'Inverter_3lvl_BUS_16OUT_0_1' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:477] -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_BUS_16OUT_0_1' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_BUS_16OUT_0_1_stub.vhdl:29] -INFO: [Synth 8-3491] module 'Inverter_3lvl_BUS_16OUT_1_0' declared at 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_BUS_16OUT_1_0_stub.vhdl:5' bound to instance 'BUS_16OUT_2' of component 'Inverter_3lvl_BUS_16OUT_1_0' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:498] -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_BUS_16OUT_1_0' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_BUS_16OUT_1_0_stub.vhdl:29] -INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_0_0' declared at 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_0_stub.vhdl:5' bound to instance 'P0N_3lvl_0' of component 'Inverter_3lvl_P0N_3lvl_0_0' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:519] -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_0' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_0_stub.vhdl:26] -INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_1_0' declared at 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_1_0_stub.vhdl:5' bound to instance 'P0N_3lvl_1' of component 'Inverter_3lvl_P0N_3lvl_1_0' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:537] -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_1_0' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_1_0_stub.vhdl:26] -INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_1_1' declared at 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_1_1_stub.vhdl:5' bound to instance 'P0N_3lvl_2' of component 'Inverter_3lvl_P0N_3lvl_1_1' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:555] -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_1_1' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_1_1_stub.vhdl:26] -INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_0_1' declared at 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_1_stub.vhdl:5' bound to instance 'P0N_3lvl_3' of component 'Inverter_3lvl_P0N_3lvl_0_1' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:573] -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_1' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_1_stub.vhdl:26] -INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_0_2' declared at 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_2_stub.vhdl:5' bound to instance 'P0N_3lvl_4' of component 'Inverter_3lvl_P0N_3lvl_0_2' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:591] -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_2' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_2_stub.vhdl:26] -INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_0_3' declared at 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_3_stub.vhdl:5' bound to instance 'P0N_3lvl_5' of component 'Inverter_3lvl_P0N_3lvl_0_3' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:609] -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_3' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_3_stub.vhdl:26] -INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_0_4' declared at 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_4_stub.vhdl:5' bound to instance 'P0N_3lvl_6' of component 'Inverter_3lvl_P0N_3lvl_0_4' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:627] -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_4' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_4_stub.vhdl:26] -INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_0_5' declared at 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_5_stub.vhdl:5' bound to instance 'P0N_3lvl_7' of component 'Inverter_3lvl_P0N_3lvl_0_5' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:645] -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_5' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_5_stub.vhdl:26] -INFO: [Synth 8-256] done synthesizing module 'Inverter_3lvl' (1#1) [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:38] -INFO: [Synth 8-256] done synthesizing module 'Inverter_3lvl_wrapper' (2#1) [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/hdl/Inverter_3lvl_wrapper.vhd:34] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_wrapper' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/hdl/Inverter_3lvl_wrapper.vhd:34] +INFO: [Synth 8-3491] module 'Inverter_3lvl' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:14' bound to instance 'Inverter_3lvl_i' of component 'Inverter_3lvl' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/hdl/Inverter_3lvl_wrapper.vhd:55] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:38] +INFO: [Synth 8-3491] module 'Inverter_3lvl_BUS_16IN_0_0' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_BUS_16IN_0_0_stub.vhdl:5' bound to instance 'BUS_16IN_0' of component 'Inverter_3lvl_BUS_16IN_0_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:416] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_BUS_16IN_0_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_BUS_16IN_0_0_stub.vhdl:28] +INFO: [Synth 8-3491] module 'Inverter_3lvl_BUS_16IN_1_0' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_BUS_16IN_1_0_stub.vhdl:5' bound to instance 'BUS_16IN_1' of component 'Inverter_3lvl_BUS_16IN_1_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:436] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_BUS_16IN_1_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_BUS_16IN_1_0_stub.vhdl:28] +INFO: [Synth 8-3491] module 'Inverter_3lvl_BUS_16OUT_0_0' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_BUS_16OUT_0_0_stub.vhdl:5' bound to instance 'BUS_16OUT_0' of component 'Inverter_3lvl_BUS_16OUT_0_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:456] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_BUS_16OUT_0_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_BUS_16OUT_0_0_stub.vhdl:29] +INFO: [Synth 8-3491] module 'Inverter_3lvl_BUS_16OUT_0_1' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_BUS_16OUT_0_1_stub.vhdl:5' bound to instance 'BUS_16OUT_1' of component 'Inverter_3lvl_BUS_16OUT_0_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:477] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_BUS_16OUT_0_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_BUS_16OUT_0_1_stub.vhdl:29] +INFO: [Synth 8-3491] module 'Inverter_3lvl_BUS_16OUT_1_0' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_BUS_16OUT_1_0_stub.vhdl:5' bound to instance 'BUS_16OUT_2' of component 'Inverter_3lvl_BUS_16OUT_1_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:498] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_BUS_16OUT_1_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_BUS_16OUT_1_0_stub.vhdl:29] +INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_0_0' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_0_stub.vhdl:5' bound to instance 'P0N_3lvl_0' of component 'Inverter_3lvl_P0N_3lvl_0_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:519] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_0_stub.vhdl:26] +INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_1_0' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_1_0_stub.vhdl:5' bound to instance 'P0N_3lvl_1' of component 'Inverter_3lvl_P0N_3lvl_1_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:537] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_1_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_1_0_stub.vhdl:26] +INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_1_1' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_1_1_stub.vhdl:5' bound to instance 'P0N_3lvl_2' of component 'Inverter_3lvl_P0N_3lvl_1_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:555] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_1_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_1_1_stub.vhdl:26] +INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_0_1' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_1_stub.vhdl:5' bound to instance 'P0N_3lvl_3' of component 'Inverter_3lvl_P0N_3lvl_0_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:573] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_1_stub.vhdl:26] +INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_0_2' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_2_stub.vhdl:5' bound to instance 'P0N_3lvl_4' of component 'Inverter_3lvl_P0N_3lvl_0_2' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:591] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_2' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_2_stub.vhdl:26] +INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_0_3' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_3_stub.vhdl:5' bound to instance 'P0N_3lvl_5' of component 'Inverter_3lvl_P0N_3lvl_0_3' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:609] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_3' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_3_stub.vhdl:26] +INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_0_4' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_4_stub.vhdl:5' bound to instance 'P0N_3lvl_6' of component 'Inverter_3lvl_P0N_3lvl_0_4' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:627] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_4' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_4_stub.vhdl:26] +INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_0_5' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_5_stub.vhdl:5' bound to instance 'P0N_3lvl_7' of component 'Inverter_3lvl_P0N_3lvl_0_5' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:645] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_5' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_5_stub.vhdl:26] +INFO: [Synth 8-256] done synthesizing module 'Inverter_3lvl' (1#1) [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:38] +INFO: [Synth 8-256] done synthesizing module 'Inverter_3lvl_wrapper' (2#1) [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/hdl/Inverter_3lvl_wrapper.vhd:34] --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 898.543 ; gain = 242.641 +Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 900.113 ; gain = 242.762 --------------------------------------------------------------------------------- Report Check Netlist: @@ -69,59 +69,59 @@ Report Check Netlist: Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 898.543 ; gain = 242.641 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 900.113 ; gain = 242.762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 898.543 ; gain = 242.641 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 900.113 ; gain = 242.762 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine -Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_0' -Finished Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_0' -Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_1' -Finished Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_1' -Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_2' -Finished Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_2' -Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_3' -Finished Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_3' -Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_4' -Finished Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_4' -Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_5' -Finished Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_5' -Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_6' -Finished Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_6' -Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_7' -Finished Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_7' -Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16IN_0' -Finished Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16IN_0' -Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16IN_1' -Finished Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16IN_1' -Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16OUT_0' -Finished Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16OUT_0' -Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16OUT_1' -Finished Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16OUT_1' -Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16OUT_2' -Finished Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16OUT_2' -Parsing XDC File [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/dont_touch.xdc] -Finished Parsing XDC File [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/dont_touch.xdc] +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_0' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_0' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_1' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_1' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_2' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_2' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_3' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_3' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_4' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_4' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_5' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_5' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_6' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_6' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_7' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_7' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16IN_0' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16IN_0' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16IN_1' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16IN_1' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16OUT_0' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16OUT_0' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16OUT_1' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16OUT_1' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16OUT_2' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16OUT_2' +Parsing XDC File [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/dont_touch.xdc] +Finished Parsing XDC File [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/dont_touch.xdc] Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 983.715 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 983.074 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 983.715 ; gain = 0.000 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 983.074 ; gain = 0.000 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 983.715 ; gain = 327.813 +Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 983.074 ; gain = 325.723 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg484-3 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 983.715 ; gain = 327.813 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 983.074 ; gain = 325.723 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints @@ -141,10 +141,10 @@ Applied set_property DONT_TOUCH = true for Inverter_3lvl_i/BUS_16OUT_0. (constra Applied set_property DONT_TOUCH = true for Inverter_3lvl_i/BUS_16OUT_1. (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for Inverter_3lvl_i/BUS_16OUT_2. (constraint file auto generated constraint, line ). --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 983.715 ; gain = 327.813 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 983.074 ; gain = 325.723 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 983.715 ; gain = 327.813 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 983.074 ; gain = 325.723 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -180,7 +180,7 @@ Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 983.715 ; gain = 327.813 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 983.074 ; gain = 325.723 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -192,13 +192,13 @@ Report RTL Partitions: Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 983.715 ; gain = 327.813 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 983.074 ; gain = 325.723 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 983.715 ; gain = 327.813 +Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 983.074 ; gain = 325.723 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -210,7 +210,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 983.715 ; gain = 327.813 +Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 985.117 ; gain = 327.766 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -234,7 +234,7 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 997.234 ; gain = 341.332 +Finished IO Insertion : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1000.926 ; gain = 343.574 --------------------------------------------------------------------------------- Report Check Netlist: @@ -247,7 +247,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 997.234 ; gain = 341.332 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1000.926 ; gain = 343.574 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -259,25 +259,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 997.234 ; gain = 341.332 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1000.926 ; gain = 343.574 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 997.234 ; gain = 341.332 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1000.926 ; gain = 343.574 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 997.234 ; gain = 341.332 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1000.926 ; gain = 343.574 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 997.234 ; gain = 341.332 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1000.926 ; gain = 343.574 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -331,25 +331,25 @@ Report Instance Areas: |2 | Inverter_3lvl_i |Inverter_3lvl | 120| +------+------------------+--------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 997.234 ; gain = 341.332 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1000.926 ; gain = 343.574 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 997.234 ; gain = 256.160 -Synthesis Optimization Complete : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 997.234 ; gain = 341.332 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 1000.926 ; gain = 260.613 +Synthesis Optimization Complete : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1000.926 ; gain = 343.574 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1016.742 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1012.535 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 43 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 1016.742 ; gain = 629.863 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1016.742 ; gain = 0.000 +synth_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 1012.535 ; gain = 623.469 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1012.535 ; gain = 0.000 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/Inverter_3lvl_wrapper.dcp' has been generated. +INFO: [Common 17-1381] The checkpoint 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/Inverter_3lvl_wrapper.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file Inverter_3lvl_wrapper_utilization_synth.rpt -pb Inverter_3lvl_wrapper_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Fri Jun 11 07:50:55 2021... +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:45:29 2023... diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/Inverter_3lvl_wrapper_utilization_synth.rpt b/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/Inverter_3lvl_wrapper_utilization_synth.rpt index ce8b9db..a383a2f 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/Inverter_3lvl_wrapper_utilization_synth.rpt +++ b/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/Inverter_3lvl_wrapper_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 -| Date : Fri Jun 11 07:50:55 2021 +| Date : Wed May 3 11:45:29 2023 | Host : STAS-W10 running 64-bit major release (build 9200) | Command : report_utilization -file Inverter_3lvl_wrapper_utilization_synth.rpt -pb Inverter_3lvl_wrapper_utilization_synth.pb | Design : Inverter_3lvl_wrapper diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/gen_run.xml b/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/gen_run.xml index 48610b8..12b82a8 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/gen_run.xml +++ b/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -49,14 +49,4 @@ - - - - - - - - - - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/project.wdf b/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/project.wdf index 22769b2..7a290ea 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/project.wdf +++ b/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/project.wdf @@ -6,8 +6,8 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3131:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3131:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:5648444c:00:00 @@ -41,4 +41,4 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:36:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:36:00:00 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3535323030373536376161373461663938353435666431303963343433336437:506172656e742050412070726f6a656374204944:00 -eof:1822582040 +eof:2475748161 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/runme.log b/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/runme.log index 6fa3d81..b17b992 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/runme.log +++ b/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/runme.log @@ -10,8 +10,8 @@ source Inverter_3lvl_wrapper.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/UPzynq20_test/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/UPzynq20_test/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. Command: synth_design -top Inverter_3lvl_wrapper -part xc7z020clg484-3 Starting synth_design @@ -19,43 +19,43 @@ Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020' INFO: [Device 21-403] Loading part xc7z020clg484-3 INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 2984 +INFO: Helper process launched with PID 1824 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 833.910 ; gain = 178.008 +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 835.906 ; gain = 178.555 --------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_wrapper' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/hdl/Inverter_3lvl_wrapper.vhd:34] -INFO: [Synth 8-3491] module 'Inverter_3lvl' declared at 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:14' bound to instance 'Inverter_3lvl_i' of component 'Inverter_3lvl' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/hdl/Inverter_3lvl_wrapper.vhd:55] -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:38] -INFO: [Synth 8-3491] module 'Inverter_3lvl_BUS_16IN_0_0' declared at 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_BUS_16IN_0_0_stub.vhdl:5' bound to instance 'BUS_16IN_0' of component 'Inverter_3lvl_BUS_16IN_0_0' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:416] -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_BUS_16IN_0_0' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_BUS_16IN_0_0_stub.vhdl:28] -INFO: [Synth 8-3491] module 'Inverter_3lvl_BUS_16IN_1_0' declared at 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_BUS_16IN_1_0_stub.vhdl:5' bound to instance 'BUS_16IN_1' of component 'Inverter_3lvl_BUS_16IN_1_0' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:436] -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_BUS_16IN_1_0' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_BUS_16IN_1_0_stub.vhdl:28] -INFO: [Synth 8-3491] module 'Inverter_3lvl_BUS_16OUT_0_0' declared at 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_BUS_16OUT_0_0_stub.vhdl:5' bound to instance 'BUS_16OUT_0' of component 'Inverter_3lvl_BUS_16OUT_0_0' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:456] -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_BUS_16OUT_0_0' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_BUS_16OUT_0_0_stub.vhdl:29] -INFO: [Synth 8-3491] module 'Inverter_3lvl_BUS_16OUT_0_1' declared at 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_BUS_16OUT_0_1_stub.vhdl:5' bound to instance 'BUS_16OUT_1' of component 'Inverter_3lvl_BUS_16OUT_0_1' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:477] -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_BUS_16OUT_0_1' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_BUS_16OUT_0_1_stub.vhdl:29] -INFO: [Synth 8-3491] module 'Inverter_3lvl_BUS_16OUT_1_0' declared at 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_BUS_16OUT_1_0_stub.vhdl:5' bound to instance 'BUS_16OUT_2' of component 'Inverter_3lvl_BUS_16OUT_1_0' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:498] -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_BUS_16OUT_1_0' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_BUS_16OUT_1_0_stub.vhdl:29] -INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_0_0' declared at 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_0_stub.vhdl:5' bound to instance 'P0N_3lvl_0' of component 'Inverter_3lvl_P0N_3lvl_0_0' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:519] -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_0' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_0_stub.vhdl:26] -INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_1_0' declared at 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_1_0_stub.vhdl:5' bound to instance 'P0N_3lvl_1' of component 'Inverter_3lvl_P0N_3lvl_1_0' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:537] -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_1_0' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_1_0_stub.vhdl:26] -INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_1_1' declared at 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_1_1_stub.vhdl:5' bound to instance 'P0N_3lvl_2' of component 'Inverter_3lvl_P0N_3lvl_1_1' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:555] -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_1_1' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_1_1_stub.vhdl:26] -INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_0_1' declared at 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_1_stub.vhdl:5' bound to instance 'P0N_3lvl_3' of component 'Inverter_3lvl_P0N_3lvl_0_1' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:573] -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_1' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_1_stub.vhdl:26] -INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_0_2' declared at 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_2_stub.vhdl:5' bound to instance 'P0N_3lvl_4' of component 'Inverter_3lvl_P0N_3lvl_0_2' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:591] -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_2' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_2_stub.vhdl:26] -INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_0_3' declared at 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_3_stub.vhdl:5' bound to instance 'P0N_3lvl_5' of component 'Inverter_3lvl_P0N_3lvl_0_3' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:609] -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_3' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_3_stub.vhdl:26] -INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_0_4' declared at 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_4_stub.vhdl:5' bound to instance 'P0N_3lvl_6' of component 'Inverter_3lvl_P0N_3lvl_0_4' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:627] -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_4' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_4_stub.vhdl:26] -INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_0_5' declared at 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_5_stub.vhdl:5' bound to instance 'P0N_3lvl_7' of component 'Inverter_3lvl_P0N_3lvl_0_5' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:645] -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_5' [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-1640-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_5_stub.vhdl:26] -INFO: [Synth 8-256] done synthesizing module 'Inverter_3lvl' (1#1) [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:38] -INFO: [Synth 8-256] done synthesizing module 'Inverter_3lvl_wrapper' (2#1) [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/hdl/Inverter_3lvl_wrapper.vhd:34] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_wrapper' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/hdl/Inverter_3lvl_wrapper.vhd:34] +INFO: [Synth 8-3491] module 'Inverter_3lvl' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:14' bound to instance 'Inverter_3lvl_i' of component 'Inverter_3lvl' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/hdl/Inverter_3lvl_wrapper.vhd:55] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:38] +INFO: [Synth 8-3491] module 'Inverter_3lvl_BUS_16IN_0_0' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_BUS_16IN_0_0_stub.vhdl:5' bound to instance 'BUS_16IN_0' of component 'Inverter_3lvl_BUS_16IN_0_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:416] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_BUS_16IN_0_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_BUS_16IN_0_0_stub.vhdl:28] +INFO: [Synth 8-3491] module 'Inverter_3lvl_BUS_16IN_1_0' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_BUS_16IN_1_0_stub.vhdl:5' bound to instance 'BUS_16IN_1' of component 'Inverter_3lvl_BUS_16IN_1_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:436] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_BUS_16IN_1_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_BUS_16IN_1_0_stub.vhdl:28] +INFO: [Synth 8-3491] module 'Inverter_3lvl_BUS_16OUT_0_0' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_BUS_16OUT_0_0_stub.vhdl:5' bound to instance 'BUS_16OUT_0' of component 'Inverter_3lvl_BUS_16OUT_0_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:456] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_BUS_16OUT_0_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_BUS_16OUT_0_0_stub.vhdl:29] +INFO: [Synth 8-3491] module 'Inverter_3lvl_BUS_16OUT_0_1' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_BUS_16OUT_0_1_stub.vhdl:5' bound to instance 'BUS_16OUT_1' of component 'Inverter_3lvl_BUS_16OUT_0_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:477] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_BUS_16OUT_0_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_BUS_16OUT_0_1_stub.vhdl:29] +INFO: [Synth 8-3491] module 'Inverter_3lvl_BUS_16OUT_1_0' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_BUS_16OUT_1_0_stub.vhdl:5' bound to instance 'BUS_16OUT_2' of component 'Inverter_3lvl_BUS_16OUT_1_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:498] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_BUS_16OUT_1_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_BUS_16OUT_1_0_stub.vhdl:29] +INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_0_0' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_0_stub.vhdl:5' bound to instance 'P0N_3lvl_0' of component 'Inverter_3lvl_P0N_3lvl_0_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:519] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_0_stub.vhdl:26] +INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_1_0' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_1_0_stub.vhdl:5' bound to instance 'P0N_3lvl_1' of component 'Inverter_3lvl_P0N_3lvl_1_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:537] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_1_0' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_1_0_stub.vhdl:26] +INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_1_1' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_1_1_stub.vhdl:5' bound to instance 'P0N_3lvl_2' of component 'Inverter_3lvl_P0N_3lvl_1_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:555] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_1_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_1_1_stub.vhdl:26] +INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_0_1' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_1_stub.vhdl:5' bound to instance 'P0N_3lvl_3' of component 'Inverter_3lvl_P0N_3lvl_0_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:573] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_1' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_1_stub.vhdl:26] +INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_0_2' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_2_stub.vhdl:5' bound to instance 'P0N_3lvl_4' of component 'Inverter_3lvl_P0N_3lvl_0_2' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:591] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_2' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_2_stub.vhdl:26] +INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_0_3' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_3_stub.vhdl:5' bound to instance 'P0N_3lvl_5' of component 'Inverter_3lvl_P0N_3lvl_0_3' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:609] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_3' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_3_stub.vhdl:26] +INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_0_4' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_4_stub.vhdl:5' bound to instance 'P0N_3lvl_6' of component 'Inverter_3lvl_P0N_3lvl_0_4' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:627] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_4' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_4_stub.vhdl:26] +INFO: [Synth 8-3491] module 'Inverter_3lvl_P0N_3lvl_0_5' declared at 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_5_stub.vhdl:5' bound to instance 'P0N_3lvl_7' of component 'Inverter_3lvl_P0N_3lvl_0_5' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:645] +INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_5' [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/.Xil/Vivado-9860-STAS-W10/realtime/Inverter_3lvl_P0N_3lvl_0_5_stub.vhdl:26] +INFO: [Synth 8-256] done synthesizing module 'Inverter_3lvl' (1#1) [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/synth/Inverter_3lvl.vhd:38] +INFO: [Synth 8-256] done synthesizing module 'Inverter_3lvl_wrapper' (2#1) [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/hdl/Inverter_3lvl_wrapper.vhd:34] --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 898.543 ; gain = 242.641 +Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 900.113 ; gain = 242.762 --------------------------------------------------------------------------------- Report Check Netlist: @@ -68,59 +68,59 @@ Report Check Netlist: Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 898.543 ; gain = 242.641 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 900.113 ; gain = 242.762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 898.543 ; gain = 242.641 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 900.113 ; gain = 242.762 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine -Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_0' -Finished Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_0' -Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_1' -Finished Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_1' -Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_2' -Finished Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_2' -Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_3' -Finished Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_3' -Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_4' -Finished Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_4' -Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_5' -Finished Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_5' -Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_6' -Finished Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_6' -Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_7' -Finished Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_7' -Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16IN_0' -Finished Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16IN_0' -Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16IN_1' -Finished Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16IN_1' -Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16OUT_0' -Finished Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16OUT_0' -Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16OUT_1' -Finished Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16OUT_1' -Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16OUT_2' -Finished Parsing XDC File [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16OUT_2' -Parsing XDC File [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/dont_touch.xdc] -Finished Parsing XDC File [D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/dont_touch.xdc] +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_0' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_0' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_1' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_1' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_2' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_2' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_3' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_3' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_4' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_4' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_5' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_5' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_6' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_6' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_7' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_4_in_context.xdc] for cell 'Inverter_3lvl_i/P0N_3lvl_7' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16IN_0' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16IN_0' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16IN_1' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16IN_1' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16OUT_0' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16OUT_0' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16OUT_1' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16OUT_1' +Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16OUT_2' +Finished Parsing XDC File [d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_0_0_in_context.xdc] for cell 'Inverter_3lvl_i/BUS_16OUT_2' +Parsing XDC File [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/dont_touch.xdc] +Finished Parsing XDC File [D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/dont_touch.xdc] Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 983.715 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 983.074 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 983.715 ; gain = 0.000 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 983.074 ; gain = 0.000 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 983.715 ; gain = 327.813 +Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 983.074 ; gain = 325.723 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg484-3 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 983.715 ; gain = 327.813 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 983.074 ; gain = 325.723 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints @@ -140,10 +140,10 @@ Applied set_property DONT_TOUCH = true for Inverter_3lvl_i/BUS_16OUT_0. (constra Applied set_property DONT_TOUCH = true for Inverter_3lvl_i/BUS_16OUT_1. (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for Inverter_3lvl_i/BUS_16OUT_2. (constraint file auto generated constraint, line ). --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 983.715 ; gain = 327.813 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 983.074 ; gain = 325.723 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 983.715 ; gain = 327.813 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 983.074 ; gain = 325.723 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -179,7 +179,7 @@ Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 983.715 ; gain = 327.813 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 983.074 ; gain = 325.723 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -191,13 +191,13 @@ Report RTL Partitions: Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 983.715 ; gain = 327.813 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 983.074 ; gain = 325.723 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 983.715 ; gain = 327.813 +Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 983.074 ; gain = 325.723 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -209,7 +209,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 983.715 ; gain = 327.813 +Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 985.117 ; gain = 327.766 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -233,7 +233,7 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 997.234 ; gain = 341.332 +Finished IO Insertion : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1000.926 ; gain = 343.574 --------------------------------------------------------------------------------- Report Check Netlist: @@ -246,7 +246,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 997.234 ; gain = 341.332 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1000.926 ; gain = 343.574 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -258,25 +258,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 997.234 ; gain = 341.332 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1000.926 ; gain = 343.574 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 997.234 ; gain = 341.332 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1000.926 ; gain = 343.574 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 997.234 ; gain = 341.332 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1000.926 ; gain = 343.574 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 997.234 ; gain = 341.332 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1000.926 ; gain = 343.574 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -330,25 +330,25 @@ Report Instance Areas: |2 | Inverter_3lvl_i |Inverter_3lvl | 120| +------+------------------+--------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 997.234 ; gain = 341.332 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1000.926 ; gain = 343.574 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 997.234 ; gain = 256.160 -Synthesis Optimization Complete : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 997.234 ; gain = 341.332 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 1000.926 ; gain = 260.613 +Synthesis Optimization Complete : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1000.926 ; gain = 343.574 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1016.742 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1012.535 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 43 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 1016.742 ; gain = 629.863 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1016.742 ; gain = 0.000 +synth_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 1012.535 ; gain = 623.469 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1012.535 ; gain = 0.000 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/Inverter_3lvl_wrapper.dcp' has been generated. +INFO: [Common 17-1381] The checkpoint 'D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/Inverter_3lvl_wrapper.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file Inverter_3lvl_wrapper_utilization_synth.rpt -pb Inverter_3lvl_wrapper_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Fri Jun 11 07:50:55 2021... +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:45:29 2023... diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/runme.sh b/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/runme.sh index 45f2311..1c53916 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/runme.sh +++ b/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/vivado.jou b/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/vivado.jou index 46d5e0a..7f77bd3 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/vivado.jou +++ b/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Fri Jun 11 07:50:20 2021 -# Process ID: 1640 -# Current directory: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1 +# Start of session at: Wed May 3 11:44:56 2023 +# Process ID: 9860 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1 # Command line: vivado.exe -log Inverter_3lvl_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_wrapper.tcl -# Log file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/Inverter_3lvl_wrapper.vds -# Journal file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/Inverter_3lvl_wrapper.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1\vivado.jou #----------------------------------------------------------- source Inverter_3lvl_wrapper.tcl -notrace diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/vivado.pb b/LIB/Inverter_3lvl/Inverter_3lvl.runs/synth_1/vivado.pb index 5131d11f4ffded3f7e951894c6e0f61ee9d1bdd9..dcd3603268471ccbc7ab1353772c0dec6af67b14 100644 GIT binary patch delta 5337 zcmb7IZA?>F7|tmma@&GHY58ogBGd74xwoGbrxOP%OgG0T+EF&F1_Qx`Y0X_UDASTc>nWXZB*?zR^!8i8|u+#l_EpZ9tC zyzhI?={m^d#lx=8vAN1|ChCJ6Kg6ptlK5(az7{E6OX^^D}wLks;V@HdLQ7 z5#VZAGHwK=m>LPUC3{q9HITxxV9G4Ur06ix0Y16}rr<hD`MlHjc;2O&8Hk_L% zklj8_`jA9Z!?@Y24mc;vlGdS+6ZzwWbCI#scr=*-&I~)+4AWtHbpleg94^JD;YD>m z1y?m+Vr#gbZzo(6rMm)RBI+r0Rzrvs$Z21_>mw!p1RI4K3v|N@MMF#itvn}g zCMKgGLW@75a;RjU)%#^8fQ!Pjcc%_ZWi-}H@^{kk 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zUZ~MJz~kXiseC{?@0985xQd9!i**0aLZT~vZ?kb(eT`8Nj8<2!! viewChecksum - fe81ab1b + 1c805ed8 @@ -82,7 +82,7 @@ viewChecksum - 2d3780d6 + 1010cca7 @@ -343,54 +343,9 @@ xilinx_anylanguagesynthesis_view_fileset - Inverter_3lvl_ooc.xdc - xdc - SCOPED_TO_REF_Inverter_3lvl - USED_IN_out_of_context - - - ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5.xci - xci - - processing_order - early - - - - ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4.xci - xci - - processing_order - early - - - - ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3.xci - xci - - processing_order - early - - - - ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2.xci - xci - - processing_order - early - - - - ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1.xci - xci - - processing_order - early - - - - ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1.xci + ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0.xci xci + CELL_NAME_P0N_3lvl_0 processing_order early @@ -399,14 +354,97 @@ ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0.xci xci + CELL_NAME_P0N_3lvl_1 processing_order early - ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0.xci + ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1.xci xci + CELL_NAME_P0N_3lvl_2 + + processing_order + early + + + + ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1.xci + xci + CELL_NAME_P0N_3lvl_3 + + processing_order + early + + + + ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2.xci + xci + CELL_NAME_P0N_3lvl_4 + + processing_order + early + + + + ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3.xci + xci + CELL_NAME_P0N_3lvl_5 + + processing_order + early + + + + ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4.xci + xci + CELL_NAME_P0N_3lvl_6 + + processing_order + early + + + + ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5.xci + xci + CELL_NAME_P0N_3lvl_7 + + processing_order + early + + + + ip/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0.xci + xci + CELL_NAME_BUS_16IN_0 + + processing_order + early + + + + ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0.xci + xci + CELL_NAME_BUS_16IN_1 + + processing_order + early + + + + ip/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0.xci + xci + CELL_NAME_BUS_16OUT_0 + + processing_order + early + + + + ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1.xci + xci + CELL_NAME_BUS_16OUT_1 processing_order early @@ -415,31 +453,34 @@ ip/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_1_0.xci xci + CELL_NAME_BUS_16OUT_2 + + processing_order + early + - ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1.xci - xci - - - ip/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0.xci - xci - - - ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0.xci - xci - - - ip/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0.xci - xci - - - sim/Inverter_3lvl.vhd + synth/Inverter_3lvl.vhd vhdlSource + + processing_order + early + + + + Inverter_3lvl_ooc.xdc + xdc + SCOPED_TO_REF_Inverter_3lvl + USED_IN_out_of_context + + processing_order + early + hdl/Inverter_3lvl_wrapper.vhd vhdlSource - CHECKSUM_15864d9a + CHECKSUM_77abda73 @@ -495,48 +536,9 @@ xilinx_anylanguagebehavioralsimulation_view_fileset - ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5.xci - xci - - processing_order - early - - - - ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4.xci - xci - - processing_order - early - - - - ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3.xci - xci - - processing_order - early - - - - ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2.xci - xci - - processing_order - early - - - - ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1.xci - xci - - processing_order - early - - - - ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1.xci + ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0.xci xci + CELL_NAME_P0N_3lvl_0 processing_order early @@ -545,14 +547,97 @@ ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0.xci xci + CELL_NAME_P0N_3lvl_1 processing_order early - ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0.xci + ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1.xci xci + CELL_NAME_P0N_3lvl_2 + + processing_order + early + + + + ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1.xci + xci + CELL_NAME_P0N_3lvl_3 + + processing_order + early + + + + ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2.xci + xci + CELL_NAME_P0N_3lvl_4 + + processing_order + early + + + + ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3.xci + xci + CELL_NAME_P0N_3lvl_5 + + processing_order + early + + + + ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4.xci + xci + CELL_NAME_P0N_3lvl_6 + + processing_order + early + + + + ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5.xci + xci + CELL_NAME_P0N_3lvl_7 + + processing_order + early + + + + ip/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0.xci + xci + CELL_NAME_BUS_16IN_0 + + processing_order + early + + + + ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0.xci + xci + CELL_NAME_BUS_16IN_1 + + processing_order + early + + + + ip/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0.xci + xci + CELL_NAME_BUS_16OUT_0 + + processing_order + early + + + + ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1.xci + xci + CELL_NAME_BUS_16OUT_1 processing_order early @@ -561,30 +646,27 @@ ip/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_1_0.xci xci - - - ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1.xci - xci - - - ip/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0.xci - xci - - - ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0.xci - xci - - - ip/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0.xci - xci + CELL_NAME_BUS_16OUT_2 + + processing_order + early + sim/Inverter_3lvl.vhd vhdlSource + + processing_order + early + sim/Inverter_3lvl.protoinst unknown + + processing_order + early + hdl/Inverter_3lvl_wrapper.vhd @@ -661,7 +743,8 @@ - zynq + zynq + artix7 /UserIP @@ -670,8 +753,8 @@ package_project S7DNRJ https://ssevendenergy.com - 8 - 2021-06-10T13:43:06Z + 9 + 2023-05-03T08:45:48Z d:/projects/ip/lib/inverter_3lvl/inverter_3lvl.srcs/sources_1/bd/inverter_3lvl d:/projects/ip/lib/inverter_3lvl/inverter_3lvl.srcs/sources_1/bd/inverter_3lvl @@ -745,13 +828,44 @@ d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl + d:/GITEA/GitHub/ES/IP_cores/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/inverter_3lvl 2019.1 - - + + diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0.dcp 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08:44:44 UTC 2023 + + + outputProductCRC + 9:ae7942a4 + + + @@ -355,6 +373,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + Inverter_3lvl_BUS_16IN_0_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + Inverter_3lvl_BUS_16IN_0_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Inverter_3lvl_BUS_16IN_0_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Inverter_3lvl_BUS_16IN_0_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Inverter_3lvl_BUS_16IN_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + BUS_16IN_v1_0 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0_sim_netlist.v b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0_sim_netlist.v new file mode 100644 index 0000000..3e72021 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0_sim_netlist.v @@ -0,0 +1,142 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Fri Jun 11 07:49:57 2021 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top Inverter_3lvl_BUS_16IN_0_0 -prefix +// Inverter_3lvl_BUS_16IN_0_0_ Inverter_3lvl_BUS_16IN_0_0_sim_netlist.v +// Design : Inverter_3lvl_BUS_16IN_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "Inverter_3lvl_BUS_16IN_0_0,BUS_16IN,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "BUS_16IN,Vivado 2019.1" *) +(* NotValidForBitStream *) +module Inverter_3lvl_BUS_16IN_0_0 + (BusBlock16IN, + Out0, + Out1, + Out2, + Out3, + Out4, + Out5, + Out6, + Out7, + Out8, + Out9, + Out10, + Out11, + Out12, + Out13, + Out14, + Out15); + input [15:0]BusBlock16IN; + output Out0; + output Out1; + output Out2; + output Out3; + output Out4; + output Out5; + output Out6; + output Out7; + output Out8; + output Out9; + output Out10; + output Out11; + output Out12; + output Out13; + output Out14; + output Out15; + + wire [15:0]BusBlock16IN; + + assign Out0 = BusBlock16IN[0]; + assign Out1 = BusBlock16IN[1]; + assign Out10 = BusBlock16IN[10]; + assign Out11 = BusBlock16IN[11]; + assign Out12 = BusBlock16IN[12]; + assign Out13 = BusBlock16IN[13]; + assign Out14 = BusBlock16IN[14]; + assign Out15 = BusBlock16IN[15]; + assign Out2 = BusBlock16IN[2]; + assign Out3 = BusBlock16IN[3]; + assign Out4 = BusBlock16IN[4]; + assign Out5 = BusBlock16IN[5]; + assign Out6 = BusBlock16IN[6]; + assign Out7 = BusBlock16IN[7]; + assign Out8 = BusBlock16IN[8]; + assign Out9 = BusBlock16IN[9]; +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0_sim_netlist.vhdl b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0_sim_netlist.vhdl new file mode 100644 index 0000000..70c4638 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0_sim_netlist.vhdl @@ -0,0 +1,69 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Fri Jun 11 07:49:57 2021 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top Inverter_3lvl_BUS_16IN_0_0 -prefix +-- Inverter_3lvl_BUS_16IN_0_0_ Inverter_3lvl_BUS_16IN_0_0_sim_netlist.vhdl +-- Design : Inverter_3lvl_BUS_16IN_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Inverter_3lvl_BUS_16IN_0_0 is + port ( + BusBlock16IN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + Out0 : out STD_LOGIC; + Out1 : out STD_LOGIC; + Out2 : out STD_LOGIC; + Out3 : out STD_LOGIC; + Out4 : out STD_LOGIC; + Out5 : out STD_LOGIC; + Out6 : out STD_LOGIC; + Out7 : out STD_LOGIC; + Out8 : out STD_LOGIC; + Out9 : out STD_LOGIC; + Out10 : out STD_LOGIC; + Out11 : out STD_LOGIC; + Out12 : out STD_LOGIC; + Out13 : out STD_LOGIC; + Out14 : out STD_LOGIC; + Out15 : out STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of Inverter_3lvl_BUS_16IN_0_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of Inverter_3lvl_BUS_16IN_0_0 : entity is "Inverter_3lvl_BUS_16IN_0_0,BUS_16IN,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of Inverter_3lvl_BUS_16IN_0_0 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of Inverter_3lvl_BUS_16IN_0_0 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of Inverter_3lvl_BUS_16IN_0_0 : entity is "BUS_16IN,Vivado 2019.1"; +end Inverter_3lvl_BUS_16IN_0_0; + +architecture STRUCTURE of Inverter_3lvl_BUS_16IN_0_0 is + signal \^busblock16in\ : STD_LOGIC_VECTOR ( 15 downto 0 ); +begin + Out0 <= \^busblock16in\(0); + Out1 <= \^busblock16in\(1); + Out10 <= \^busblock16in\(10); + Out11 <= \^busblock16in\(11); + Out12 <= \^busblock16in\(12); + Out13 <= \^busblock16in\(13); + Out14 <= \^busblock16in\(14); + Out15 <= \^busblock16in\(15); + Out2 <= \^busblock16in\(2); + Out3 <= \^busblock16in\(3); + Out4 <= \^busblock16in\(4); + Out5 <= \^busblock16in\(5); + Out6 <= \^busblock16in\(6); + Out7 <= \^busblock16in\(7); + Out8 <= \^busblock16in\(8); + Out9 <= \^busblock16in\(9); + \^busblock16in\(15 downto 0) <= BusBlock16IN(15 downto 0); +end STRUCTURE; diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0_stub.v b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0_stub.v new file mode 100644 index 0000000..b9ba4c4 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0_stub.v @@ -0,0 +1,37 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Fri Jun 11 07:49:57 2021 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top Inverter_3lvl_BUS_16IN_0_0 -prefix +// Inverter_3lvl_BUS_16IN_0_0_ Inverter_3lvl_BUS_16IN_0_0_stub.v +// Design : Inverter_3lvl_BUS_16IN_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "BUS_16IN,Vivado 2019.1" *) +module Inverter_3lvl_BUS_16IN_0_0(BusBlock16IN, Out0, Out1, Out2, Out3, Out4, Out5, Out6, + Out7, Out8, Out9, Out10, Out11, Out12, Out13, Out14, Out15) +/* synthesis syn_black_box black_box_pad_pin="BusBlock16IN[15:0],Out0,Out1,Out2,Out3,Out4,Out5,Out6,Out7,Out8,Out9,Out10,Out11,Out12,Out13,Out14,Out15" */; + input [15:0]BusBlock16IN; + output Out0; + output Out1; + output Out2; + output Out3; + output Out4; + output Out5; + output Out6; + output Out7; + output Out8; + output Out9; + output Out10; + output Out11; + output Out12; + output Out13; + output Out14; + output Out15; +endmodule diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0_stub.vhdl b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0_stub.vhdl new file mode 100644 index 0000000..ed984c8 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_0_0/Inverter_3lvl_BUS_16IN_0_0_stub.vhdl @@ -0,0 +1,46 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Fri Jun 11 07:49:57 2021 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top Inverter_3lvl_BUS_16IN_0_0 -prefix +-- Inverter_3lvl_BUS_16IN_0_0_ Inverter_3lvl_BUS_16IN_0_0_stub.vhdl +-- Design : Inverter_3lvl_BUS_16IN_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Inverter_3lvl_BUS_16IN_0_0 is + Port ( + BusBlock16IN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + Out0 : out STD_LOGIC; + Out1 : out STD_LOGIC; + Out2 : out STD_LOGIC; + Out3 : out STD_LOGIC; + Out4 : out STD_LOGIC; + Out5 : out STD_LOGIC; + Out6 : out STD_LOGIC; + Out7 : out STD_LOGIC; + Out8 : out STD_LOGIC; + Out9 : out STD_LOGIC; + Out10 : out STD_LOGIC; + Out11 : out STD_LOGIC; + Out12 : out STD_LOGIC; + Out13 : out STD_LOGIC; + Out14 : out STD_LOGIC; + Out15 : out STD_LOGIC + ); + +end Inverter_3lvl_BUS_16IN_0_0; + +architecture stub of Inverter_3lvl_BUS_16IN_0_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "BusBlock16IN[15:0],Out0,Out1,Out2,Out3,Out4,Out5,Out6,Out7,Out8,Out9,Out10,Out11,Out12,Out13,Out14,Out15"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "BUS_16IN,Vivado 2019.1"; +begin +end; diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/Inverter_3lvl_BUS_16IN_1_0.dcp b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0.dcp similarity index 97% rename from LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_1_0_synth_1/Inverter_3lvl_BUS_16IN_1_0.dcp rename to LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0.dcp index 72d3758c80794360423adc5a380ff03dbc7df5f7..7e6c3f56f92502a2dfe95bf7c8773be0100416d8 100644 GIT binary patch delta 26 ecmaE_^;h-RYpsc>;%6z^ut8qSgSAjR~&+ diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0.xml b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0.xml index d190784..d8bb4a8 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0.xml +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0.xml @@ -95,6 +95,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:44:44 UTC 2023 + + + outputProductCRC + 9:cd8310d7 + + + @@ -355,6 +373,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + Inverter_3lvl_BUS_16IN_1_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + Inverter_3lvl_BUS_16IN_1_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Inverter_3lvl_BUS_16IN_1_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Inverter_3lvl_BUS_16IN_1_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Inverter_3lvl_BUS_16IN_1_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + BUS_16IN_v1_0 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0_sim_netlist.v b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0_sim_netlist.v new file mode 100644 index 0000000..f8efa2c --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0_sim_netlist.v @@ -0,0 +1,142 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Fri Jun 11 07:49:57 2021 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top Inverter_3lvl_BUS_16IN_1_0 -prefix +// Inverter_3lvl_BUS_16IN_1_0_ Inverter_3lvl_BUS_16IN_0_0_sim_netlist.v +// Design : Inverter_3lvl_BUS_16IN_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "Inverter_3lvl_BUS_16IN_0_0,BUS_16IN,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "BUS_16IN,Vivado 2019.1" *) +(* NotValidForBitStream *) +module Inverter_3lvl_BUS_16IN_1_0 + (BusBlock16IN, + Out0, + Out1, + Out2, + Out3, + Out4, + Out5, + Out6, + Out7, + Out8, + Out9, + Out10, + Out11, + Out12, + Out13, + Out14, + Out15); + input [15:0]BusBlock16IN; + output Out0; + output Out1; + output Out2; + output Out3; + output Out4; + output Out5; + output Out6; + output Out7; + output Out8; + output Out9; + output Out10; + output Out11; + output Out12; + output Out13; + output Out14; + output Out15; + + wire [15:0]BusBlock16IN; + + assign Out0 = BusBlock16IN[0]; + assign Out1 = BusBlock16IN[1]; + assign Out10 = BusBlock16IN[10]; + assign Out11 = BusBlock16IN[11]; + assign Out12 = BusBlock16IN[12]; + assign Out13 = BusBlock16IN[13]; + assign Out14 = BusBlock16IN[14]; + assign Out15 = BusBlock16IN[15]; + assign Out2 = BusBlock16IN[2]; + assign Out3 = BusBlock16IN[3]; + assign Out4 = BusBlock16IN[4]; + assign Out5 = BusBlock16IN[5]; + assign Out6 = BusBlock16IN[6]; + assign Out7 = BusBlock16IN[7]; + assign Out8 = BusBlock16IN[8]; + assign Out9 = BusBlock16IN[9]; +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0_sim_netlist.vhdl b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0_sim_netlist.vhdl new file mode 100644 index 0000000..57b6015 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0_sim_netlist.vhdl @@ -0,0 +1,69 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Fri Jun 11 07:49:57 2021 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top Inverter_3lvl_BUS_16IN_1_0 -prefix +-- Inverter_3lvl_BUS_16IN_1_0_ Inverter_3lvl_BUS_16IN_0_0_sim_netlist.vhdl +-- Design : Inverter_3lvl_BUS_16IN_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Inverter_3lvl_BUS_16IN_1_0 is + port ( + BusBlock16IN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + Out0 : out STD_LOGIC; + Out1 : out STD_LOGIC; + Out2 : out STD_LOGIC; + Out3 : out STD_LOGIC; + Out4 : out STD_LOGIC; + Out5 : out STD_LOGIC; + Out6 : out STD_LOGIC; + Out7 : out STD_LOGIC; + Out8 : out STD_LOGIC; + Out9 : out STD_LOGIC; + Out10 : out STD_LOGIC; + Out11 : out STD_LOGIC; + Out12 : out STD_LOGIC; + Out13 : out STD_LOGIC; + Out14 : out STD_LOGIC; + Out15 : out STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of Inverter_3lvl_BUS_16IN_1_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of Inverter_3lvl_BUS_16IN_1_0 : entity is "Inverter_3lvl_BUS_16IN_0_0,BUS_16IN,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of Inverter_3lvl_BUS_16IN_1_0 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of Inverter_3lvl_BUS_16IN_1_0 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of Inverter_3lvl_BUS_16IN_1_0 : entity is "BUS_16IN,Vivado 2019.1"; +end Inverter_3lvl_BUS_16IN_1_0; + +architecture STRUCTURE of Inverter_3lvl_BUS_16IN_1_0 is + signal \^busblock16in\ : STD_LOGIC_VECTOR ( 15 downto 0 ); +begin + Out0 <= \^busblock16in\(0); + Out1 <= \^busblock16in\(1); + Out10 <= \^busblock16in\(10); + Out11 <= \^busblock16in\(11); + Out12 <= \^busblock16in\(12); + Out13 <= \^busblock16in\(13); + Out14 <= \^busblock16in\(14); + Out15 <= \^busblock16in\(15); + Out2 <= \^busblock16in\(2); + Out3 <= \^busblock16in\(3); + Out4 <= \^busblock16in\(4); + Out5 <= \^busblock16in\(5); + Out6 <= \^busblock16in\(6); + Out7 <= \^busblock16in\(7); + Out8 <= \^busblock16in\(8); + Out9 <= \^busblock16in\(9); + \^busblock16in\(15 downto 0) <= BusBlock16IN(15 downto 0); +end STRUCTURE; diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0_stub.v b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0_stub.v new file mode 100644 index 0000000..39e7bae --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0_stub.v @@ -0,0 +1,37 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Fri Jun 11 07:49:57 2021 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top Inverter_3lvl_BUS_16IN_1_0 -prefix +// Inverter_3lvl_BUS_16IN_1_0_ Inverter_3lvl_BUS_16IN_0_0_stub.v +// Design : Inverter_3lvl_BUS_16IN_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "BUS_16IN,Vivado 2019.1" *) +module Inverter_3lvl_BUS_16IN_1_0(BusBlock16IN, Out0, Out1, Out2, Out3, Out4, Out5, Out6, + Out7, Out8, Out9, Out10, Out11, Out12, Out13, Out14, Out15) +/* synthesis syn_black_box black_box_pad_pin="BusBlock16IN[15:0],Out0,Out1,Out2,Out3,Out4,Out5,Out6,Out7,Out8,Out9,Out10,Out11,Out12,Out13,Out14,Out15" */; + input [15:0]BusBlock16IN; + output Out0; + output Out1; + output Out2; + output Out3; + output Out4; + output Out5; + output Out6; + output Out7; + output Out8; + output Out9; + output Out10; + output Out11; + output Out12; + output Out13; + output Out14; + output Out15; +endmodule diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0_stub.vhdl b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0_stub.vhdl new file mode 100644 index 0000000..52849d6 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_1_0/Inverter_3lvl_BUS_16IN_1_0_stub.vhdl @@ -0,0 +1,46 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Fri Jun 11 07:49:57 2021 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top Inverter_3lvl_BUS_16IN_1_0 -prefix +-- Inverter_3lvl_BUS_16IN_1_0_ Inverter_3lvl_BUS_16IN_0_0_stub.vhdl +-- Design : Inverter_3lvl_BUS_16IN_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Inverter_3lvl_BUS_16IN_1_0 is + Port ( + BusBlock16IN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + Out0 : out STD_LOGIC; + Out1 : out STD_LOGIC; + Out2 : out STD_LOGIC; + Out3 : out STD_LOGIC; + Out4 : out STD_LOGIC; + Out5 : out STD_LOGIC; + Out6 : out STD_LOGIC; + Out7 : out STD_LOGIC; + Out8 : out STD_LOGIC; + Out9 : out STD_LOGIC; + Out10 : out STD_LOGIC; + Out11 : out STD_LOGIC; + Out12 : out STD_LOGIC; + Out13 : out STD_LOGIC; + Out14 : out STD_LOGIC; + Out15 : out STD_LOGIC + ); + +end Inverter_3lvl_BUS_16IN_1_0; + +architecture stub of Inverter_3lvl_BUS_16IN_1_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "BusBlock16IN[15:0],Out0,Out1,Out2,Out3,Out4,Out5,Out6,Out7,Out8,Out9,Out10,Out11,Out12,Out13,Out14,Out15"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "BUS_16IN,Vivado 2019.1"; +begin +end; diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0.dcp b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0.dcp new file mode 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Inverter_3lvl_BUS_16OUT_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + BUS_16OUT_v1_0 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0_sim_netlist.v b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0_sim_netlist.v new file mode 100644 index 0000000..ba1761b --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0_sim_netlist.v @@ -0,0 +1,319 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Thu Jun 10 15:31:51 2021 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top Inverter_3lvl_BUS_16OUT_0_0 -prefix +// Inverter_3lvl_BUS_16OUT_0_0_ Inverter_3lvl_BUS_16OUT_0_0_sim_netlist.v +// Design : Inverter_3lvl_BUS_16OUT_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module Inverter_3lvl_BUS_16OUT_0_0_BUS_16OUT + (BusBlock16OUT, + In0, + Mask, + In1, + In2, + In3, + In4, + In5, + In6, + In7, + In8, + In9, + In10, + In11, + In12, + In13, + In14, + In15); + output [15:0]BusBlock16OUT; + input In0; + input [15:0]Mask; + input In1; + input In2; + input In3; + input In4; + input In5; + input In6; + input In7; + input In8; + input In9; + input In10; + input In11; + input In12; + input In13; + input In14; + input In15; + + wire [15:0]BusBlock16OUT; + wire In0; + wire In1; + wire In10; + wire In11; + wire In12; + wire In13; + wire In14; + wire In15; + wire In2; + wire In3; + wire In4; + wire In5; + wire In6; + wire In7; + wire In8; + wire In9; + wire [15:0]Mask; + + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[0]_INST_0 + (.I0(In0), + .I1(Mask[0]), + .O(BusBlock16OUT[0])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[10]_INST_0 + (.I0(In10), + .I1(Mask[10]), + .O(BusBlock16OUT[10])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[11]_INST_0 + (.I0(In11), + .I1(Mask[11]), + .O(BusBlock16OUT[11])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[12]_INST_0 + (.I0(In12), + .I1(Mask[12]), + .O(BusBlock16OUT[12])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[13]_INST_0 + (.I0(In13), + .I1(Mask[13]), + .O(BusBlock16OUT[13])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[14]_INST_0 + (.I0(In14), + .I1(Mask[14]), + .O(BusBlock16OUT[14])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[15]_INST_0 + (.I0(In15), + .I1(Mask[15]), + .O(BusBlock16OUT[15])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[1]_INST_0 + (.I0(In1), + .I1(Mask[1]), + .O(BusBlock16OUT[1])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[2]_INST_0 + (.I0(In2), + .I1(Mask[2]), + .O(BusBlock16OUT[2])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[3]_INST_0 + (.I0(In3), + .I1(Mask[3]), + .O(BusBlock16OUT[3])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[4]_INST_0 + (.I0(In4), + .I1(Mask[4]), + .O(BusBlock16OUT[4])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[5]_INST_0 + (.I0(In5), + .I1(Mask[5]), + .O(BusBlock16OUT[5])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[6]_INST_0 + (.I0(In6), + .I1(Mask[6]), + .O(BusBlock16OUT[6])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[7]_INST_0 + (.I0(In7), + .I1(Mask[7]), + .O(BusBlock16OUT[7])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[8]_INST_0 + (.I0(In8), + .I1(Mask[8]), + .O(BusBlock16OUT[8])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[9]_INST_0 + (.I0(In9), + .I1(Mask[9]), + .O(BusBlock16OUT[9])); +endmodule + +(* CHECK_LICENSE_TYPE = "Inverter_3lvl_BUS_16OUT_0_0,BUS_16OUT,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "BUS_16OUT,Vivado 2019.1" *) +(* NotValidForBitStream *) +module Inverter_3lvl_BUS_16OUT_0_0 + (BusBlock16OUT, + In0, + In1, + In2, + In3, + In4, + In5, + In6, + In7, + In8, + In9, + In10, + In11, + In12, + In13, + In14, + In15, + Mask); + output [15:0]BusBlock16OUT; + input In0; + input In1; + input In2; + input In3; + input In4; + input In5; + input In6; + input In7; + input In8; + input In9; + input In10; + input In11; + input In12; + input In13; + input In14; + input In15; + input [15:0]Mask; + + wire [15:0]BusBlock16OUT; + wire In0; + wire In1; + wire In10; + wire In11; + wire In12; + wire In13; + wire In14; + wire In15; + wire In2; + wire In3; + wire In4; + wire In5; + wire In6; + wire In7; + wire In8; + wire In9; + wire [15:0]Mask; + + Inverter_3lvl_BUS_16OUT_0_0_BUS_16OUT U0 + (.BusBlock16OUT(BusBlock16OUT), + .In0(In0), + .In1(In1), + .In10(In10), + .In11(In11), + .In12(In12), + .In13(In13), + .In14(In14), + .In15(In15), + .In2(In2), + .In3(In3), + .In4(In4), + .In5(In5), + .In6(In6), + .In7(In7), + .In8(In8), + .In9(In9), + .Mask(Mask)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0_sim_netlist.vhdl b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0_sim_netlist.vhdl new file mode 100644 index 0000000..d002edb --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0_sim_netlist.vhdl @@ -0,0 +1,247 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Thu Jun 10 15:31:51 2021 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top Inverter_3lvl_BUS_16OUT_0_0 -prefix +-- Inverter_3lvl_BUS_16OUT_0_0_ Inverter_3lvl_BUS_16OUT_0_0_sim_netlist.vhdl +-- Design : Inverter_3lvl_BUS_16OUT_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Inverter_3lvl_BUS_16OUT_0_0_BUS_16OUT is + port ( + BusBlock16OUT : out STD_LOGIC_VECTOR ( 15 downto 0 ); + In0 : in STD_LOGIC; + Mask : in STD_LOGIC_VECTOR ( 15 downto 0 ); + In1 : in STD_LOGIC; + In2 : in STD_LOGIC; + In3 : in STD_LOGIC; + In4 : in STD_LOGIC; + In5 : in STD_LOGIC; + In6 : in STD_LOGIC; + In7 : in STD_LOGIC; + In8 : in STD_LOGIC; + In9 : in STD_LOGIC; + In10 : in STD_LOGIC; + In11 : in STD_LOGIC; + In12 : in STD_LOGIC; + In13 : in STD_LOGIC; + In14 : in STD_LOGIC; + In15 : in STD_LOGIC + ); +end Inverter_3lvl_BUS_16OUT_0_0_BUS_16OUT; + +architecture STRUCTURE of Inverter_3lvl_BUS_16OUT_0_0_BUS_16OUT is +begin +\BusBlock16OUT[0]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In0, + I1 => Mask(0), + O => BusBlock16OUT(0) + ); +\BusBlock16OUT[10]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In10, + I1 => Mask(10), + O => BusBlock16OUT(10) + ); +\BusBlock16OUT[11]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In11, + I1 => Mask(11), + O => BusBlock16OUT(11) + ); +\BusBlock16OUT[12]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In12, + I1 => Mask(12), + O => BusBlock16OUT(12) + ); +\BusBlock16OUT[13]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In13, + I1 => Mask(13), + O => BusBlock16OUT(13) + ); +\BusBlock16OUT[14]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In14, + I1 => Mask(14), + O => BusBlock16OUT(14) + ); +\BusBlock16OUT[15]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In15, + I1 => Mask(15), + O => BusBlock16OUT(15) + ); +\BusBlock16OUT[1]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In1, + I1 => Mask(1), + O => BusBlock16OUT(1) + ); +\BusBlock16OUT[2]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In2, + I1 => Mask(2), + O => BusBlock16OUT(2) + ); +\BusBlock16OUT[3]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In3, + I1 => Mask(3), + O => BusBlock16OUT(3) + ); +\BusBlock16OUT[4]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In4, + I1 => Mask(4), + O => BusBlock16OUT(4) + ); +\BusBlock16OUT[5]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In5, + I1 => Mask(5), + O => BusBlock16OUT(5) + ); +\BusBlock16OUT[6]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In6, + I1 => Mask(6), + O => BusBlock16OUT(6) + ); +\BusBlock16OUT[7]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In7, + I1 => Mask(7), + O => BusBlock16OUT(7) + ); +\BusBlock16OUT[8]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In8, + I1 => Mask(8), + O => BusBlock16OUT(8) + ); +\BusBlock16OUT[9]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In9, + I1 => Mask(9), + O => BusBlock16OUT(9) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Inverter_3lvl_BUS_16OUT_0_0 is + port ( + BusBlock16OUT : out STD_LOGIC_VECTOR ( 15 downto 0 ); + In0 : in STD_LOGIC; + In1 : in STD_LOGIC; + In2 : in STD_LOGIC; + In3 : in STD_LOGIC; + In4 : in STD_LOGIC; + In5 : in STD_LOGIC; + In6 : in STD_LOGIC; + In7 : in STD_LOGIC; + In8 : in STD_LOGIC; + In9 : in STD_LOGIC; + In10 : in STD_LOGIC; + In11 : in STD_LOGIC; + In12 : in STD_LOGIC; + In13 : in STD_LOGIC; + In14 : in STD_LOGIC; + In15 : in STD_LOGIC; + Mask : in STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of Inverter_3lvl_BUS_16OUT_0_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of Inverter_3lvl_BUS_16OUT_0_0 : entity is "Inverter_3lvl_BUS_16OUT_0_0,BUS_16OUT,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of Inverter_3lvl_BUS_16OUT_0_0 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of Inverter_3lvl_BUS_16OUT_0_0 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of Inverter_3lvl_BUS_16OUT_0_0 : entity is "BUS_16OUT,Vivado 2019.1"; +end Inverter_3lvl_BUS_16OUT_0_0; + +architecture STRUCTURE of Inverter_3lvl_BUS_16OUT_0_0 is +begin +U0: entity work.Inverter_3lvl_BUS_16OUT_0_0_BUS_16OUT + port map ( + BusBlock16OUT(15 downto 0) => BusBlock16OUT(15 downto 0), + In0 => In0, + In1 => In1, + In10 => In10, + In11 => In11, + In12 => In12, + In13 => In13, + In14 => In14, + In15 => In15, + In2 => In2, + In3 => In3, + In4 => In4, + In5 => In5, + In6 => In6, + In7 => In7, + In8 => In8, + In9 => In9, + Mask(15 downto 0) => Mask(15 downto 0) + ); +end STRUCTURE; diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0_stub.v b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0_stub.v new file mode 100644 index 0000000..a7c82f8 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0_stub.v @@ -0,0 +1,38 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Thu Jun 10 15:31:51 2021 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top Inverter_3lvl_BUS_16OUT_0_0 -prefix +// Inverter_3lvl_BUS_16OUT_0_0_ Inverter_3lvl_BUS_16OUT_0_0_stub.v +// Design : Inverter_3lvl_BUS_16OUT_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "BUS_16OUT,Vivado 2019.1" *) +module Inverter_3lvl_BUS_16OUT_0_0(BusBlock16OUT, In0, In1, In2, In3, In4, In5, In6, In7, In8, + In9, In10, In11, In12, In13, In14, In15, Mask) +/* synthesis syn_black_box black_box_pad_pin="BusBlock16OUT[15:0],In0,In1,In2,In3,In4,In5,In6,In7,In8,In9,In10,In11,In12,In13,In14,In15,Mask[15:0]" */; + output [15:0]BusBlock16OUT; + input In0; + input In1; + input In2; + input In3; + input In4; + input In5; + input In6; + input In7; + input In8; + input In9; + input In10; + input In11; + input In12; + input In13; + input In14; + input In15; + input [15:0]Mask; +endmodule diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0_stub.vhdl b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0_stub.vhdl new file mode 100644 index 0000000..1368a05 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_0/Inverter_3lvl_BUS_16OUT_0_0_stub.vhdl @@ -0,0 +1,47 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Thu Jun 10 15:31:51 2021 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top Inverter_3lvl_BUS_16OUT_0_0 -prefix +-- Inverter_3lvl_BUS_16OUT_0_0_ Inverter_3lvl_BUS_16OUT_0_0_stub.vhdl +-- Design : Inverter_3lvl_BUS_16OUT_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Inverter_3lvl_BUS_16OUT_0_0 is + Port ( + BusBlock16OUT : out STD_LOGIC_VECTOR ( 15 downto 0 ); + In0 : in STD_LOGIC; + In1 : in STD_LOGIC; + In2 : in STD_LOGIC; + In3 : in STD_LOGIC; + In4 : in STD_LOGIC; + In5 : in STD_LOGIC; + In6 : in STD_LOGIC; + In7 : in STD_LOGIC; + In8 : in STD_LOGIC; + In9 : in STD_LOGIC; + In10 : in STD_LOGIC; + In11 : in STD_LOGIC; + In12 : in STD_LOGIC; + In13 : in STD_LOGIC; + In14 : in STD_LOGIC; + In15 : in STD_LOGIC; + Mask : in STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + +end Inverter_3lvl_BUS_16OUT_0_0; + +architecture stub of Inverter_3lvl_BUS_16OUT_0_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "BusBlock16OUT[15:0],In0,In1,In2,In3,In4,In5,In6,In7,In8,In9,In10,In11,In12,In13,In14,In15,Mask[15:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "BUS_16OUT,Vivado 2019.1"; +begin +end; diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1.dcp 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a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1.xml b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1.xml index 34b87f6..873d15c 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1.xml +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1.xml @@ -95,6 +95,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:44:44 UTC 2023 + + + outputProductCRC + 9:f36a0e0b + + + @@ -375,6 +393,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + Inverter_3lvl_BUS_16OUT_0_1.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + Inverter_3lvl_BUS_16OUT_0_1_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Inverter_3lvl_BUS_16OUT_0_1_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Inverter_3lvl_BUS_16OUT_0_1_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Inverter_3lvl_BUS_16OUT_0_1_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + BUS_16OUT_v1_0 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1_sim_netlist.v b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1_sim_netlist.v new file mode 100644 index 0000000..18e6a07 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1_sim_netlist.v @@ -0,0 +1,319 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Thu Jun 10 15:31:51 2021 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top Inverter_3lvl_BUS_16OUT_0_1 -prefix +// Inverter_3lvl_BUS_16OUT_0_1_ Inverter_3lvl_BUS_16OUT_0_0_sim_netlist.v +// Design : Inverter_3lvl_BUS_16OUT_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module Inverter_3lvl_BUS_16OUT_0_1_BUS_16OUT + (BusBlock16OUT, + In0, + Mask, + In1, + In2, + In3, + In4, + In5, + In6, + In7, + In8, + In9, + In10, + In11, + In12, + In13, + In14, + In15); + output [15:0]BusBlock16OUT; + input In0; + input [15:0]Mask; + input In1; + input In2; + input In3; + input In4; + input In5; + input In6; + input In7; + input In8; + input In9; + input In10; + input In11; + input In12; + input In13; + input In14; + input In15; + + wire [15:0]BusBlock16OUT; + wire In0; + wire In1; + wire In10; + wire In11; + wire In12; + wire In13; + wire In14; + wire In15; + wire In2; + wire In3; + wire In4; + wire In5; + wire In6; + wire In7; + wire In8; + wire In9; + wire [15:0]Mask; + + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[0]_INST_0 + (.I0(In0), + .I1(Mask[0]), + .O(BusBlock16OUT[0])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[10]_INST_0 + (.I0(In10), + .I1(Mask[10]), + .O(BusBlock16OUT[10])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[11]_INST_0 + (.I0(In11), + .I1(Mask[11]), + .O(BusBlock16OUT[11])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[12]_INST_0 + (.I0(In12), + .I1(Mask[12]), + .O(BusBlock16OUT[12])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[13]_INST_0 + (.I0(In13), + .I1(Mask[13]), + .O(BusBlock16OUT[13])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[14]_INST_0 + (.I0(In14), + .I1(Mask[14]), + .O(BusBlock16OUT[14])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[15]_INST_0 + (.I0(In15), + .I1(Mask[15]), + .O(BusBlock16OUT[15])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[1]_INST_0 + (.I0(In1), + .I1(Mask[1]), + .O(BusBlock16OUT[1])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[2]_INST_0 + (.I0(In2), + .I1(Mask[2]), + .O(BusBlock16OUT[2])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[3]_INST_0 + (.I0(In3), + .I1(Mask[3]), + .O(BusBlock16OUT[3])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[4]_INST_0 + (.I0(In4), + .I1(Mask[4]), + .O(BusBlock16OUT[4])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[5]_INST_0 + (.I0(In5), + .I1(Mask[5]), + .O(BusBlock16OUT[5])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[6]_INST_0 + (.I0(In6), + .I1(Mask[6]), + .O(BusBlock16OUT[6])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[7]_INST_0 + (.I0(In7), + .I1(Mask[7]), + .O(BusBlock16OUT[7])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[8]_INST_0 + (.I0(In8), + .I1(Mask[8]), + .O(BusBlock16OUT[8])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[9]_INST_0 + (.I0(In9), + .I1(Mask[9]), + .O(BusBlock16OUT[9])); +endmodule + +(* CHECK_LICENSE_TYPE = "Inverter_3lvl_BUS_16OUT_0_0,BUS_16OUT,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "BUS_16OUT,Vivado 2019.1" *) +(* NotValidForBitStream *) +module Inverter_3lvl_BUS_16OUT_0_1 + (BusBlock16OUT, + In0, + In1, + In2, + In3, + In4, + In5, + In6, + In7, + In8, + In9, + In10, + In11, + In12, + In13, + In14, + In15, + Mask); + output [15:0]BusBlock16OUT; + input In0; + input In1; + input In2; + input In3; + input In4; + input In5; + input In6; + input In7; + input In8; + input In9; + input In10; + input In11; + input In12; + input In13; + input In14; + input In15; + input [15:0]Mask; + + wire [15:0]BusBlock16OUT; + wire In0; + wire In1; + wire In10; + wire In11; + wire In12; + wire In13; + wire In14; + wire In15; + wire In2; + wire In3; + wire In4; + wire In5; + wire In6; + wire In7; + wire In8; + wire In9; + wire [15:0]Mask; + + Inverter_3lvl_BUS_16OUT_0_1_BUS_16OUT U0 + (.BusBlock16OUT(BusBlock16OUT), + .In0(In0), + .In1(In1), + .In10(In10), + .In11(In11), + .In12(In12), + .In13(In13), + .In14(In14), + .In15(In15), + .In2(In2), + .In3(In3), + .In4(In4), + .In5(In5), + .In6(In6), + .In7(In7), + .In8(In8), + .In9(In9), + .Mask(Mask)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1_sim_netlist.vhdl b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1_sim_netlist.vhdl new file mode 100644 index 0000000..5c7c0a1 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1_sim_netlist.vhdl @@ -0,0 +1,247 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Thu Jun 10 15:31:51 2021 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top Inverter_3lvl_BUS_16OUT_0_1 -prefix +-- Inverter_3lvl_BUS_16OUT_0_1_ Inverter_3lvl_BUS_16OUT_0_0_sim_netlist.vhdl +-- Design : Inverter_3lvl_BUS_16OUT_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Inverter_3lvl_BUS_16OUT_0_1_BUS_16OUT is + port ( + BusBlock16OUT : out STD_LOGIC_VECTOR ( 15 downto 0 ); + In0 : in STD_LOGIC; + Mask : in STD_LOGIC_VECTOR ( 15 downto 0 ); + In1 : in STD_LOGIC; + In2 : in STD_LOGIC; + In3 : in STD_LOGIC; + In4 : in STD_LOGIC; + In5 : in STD_LOGIC; + In6 : in STD_LOGIC; + In7 : in STD_LOGIC; + In8 : in STD_LOGIC; + In9 : in STD_LOGIC; + In10 : in STD_LOGIC; + In11 : in STD_LOGIC; + In12 : in STD_LOGIC; + In13 : in STD_LOGIC; + In14 : in STD_LOGIC; + In15 : in STD_LOGIC + ); +end Inverter_3lvl_BUS_16OUT_0_1_BUS_16OUT; + +architecture STRUCTURE of Inverter_3lvl_BUS_16OUT_0_1_BUS_16OUT is +begin +\BusBlock16OUT[0]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In0, + I1 => Mask(0), + O => BusBlock16OUT(0) + ); +\BusBlock16OUT[10]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In10, + I1 => Mask(10), + O => BusBlock16OUT(10) + ); +\BusBlock16OUT[11]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In11, + I1 => Mask(11), + O => BusBlock16OUT(11) + ); +\BusBlock16OUT[12]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In12, + I1 => Mask(12), + O => BusBlock16OUT(12) + ); +\BusBlock16OUT[13]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In13, + I1 => Mask(13), + O => BusBlock16OUT(13) + ); +\BusBlock16OUT[14]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In14, + I1 => Mask(14), + O => BusBlock16OUT(14) + ); +\BusBlock16OUT[15]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In15, + I1 => Mask(15), + O => BusBlock16OUT(15) + ); +\BusBlock16OUT[1]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In1, + I1 => Mask(1), + O => BusBlock16OUT(1) + ); +\BusBlock16OUT[2]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In2, + I1 => Mask(2), + O => BusBlock16OUT(2) + ); +\BusBlock16OUT[3]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In3, + I1 => Mask(3), + O => BusBlock16OUT(3) + ); +\BusBlock16OUT[4]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In4, + I1 => Mask(4), + O => BusBlock16OUT(4) + ); +\BusBlock16OUT[5]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In5, + I1 => Mask(5), + O => BusBlock16OUT(5) + ); +\BusBlock16OUT[6]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In6, + I1 => Mask(6), + O => BusBlock16OUT(6) + ); +\BusBlock16OUT[7]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In7, + I1 => Mask(7), + O => BusBlock16OUT(7) + ); +\BusBlock16OUT[8]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In8, + I1 => Mask(8), + O => BusBlock16OUT(8) + ); +\BusBlock16OUT[9]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In9, + I1 => Mask(9), + O => BusBlock16OUT(9) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Inverter_3lvl_BUS_16OUT_0_1 is + port ( + BusBlock16OUT : out STD_LOGIC_VECTOR ( 15 downto 0 ); + In0 : in STD_LOGIC; + In1 : in STD_LOGIC; + In2 : in STD_LOGIC; + In3 : in STD_LOGIC; + In4 : in STD_LOGIC; + In5 : in STD_LOGIC; + In6 : in STD_LOGIC; + In7 : in STD_LOGIC; + In8 : in STD_LOGIC; + In9 : in STD_LOGIC; + In10 : in STD_LOGIC; + In11 : in STD_LOGIC; + In12 : in STD_LOGIC; + In13 : in STD_LOGIC; + In14 : in STD_LOGIC; + In15 : in STD_LOGIC; + Mask : in STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of Inverter_3lvl_BUS_16OUT_0_1 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of Inverter_3lvl_BUS_16OUT_0_1 : entity is "Inverter_3lvl_BUS_16OUT_0_0,BUS_16OUT,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of Inverter_3lvl_BUS_16OUT_0_1 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of Inverter_3lvl_BUS_16OUT_0_1 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of Inverter_3lvl_BUS_16OUT_0_1 : entity is "BUS_16OUT,Vivado 2019.1"; +end Inverter_3lvl_BUS_16OUT_0_1; + +architecture STRUCTURE of Inverter_3lvl_BUS_16OUT_0_1 is +begin +U0: entity work.Inverter_3lvl_BUS_16OUT_0_1_BUS_16OUT + port map ( + BusBlock16OUT(15 downto 0) => BusBlock16OUT(15 downto 0), + In0 => In0, + In1 => In1, + In10 => In10, + In11 => In11, + In12 => In12, + In13 => In13, + In14 => In14, + In15 => In15, + In2 => In2, + In3 => In3, + In4 => In4, + In5 => In5, + In6 => In6, + In7 => In7, + In8 => In8, + In9 => In9, + Mask(15 downto 0) => Mask(15 downto 0) + ); +end STRUCTURE; diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1_stub.v b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1_stub.v new file mode 100644 index 0000000..4ec9a39 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1_stub.v @@ -0,0 +1,38 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Thu Jun 10 15:31:51 2021 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top Inverter_3lvl_BUS_16OUT_0_1 -prefix +// Inverter_3lvl_BUS_16OUT_0_1_ Inverter_3lvl_BUS_16OUT_0_0_stub.v +// Design : Inverter_3lvl_BUS_16OUT_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "BUS_16OUT,Vivado 2019.1" *) +module Inverter_3lvl_BUS_16OUT_0_1(BusBlock16OUT, In0, In1, In2, In3, In4, In5, In6, In7, In8, + In9, In10, In11, In12, In13, In14, In15, Mask) +/* synthesis syn_black_box black_box_pad_pin="BusBlock16OUT[15:0],In0,In1,In2,In3,In4,In5,In6,In7,In8,In9,In10,In11,In12,In13,In14,In15,Mask[15:0]" */; + output [15:0]BusBlock16OUT; + input In0; + input In1; + input In2; + input In3; + input In4; + input In5; + input In6; + input In7; + input In8; + input In9; + input In10; + input In11; + input In12; + input In13; + input In14; + input In15; + input [15:0]Mask; +endmodule diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1_stub.vhdl b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1_stub.vhdl new file mode 100644 index 0000000..58de552 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_0_1/Inverter_3lvl_BUS_16OUT_0_1_stub.vhdl @@ -0,0 +1,47 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Thu Jun 10 15:31:51 2021 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top Inverter_3lvl_BUS_16OUT_0_1 -prefix +-- Inverter_3lvl_BUS_16OUT_0_1_ Inverter_3lvl_BUS_16OUT_0_0_stub.vhdl +-- Design : Inverter_3lvl_BUS_16OUT_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Inverter_3lvl_BUS_16OUT_0_1 is + Port ( + BusBlock16OUT : out STD_LOGIC_VECTOR ( 15 downto 0 ); + In0 : in STD_LOGIC; + In1 : in STD_LOGIC; + In2 : in STD_LOGIC; + In3 : in STD_LOGIC; + In4 : in STD_LOGIC; + In5 : in STD_LOGIC; + In6 : in STD_LOGIC; + In7 : in STD_LOGIC; + In8 : in STD_LOGIC; + In9 : in STD_LOGIC; + In10 : in STD_LOGIC; + In11 : in STD_LOGIC; + In12 : in STD_LOGIC; + In13 : in STD_LOGIC; + In14 : in STD_LOGIC; + In15 : in STD_LOGIC; + Mask : in STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + +end Inverter_3lvl_BUS_16OUT_0_1; + +architecture stub of Inverter_3lvl_BUS_16OUT_0_1 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "BusBlock16OUT[15:0],In0,In1,In2,In3,In4,In5,In6,In7,In8,In9,In10,In11,In12,In13,In14,In15,Mask[15:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "BUS_16OUT,Vivado 2019.1"; +begin +end; diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_1_0.dcp b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_1_0.dcp new file mode 100644 index 0000000000000000000000000000000000000000..584fcfeaa4c7831b7bd0d27bea4726f200b75fab GIT binary patch literal 8894 zcma)?1yCHz8mJd{m*DR1AxMA_+}%QOcXxMRoZwDycW05{?tuh%4X$ri0s#$sY@x}$63RM3R`lC76_k=kgs!VPIX=G#8pR(a-x zFneG^RItRwa|4r5v3lUgiV3R&o7c>=H8C!07)>?tOL9{H&H>(L8%{wVyDOhgB;Ks@ zv&Q-ks1xq-Et<;Yc{CDWrA1zw9F>QhEdU}~zRNB8^R(sbGycgsPkeW_P1MPJSBukh zY@*gBrk?+e4mK46qC*swX2GLz(>mlV8#&tpfBU}Re`PLWO;E)sxzEF{Ld!HQF9I+vYhmhY zO6Ah9x%d*Fp12i7n(6|S_^e@Zt@(S zKe@t7EFyBZRt5zdAo&VOtG?PB%dYlcibzfSE^U!2hD<7ZQ zm!?_fk#GCui7OO@`!agi!G~=&?}k%i--y4{MHpfV#Zv)my@ax~&#hnZ!ylytf-nfy zx&>v)|Hpbjk$5`qtN~UDpY`UaFuBa*bHePC0dY?epgL+I6VtdWjDhD4X0d^&i9Zl_ zecjwK$2U6^anSA&l1ZMIDPn4tTpx6SydED?UCw0L$Dg9={{3BGR4+D_MB?-nSwkefjsf8fY&B&aB;aT5k~~*7wvleCz<4yVJh2fA%{hhma=|k z8i%9fhzxbRDHUp4&WP1Lh3^MwxeOO1iSB2|5js;2Nm+!6x2>~0#H&rJx`ea!S)E3l zSt66FF4nT$t~a*hL}@-M^OfwKE6e=cPE&5OY9)hL7G`HNvWs}aYN-om)2BH?Hmf0J zEaL{#t`j*;R(NGBHa+=*ylyKg1|p*KMXgLLr}wk2vOxzk%7x46*Jl}IA77^PhU);K zk#=3%ok88R#44YPlv_|^K+l2^$0fKhsuD`UYE0PMpUqxW;yx5`qAniG5@D|8&5}N$ z#_waOKuKcUvj?PY3NxXQi7^dA8%99Ya{FUXV_=0dqZXDx6ozZ0348Vla}~q8g@!Aj z$K3a3k!;qB8adkUh2G6grQv^%Ab-#La7Y)~k`R*58r`P^{zeZb>{zzQ0KQ0yL&H2g z_yYTRC2SFNq!7mNe2ziL+~l>M;+xGH2GD9e|0jYknS++w>+UFz8GM&S7IxJb6ZO1# z(53DwZ89@0yGc-U8$A(-ctqBMsHPD?rJw-HH^``SYS{vC<^8=g8$B3=uy87ILAsmz zNA^D@ae|;+$SEfCG&ZMZ!EJo7aBWRoVZITfdSOr!H0AFUHC`{VGcjQ#!XPD#%IT4> z=#ZtcVfnCmA$8>fv>g&lex}g1fG-a}%jH!|K%|HfSe9~~A$FvPR7q=mYsi*oL})CQ z2h}NxG8gUYK5EoYsak5LSbi;^ zmgEul@YnHb@$*zD;}DS8vhqAU!NNL_T15hsCbu!;g$WdnT6IC`PLo-$aa)flXT2v$J= ztC0OxkqlKGb^zXGlkJ3DgRi$d16BDlX@woI75py)Z#{DZr}-fmh#RnSdDUr!J;*%; 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All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Thu Jun 10 15:31:51 2021 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top Inverter_3lvl_BUS_16OUT_1_0 -prefix +// Inverter_3lvl_BUS_16OUT_1_0_ Inverter_3lvl_BUS_16OUT_0_0_sim_netlist.v +// Design : Inverter_3lvl_BUS_16OUT_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module Inverter_3lvl_BUS_16OUT_1_0_BUS_16OUT + (BusBlock16OUT, + In0, + Mask, + In1, + In2, + In3, + In4, + In5, + In6, + In7, + In8, + In9, + In10, + In11, + In12, + In13, + In14, + In15); + output [15:0]BusBlock16OUT; + input In0; + input [15:0]Mask; + input In1; + input In2; + input In3; + input In4; + input In5; + input In6; + input In7; + input In8; + input In9; + input In10; + input In11; + input In12; + input In13; + input In14; + input In15; + + wire [15:0]BusBlock16OUT; + wire In0; + wire In1; + wire In10; + wire In11; + wire In12; + wire In13; + wire In14; + wire In15; + wire In2; + wire In3; + wire In4; + wire In5; + wire In6; + wire In7; + wire In8; + wire In9; + wire [15:0]Mask; + + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[0]_INST_0 + (.I0(In0), + .I1(Mask[0]), + .O(BusBlock16OUT[0])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[10]_INST_0 + (.I0(In10), + .I1(Mask[10]), + .O(BusBlock16OUT[10])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[11]_INST_0 + (.I0(In11), + .I1(Mask[11]), + .O(BusBlock16OUT[11])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[12]_INST_0 + (.I0(In12), + .I1(Mask[12]), + .O(BusBlock16OUT[12])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[13]_INST_0 + (.I0(In13), + .I1(Mask[13]), + .O(BusBlock16OUT[13])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[14]_INST_0 + (.I0(In14), + .I1(Mask[14]), + .O(BusBlock16OUT[14])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[15]_INST_0 + (.I0(In15), + .I1(Mask[15]), + .O(BusBlock16OUT[15])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[1]_INST_0 + (.I0(In1), + .I1(Mask[1]), + .O(BusBlock16OUT[1])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[2]_INST_0 + (.I0(In2), + .I1(Mask[2]), + .O(BusBlock16OUT[2])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[3]_INST_0 + (.I0(In3), + .I1(Mask[3]), + .O(BusBlock16OUT[3])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[4]_INST_0 + (.I0(In4), + .I1(Mask[4]), + .O(BusBlock16OUT[4])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[5]_INST_0 + (.I0(In5), + .I1(Mask[5]), + .O(BusBlock16OUT[5])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[6]_INST_0 + (.I0(In6), + .I1(Mask[6]), + .O(BusBlock16OUT[6])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[7]_INST_0 + (.I0(In7), + .I1(Mask[7]), + .O(BusBlock16OUT[7])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[8]_INST_0 + (.I0(In8), + .I1(Mask[8]), + .O(BusBlock16OUT[8])); + LUT2 #( + .INIT(4'hE)) + \BusBlock16OUT[9]_INST_0 + (.I0(In9), + .I1(Mask[9]), + .O(BusBlock16OUT[9])); +endmodule + +(* CHECK_LICENSE_TYPE = "Inverter_3lvl_BUS_16OUT_0_0,BUS_16OUT,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "BUS_16OUT,Vivado 2019.1" *) +(* NotValidForBitStream *) +module Inverter_3lvl_BUS_16OUT_1_0 + (BusBlock16OUT, + In0, + In1, + In2, + In3, + In4, + In5, + In6, + In7, + In8, + In9, + In10, + In11, + In12, + In13, + In14, + In15, + Mask); + output [15:0]BusBlock16OUT; + input In0; + input In1; + input In2; + input In3; + input In4; + input In5; + input In6; + input In7; + input In8; + input In9; + input In10; + input In11; + input In12; + input In13; + input In14; + input In15; + input [15:0]Mask; + + wire [15:0]BusBlock16OUT; + wire In0; + wire In1; + wire In10; + wire In11; + wire In12; + wire In13; + wire In14; + wire In15; + wire In2; + wire In3; + wire In4; + wire In5; + wire In6; + wire In7; + wire In8; + wire In9; + wire [15:0]Mask; + + Inverter_3lvl_BUS_16OUT_1_0_BUS_16OUT U0 + (.BusBlock16OUT(BusBlock16OUT), + .In0(In0), + .In1(In1), + .In10(In10), + .In11(In11), + .In12(In12), + .In13(In13), + .In14(In14), + .In15(In15), + .In2(In2), + .In3(In3), + .In4(In4), + .In5(In5), + .In6(In6), + .In7(In7), + .In8(In8), + .In9(In9), + .Mask(Mask)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_1_0_sim_netlist.vhdl b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_1_0_sim_netlist.vhdl new file mode 100644 index 0000000..f9633b5 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_1_0_sim_netlist.vhdl @@ -0,0 +1,247 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Thu Jun 10 15:31:51 2021 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top Inverter_3lvl_BUS_16OUT_1_0 -prefix +-- Inverter_3lvl_BUS_16OUT_1_0_ Inverter_3lvl_BUS_16OUT_0_0_sim_netlist.vhdl +-- Design : Inverter_3lvl_BUS_16OUT_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Inverter_3lvl_BUS_16OUT_1_0_BUS_16OUT is + port ( + BusBlock16OUT : out STD_LOGIC_VECTOR ( 15 downto 0 ); + In0 : in STD_LOGIC; + Mask : in STD_LOGIC_VECTOR ( 15 downto 0 ); + In1 : in STD_LOGIC; + In2 : in STD_LOGIC; + In3 : in STD_LOGIC; + In4 : in STD_LOGIC; + In5 : in STD_LOGIC; + In6 : in STD_LOGIC; + In7 : in STD_LOGIC; + In8 : in STD_LOGIC; + In9 : in STD_LOGIC; + In10 : in STD_LOGIC; + In11 : in STD_LOGIC; + In12 : in STD_LOGIC; + In13 : in STD_LOGIC; + In14 : in STD_LOGIC; + In15 : in STD_LOGIC + ); +end Inverter_3lvl_BUS_16OUT_1_0_BUS_16OUT; + +architecture STRUCTURE of Inverter_3lvl_BUS_16OUT_1_0_BUS_16OUT is +begin +\BusBlock16OUT[0]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In0, + I1 => Mask(0), + O => BusBlock16OUT(0) + ); +\BusBlock16OUT[10]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In10, + I1 => Mask(10), + O => BusBlock16OUT(10) + ); +\BusBlock16OUT[11]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In11, + I1 => Mask(11), + O => BusBlock16OUT(11) + ); +\BusBlock16OUT[12]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In12, + I1 => Mask(12), + O => BusBlock16OUT(12) + ); +\BusBlock16OUT[13]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In13, + I1 => Mask(13), + O => BusBlock16OUT(13) + ); +\BusBlock16OUT[14]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In14, + I1 => Mask(14), + O => BusBlock16OUT(14) + ); +\BusBlock16OUT[15]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In15, + I1 => Mask(15), + O => BusBlock16OUT(15) + ); +\BusBlock16OUT[1]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In1, + I1 => Mask(1), + O => BusBlock16OUT(1) + ); +\BusBlock16OUT[2]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In2, + I1 => Mask(2), + O => BusBlock16OUT(2) + ); +\BusBlock16OUT[3]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In3, + I1 => Mask(3), + O => BusBlock16OUT(3) + ); +\BusBlock16OUT[4]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In4, + I1 => Mask(4), + O => BusBlock16OUT(4) + ); +\BusBlock16OUT[5]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In5, + I1 => Mask(5), + O => BusBlock16OUT(5) + ); +\BusBlock16OUT[6]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In6, + I1 => Mask(6), + O => BusBlock16OUT(6) + ); +\BusBlock16OUT[7]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In7, + I1 => Mask(7), + O => BusBlock16OUT(7) + ); +\BusBlock16OUT[8]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In8, + I1 => Mask(8), + O => BusBlock16OUT(8) + ); +\BusBlock16OUT[9]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => In9, + I1 => Mask(9), + O => BusBlock16OUT(9) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Inverter_3lvl_BUS_16OUT_1_0 is + port ( + BusBlock16OUT : out STD_LOGIC_VECTOR ( 15 downto 0 ); + In0 : in STD_LOGIC; + In1 : in STD_LOGIC; + In2 : in STD_LOGIC; + In3 : in STD_LOGIC; + In4 : in STD_LOGIC; + In5 : in STD_LOGIC; + In6 : in STD_LOGIC; + In7 : in STD_LOGIC; + In8 : in STD_LOGIC; + In9 : in STD_LOGIC; + In10 : in STD_LOGIC; + In11 : in STD_LOGIC; + In12 : in STD_LOGIC; + In13 : in STD_LOGIC; + In14 : in STD_LOGIC; + In15 : in STD_LOGIC; + Mask : in STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of Inverter_3lvl_BUS_16OUT_1_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of Inverter_3lvl_BUS_16OUT_1_0 : entity is "Inverter_3lvl_BUS_16OUT_0_0,BUS_16OUT,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of Inverter_3lvl_BUS_16OUT_1_0 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of Inverter_3lvl_BUS_16OUT_1_0 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of Inverter_3lvl_BUS_16OUT_1_0 : entity is "BUS_16OUT,Vivado 2019.1"; +end Inverter_3lvl_BUS_16OUT_1_0; + +architecture STRUCTURE of Inverter_3lvl_BUS_16OUT_1_0 is +begin +U0: entity work.Inverter_3lvl_BUS_16OUT_1_0_BUS_16OUT + port map ( + BusBlock16OUT(15 downto 0) => BusBlock16OUT(15 downto 0), + In0 => In0, + In1 => In1, + In10 => In10, + In11 => In11, + In12 => In12, + In13 => In13, + In14 => In14, + In15 => In15, + In2 => In2, + In3 => In3, + In4 => In4, + In5 => In5, + In6 => In6, + In7 => In7, + In8 => In8, + In9 => In9, + Mask(15 downto 0) => Mask(15 downto 0) + ); +end STRUCTURE; diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_1_0_stub.v b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_1_0_stub.v new file mode 100644 index 0000000..8cf4a38 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_1_0_stub.v @@ -0,0 +1,38 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Thu Jun 10 15:31:51 2021 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top Inverter_3lvl_BUS_16OUT_1_0 -prefix +// Inverter_3lvl_BUS_16OUT_1_0_ Inverter_3lvl_BUS_16OUT_0_0_stub.v +// Design : Inverter_3lvl_BUS_16OUT_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "BUS_16OUT,Vivado 2019.1" *) +module Inverter_3lvl_BUS_16OUT_1_0(BusBlock16OUT, In0, In1, In2, In3, In4, In5, In6, In7, In8, + In9, In10, In11, In12, In13, In14, In15, Mask) +/* synthesis syn_black_box black_box_pad_pin="BusBlock16OUT[15:0],In0,In1,In2,In3,In4,In5,In6,In7,In8,In9,In10,In11,In12,In13,In14,In15,Mask[15:0]" */; + output [15:0]BusBlock16OUT; + input In0; + input In1; + input In2; + input In3; + input In4; + input In5; + input In6; + input In7; + input In8; + input In9; + input In10; + input In11; + input In12; + input In13; + input In14; + input In15; + input [15:0]Mask; +endmodule diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_1_0_stub.vhdl b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_1_0_stub.vhdl new file mode 100644 index 0000000..0e658fb --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16OUT_1_0/Inverter_3lvl_BUS_16OUT_1_0_stub.vhdl @@ -0,0 +1,47 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Thu Jun 10 15:31:51 2021 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top Inverter_3lvl_BUS_16OUT_1_0 -prefix +-- Inverter_3lvl_BUS_16OUT_1_0_ Inverter_3lvl_BUS_16OUT_0_0_stub.vhdl +-- Design : Inverter_3lvl_BUS_16OUT_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Inverter_3lvl_BUS_16OUT_1_0 is + Port ( + BusBlock16OUT : out STD_LOGIC_VECTOR ( 15 downto 0 ); + In0 : in STD_LOGIC; + In1 : in STD_LOGIC; + In2 : in STD_LOGIC; + In3 : in STD_LOGIC; + In4 : in STD_LOGIC; + In5 : in STD_LOGIC; + In6 : in STD_LOGIC; + In7 : in STD_LOGIC; + In8 : in STD_LOGIC; + In9 : in STD_LOGIC; + In10 : in STD_LOGIC; + In11 : in STD_LOGIC; + In12 : in STD_LOGIC; + In13 : in STD_LOGIC; + In14 : in STD_LOGIC; + In15 : in STD_LOGIC; + Mask : in STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + +end Inverter_3lvl_BUS_16OUT_1_0; + +architecture stub of Inverter_3lvl_BUS_16OUT_1_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "BusBlock16OUT[15:0],In0,In1,In2,In3,In4,In5,In6,In7,In8,In9,In10,In11,In12,In13,In14,In15,Mask[15:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "BUS_16OUT,Vivado 2019.1"; +begin +end; diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0.dcp b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0.dcp 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zv@H$h9%9kU{X>~rzo|Lo9nQYaxQMvwzftOSK+EOa z&}FNV&JPW3CSrpzSMcz!LZQ=8nvAbTe|Fvp-M^Mm<27?P5+C#`!jC$AjCu>mxHQAH zO1>HNN8i_bMHrgG zB~jfc$#p#v)L8NUUviK2v7C-`mth?14d&yC962wh)i%JN!gxXwOx{O4M@BPyIY*J` zF$LXR&$j~u^Eat-YhfSh3f(;e5w2ENlv%8uQ-GgdXMKFFWQ_e~%Eq_)r_gLK6f$^n zz4qQQm~g^-+Oule%+HGr_vZ|tR3XE#dSWwEhW&^Mia|`8s4o9C>#+!`6d9z z*gCwBnd|1+tY#Qpa?2edaOAQhM7;gd$&m*#s`HPF4+_q-Sk||s8mSg1X($=K($9J% z9vPWKZvCK*G>32ipu53w7tqmbw^CC=Jo?Q908DiD0OJ33JJ>6L>ger;sb4S#AB4d> ztN8@`I3wW}I|p!Qbr{CogPqkw?=rFitx~`$v26~P9TpwD!Y(W?KQx{lhVNxX=YZDg zpxp1mwt>~rMy9*M@b0ectkIscd?BFiZLn^SQrl%m7}R`s7A6o!z@ssN>_n0&Dj^QM z#|L0+mHd~tv#XBo+MO8a>FSSRr?KY}*=FtNOZVPYADCH$oyDGs + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:44:44 UTC 2023 + + + outputProductCRC + 9:78cebd63 + + + @@ -407,6 +425,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + Inverter_3lvl_P0N_3lvl_0_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_0_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_0_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_0_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + P0N_3lvl_v1_0 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0_sim_netlist.v b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0_sim_netlist.v similarity index 99% rename from LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0_sim_netlist.v rename to LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0_sim_netlist.v index f48dbf2..997c58f 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0_sim_netlist.v +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0_sim_netlist.v @@ -1,21 +1,21 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 -// Date : Fri Jun 11 07:49:59 2021 +// Date : Fri Jun 11 07:49:57 2021 // Host : STAS-W10 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_0_sim_netlist.v -// Design : Inverter_3lvl_P0N_3lvl_0_0 +// Command : write_verilog -force -mode funcsim -rename_top Inverter_3lvl_P0N_3lvl_0_0 -prefix +// Inverter_3lvl_P0N_3lvl_0_0_ Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.v +// Design : Inverter_3lvl_P0N_3lvl_0_4 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. // Device : xc7z020clg484-3 // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps -(* CHECK_LICENSE_TYPE = "Inverter_3lvl_P0N_3lvl_0_0,P0N_3lvl,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* CHECK_LICENSE_TYPE = "Inverter_3lvl_P0N_3lvl_0_4,P0N_3lvl,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) (* x_core_info = "P0N_3lvl,Vivado 2019.1" *) (* NotValidForBitStream *) -module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix +module Inverter_3lvl_P0N_3lvl_0_0 (externalCLK, ready, reset, @@ -63,7 +63,7 @@ module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix wire ready; wire reset; - decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_P0N_3lvl U0 + Inverter_3lvl_P0N_3lvl_0_0_P0N_3lvl U0 (.PWM_out_0(PWM_out_0), .PWM_out_1(PWM_out_1), .PWM_out_2(PWM_out_2), @@ -81,7 +81,7 @@ module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix .reset(reset)); endmodule -module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_P0N_3lvl +module Inverter_3lvl_P0N_3lvl_0_0_P0N_3lvl (minTimeEr_reg_0, PWM_out_0, PWM_out_1, diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0_sim_netlist.vhdl b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0_sim_netlist.vhdl similarity index 99% rename from LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0_sim_netlist.vhdl rename to LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0_sim_netlist.vhdl index f7f2d23..d7c5ab5 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0_sim_netlist.vhdl +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0_sim_netlist.vhdl @@ -1,11 +1,11 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 --- Date : Fri Jun 11 07:49:59 2021 +-- Date : Fri Jun 11 07:49:57 2021 -- Host : STAS-W10 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix --- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_0_sim_netlist.vhdl --- Design : Inverter_3lvl_P0N_3lvl_0_0 +-- Command : write_vhdl -force -mode funcsim -rename_top Inverter_3lvl_P0N_3lvl_0_0 -prefix +-- Inverter_3lvl_P0N_3lvl_0_0_ Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.vhdl +-- Design : Inverter_3lvl_P0N_3lvl_0_4 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-3 @@ -14,7 +14,7 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_P0N_3lvl is +entity Inverter_3lvl_P0N_3lvl_0_0_P0N_3lvl is port ( minTimeEr_reg_0 : out STD_LOGIC; PWM_out_0 : out STD_LOGIC; @@ -32,9 +32,9 @@ entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_P0N_3lvl is deadTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); minTime : in STD_LOGIC_VECTOR ( 31 downto 0 ) ); -end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_P0N_3lvl; +end Inverter_3lvl_P0N_3lvl_0_0_P0N_3lvl; -architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_P0N_3lvl is +architecture STRUCTURE of Inverter_3lvl_P0N_3lvl_0_0_P0N_3lvl is signal \FSM_onehot_lineconfig[0]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_lineconfig[0]_i_2_n_0\ : STD_LOGIC; signal \FSM_onehot_lineconfig[1]_i_1_n_0\ : STD_LOGIC; @@ -4126,7 +4126,7 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +entity Inverter_3lvl_P0N_3lvl_0_0 is port ( externalCLK : in STD_LOGIC; ready : in STD_LOGIC; @@ -4145,24 +4145,24 @@ entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is PWM_out_3 : out STD_LOGIC ); attribute NotValidForBitStream : boolean; - attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; + attribute NotValidForBitStream of Inverter_3lvl_P0N_3lvl_0_0 : entity is true; attribute CHECK_LICENSE_TYPE : string; - attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "Inverter_3lvl_P0N_3lvl_0_0,P0N_3lvl,{}"; + attribute CHECK_LICENSE_TYPE of Inverter_3lvl_P0N_3lvl_0_0 : entity is "Inverter_3lvl_P0N_3lvl_0_4,P0N_3lvl,{}"; attribute downgradeipidentifiedwarnings : string; - attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; + attribute downgradeipidentifiedwarnings of Inverter_3lvl_P0N_3lvl_0_0 : entity is "yes"; attribute ip_definition_source : string; - attribute ip_definition_source of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "package_project"; + attribute ip_definition_source of Inverter_3lvl_P0N_3lvl_0_0 : entity is "package_project"; attribute x_core_info : string; - attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "P0N_3lvl,Vivado 2019.1"; -end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + attribute x_core_info of Inverter_3lvl_P0N_3lvl_0_0 : entity is "P0N_3lvl,Vivado 2019.1"; +end Inverter_3lvl_P0N_3lvl_0_0; -architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +architecture STRUCTURE of Inverter_3lvl_P0N_3lvl_0_0 is attribute x_interface_info : string; attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; attribute x_interface_parameter : string; attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; begin -U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_P0N_3lvl +U0: entity work.Inverter_3lvl_P0N_3lvl_0_0_P0N_3lvl port map ( PWM_out_0 => PWM_out_0, PWM_out_1 => PWM_out_1, diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0_stub.v b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0_stub.v similarity index 81% rename from LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0_stub.v rename to LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0_stub.v index c11f89a..a6ffbae 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0_stub.v +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0_stub.v @@ -1,11 +1,11 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 -// Date : Fri Jun 11 07:49:59 2021 +// Date : Fri Jun 11 07:49:57 2021 // Host : STAS-W10 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_0_stub.v -// Design : Inverter_3lvl_P0N_3lvl_0_0 +// Command : write_verilog -force -mode synth_stub -rename_top Inverter_3lvl_P0N_3lvl_0_0 -prefix +// Inverter_3lvl_P0N_3lvl_0_0_ Inverter_3lvl_P0N_3lvl_0_4_stub.v +// Design : Inverter_3lvl_P0N_3lvl_0_4 // Purpose : Stub declaration of top-level module interface // Device : xc7z020clg484-3 // -------------------------------------------------------------------------------- @@ -14,7 +14,7 @@ // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. (* x_core_info = "P0N_3lvl,Vivado 2019.1" *) -module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(externalCLK, ready, reset, deadTime, minTime, er, +module Inverter_3lvl_P0N_3lvl_0_0(externalCLK, ready, reset, deadTime, minTime, er, minTime_En, minTimeEr, TKin0, TKin1, breaking_en, PWM_out_0, PWM_out_1, PWM_out_2, PWM_out_3) /* synthesis syn_black_box black_box_pad_pin="externalCLK,ready,reset,deadTime[31:0],minTime[31:0],er,minTime_En,minTimeEr,TKin0,TKin1,breaking_en,PWM_out_0,PWM_out_1,PWM_out_2,PWM_out_3" */; input externalCLK; diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0_stub.vhdl b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0_stub.vhdl similarity index 79% rename from LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0_stub.vhdl rename to LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0_stub.vhdl index 65b6f46..e3a36e6 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_0_synth_1/Inverter_3lvl_P0N_3lvl_0_0_stub.vhdl +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_0/Inverter_3lvl_P0N_3lvl_0_0_stub.vhdl @@ -1,18 +1,18 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 --- Date : Fri Jun 11 07:49:59 2021 +-- Date : Fri Jun 11 07:49:57 2021 -- Host : STAS-W10 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix --- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_0_stub.vhdl --- Design : Inverter_3lvl_P0N_3lvl_0_0 +-- Command : write_vhdl -force -mode synth_stub -rename_top Inverter_3lvl_P0N_3lvl_0_0 -prefix +-- Inverter_3lvl_P0N_3lvl_0_0_ Inverter_3lvl_P0N_3lvl_0_4_stub.vhdl +-- Design : Inverter_3lvl_P0N_3lvl_0_4 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z020clg484-3 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +entity Inverter_3lvl_P0N_3lvl_0_0 is Port ( externalCLK : in STD_LOGIC; ready : in STD_LOGIC; @@ -31,9 +31,9 @@ entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is PWM_out_3 : out STD_LOGIC ); -end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; +end Inverter_3lvl_P0N_3lvl_0_0; -architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +architecture stub of Inverter_3lvl_P0N_3lvl_0_0 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/Inverter_3lvl_P0N_3lvl_0_1.dcp b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1.dcp similarity index 99% rename from LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_1_synth_1/Inverter_3lvl_P0N_3lvl_0_1.dcp rename to LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1.dcp index 425daf20cc547a6d3741d8acbc714ac7095d74d3..6f224a6dc4f3c2b2a4f02d9051dcf8b9f4ffc5b7 100644 GIT binary patch delta 28 hcmdn8n0d=$<_%G2Sf<4;4%-}eMw}JQnp}C&8UVQ84153p delta 28 hcmdn8n0d=$<_%G2SX}H*2W^f!BhCtDO|HCX4FIsi3*rC( diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1.xml b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1.xml index 00af561..cee9e1d 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1.xml +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1.xml @@ -133,6 +133,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:44:44 UTC 2023 + + + outputProductCRC + 9:59946382 + + + @@ -407,6 +425,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + Inverter_3lvl_P0N_3lvl_0_1.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_0_1_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_0_1_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_0_1_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_0_1_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + P0N_3lvl_v1_0 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1_sim_netlist.v b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1_sim_netlist.v new file mode 100644 index 0000000..ccf8d65 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1_sim_netlist.v @@ -0,0 +1,3131 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Fri Jun 11 07:49:57 2021 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top Inverter_3lvl_P0N_3lvl_0_1 -prefix +// Inverter_3lvl_P0N_3lvl_0_1_ Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.v +// Design : Inverter_3lvl_P0N_3lvl_0_4 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "Inverter_3lvl_P0N_3lvl_0_4,P0N_3lvl,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "P0N_3lvl,Vivado 2019.1" *) +(* NotValidForBitStream *) +module Inverter_3lvl_P0N_3lvl_0_1 + (externalCLK, + ready, + reset, + deadTime, + minTime, + er, + minTime_En, + minTimeEr, + TKin0, + TKin1, + breaking_en, + PWM_out_0, + PWM_out_1, + PWM_out_2, + PWM_out_3); + input externalCLK; + input ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + input [31:0]deadTime; + input [31:0]minTime; + input er; + input minTime_En; + output minTimeEr; + input TKin0; + input TKin1; + input breaking_en; + output PWM_out_0; + output PWM_out_1; + output PWM_out_2; + output PWM_out_3; + + wire PWM_out_0; + wire PWM_out_1; + wire PWM_out_2; + wire PWM_out_3; + wire TKin0; + wire TKin1; + wire breaking_en; + wire [31:0]deadTime; + wire er; + wire externalCLK; + wire [31:0]minTime; + wire minTimeEr; + wire minTime_En; + wire ready; + wire reset; + + Inverter_3lvl_P0N_3lvl_0_1_P0N_3lvl U0 + (.PWM_out_0(PWM_out_0), + .PWM_out_1(PWM_out_1), + .PWM_out_2(PWM_out_2), + .PWM_out_3(PWM_out_3), + .TKin0(TKin0), + .TKin1(TKin1), + .breaking_en(breaking_en), + .deadTime(deadTime), + .er(er), + .externalCLK(externalCLK), + .minTime(minTime), + .minTimeEr_reg_0(minTimeEr), + .minTime_En(minTime_En), + .ready(ready), + .reset(reset)); +endmodule + +module Inverter_3lvl_P0N_3lvl_0_1_P0N_3lvl + (minTimeEr_reg_0, + PWM_out_0, + PWM_out_1, + PWM_out_2, + PWM_out_3, + reset, + externalCLK, + TKin0, + TKin1, + breaking_en, + er, + ready, + minTime_En, + deadTime, + minTime); + output minTimeEr_reg_0; + output PWM_out_0; + output PWM_out_1; + output PWM_out_2; + output PWM_out_3; + input reset; + input externalCLK; + input TKin0; + input TKin1; + input breaking_en; + input er; + input ready; + input minTime_En; + input [31:0]deadTime; + input [31:0]minTime; + + wire \FSM_onehot_lineconfig[0]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[0]_i_2_n_0 ; + wire \FSM_onehot_lineconfig[1]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[2]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[2]_i_2_n_0 ; + wire \FSM_onehot_lineconfig[3]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[4]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[5]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[5]_i_2_n_0 ; + wire \FSM_onehot_lineconfig[5]_i_3_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_2_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_3_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_4_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_5_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_6_n_0 ; + wire \FSM_onehot_lineconfig_reg_n_0_[0] ; + wire \FSM_onehot_lineconfig_reg_n_0_[1] ; + wire \FSM_onehot_lineconfig_reg_n_0_[2] ; + wire \FSM_onehot_lineconfig_reg_n_0_[3] ; + wire \FSM_onehot_lineconfig_reg_n_0_[4] ; + wire \FSM_onehot_lineconfig_reg_n_0_[5] ; + wire \FSM_onehot_lineconfig_reg_n_0_[6] ; + wire PWM_out_0; + wire PWM_out_0_i_1_n_0; + wire PWM_out_1; + wire PWM_out_1_i_1_n_0; + wire PWM_out_2; + wire PWM_out_2_i_1_n_0; + wire PWM_out_3; + wire PWM_out_3_i_1_n_0; + wire TKin0; + wire TKin0_triggered; + wire TKin0_triggered28_out; + wire TKin0_triggered_i_1_n_0; + wire TKin1; + wire TKin1_triggered; + wire TKin1_triggered_i_1_n_0; + wire \TimeCounter[0]_i_2_n_0 ; + wire [31:0]TimeCounter_reg; + wire \TimeCounter_reg[0]_i_1_n_0 ; + wire \TimeCounter_reg[0]_i_1_n_1 ; + wire \TimeCounter_reg[0]_i_1_n_2 ; + wire \TimeCounter_reg[0]_i_1_n_3 ; + wire \TimeCounter_reg[0]_i_1_n_4 ; + wire \TimeCounter_reg[0]_i_1_n_5 ; + wire \TimeCounter_reg[0]_i_1_n_6 ; + wire \TimeCounter_reg[0]_i_1_n_7 ; + wire \TimeCounter_reg[12]_i_1_n_0 ; + wire \TimeCounter_reg[12]_i_1_n_1 ; + wire \TimeCounter_reg[12]_i_1_n_2 ; + wire \TimeCounter_reg[12]_i_1_n_3 ; + wire \TimeCounter_reg[12]_i_1_n_4 ; + wire \TimeCounter_reg[12]_i_1_n_5 ; + wire \TimeCounter_reg[12]_i_1_n_6 ; + wire \TimeCounter_reg[12]_i_1_n_7 ; + wire \TimeCounter_reg[16]_i_1_n_0 ; + wire \TimeCounter_reg[16]_i_1_n_1 ; + wire \TimeCounter_reg[16]_i_1_n_2 ; + wire \TimeCounter_reg[16]_i_1_n_3 ; + wire \TimeCounter_reg[16]_i_1_n_4 ; + wire \TimeCounter_reg[16]_i_1_n_5 ; + wire \TimeCounter_reg[16]_i_1_n_6 ; + wire \TimeCounter_reg[16]_i_1_n_7 ; + wire \TimeCounter_reg[20]_i_1_n_0 ; + wire \TimeCounter_reg[20]_i_1_n_1 ; + wire \TimeCounter_reg[20]_i_1_n_2 ; + wire \TimeCounter_reg[20]_i_1_n_3 ; + wire \TimeCounter_reg[20]_i_1_n_4 ; + wire \TimeCounter_reg[20]_i_1_n_5 ; + wire \TimeCounter_reg[20]_i_1_n_6 ; + wire \TimeCounter_reg[20]_i_1_n_7 ; + wire \TimeCounter_reg[24]_i_1_n_0 ; + wire \TimeCounter_reg[24]_i_1_n_1 ; + wire \TimeCounter_reg[24]_i_1_n_2 ; + wire \TimeCounter_reg[24]_i_1_n_3 ; + wire \TimeCounter_reg[24]_i_1_n_4 ; + wire \TimeCounter_reg[24]_i_1_n_5 ; + wire \TimeCounter_reg[24]_i_1_n_6 ; + wire \TimeCounter_reg[24]_i_1_n_7 ; + wire \TimeCounter_reg[28]_i_1_n_1 ; + wire \TimeCounter_reg[28]_i_1_n_2 ; + wire \TimeCounter_reg[28]_i_1_n_3 ; + wire \TimeCounter_reg[28]_i_1_n_4 ; + wire \TimeCounter_reg[28]_i_1_n_5 ; + wire \TimeCounter_reg[28]_i_1_n_6 ; + wire \TimeCounter_reg[28]_i_1_n_7 ; + wire \TimeCounter_reg[4]_i_1_n_0 ; + wire \TimeCounter_reg[4]_i_1_n_1 ; + wire \TimeCounter_reg[4]_i_1_n_2 ; + wire \TimeCounter_reg[4]_i_1_n_3 ; + wire \TimeCounter_reg[4]_i_1_n_4 ; + wire \TimeCounter_reg[4]_i_1_n_5 ; + wire \TimeCounter_reg[4]_i_1_n_6 ; + wire \TimeCounter_reg[4]_i_1_n_7 ; + wire \TimeCounter_reg[8]_i_1_n_0 ; + wire \TimeCounter_reg[8]_i_1_n_1 ; + wire \TimeCounter_reg[8]_i_1_n_2 ; + wire \TimeCounter_reg[8]_i_1_n_3 ; + wire \TimeCounter_reg[8]_i_1_n_4 ; + wire \TimeCounter_reg[8]_i_1_n_5 ; + wire \TimeCounter_reg[8]_i_1_n_6 ; + wire \TimeCounter_reg[8]_i_1_n_7 ; + wire breaking_en; + wire [31:0]deadTime; + wire deadTimeCounterReset_i_1_n_0; + wire deadTimeCounterReset_i_2_n_0; + wire deadTimeCounterReset_i_3_n_0; + wire deadTimeCounterReset_i_4_n_0; + wire deadTimeCounterReset_i_5_n_0; + wire deadTimeCounterReset_i_6_n_0; + wire deadTimeCounterReset_i_7_n_0; + wire deadTimeCounterReset_reg_n_0; + wire deadTimeOK; + wire deadTimeOK_i_1_n_0; + wire er; + wire externalCLK; + wire key1_i_1_n_0; + wire key1_i_2_n_0; + wire key1_prev; + wire key1_reg_n_0; + wire key2_i_2_n_0; + wire key2_prev; + wire key2_reg_n_0; + wire key3; + wire key3_i_1_n_0; + wire key3_prev; + wire key3_reg_n_0; + wire key4_i_1_n_0; + wire key4_prev; + wire key4_reg_n_0; + wire ltOp__15_carry__0_i_1_n_0; + wire ltOp__15_carry__0_i_2_n_0; + wire ltOp__15_carry__0_i_3_n_0; + wire ltOp__15_carry__0_i_4_n_0; + wire ltOp__15_carry__0_i_5_n_0; + wire ltOp__15_carry__0_i_6_n_0; + wire ltOp__15_carry__0_i_7_n_0; + wire ltOp__15_carry__0_i_8_n_0; + wire ltOp__15_carry__0_n_0; + wire ltOp__15_carry__0_n_1; + wire ltOp__15_carry__0_n_2; + wire ltOp__15_carry__0_n_3; + wire ltOp__15_carry__1_i_1_n_0; + wire ltOp__15_carry__1_i_2_n_0; + wire ltOp__15_carry__1_i_3_n_0; + wire ltOp__15_carry__1_i_4_n_0; + wire ltOp__15_carry__1_i_5_n_0; + wire ltOp__15_carry__1_i_6_n_0; + wire ltOp__15_carry__1_i_7_n_0; + wire ltOp__15_carry__1_i_8_n_0; + wire ltOp__15_carry__1_n_0; + wire ltOp__15_carry__1_n_1; + wire ltOp__15_carry__1_n_2; + wire ltOp__15_carry__1_n_3; + wire ltOp__15_carry__2_i_1_n_0; + wire ltOp__15_carry__2_i_2_n_0; + wire ltOp__15_carry__2_i_3_n_0; + wire ltOp__15_carry__2_i_4_n_0; + wire ltOp__15_carry__2_i_5_n_0; + wire ltOp__15_carry__2_i_6_n_0; + wire ltOp__15_carry__2_i_7_n_0; + wire ltOp__15_carry__2_i_8_n_0; + wire ltOp__15_carry__2_n_0; + wire ltOp__15_carry__2_n_1; + wire ltOp__15_carry__2_n_2; + wire ltOp__15_carry__2_n_3; + wire ltOp__15_carry_i_1_n_0; + wire ltOp__15_carry_i_2_n_0; + wire ltOp__15_carry_i_3_n_0; + wire ltOp__15_carry_i_4_n_0; + wire ltOp__15_carry_i_5_n_0; + wire ltOp__15_carry_i_6_n_0; + wire ltOp__15_carry_i_7_n_0; + wire ltOp__15_carry_i_8_n_0; + wire ltOp__15_carry_n_0; + wire ltOp__15_carry_n_1; + wire ltOp__15_carry_n_2; + wire ltOp__15_carry_n_3; + wire ltOp__31_carry__0_n_0; + wire ltOp__31_carry__0_n_1; + wire ltOp__31_carry__0_n_2; + wire ltOp__31_carry__0_n_3; + wire ltOp__31_carry__1_n_0; + wire ltOp__31_carry__1_n_1; + wire ltOp__31_carry__1_n_2; + wire ltOp__31_carry__1_n_3; + wire ltOp__31_carry__2_n_0; + wire ltOp__31_carry__2_n_1; + wire ltOp__31_carry__2_n_2; + wire ltOp__31_carry__2_n_3; + wire ltOp__31_carry_i_1__0_n_0; + wire ltOp__31_carry_i_1__1_n_0; + wire ltOp__31_carry_i_1__2_n_0; + wire ltOp__31_carry_i_1_n_0; + wire ltOp__31_carry_i_2__0_n_0; + wire ltOp__31_carry_i_2__1_n_0; + wire ltOp__31_carry_i_2__2_n_0; + wire ltOp__31_carry_i_2_n_0; + wire ltOp__31_carry_i_3__0_n_0; + wire ltOp__31_carry_i_3__1_n_0; + wire ltOp__31_carry_i_3__2_n_0; + wire ltOp__31_carry_i_3_n_0; + wire ltOp__31_carry_i_4__0_n_0; + wire ltOp__31_carry_i_4__1_n_0; + wire ltOp__31_carry_i_4__2_n_0; + wire ltOp__31_carry_i_4_n_0; + wire ltOp__31_carry_i_5__0_n_0; + wire ltOp__31_carry_i_5__1_n_0; + wire ltOp__31_carry_i_5__2_n_0; + wire ltOp__31_carry_i_5_n_0; + wire ltOp__31_carry_i_6__0_n_0; + wire ltOp__31_carry_i_6__1_n_0; + wire ltOp__31_carry_i_6__2_n_0; + wire ltOp__31_carry_i_6_n_0; + wire ltOp__31_carry_i_7__0_n_0; + wire ltOp__31_carry_i_7__1_n_0; + wire ltOp__31_carry_i_7__2_n_0; + wire ltOp__31_carry_i_7_n_0; + wire ltOp__31_carry_i_8__0_n_0; + wire ltOp__31_carry_i_8__1_n_0; + wire ltOp__31_carry_i_8__2_n_0; + wire ltOp__31_carry_i_8_n_0; + wire ltOp__31_carry_n_0; + wire ltOp__31_carry_n_1; + wire ltOp__31_carry_n_2; + wire ltOp__31_carry_n_3; + wire ltOp_carry__0_i_1_n_0; + wire ltOp_carry__0_i_2_n_0; + wire ltOp_carry__0_i_3_n_0; + wire ltOp_carry__0_i_4_n_0; + wire ltOp_carry__0_i_5_n_0; + wire ltOp_carry__0_i_6_n_0; + wire ltOp_carry__0_i_7_n_0; + wire ltOp_carry__0_i_8_n_0; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_i_1_n_0; + wire ltOp_carry__1_i_2_n_0; + wire ltOp_carry__1_i_3_n_0; + wire ltOp_carry__1_i_4_n_0; + wire ltOp_carry__1_i_5_n_0; + wire ltOp_carry__1_i_6_n_0; + wire ltOp_carry__1_i_7_n_0; + wire ltOp_carry__1_i_8_n_0; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_i_1_n_0; + wire ltOp_carry__2_i_2_n_0; + wire ltOp_carry__2_i_3_n_0; + wire ltOp_carry__2_i_4_n_0; + wire ltOp_carry__2_i_5_n_0; + wire ltOp_carry__2_i_6_n_0; + wire ltOp_carry__2_i_7_n_0; + wire ltOp_carry__2_i_8_n_0; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [31:0]minTime; + wire minTimeCounter_high; + wire \minTimeCounter_high[0]_i_1_n_0 ; + wire \minTimeCounter_high[0]_i_4_n_0 ; + wire [31:0]minTimeCounter_high_reg; + wire \minTimeCounter_high_reg[0]_i_3_n_0 ; + wire \minTimeCounter_high_reg[0]_i_3_n_1 ; + wire \minTimeCounter_high_reg[0]_i_3_n_2 ; + wire \minTimeCounter_high_reg[0]_i_3_n_3 ; + wire \minTimeCounter_high_reg[0]_i_3_n_4 ; + wire \minTimeCounter_high_reg[0]_i_3_n_5 ; + wire \minTimeCounter_high_reg[0]_i_3_n_6 ; + wire \minTimeCounter_high_reg[0]_i_3_n_7 ; + wire \minTimeCounter_high_reg[12]_i_1_n_0 ; + wire \minTimeCounter_high_reg[12]_i_1_n_1 ; + wire \minTimeCounter_high_reg[12]_i_1_n_2 ; + wire \minTimeCounter_high_reg[12]_i_1_n_3 ; + wire \minTimeCounter_high_reg[12]_i_1_n_4 ; + wire \minTimeCounter_high_reg[12]_i_1_n_5 ; + wire \minTimeCounter_high_reg[12]_i_1_n_6 ; + wire \minTimeCounter_high_reg[12]_i_1_n_7 ; + wire \minTimeCounter_high_reg[16]_i_1_n_0 ; + wire \minTimeCounter_high_reg[16]_i_1_n_1 ; + wire \minTimeCounter_high_reg[16]_i_1_n_2 ; + wire \minTimeCounter_high_reg[16]_i_1_n_3 ; + wire \minTimeCounter_high_reg[16]_i_1_n_4 ; + wire \minTimeCounter_high_reg[16]_i_1_n_5 ; + wire \minTimeCounter_high_reg[16]_i_1_n_6 ; + wire \minTimeCounter_high_reg[16]_i_1_n_7 ; + wire \minTimeCounter_high_reg[20]_i_1_n_0 ; + wire \minTimeCounter_high_reg[20]_i_1_n_1 ; + wire \minTimeCounter_high_reg[20]_i_1_n_2 ; + wire \minTimeCounter_high_reg[20]_i_1_n_3 ; + wire \minTimeCounter_high_reg[20]_i_1_n_4 ; + wire \minTimeCounter_high_reg[20]_i_1_n_5 ; + wire \minTimeCounter_high_reg[20]_i_1_n_6 ; + wire \minTimeCounter_high_reg[20]_i_1_n_7 ; + wire \minTimeCounter_high_reg[24]_i_1_n_0 ; + wire \minTimeCounter_high_reg[24]_i_1_n_1 ; + wire \minTimeCounter_high_reg[24]_i_1_n_2 ; + wire \minTimeCounter_high_reg[24]_i_1_n_3 ; + wire \minTimeCounter_high_reg[24]_i_1_n_4 ; + wire \minTimeCounter_high_reg[24]_i_1_n_5 ; + wire \minTimeCounter_high_reg[24]_i_1_n_6 ; + wire \minTimeCounter_high_reg[24]_i_1_n_7 ; + wire \minTimeCounter_high_reg[28]_i_1_n_1 ; + wire \minTimeCounter_high_reg[28]_i_1_n_2 ; + wire \minTimeCounter_high_reg[28]_i_1_n_3 ; + wire \minTimeCounter_high_reg[28]_i_1_n_4 ; + wire \minTimeCounter_high_reg[28]_i_1_n_5 ; + wire \minTimeCounter_high_reg[28]_i_1_n_6 ; + wire \minTimeCounter_high_reg[28]_i_1_n_7 ; + wire \minTimeCounter_high_reg[4]_i_1_n_0 ; + wire \minTimeCounter_high_reg[4]_i_1_n_1 ; + wire \minTimeCounter_high_reg[4]_i_1_n_2 ; + wire \minTimeCounter_high_reg[4]_i_1_n_3 ; + wire \minTimeCounter_high_reg[4]_i_1_n_4 ; + wire \minTimeCounter_high_reg[4]_i_1_n_5 ; + wire \minTimeCounter_high_reg[4]_i_1_n_6 ; + wire \minTimeCounter_high_reg[4]_i_1_n_7 ; + wire \minTimeCounter_high_reg[8]_i_1_n_0 ; + wire \minTimeCounter_high_reg[8]_i_1_n_1 ; + wire \minTimeCounter_high_reg[8]_i_1_n_2 ; + wire \minTimeCounter_high_reg[8]_i_1_n_3 ; + wire \minTimeCounter_high_reg[8]_i_1_n_4 ; + wire \minTimeCounter_high_reg[8]_i_1_n_5 ; + wire \minTimeCounter_high_reg[8]_i_1_n_6 ; + wire \minTimeCounter_high_reg[8]_i_1_n_7 ; + wire minTimeCounter_low; + wire \minTimeCounter_low[0]_i_1_n_0 ; + wire \minTimeCounter_low[0]_i_4_n_0 ; + wire \minTimeCounter_low[0]_i_5_n_0 ; + wire [31:0]minTimeCounter_low_reg; + wire \minTimeCounter_low_reg[0]_i_3_n_0 ; + wire \minTimeCounter_low_reg[0]_i_3_n_1 ; + wire \minTimeCounter_low_reg[0]_i_3_n_2 ; + wire \minTimeCounter_low_reg[0]_i_3_n_3 ; + wire \minTimeCounter_low_reg[0]_i_3_n_4 ; + wire \minTimeCounter_low_reg[0]_i_3_n_5 ; + wire \minTimeCounter_low_reg[0]_i_3_n_6 ; + wire \minTimeCounter_low_reg[0]_i_3_n_7 ; + wire \minTimeCounter_low_reg[12]_i_1_n_0 ; + wire \minTimeCounter_low_reg[12]_i_1_n_1 ; + wire \minTimeCounter_low_reg[12]_i_1_n_2 ; + wire \minTimeCounter_low_reg[12]_i_1_n_3 ; + wire \minTimeCounter_low_reg[12]_i_1_n_4 ; + wire \minTimeCounter_low_reg[12]_i_1_n_5 ; + wire \minTimeCounter_low_reg[12]_i_1_n_6 ; + wire \minTimeCounter_low_reg[12]_i_1_n_7 ; + wire \minTimeCounter_low_reg[16]_i_1_n_0 ; + wire \minTimeCounter_low_reg[16]_i_1_n_1 ; + wire \minTimeCounter_low_reg[16]_i_1_n_2 ; + wire \minTimeCounter_low_reg[16]_i_1_n_3 ; + wire \minTimeCounter_low_reg[16]_i_1_n_4 ; + wire \minTimeCounter_low_reg[16]_i_1_n_5 ; + wire \minTimeCounter_low_reg[16]_i_1_n_6 ; + wire \minTimeCounter_low_reg[16]_i_1_n_7 ; + wire \minTimeCounter_low_reg[20]_i_1_n_0 ; + wire \minTimeCounter_low_reg[20]_i_1_n_1 ; + wire \minTimeCounter_low_reg[20]_i_1_n_2 ; + wire \minTimeCounter_low_reg[20]_i_1_n_3 ; + wire \minTimeCounter_low_reg[20]_i_1_n_4 ; + wire \minTimeCounter_low_reg[20]_i_1_n_5 ; + wire \minTimeCounter_low_reg[20]_i_1_n_6 ; + wire \minTimeCounter_low_reg[20]_i_1_n_7 ; + wire \minTimeCounter_low_reg[24]_i_1_n_0 ; + wire \minTimeCounter_low_reg[24]_i_1_n_1 ; + wire \minTimeCounter_low_reg[24]_i_1_n_2 ; + wire \minTimeCounter_low_reg[24]_i_1_n_3 ; + wire \minTimeCounter_low_reg[24]_i_1_n_4 ; + wire \minTimeCounter_low_reg[24]_i_1_n_5 ; + wire \minTimeCounter_low_reg[24]_i_1_n_6 ; + wire \minTimeCounter_low_reg[24]_i_1_n_7 ; + wire \minTimeCounter_low_reg[28]_i_1_n_1 ; + wire \minTimeCounter_low_reg[28]_i_1_n_2 ; + wire \minTimeCounter_low_reg[28]_i_1_n_3 ; + wire \minTimeCounter_low_reg[28]_i_1_n_4 ; + wire \minTimeCounter_low_reg[28]_i_1_n_5 ; + wire \minTimeCounter_low_reg[28]_i_1_n_6 ; + wire \minTimeCounter_low_reg[28]_i_1_n_7 ; + wire \minTimeCounter_low_reg[4]_i_1_n_0 ; + wire \minTimeCounter_low_reg[4]_i_1_n_1 ; + wire \minTimeCounter_low_reg[4]_i_1_n_2 ; + wire \minTimeCounter_low_reg[4]_i_1_n_3 ; + wire \minTimeCounter_low_reg[4]_i_1_n_4 ; + wire \minTimeCounter_low_reg[4]_i_1_n_5 ; + wire \minTimeCounter_low_reg[4]_i_1_n_6 ; + wire \minTimeCounter_low_reg[4]_i_1_n_7 ; + wire \minTimeCounter_low_reg[8]_i_1_n_0 ; + wire \minTimeCounter_low_reg[8]_i_1_n_1 ; + wire \minTimeCounter_low_reg[8]_i_1_n_2 ; + wire \minTimeCounter_low_reg[8]_i_1_n_3 ; + wire \minTimeCounter_low_reg[8]_i_1_n_4 ; + wire \minTimeCounter_low_reg[8]_i_1_n_5 ; + wire \minTimeCounter_low_reg[8]_i_1_n_6 ; + wire \minTimeCounter_low_reg[8]_i_1_n_7 ; + wire minTimeEr_i_1_n_0; + wire minTimeEr_i_2_n_0; + wire minTimeEr_i_3_n_0; + wire minTimeEr_i_4_n_0; + wire minTimeEr_i_5_n_0; + wire minTimeEr_i_6_n_0; + wire minTimeEr_i_7_n_0; + wire minTimeEr_i_8_n_0; + wire minTimeEr_i_9_n_0; + wire minTimeEr_reg_0; + wire minTimeOK_high; + wire minTimeOK_high_i_1_n_0; + wire minTimeOK_low; + wire minTimeOK_low_i_1_n_0; + wire minTime_En; + wire p_0_in; + wire ready; + wire reset; + wire sel; + wire [3:3]\NLW_TimeCounter_reg[28]_i_1_CO_UNCONNECTED ; + wire [3:0]NLW_ltOp__15_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp__15_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp__15_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp__15_carry__2_O_UNCONNECTED; + wire [3:0]NLW_ltOp__31_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp__31_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp__31_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp__31_carry__2_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + wire [3:3]\NLW_minTimeCounter_high_reg[28]_i_1_CO_UNCONNECTED ; + wire [3:3]\NLW_minTimeCounter_low_reg[28]_i_1_CO_UNCONNECTED ; + + LUT6 #( + .INIT(64'hFFFFFFFE00000000)) + \FSM_onehot_lineconfig[0]_i_1 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I4(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I5(\FSM_onehot_lineconfig[0]_i_2_n_0 ), + .O(\FSM_onehot_lineconfig[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_lineconfig[0]_i_2 + (.I0(TKin1), + .I1(TKin0), + .O(\FSM_onehot_lineconfig[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'h1000FFFF00000000)) + \FSM_onehot_lineconfig[1]_i_1 + (.I0(TKin1), + .I1(TKin1_triggered), + .I2(TKin0_triggered), + .I3(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I4(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I5(TKin0), + .O(\FSM_onehot_lineconfig[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h00EFEF0F)) + \FSM_onehot_lineconfig[2]_i_1 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I2(\FSM_onehot_lineconfig[2]_i_2_n_0 ), + .I3(TKin0), + .I4(TKin1), + .O(\FSM_onehot_lineconfig[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'h900990099009FFFF)) + \FSM_onehot_lineconfig[2]_i_2 + (.I0(TKin1), + .I1(TKin1_triggered), + .I2(TKin0), + .I3(TKin0_triggered), + .I4(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I5(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .O(\FSM_onehot_lineconfig[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0000000055D50000)) + \FSM_onehot_lineconfig[3]_i_1 + (.I0(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I2(TKin1_triggered), + .I3(TKin0_triggered), + .I4(TKin1), + .I5(TKin0), + .O(\FSM_onehot_lineconfig[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT4 #( + .INIT(16'h2230)) + \FSM_onehot_lineconfig[4]_i_1 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I1(TKin0), + .I2(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I3(TKin1), + .O(\FSM_onehot_lineconfig[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0CFF0C0D00050005)) + \FSM_onehot_lineconfig[5]_i_1 + (.I0(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I2(TKin1), + .I3(TKin0), + .I4(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I5(\FSM_onehot_lineconfig[5]_i_3_n_0 ), + .O(\FSM_onehot_lineconfig[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h1)) + \FSM_onehot_lineconfig[5]_i_2 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .O(\FSM_onehot_lineconfig[5]_i_2_n_0 )); + LUT4 #( + .INIT(16'h9009)) + \FSM_onehot_lineconfig[5]_i_3 + (.I0(TKin0_triggered), + .I1(TKin0), + .I2(TKin1_triggered), + .I3(TKin1), + .O(\FSM_onehot_lineconfig[5]_i_3_n_0 )); + LUT3 #( + .INIT(8'h0E)) + \FSM_onehot_lineconfig[6]_i_1 + (.I0(\FSM_onehot_lineconfig[6]_i_3_n_0 ), + .I1(\FSM_onehot_lineconfig[6]_i_4_n_0 ), + .I2(breaking_en), + .O(\FSM_onehot_lineconfig[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT4 #( + .INIT(16'h5504)) + \FSM_onehot_lineconfig[6]_i_2 + (.I0(TKin1), + .I1(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I2(TKin0), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .O(\FSM_onehot_lineconfig[6]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'hFFFEECAE)) + \FSM_onehot_lineconfig[6]_i_3 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I2(TKin1), + .I3(TKin0), + .I4(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .O(\FSM_onehot_lineconfig[6]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAABAAAAAFFFFAAAA)) + \FSM_onehot_lineconfig[6]_i_4 + (.I0(\FSM_onehot_lineconfig[6]_i_5_n_0 ), + .I1(er), + .I2(ready), + .I3(\FSM_onehot_lineconfig[6]_i_6_n_0 ), + .I4(deadTimeOK), + .I5(\FSM_onehot_lineconfig[2]_i_2_n_0 ), + .O(\FSM_onehot_lineconfig[6]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFC88A0A8)) + \FSM_onehot_lineconfig[6]_i_5 + (.I0(deadTimeOK), + .I1(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I3(TKin1), + .I4(TKin0), + .O(\FSM_onehot_lineconfig[6]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'hFF232323)) + \FSM_onehot_lineconfig[6]_i_6 + (.I0(deadTimeCounterReset_reg_n_0), + .I1(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I3(TKin1), + .I4(TKin0), + .O(\FSM_onehot_lineconfig[6]_i_6_n_0 )); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDSE #( + .INIT(1'b1)) + \FSM_onehot_lineconfig_reg[0] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[0]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .S(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[1] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[1]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[2] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[2]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[3] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[3]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[4] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[4]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[5] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[5]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[6] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[6]_i_2_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT4 #( + .INIT(16'hFFEF)) + PWM_out_0_i_1 + (.I0(key1_reg_n_0), + .I1(er), + .I2(ready), + .I3(minTimeEr_reg_0), + .O(PWM_out_0_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + PWM_out_0_reg + (.C(externalCLK), + .CE(1'b1), + .D(PWM_out_0_i_1_n_0), + .Q(PWM_out_0), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT4 #( + .INIT(16'hFFEF)) + PWM_out_1_i_1 + (.I0(key2_reg_n_0), + .I1(er), + .I2(ready), + .I3(minTimeEr_reg_0), + .O(PWM_out_1_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + PWM_out_1_reg + (.C(externalCLK), + .CE(1'b1), + .D(PWM_out_1_i_1_n_0), + .Q(PWM_out_1), + .R(1'b0)); + LUT5 #( + .INIT(32'hFFFFFFEF)) + PWM_out_2_i_1 + (.I0(key3_reg_n_0), + .I1(minTimeEr_reg_0), + .I2(ready), + .I3(er), + .I4(breaking_en), + .O(PWM_out_2_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + PWM_out_2_reg + (.C(externalCLK), + .CE(1'b1), + .D(PWM_out_2_i_1_n_0), + .Q(PWM_out_2), + .R(1'b0)); + LUT5 #( + .INIT(32'hFFFFFFEF)) + PWM_out_3_i_1 + (.I0(key4_reg_n_0), + .I1(minTimeEr_reg_0), + .I2(ready), + .I3(er), + .I4(breaking_en), + .O(PWM_out_3_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + PWM_out_3_reg + (.C(externalCLK), + .CE(1'b1), + .D(PWM_out_3_i_1_n_0), + .Q(PWM_out_3), + .R(1'b0)); + LUT6 #( + .INIT(64'hAA08FFFFAA080000)) + TKin0_triggered_i_1 + (.I0(TKin0), + .I1(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I2(TKin1), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I4(TKin0_triggered28_out), + .I5(TKin0_triggered), + .O(TKin0_triggered_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + TKin0_triggered_reg + (.C(externalCLK), + .CE(1'b1), + .D(TKin0_triggered_i_1_n_0), + .Q(TKin0_triggered), + .R(1'b0)); + LUT6 #( + .INIT(64'hAA08FFFFAA080000)) + TKin1_triggered_i_1 + (.I0(TKin1), + .I1(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I2(TKin0), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I4(TKin0_triggered28_out), + .I5(TKin1_triggered), + .O(TKin1_triggered_i_1_n_0)); + LUT6 #( + .INIT(64'h22AA22A820AA2020)) + TKin1_triggered_i_2 + (.I0(minTimeEr_i_9_n_0), + .I1(TKin1), + .I2(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I3(TKin0), + .I4(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I5(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .O(TKin0_triggered28_out)); + FDRE #( + .INIT(1'b1)) + TKin1_triggered_reg + (.C(externalCLK), + .CE(1'b1), + .D(TKin1_triggered_i_1_n_0), + .Q(TKin1_triggered), + .R(1'b0)); + LUT1 #( + .INIT(2'h1)) + \TimeCounter[0]_i_2 + (.I0(TimeCounter_reg[0]), + .O(\TimeCounter[0]_i_2_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[0] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[0]_i_1_n_7 ), + .Q(TimeCounter_reg[0]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[0]_i_1 + (.CI(1'b0), + .CO({\TimeCounter_reg[0]_i_1_n_0 ,\TimeCounter_reg[0]_i_1_n_1 ,\TimeCounter_reg[0]_i_1_n_2 ,\TimeCounter_reg[0]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\TimeCounter_reg[0]_i_1_n_4 ,\TimeCounter_reg[0]_i_1_n_5 ,\TimeCounter_reg[0]_i_1_n_6 ,\TimeCounter_reg[0]_i_1_n_7 }), + .S({TimeCounter_reg[3:1],\TimeCounter[0]_i_2_n_0 })); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[10] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[8]_i_1_n_5 ), + .Q(TimeCounter_reg[10]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[11] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[8]_i_1_n_4 ), + .Q(TimeCounter_reg[11]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[12] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[12]_i_1_n_7 ), + .Q(TimeCounter_reg[12]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[12]_i_1 + (.CI(\TimeCounter_reg[8]_i_1_n_0 ), + .CO({\TimeCounter_reg[12]_i_1_n_0 ,\TimeCounter_reg[12]_i_1_n_1 ,\TimeCounter_reg[12]_i_1_n_2 ,\TimeCounter_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[12]_i_1_n_4 ,\TimeCounter_reg[12]_i_1_n_5 ,\TimeCounter_reg[12]_i_1_n_6 ,\TimeCounter_reg[12]_i_1_n_7 }), + .S(TimeCounter_reg[15:12])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[13] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[12]_i_1_n_6 ), + .Q(TimeCounter_reg[13]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[14] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[12]_i_1_n_5 ), + .Q(TimeCounter_reg[14]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[15] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[12]_i_1_n_4 ), + .Q(TimeCounter_reg[15]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[16] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[16]_i_1_n_7 ), + .Q(TimeCounter_reg[16]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[16]_i_1 + (.CI(\TimeCounter_reg[12]_i_1_n_0 ), + .CO({\TimeCounter_reg[16]_i_1_n_0 ,\TimeCounter_reg[16]_i_1_n_1 ,\TimeCounter_reg[16]_i_1_n_2 ,\TimeCounter_reg[16]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[16]_i_1_n_4 ,\TimeCounter_reg[16]_i_1_n_5 ,\TimeCounter_reg[16]_i_1_n_6 ,\TimeCounter_reg[16]_i_1_n_7 }), + .S(TimeCounter_reg[19:16])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[17] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[16]_i_1_n_6 ), + .Q(TimeCounter_reg[17]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[18] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[16]_i_1_n_5 ), + .Q(TimeCounter_reg[18]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[19] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[16]_i_1_n_4 ), + .Q(TimeCounter_reg[19]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[1] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[0]_i_1_n_6 ), + .Q(TimeCounter_reg[1]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[20] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[20]_i_1_n_7 ), + .Q(TimeCounter_reg[20]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[20]_i_1 + (.CI(\TimeCounter_reg[16]_i_1_n_0 ), + .CO({\TimeCounter_reg[20]_i_1_n_0 ,\TimeCounter_reg[20]_i_1_n_1 ,\TimeCounter_reg[20]_i_1_n_2 ,\TimeCounter_reg[20]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[20]_i_1_n_4 ,\TimeCounter_reg[20]_i_1_n_5 ,\TimeCounter_reg[20]_i_1_n_6 ,\TimeCounter_reg[20]_i_1_n_7 }), + .S(TimeCounter_reg[23:20])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[21] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[20]_i_1_n_6 ), + .Q(TimeCounter_reg[21]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[22] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[20]_i_1_n_5 ), + .Q(TimeCounter_reg[22]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[23] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[20]_i_1_n_4 ), + .Q(TimeCounter_reg[23]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[24] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[24]_i_1_n_7 ), + .Q(TimeCounter_reg[24]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[24]_i_1 + (.CI(\TimeCounter_reg[20]_i_1_n_0 ), + .CO({\TimeCounter_reg[24]_i_1_n_0 ,\TimeCounter_reg[24]_i_1_n_1 ,\TimeCounter_reg[24]_i_1_n_2 ,\TimeCounter_reg[24]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[24]_i_1_n_4 ,\TimeCounter_reg[24]_i_1_n_5 ,\TimeCounter_reg[24]_i_1_n_6 ,\TimeCounter_reg[24]_i_1_n_7 }), + .S(TimeCounter_reg[27:24])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[25] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[24]_i_1_n_6 ), + .Q(TimeCounter_reg[25]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[26] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[24]_i_1_n_5 ), + .Q(TimeCounter_reg[26]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[27] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[24]_i_1_n_4 ), + .Q(TimeCounter_reg[27]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[28] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[28]_i_1_n_7 ), + .Q(TimeCounter_reg[28]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[28]_i_1 + (.CI(\TimeCounter_reg[24]_i_1_n_0 ), + .CO({\NLW_TimeCounter_reg[28]_i_1_CO_UNCONNECTED [3],\TimeCounter_reg[28]_i_1_n_1 ,\TimeCounter_reg[28]_i_1_n_2 ,\TimeCounter_reg[28]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[28]_i_1_n_4 ,\TimeCounter_reg[28]_i_1_n_5 ,\TimeCounter_reg[28]_i_1_n_6 ,\TimeCounter_reg[28]_i_1_n_7 }), + .S(TimeCounter_reg[31:28])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[29] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[28]_i_1_n_6 ), + .Q(TimeCounter_reg[29]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[2] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[0]_i_1_n_5 ), + .Q(TimeCounter_reg[2]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[30] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[28]_i_1_n_5 ), + .Q(TimeCounter_reg[30]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[31] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[28]_i_1_n_4 ), + .Q(TimeCounter_reg[31]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[3] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[0]_i_1_n_4 ), + .Q(TimeCounter_reg[3]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[4] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[4]_i_1_n_7 ), + .Q(TimeCounter_reg[4]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[4]_i_1 + (.CI(\TimeCounter_reg[0]_i_1_n_0 ), + .CO({\TimeCounter_reg[4]_i_1_n_0 ,\TimeCounter_reg[4]_i_1_n_1 ,\TimeCounter_reg[4]_i_1_n_2 ,\TimeCounter_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[4]_i_1_n_4 ,\TimeCounter_reg[4]_i_1_n_5 ,\TimeCounter_reg[4]_i_1_n_6 ,\TimeCounter_reg[4]_i_1_n_7 }), + .S(TimeCounter_reg[7:4])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[5] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[4]_i_1_n_6 ), + .Q(TimeCounter_reg[5]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[6] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[4]_i_1_n_5 ), + .Q(TimeCounter_reg[6]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[7] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[4]_i_1_n_4 ), + .Q(TimeCounter_reg[7]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[8] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[8]_i_1_n_7 ), + .Q(TimeCounter_reg[8]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[8]_i_1 + (.CI(\TimeCounter_reg[4]_i_1_n_0 ), + .CO({\TimeCounter_reg[8]_i_1_n_0 ,\TimeCounter_reg[8]_i_1_n_1 ,\TimeCounter_reg[8]_i_1_n_2 ,\TimeCounter_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[8]_i_1_n_4 ,\TimeCounter_reg[8]_i_1_n_5 ,\TimeCounter_reg[8]_i_1_n_6 ,\TimeCounter_reg[8]_i_1_n_7 }), + .S(TimeCounter_reg[11:8])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[9] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[8]_i_1_n_6 ), + .Q(TimeCounter_reg[9]), + .R(deadTimeCounterReset_reg_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFE0000000E)) + deadTimeCounterReset_i_1 + (.I0(deadTimeCounterReset_i_2_n_0), + .I1(\FSM_onehot_lineconfig[6]_i_4_n_0 ), + .I2(reset), + .I3(breaking_en), + .I4(deadTimeCounterReset_i_3_n_0), + .I5(deadTimeCounterReset_reg_n_0), + .O(deadTimeCounterReset_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'hFE)) + deadTimeCounterReset_i_2 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .O(deadTimeCounterReset_i_2_n_0)); + LUT6 #( + .INIT(64'h0000000022220020)) + deadTimeCounterReset_i_3 + (.I0(deadTimeCounterReset_i_4_n_0), + .I1(deadTimeCounterReset_i_2_n_0), + .I2(deadTimeCounterReset_i_5_n_0), + .I3(deadTimeCounterReset_i_6_n_0), + .I4(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I5(deadTimeCounterReset_i_7_n_0), + .O(deadTimeCounterReset_i_3_n_0)); + LUT6 #( + .INIT(64'h555D555555555555)) + deadTimeCounterReset_i_4 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I1(deadTimeOK), + .I2(TKin1), + .I3(TKin1_triggered), + .I4(TKin0), + .I5(TKin0_triggered), + .O(deadTimeCounterReset_i_4_n_0)); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT3 #( + .INIT(8'h08)) + deadTimeCounterReset_i_5 + (.I0(deadTimeOK), + .I1(ready), + .I2(er), + .O(deadTimeCounterReset_i_5_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT4 #( + .INIT(16'hF777)) + deadTimeCounterReset_i_6 + (.I0(TKin0), + .I1(TKin1), + .I2(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I3(deadTimeCounterReset_reg_n_0), + .O(deadTimeCounterReset_i_6_n_0)); + LUT6 #( + .INIT(64'hAAAAA2AAAAAAAAAA)) + deadTimeCounterReset_i_7 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I1(TKin1), + .I2(TKin0), + .I3(deadTimeOK), + .I4(TKin0_triggered), + .I5(TKin1_triggered), + .O(deadTimeCounterReset_i_7_n_0)); + FDRE #( + .INIT(1'b0)) + deadTimeCounterReset_reg + (.C(externalCLK), + .CE(1'b1), + .D(deadTimeCounterReset_i_1_n_0), + .Q(deadTimeCounterReset_reg_n_0), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT3 #( + .INIT(8'h0D)) + deadTimeOK_i_1 + (.I0(sel), + .I1(deadTimeOK), + .I2(deadTimeCounterReset_reg_n_0), + .O(deadTimeOK_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + deadTimeOK_reg + (.C(externalCLK), + .CE(1'b1), + .D(deadTimeOK_i_1_n_0), + .Q(deadTimeOK), + .R(1'b0)); + LUT6 #( + .INIT(64'hDDDDDDD0DDDDDDDD)) + key1_i_1 + (.I0(breaking_en), + .I1(TKin0), + .I2(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I4(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I5(key1_i_2_n_0), + .O(key1_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT4 #( + .INIT(16'h0001)) + key1_i_2 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I3(breaking_en), + .O(key1_i_2_n_0)); + FDRE #( + .INIT(1'b1)) + key1_prev_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key1_reg_n_0), + .Q(key1_prev), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + key1_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key1_i_1_n_0), + .Q(key1_reg_n_0), + .R(1'b0)); + LUT1 #( + .INIT(2'h1)) + key2_i_1 + (.I0(reset), + .O(p_0_in)); + LUT6 #( + .INIT(64'hAAAAAAAAFFFFFFFC)) + key2_i_2 + (.I0(TKin1), + .I1(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I4(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I5(breaking_en), + .O(key2_i_2_n_0)); + FDRE #( + .INIT(1'b1)) + key2_prev_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key2_reg_n_0), + .Q(key2_prev), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + key2_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key2_i_2_n_0), + .Q(key2_reg_n_0), + .R(1'b0)); + LUT6 #( + .INIT(64'hAAAAFFFFAAAAFCFF)) + key3_i_1 + (.I0(key3_reg_n_0), + .I1(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I3(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I4(reset), + .I5(breaking_en), + .O(key3_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + key3_prev_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key3_reg_n_0), + .Q(key3_prev), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + key3_reg + (.C(externalCLK), + .CE(1'b1), + .D(key3_i_1_n_0), + .Q(key3_reg_n_0), + .R(1'b0)); + LUT6 #( + .INIT(64'hAAAAFFFFAAAAFFFC)) + key4_i_1 + (.I0(key4_reg_n_0), + .I1(key3), + .I2(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I4(reset), + .I5(breaking_en), + .O(key4_i_1_n_0)); + LUT4 #( + .INIT(16'hFFFE)) + key4_i_2 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .O(key3)); + FDRE #( + .INIT(1'b1)) + key4_prev_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key4_reg_n_0), + .Q(key4_prev), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + key4_reg + (.C(externalCLK), + .CE(1'b1), + .D(key4_i_1_n_0), + .Q(key4_reg_n_0), + .R(1'b0)); + CARRY4 ltOp__15_carry + (.CI(1'b0), + .CO({ltOp__15_carry_n_0,ltOp__15_carry_n_1,ltOp__15_carry_n_2,ltOp__15_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp__15_carry_i_1_n_0,ltOp__15_carry_i_2_n_0,ltOp__15_carry_i_3_n_0,ltOp__15_carry_i_4_n_0}), + .O(NLW_ltOp__15_carry_O_UNCONNECTED[3:0]), + .S({ltOp__15_carry_i_5_n_0,ltOp__15_carry_i_6_n_0,ltOp__15_carry_i_7_n_0,ltOp__15_carry_i_8_n_0})); + CARRY4 ltOp__15_carry__0 + (.CI(ltOp__15_carry_n_0), + .CO({ltOp__15_carry__0_n_0,ltOp__15_carry__0_n_1,ltOp__15_carry__0_n_2,ltOp__15_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp__15_carry__0_i_1_n_0,ltOp__15_carry__0_i_2_n_0,ltOp__15_carry__0_i_3_n_0,ltOp__15_carry__0_i_4_n_0}), + .O(NLW_ltOp__15_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp__15_carry__0_i_5_n_0,ltOp__15_carry__0_i_6_n_0,ltOp__15_carry__0_i_7_n_0,ltOp__15_carry__0_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__0_i_1 + (.I0(minTime[15]), + .I1(minTimeCounter_low_reg[15]), + .I2(minTime[14]), + .I3(minTimeCounter_low_reg[14]), + .O(ltOp__15_carry__0_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__0_i_2 + (.I0(minTime[13]), + .I1(minTimeCounter_low_reg[13]), + .I2(minTime[12]), + .I3(minTimeCounter_low_reg[12]), + .O(ltOp__15_carry__0_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__0_i_3 + (.I0(minTime[11]), + .I1(minTimeCounter_low_reg[11]), + .I2(minTime[10]), + .I3(minTimeCounter_low_reg[10]), + .O(ltOp__15_carry__0_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__0_i_4 + (.I0(minTime[9]), + .I1(minTimeCounter_low_reg[9]), + .I2(minTime[8]), + .I3(minTimeCounter_low_reg[8]), + .O(ltOp__15_carry__0_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__0_i_5 + (.I0(minTimeCounter_low_reg[15]), + .I1(minTime[15]), + .I2(minTimeCounter_low_reg[14]), + .I3(minTime[14]), + .O(ltOp__15_carry__0_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__0_i_6 + (.I0(minTimeCounter_low_reg[13]), + .I1(minTime[13]), + .I2(minTimeCounter_low_reg[12]), + .I3(minTime[12]), + .O(ltOp__15_carry__0_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__0_i_7 + (.I0(minTimeCounter_low_reg[11]), + .I1(minTime[11]), + .I2(minTimeCounter_low_reg[10]), + .I3(minTime[10]), + .O(ltOp__15_carry__0_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__0_i_8 + (.I0(minTimeCounter_low_reg[9]), + .I1(minTime[9]), + .I2(minTimeCounter_low_reg[8]), + .I3(minTime[8]), + .O(ltOp__15_carry__0_i_8_n_0)); + CARRY4 ltOp__15_carry__1 + (.CI(ltOp__15_carry__0_n_0), + .CO({ltOp__15_carry__1_n_0,ltOp__15_carry__1_n_1,ltOp__15_carry__1_n_2,ltOp__15_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp__15_carry__1_i_1_n_0,ltOp__15_carry__1_i_2_n_0,ltOp__15_carry__1_i_3_n_0,ltOp__15_carry__1_i_4_n_0}), + .O(NLW_ltOp__15_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp__15_carry__1_i_5_n_0,ltOp__15_carry__1_i_6_n_0,ltOp__15_carry__1_i_7_n_0,ltOp__15_carry__1_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__1_i_1 + (.I0(minTime[23]), + .I1(minTimeCounter_low_reg[23]), + .I2(minTime[22]), + .I3(minTimeCounter_low_reg[22]), + .O(ltOp__15_carry__1_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__1_i_2 + (.I0(minTime[21]), + .I1(minTimeCounter_low_reg[21]), + .I2(minTime[20]), + .I3(minTimeCounter_low_reg[20]), + .O(ltOp__15_carry__1_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__1_i_3 + (.I0(minTime[19]), + .I1(minTimeCounter_low_reg[19]), + .I2(minTime[18]), + .I3(minTimeCounter_low_reg[18]), + .O(ltOp__15_carry__1_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__1_i_4 + (.I0(minTime[17]), + .I1(minTimeCounter_low_reg[17]), + .I2(minTime[16]), + .I3(minTimeCounter_low_reg[16]), + .O(ltOp__15_carry__1_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__1_i_5 + (.I0(minTimeCounter_low_reg[23]), + .I1(minTime[23]), + .I2(minTimeCounter_low_reg[22]), + .I3(minTime[22]), + .O(ltOp__15_carry__1_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__1_i_6 + (.I0(minTimeCounter_low_reg[21]), + .I1(minTime[21]), + .I2(minTimeCounter_low_reg[20]), + .I3(minTime[20]), + .O(ltOp__15_carry__1_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__1_i_7 + (.I0(minTimeCounter_low_reg[19]), + .I1(minTime[19]), + .I2(minTimeCounter_low_reg[18]), + .I3(minTime[18]), + .O(ltOp__15_carry__1_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__1_i_8 + (.I0(minTimeCounter_low_reg[17]), + .I1(minTime[17]), + .I2(minTimeCounter_low_reg[16]), + .I3(minTime[16]), + .O(ltOp__15_carry__1_i_8_n_0)); + CARRY4 ltOp__15_carry__2 + (.CI(ltOp__15_carry__1_n_0), + .CO({ltOp__15_carry__2_n_0,ltOp__15_carry__2_n_1,ltOp__15_carry__2_n_2,ltOp__15_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp__15_carry__2_i_1_n_0,ltOp__15_carry__2_i_2_n_0,ltOp__15_carry__2_i_3_n_0,ltOp__15_carry__2_i_4_n_0}), + .O(NLW_ltOp__15_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp__15_carry__2_i_5_n_0,ltOp__15_carry__2_i_6_n_0,ltOp__15_carry__2_i_7_n_0,ltOp__15_carry__2_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__2_i_1 + (.I0(minTime[31]), + .I1(minTimeCounter_low_reg[31]), + .I2(minTime[30]), + .I3(minTimeCounter_low_reg[30]), + .O(ltOp__15_carry__2_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__2_i_2 + (.I0(minTime[29]), + .I1(minTimeCounter_low_reg[29]), + .I2(minTime[28]), + .I3(minTimeCounter_low_reg[28]), + .O(ltOp__15_carry__2_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__2_i_3 + (.I0(minTime[27]), + .I1(minTimeCounter_low_reg[27]), + .I2(minTime[26]), + .I3(minTimeCounter_low_reg[26]), + .O(ltOp__15_carry__2_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__2_i_4 + (.I0(minTime[25]), + .I1(minTimeCounter_low_reg[25]), + .I2(minTime[24]), + .I3(minTimeCounter_low_reg[24]), + .O(ltOp__15_carry__2_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__2_i_5 + (.I0(minTimeCounter_low_reg[31]), + .I1(minTime[31]), + .I2(minTimeCounter_low_reg[30]), + .I3(minTime[30]), + .O(ltOp__15_carry__2_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__2_i_6 + (.I0(minTimeCounter_low_reg[29]), + .I1(minTime[29]), + .I2(minTimeCounter_low_reg[28]), + .I3(minTime[28]), + .O(ltOp__15_carry__2_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__2_i_7 + (.I0(minTimeCounter_low_reg[27]), + .I1(minTime[27]), + .I2(minTimeCounter_low_reg[26]), + .I3(minTime[26]), + .O(ltOp__15_carry__2_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__2_i_8 + (.I0(minTimeCounter_low_reg[25]), + .I1(minTime[25]), + .I2(minTimeCounter_low_reg[24]), + .I3(minTime[24]), + .O(ltOp__15_carry__2_i_8_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry_i_1 + (.I0(minTime[7]), + .I1(minTimeCounter_low_reg[7]), + .I2(minTime[6]), + .I3(minTimeCounter_low_reg[6]), + .O(ltOp__15_carry_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry_i_2 + (.I0(minTime[5]), + .I1(minTimeCounter_low_reg[5]), + .I2(minTime[4]), + .I3(minTimeCounter_low_reg[4]), + .O(ltOp__15_carry_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry_i_3 + (.I0(minTime[3]), + .I1(minTimeCounter_low_reg[3]), + .I2(minTime[2]), + .I3(minTimeCounter_low_reg[2]), + .O(ltOp__15_carry_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry_i_4 + (.I0(minTime[1]), + .I1(minTimeCounter_low_reg[1]), + .I2(minTime[0]), + .I3(minTimeCounter_low_reg[0]), + .O(ltOp__15_carry_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry_i_5 + (.I0(minTimeCounter_low_reg[7]), + .I1(minTime[7]), + .I2(minTimeCounter_low_reg[6]), + .I3(minTime[6]), + .O(ltOp__15_carry_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry_i_6 + (.I0(minTimeCounter_low_reg[5]), + .I1(minTime[5]), + .I2(minTimeCounter_low_reg[4]), + .I3(minTime[4]), + .O(ltOp__15_carry_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry_i_7 + (.I0(minTimeCounter_low_reg[3]), + .I1(minTime[3]), + .I2(minTimeCounter_low_reg[2]), + .I3(minTime[2]), + .O(ltOp__15_carry_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry_i_8 + (.I0(minTimeCounter_low_reg[1]), + .I1(minTime[1]), + .I2(minTimeCounter_low_reg[0]), + .I3(minTime[0]), + .O(ltOp__15_carry_i_8_n_0)); + CARRY4 ltOp__31_carry + (.CI(1'b0), + .CO({ltOp__31_carry_n_0,ltOp__31_carry_n_1,ltOp__31_carry_n_2,ltOp__31_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp__31_carry_i_1_n_0,ltOp__31_carry_i_2_n_0,ltOp__31_carry_i_3_n_0,ltOp__31_carry_i_4_n_0}), + .O(NLW_ltOp__31_carry_O_UNCONNECTED[3:0]), + .S({ltOp__31_carry_i_5_n_0,ltOp__31_carry_i_6_n_0,ltOp__31_carry_i_7_n_0,ltOp__31_carry_i_8_n_0})); + CARRY4 ltOp__31_carry__0 + (.CI(ltOp__31_carry_n_0), + .CO({ltOp__31_carry__0_n_0,ltOp__31_carry__0_n_1,ltOp__31_carry__0_n_2,ltOp__31_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp__31_carry_i_1__0_n_0,ltOp__31_carry_i_2__0_n_0,ltOp__31_carry_i_3__0_n_0,ltOp__31_carry_i_4__0_n_0}), + .O(NLW_ltOp__31_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp__31_carry_i_5__0_n_0,ltOp__31_carry_i_6__0_n_0,ltOp__31_carry_i_7__0_n_0,ltOp__31_carry_i_8__0_n_0})); + CARRY4 ltOp__31_carry__1 + (.CI(ltOp__31_carry__0_n_0), + .CO({ltOp__31_carry__1_n_0,ltOp__31_carry__1_n_1,ltOp__31_carry__1_n_2,ltOp__31_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp__31_carry_i_1__1_n_0,ltOp__31_carry_i_2__1_n_0,ltOp__31_carry_i_3__1_n_0,ltOp__31_carry_i_4__1_n_0}), + .O(NLW_ltOp__31_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp__31_carry_i_5__1_n_0,ltOp__31_carry_i_6__1_n_0,ltOp__31_carry_i_7__1_n_0,ltOp__31_carry_i_8__1_n_0})); + CARRY4 ltOp__31_carry__2 + (.CI(ltOp__31_carry__1_n_0), + .CO({ltOp__31_carry__2_n_0,ltOp__31_carry__2_n_1,ltOp__31_carry__2_n_2,ltOp__31_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp__31_carry_i_1__2_n_0,ltOp__31_carry_i_2__2_n_0,ltOp__31_carry_i_3__2_n_0,ltOp__31_carry_i_4__2_n_0}), + .O(NLW_ltOp__31_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp__31_carry_i_5__2_n_0,ltOp__31_carry_i_6__2_n_0,ltOp__31_carry_i_7__2_n_0,ltOp__31_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_1 + (.I0(minTime[7]), + .I1(minTimeCounter_high_reg[7]), + .I2(minTime[6]), + .I3(minTimeCounter_high_reg[6]), + .O(ltOp__31_carry_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_1__0 + (.I0(minTime[15]), + .I1(minTimeCounter_high_reg[15]), + .I2(minTime[14]), + .I3(minTimeCounter_high_reg[14]), + .O(ltOp__31_carry_i_1__0_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_1__1 + (.I0(minTime[23]), + .I1(minTimeCounter_high_reg[23]), + .I2(minTime[22]), + .I3(minTimeCounter_high_reg[22]), + .O(ltOp__31_carry_i_1__1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_1__2 + (.I0(minTime[31]), + .I1(minTimeCounter_high_reg[31]), + .I2(minTime[30]), + .I3(minTimeCounter_high_reg[30]), + .O(ltOp__31_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_2 + (.I0(minTime[5]), + .I1(minTimeCounter_high_reg[5]), + .I2(minTime[4]), + .I3(minTimeCounter_high_reg[4]), + .O(ltOp__31_carry_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_2__0 + (.I0(minTime[13]), + .I1(minTimeCounter_high_reg[13]), + .I2(minTime[12]), + .I3(minTimeCounter_high_reg[12]), + .O(ltOp__31_carry_i_2__0_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_2__1 + (.I0(minTime[21]), + .I1(minTimeCounter_high_reg[21]), + .I2(minTime[20]), + .I3(minTimeCounter_high_reg[20]), + .O(ltOp__31_carry_i_2__1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_2__2 + (.I0(minTime[29]), + .I1(minTimeCounter_high_reg[29]), + .I2(minTime[28]), + .I3(minTimeCounter_high_reg[28]), + .O(ltOp__31_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_3 + (.I0(minTime[3]), + .I1(minTimeCounter_high_reg[3]), + .I2(minTime[2]), + .I3(minTimeCounter_high_reg[2]), + .O(ltOp__31_carry_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_3__0 + (.I0(minTime[11]), + .I1(minTimeCounter_high_reg[11]), + .I2(minTime[10]), + .I3(minTimeCounter_high_reg[10]), + .O(ltOp__31_carry_i_3__0_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_3__1 + (.I0(minTime[19]), + .I1(minTimeCounter_high_reg[19]), + .I2(minTime[18]), + .I3(minTimeCounter_high_reg[18]), + .O(ltOp__31_carry_i_3__1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_3__2 + (.I0(minTime[27]), + .I1(minTimeCounter_high_reg[27]), + .I2(minTime[26]), + .I3(minTimeCounter_high_reg[26]), + .O(ltOp__31_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_4 + (.I0(minTime[1]), + .I1(minTimeCounter_high_reg[1]), + .I2(minTime[0]), + .I3(minTimeCounter_high_reg[0]), + .O(ltOp__31_carry_i_4_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_4__0 + (.I0(minTime[9]), + .I1(minTimeCounter_high_reg[9]), + .I2(minTime[8]), + .I3(minTimeCounter_high_reg[8]), + .O(ltOp__31_carry_i_4__0_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_4__1 + (.I0(minTime[17]), + .I1(minTimeCounter_high_reg[17]), + .I2(minTime[16]), + .I3(minTimeCounter_high_reg[16]), + .O(ltOp__31_carry_i_4__1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_4__2 + (.I0(minTime[25]), + .I1(minTimeCounter_high_reg[25]), + .I2(minTime[24]), + .I3(minTimeCounter_high_reg[24]), + .O(ltOp__31_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_5 + (.I0(minTimeCounter_high_reg[7]), + .I1(minTime[7]), + .I2(minTimeCounter_high_reg[6]), + .I3(minTime[6]), + .O(ltOp__31_carry_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_5__0 + (.I0(minTimeCounter_high_reg[15]), + .I1(minTime[15]), + .I2(minTimeCounter_high_reg[14]), + .I3(minTime[14]), + .O(ltOp__31_carry_i_5__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_5__1 + (.I0(minTimeCounter_high_reg[23]), + .I1(minTime[23]), + .I2(minTimeCounter_high_reg[22]), + .I3(minTime[22]), + .O(ltOp__31_carry_i_5__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_5__2 + (.I0(minTimeCounter_high_reg[31]), + .I1(minTime[31]), + .I2(minTimeCounter_high_reg[30]), + .I3(minTime[30]), + .O(ltOp__31_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_6 + (.I0(minTimeCounter_high_reg[5]), + .I1(minTime[5]), + .I2(minTimeCounter_high_reg[4]), + .I3(minTime[4]), + .O(ltOp__31_carry_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_6__0 + (.I0(minTimeCounter_high_reg[13]), + .I1(minTime[13]), + .I2(minTimeCounter_high_reg[12]), + .I3(minTime[12]), + .O(ltOp__31_carry_i_6__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_6__1 + (.I0(minTimeCounter_high_reg[21]), + .I1(minTime[21]), + .I2(minTimeCounter_high_reg[20]), + .I3(minTime[20]), + .O(ltOp__31_carry_i_6__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_6__2 + (.I0(minTimeCounter_high_reg[29]), + .I1(minTime[29]), + .I2(minTimeCounter_high_reg[28]), + .I3(minTime[28]), + .O(ltOp__31_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_7 + (.I0(minTimeCounter_high_reg[3]), + .I1(minTime[3]), + .I2(minTimeCounter_high_reg[2]), + .I3(minTime[2]), + .O(ltOp__31_carry_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_7__0 + (.I0(minTimeCounter_high_reg[11]), + .I1(minTime[11]), + .I2(minTimeCounter_high_reg[10]), + .I3(minTime[10]), + .O(ltOp__31_carry_i_7__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_7__1 + (.I0(minTimeCounter_high_reg[19]), + .I1(minTime[19]), + .I2(minTimeCounter_high_reg[18]), + .I3(minTime[18]), + .O(ltOp__31_carry_i_7__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_7__2 + (.I0(minTimeCounter_high_reg[27]), + .I1(minTime[27]), + .I2(minTimeCounter_high_reg[26]), + .I3(minTime[26]), + .O(ltOp__31_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_8 + (.I0(minTimeCounter_high_reg[1]), + .I1(minTime[1]), + .I2(minTimeCounter_high_reg[0]), + .I3(minTime[0]), + .O(ltOp__31_carry_i_8_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_8__0 + (.I0(minTimeCounter_high_reg[9]), + .I1(minTime[9]), + .I2(minTimeCounter_high_reg[8]), + .I3(minTime[8]), + .O(ltOp__31_carry_i_8__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_8__1 + (.I0(minTimeCounter_high_reg[17]), + .I1(minTime[17]), + .I2(minTimeCounter_high_reg[16]), + .I3(minTime[16]), + .O(ltOp__31_carry_i_8__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_8__2 + (.I0(minTimeCounter_high_reg[25]), + .I1(minTime[25]), + .I2(minTimeCounter_high_reg[24]), + .I3(minTime[24]), + .O(ltOp__31_carry_i_8__2_n_0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry__0_i_1_n_0,ltOp_carry__0_i_2_n_0,ltOp_carry__0_i_3_n_0,ltOp_carry__0_i_4_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry__0_i_5_n_0,ltOp_carry__0_i_6_n_0,ltOp_carry__0_i_7_n_0,ltOp_carry__0_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__0_i_1 + (.I0(deadTime[15]), + .I1(TimeCounter_reg[15]), + .I2(deadTime[14]), + .I3(TimeCounter_reg[14]), + .O(ltOp_carry__0_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__0_i_2 + (.I0(deadTime[13]), + .I1(TimeCounter_reg[13]), + .I2(deadTime[12]), + .I3(TimeCounter_reg[12]), + .O(ltOp_carry__0_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__0_i_3 + (.I0(deadTime[11]), + .I1(TimeCounter_reg[11]), + .I2(deadTime[10]), + .I3(TimeCounter_reg[10]), + .O(ltOp_carry__0_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__0_i_4 + (.I0(deadTime[9]), + .I1(TimeCounter_reg[9]), + .I2(deadTime[8]), + .I3(TimeCounter_reg[8]), + .O(ltOp_carry__0_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__0_i_5 + (.I0(TimeCounter_reg[15]), + .I1(deadTime[15]), + .I2(TimeCounter_reg[14]), + .I3(deadTime[14]), + .O(ltOp_carry__0_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__0_i_6 + (.I0(TimeCounter_reg[13]), + .I1(deadTime[13]), + .I2(TimeCounter_reg[12]), + .I3(deadTime[12]), + .O(ltOp_carry__0_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__0_i_7 + (.I0(TimeCounter_reg[11]), + .I1(deadTime[11]), + .I2(TimeCounter_reg[10]), + .I3(deadTime[10]), + .O(ltOp_carry__0_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__0_i_8 + (.I0(TimeCounter_reg[9]), + .I1(deadTime[9]), + .I2(TimeCounter_reg[8]), + .I3(deadTime[8]), + .O(ltOp_carry__0_i_8_n_0)); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry__1_i_1_n_0,ltOp_carry__1_i_2_n_0,ltOp_carry__1_i_3_n_0,ltOp_carry__1_i_4_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry__1_i_5_n_0,ltOp_carry__1_i_6_n_0,ltOp_carry__1_i_7_n_0,ltOp_carry__1_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__1_i_1 + (.I0(deadTime[23]), + .I1(TimeCounter_reg[23]), + .I2(deadTime[22]), + .I3(TimeCounter_reg[22]), + .O(ltOp_carry__1_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__1_i_2 + (.I0(deadTime[21]), + .I1(TimeCounter_reg[21]), + .I2(deadTime[20]), + .I3(TimeCounter_reg[20]), + .O(ltOp_carry__1_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__1_i_3 + (.I0(deadTime[19]), + .I1(TimeCounter_reg[19]), + .I2(deadTime[18]), + .I3(TimeCounter_reg[18]), + .O(ltOp_carry__1_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__1_i_4 + (.I0(deadTime[17]), + .I1(TimeCounter_reg[17]), + .I2(deadTime[16]), + .I3(TimeCounter_reg[16]), + .O(ltOp_carry__1_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__1_i_5 + (.I0(TimeCounter_reg[23]), + .I1(deadTime[23]), + .I2(TimeCounter_reg[22]), + .I3(deadTime[22]), + .O(ltOp_carry__1_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__1_i_6 + (.I0(TimeCounter_reg[21]), + .I1(deadTime[21]), + .I2(TimeCounter_reg[20]), + .I3(deadTime[20]), + .O(ltOp_carry__1_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__1_i_7 + (.I0(TimeCounter_reg[19]), + .I1(deadTime[19]), + .I2(TimeCounter_reg[18]), + .I3(deadTime[18]), + .O(ltOp_carry__1_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__1_i_8 + (.I0(TimeCounter_reg[17]), + .I1(deadTime[17]), + .I2(TimeCounter_reg[16]), + .I3(deadTime[16]), + .O(ltOp_carry__1_i_8_n_0)); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({sel,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry__2_i_1_n_0,ltOp_carry__2_i_2_n_0,ltOp_carry__2_i_3_n_0,ltOp_carry__2_i_4_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry__2_i_5_n_0,ltOp_carry__2_i_6_n_0,ltOp_carry__2_i_7_n_0,ltOp_carry__2_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__2_i_1 + (.I0(deadTime[31]), + .I1(TimeCounter_reg[31]), + .I2(deadTime[30]), + .I3(TimeCounter_reg[30]), + .O(ltOp_carry__2_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__2_i_2 + (.I0(deadTime[29]), + .I1(TimeCounter_reg[29]), + .I2(deadTime[28]), + .I3(TimeCounter_reg[28]), + .O(ltOp_carry__2_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__2_i_3 + (.I0(deadTime[27]), + .I1(TimeCounter_reg[27]), + .I2(deadTime[26]), + .I3(TimeCounter_reg[26]), + .O(ltOp_carry__2_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__2_i_4 + (.I0(deadTime[25]), + .I1(TimeCounter_reg[25]), + .I2(deadTime[24]), + .I3(TimeCounter_reg[24]), + .O(ltOp_carry__2_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__2_i_5 + (.I0(TimeCounter_reg[31]), + .I1(deadTime[31]), + .I2(TimeCounter_reg[30]), + .I3(deadTime[30]), + .O(ltOp_carry__2_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__2_i_6 + (.I0(TimeCounter_reg[29]), + .I1(deadTime[29]), + .I2(TimeCounter_reg[28]), + .I3(deadTime[28]), + .O(ltOp_carry__2_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__2_i_7 + (.I0(TimeCounter_reg[27]), + .I1(deadTime[27]), + .I2(TimeCounter_reg[26]), + .I3(deadTime[26]), + .O(ltOp_carry__2_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__2_i_8 + (.I0(TimeCounter_reg[25]), + .I1(deadTime[25]), + .I2(TimeCounter_reg[24]), + .I3(deadTime[24]), + .O(ltOp_carry__2_i_8_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry_i_1 + (.I0(deadTime[7]), + .I1(TimeCounter_reg[7]), + .I2(deadTime[6]), + .I3(TimeCounter_reg[6]), + .O(ltOp_carry_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry_i_2 + (.I0(deadTime[5]), + .I1(TimeCounter_reg[5]), + .I2(deadTime[4]), + .I3(TimeCounter_reg[4]), + .O(ltOp_carry_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry_i_3 + (.I0(deadTime[3]), + .I1(TimeCounter_reg[3]), + .I2(deadTime[2]), + .I3(TimeCounter_reg[2]), + .O(ltOp_carry_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry_i_4 + (.I0(deadTime[1]), + .I1(TimeCounter_reg[1]), + .I2(deadTime[0]), + .I3(TimeCounter_reg[0]), + .O(ltOp_carry_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(TimeCounter_reg[7]), + .I1(deadTime[7]), + .I2(TimeCounter_reg[6]), + .I3(deadTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(TimeCounter_reg[5]), + .I1(deadTime[5]), + .I2(TimeCounter_reg[4]), + .I3(deadTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(TimeCounter_reg[3]), + .I1(deadTime[3]), + .I2(TimeCounter_reg[2]), + .I3(deadTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(TimeCounter_reg[1]), + .I1(deadTime[1]), + .I2(TimeCounter_reg[0]), + .I3(deadTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT6 #( + .INIT(64'h0000000022222F22)) + \minTimeCounter_high[0]_i_1 + (.I0(key1_prev), + .I1(key1_reg_n_0), + .I2(key2_reg_n_0), + .I3(key2_prev), + .I4(breaking_en), + .I5(reset), + .O(\minTimeCounter_high[0]_i_1_n_0 )); + LUT2 #( + .INIT(4'h2)) + \minTimeCounter_high[0]_i_2 + (.I0(ltOp__31_carry__2_n_0), + .I1(reset), + .O(minTimeCounter_high)); + LUT1 #( + .INIT(2'h1)) + \minTimeCounter_high[0]_i_4 + (.I0(minTimeCounter_high_reg[0]), + .O(\minTimeCounter_high[0]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[0] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[0]_i_3_n_7 ), + .Q(minTimeCounter_high_reg[0]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[0]_i_3 + (.CI(1'b0), + .CO({\minTimeCounter_high_reg[0]_i_3_n_0 ,\minTimeCounter_high_reg[0]_i_3_n_1 ,\minTimeCounter_high_reg[0]_i_3_n_2 ,\minTimeCounter_high_reg[0]_i_3_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\minTimeCounter_high_reg[0]_i_3_n_4 ,\minTimeCounter_high_reg[0]_i_3_n_5 ,\minTimeCounter_high_reg[0]_i_3_n_6 ,\minTimeCounter_high_reg[0]_i_3_n_7 }), + .S({minTimeCounter_high_reg[3:1],\minTimeCounter_high[0]_i_4_n_0 })); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[10] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[8]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[10]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[11] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[8]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[11]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[12] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[12]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[12]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[12]_i_1 + (.CI(\minTimeCounter_high_reg[8]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[12]_i_1_n_0 ,\minTimeCounter_high_reg[12]_i_1_n_1 ,\minTimeCounter_high_reg[12]_i_1_n_2 ,\minTimeCounter_high_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[12]_i_1_n_4 ,\minTimeCounter_high_reg[12]_i_1_n_5 ,\minTimeCounter_high_reg[12]_i_1_n_6 ,\minTimeCounter_high_reg[12]_i_1_n_7 }), + .S(minTimeCounter_high_reg[15:12])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[13] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[12]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[13]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[14] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[12]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[14]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[15] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[12]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[15]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[16] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[16]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[16]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[16]_i_1 + (.CI(\minTimeCounter_high_reg[12]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[16]_i_1_n_0 ,\minTimeCounter_high_reg[16]_i_1_n_1 ,\minTimeCounter_high_reg[16]_i_1_n_2 ,\minTimeCounter_high_reg[16]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[16]_i_1_n_4 ,\minTimeCounter_high_reg[16]_i_1_n_5 ,\minTimeCounter_high_reg[16]_i_1_n_6 ,\minTimeCounter_high_reg[16]_i_1_n_7 }), + .S(minTimeCounter_high_reg[19:16])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[17] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[16]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[17]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[18] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[16]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[18]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[19] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[16]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[19]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[1] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[0]_i_3_n_6 ), + .Q(minTimeCounter_high_reg[1]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[20] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[20]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[20]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[20]_i_1 + (.CI(\minTimeCounter_high_reg[16]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[20]_i_1_n_0 ,\minTimeCounter_high_reg[20]_i_1_n_1 ,\minTimeCounter_high_reg[20]_i_1_n_2 ,\minTimeCounter_high_reg[20]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[20]_i_1_n_4 ,\minTimeCounter_high_reg[20]_i_1_n_5 ,\minTimeCounter_high_reg[20]_i_1_n_6 ,\minTimeCounter_high_reg[20]_i_1_n_7 }), + .S(minTimeCounter_high_reg[23:20])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[21] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[20]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[21]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[22] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[20]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[22]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[23] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[20]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[23]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[24] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[24]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[24]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[24]_i_1 + (.CI(\minTimeCounter_high_reg[20]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[24]_i_1_n_0 ,\minTimeCounter_high_reg[24]_i_1_n_1 ,\minTimeCounter_high_reg[24]_i_1_n_2 ,\minTimeCounter_high_reg[24]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[24]_i_1_n_4 ,\minTimeCounter_high_reg[24]_i_1_n_5 ,\minTimeCounter_high_reg[24]_i_1_n_6 ,\minTimeCounter_high_reg[24]_i_1_n_7 }), + .S(minTimeCounter_high_reg[27:24])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[25] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[24]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[25]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[26] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[24]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[26]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[27] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[24]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[27]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[28] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[28]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[28]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[28]_i_1 + (.CI(\minTimeCounter_high_reg[24]_i_1_n_0 ), + .CO({\NLW_minTimeCounter_high_reg[28]_i_1_CO_UNCONNECTED [3],\minTimeCounter_high_reg[28]_i_1_n_1 ,\minTimeCounter_high_reg[28]_i_1_n_2 ,\minTimeCounter_high_reg[28]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[28]_i_1_n_4 ,\minTimeCounter_high_reg[28]_i_1_n_5 ,\minTimeCounter_high_reg[28]_i_1_n_6 ,\minTimeCounter_high_reg[28]_i_1_n_7 }), + .S(minTimeCounter_high_reg[31:28])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[29] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[28]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[29]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[2] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[0]_i_3_n_5 ), + .Q(minTimeCounter_high_reg[2]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[30] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[28]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[30]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[31] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[28]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[31]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[3] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[0]_i_3_n_4 ), + .Q(minTimeCounter_high_reg[3]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[4] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[4]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[4]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[4]_i_1 + (.CI(\minTimeCounter_high_reg[0]_i_3_n_0 ), + .CO({\minTimeCounter_high_reg[4]_i_1_n_0 ,\minTimeCounter_high_reg[4]_i_1_n_1 ,\minTimeCounter_high_reg[4]_i_1_n_2 ,\minTimeCounter_high_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[4]_i_1_n_4 ,\minTimeCounter_high_reg[4]_i_1_n_5 ,\minTimeCounter_high_reg[4]_i_1_n_6 ,\minTimeCounter_high_reg[4]_i_1_n_7 }), + .S(minTimeCounter_high_reg[7:4])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[5] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[4]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[5]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[6] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[4]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[6]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[7] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[4]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[7]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[8] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[8]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[8]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[8]_i_1 + (.CI(\minTimeCounter_high_reg[4]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[8]_i_1_n_0 ,\minTimeCounter_high_reg[8]_i_1_n_1 ,\minTimeCounter_high_reg[8]_i_1_n_2 ,\minTimeCounter_high_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[8]_i_1_n_4 ,\minTimeCounter_high_reg[8]_i_1_n_5 ,\minTimeCounter_high_reg[8]_i_1_n_6 ,\minTimeCounter_high_reg[8]_i_1_n_7 }), + .S(minTimeCounter_high_reg[11:8])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[9] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[8]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[9]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + LUT5 #( + .INIT(32'h0000440F)) + \minTimeCounter_low[0]_i_1 + (.I0(key2_reg_n_0), + .I1(key2_prev), + .I2(\minTimeCounter_low[0]_i_4_n_0 ), + .I3(breaking_en), + .I4(reset), + .O(\minTimeCounter_low[0]_i_1_n_0 )); + LUT2 #( + .INIT(4'h2)) + \minTimeCounter_low[0]_i_2 + (.I0(ltOp__15_carry__2_n_0), + .I1(reset), + .O(minTimeCounter_low)); + LUT4 #( + .INIT(16'hD0DD)) + \minTimeCounter_low[0]_i_4 + (.I0(key4_prev), + .I1(key4_reg_n_0), + .I2(key3_reg_n_0), + .I3(key3_prev), + .O(\minTimeCounter_low[0]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \minTimeCounter_low[0]_i_5 + (.I0(minTimeCounter_low_reg[0]), + .O(\minTimeCounter_low[0]_i_5_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[0] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[0]_i_3_n_7 ), + .Q(minTimeCounter_low_reg[0]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[0]_i_3 + (.CI(1'b0), + .CO({\minTimeCounter_low_reg[0]_i_3_n_0 ,\minTimeCounter_low_reg[0]_i_3_n_1 ,\minTimeCounter_low_reg[0]_i_3_n_2 ,\minTimeCounter_low_reg[0]_i_3_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\minTimeCounter_low_reg[0]_i_3_n_4 ,\minTimeCounter_low_reg[0]_i_3_n_5 ,\minTimeCounter_low_reg[0]_i_3_n_6 ,\minTimeCounter_low_reg[0]_i_3_n_7 }), + .S({minTimeCounter_low_reg[3:1],\minTimeCounter_low[0]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[10] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[8]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[10]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[11] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[8]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[11]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[12] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[12]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[12]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[12]_i_1 + (.CI(\minTimeCounter_low_reg[8]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[12]_i_1_n_0 ,\minTimeCounter_low_reg[12]_i_1_n_1 ,\minTimeCounter_low_reg[12]_i_1_n_2 ,\minTimeCounter_low_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[12]_i_1_n_4 ,\minTimeCounter_low_reg[12]_i_1_n_5 ,\minTimeCounter_low_reg[12]_i_1_n_6 ,\minTimeCounter_low_reg[12]_i_1_n_7 }), + .S(minTimeCounter_low_reg[15:12])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[13] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[12]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[13]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[14] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[12]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[14]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[15] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[12]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[15]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[16] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[16]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[16]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[16]_i_1 + (.CI(\minTimeCounter_low_reg[12]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[16]_i_1_n_0 ,\minTimeCounter_low_reg[16]_i_1_n_1 ,\minTimeCounter_low_reg[16]_i_1_n_2 ,\minTimeCounter_low_reg[16]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[16]_i_1_n_4 ,\minTimeCounter_low_reg[16]_i_1_n_5 ,\minTimeCounter_low_reg[16]_i_1_n_6 ,\minTimeCounter_low_reg[16]_i_1_n_7 }), + .S(minTimeCounter_low_reg[19:16])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[17] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[16]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[17]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[18] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[16]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[18]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[19] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[16]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[19]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[1] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[0]_i_3_n_6 ), + .Q(minTimeCounter_low_reg[1]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[20] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[20]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[20]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[20]_i_1 + (.CI(\minTimeCounter_low_reg[16]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[20]_i_1_n_0 ,\minTimeCounter_low_reg[20]_i_1_n_1 ,\minTimeCounter_low_reg[20]_i_1_n_2 ,\minTimeCounter_low_reg[20]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[20]_i_1_n_4 ,\minTimeCounter_low_reg[20]_i_1_n_5 ,\minTimeCounter_low_reg[20]_i_1_n_6 ,\minTimeCounter_low_reg[20]_i_1_n_7 }), + .S(minTimeCounter_low_reg[23:20])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[21] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[20]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[21]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[22] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[20]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[22]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[23] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[20]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[23]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[24] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[24]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[24]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[24]_i_1 + (.CI(\minTimeCounter_low_reg[20]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[24]_i_1_n_0 ,\minTimeCounter_low_reg[24]_i_1_n_1 ,\minTimeCounter_low_reg[24]_i_1_n_2 ,\minTimeCounter_low_reg[24]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[24]_i_1_n_4 ,\minTimeCounter_low_reg[24]_i_1_n_5 ,\minTimeCounter_low_reg[24]_i_1_n_6 ,\minTimeCounter_low_reg[24]_i_1_n_7 }), + .S(minTimeCounter_low_reg[27:24])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[25] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[24]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[25]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[26] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[24]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[26]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[27] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[24]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[27]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[28] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[28]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[28]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[28]_i_1 + (.CI(\minTimeCounter_low_reg[24]_i_1_n_0 ), + .CO({\NLW_minTimeCounter_low_reg[28]_i_1_CO_UNCONNECTED [3],\minTimeCounter_low_reg[28]_i_1_n_1 ,\minTimeCounter_low_reg[28]_i_1_n_2 ,\minTimeCounter_low_reg[28]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[28]_i_1_n_4 ,\minTimeCounter_low_reg[28]_i_1_n_5 ,\minTimeCounter_low_reg[28]_i_1_n_6 ,\minTimeCounter_low_reg[28]_i_1_n_7 }), + .S(minTimeCounter_low_reg[31:28])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[29] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[28]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[29]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[2] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[0]_i_3_n_5 ), + .Q(minTimeCounter_low_reg[2]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[30] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[28]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[30]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[31] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[28]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[31]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[3] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[0]_i_3_n_4 ), + .Q(minTimeCounter_low_reg[3]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[4] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[4]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[4]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[4]_i_1 + (.CI(\minTimeCounter_low_reg[0]_i_3_n_0 ), + .CO({\minTimeCounter_low_reg[4]_i_1_n_0 ,\minTimeCounter_low_reg[4]_i_1_n_1 ,\minTimeCounter_low_reg[4]_i_1_n_2 ,\minTimeCounter_low_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[4]_i_1_n_4 ,\minTimeCounter_low_reg[4]_i_1_n_5 ,\minTimeCounter_low_reg[4]_i_1_n_6 ,\minTimeCounter_low_reg[4]_i_1_n_7 }), + .S(minTimeCounter_low_reg[7:4])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[5] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[4]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[5]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[6] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[4]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[6]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[7] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[4]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[7]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[8] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[8]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[8]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[8]_i_1 + (.CI(\minTimeCounter_low_reg[4]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[8]_i_1_n_0 ,\minTimeCounter_low_reg[8]_i_1_n_1 ,\minTimeCounter_low_reg[8]_i_1_n_2 ,\minTimeCounter_low_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[8]_i_1_n_4 ,\minTimeCounter_low_reg[8]_i_1_n_5 ,\minTimeCounter_low_reg[8]_i_1_n_6 ,\minTimeCounter_low_reg[8]_i_1_n_7 }), + .S(minTimeCounter_low_reg[11:8])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[9] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[8]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[9]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'hEEFFEEEEE200E2E2)) + minTimeEr_i_1 + (.I0(minTimeEr_i_2_n_0), + .I1(minTimeEr_i_3_n_0), + .I2(minTimeEr_i_4_n_0), + .I3(minTimeEr_i_5_n_0), + .I4(minTimeEr_i_6_n_0), + .I5(minTimeEr_reg_0), + .O(minTimeEr_i_1_n_0)); + LUT4 #( + .INIT(16'h0111)) + minTimeEr_i_2 + (.I0(reset), + .I1(breaking_en), + .I2(minTimeEr_i_6_n_0), + .I3(minTimeEr_i_7_n_0), + .O(minTimeEr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h2)) + minTimeEr_i_3 + (.I0(breaking_en), + .I1(reset), + .O(minTimeEr_i_3_n_0)); + LUT6 #( + .INIT(64'h040404FF00000000)) + minTimeEr_i_4 + (.I0(minTimeOK_low), + .I1(key2_reg_n_0), + .I2(key2_prev), + .I3(minTimeEr_i_8_n_0), + .I4(minTimeOK_high), + .I5(minTime_En), + .O(minTimeEr_i_4_n_0)); + LUT6 #( + .INIT(64'h55555555F755F7F7)) + minTimeEr_i_5 + (.I0(minTimeEr_i_9_n_0), + .I1(key2_prev), + .I2(key2_reg_n_0), + .I3(key1_reg_n_0), + .I4(key1_prev), + .I5(minTimeEr_i_7_n_0), + .O(minTimeEr_i_5_n_0)); + LUT6 #( + .INIT(64'hFBFFFFFFBBFBFBFF)) + minTimeEr_i_6 + (.I0(minTimeOK_low), + .I1(minTime_En), + .I2(key3_prev), + .I3(key3_reg_n_0), + .I4(key4_reg_n_0), + .I5(key4_prev), + .O(minTimeEr_i_6_n_0)); + LUT6 #( + .INIT(64'hFFDFDDDDFFDFFFDF)) + minTimeEr_i_7 + (.I0(minTime_En), + .I1(minTimeOK_high), + .I2(key2_reg_n_0), + .I3(key2_prev), + .I4(key1_prev), + .I5(key1_reg_n_0), + .O(minTimeEr_i_7_n_0)); + LUT2 #( + .INIT(4'hB)) + minTimeEr_i_8 + (.I0(key1_prev), + .I1(key1_reg_n_0), + .O(minTimeEr_i_8_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h1)) + minTimeEr_i_9 + (.I0(breaking_en), + .I1(reset), + .O(minTimeEr_i_9_n_0)); + FDRE #( + .INIT(1'b0)) + minTimeEr_reg + (.C(externalCLK), + .CE(1'b1), + .D(minTimeEr_i_1_n_0), + .Q(minTimeEr_reg_0), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h00AB)) + minTimeOK_high_i_1 + (.I0(minTimeOK_high), + .I1(ltOp__31_carry__2_n_0), + .I2(reset), + .I3(\minTimeCounter_high[0]_i_1_n_0 ), + .O(minTimeOK_high_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + minTimeOK_high_reg + (.C(externalCLK), + .CE(1'b1), + .D(minTimeOK_high_i_1_n_0), + .Q(minTimeOK_high), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'h00AB)) + minTimeOK_low_i_1 + (.I0(minTimeOK_low), + .I1(ltOp__15_carry__2_n_0), + .I2(reset), + .I3(\minTimeCounter_low[0]_i_1_n_0 ), + .O(minTimeOK_low_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + minTimeOK_low_reg + (.C(externalCLK), + .CE(1'b1), + .D(minTimeOK_low_i_1_n_0), + .Q(minTimeOK_low), + .R(1'b0)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1_sim_netlist.vhdl b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1_sim_netlist.vhdl new file mode 100644 index 0000000..426e44f --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1_sim_netlist.vhdl @@ -0,0 +1,4183 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Fri Jun 11 07:49:57 2021 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top Inverter_3lvl_P0N_3lvl_0_1 -prefix +-- Inverter_3lvl_P0N_3lvl_0_1_ Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.vhdl +-- Design : Inverter_3lvl_P0N_3lvl_0_4 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Inverter_3lvl_P0N_3lvl_0_1_P0N_3lvl is + port ( + minTimeEr_reg_0 : out STD_LOGIC; + PWM_out_0 : out STD_LOGIC; + PWM_out_1 : out STD_LOGIC; + PWM_out_2 : out STD_LOGIC; + PWM_out_3 : out STD_LOGIC; + reset : in STD_LOGIC; + externalCLK : in STD_LOGIC; + TKin0 : in STD_LOGIC; + TKin1 : in STD_LOGIC; + breaking_en : in STD_LOGIC; + er : in STD_LOGIC; + ready : in STD_LOGIC; + minTime_En : in STD_LOGIC; + deadTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + minTime : in STD_LOGIC_VECTOR ( 31 downto 0 ) + ); +end Inverter_3lvl_P0N_3lvl_0_1_P0N_3lvl; + +architecture STRUCTURE of Inverter_3lvl_P0N_3lvl_0_1_P0N_3lvl is + signal \FSM_onehot_lineconfig[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[0]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[1]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[2]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[2]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[3]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[4]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[5]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[5]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[5]_i_3_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_3_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_4_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_5_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_6_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[0]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[1]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[2]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[3]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[4]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[5]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[6]\ : STD_LOGIC; + signal PWM_out_0_i_1_n_0 : STD_LOGIC; + signal PWM_out_1_i_1_n_0 : STD_LOGIC; + signal PWM_out_2_i_1_n_0 : STD_LOGIC; + signal PWM_out_3_i_1_n_0 : STD_LOGIC; + signal TKin0_triggered : STD_LOGIC; + signal TKin0_triggered28_out : STD_LOGIC; + signal TKin0_triggered_i_1_n_0 : STD_LOGIC; + signal TKin1_triggered : STD_LOGIC; + signal TKin1_triggered_i_1_n_0 : STD_LOGIC; + signal \TimeCounter[0]_i_2_n_0\ : STD_LOGIC; + signal TimeCounter_reg : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \TimeCounter_reg[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_7\ : STD_LOGIC; + signal deadTimeCounterReset_i_1_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_2_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_3_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_4_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_5_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_6_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_7_n_0 : STD_LOGIC; + signal deadTimeCounterReset_reg_n_0 : STD_LOGIC; + signal deadTimeOK : STD_LOGIC; + signal deadTimeOK_i_1_n_0 : STD_LOGIC; + signal key1_i_1_n_0 : STD_LOGIC; + signal key1_i_2_n_0 : STD_LOGIC; + signal key1_prev : STD_LOGIC; + signal key1_reg_n_0 : STD_LOGIC; + signal key2_i_2_n_0 : STD_LOGIC; + signal key2_prev : STD_LOGIC; + signal key2_reg_n_0 : STD_LOGIC; + signal key3 : STD_LOGIC; + signal key3_i_1_n_0 : STD_LOGIC; + signal key3_prev : STD_LOGIC; + signal key3_reg_n_0 : STD_LOGIC; + signal key4_i_1_n_0 : STD_LOGIC; + signal key4_prev : STD_LOGIC; + signal key4_reg_n_0 : STD_LOGIC; + signal \ltOp__15_carry__0_i_1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_3_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_4_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_5_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_6_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_7_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_8_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_n_1\ : STD_LOGIC; + signal \ltOp__15_carry__0_n_2\ : STD_LOGIC; + signal \ltOp__15_carry__0_n_3\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_3_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_4_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_5_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_6_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_7_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_8_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_n_1\ : STD_LOGIC; + signal \ltOp__15_carry__1_n_2\ : STD_LOGIC; + signal \ltOp__15_carry__1_n_3\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_3_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_4_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_5_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_6_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_7_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_8_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_n_1\ : STD_LOGIC; + signal \ltOp__15_carry__2_n_2\ : STD_LOGIC; + signal \ltOp__15_carry__2_n_3\ : STD_LOGIC; + signal \ltOp__15_carry_i_1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_3_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_4_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_5_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_6_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_7_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_8_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_n_1\ : STD_LOGIC; + signal \ltOp__15_carry_n_2\ : STD_LOGIC; + signal \ltOp__15_carry_n_3\ : STD_LOGIC; + signal \ltOp__31_carry__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry__0_n_1\ : STD_LOGIC; + signal \ltOp__31_carry__0_n_2\ : STD_LOGIC; + signal \ltOp__31_carry__0_n_3\ : STD_LOGIC; + signal \ltOp__31_carry__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry__1_n_1\ : STD_LOGIC; + signal \ltOp__31_carry__1_n_2\ : STD_LOGIC; + signal \ltOp__31_carry__1_n_3\ : STD_LOGIC; + signal \ltOp__31_carry__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry__2_n_1\ : STD_LOGIC; + signal \ltOp__31_carry__2_n_2\ : STD_LOGIC; + signal \ltOp__31_carry__2_n_3\ : STD_LOGIC; + signal \ltOp__31_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_1__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_2__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_3__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_3_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_4__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_4_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_5__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_5_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_6__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_6_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_7__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_7_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_8__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_8_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_n_1\ : STD_LOGIC; + signal \ltOp__31_carry_n_2\ : STD_LOGIC; + signal \ltOp__31_carry_n_3\ : STD_LOGIC; + signal \ltOp_carry__0_i_1_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_2_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_3_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_4_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_5_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_6_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_7_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_8_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_i_1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_2_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_3_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_4_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_5_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_6_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_7_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_8_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_i_1_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_2_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_3_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_4_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_5_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_6_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_7_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_8_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal minTimeCounter_high : STD_LOGIC; + signal \minTimeCounter_high[0]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high[0]_i_4_n_0\ : STD_LOGIC; + signal minTimeCounter_high_reg : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \minTimeCounter_high_reg[0]_i_3_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_7\ : STD_LOGIC; + signal minTimeCounter_low : STD_LOGIC; + signal \minTimeCounter_low[0]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low[0]_i_4_n_0\ : STD_LOGIC; + signal \minTimeCounter_low[0]_i_5_n_0\ : STD_LOGIC; + signal minTimeCounter_low_reg : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \minTimeCounter_low_reg[0]_i_3_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_7\ : STD_LOGIC; + signal minTimeEr_i_1_n_0 : STD_LOGIC; + signal minTimeEr_i_2_n_0 : STD_LOGIC; + signal minTimeEr_i_3_n_0 : STD_LOGIC; + signal minTimeEr_i_4_n_0 : STD_LOGIC; + signal minTimeEr_i_5_n_0 : STD_LOGIC; + signal minTimeEr_i_6_n_0 : STD_LOGIC; + signal minTimeEr_i_7_n_0 : STD_LOGIC; + signal minTimeEr_i_8_n_0 : STD_LOGIC; + signal minTimeEr_i_9_n_0 : STD_LOGIC; + signal \^mintimeer_reg_0\ : STD_LOGIC; + signal minTimeOK_high : STD_LOGIC; + signal minTimeOK_high_i_1_n_0 : STD_LOGIC; + signal minTimeOK_low : STD_LOGIC; + signal minTimeOK_low_i_1_n_0 : STD_LOGIC; + signal p_0_in : STD_LOGIC; + signal sel : STD_LOGIC; + signal \NLW_TimeCounter_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_ltOp__15_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__15_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__15_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__15_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__31_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__31_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__31_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__31_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_minTimeCounter_high_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_minTimeCounter_low_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[0]_i_2\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[2]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[5]_i_2\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[6]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[6]_i_3\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[6]_i_6\ : label is "soft_lutpair2"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[0]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[1]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[2]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[3]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[4]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[5]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[6]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute SOFT_HLUTNM of PWM_out_0_i_1 : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of PWM_out_1_i_1 : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of deadTimeCounterReset_i_2 : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of deadTimeCounterReset_i_5 : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of deadTimeCounterReset_i_6 : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of deadTimeOK_i_1 : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of key1_i_2 : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of minTimeEr_i_3 : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of minTimeEr_i_9 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of minTimeOK_high_i_1 : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of minTimeOK_low_i_1 : label is "soft_lutpair3"; +begin + minTimeEr_reg_0 <= \^mintimeer_reg_0\; +\FSM_onehot_lineconfig[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFE00000000" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I4 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I5 => \FSM_onehot_lineconfig[0]_i_2_n_0\, + O => \FSM_onehot_lineconfig[0]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[0]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => TKin1, + I1 => TKin0, + O => \FSM_onehot_lineconfig[0]_i_2_n_0\ + ); +\FSM_onehot_lineconfig[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1000FFFF00000000" + ) + port map ( + I0 => TKin1, + I1 => TKin1_triggered, + I2 => TKin0_triggered, + I3 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I4 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I5 => TKin0, + O => \FSM_onehot_lineconfig[1]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00EFEF0F" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I2 => \FSM_onehot_lineconfig[2]_i_2_n_0\, + I3 => TKin0, + I4 => TKin1, + O => \FSM_onehot_lineconfig[2]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"900990099009FFFF" + ) + port map ( + I0 => TKin1, + I1 => TKin1_triggered, + I2 => TKin0, + I3 => TKin0_triggered, + I4 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I5 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + O => \FSM_onehot_lineconfig[2]_i_2_n_0\ + ); +\FSM_onehot_lineconfig[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000055D50000" + ) + port map ( + I0 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I2 => TKin1_triggered, + I3 => TKin0_triggered, + I4 => TKin1, + I5 => TKin0, + O => \FSM_onehot_lineconfig[3]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2230" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I1 => TKin0, + I2 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I3 => TKin1, + O => \FSM_onehot_lineconfig[4]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0CFF0C0D00050005" + ) + port map ( + I0 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I2 => TKin1, + I3 => TKin0, + I4 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I5 => \FSM_onehot_lineconfig[5]_i_3_n_0\, + O => \FSM_onehot_lineconfig[5]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[5]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + O => \FSM_onehot_lineconfig[5]_i_2_n_0\ + ); +\FSM_onehot_lineconfig[5]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TKin0_triggered, + I1 => TKin0, + I2 => TKin1_triggered, + I3 => TKin1, + O => \FSM_onehot_lineconfig[5]_i_3_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => \FSM_onehot_lineconfig[6]_i_3_n_0\, + I1 => \FSM_onehot_lineconfig[6]_i_4_n_0\, + I2 => breaking_en, + O => \FSM_onehot_lineconfig[6]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"5504" + ) + port map ( + I0 => TKin1, + I1 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I2 => TKin0, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + O => \FSM_onehot_lineconfig[6]_i_2_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFEECAE" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I2 => TKin1, + I3 => TKin0, + I4 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + O => \FSM_onehot_lineconfig[6]_i_3_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AABAAAAAFFFFAAAA" + ) + port map ( + I0 => \FSM_onehot_lineconfig[6]_i_5_n_0\, + I1 => er, + I2 => ready, + I3 => \FSM_onehot_lineconfig[6]_i_6_n_0\, + I4 => deadTimeOK, + I5 => \FSM_onehot_lineconfig[2]_i_2_n_0\, + O => \FSM_onehot_lineconfig[6]_i_4_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FC88A0A8" + ) + port map ( + I0 => deadTimeOK, + I1 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I3 => TKin1, + I4 => TKin0, + O => \FSM_onehot_lineconfig[6]_i_5_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF232323" + ) + port map ( + I0 => deadTimeCounterReset_reg_n_0, + I1 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I3 => TKin1, + I4 => TKin0, + O => \FSM_onehot_lineconfig[6]_i_6_n_0\ + ); +\FSM_onehot_lineconfig_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[0]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[0]\, + S => reset + ); +\FSM_onehot_lineconfig_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[1]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[1]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[2]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[2]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[3]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[3]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[4]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[4]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[5]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[5]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[6]_i_2_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[6]\, + R => reset + ); +PWM_out_0_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFEF" + ) + port map ( + I0 => key1_reg_n_0, + I1 => er, + I2 => ready, + I3 => \^mintimeer_reg_0\, + O => PWM_out_0_i_1_n_0 + ); +PWM_out_0_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => PWM_out_0_i_1_n_0, + Q => PWM_out_0, + R => '0' + ); +PWM_out_1_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFEF" + ) + port map ( + I0 => key2_reg_n_0, + I1 => er, + I2 => ready, + I3 => \^mintimeer_reg_0\, + O => PWM_out_1_i_1_n_0 + ); +PWM_out_1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => PWM_out_1_i_1_n_0, + Q => PWM_out_1, + R => '0' + ); +PWM_out_2_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFEF" + ) + port map ( + I0 => key3_reg_n_0, + I1 => \^mintimeer_reg_0\, + I2 => ready, + I3 => er, + I4 => breaking_en, + O => PWM_out_2_i_1_n_0 + ); +PWM_out_2_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => PWM_out_2_i_1_n_0, + Q => PWM_out_2, + R => '0' + ); +PWM_out_3_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFEF" + ) + port map ( + I0 => key4_reg_n_0, + I1 => \^mintimeer_reg_0\, + I2 => ready, + I3 => er, + I4 => breaking_en, + O => PWM_out_3_i_1_n_0 + ); +PWM_out_3_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => PWM_out_3_i_1_n_0, + Q => PWM_out_3, + R => '0' + ); +TKin0_triggered_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA08FFFFAA080000" + ) + port map ( + I0 => TKin0, + I1 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I2 => TKin1, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I4 => TKin0_triggered28_out, + I5 => TKin0_triggered, + O => TKin0_triggered_i_1_n_0 + ); +TKin0_triggered_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => TKin0_triggered_i_1_n_0, + Q => TKin0_triggered, + R => '0' + ); +TKin1_triggered_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA08FFFFAA080000" + ) + port map ( + I0 => TKin1, + I1 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I2 => TKin0, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I4 => TKin0_triggered28_out, + I5 => TKin1_triggered, + O => TKin1_triggered_i_1_n_0 + ); +TKin1_triggered_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"22AA22A820AA2020" + ) + port map ( + I0 => minTimeEr_i_9_n_0, + I1 => TKin1, + I2 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I3 => TKin0, + I4 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I5 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + O => TKin0_triggered28_out + ); +TKin1_triggered_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => TKin1_triggered_i_1_n_0, + Q => TKin1_triggered, + R => '0' + ); +\TimeCounter[0]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => TimeCounter_reg(0), + O => \TimeCounter[0]_i_2_n_0\ + ); +\TimeCounter_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[0]_i_1_n_7\, + Q => TimeCounter_reg(0), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[0]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \TimeCounter_reg[0]_i_1_n_0\, + CO(2) => \TimeCounter_reg[0]_i_1_n_1\, + CO(1) => \TimeCounter_reg[0]_i_1_n_2\, + CO(0) => \TimeCounter_reg[0]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \TimeCounter_reg[0]_i_1_n_4\, + O(2) => \TimeCounter_reg[0]_i_1_n_5\, + O(1) => \TimeCounter_reg[0]_i_1_n_6\, + O(0) => \TimeCounter_reg[0]_i_1_n_7\, + S(3 downto 1) => TimeCounter_reg(3 downto 1), + S(0) => \TimeCounter[0]_i_2_n_0\ + ); +\TimeCounter_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[8]_i_1_n_5\, + Q => TimeCounter_reg(10), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[8]_i_1_n_4\, + Q => TimeCounter_reg(11), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[12]_i_1_n_7\, + Q => TimeCounter_reg(12), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[8]_i_1_n_0\, + CO(3) => \TimeCounter_reg[12]_i_1_n_0\, + CO(2) => \TimeCounter_reg[12]_i_1_n_1\, + CO(1) => \TimeCounter_reg[12]_i_1_n_2\, + CO(0) => \TimeCounter_reg[12]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[12]_i_1_n_4\, + O(2) => \TimeCounter_reg[12]_i_1_n_5\, + O(1) => \TimeCounter_reg[12]_i_1_n_6\, + O(0) => \TimeCounter_reg[12]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(15 downto 12) + ); +\TimeCounter_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[12]_i_1_n_6\, + Q => TimeCounter_reg(13), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[12]_i_1_n_5\, + Q => TimeCounter_reg(14), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[12]_i_1_n_4\, + Q => TimeCounter_reg(15), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[16]_i_1_n_7\, + Q => TimeCounter_reg(16), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[16]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[12]_i_1_n_0\, + CO(3) => \TimeCounter_reg[16]_i_1_n_0\, + CO(2) => \TimeCounter_reg[16]_i_1_n_1\, + CO(1) => \TimeCounter_reg[16]_i_1_n_2\, + CO(0) => \TimeCounter_reg[16]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[16]_i_1_n_4\, + O(2) => \TimeCounter_reg[16]_i_1_n_5\, + O(1) => \TimeCounter_reg[16]_i_1_n_6\, + O(0) => \TimeCounter_reg[16]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(19 downto 16) + ); +\TimeCounter_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[16]_i_1_n_6\, + Q => TimeCounter_reg(17), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[16]_i_1_n_5\, + Q => TimeCounter_reg(18), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[16]_i_1_n_4\, + Q => TimeCounter_reg(19), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[0]_i_1_n_6\, + Q => TimeCounter_reg(1), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[20]_i_1_n_7\, + Q => TimeCounter_reg(20), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[20]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[16]_i_1_n_0\, + CO(3) => \TimeCounter_reg[20]_i_1_n_0\, + CO(2) => \TimeCounter_reg[20]_i_1_n_1\, + CO(1) => \TimeCounter_reg[20]_i_1_n_2\, + CO(0) => \TimeCounter_reg[20]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[20]_i_1_n_4\, + O(2) => \TimeCounter_reg[20]_i_1_n_5\, + O(1) => \TimeCounter_reg[20]_i_1_n_6\, + O(0) => \TimeCounter_reg[20]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(23 downto 20) + ); +\TimeCounter_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[20]_i_1_n_6\, + Q => TimeCounter_reg(21), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[20]_i_1_n_5\, + Q => TimeCounter_reg(22), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[20]_i_1_n_4\, + Q => TimeCounter_reg(23), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[24]_i_1_n_7\, + Q => TimeCounter_reg(24), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[24]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[20]_i_1_n_0\, + CO(3) => \TimeCounter_reg[24]_i_1_n_0\, + CO(2) => \TimeCounter_reg[24]_i_1_n_1\, + CO(1) => \TimeCounter_reg[24]_i_1_n_2\, + CO(0) => \TimeCounter_reg[24]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[24]_i_1_n_4\, + O(2) => \TimeCounter_reg[24]_i_1_n_5\, + O(1) => \TimeCounter_reg[24]_i_1_n_6\, + O(0) => \TimeCounter_reg[24]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(27 downto 24) + ); +\TimeCounter_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[24]_i_1_n_6\, + Q => TimeCounter_reg(25), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[24]_i_1_n_5\, + Q => TimeCounter_reg(26), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[24]_i_1_n_4\, + Q => TimeCounter_reg(27), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[28]_i_1_n_7\, + Q => TimeCounter_reg(28), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[28]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[24]_i_1_n_0\, + CO(3) => \NLW_TimeCounter_reg[28]_i_1_CO_UNCONNECTED\(3), + CO(2) => \TimeCounter_reg[28]_i_1_n_1\, + CO(1) => \TimeCounter_reg[28]_i_1_n_2\, + CO(0) => \TimeCounter_reg[28]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[28]_i_1_n_4\, + O(2) => \TimeCounter_reg[28]_i_1_n_5\, + O(1) => \TimeCounter_reg[28]_i_1_n_6\, + O(0) => \TimeCounter_reg[28]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(31 downto 28) + ); +\TimeCounter_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[28]_i_1_n_6\, + Q => TimeCounter_reg(29), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[0]_i_1_n_5\, + Q => TimeCounter_reg(2), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[28]_i_1_n_5\, + Q => TimeCounter_reg(30), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[28]_i_1_n_4\, + Q => TimeCounter_reg(31), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[0]_i_1_n_4\, + Q => TimeCounter_reg(3), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[4]_i_1_n_7\, + Q => TimeCounter_reg(4), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[0]_i_1_n_0\, + CO(3) => \TimeCounter_reg[4]_i_1_n_0\, + CO(2) => \TimeCounter_reg[4]_i_1_n_1\, + CO(1) => \TimeCounter_reg[4]_i_1_n_2\, + CO(0) => \TimeCounter_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[4]_i_1_n_4\, + O(2) => \TimeCounter_reg[4]_i_1_n_5\, + O(1) => \TimeCounter_reg[4]_i_1_n_6\, + O(0) => \TimeCounter_reg[4]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(7 downto 4) + ); +\TimeCounter_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[4]_i_1_n_6\, + Q => TimeCounter_reg(5), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[4]_i_1_n_5\, + Q => TimeCounter_reg(6), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[4]_i_1_n_4\, + Q => TimeCounter_reg(7), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[8]_i_1_n_7\, + Q => TimeCounter_reg(8), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[4]_i_1_n_0\, + CO(3) => \TimeCounter_reg[8]_i_1_n_0\, + CO(2) => \TimeCounter_reg[8]_i_1_n_1\, + CO(1) => \TimeCounter_reg[8]_i_1_n_2\, + CO(0) => \TimeCounter_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[8]_i_1_n_4\, + O(2) => \TimeCounter_reg[8]_i_1_n_5\, + O(1) => \TimeCounter_reg[8]_i_1_n_6\, + O(0) => \TimeCounter_reg[8]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(11 downto 8) + ); +\TimeCounter_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[8]_i_1_n_6\, + Q => TimeCounter_reg(9), + R => deadTimeCounterReset_reg_n_0 + ); +deadTimeCounterReset_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFE0000000E" + ) + port map ( + I0 => deadTimeCounterReset_i_2_n_0, + I1 => \FSM_onehot_lineconfig[6]_i_4_n_0\, + I2 => reset, + I3 => breaking_en, + I4 => deadTimeCounterReset_i_3_n_0, + I5 => deadTimeCounterReset_reg_n_0, + O => deadTimeCounterReset_i_1_n_0 + ); +deadTimeCounterReset_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + O => deadTimeCounterReset_i_2_n_0 + ); +deadTimeCounterReset_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000022220020" + ) + port map ( + I0 => deadTimeCounterReset_i_4_n_0, + I1 => deadTimeCounterReset_i_2_n_0, + I2 => deadTimeCounterReset_i_5_n_0, + I3 => deadTimeCounterReset_i_6_n_0, + I4 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I5 => deadTimeCounterReset_i_7_n_0, + O => deadTimeCounterReset_i_3_n_0 + ); +deadTimeCounterReset_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"555D555555555555" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I1 => deadTimeOK, + I2 => TKin1, + I3 => TKin1_triggered, + I4 => TKin0, + I5 => TKin0_triggered, + O => deadTimeCounterReset_i_4_n_0 + ); +deadTimeCounterReset_i_5: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => deadTimeOK, + I1 => ready, + I2 => er, + O => deadTimeCounterReset_i_5_n_0 + ); +deadTimeCounterReset_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"F777" + ) + port map ( + I0 => TKin0, + I1 => TKin1, + I2 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I3 => deadTimeCounterReset_reg_n_0, + O => deadTimeCounterReset_i_6_n_0 + ); +deadTimeCounterReset_i_7: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAA2AAAAAAAAAA" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I1 => TKin1, + I2 => TKin0, + I3 => deadTimeOK, + I4 => TKin0_triggered, + I5 => TKin1_triggered, + O => deadTimeCounterReset_i_7_n_0 + ); +deadTimeCounterReset_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => '1', + D => deadTimeCounterReset_i_1_n_0, + Q => deadTimeCounterReset_reg_n_0, + R => '0' + ); +deadTimeOK_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"0D" + ) + port map ( + I0 => sel, + I1 => deadTimeOK, + I2 => deadTimeCounterReset_reg_n_0, + O => deadTimeOK_i_1_n_0 + ); +deadTimeOK_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => deadTimeOK_i_1_n_0, + Q => deadTimeOK, + R => '0' + ); +key1_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"DDDDDDD0DDDDDDDD" + ) + port map ( + I0 => breaking_en, + I1 => TKin0, + I2 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I4 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I5 => key1_i_2_n_0, + O => key1_i_1_n_0 + ); +key1_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I3 => breaking_en, + O => key1_i_2_n_0 + ); +key1_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key1_reg_n_0, + Q => key1_prev, + R => '0' + ); +key1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key1_i_1_n_0, + Q => key1_reg_n_0, + R => '0' + ); +key2_i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => reset, + O => p_0_in + ); +key2_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAFFFFFFFC" + ) + port map ( + I0 => TKin1, + I1 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I4 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I5 => breaking_en, + O => key2_i_2_n_0 + ); +key2_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key2_reg_n_0, + Q => key2_prev, + R => '0' + ); +key2_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key2_i_2_n_0, + Q => key2_reg_n_0, + R => '0' + ); +key3_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAFFFFAAAAFCFF" + ) + port map ( + I0 => key3_reg_n_0, + I1 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I3 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I4 => reset, + I5 => breaking_en, + O => key3_i_1_n_0 + ); +key3_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key3_reg_n_0, + Q => key3_prev, + R => '0' + ); +key3_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => key3_i_1_n_0, + Q => key3_reg_n_0, + R => '0' + ); +key4_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAFFFFAAAAFFFC" + ) + port map ( + I0 => key4_reg_n_0, + I1 => key3, + I2 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I4 => reset, + I5 => breaking_en, + O => key4_i_1_n_0 + ); +key4_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + O => key3 + ); +key4_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key4_reg_n_0, + Q => key4_prev, + R => '0' + ); +key4_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => key4_i_1_n_0, + Q => key4_reg_n_0, + R => '0' + ); +\ltOp__15_carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \ltOp__15_carry_n_0\, + CO(2) => \ltOp__15_carry_n_1\, + CO(1) => \ltOp__15_carry_n_2\, + CO(0) => \ltOp__15_carry_n_3\, + CYINIT => '0', + DI(3) => \ltOp__15_carry_i_1_n_0\, + DI(2) => \ltOp__15_carry_i_2_n_0\, + DI(1) => \ltOp__15_carry_i_3_n_0\, + DI(0) => \ltOp__15_carry_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__15_carry_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__15_carry_i_5_n_0\, + S(2) => \ltOp__15_carry_i_6_n_0\, + S(1) => \ltOp__15_carry_i_7_n_0\, + S(0) => \ltOp__15_carry_i_8_n_0\ + ); +\ltOp__15_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__15_carry_n_0\, + CO(3) => \ltOp__15_carry__0_n_0\, + CO(2) => \ltOp__15_carry__0_n_1\, + CO(1) => \ltOp__15_carry__0_n_2\, + CO(0) => \ltOp__15_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp__15_carry__0_i_1_n_0\, + DI(2) => \ltOp__15_carry__0_i_2_n_0\, + DI(1) => \ltOp__15_carry__0_i_3_n_0\, + DI(0) => \ltOp__15_carry__0_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__15_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__15_carry__0_i_5_n_0\, + S(2) => \ltOp__15_carry__0_i_6_n_0\, + S(1) => \ltOp__15_carry__0_i_7_n_0\, + S(0) => \ltOp__15_carry__0_i_8_n_0\ + ); +\ltOp__15_carry__0_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(15), + I1 => minTimeCounter_low_reg(15), + I2 => minTime(14), + I3 => minTimeCounter_low_reg(14), + O => \ltOp__15_carry__0_i_1_n_0\ + ); +\ltOp__15_carry__0_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(13), + I1 => minTimeCounter_low_reg(13), + I2 => minTime(12), + I3 => minTimeCounter_low_reg(12), + O => \ltOp__15_carry__0_i_2_n_0\ + ); +\ltOp__15_carry__0_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(11), + I1 => minTimeCounter_low_reg(11), + I2 => minTime(10), + I3 => minTimeCounter_low_reg(10), + O => \ltOp__15_carry__0_i_3_n_0\ + ); +\ltOp__15_carry__0_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(9), + I1 => minTimeCounter_low_reg(9), + I2 => minTime(8), + I3 => minTimeCounter_low_reg(8), + O => \ltOp__15_carry__0_i_4_n_0\ + ); +\ltOp__15_carry__0_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(15), + I1 => minTime(15), + I2 => minTimeCounter_low_reg(14), + I3 => minTime(14), + O => \ltOp__15_carry__0_i_5_n_0\ + ); +\ltOp__15_carry__0_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(13), + I1 => minTime(13), + I2 => minTimeCounter_low_reg(12), + I3 => minTime(12), + O => \ltOp__15_carry__0_i_6_n_0\ + ); +\ltOp__15_carry__0_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(11), + I1 => minTime(11), + I2 => minTimeCounter_low_reg(10), + I3 => minTime(10), + O => \ltOp__15_carry__0_i_7_n_0\ + ); +\ltOp__15_carry__0_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(9), + I1 => minTime(9), + I2 => minTimeCounter_low_reg(8), + I3 => minTime(8), + O => \ltOp__15_carry__0_i_8_n_0\ + ); +\ltOp__15_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__15_carry__0_n_0\, + CO(3) => \ltOp__15_carry__1_n_0\, + CO(2) => \ltOp__15_carry__1_n_1\, + CO(1) => \ltOp__15_carry__1_n_2\, + CO(0) => \ltOp__15_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp__15_carry__1_i_1_n_0\, + DI(2) => \ltOp__15_carry__1_i_2_n_0\, + DI(1) => \ltOp__15_carry__1_i_3_n_0\, + DI(0) => \ltOp__15_carry__1_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__15_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__15_carry__1_i_5_n_0\, + S(2) => \ltOp__15_carry__1_i_6_n_0\, + S(1) => \ltOp__15_carry__1_i_7_n_0\, + S(0) => \ltOp__15_carry__1_i_8_n_0\ + ); +\ltOp__15_carry__1_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(23), + I1 => minTimeCounter_low_reg(23), + I2 => minTime(22), + I3 => minTimeCounter_low_reg(22), + O => \ltOp__15_carry__1_i_1_n_0\ + ); +\ltOp__15_carry__1_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(21), + I1 => minTimeCounter_low_reg(21), + I2 => minTime(20), + I3 => minTimeCounter_low_reg(20), + O => \ltOp__15_carry__1_i_2_n_0\ + ); +\ltOp__15_carry__1_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(19), + I1 => minTimeCounter_low_reg(19), + I2 => minTime(18), + I3 => minTimeCounter_low_reg(18), + O => \ltOp__15_carry__1_i_3_n_0\ + ); +\ltOp__15_carry__1_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(17), + I1 => minTimeCounter_low_reg(17), + I2 => minTime(16), + I3 => minTimeCounter_low_reg(16), + O => \ltOp__15_carry__1_i_4_n_0\ + ); +\ltOp__15_carry__1_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(23), + I1 => minTime(23), + I2 => minTimeCounter_low_reg(22), + I3 => minTime(22), + O => \ltOp__15_carry__1_i_5_n_0\ + ); +\ltOp__15_carry__1_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(21), + I1 => minTime(21), + I2 => minTimeCounter_low_reg(20), + I3 => minTime(20), + O => \ltOp__15_carry__1_i_6_n_0\ + ); +\ltOp__15_carry__1_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(19), + I1 => minTime(19), + I2 => minTimeCounter_low_reg(18), + I3 => minTime(18), + O => \ltOp__15_carry__1_i_7_n_0\ + ); +\ltOp__15_carry__1_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(17), + I1 => minTime(17), + I2 => minTimeCounter_low_reg(16), + I3 => minTime(16), + O => \ltOp__15_carry__1_i_8_n_0\ + ); +\ltOp__15_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__15_carry__1_n_0\, + CO(3) => \ltOp__15_carry__2_n_0\, + CO(2) => \ltOp__15_carry__2_n_1\, + CO(1) => \ltOp__15_carry__2_n_2\, + CO(0) => \ltOp__15_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp__15_carry__2_i_1_n_0\, + DI(2) => \ltOp__15_carry__2_i_2_n_0\, + DI(1) => \ltOp__15_carry__2_i_3_n_0\, + DI(0) => \ltOp__15_carry__2_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__15_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__15_carry__2_i_5_n_0\, + S(2) => \ltOp__15_carry__2_i_6_n_0\, + S(1) => \ltOp__15_carry__2_i_7_n_0\, + S(0) => \ltOp__15_carry__2_i_8_n_0\ + ); +\ltOp__15_carry__2_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(31), + I1 => minTimeCounter_low_reg(31), + I2 => minTime(30), + I3 => minTimeCounter_low_reg(30), + O => \ltOp__15_carry__2_i_1_n_0\ + ); +\ltOp__15_carry__2_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(29), + I1 => minTimeCounter_low_reg(29), + I2 => minTime(28), + I3 => minTimeCounter_low_reg(28), + O => \ltOp__15_carry__2_i_2_n_0\ + ); +\ltOp__15_carry__2_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(27), + I1 => minTimeCounter_low_reg(27), + I2 => minTime(26), + I3 => minTimeCounter_low_reg(26), + O => \ltOp__15_carry__2_i_3_n_0\ + ); +\ltOp__15_carry__2_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(25), + I1 => minTimeCounter_low_reg(25), + I2 => minTime(24), + I3 => minTimeCounter_low_reg(24), + O => \ltOp__15_carry__2_i_4_n_0\ + ); +\ltOp__15_carry__2_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(31), + I1 => minTime(31), + I2 => minTimeCounter_low_reg(30), + I3 => minTime(30), + O => \ltOp__15_carry__2_i_5_n_0\ + ); +\ltOp__15_carry__2_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(29), + I1 => minTime(29), + I2 => minTimeCounter_low_reg(28), + I3 => minTime(28), + O => \ltOp__15_carry__2_i_6_n_0\ + ); +\ltOp__15_carry__2_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(27), + I1 => minTime(27), + I2 => minTimeCounter_low_reg(26), + I3 => minTime(26), + O => \ltOp__15_carry__2_i_7_n_0\ + ); +\ltOp__15_carry__2_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(25), + I1 => minTime(25), + I2 => minTimeCounter_low_reg(24), + I3 => minTime(24), + O => \ltOp__15_carry__2_i_8_n_0\ + ); +\ltOp__15_carry_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(7), + I1 => minTimeCounter_low_reg(7), + I2 => minTime(6), + I3 => minTimeCounter_low_reg(6), + O => \ltOp__15_carry_i_1_n_0\ + ); +\ltOp__15_carry_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(5), + I1 => minTimeCounter_low_reg(5), + I2 => minTime(4), + I3 => minTimeCounter_low_reg(4), + O => \ltOp__15_carry_i_2_n_0\ + ); +\ltOp__15_carry_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(3), + I1 => minTimeCounter_low_reg(3), + I2 => minTime(2), + I3 => minTimeCounter_low_reg(2), + O => \ltOp__15_carry_i_3_n_0\ + ); +\ltOp__15_carry_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(1), + I1 => minTimeCounter_low_reg(1), + I2 => minTime(0), + I3 => minTimeCounter_low_reg(0), + O => \ltOp__15_carry_i_4_n_0\ + ); +\ltOp__15_carry_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(7), + I1 => minTime(7), + I2 => minTimeCounter_low_reg(6), + I3 => minTime(6), + O => \ltOp__15_carry_i_5_n_0\ + ); +\ltOp__15_carry_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(5), + I1 => minTime(5), + I2 => minTimeCounter_low_reg(4), + I3 => minTime(4), + O => \ltOp__15_carry_i_6_n_0\ + ); +\ltOp__15_carry_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(3), + I1 => minTime(3), + I2 => minTimeCounter_low_reg(2), + I3 => minTime(2), + O => \ltOp__15_carry_i_7_n_0\ + ); +\ltOp__15_carry_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(1), + I1 => minTime(1), + I2 => minTimeCounter_low_reg(0), + I3 => minTime(0), + O => \ltOp__15_carry_i_8_n_0\ + ); +\ltOp__31_carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \ltOp__31_carry_n_0\, + CO(2) => \ltOp__31_carry_n_1\, + CO(1) => \ltOp__31_carry_n_2\, + CO(0) => \ltOp__31_carry_n_3\, + CYINIT => '0', + DI(3) => \ltOp__31_carry_i_1_n_0\, + DI(2) => \ltOp__31_carry_i_2_n_0\, + DI(1) => \ltOp__31_carry_i_3_n_0\, + DI(0) => \ltOp__31_carry_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__31_carry_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__31_carry_i_5_n_0\, + S(2) => \ltOp__31_carry_i_6_n_0\, + S(1) => \ltOp__31_carry_i_7_n_0\, + S(0) => \ltOp__31_carry_i_8_n_0\ + ); +\ltOp__31_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__31_carry_n_0\, + CO(3) => \ltOp__31_carry__0_n_0\, + CO(2) => \ltOp__31_carry__0_n_1\, + CO(1) => \ltOp__31_carry__0_n_2\, + CO(0) => \ltOp__31_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp__31_carry_i_1__0_n_0\, + DI(2) => \ltOp__31_carry_i_2__0_n_0\, + DI(1) => \ltOp__31_carry_i_3__0_n_0\, + DI(0) => \ltOp__31_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp__31_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__31_carry_i_5__0_n_0\, + S(2) => \ltOp__31_carry_i_6__0_n_0\, + S(1) => \ltOp__31_carry_i_7__0_n_0\, + S(0) => \ltOp__31_carry_i_8__0_n_0\ + ); +\ltOp__31_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__31_carry__0_n_0\, + CO(3) => \ltOp__31_carry__1_n_0\, + CO(2) => \ltOp__31_carry__1_n_1\, + CO(1) => \ltOp__31_carry__1_n_2\, + CO(0) => \ltOp__31_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp__31_carry_i_1__1_n_0\, + DI(2) => \ltOp__31_carry_i_2__1_n_0\, + DI(1) => \ltOp__31_carry_i_3__1_n_0\, + DI(0) => \ltOp__31_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp__31_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__31_carry_i_5__1_n_0\, + S(2) => \ltOp__31_carry_i_6__1_n_0\, + S(1) => \ltOp__31_carry_i_7__1_n_0\, + S(0) => \ltOp__31_carry_i_8__1_n_0\ + ); +\ltOp__31_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__31_carry__1_n_0\, + CO(3) => \ltOp__31_carry__2_n_0\, + CO(2) => \ltOp__31_carry__2_n_1\, + CO(1) => \ltOp__31_carry__2_n_2\, + CO(0) => \ltOp__31_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp__31_carry_i_1__2_n_0\, + DI(2) => \ltOp__31_carry_i_2__2_n_0\, + DI(1) => \ltOp__31_carry_i_3__2_n_0\, + DI(0) => \ltOp__31_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp__31_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__31_carry_i_5__2_n_0\, + S(2) => \ltOp__31_carry_i_6__2_n_0\, + S(1) => \ltOp__31_carry_i_7__2_n_0\, + S(0) => \ltOp__31_carry_i_8__2_n_0\ + ); +\ltOp__31_carry_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(7), + I1 => minTimeCounter_high_reg(7), + I2 => minTime(6), + I3 => minTimeCounter_high_reg(6), + O => \ltOp__31_carry_i_1_n_0\ + ); +\ltOp__31_carry_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(15), + I1 => minTimeCounter_high_reg(15), + I2 => minTime(14), + I3 => minTimeCounter_high_reg(14), + O => \ltOp__31_carry_i_1__0_n_0\ + ); +\ltOp__31_carry_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(23), + I1 => minTimeCounter_high_reg(23), + I2 => minTime(22), + I3 => minTimeCounter_high_reg(22), + O => \ltOp__31_carry_i_1__1_n_0\ + ); +\ltOp__31_carry_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(31), + I1 => minTimeCounter_high_reg(31), + I2 => minTime(30), + I3 => minTimeCounter_high_reg(30), + O => \ltOp__31_carry_i_1__2_n_0\ + ); +\ltOp__31_carry_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(5), + I1 => minTimeCounter_high_reg(5), + I2 => minTime(4), + I3 => minTimeCounter_high_reg(4), + O => \ltOp__31_carry_i_2_n_0\ + ); +\ltOp__31_carry_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(13), + I1 => minTimeCounter_high_reg(13), + I2 => minTime(12), + I3 => minTimeCounter_high_reg(12), + O => \ltOp__31_carry_i_2__0_n_0\ + ); +\ltOp__31_carry_i_2__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(21), + I1 => minTimeCounter_high_reg(21), + I2 => minTime(20), + I3 => minTimeCounter_high_reg(20), + O => \ltOp__31_carry_i_2__1_n_0\ + ); +\ltOp__31_carry_i_2__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(29), + I1 => minTimeCounter_high_reg(29), + I2 => minTime(28), + I3 => minTimeCounter_high_reg(28), + O => \ltOp__31_carry_i_2__2_n_0\ + ); +\ltOp__31_carry_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(3), + I1 => minTimeCounter_high_reg(3), + I2 => minTime(2), + I3 => minTimeCounter_high_reg(2), + O => \ltOp__31_carry_i_3_n_0\ + ); +\ltOp__31_carry_i_3__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(11), + I1 => minTimeCounter_high_reg(11), + I2 => minTime(10), + I3 => minTimeCounter_high_reg(10), + O => \ltOp__31_carry_i_3__0_n_0\ + ); +\ltOp__31_carry_i_3__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(19), + I1 => minTimeCounter_high_reg(19), + I2 => minTime(18), + I3 => minTimeCounter_high_reg(18), + O => \ltOp__31_carry_i_3__1_n_0\ + ); +\ltOp__31_carry_i_3__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(27), + I1 => minTimeCounter_high_reg(27), + I2 => minTime(26), + I3 => minTimeCounter_high_reg(26), + O => \ltOp__31_carry_i_3__2_n_0\ + ); +\ltOp__31_carry_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(1), + I1 => minTimeCounter_high_reg(1), + I2 => minTime(0), + I3 => minTimeCounter_high_reg(0), + O => \ltOp__31_carry_i_4_n_0\ + ); +\ltOp__31_carry_i_4__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(9), + I1 => minTimeCounter_high_reg(9), + I2 => minTime(8), + I3 => minTimeCounter_high_reg(8), + O => \ltOp__31_carry_i_4__0_n_0\ + ); +\ltOp__31_carry_i_4__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(17), + I1 => minTimeCounter_high_reg(17), + I2 => minTime(16), + I3 => minTimeCounter_high_reg(16), + O => \ltOp__31_carry_i_4__1_n_0\ + ); +\ltOp__31_carry_i_4__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(25), + I1 => minTimeCounter_high_reg(25), + I2 => minTime(24), + I3 => minTimeCounter_high_reg(24), + O => \ltOp__31_carry_i_4__2_n_0\ + ); +\ltOp__31_carry_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(7), + I1 => minTime(7), + I2 => minTimeCounter_high_reg(6), + I3 => minTime(6), + O => \ltOp__31_carry_i_5_n_0\ + ); +\ltOp__31_carry_i_5__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(15), + I1 => minTime(15), + I2 => minTimeCounter_high_reg(14), + I3 => minTime(14), + O => \ltOp__31_carry_i_5__0_n_0\ + ); +\ltOp__31_carry_i_5__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(23), + I1 => minTime(23), + I2 => minTimeCounter_high_reg(22), + I3 => minTime(22), + O => \ltOp__31_carry_i_5__1_n_0\ + ); +\ltOp__31_carry_i_5__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(31), + I1 => minTime(31), + I2 => minTimeCounter_high_reg(30), + I3 => minTime(30), + O => \ltOp__31_carry_i_5__2_n_0\ + ); +\ltOp__31_carry_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(5), + I1 => minTime(5), + I2 => minTimeCounter_high_reg(4), + I3 => minTime(4), + O => \ltOp__31_carry_i_6_n_0\ + ); +\ltOp__31_carry_i_6__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(13), + I1 => minTime(13), + I2 => minTimeCounter_high_reg(12), + I3 => minTime(12), + O => \ltOp__31_carry_i_6__0_n_0\ + ); +\ltOp__31_carry_i_6__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(21), + I1 => minTime(21), + I2 => minTimeCounter_high_reg(20), + I3 => minTime(20), + O => \ltOp__31_carry_i_6__1_n_0\ + ); +\ltOp__31_carry_i_6__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(29), + I1 => minTime(29), + I2 => minTimeCounter_high_reg(28), + I3 => minTime(28), + O => \ltOp__31_carry_i_6__2_n_0\ + ); +\ltOp__31_carry_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(3), + I1 => minTime(3), + I2 => minTimeCounter_high_reg(2), + I3 => minTime(2), + O => \ltOp__31_carry_i_7_n_0\ + ); +\ltOp__31_carry_i_7__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(11), + I1 => minTime(11), + I2 => minTimeCounter_high_reg(10), + I3 => minTime(10), + O => \ltOp__31_carry_i_7__0_n_0\ + ); +\ltOp__31_carry_i_7__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(19), + I1 => minTime(19), + I2 => minTimeCounter_high_reg(18), + I3 => minTime(18), + O => \ltOp__31_carry_i_7__1_n_0\ + ); +\ltOp__31_carry_i_7__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(27), + I1 => minTime(27), + I2 => minTimeCounter_high_reg(26), + I3 => minTime(26), + O => \ltOp__31_carry_i_7__2_n_0\ + ); +\ltOp__31_carry_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(1), + I1 => minTime(1), + I2 => minTimeCounter_high_reg(0), + I3 => minTime(0), + O => \ltOp__31_carry_i_8_n_0\ + ); +\ltOp__31_carry_i_8__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(9), + I1 => minTime(9), + I2 => minTimeCounter_high_reg(8), + I3 => minTime(8), + O => \ltOp__31_carry_i_8__0_n_0\ + ); +\ltOp__31_carry_i_8__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(17), + I1 => minTime(17), + I2 => minTimeCounter_high_reg(16), + I3 => minTime(16), + O => \ltOp__31_carry_i_8__1_n_0\ + ); +\ltOp__31_carry_i_8__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(25), + I1 => minTime(25), + I2 => minTimeCounter_high_reg(24), + I3 => minTime(24), + O => \ltOp__31_carry_i_8__2_n_0\ + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry__0_i_1_n_0\, + DI(2) => \ltOp_carry__0_i_2_n_0\, + DI(1) => \ltOp_carry__0_i_3_n_0\, + DI(0) => \ltOp_carry__0_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry__0_i_5_n_0\, + S(2) => \ltOp_carry__0_i_6_n_0\, + S(1) => \ltOp_carry__0_i_7_n_0\, + S(0) => \ltOp_carry__0_i_8_n_0\ + ); +\ltOp_carry__0_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(15), + I1 => TimeCounter_reg(15), + I2 => deadTime(14), + I3 => TimeCounter_reg(14), + O => \ltOp_carry__0_i_1_n_0\ + ); +\ltOp_carry__0_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(13), + I1 => TimeCounter_reg(13), + I2 => deadTime(12), + I3 => TimeCounter_reg(12), + O => \ltOp_carry__0_i_2_n_0\ + ); +\ltOp_carry__0_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(11), + I1 => TimeCounter_reg(11), + I2 => deadTime(10), + I3 => TimeCounter_reg(10), + O => \ltOp_carry__0_i_3_n_0\ + ); +\ltOp_carry__0_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(9), + I1 => TimeCounter_reg(9), + I2 => deadTime(8), + I3 => TimeCounter_reg(8), + O => \ltOp_carry__0_i_4_n_0\ + ); +\ltOp_carry__0_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(15), + I1 => deadTime(15), + I2 => TimeCounter_reg(14), + I3 => deadTime(14), + O => \ltOp_carry__0_i_5_n_0\ + ); +\ltOp_carry__0_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(13), + I1 => deadTime(13), + I2 => TimeCounter_reg(12), + I3 => deadTime(12), + O => \ltOp_carry__0_i_6_n_0\ + ); +\ltOp_carry__0_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(11), + I1 => deadTime(11), + I2 => TimeCounter_reg(10), + I3 => deadTime(10), + O => \ltOp_carry__0_i_7_n_0\ + ); +\ltOp_carry__0_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(9), + I1 => deadTime(9), + I2 => TimeCounter_reg(8), + I3 => deadTime(8), + O => \ltOp_carry__0_i_8_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry__1_i_1_n_0\, + DI(2) => \ltOp_carry__1_i_2_n_0\, + DI(1) => \ltOp_carry__1_i_3_n_0\, + DI(0) => \ltOp_carry__1_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry__1_i_5_n_0\, + S(2) => \ltOp_carry__1_i_6_n_0\, + S(1) => \ltOp_carry__1_i_7_n_0\, + S(0) => \ltOp_carry__1_i_8_n_0\ + ); +\ltOp_carry__1_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(23), + I1 => TimeCounter_reg(23), + I2 => deadTime(22), + I3 => TimeCounter_reg(22), + O => \ltOp_carry__1_i_1_n_0\ + ); +\ltOp_carry__1_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(21), + I1 => TimeCounter_reg(21), + I2 => deadTime(20), + I3 => TimeCounter_reg(20), + O => \ltOp_carry__1_i_2_n_0\ + ); +\ltOp_carry__1_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(19), + I1 => TimeCounter_reg(19), + I2 => deadTime(18), + I3 => TimeCounter_reg(18), + O => \ltOp_carry__1_i_3_n_0\ + ); +\ltOp_carry__1_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(17), + I1 => TimeCounter_reg(17), + I2 => deadTime(16), + I3 => TimeCounter_reg(16), + O => \ltOp_carry__1_i_4_n_0\ + ); +\ltOp_carry__1_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(23), + I1 => deadTime(23), + I2 => TimeCounter_reg(22), + I3 => deadTime(22), + O => \ltOp_carry__1_i_5_n_0\ + ); +\ltOp_carry__1_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(21), + I1 => deadTime(21), + I2 => TimeCounter_reg(20), + I3 => deadTime(20), + O => \ltOp_carry__1_i_6_n_0\ + ); +\ltOp_carry__1_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(19), + I1 => deadTime(19), + I2 => TimeCounter_reg(18), + I3 => deadTime(18), + O => \ltOp_carry__1_i_7_n_0\ + ); +\ltOp_carry__1_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(17), + I1 => deadTime(17), + I2 => TimeCounter_reg(16), + I3 => deadTime(16), + O => \ltOp_carry__1_i_8_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => sel, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry__2_i_1_n_0\, + DI(2) => \ltOp_carry__2_i_2_n_0\, + DI(1) => \ltOp_carry__2_i_3_n_0\, + DI(0) => \ltOp_carry__2_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry__2_i_5_n_0\, + S(2) => \ltOp_carry__2_i_6_n_0\, + S(1) => \ltOp_carry__2_i_7_n_0\, + S(0) => \ltOp_carry__2_i_8_n_0\ + ); +\ltOp_carry__2_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(31), + I1 => TimeCounter_reg(31), + I2 => deadTime(30), + I3 => TimeCounter_reg(30), + O => \ltOp_carry__2_i_1_n_0\ + ); +\ltOp_carry__2_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(29), + I1 => TimeCounter_reg(29), + I2 => deadTime(28), + I3 => TimeCounter_reg(28), + O => \ltOp_carry__2_i_2_n_0\ + ); +\ltOp_carry__2_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(27), + I1 => TimeCounter_reg(27), + I2 => deadTime(26), + I3 => TimeCounter_reg(26), + O => \ltOp_carry__2_i_3_n_0\ + ); +\ltOp_carry__2_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(25), + I1 => TimeCounter_reg(25), + I2 => deadTime(24), + I3 => TimeCounter_reg(24), + O => \ltOp_carry__2_i_4_n_0\ + ); +\ltOp_carry__2_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(31), + I1 => deadTime(31), + I2 => TimeCounter_reg(30), + I3 => deadTime(30), + O => \ltOp_carry__2_i_5_n_0\ + ); +\ltOp_carry__2_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(29), + I1 => deadTime(29), + I2 => TimeCounter_reg(28), + I3 => deadTime(28), + O => \ltOp_carry__2_i_6_n_0\ + ); +\ltOp_carry__2_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(27), + I1 => deadTime(27), + I2 => TimeCounter_reg(26), + I3 => deadTime(26), + O => \ltOp_carry__2_i_7_n_0\ + ); +\ltOp_carry__2_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(25), + I1 => deadTime(25), + I2 => TimeCounter_reg(24), + I3 => deadTime(24), + O => \ltOp_carry__2_i_8_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(7), + I1 => TimeCounter_reg(7), + I2 => deadTime(6), + I3 => TimeCounter_reg(6), + O => ltOp_carry_i_1_n_0 + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(5), + I1 => TimeCounter_reg(5), + I2 => deadTime(4), + I3 => TimeCounter_reg(4), + O => ltOp_carry_i_2_n_0 + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(3), + I1 => TimeCounter_reg(3), + I2 => deadTime(2), + I3 => TimeCounter_reg(2), + O => ltOp_carry_i_3_n_0 + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(1), + I1 => TimeCounter_reg(1), + I2 => deadTime(0), + I3 => TimeCounter_reg(0), + O => ltOp_carry_i_4_n_0 + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(7), + I1 => deadTime(7), + I2 => TimeCounter_reg(6), + I3 => deadTime(6), + O => ltOp_carry_i_5_n_0 + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(5), + I1 => deadTime(5), + I2 => TimeCounter_reg(4), + I3 => deadTime(4), + O => ltOp_carry_i_6_n_0 + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(3), + I1 => deadTime(3), + I2 => TimeCounter_reg(2), + I3 => deadTime(2), + O => ltOp_carry_i_7_n_0 + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(1), + I1 => deadTime(1), + I2 => TimeCounter_reg(0), + I3 => deadTime(0), + O => ltOp_carry_i_8_n_0 + ); +\minTimeCounter_high[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000022222F22" + ) + port map ( + I0 => key1_prev, + I1 => key1_reg_n_0, + I2 => key2_reg_n_0, + I3 => key2_prev, + I4 => breaking_en, + I5 => reset, + O => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high[0]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \ltOp__31_carry__2_n_0\, + I1 => reset, + O => minTimeCounter_high + ); +\minTimeCounter_high[0]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => minTimeCounter_high_reg(0), + O => \minTimeCounter_high[0]_i_4_n_0\ + ); +\minTimeCounter_high_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[0]_i_3_n_7\, + Q => minTimeCounter_high_reg(0), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[0]_i_3\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \minTimeCounter_high_reg[0]_i_3_n_0\, + CO(2) => \minTimeCounter_high_reg[0]_i_3_n_1\, + CO(1) => \minTimeCounter_high_reg[0]_i_3_n_2\, + CO(0) => \minTimeCounter_high_reg[0]_i_3_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \minTimeCounter_high_reg[0]_i_3_n_4\, + O(2) => \minTimeCounter_high_reg[0]_i_3_n_5\, + O(1) => \minTimeCounter_high_reg[0]_i_3_n_6\, + O(0) => \minTimeCounter_high_reg[0]_i_3_n_7\, + S(3 downto 1) => minTimeCounter_high_reg(3 downto 1), + S(0) => \minTimeCounter_high[0]_i_4_n_0\ + ); +\minTimeCounter_high_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[8]_i_1_n_5\, + Q => minTimeCounter_high_reg(10), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[8]_i_1_n_4\, + Q => minTimeCounter_high_reg(11), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[12]_i_1_n_7\, + Q => minTimeCounter_high_reg(12), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[8]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[12]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[12]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[12]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[12]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[12]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[12]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[12]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[12]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(15 downto 12) + ); +\minTimeCounter_high_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[12]_i_1_n_6\, + Q => minTimeCounter_high_reg(13), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[12]_i_1_n_5\, + Q => minTimeCounter_high_reg(14), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[12]_i_1_n_4\, + Q => minTimeCounter_high_reg(15), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[16]_i_1_n_7\, + Q => minTimeCounter_high_reg(16), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[16]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[12]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[16]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[16]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[16]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[16]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[16]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[16]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[16]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[16]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(19 downto 16) + ); +\minTimeCounter_high_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[16]_i_1_n_6\, + Q => minTimeCounter_high_reg(17), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[16]_i_1_n_5\, + Q => minTimeCounter_high_reg(18), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[16]_i_1_n_4\, + Q => minTimeCounter_high_reg(19), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[0]_i_3_n_6\, + Q => minTimeCounter_high_reg(1), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[20]_i_1_n_7\, + Q => minTimeCounter_high_reg(20), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[20]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[16]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[20]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[20]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[20]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[20]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[20]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[20]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[20]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[20]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(23 downto 20) + ); +\minTimeCounter_high_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[20]_i_1_n_6\, + Q => minTimeCounter_high_reg(21), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[20]_i_1_n_5\, + Q => minTimeCounter_high_reg(22), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[20]_i_1_n_4\, + Q => minTimeCounter_high_reg(23), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[24]_i_1_n_7\, + Q => minTimeCounter_high_reg(24), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[24]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[20]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[24]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[24]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[24]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[24]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[24]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[24]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[24]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[24]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(27 downto 24) + ); +\minTimeCounter_high_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[24]_i_1_n_6\, + Q => minTimeCounter_high_reg(25), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[24]_i_1_n_5\, + Q => minTimeCounter_high_reg(26), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[24]_i_1_n_4\, + Q => minTimeCounter_high_reg(27), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[28]_i_1_n_7\, + Q => minTimeCounter_high_reg(28), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[28]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[24]_i_1_n_0\, + CO(3) => \NLW_minTimeCounter_high_reg[28]_i_1_CO_UNCONNECTED\(3), + CO(2) => \minTimeCounter_high_reg[28]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[28]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[28]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[28]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[28]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[28]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[28]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(31 downto 28) + ); +\minTimeCounter_high_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[28]_i_1_n_6\, + Q => minTimeCounter_high_reg(29), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[0]_i_3_n_5\, + Q => minTimeCounter_high_reg(2), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[28]_i_1_n_5\, + Q => minTimeCounter_high_reg(30), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[28]_i_1_n_4\, + Q => minTimeCounter_high_reg(31), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[0]_i_3_n_4\, + Q => minTimeCounter_high_reg(3), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[4]_i_1_n_7\, + Q => minTimeCounter_high_reg(4), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[0]_i_3_n_0\, + CO(3) => \minTimeCounter_high_reg[4]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[4]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[4]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[4]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[4]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[4]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[4]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(7 downto 4) + ); +\minTimeCounter_high_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[4]_i_1_n_6\, + Q => minTimeCounter_high_reg(5), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[4]_i_1_n_5\, + Q => minTimeCounter_high_reg(6), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[4]_i_1_n_4\, + Q => minTimeCounter_high_reg(7), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[8]_i_1_n_7\, + Q => minTimeCounter_high_reg(8), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[4]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[8]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[8]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[8]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[8]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[8]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[8]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[8]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(11 downto 8) + ); +\minTimeCounter_high_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[8]_i_1_n_6\, + Q => minTimeCounter_high_reg(9), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_low[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000440F" + ) + port map ( + I0 => key2_reg_n_0, + I1 => key2_prev, + I2 => \minTimeCounter_low[0]_i_4_n_0\, + I3 => breaking_en, + I4 => reset, + O => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low[0]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \ltOp__15_carry__2_n_0\, + I1 => reset, + O => minTimeCounter_low + ); +\minTimeCounter_low[0]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"D0DD" + ) + port map ( + I0 => key4_prev, + I1 => key4_reg_n_0, + I2 => key3_reg_n_0, + I3 => key3_prev, + O => \minTimeCounter_low[0]_i_4_n_0\ + ); +\minTimeCounter_low[0]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => minTimeCounter_low_reg(0), + O => \minTimeCounter_low[0]_i_5_n_0\ + ); +\minTimeCounter_low_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[0]_i_3_n_7\, + Q => minTimeCounter_low_reg(0), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[0]_i_3\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \minTimeCounter_low_reg[0]_i_3_n_0\, + CO(2) => \minTimeCounter_low_reg[0]_i_3_n_1\, + CO(1) => \minTimeCounter_low_reg[0]_i_3_n_2\, + CO(0) => \minTimeCounter_low_reg[0]_i_3_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \minTimeCounter_low_reg[0]_i_3_n_4\, + O(2) => \minTimeCounter_low_reg[0]_i_3_n_5\, + O(1) => \minTimeCounter_low_reg[0]_i_3_n_6\, + O(0) => \minTimeCounter_low_reg[0]_i_3_n_7\, + S(3 downto 1) => minTimeCounter_low_reg(3 downto 1), + S(0) => \minTimeCounter_low[0]_i_5_n_0\ + ); +\minTimeCounter_low_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[8]_i_1_n_5\, + Q => minTimeCounter_low_reg(10), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[8]_i_1_n_4\, + Q => minTimeCounter_low_reg(11), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[12]_i_1_n_7\, + Q => minTimeCounter_low_reg(12), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[8]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[12]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[12]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[12]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[12]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[12]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[12]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[12]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[12]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(15 downto 12) + ); +\minTimeCounter_low_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[12]_i_1_n_6\, + Q => minTimeCounter_low_reg(13), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[12]_i_1_n_5\, + Q => minTimeCounter_low_reg(14), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[12]_i_1_n_4\, + Q => minTimeCounter_low_reg(15), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[16]_i_1_n_7\, + Q => minTimeCounter_low_reg(16), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[16]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[12]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[16]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[16]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[16]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[16]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[16]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[16]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[16]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[16]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(19 downto 16) + ); +\minTimeCounter_low_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[16]_i_1_n_6\, + Q => minTimeCounter_low_reg(17), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[16]_i_1_n_5\, + Q => minTimeCounter_low_reg(18), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[16]_i_1_n_4\, + Q => minTimeCounter_low_reg(19), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[0]_i_3_n_6\, + Q => minTimeCounter_low_reg(1), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[20]_i_1_n_7\, + Q => minTimeCounter_low_reg(20), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[20]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[16]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[20]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[20]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[20]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[20]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[20]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[20]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[20]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[20]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(23 downto 20) + ); +\minTimeCounter_low_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[20]_i_1_n_6\, + Q => minTimeCounter_low_reg(21), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[20]_i_1_n_5\, + Q => minTimeCounter_low_reg(22), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[20]_i_1_n_4\, + Q => minTimeCounter_low_reg(23), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[24]_i_1_n_7\, + Q => minTimeCounter_low_reg(24), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[24]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[20]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[24]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[24]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[24]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[24]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[24]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[24]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[24]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[24]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(27 downto 24) + ); +\minTimeCounter_low_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[24]_i_1_n_6\, + Q => minTimeCounter_low_reg(25), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[24]_i_1_n_5\, + Q => minTimeCounter_low_reg(26), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[24]_i_1_n_4\, + Q => minTimeCounter_low_reg(27), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[28]_i_1_n_7\, + Q => minTimeCounter_low_reg(28), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[28]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[24]_i_1_n_0\, + CO(3) => \NLW_minTimeCounter_low_reg[28]_i_1_CO_UNCONNECTED\(3), + CO(2) => \minTimeCounter_low_reg[28]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[28]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[28]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[28]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[28]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[28]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[28]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(31 downto 28) + ); +\minTimeCounter_low_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[28]_i_1_n_6\, + Q => minTimeCounter_low_reg(29), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[0]_i_3_n_5\, + Q => minTimeCounter_low_reg(2), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[28]_i_1_n_5\, + Q => minTimeCounter_low_reg(30), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[28]_i_1_n_4\, + Q => minTimeCounter_low_reg(31), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[0]_i_3_n_4\, + Q => minTimeCounter_low_reg(3), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[4]_i_1_n_7\, + Q => minTimeCounter_low_reg(4), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[0]_i_3_n_0\, + CO(3) => \minTimeCounter_low_reg[4]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[4]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[4]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[4]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[4]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[4]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[4]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(7 downto 4) + ); +\minTimeCounter_low_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[4]_i_1_n_6\, + Q => minTimeCounter_low_reg(5), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[4]_i_1_n_5\, + Q => minTimeCounter_low_reg(6), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[4]_i_1_n_4\, + Q => minTimeCounter_low_reg(7), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[8]_i_1_n_7\, + Q => minTimeCounter_low_reg(8), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[4]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[8]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[8]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[8]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[8]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[8]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[8]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[8]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(11 downto 8) + ); +\minTimeCounter_low_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[8]_i_1_n_6\, + Q => minTimeCounter_low_reg(9), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +minTimeEr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"EEFFEEEEE200E2E2" + ) + port map ( + I0 => minTimeEr_i_2_n_0, + I1 => minTimeEr_i_3_n_0, + I2 => minTimeEr_i_4_n_0, + I3 => minTimeEr_i_5_n_0, + I4 => minTimeEr_i_6_n_0, + I5 => \^mintimeer_reg_0\, + O => minTimeEr_i_1_n_0 + ); +minTimeEr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"0111" + ) + port map ( + I0 => reset, + I1 => breaking_en, + I2 => minTimeEr_i_6_n_0, + I3 => minTimeEr_i_7_n_0, + O => minTimeEr_i_2_n_0 + ); +minTimeEr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => breaking_en, + I1 => reset, + O => minTimeEr_i_3_n_0 + ); +minTimeEr_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"040404FF00000000" + ) + port map ( + I0 => minTimeOK_low, + I1 => key2_reg_n_0, + I2 => key2_prev, + I3 => minTimeEr_i_8_n_0, + I4 => minTimeOK_high, + I5 => minTime_En, + O => minTimeEr_i_4_n_0 + ); +minTimeEr_i_5: unisim.vcomponents.LUT6 + generic map( + INIT => X"55555555F755F7F7" + ) + port map ( + I0 => minTimeEr_i_9_n_0, + I1 => key2_prev, + I2 => key2_reg_n_0, + I3 => key1_reg_n_0, + I4 => key1_prev, + I5 => minTimeEr_i_7_n_0, + O => minTimeEr_i_5_n_0 + ); +minTimeEr_i_6: unisim.vcomponents.LUT6 + generic map( + INIT => X"FBFFFFFFBBFBFBFF" + ) + port map ( + I0 => minTimeOK_low, + I1 => minTime_En, + I2 => key3_prev, + I3 => key3_reg_n_0, + I4 => key4_reg_n_0, + I5 => key4_prev, + O => minTimeEr_i_6_n_0 + ); +minTimeEr_i_7: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFDFDDDDFFDFFFDF" + ) + port map ( + I0 => minTime_En, + I1 => minTimeOK_high, + I2 => key2_reg_n_0, + I3 => key2_prev, + I4 => key1_prev, + I5 => key1_reg_n_0, + O => minTimeEr_i_7_n_0 + ); +minTimeEr_i_8: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => key1_prev, + I1 => key1_reg_n_0, + O => minTimeEr_i_8_n_0 + ); +minTimeEr_i_9: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => breaking_en, + I1 => reset, + O => minTimeEr_i_9_n_0 + ); +minTimeEr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => '1', + D => minTimeEr_i_1_n_0, + Q => \^mintimeer_reg_0\, + R => '0' + ); +minTimeOK_high_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"00AB" + ) + port map ( + I0 => minTimeOK_high, + I1 => \ltOp__31_carry__2_n_0\, + I2 => reset, + I3 => \minTimeCounter_high[0]_i_1_n_0\, + O => minTimeOK_high_i_1_n_0 + ); +minTimeOK_high_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => minTimeOK_high_i_1_n_0, + Q => minTimeOK_high, + R => '0' + ); +minTimeOK_low_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"00AB" + ) + port map ( + I0 => minTimeOK_low, + I1 => \ltOp__15_carry__2_n_0\, + I2 => reset, + I3 => \minTimeCounter_low[0]_i_1_n_0\, + O => minTimeOK_low_i_1_n_0 + ); +minTimeOK_low_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => minTimeOK_low_i_1_n_0, + Q => minTimeOK_low, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Inverter_3lvl_P0N_3lvl_0_1 is + port ( + externalCLK : in STD_LOGIC; + ready : in STD_LOGIC; + reset : in STD_LOGIC; + deadTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + minTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + er : in STD_LOGIC; + minTime_En : in STD_LOGIC; + minTimeEr : out STD_LOGIC; + TKin0 : in STD_LOGIC; + TKin1 : in STD_LOGIC; + breaking_en : in STD_LOGIC; + PWM_out_0 : out STD_LOGIC; + PWM_out_1 : out STD_LOGIC; + PWM_out_2 : out STD_LOGIC; + PWM_out_3 : out STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of Inverter_3lvl_P0N_3lvl_0_1 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of Inverter_3lvl_P0N_3lvl_0_1 : entity is "Inverter_3lvl_P0N_3lvl_0_4,P0N_3lvl,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of Inverter_3lvl_P0N_3lvl_0_1 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of Inverter_3lvl_P0N_3lvl_0_1 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of Inverter_3lvl_P0N_3lvl_0_1 : entity is "P0N_3lvl,Vivado 2019.1"; +end Inverter_3lvl_P0N_3lvl_0_1; + +architecture STRUCTURE of Inverter_3lvl_P0N_3lvl_0_1 is + attribute x_interface_info : string; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.Inverter_3lvl_P0N_3lvl_0_1_P0N_3lvl + port map ( + PWM_out_0 => PWM_out_0, + PWM_out_1 => PWM_out_1, + PWM_out_2 => PWM_out_2, + PWM_out_3 => PWM_out_3, + TKin0 => TKin0, + TKin1 => TKin1, + breaking_en => breaking_en, + deadTime(31 downto 0) => deadTime(31 downto 0), + er => er, + externalCLK => externalCLK, + minTime(31 downto 0) => minTime(31 downto 0), + minTimeEr_reg_0 => minTimeEr, + minTime_En => minTime_En, + ready => ready, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1_stub.v b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1_stub.v new file mode 100644 index 0000000..dfa58b9 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1_stub.v @@ -0,0 +1,35 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Fri Jun 11 07:49:57 2021 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top Inverter_3lvl_P0N_3lvl_0_1 -prefix +// Inverter_3lvl_P0N_3lvl_0_1_ Inverter_3lvl_P0N_3lvl_0_4_stub.v +// Design : Inverter_3lvl_P0N_3lvl_0_4 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "P0N_3lvl,Vivado 2019.1" *) +module Inverter_3lvl_P0N_3lvl_0_1(externalCLK, ready, reset, deadTime, minTime, er, + minTime_En, minTimeEr, TKin0, TKin1, breaking_en, PWM_out_0, PWM_out_1, PWM_out_2, PWM_out_3) +/* synthesis syn_black_box black_box_pad_pin="externalCLK,ready,reset,deadTime[31:0],minTime[31:0],er,minTime_En,minTimeEr,TKin0,TKin1,breaking_en,PWM_out_0,PWM_out_1,PWM_out_2,PWM_out_3" */; + input externalCLK; + input ready; + input reset; + input [31:0]deadTime; + input [31:0]minTime; + input er; + input minTime_En; + output minTimeEr; + input TKin0; + input TKin1; + input breaking_en; + output PWM_out_0; + output PWM_out_1; + output PWM_out_2; + output PWM_out_3; +endmodule diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1_stub.vhdl b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1_stub.vhdl new file mode 100644 index 0000000..6929640 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_1/Inverter_3lvl_P0N_3lvl_0_1_stub.vhdl @@ -0,0 +1,44 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Fri Jun 11 07:49:57 2021 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top Inverter_3lvl_P0N_3lvl_0_1 -prefix +-- Inverter_3lvl_P0N_3lvl_0_1_ Inverter_3lvl_P0N_3lvl_0_4_stub.vhdl +-- Design : Inverter_3lvl_P0N_3lvl_0_4 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Inverter_3lvl_P0N_3lvl_0_1 is + Port ( + externalCLK : in STD_LOGIC; + ready : in STD_LOGIC; + reset : in STD_LOGIC; + deadTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + minTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + er : in STD_LOGIC; + minTime_En : in STD_LOGIC; + minTimeEr : out STD_LOGIC; + TKin0 : in STD_LOGIC; + TKin1 : in STD_LOGIC; + breaking_en : in STD_LOGIC; + PWM_out_0 : out STD_LOGIC; + PWM_out_1 : out STD_LOGIC; + PWM_out_2 : out STD_LOGIC; + PWM_out_3 : out STD_LOGIC + ); + +end Inverter_3lvl_P0N_3lvl_0_1; + +architecture stub of Inverter_3lvl_P0N_3lvl_0_1 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "externalCLK,ready,reset,deadTime[31:0],minTime[31:0],er,minTime_En,minTimeEr,TKin0,TKin1,breaking_en,PWM_out_0,PWM_out_1,PWM_out_2,PWM_out_3"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "P0N_3lvl,Vivado 2019.1"; +begin +end; diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/Inverter_3lvl_P0N_3lvl_0_2.dcp b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2.dcp similarity index 99% rename from LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_2_synth_1/Inverter_3lvl_P0N_3lvl_0_2.dcp rename to LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2.dcp index 185787d3305b55d3be04b3f2129e012365e27cd7..ff9034fc7f8f0891764077cc054385010aff2544 100644 GIT binary patch delta 28 hcmdn8n0d=$<_%G2Sf<4;4%-}eMw}JQnp}C&8UVQ84153p delta 28 hcmdn8n0d=$<_%G2SlsMR2W^f!BhCtDO|HCX4FItB3+4a- diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2.xml b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2.xml index 0d03662..10eb23f 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2.xml +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2.xml @@ -133,6 +133,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:44:44 UTC 2023 + + + outputProductCRC + 9:3a7b00a1 + + + @@ -407,6 +425,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + Inverter_3lvl_P0N_3lvl_0_2.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_0_2_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_0_2_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_0_2_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_0_2_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + P0N_3lvl_v1_0 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2_sim_netlist.v b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2_sim_netlist.v new file mode 100644 index 0000000..d637c70 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2_sim_netlist.v @@ -0,0 +1,3131 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Fri Jun 11 07:49:57 2021 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top Inverter_3lvl_P0N_3lvl_0_2 -prefix +// Inverter_3lvl_P0N_3lvl_0_2_ Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.v +// Design : Inverter_3lvl_P0N_3lvl_0_4 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "Inverter_3lvl_P0N_3lvl_0_4,P0N_3lvl,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "P0N_3lvl,Vivado 2019.1" *) +(* NotValidForBitStream *) +module Inverter_3lvl_P0N_3lvl_0_2 + (externalCLK, + ready, + reset, + deadTime, + minTime, + er, + minTime_En, + minTimeEr, + TKin0, + TKin1, + breaking_en, + PWM_out_0, + PWM_out_1, + PWM_out_2, + PWM_out_3); + input externalCLK; + input ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + input [31:0]deadTime; + input [31:0]minTime; + input er; + input minTime_En; + output minTimeEr; + input TKin0; + input TKin1; + input breaking_en; + output PWM_out_0; + output PWM_out_1; + output PWM_out_2; + output PWM_out_3; + + wire PWM_out_0; + wire PWM_out_1; + wire PWM_out_2; + wire PWM_out_3; + wire TKin0; + wire TKin1; + wire breaking_en; + wire [31:0]deadTime; + wire er; + wire externalCLK; + wire [31:0]minTime; + wire minTimeEr; + wire minTime_En; + wire ready; + wire reset; + + Inverter_3lvl_P0N_3lvl_0_2_P0N_3lvl U0 + (.PWM_out_0(PWM_out_0), + .PWM_out_1(PWM_out_1), + .PWM_out_2(PWM_out_2), + .PWM_out_3(PWM_out_3), + .TKin0(TKin0), + .TKin1(TKin1), + .breaking_en(breaking_en), + .deadTime(deadTime), + .er(er), + .externalCLK(externalCLK), + .minTime(minTime), + .minTimeEr_reg_0(minTimeEr), + .minTime_En(minTime_En), + .ready(ready), + .reset(reset)); +endmodule + +module Inverter_3lvl_P0N_3lvl_0_2_P0N_3lvl + (minTimeEr_reg_0, + PWM_out_0, + PWM_out_1, + PWM_out_2, + PWM_out_3, + reset, + externalCLK, + TKin0, + TKin1, + breaking_en, + er, + ready, + minTime_En, + deadTime, + minTime); + output minTimeEr_reg_0; + output PWM_out_0; + output PWM_out_1; + output PWM_out_2; + output PWM_out_3; + input reset; + input externalCLK; + input TKin0; + input TKin1; + input breaking_en; + input er; + input ready; + input minTime_En; + input [31:0]deadTime; + input [31:0]minTime; + + wire \FSM_onehot_lineconfig[0]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[0]_i_2_n_0 ; + wire \FSM_onehot_lineconfig[1]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[2]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[2]_i_2_n_0 ; + wire \FSM_onehot_lineconfig[3]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[4]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[5]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[5]_i_2_n_0 ; + wire \FSM_onehot_lineconfig[5]_i_3_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_2_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_3_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_4_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_5_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_6_n_0 ; + wire \FSM_onehot_lineconfig_reg_n_0_[0] ; + wire \FSM_onehot_lineconfig_reg_n_0_[1] ; + wire \FSM_onehot_lineconfig_reg_n_0_[2] ; + wire \FSM_onehot_lineconfig_reg_n_0_[3] ; + wire \FSM_onehot_lineconfig_reg_n_0_[4] ; + wire \FSM_onehot_lineconfig_reg_n_0_[5] ; + wire \FSM_onehot_lineconfig_reg_n_0_[6] ; + wire PWM_out_0; + wire PWM_out_0_i_1_n_0; + wire PWM_out_1; + wire PWM_out_1_i_1_n_0; + wire PWM_out_2; + wire PWM_out_2_i_1_n_0; + wire PWM_out_3; + wire PWM_out_3_i_1_n_0; + wire TKin0; + wire TKin0_triggered; + wire TKin0_triggered28_out; + wire TKin0_triggered_i_1_n_0; + wire TKin1; + wire TKin1_triggered; + wire TKin1_triggered_i_1_n_0; + wire \TimeCounter[0]_i_2_n_0 ; + wire [31:0]TimeCounter_reg; + wire \TimeCounter_reg[0]_i_1_n_0 ; + wire \TimeCounter_reg[0]_i_1_n_1 ; + wire \TimeCounter_reg[0]_i_1_n_2 ; + wire \TimeCounter_reg[0]_i_1_n_3 ; + wire \TimeCounter_reg[0]_i_1_n_4 ; + wire \TimeCounter_reg[0]_i_1_n_5 ; + wire \TimeCounter_reg[0]_i_1_n_6 ; + wire \TimeCounter_reg[0]_i_1_n_7 ; + wire \TimeCounter_reg[12]_i_1_n_0 ; + wire \TimeCounter_reg[12]_i_1_n_1 ; + wire \TimeCounter_reg[12]_i_1_n_2 ; + wire \TimeCounter_reg[12]_i_1_n_3 ; + wire \TimeCounter_reg[12]_i_1_n_4 ; + wire \TimeCounter_reg[12]_i_1_n_5 ; + wire \TimeCounter_reg[12]_i_1_n_6 ; + wire \TimeCounter_reg[12]_i_1_n_7 ; + wire \TimeCounter_reg[16]_i_1_n_0 ; + wire \TimeCounter_reg[16]_i_1_n_1 ; + wire \TimeCounter_reg[16]_i_1_n_2 ; + wire \TimeCounter_reg[16]_i_1_n_3 ; + wire \TimeCounter_reg[16]_i_1_n_4 ; + wire \TimeCounter_reg[16]_i_1_n_5 ; + wire \TimeCounter_reg[16]_i_1_n_6 ; + wire \TimeCounter_reg[16]_i_1_n_7 ; + wire \TimeCounter_reg[20]_i_1_n_0 ; + wire \TimeCounter_reg[20]_i_1_n_1 ; + wire \TimeCounter_reg[20]_i_1_n_2 ; + wire \TimeCounter_reg[20]_i_1_n_3 ; + wire \TimeCounter_reg[20]_i_1_n_4 ; + wire \TimeCounter_reg[20]_i_1_n_5 ; + wire \TimeCounter_reg[20]_i_1_n_6 ; + wire \TimeCounter_reg[20]_i_1_n_7 ; + wire \TimeCounter_reg[24]_i_1_n_0 ; + wire \TimeCounter_reg[24]_i_1_n_1 ; + wire \TimeCounter_reg[24]_i_1_n_2 ; + wire \TimeCounter_reg[24]_i_1_n_3 ; + wire \TimeCounter_reg[24]_i_1_n_4 ; + wire \TimeCounter_reg[24]_i_1_n_5 ; + wire \TimeCounter_reg[24]_i_1_n_6 ; + wire \TimeCounter_reg[24]_i_1_n_7 ; + wire \TimeCounter_reg[28]_i_1_n_1 ; + wire \TimeCounter_reg[28]_i_1_n_2 ; + wire \TimeCounter_reg[28]_i_1_n_3 ; + wire \TimeCounter_reg[28]_i_1_n_4 ; + wire \TimeCounter_reg[28]_i_1_n_5 ; + wire \TimeCounter_reg[28]_i_1_n_6 ; + wire \TimeCounter_reg[28]_i_1_n_7 ; + wire \TimeCounter_reg[4]_i_1_n_0 ; + wire \TimeCounter_reg[4]_i_1_n_1 ; + wire \TimeCounter_reg[4]_i_1_n_2 ; + wire \TimeCounter_reg[4]_i_1_n_3 ; + wire \TimeCounter_reg[4]_i_1_n_4 ; + wire \TimeCounter_reg[4]_i_1_n_5 ; + wire \TimeCounter_reg[4]_i_1_n_6 ; + wire \TimeCounter_reg[4]_i_1_n_7 ; + wire \TimeCounter_reg[8]_i_1_n_0 ; + wire \TimeCounter_reg[8]_i_1_n_1 ; + wire \TimeCounter_reg[8]_i_1_n_2 ; + wire \TimeCounter_reg[8]_i_1_n_3 ; + wire \TimeCounter_reg[8]_i_1_n_4 ; + wire \TimeCounter_reg[8]_i_1_n_5 ; + wire \TimeCounter_reg[8]_i_1_n_6 ; + wire \TimeCounter_reg[8]_i_1_n_7 ; + wire breaking_en; + wire [31:0]deadTime; + wire deadTimeCounterReset_i_1_n_0; + wire deadTimeCounterReset_i_2_n_0; + wire deadTimeCounterReset_i_3_n_0; + wire deadTimeCounterReset_i_4_n_0; + wire deadTimeCounterReset_i_5_n_0; + wire deadTimeCounterReset_i_6_n_0; + wire deadTimeCounterReset_i_7_n_0; + wire deadTimeCounterReset_reg_n_0; + wire deadTimeOK; + wire deadTimeOK_i_1_n_0; + wire er; + wire externalCLK; + wire key1_i_1_n_0; + wire key1_i_2_n_0; + wire key1_prev; + wire key1_reg_n_0; + wire key2_i_2_n_0; + wire key2_prev; + wire key2_reg_n_0; + wire key3; + wire key3_i_1_n_0; + wire key3_prev; + wire key3_reg_n_0; + wire key4_i_1_n_0; + wire key4_prev; + wire key4_reg_n_0; + wire ltOp__15_carry__0_i_1_n_0; + wire ltOp__15_carry__0_i_2_n_0; + wire ltOp__15_carry__0_i_3_n_0; + wire ltOp__15_carry__0_i_4_n_0; + wire ltOp__15_carry__0_i_5_n_0; + wire ltOp__15_carry__0_i_6_n_0; + wire ltOp__15_carry__0_i_7_n_0; + wire ltOp__15_carry__0_i_8_n_0; + wire ltOp__15_carry__0_n_0; + wire ltOp__15_carry__0_n_1; + wire ltOp__15_carry__0_n_2; + wire ltOp__15_carry__0_n_3; + wire ltOp__15_carry__1_i_1_n_0; + wire ltOp__15_carry__1_i_2_n_0; + wire ltOp__15_carry__1_i_3_n_0; + wire ltOp__15_carry__1_i_4_n_0; + wire ltOp__15_carry__1_i_5_n_0; + wire ltOp__15_carry__1_i_6_n_0; + wire ltOp__15_carry__1_i_7_n_0; + wire ltOp__15_carry__1_i_8_n_0; + wire ltOp__15_carry__1_n_0; + wire ltOp__15_carry__1_n_1; + wire ltOp__15_carry__1_n_2; + wire ltOp__15_carry__1_n_3; + wire ltOp__15_carry__2_i_1_n_0; + wire ltOp__15_carry__2_i_2_n_0; + wire ltOp__15_carry__2_i_3_n_0; + wire ltOp__15_carry__2_i_4_n_0; + wire ltOp__15_carry__2_i_5_n_0; + wire ltOp__15_carry__2_i_6_n_0; + wire ltOp__15_carry__2_i_7_n_0; + wire ltOp__15_carry__2_i_8_n_0; + wire ltOp__15_carry__2_n_0; + wire ltOp__15_carry__2_n_1; + wire ltOp__15_carry__2_n_2; + wire ltOp__15_carry__2_n_3; + wire ltOp__15_carry_i_1_n_0; + wire ltOp__15_carry_i_2_n_0; + wire ltOp__15_carry_i_3_n_0; + wire ltOp__15_carry_i_4_n_0; + wire ltOp__15_carry_i_5_n_0; + wire ltOp__15_carry_i_6_n_0; + wire ltOp__15_carry_i_7_n_0; + wire ltOp__15_carry_i_8_n_0; + wire ltOp__15_carry_n_0; + wire ltOp__15_carry_n_1; + wire ltOp__15_carry_n_2; + wire ltOp__15_carry_n_3; + wire ltOp__31_carry__0_n_0; + wire ltOp__31_carry__0_n_1; + wire ltOp__31_carry__0_n_2; + wire ltOp__31_carry__0_n_3; + wire ltOp__31_carry__1_n_0; + wire ltOp__31_carry__1_n_1; + wire ltOp__31_carry__1_n_2; + wire ltOp__31_carry__1_n_3; + wire ltOp__31_carry__2_n_0; + wire ltOp__31_carry__2_n_1; + wire ltOp__31_carry__2_n_2; + wire ltOp__31_carry__2_n_3; + wire ltOp__31_carry_i_1__0_n_0; + wire ltOp__31_carry_i_1__1_n_0; + wire ltOp__31_carry_i_1__2_n_0; + wire ltOp__31_carry_i_1_n_0; + wire ltOp__31_carry_i_2__0_n_0; + wire ltOp__31_carry_i_2__1_n_0; + wire ltOp__31_carry_i_2__2_n_0; + wire ltOp__31_carry_i_2_n_0; + wire ltOp__31_carry_i_3__0_n_0; + wire ltOp__31_carry_i_3__1_n_0; + wire ltOp__31_carry_i_3__2_n_0; + wire ltOp__31_carry_i_3_n_0; + wire ltOp__31_carry_i_4__0_n_0; + wire ltOp__31_carry_i_4__1_n_0; + wire ltOp__31_carry_i_4__2_n_0; + wire ltOp__31_carry_i_4_n_0; + wire ltOp__31_carry_i_5__0_n_0; + wire ltOp__31_carry_i_5__1_n_0; + wire ltOp__31_carry_i_5__2_n_0; + wire ltOp__31_carry_i_5_n_0; + wire ltOp__31_carry_i_6__0_n_0; + wire ltOp__31_carry_i_6__1_n_0; + wire ltOp__31_carry_i_6__2_n_0; + wire ltOp__31_carry_i_6_n_0; + wire ltOp__31_carry_i_7__0_n_0; + wire ltOp__31_carry_i_7__1_n_0; + wire ltOp__31_carry_i_7__2_n_0; + wire ltOp__31_carry_i_7_n_0; + wire ltOp__31_carry_i_8__0_n_0; + wire ltOp__31_carry_i_8__1_n_0; + wire ltOp__31_carry_i_8__2_n_0; + wire ltOp__31_carry_i_8_n_0; + wire ltOp__31_carry_n_0; + wire ltOp__31_carry_n_1; + wire ltOp__31_carry_n_2; + wire ltOp__31_carry_n_3; + wire ltOp_carry__0_i_1_n_0; + wire ltOp_carry__0_i_2_n_0; + wire ltOp_carry__0_i_3_n_0; + wire ltOp_carry__0_i_4_n_0; + wire ltOp_carry__0_i_5_n_0; + wire ltOp_carry__0_i_6_n_0; + wire ltOp_carry__0_i_7_n_0; + wire ltOp_carry__0_i_8_n_0; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_i_1_n_0; + wire ltOp_carry__1_i_2_n_0; + wire ltOp_carry__1_i_3_n_0; + wire ltOp_carry__1_i_4_n_0; + wire ltOp_carry__1_i_5_n_0; + wire ltOp_carry__1_i_6_n_0; + wire ltOp_carry__1_i_7_n_0; + wire ltOp_carry__1_i_8_n_0; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_i_1_n_0; + wire ltOp_carry__2_i_2_n_0; + wire ltOp_carry__2_i_3_n_0; + wire ltOp_carry__2_i_4_n_0; + wire ltOp_carry__2_i_5_n_0; + wire ltOp_carry__2_i_6_n_0; + wire ltOp_carry__2_i_7_n_0; + wire ltOp_carry__2_i_8_n_0; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [31:0]minTime; + wire minTimeCounter_high; + wire \minTimeCounter_high[0]_i_1_n_0 ; + wire \minTimeCounter_high[0]_i_4_n_0 ; + wire [31:0]minTimeCounter_high_reg; + wire \minTimeCounter_high_reg[0]_i_3_n_0 ; + wire \minTimeCounter_high_reg[0]_i_3_n_1 ; + wire \minTimeCounter_high_reg[0]_i_3_n_2 ; + wire \minTimeCounter_high_reg[0]_i_3_n_3 ; + wire \minTimeCounter_high_reg[0]_i_3_n_4 ; + wire \minTimeCounter_high_reg[0]_i_3_n_5 ; + wire \minTimeCounter_high_reg[0]_i_3_n_6 ; + wire \minTimeCounter_high_reg[0]_i_3_n_7 ; + wire \minTimeCounter_high_reg[12]_i_1_n_0 ; + wire \minTimeCounter_high_reg[12]_i_1_n_1 ; + wire \minTimeCounter_high_reg[12]_i_1_n_2 ; + wire \minTimeCounter_high_reg[12]_i_1_n_3 ; + wire \minTimeCounter_high_reg[12]_i_1_n_4 ; + wire \minTimeCounter_high_reg[12]_i_1_n_5 ; + wire \minTimeCounter_high_reg[12]_i_1_n_6 ; + wire \minTimeCounter_high_reg[12]_i_1_n_7 ; + wire \minTimeCounter_high_reg[16]_i_1_n_0 ; + wire \minTimeCounter_high_reg[16]_i_1_n_1 ; + wire \minTimeCounter_high_reg[16]_i_1_n_2 ; + wire \minTimeCounter_high_reg[16]_i_1_n_3 ; + wire \minTimeCounter_high_reg[16]_i_1_n_4 ; + wire \minTimeCounter_high_reg[16]_i_1_n_5 ; + wire \minTimeCounter_high_reg[16]_i_1_n_6 ; + wire \minTimeCounter_high_reg[16]_i_1_n_7 ; + wire \minTimeCounter_high_reg[20]_i_1_n_0 ; + wire \minTimeCounter_high_reg[20]_i_1_n_1 ; + wire \minTimeCounter_high_reg[20]_i_1_n_2 ; + wire \minTimeCounter_high_reg[20]_i_1_n_3 ; + wire \minTimeCounter_high_reg[20]_i_1_n_4 ; + wire \minTimeCounter_high_reg[20]_i_1_n_5 ; + wire \minTimeCounter_high_reg[20]_i_1_n_6 ; + wire \minTimeCounter_high_reg[20]_i_1_n_7 ; + wire \minTimeCounter_high_reg[24]_i_1_n_0 ; + wire \minTimeCounter_high_reg[24]_i_1_n_1 ; + wire \minTimeCounter_high_reg[24]_i_1_n_2 ; + wire \minTimeCounter_high_reg[24]_i_1_n_3 ; + wire \minTimeCounter_high_reg[24]_i_1_n_4 ; + wire \minTimeCounter_high_reg[24]_i_1_n_5 ; + wire \minTimeCounter_high_reg[24]_i_1_n_6 ; + wire \minTimeCounter_high_reg[24]_i_1_n_7 ; + wire \minTimeCounter_high_reg[28]_i_1_n_1 ; + wire \minTimeCounter_high_reg[28]_i_1_n_2 ; + wire \minTimeCounter_high_reg[28]_i_1_n_3 ; + wire \minTimeCounter_high_reg[28]_i_1_n_4 ; + wire \minTimeCounter_high_reg[28]_i_1_n_5 ; + wire \minTimeCounter_high_reg[28]_i_1_n_6 ; + wire \minTimeCounter_high_reg[28]_i_1_n_7 ; + wire \minTimeCounter_high_reg[4]_i_1_n_0 ; + wire \minTimeCounter_high_reg[4]_i_1_n_1 ; + wire \minTimeCounter_high_reg[4]_i_1_n_2 ; + wire \minTimeCounter_high_reg[4]_i_1_n_3 ; + wire \minTimeCounter_high_reg[4]_i_1_n_4 ; + wire \minTimeCounter_high_reg[4]_i_1_n_5 ; + wire \minTimeCounter_high_reg[4]_i_1_n_6 ; + wire \minTimeCounter_high_reg[4]_i_1_n_7 ; + wire \minTimeCounter_high_reg[8]_i_1_n_0 ; + wire \minTimeCounter_high_reg[8]_i_1_n_1 ; + wire \minTimeCounter_high_reg[8]_i_1_n_2 ; + wire \minTimeCounter_high_reg[8]_i_1_n_3 ; + wire \minTimeCounter_high_reg[8]_i_1_n_4 ; + wire \minTimeCounter_high_reg[8]_i_1_n_5 ; + wire \minTimeCounter_high_reg[8]_i_1_n_6 ; + wire \minTimeCounter_high_reg[8]_i_1_n_7 ; + wire minTimeCounter_low; + wire \minTimeCounter_low[0]_i_1_n_0 ; + wire \minTimeCounter_low[0]_i_4_n_0 ; + wire \minTimeCounter_low[0]_i_5_n_0 ; + wire [31:0]minTimeCounter_low_reg; + wire \minTimeCounter_low_reg[0]_i_3_n_0 ; + wire \minTimeCounter_low_reg[0]_i_3_n_1 ; + wire \minTimeCounter_low_reg[0]_i_3_n_2 ; + wire \minTimeCounter_low_reg[0]_i_3_n_3 ; + wire \minTimeCounter_low_reg[0]_i_3_n_4 ; + wire \minTimeCounter_low_reg[0]_i_3_n_5 ; + wire \minTimeCounter_low_reg[0]_i_3_n_6 ; + wire \minTimeCounter_low_reg[0]_i_3_n_7 ; + wire \minTimeCounter_low_reg[12]_i_1_n_0 ; + wire \minTimeCounter_low_reg[12]_i_1_n_1 ; + wire \minTimeCounter_low_reg[12]_i_1_n_2 ; + wire \minTimeCounter_low_reg[12]_i_1_n_3 ; + wire \minTimeCounter_low_reg[12]_i_1_n_4 ; + wire \minTimeCounter_low_reg[12]_i_1_n_5 ; + wire \minTimeCounter_low_reg[12]_i_1_n_6 ; + wire \minTimeCounter_low_reg[12]_i_1_n_7 ; + wire \minTimeCounter_low_reg[16]_i_1_n_0 ; + wire \minTimeCounter_low_reg[16]_i_1_n_1 ; + wire \minTimeCounter_low_reg[16]_i_1_n_2 ; + wire \minTimeCounter_low_reg[16]_i_1_n_3 ; + wire \minTimeCounter_low_reg[16]_i_1_n_4 ; + wire \minTimeCounter_low_reg[16]_i_1_n_5 ; + wire \minTimeCounter_low_reg[16]_i_1_n_6 ; + wire \minTimeCounter_low_reg[16]_i_1_n_7 ; + wire \minTimeCounter_low_reg[20]_i_1_n_0 ; + wire \minTimeCounter_low_reg[20]_i_1_n_1 ; + wire \minTimeCounter_low_reg[20]_i_1_n_2 ; + wire \minTimeCounter_low_reg[20]_i_1_n_3 ; + wire \minTimeCounter_low_reg[20]_i_1_n_4 ; + wire \minTimeCounter_low_reg[20]_i_1_n_5 ; + wire \minTimeCounter_low_reg[20]_i_1_n_6 ; + wire \minTimeCounter_low_reg[20]_i_1_n_7 ; + wire \minTimeCounter_low_reg[24]_i_1_n_0 ; + wire \minTimeCounter_low_reg[24]_i_1_n_1 ; + wire \minTimeCounter_low_reg[24]_i_1_n_2 ; + wire \minTimeCounter_low_reg[24]_i_1_n_3 ; + wire \minTimeCounter_low_reg[24]_i_1_n_4 ; + wire \minTimeCounter_low_reg[24]_i_1_n_5 ; + wire \minTimeCounter_low_reg[24]_i_1_n_6 ; + wire \minTimeCounter_low_reg[24]_i_1_n_7 ; + wire \minTimeCounter_low_reg[28]_i_1_n_1 ; + wire \minTimeCounter_low_reg[28]_i_1_n_2 ; + wire \minTimeCounter_low_reg[28]_i_1_n_3 ; + wire \minTimeCounter_low_reg[28]_i_1_n_4 ; + wire \minTimeCounter_low_reg[28]_i_1_n_5 ; + wire \minTimeCounter_low_reg[28]_i_1_n_6 ; + wire \minTimeCounter_low_reg[28]_i_1_n_7 ; + wire \minTimeCounter_low_reg[4]_i_1_n_0 ; + wire \minTimeCounter_low_reg[4]_i_1_n_1 ; + wire \minTimeCounter_low_reg[4]_i_1_n_2 ; + wire \minTimeCounter_low_reg[4]_i_1_n_3 ; + wire \minTimeCounter_low_reg[4]_i_1_n_4 ; + wire \minTimeCounter_low_reg[4]_i_1_n_5 ; + wire \minTimeCounter_low_reg[4]_i_1_n_6 ; + wire \minTimeCounter_low_reg[4]_i_1_n_7 ; + wire \minTimeCounter_low_reg[8]_i_1_n_0 ; + wire \minTimeCounter_low_reg[8]_i_1_n_1 ; + wire \minTimeCounter_low_reg[8]_i_1_n_2 ; + wire \minTimeCounter_low_reg[8]_i_1_n_3 ; + wire \minTimeCounter_low_reg[8]_i_1_n_4 ; + wire \minTimeCounter_low_reg[8]_i_1_n_5 ; + wire \minTimeCounter_low_reg[8]_i_1_n_6 ; + wire \minTimeCounter_low_reg[8]_i_1_n_7 ; + wire minTimeEr_i_1_n_0; + wire minTimeEr_i_2_n_0; + wire minTimeEr_i_3_n_0; + wire minTimeEr_i_4_n_0; + wire minTimeEr_i_5_n_0; + wire minTimeEr_i_6_n_0; + wire minTimeEr_i_7_n_0; + wire minTimeEr_i_8_n_0; + wire minTimeEr_i_9_n_0; + wire minTimeEr_reg_0; + wire minTimeOK_high; + wire minTimeOK_high_i_1_n_0; + wire minTimeOK_low; + wire minTimeOK_low_i_1_n_0; + wire minTime_En; + wire p_0_in; + wire ready; + wire reset; + wire sel; + wire [3:3]\NLW_TimeCounter_reg[28]_i_1_CO_UNCONNECTED ; + wire [3:0]NLW_ltOp__15_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp__15_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp__15_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp__15_carry__2_O_UNCONNECTED; + wire [3:0]NLW_ltOp__31_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp__31_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp__31_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp__31_carry__2_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + wire [3:3]\NLW_minTimeCounter_high_reg[28]_i_1_CO_UNCONNECTED ; + wire [3:3]\NLW_minTimeCounter_low_reg[28]_i_1_CO_UNCONNECTED ; + + LUT6 #( + .INIT(64'hFFFFFFFE00000000)) + \FSM_onehot_lineconfig[0]_i_1 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I4(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I5(\FSM_onehot_lineconfig[0]_i_2_n_0 ), + .O(\FSM_onehot_lineconfig[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_lineconfig[0]_i_2 + (.I0(TKin1), + .I1(TKin0), + .O(\FSM_onehot_lineconfig[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'h1000FFFF00000000)) + \FSM_onehot_lineconfig[1]_i_1 + (.I0(TKin1), + .I1(TKin1_triggered), + .I2(TKin0_triggered), + .I3(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I4(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I5(TKin0), + .O(\FSM_onehot_lineconfig[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h00EFEF0F)) + \FSM_onehot_lineconfig[2]_i_1 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I2(\FSM_onehot_lineconfig[2]_i_2_n_0 ), + .I3(TKin0), + .I4(TKin1), + .O(\FSM_onehot_lineconfig[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'h900990099009FFFF)) + \FSM_onehot_lineconfig[2]_i_2 + (.I0(TKin1), + .I1(TKin1_triggered), + .I2(TKin0), + .I3(TKin0_triggered), + .I4(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I5(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .O(\FSM_onehot_lineconfig[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0000000055D50000)) + \FSM_onehot_lineconfig[3]_i_1 + (.I0(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I2(TKin1_triggered), + .I3(TKin0_triggered), + .I4(TKin1), + .I5(TKin0), + .O(\FSM_onehot_lineconfig[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT4 #( + .INIT(16'h2230)) + \FSM_onehot_lineconfig[4]_i_1 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I1(TKin0), + .I2(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I3(TKin1), + .O(\FSM_onehot_lineconfig[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0CFF0C0D00050005)) + \FSM_onehot_lineconfig[5]_i_1 + (.I0(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I2(TKin1), + .I3(TKin0), + .I4(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I5(\FSM_onehot_lineconfig[5]_i_3_n_0 ), + .O(\FSM_onehot_lineconfig[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h1)) + \FSM_onehot_lineconfig[5]_i_2 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .O(\FSM_onehot_lineconfig[5]_i_2_n_0 )); + LUT4 #( + .INIT(16'h9009)) + \FSM_onehot_lineconfig[5]_i_3 + (.I0(TKin0_triggered), + .I1(TKin0), + .I2(TKin1_triggered), + .I3(TKin1), + .O(\FSM_onehot_lineconfig[5]_i_3_n_0 )); + LUT3 #( + .INIT(8'h0E)) + \FSM_onehot_lineconfig[6]_i_1 + (.I0(\FSM_onehot_lineconfig[6]_i_3_n_0 ), + .I1(\FSM_onehot_lineconfig[6]_i_4_n_0 ), + .I2(breaking_en), + .O(\FSM_onehot_lineconfig[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT4 #( + .INIT(16'h5504)) + \FSM_onehot_lineconfig[6]_i_2 + (.I0(TKin1), + .I1(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I2(TKin0), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .O(\FSM_onehot_lineconfig[6]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'hFFFEECAE)) + \FSM_onehot_lineconfig[6]_i_3 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I2(TKin1), + .I3(TKin0), + .I4(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .O(\FSM_onehot_lineconfig[6]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAABAAAAAFFFFAAAA)) + \FSM_onehot_lineconfig[6]_i_4 + (.I0(\FSM_onehot_lineconfig[6]_i_5_n_0 ), + .I1(er), + .I2(ready), + .I3(\FSM_onehot_lineconfig[6]_i_6_n_0 ), + .I4(deadTimeOK), + .I5(\FSM_onehot_lineconfig[2]_i_2_n_0 ), + .O(\FSM_onehot_lineconfig[6]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFC88A0A8)) + \FSM_onehot_lineconfig[6]_i_5 + (.I0(deadTimeOK), + .I1(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I3(TKin1), + .I4(TKin0), + .O(\FSM_onehot_lineconfig[6]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'hFF232323)) + \FSM_onehot_lineconfig[6]_i_6 + (.I0(deadTimeCounterReset_reg_n_0), + .I1(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I3(TKin1), + .I4(TKin0), + .O(\FSM_onehot_lineconfig[6]_i_6_n_0 )); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDSE #( + .INIT(1'b1)) + \FSM_onehot_lineconfig_reg[0] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[0]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .S(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[1] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[1]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[2] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[2]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[3] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[3]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[4] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[4]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[5] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[5]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[6] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[6]_i_2_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT4 #( + .INIT(16'hFFEF)) + PWM_out_0_i_1 + (.I0(key1_reg_n_0), + .I1(er), + .I2(ready), + .I3(minTimeEr_reg_0), + .O(PWM_out_0_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + PWM_out_0_reg + (.C(externalCLK), + .CE(1'b1), + .D(PWM_out_0_i_1_n_0), + .Q(PWM_out_0), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT4 #( + .INIT(16'hFFEF)) + PWM_out_1_i_1 + (.I0(key2_reg_n_0), + .I1(er), + .I2(ready), + .I3(minTimeEr_reg_0), + .O(PWM_out_1_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + PWM_out_1_reg + (.C(externalCLK), + .CE(1'b1), + .D(PWM_out_1_i_1_n_0), + .Q(PWM_out_1), + .R(1'b0)); + LUT5 #( + .INIT(32'hFFFFFFEF)) + PWM_out_2_i_1 + (.I0(key3_reg_n_0), + .I1(minTimeEr_reg_0), + .I2(ready), + .I3(er), + .I4(breaking_en), + .O(PWM_out_2_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + PWM_out_2_reg + (.C(externalCLK), + .CE(1'b1), + .D(PWM_out_2_i_1_n_0), + .Q(PWM_out_2), + .R(1'b0)); + LUT5 #( + .INIT(32'hFFFFFFEF)) + PWM_out_3_i_1 + (.I0(key4_reg_n_0), + .I1(minTimeEr_reg_0), + .I2(ready), + .I3(er), + .I4(breaking_en), + .O(PWM_out_3_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + PWM_out_3_reg + (.C(externalCLK), + .CE(1'b1), + .D(PWM_out_3_i_1_n_0), + .Q(PWM_out_3), + .R(1'b0)); + LUT6 #( + .INIT(64'hAA08FFFFAA080000)) + TKin0_triggered_i_1 + (.I0(TKin0), + .I1(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I2(TKin1), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I4(TKin0_triggered28_out), + .I5(TKin0_triggered), + .O(TKin0_triggered_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + TKin0_triggered_reg + (.C(externalCLK), + .CE(1'b1), + .D(TKin0_triggered_i_1_n_0), + .Q(TKin0_triggered), + .R(1'b0)); + LUT6 #( + .INIT(64'hAA08FFFFAA080000)) + TKin1_triggered_i_1 + (.I0(TKin1), + .I1(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I2(TKin0), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I4(TKin0_triggered28_out), + .I5(TKin1_triggered), + .O(TKin1_triggered_i_1_n_0)); + LUT6 #( + .INIT(64'h22AA22A820AA2020)) + TKin1_triggered_i_2 + (.I0(minTimeEr_i_9_n_0), + .I1(TKin1), + .I2(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I3(TKin0), + .I4(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I5(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .O(TKin0_triggered28_out)); + FDRE #( + .INIT(1'b1)) + TKin1_triggered_reg + (.C(externalCLK), + .CE(1'b1), + .D(TKin1_triggered_i_1_n_0), + .Q(TKin1_triggered), + .R(1'b0)); + LUT1 #( + .INIT(2'h1)) + \TimeCounter[0]_i_2 + (.I0(TimeCounter_reg[0]), + .O(\TimeCounter[0]_i_2_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[0] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[0]_i_1_n_7 ), + .Q(TimeCounter_reg[0]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[0]_i_1 + (.CI(1'b0), + .CO({\TimeCounter_reg[0]_i_1_n_0 ,\TimeCounter_reg[0]_i_1_n_1 ,\TimeCounter_reg[0]_i_1_n_2 ,\TimeCounter_reg[0]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\TimeCounter_reg[0]_i_1_n_4 ,\TimeCounter_reg[0]_i_1_n_5 ,\TimeCounter_reg[0]_i_1_n_6 ,\TimeCounter_reg[0]_i_1_n_7 }), + .S({TimeCounter_reg[3:1],\TimeCounter[0]_i_2_n_0 })); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[10] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[8]_i_1_n_5 ), + .Q(TimeCounter_reg[10]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[11] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[8]_i_1_n_4 ), + .Q(TimeCounter_reg[11]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[12] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[12]_i_1_n_7 ), + .Q(TimeCounter_reg[12]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[12]_i_1 + (.CI(\TimeCounter_reg[8]_i_1_n_0 ), + .CO({\TimeCounter_reg[12]_i_1_n_0 ,\TimeCounter_reg[12]_i_1_n_1 ,\TimeCounter_reg[12]_i_1_n_2 ,\TimeCounter_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[12]_i_1_n_4 ,\TimeCounter_reg[12]_i_1_n_5 ,\TimeCounter_reg[12]_i_1_n_6 ,\TimeCounter_reg[12]_i_1_n_7 }), + .S(TimeCounter_reg[15:12])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[13] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[12]_i_1_n_6 ), + .Q(TimeCounter_reg[13]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[14] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[12]_i_1_n_5 ), + .Q(TimeCounter_reg[14]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[15] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[12]_i_1_n_4 ), + .Q(TimeCounter_reg[15]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[16] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[16]_i_1_n_7 ), + .Q(TimeCounter_reg[16]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[16]_i_1 + (.CI(\TimeCounter_reg[12]_i_1_n_0 ), + .CO({\TimeCounter_reg[16]_i_1_n_0 ,\TimeCounter_reg[16]_i_1_n_1 ,\TimeCounter_reg[16]_i_1_n_2 ,\TimeCounter_reg[16]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[16]_i_1_n_4 ,\TimeCounter_reg[16]_i_1_n_5 ,\TimeCounter_reg[16]_i_1_n_6 ,\TimeCounter_reg[16]_i_1_n_7 }), + .S(TimeCounter_reg[19:16])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[17] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[16]_i_1_n_6 ), + .Q(TimeCounter_reg[17]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[18] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[16]_i_1_n_5 ), + .Q(TimeCounter_reg[18]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[19] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[16]_i_1_n_4 ), + .Q(TimeCounter_reg[19]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[1] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[0]_i_1_n_6 ), + .Q(TimeCounter_reg[1]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[20] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[20]_i_1_n_7 ), + .Q(TimeCounter_reg[20]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[20]_i_1 + (.CI(\TimeCounter_reg[16]_i_1_n_0 ), + .CO({\TimeCounter_reg[20]_i_1_n_0 ,\TimeCounter_reg[20]_i_1_n_1 ,\TimeCounter_reg[20]_i_1_n_2 ,\TimeCounter_reg[20]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[20]_i_1_n_4 ,\TimeCounter_reg[20]_i_1_n_5 ,\TimeCounter_reg[20]_i_1_n_6 ,\TimeCounter_reg[20]_i_1_n_7 }), + .S(TimeCounter_reg[23:20])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[21] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[20]_i_1_n_6 ), + .Q(TimeCounter_reg[21]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[22] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[20]_i_1_n_5 ), + .Q(TimeCounter_reg[22]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[23] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[20]_i_1_n_4 ), + .Q(TimeCounter_reg[23]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[24] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[24]_i_1_n_7 ), + .Q(TimeCounter_reg[24]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[24]_i_1 + (.CI(\TimeCounter_reg[20]_i_1_n_0 ), + .CO({\TimeCounter_reg[24]_i_1_n_0 ,\TimeCounter_reg[24]_i_1_n_1 ,\TimeCounter_reg[24]_i_1_n_2 ,\TimeCounter_reg[24]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[24]_i_1_n_4 ,\TimeCounter_reg[24]_i_1_n_5 ,\TimeCounter_reg[24]_i_1_n_6 ,\TimeCounter_reg[24]_i_1_n_7 }), + .S(TimeCounter_reg[27:24])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[25] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[24]_i_1_n_6 ), + .Q(TimeCounter_reg[25]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[26] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[24]_i_1_n_5 ), + .Q(TimeCounter_reg[26]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[27] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[24]_i_1_n_4 ), + .Q(TimeCounter_reg[27]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[28] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[28]_i_1_n_7 ), + .Q(TimeCounter_reg[28]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[28]_i_1 + (.CI(\TimeCounter_reg[24]_i_1_n_0 ), + .CO({\NLW_TimeCounter_reg[28]_i_1_CO_UNCONNECTED [3],\TimeCounter_reg[28]_i_1_n_1 ,\TimeCounter_reg[28]_i_1_n_2 ,\TimeCounter_reg[28]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[28]_i_1_n_4 ,\TimeCounter_reg[28]_i_1_n_5 ,\TimeCounter_reg[28]_i_1_n_6 ,\TimeCounter_reg[28]_i_1_n_7 }), + .S(TimeCounter_reg[31:28])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[29] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[28]_i_1_n_6 ), + .Q(TimeCounter_reg[29]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[2] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[0]_i_1_n_5 ), + .Q(TimeCounter_reg[2]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[30] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[28]_i_1_n_5 ), + .Q(TimeCounter_reg[30]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[31] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[28]_i_1_n_4 ), + .Q(TimeCounter_reg[31]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[3] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[0]_i_1_n_4 ), + .Q(TimeCounter_reg[3]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[4] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[4]_i_1_n_7 ), + .Q(TimeCounter_reg[4]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[4]_i_1 + (.CI(\TimeCounter_reg[0]_i_1_n_0 ), + .CO({\TimeCounter_reg[4]_i_1_n_0 ,\TimeCounter_reg[4]_i_1_n_1 ,\TimeCounter_reg[4]_i_1_n_2 ,\TimeCounter_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[4]_i_1_n_4 ,\TimeCounter_reg[4]_i_1_n_5 ,\TimeCounter_reg[4]_i_1_n_6 ,\TimeCounter_reg[4]_i_1_n_7 }), + .S(TimeCounter_reg[7:4])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[5] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[4]_i_1_n_6 ), + .Q(TimeCounter_reg[5]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[6] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[4]_i_1_n_5 ), + .Q(TimeCounter_reg[6]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[7] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[4]_i_1_n_4 ), + .Q(TimeCounter_reg[7]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[8] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[8]_i_1_n_7 ), + .Q(TimeCounter_reg[8]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[8]_i_1 + (.CI(\TimeCounter_reg[4]_i_1_n_0 ), + .CO({\TimeCounter_reg[8]_i_1_n_0 ,\TimeCounter_reg[8]_i_1_n_1 ,\TimeCounter_reg[8]_i_1_n_2 ,\TimeCounter_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[8]_i_1_n_4 ,\TimeCounter_reg[8]_i_1_n_5 ,\TimeCounter_reg[8]_i_1_n_6 ,\TimeCounter_reg[8]_i_1_n_7 }), + .S(TimeCounter_reg[11:8])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[9] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[8]_i_1_n_6 ), + .Q(TimeCounter_reg[9]), + .R(deadTimeCounterReset_reg_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFE0000000E)) + deadTimeCounterReset_i_1 + (.I0(deadTimeCounterReset_i_2_n_0), + .I1(\FSM_onehot_lineconfig[6]_i_4_n_0 ), + .I2(reset), + .I3(breaking_en), + .I4(deadTimeCounterReset_i_3_n_0), + .I5(deadTimeCounterReset_reg_n_0), + .O(deadTimeCounterReset_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'hFE)) + deadTimeCounterReset_i_2 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .O(deadTimeCounterReset_i_2_n_0)); + LUT6 #( + .INIT(64'h0000000022220020)) + deadTimeCounterReset_i_3 + (.I0(deadTimeCounterReset_i_4_n_0), + .I1(deadTimeCounterReset_i_2_n_0), + .I2(deadTimeCounterReset_i_5_n_0), + .I3(deadTimeCounterReset_i_6_n_0), + .I4(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I5(deadTimeCounterReset_i_7_n_0), + .O(deadTimeCounterReset_i_3_n_0)); + LUT6 #( + .INIT(64'h555D555555555555)) + deadTimeCounterReset_i_4 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I1(deadTimeOK), + .I2(TKin1), + .I3(TKin1_triggered), + .I4(TKin0), + .I5(TKin0_triggered), + .O(deadTimeCounterReset_i_4_n_0)); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT3 #( + .INIT(8'h08)) + deadTimeCounterReset_i_5 + (.I0(deadTimeOK), + .I1(ready), + .I2(er), + .O(deadTimeCounterReset_i_5_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT4 #( + .INIT(16'hF777)) + deadTimeCounterReset_i_6 + (.I0(TKin0), + .I1(TKin1), + .I2(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I3(deadTimeCounterReset_reg_n_0), + .O(deadTimeCounterReset_i_6_n_0)); + LUT6 #( + .INIT(64'hAAAAA2AAAAAAAAAA)) + deadTimeCounterReset_i_7 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I1(TKin1), + .I2(TKin0), + .I3(deadTimeOK), + .I4(TKin0_triggered), + .I5(TKin1_triggered), + .O(deadTimeCounterReset_i_7_n_0)); + FDRE #( + .INIT(1'b0)) + deadTimeCounterReset_reg + (.C(externalCLK), + .CE(1'b1), + .D(deadTimeCounterReset_i_1_n_0), + .Q(deadTimeCounterReset_reg_n_0), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT3 #( + .INIT(8'h0D)) + deadTimeOK_i_1 + (.I0(sel), + .I1(deadTimeOK), + .I2(deadTimeCounterReset_reg_n_0), + .O(deadTimeOK_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + deadTimeOK_reg + (.C(externalCLK), + .CE(1'b1), + .D(deadTimeOK_i_1_n_0), + .Q(deadTimeOK), + .R(1'b0)); + LUT6 #( + .INIT(64'hDDDDDDD0DDDDDDDD)) + key1_i_1 + (.I0(breaking_en), + .I1(TKin0), + .I2(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I4(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I5(key1_i_2_n_0), + .O(key1_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT4 #( + .INIT(16'h0001)) + key1_i_2 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I3(breaking_en), + .O(key1_i_2_n_0)); + FDRE #( + .INIT(1'b1)) + key1_prev_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key1_reg_n_0), + .Q(key1_prev), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + key1_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key1_i_1_n_0), + .Q(key1_reg_n_0), + .R(1'b0)); + LUT1 #( + .INIT(2'h1)) + key2_i_1 + (.I0(reset), + .O(p_0_in)); + LUT6 #( + .INIT(64'hAAAAAAAAFFFFFFFC)) + key2_i_2 + (.I0(TKin1), + .I1(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I4(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I5(breaking_en), + .O(key2_i_2_n_0)); + FDRE #( + .INIT(1'b1)) + key2_prev_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key2_reg_n_0), + .Q(key2_prev), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + key2_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key2_i_2_n_0), + .Q(key2_reg_n_0), + .R(1'b0)); + LUT6 #( + .INIT(64'hAAAAFFFFAAAAFCFF)) + key3_i_1 + (.I0(key3_reg_n_0), + .I1(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I3(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I4(reset), + .I5(breaking_en), + .O(key3_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + key3_prev_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key3_reg_n_0), + .Q(key3_prev), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + key3_reg + (.C(externalCLK), + .CE(1'b1), + .D(key3_i_1_n_0), + .Q(key3_reg_n_0), + .R(1'b0)); + LUT6 #( + .INIT(64'hAAAAFFFFAAAAFFFC)) + key4_i_1 + (.I0(key4_reg_n_0), + .I1(key3), + .I2(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I4(reset), + .I5(breaking_en), + .O(key4_i_1_n_0)); + LUT4 #( + .INIT(16'hFFFE)) + key4_i_2 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .O(key3)); + FDRE #( + .INIT(1'b1)) + key4_prev_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key4_reg_n_0), + .Q(key4_prev), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + key4_reg + (.C(externalCLK), + .CE(1'b1), + .D(key4_i_1_n_0), + .Q(key4_reg_n_0), + .R(1'b0)); + CARRY4 ltOp__15_carry + (.CI(1'b0), + .CO({ltOp__15_carry_n_0,ltOp__15_carry_n_1,ltOp__15_carry_n_2,ltOp__15_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp__15_carry_i_1_n_0,ltOp__15_carry_i_2_n_0,ltOp__15_carry_i_3_n_0,ltOp__15_carry_i_4_n_0}), + .O(NLW_ltOp__15_carry_O_UNCONNECTED[3:0]), + .S({ltOp__15_carry_i_5_n_0,ltOp__15_carry_i_6_n_0,ltOp__15_carry_i_7_n_0,ltOp__15_carry_i_8_n_0})); + CARRY4 ltOp__15_carry__0 + (.CI(ltOp__15_carry_n_0), + .CO({ltOp__15_carry__0_n_0,ltOp__15_carry__0_n_1,ltOp__15_carry__0_n_2,ltOp__15_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp__15_carry__0_i_1_n_0,ltOp__15_carry__0_i_2_n_0,ltOp__15_carry__0_i_3_n_0,ltOp__15_carry__0_i_4_n_0}), + .O(NLW_ltOp__15_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp__15_carry__0_i_5_n_0,ltOp__15_carry__0_i_6_n_0,ltOp__15_carry__0_i_7_n_0,ltOp__15_carry__0_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__0_i_1 + (.I0(minTime[15]), + .I1(minTimeCounter_low_reg[15]), + .I2(minTime[14]), + .I3(minTimeCounter_low_reg[14]), + .O(ltOp__15_carry__0_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__0_i_2 + (.I0(minTime[13]), + .I1(minTimeCounter_low_reg[13]), + .I2(minTime[12]), + .I3(minTimeCounter_low_reg[12]), + .O(ltOp__15_carry__0_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__0_i_3 + (.I0(minTime[11]), + .I1(minTimeCounter_low_reg[11]), + .I2(minTime[10]), + .I3(minTimeCounter_low_reg[10]), + .O(ltOp__15_carry__0_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__0_i_4 + (.I0(minTime[9]), + .I1(minTimeCounter_low_reg[9]), + .I2(minTime[8]), + .I3(minTimeCounter_low_reg[8]), + .O(ltOp__15_carry__0_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__0_i_5 + (.I0(minTimeCounter_low_reg[15]), + .I1(minTime[15]), + .I2(minTimeCounter_low_reg[14]), + .I3(minTime[14]), + .O(ltOp__15_carry__0_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__0_i_6 + (.I0(minTimeCounter_low_reg[13]), + .I1(minTime[13]), + .I2(minTimeCounter_low_reg[12]), + .I3(minTime[12]), + .O(ltOp__15_carry__0_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__0_i_7 + (.I0(minTimeCounter_low_reg[11]), + .I1(minTime[11]), + .I2(minTimeCounter_low_reg[10]), + .I3(minTime[10]), + .O(ltOp__15_carry__0_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__0_i_8 + (.I0(minTimeCounter_low_reg[9]), + .I1(minTime[9]), + .I2(minTimeCounter_low_reg[8]), + .I3(minTime[8]), + .O(ltOp__15_carry__0_i_8_n_0)); + CARRY4 ltOp__15_carry__1 + (.CI(ltOp__15_carry__0_n_0), + .CO({ltOp__15_carry__1_n_0,ltOp__15_carry__1_n_1,ltOp__15_carry__1_n_2,ltOp__15_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp__15_carry__1_i_1_n_0,ltOp__15_carry__1_i_2_n_0,ltOp__15_carry__1_i_3_n_0,ltOp__15_carry__1_i_4_n_0}), + .O(NLW_ltOp__15_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp__15_carry__1_i_5_n_0,ltOp__15_carry__1_i_6_n_0,ltOp__15_carry__1_i_7_n_0,ltOp__15_carry__1_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__1_i_1 + (.I0(minTime[23]), + .I1(minTimeCounter_low_reg[23]), + .I2(minTime[22]), + .I3(minTimeCounter_low_reg[22]), + .O(ltOp__15_carry__1_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__1_i_2 + (.I0(minTime[21]), + .I1(minTimeCounter_low_reg[21]), + .I2(minTime[20]), + .I3(minTimeCounter_low_reg[20]), + .O(ltOp__15_carry__1_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__1_i_3 + (.I0(minTime[19]), + .I1(minTimeCounter_low_reg[19]), + .I2(minTime[18]), + .I3(minTimeCounter_low_reg[18]), + .O(ltOp__15_carry__1_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__1_i_4 + (.I0(minTime[17]), + .I1(minTimeCounter_low_reg[17]), + .I2(minTime[16]), + .I3(minTimeCounter_low_reg[16]), + .O(ltOp__15_carry__1_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__1_i_5 + (.I0(minTimeCounter_low_reg[23]), + .I1(minTime[23]), + .I2(minTimeCounter_low_reg[22]), + .I3(minTime[22]), + .O(ltOp__15_carry__1_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__1_i_6 + (.I0(minTimeCounter_low_reg[21]), + .I1(minTime[21]), + .I2(minTimeCounter_low_reg[20]), + .I3(minTime[20]), + .O(ltOp__15_carry__1_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__1_i_7 + (.I0(minTimeCounter_low_reg[19]), + .I1(minTime[19]), + .I2(minTimeCounter_low_reg[18]), + .I3(minTime[18]), + .O(ltOp__15_carry__1_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__1_i_8 + (.I0(minTimeCounter_low_reg[17]), + .I1(minTime[17]), + .I2(minTimeCounter_low_reg[16]), + .I3(minTime[16]), + .O(ltOp__15_carry__1_i_8_n_0)); + CARRY4 ltOp__15_carry__2 + (.CI(ltOp__15_carry__1_n_0), + .CO({ltOp__15_carry__2_n_0,ltOp__15_carry__2_n_1,ltOp__15_carry__2_n_2,ltOp__15_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp__15_carry__2_i_1_n_0,ltOp__15_carry__2_i_2_n_0,ltOp__15_carry__2_i_3_n_0,ltOp__15_carry__2_i_4_n_0}), + .O(NLW_ltOp__15_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp__15_carry__2_i_5_n_0,ltOp__15_carry__2_i_6_n_0,ltOp__15_carry__2_i_7_n_0,ltOp__15_carry__2_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__2_i_1 + (.I0(minTime[31]), + .I1(minTimeCounter_low_reg[31]), + .I2(minTime[30]), + .I3(minTimeCounter_low_reg[30]), + .O(ltOp__15_carry__2_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__2_i_2 + (.I0(minTime[29]), + .I1(minTimeCounter_low_reg[29]), + .I2(minTime[28]), + .I3(minTimeCounter_low_reg[28]), + .O(ltOp__15_carry__2_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__2_i_3 + (.I0(minTime[27]), + .I1(minTimeCounter_low_reg[27]), + .I2(minTime[26]), + .I3(minTimeCounter_low_reg[26]), + .O(ltOp__15_carry__2_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__2_i_4 + (.I0(minTime[25]), + .I1(minTimeCounter_low_reg[25]), + .I2(minTime[24]), + .I3(minTimeCounter_low_reg[24]), + .O(ltOp__15_carry__2_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__2_i_5 + (.I0(minTimeCounter_low_reg[31]), + .I1(minTime[31]), + .I2(minTimeCounter_low_reg[30]), + .I3(minTime[30]), + .O(ltOp__15_carry__2_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__2_i_6 + (.I0(minTimeCounter_low_reg[29]), + .I1(minTime[29]), + .I2(minTimeCounter_low_reg[28]), + .I3(minTime[28]), + .O(ltOp__15_carry__2_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__2_i_7 + (.I0(minTimeCounter_low_reg[27]), + .I1(minTime[27]), + .I2(minTimeCounter_low_reg[26]), + .I3(minTime[26]), + .O(ltOp__15_carry__2_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__2_i_8 + (.I0(minTimeCounter_low_reg[25]), + .I1(minTime[25]), + .I2(minTimeCounter_low_reg[24]), + .I3(minTime[24]), + .O(ltOp__15_carry__2_i_8_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry_i_1 + (.I0(minTime[7]), + .I1(minTimeCounter_low_reg[7]), + .I2(minTime[6]), + .I3(minTimeCounter_low_reg[6]), + .O(ltOp__15_carry_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry_i_2 + (.I0(minTime[5]), + .I1(minTimeCounter_low_reg[5]), + .I2(minTime[4]), + .I3(minTimeCounter_low_reg[4]), + .O(ltOp__15_carry_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry_i_3 + (.I0(minTime[3]), + .I1(minTimeCounter_low_reg[3]), + .I2(minTime[2]), + .I3(minTimeCounter_low_reg[2]), + .O(ltOp__15_carry_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry_i_4 + (.I0(minTime[1]), + .I1(minTimeCounter_low_reg[1]), + .I2(minTime[0]), + .I3(minTimeCounter_low_reg[0]), + .O(ltOp__15_carry_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry_i_5 + (.I0(minTimeCounter_low_reg[7]), + .I1(minTime[7]), + .I2(minTimeCounter_low_reg[6]), + .I3(minTime[6]), + .O(ltOp__15_carry_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry_i_6 + (.I0(minTimeCounter_low_reg[5]), + .I1(minTime[5]), + .I2(minTimeCounter_low_reg[4]), + .I3(minTime[4]), + .O(ltOp__15_carry_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry_i_7 + (.I0(minTimeCounter_low_reg[3]), + .I1(minTime[3]), + .I2(minTimeCounter_low_reg[2]), + .I3(minTime[2]), + .O(ltOp__15_carry_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry_i_8 + (.I0(minTimeCounter_low_reg[1]), + .I1(minTime[1]), + .I2(minTimeCounter_low_reg[0]), + .I3(minTime[0]), + .O(ltOp__15_carry_i_8_n_0)); + CARRY4 ltOp__31_carry + (.CI(1'b0), + .CO({ltOp__31_carry_n_0,ltOp__31_carry_n_1,ltOp__31_carry_n_2,ltOp__31_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp__31_carry_i_1_n_0,ltOp__31_carry_i_2_n_0,ltOp__31_carry_i_3_n_0,ltOp__31_carry_i_4_n_0}), + .O(NLW_ltOp__31_carry_O_UNCONNECTED[3:0]), + .S({ltOp__31_carry_i_5_n_0,ltOp__31_carry_i_6_n_0,ltOp__31_carry_i_7_n_0,ltOp__31_carry_i_8_n_0})); + CARRY4 ltOp__31_carry__0 + (.CI(ltOp__31_carry_n_0), + .CO({ltOp__31_carry__0_n_0,ltOp__31_carry__0_n_1,ltOp__31_carry__0_n_2,ltOp__31_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp__31_carry_i_1__0_n_0,ltOp__31_carry_i_2__0_n_0,ltOp__31_carry_i_3__0_n_0,ltOp__31_carry_i_4__0_n_0}), + .O(NLW_ltOp__31_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp__31_carry_i_5__0_n_0,ltOp__31_carry_i_6__0_n_0,ltOp__31_carry_i_7__0_n_0,ltOp__31_carry_i_8__0_n_0})); + CARRY4 ltOp__31_carry__1 + (.CI(ltOp__31_carry__0_n_0), + .CO({ltOp__31_carry__1_n_0,ltOp__31_carry__1_n_1,ltOp__31_carry__1_n_2,ltOp__31_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp__31_carry_i_1__1_n_0,ltOp__31_carry_i_2__1_n_0,ltOp__31_carry_i_3__1_n_0,ltOp__31_carry_i_4__1_n_0}), + .O(NLW_ltOp__31_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp__31_carry_i_5__1_n_0,ltOp__31_carry_i_6__1_n_0,ltOp__31_carry_i_7__1_n_0,ltOp__31_carry_i_8__1_n_0})); + CARRY4 ltOp__31_carry__2 + (.CI(ltOp__31_carry__1_n_0), + .CO({ltOp__31_carry__2_n_0,ltOp__31_carry__2_n_1,ltOp__31_carry__2_n_2,ltOp__31_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp__31_carry_i_1__2_n_0,ltOp__31_carry_i_2__2_n_0,ltOp__31_carry_i_3__2_n_0,ltOp__31_carry_i_4__2_n_0}), + .O(NLW_ltOp__31_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp__31_carry_i_5__2_n_0,ltOp__31_carry_i_6__2_n_0,ltOp__31_carry_i_7__2_n_0,ltOp__31_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_1 + (.I0(minTime[7]), + .I1(minTimeCounter_high_reg[7]), + .I2(minTime[6]), + .I3(minTimeCounter_high_reg[6]), + .O(ltOp__31_carry_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_1__0 + (.I0(minTime[15]), + .I1(minTimeCounter_high_reg[15]), + .I2(minTime[14]), + .I3(minTimeCounter_high_reg[14]), + .O(ltOp__31_carry_i_1__0_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_1__1 + (.I0(minTime[23]), + .I1(minTimeCounter_high_reg[23]), + .I2(minTime[22]), + .I3(minTimeCounter_high_reg[22]), + .O(ltOp__31_carry_i_1__1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_1__2 + (.I0(minTime[31]), + .I1(minTimeCounter_high_reg[31]), + .I2(minTime[30]), + .I3(minTimeCounter_high_reg[30]), + .O(ltOp__31_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_2 + (.I0(minTime[5]), + .I1(minTimeCounter_high_reg[5]), + .I2(minTime[4]), + .I3(minTimeCounter_high_reg[4]), + .O(ltOp__31_carry_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_2__0 + (.I0(minTime[13]), + .I1(minTimeCounter_high_reg[13]), + .I2(minTime[12]), + .I3(minTimeCounter_high_reg[12]), + .O(ltOp__31_carry_i_2__0_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_2__1 + (.I0(minTime[21]), + .I1(minTimeCounter_high_reg[21]), + .I2(minTime[20]), + .I3(minTimeCounter_high_reg[20]), + .O(ltOp__31_carry_i_2__1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_2__2 + (.I0(minTime[29]), + .I1(minTimeCounter_high_reg[29]), + .I2(minTime[28]), + .I3(minTimeCounter_high_reg[28]), + .O(ltOp__31_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_3 + (.I0(minTime[3]), + .I1(minTimeCounter_high_reg[3]), + .I2(minTime[2]), + .I3(minTimeCounter_high_reg[2]), + .O(ltOp__31_carry_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_3__0 + (.I0(minTime[11]), + .I1(minTimeCounter_high_reg[11]), + .I2(minTime[10]), + .I3(minTimeCounter_high_reg[10]), + .O(ltOp__31_carry_i_3__0_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_3__1 + (.I0(minTime[19]), + .I1(minTimeCounter_high_reg[19]), + .I2(minTime[18]), + .I3(minTimeCounter_high_reg[18]), + .O(ltOp__31_carry_i_3__1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_3__2 + (.I0(minTime[27]), + .I1(minTimeCounter_high_reg[27]), + .I2(minTime[26]), + .I3(minTimeCounter_high_reg[26]), + .O(ltOp__31_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_4 + (.I0(minTime[1]), + .I1(minTimeCounter_high_reg[1]), + .I2(minTime[0]), + .I3(minTimeCounter_high_reg[0]), + .O(ltOp__31_carry_i_4_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_4__0 + (.I0(minTime[9]), + .I1(minTimeCounter_high_reg[9]), + .I2(minTime[8]), + .I3(minTimeCounter_high_reg[8]), + .O(ltOp__31_carry_i_4__0_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_4__1 + (.I0(minTime[17]), + .I1(minTimeCounter_high_reg[17]), + .I2(minTime[16]), + .I3(minTimeCounter_high_reg[16]), + .O(ltOp__31_carry_i_4__1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_4__2 + (.I0(minTime[25]), + .I1(minTimeCounter_high_reg[25]), + .I2(minTime[24]), + .I3(minTimeCounter_high_reg[24]), + .O(ltOp__31_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_5 + (.I0(minTimeCounter_high_reg[7]), + .I1(minTime[7]), + .I2(minTimeCounter_high_reg[6]), + .I3(minTime[6]), + .O(ltOp__31_carry_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_5__0 + (.I0(minTimeCounter_high_reg[15]), + .I1(minTime[15]), + .I2(minTimeCounter_high_reg[14]), + .I3(minTime[14]), + .O(ltOp__31_carry_i_5__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_5__1 + (.I0(minTimeCounter_high_reg[23]), + .I1(minTime[23]), + .I2(minTimeCounter_high_reg[22]), + .I3(minTime[22]), + .O(ltOp__31_carry_i_5__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_5__2 + (.I0(minTimeCounter_high_reg[31]), + .I1(minTime[31]), + .I2(minTimeCounter_high_reg[30]), + .I3(minTime[30]), + .O(ltOp__31_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_6 + (.I0(minTimeCounter_high_reg[5]), + .I1(minTime[5]), + .I2(minTimeCounter_high_reg[4]), + .I3(minTime[4]), + .O(ltOp__31_carry_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_6__0 + (.I0(minTimeCounter_high_reg[13]), + .I1(minTime[13]), + .I2(minTimeCounter_high_reg[12]), + .I3(minTime[12]), + .O(ltOp__31_carry_i_6__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_6__1 + (.I0(minTimeCounter_high_reg[21]), + .I1(minTime[21]), + .I2(minTimeCounter_high_reg[20]), + .I3(minTime[20]), + .O(ltOp__31_carry_i_6__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_6__2 + (.I0(minTimeCounter_high_reg[29]), + .I1(minTime[29]), + .I2(minTimeCounter_high_reg[28]), + .I3(minTime[28]), + .O(ltOp__31_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_7 + (.I0(minTimeCounter_high_reg[3]), + .I1(minTime[3]), + .I2(minTimeCounter_high_reg[2]), + .I3(minTime[2]), + .O(ltOp__31_carry_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_7__0 + (.I0(minTimeCounter_high_reg[11]), + .I1(minTime[11]), + .I2(minTimeCounter_high_reg[10]), + .I3(minTime[10]), + .O(ltOp__31_carry_i_7__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_7__1 + (.I0(minTimeCounter_high_reg[19]), + .I1(minTime[19]), + .I2(minTimeCounter_high_reg[18]), + .I3(minTime[18]), + .O(ltOp__31_carry_i_7__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_7__2 + (.I0(minTimeCounter_high_reg[27]), + .I1(minTime[27]), + .I2(minTimeCounter_high_reg[26]), + .I3(minTime[26]), + .O(ltOp__31_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_8 + (.I0(minTimeCounter_high_reg[1]), + .I1(minTime[1]), + .I2(minTimeCounter_high_reg[0]), + .I3(minTime[0]), + .O(ltOp__31_carry_i_8_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_8__0 + (.I0(minTimeCounter_high_reg[9]), + .I1(minTime[9]), + .I2(minTimeCounter_high_reg[8]), + .I3(minTime[8]), + .O(ltOp__31_carry_i_8__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_8__1 + (.I0(minTimeCounter_high_reg[17]), + .I1(minTime[17]), + .I2(minTimeCounter_high_reg[16]), + .I3(minTime[16]), + .O(ltOp__31_carry_i_8__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_8__2 + (.I0(minTimeCounter_high_reg[25]), + .I1(minTime[25]), + .I2(minTimeCounter_high_reg[24]), + .I3(minTime[24]), + .O(ltOp__31_carry_i_8__2_n_0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry__0_i_1_n_0,ltOp_carry__0_i_2_n_0,ltOp_carry__0_i_3_n_0,ltOp_carry__0_i_4_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry__0_i_5_n_0,ltOp_carry__0_i_6_n_0,ltOp_carry__0_i_7_n_0,ltOp_carry__0_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__0_i_1 + (.I0(deadTime[15]), + .I1(TimeCounter_reg[15]), + .I2(deadTime[14]), + .I3(TimeCounter_reg[14]), + .O(ltOp_carry__0_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__0_i_2 + (.I0(deadTime[13]), + .I1(TimeCounter_reg[13]), + .I2(deadTime[12]), + .I3(TimeCounter_reg[12]), + .O(ltOp_carry__0_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__0_i_3 + (.I0(deadTime[11]), + .I1(TimeCounter_reg[11]), + .I2(deadTime[10]), + .I3(TimeCounter_reg[10]), + .O(ltOp_carry__0_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__0_i_4 + (.I0(deadTime[9]), + .I1(TimeCounter_reg[9]), + .I2(deadTime[8]), + .I3(TimeCounter_reg[8]), + .O(ltOp_carry__0_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__0_i_5 + (.I0(TimeCounter_reg[15]), + .I1(deadTime[15]), + .I2(TimeCounter_reg[14]), + .I3(deadTime[14]), + .O(ltOp_carry__0_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__0_i_6 + (.I0(TimeCounter_reg[13]), + .I1(deadTime[13]), + .I2(TimeCounter_reg[12]), + .I3(deadTime[12]), + .O(ltOp_carry__0_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__0_i_7 + (.I0(TimeCounter_reg[11]), + .I1(deadTime[11]), + .I2(TimeCounter_reg[10]), + .I3(deadTime[10]), + .O(ltOp_carry__0_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__0_i_8 + (.I0(TimeCounter_reg[9]), + .I1(deadTime[9]), + .I2(TimeCounter_reg[8]), + .I3(deadTime[8]), + .O(ltOp_carry__0_i_8_n_0)); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry__1_i_1_n_0,ltOp_carry__1_i_2_n_0,ltOp_carry__1_i_3_n_0,ltOp_carry__1_i_4_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry__1_i_5_n_0,ltOp_carry__1_i_6_n_0,ltOp_carry__1_i_7_n_0,ltOp_carry__1_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__1_i_1 + (.I0(deadTime[23]), + .I1(TimeCounter_reg[23]), + .I2(deadTime[22]), + .I3(TimeCounter_reg[22]), + .O(ltOp_carry__1_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__1_i_2 + (.I0(deadTime[21]), + .I1(TimeCounter_reg[21]), + .I2(deadTime[20]), + .I3(TimeCounter_reg[20]), + .O(ltOp_carry__1_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__1_i_3 + (.I0(deadTime[19]), + .I1(TimeCounter_reg[19]), + .I2(deadTime[18]), + .I3(TimeCounter_reg[18]), + .O(ltOp_carry__1_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__1_i_4 + (.I0(deadTime[17]), + .I1(TimeCounter_reg[17]), + .I2(deadTime[16]), + .I3(TimeCounter_reg[16]), + .O(ltOp_carry__1_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__1_i_5 + (.I0(TimeCounter_reg[23]), + .I1(deadTime[23]), + .I2(TimeCounter_reg[22]), + .I3(deadTime[22]), + .O(ltOp_carry__1_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__1_i_6 + (.I0(TimeCounter_reg[21]), + .I1(deadTime[21]), + .I2(TimeCounter_reg[20]), + .I3(deadTime[20]), + .O(ltOp_carry__1_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__1_i_7 + (.I0(TimeCounter_reg[19]), + .I1(deadTime[19]), + .I2(TimeCounter_reg[18]), + .I3(deadTime[18]), + .O(ltOp_carry__1_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__1_i_8 + (.I0(TimeCounter_reg[17]), + .I1(deadTime[17]), + .I2(TimeCounter_reg[16]), + .I3(deadTime[16]), + .O(ltOp_carry__1_i_8_n_0)); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({sel,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry__2_i_1_n_0,ltOp_carry__2_i_2_n_0,ltOp_carry__2_i_3_n_0,ltOp_carry__2_i_4_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry__2_i_5_n_0,ltOp_carry__2_i_6_n_0,ltOp_carry__2_i_7_n_0,ltOp_carry__2_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__2_i_1 + (.I0(deadTime[31]), + .I1(TimeCounter_reg[31]), + .I2(deadTime[30]), + .I3(TimeCounter_reg[30]), + .O(ltOp_carry__2_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__2_i_2 + (.I0(deadTime[29]), + .I1(TimeCounter_reg[29]), + .I2(deadTime[28]), + .I3(TimeCounter_reg[28]), + .O(ltOp_carry__2_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__2_i_3 + (.I0(deadTime[27]), + .I1(TimeCounter_reg[27]), + .I2(deadTime[26]), + .I3(TimeCounter_reg[26]), + .O(ltOp_carry__2_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__2_i_4 + (.I0(deadTime[25]), + .I1(TimeCounter_reg[25]), + .I2(deadTime[24]), + .I3(TimeCounter_reg[24]), + .O(ltOp_carry__2_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__2_i_5 + (.I0(TimeCounter_reg[31]), + .I1(deadTime[31]), + .I2(TimeCounter_reg[30]), + .I3(deadTime[30]), + .O(ltOp_carry__2_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__2_i_6 + (.I0(TimeCounter_reg[29]), + .I1(deadTime[29]), + .I2(TimeCounter_reg[28]), + .I3(deadTime[28]), + .O(ltOp_carry__2_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__2_i_7 + (.I0(TimeCounter_reg[27]), + .I1(deadTime[27]), + .I2(TimeCounter_reg[26]), + .I3(deadTime[26]), + .O(ltOp_carry__2_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__2_i_8 + (.I0(TimeCounter_reg[25]), + .I1(deadTime[25]), + .I2(TimeCounter_reg[24]), + .I3(deadTime[24]), + .O(ltOp_carry__2_i_8_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry_i_1 + (.I0(deadTime[7]), + .I1(TimeCounter_reg[7]), + .I2(deadTime[6]), + .I3(TimeCounter_reg[6]), + .O(ltOp_carry_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry_i_2 + (.I0(deadTime[5]), + .I1(TimeCounter_reg[5]), + .I2(deadTime[4]), + .I3(TimeCounter_reg[4]), + .O(ltOp_carry_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry_i_3 + (.I0(deadTime[3]), + .I1(TimeCounter_reg[3]), + .I2(deadTime[2]), + .I3(TimeCounter_reg[2]), + .O(ltOp_carry_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry_i_4 + (.I0(deadTime[1]), + .I1(TimeCounter_reg[1]), + .I2(deadTime[0]), + .I3(TimeCounter_reg[0]), + .O(ltOp_carry_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(TimeCounter_reg[7]), + .I1(deadTime[7]), + .I2(TimeCounter_reg[6]), + .I3(deadTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(TimeCounter_reg[5]), + .I1(deadTime[5]), + .I2(TimeCounter_reg[4]), + .I3(deadTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(TimeCounter_reg[3]), + .I1(deadTime[3]), + .I2(TimeCounter_reg[2]), + .I3(deadTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(TimeCounter_reg[1]), + .I1(deadTime[1]), + .I2(TimeCounter_reg[0]), + .I3(deadTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT6 #( + .INIT(64'h0000000022222F22)) + \minTimeCounter_high[0]_i_1 + (.I0(key1_prev), + .I1(key1_reg_n_0), + .I2(key2_reg_n_0), + .I3(key2_prev), + .I4(breaking_en), + .I5(reset), + .O(\minTimeCounter_high[0]_i_1_n_0 )); + LUT2 #( + .INIT(4'h2)) + \minTimeCounter_high[0]_i_2 + (.I0(ltOp__31_carry__2_n_0), + .I1(reset), + .O(minTimeCounter_high)); + LUT1 #( + .INIT(2'h1)) + \minTimeCounter_high[0]_i_4 + (.I0(minTimeCounter_high_reg[0]), + .O(\minTimeCounter_high[0]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[0] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[0]_i_3_n_7 ), + .Q(minTimeCounter_high_reg[0]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[0]_i_3 + (.CI(1'b0), + .CO({\minTimeCounter_high_reg[0]_i_3_n_0 ,\minTimeCounter_high_reg[0]_i_3_n_1 ,\minTimeCounter_high_reg[0]_i_3_n_2 ,\minTimeCounter_high_reg[0]_i_3_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\minTimeCounter_high_reg[0]_i_3_n_4 ,\minTimeCounter_high_reg[0]_i_3_n_5 ,\minTimeCounter_high_reg[0]_i_3_n_6 ,\minTimeCounter_high_reg[0]_i_3_n_7 }), + .S({minTimeCounter_high_reg[3:1],\minTimeCounter_high[0]_i_4_n_0 })); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[10] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[8]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[10]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[11] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[8]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[11]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[12] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[12]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[12]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[12]_i_1 + (.CI(\minTimeCounter_high_reg[8]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[12]_i_1_n_0 ,\minTimeCounter_high_reg[12]_i_1_n_1 ,\minTimeCounter_high_reg[12]_i_1_n_2 ,\minTimeCounter_high_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[12]_i_1_n_4 ,\minTimeCounter_high_reg[12]_i_1_n_5 ,\minTimeCounter_high_reg[12]_i_1_n_6 ,\minTimeCounter_high_reg[12]_i_1_n_7 }), + .S(minTimeCounter_high_reg[15:12])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[13] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[12]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[13]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[14] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[12]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[14]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[15] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[12]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[15]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[16] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[16]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[16]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[16]_i_1 + (.CI(\minTimeCounter_high_reg[12]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[16]_i_1_n_0 ,\minTimeCounter_high_reg[16]_i_1_n_1 ,\minTimeCounter_high_reg[16]_i_1_n_2 ,\minTimeCounter_high_reg[16]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[16]_i_1_n_4 ,\minTimeCounter_high_reg[16]_i_1_n_5 ,\minTimeCounter_high_reg[16]_i_1_n_6 ,\minTimeCounter_high_reg[16]_i_1_n_7 }), + .S(minTimeCounter_high_reg[19:16])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[17] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[16]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[17]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[18] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[16]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[18]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[19] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[16]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[19]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[1] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[0]_i_3_n_6 ), + .Q(minTimeCounter_high_reg[1]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[20] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[20]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[20]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[20]_i_1 + (.CI(\minTimeCounter_high_reg[16]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[20]_i_1_n_0 ,\minTimeCounter_high_reg[20]_i_1_n_1 ,\minTimeCounter_high_reg[20]_i_1_n_2 ,\minTimeCounter_high_reg[20]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[20]_i_1_n_4 ,\minTimeCounter_high_reg[20]_i_1_n_5 ,\minTimeCounter_high_reg[20]_i_1_n_6 ,\minTimeCounter_high_reg[20]_i_1_n_7 }), + .S(minTimeCounter_high_reg[23:20])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[21] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[20]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[21]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[22] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[20]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[22]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[23] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[20]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[23]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[24] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[24]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[24]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[24]_i_1 + (.CI(\minTimeCounter_high_reg[20]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[24]_i_1_n_0 ,\minTimeCounter_high_reg[24]_i_1_n_1 ,\minTimeCounter_high_reg[24]_i_1_n_2 ,\minTimeCounter_high_reg[24]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[24]_i_1_n_4 ,\minTimeCounter_high_reg[24]_i_1_n_5 ,\minTimeCounter_high_reg[24]_i_1_n_6 ,\minTimeCounter_high_reg[24]_i_1_n_7 }), + .S(minTimeCounter_high_reg[27:24])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[25] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[24]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[25]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[26] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[24]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[26]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[27] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[24]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[27]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[28] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[28]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[28]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[28]_i_1 + (.CI(\minTimeCounter_high_reg[24]_i_1_n_0 ), + .CO({\NLW_minTimeCounter_high_reg[28]_i_1_CO_UNCONNECTED [3],\minTimeCounter_high_reg[28]_i_1_n_1 ,\minTimeCounter_high_reg[28]_i_1_n_2 ,\minTimeCounter_high_reg[28]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[28]_i_1_n_4 ,\minTimeCounter_high_reg[28]_i_1_n_5 ,\minTimeCounter_high_reg[28]_i_1_n_6 ,\minTimeCounter_high_reg[28]_i_1_n_7 }), + .S(minTimeCounter_high_reg[31:28])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[29] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[28]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[29]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[2] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[0]_i_3_n_5 ), + .Q(minTimeCounter_high_reg[2]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[30] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[28]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[30]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[31] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[28]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[31]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[3] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[0]_i_3_n_4 ), + .Q(minTimeCounter_high_reg[3]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[4] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[4]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[4]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[4]_i_1 + (.CI(\minTimeCounter_high_reg[0]_i_3_n_0 ), + .CO({\minTimeCounter_high_reg[4]_i_1_n_0 ,\minTimeCounter_high_reg[4]_i_1_n_1 ,\minTimeCounter_high_reg[4]_i_1_n_2 ,\minTimeCounter_high_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[4]_i_1_n_4 ,\minTimeCounter_high_reg[4]_i_1_n_5 ,\minTimeCounter_high_reg[4]_i_1_n_6 ,\minTimeCounter_high_reg[4]_i_1_n_7 }), + .S(minTimeCounter_high_reg[7:4])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[5] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[4]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[5]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[6] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[4]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[6]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[7] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[4]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[7]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[8] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[8]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[8]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[8]_i_1 + (.CI(\minTimeCounter_high_reg[4]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[8]_i_1_n_0 ,\minTimeCounter_high_reg[8]_i_1_n_1 ,\minTimeCounter_high_reg[8]_i_1_n_2 ,\minTimeCounter_high_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[8]_i_1_n_4 ,\minTimeCounter_high_reg[8]_i_1_n_5 ,\minTimeCounter_high_reg[8]_i_1_n_6 ,\minTimeCounter_high_reg[8]_i_1_n_7 }), + .S(minTimeCounter_high_reg[11:8])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[9] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[8]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[9]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + LUT5 #( + .INIT(32'h0000440F)) + \minTimeCounter_low[0]_i_1 + (.I0(key2_reg_n_0), + .I1(key2_prev), + .I2(\minTimeCounter_low[0]_i_4_n_0 ), + .I3(breaking_en), + .I4(reset), + .O(\minTimeCounter_low[0]_i_1_n_0 )); + LUT2 #( + .INIT(4'h2)) + \minTimeCounter_low[0]_i_2 + (.I0(ltOp__15_carry__2_n_0), + .I1(reset), + .O(minTimeCounter_low)); + LUT4 #( + .INIT(16'hD0DD)) + \minTimeCounter_low[0]_i_4 + (.I0(key4_prev), + .I1(key4_reg_n_0), + .I2(key3_reg_n_0), + .I3(key3_prev), + .O(\minTimeCounter_low[0]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \minTimeCounter_low[0]_i_5 + (.I0(minTimeCounter_low_reg[0]), + .O(\minTimeCounter_low[0]_i_5_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[0] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[0]_i_3_n_7 ), + .Q(minTimeCounter_low_reg[0]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[0]_i_3 + (.CI(1'b0), + .CO({\minTimeCounter_low_reg[0]_i_3_n_0 ,\minTimeCounter_low_reg[0]_i_3_n_1 ,\minTimeCounter_low_reg[0]_i_3_n_2 ,\minTimeCounter_low_reg[0]_i_3_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\minTimeCounter_low_reg[0]_i_3_n_4 ,\minTimeCounter_low_reg[0]_i_3_n_5 ,\minTimeCounter_low_reg[0]_i_3_n_6 ,\minTimeCounter_low_reg[0]_i_3_n_7 }), + .S({minTimeCounter_low_reg[3:1],\minTimeCounter_low[0]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[10] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[8]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[10]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[11] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[8]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[11]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[12] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[12]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[12]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[12]_i_1 + (.CI(\minTimeCounter_low_reg[8]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[12]_i_1_n_0 ,\minTimeCounter_low_reg[12]_i_1_n_1 ,\minTimeCounter_low_reg[12]_i_1_n_2 ,\minTimeCounter_low_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[12]_i_1_n_4 ,\minTimeCounter_low_reg[12]_i_1_n_5 ,\minTimeCounter_low_reg[12]_i_1_n_6 ,\minTimeCounter_low_reg[12]_i_1_n_7 }), + .S(minTimeCounter_low_reg[15:12])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[13] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[12]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[13]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[14] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[12]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[14]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[15] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[12]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[15]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[16] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[16]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[16]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[16]_i_1 + (.CI(\minTimeCounter_low_reg[12]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[16]_i_1_n_0 ,\minTimeCounter_low_reg[16]_i_1_n_1 ,\minTimeCounter_low_reg[16]_i_1_n_2 ,\minTimeCounter_low_reg[16]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[16]_i_1_n_4 ,\minTimeCounter_low_reg[16]_i_1_n_5 ,\minTimeCounter_low_reg[16]_i_1_n_6 ,\minTimeCounter_low_reg[16]_i_1_n_7 }), + .S(minTimeCounter_low_reg[19:16])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[17] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[16]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[17]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[18] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[16]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[18]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[19] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[16]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[19]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[1] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[0]_i_3_n_6 ), + .Q(minTimeCounter_low_reg[1]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[20] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[20]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[20]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[20]_i_1 + (.CI(\minTimeCounter_low_reg[16]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[20]_i_1_n_0 ,\minTimeCounter_low_reg[20]_i_1_n_1 ,\minTimeCounter_low_reg[20]_i_1_n_2 ,\minTimeCounter_low_reg[20]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[20]_i_1_n_4 ,\minTimeCounter_low_reg[20]_i_1_n_5 ,\minTimeCounter_low_reg[20]_i_1_n_6 ,\minTimeCounter_low_reg[20]_i_1_n_7 }), + .S(minTimeCounter_low_reg[23:20])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[21] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[20]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[21]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[22] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[20]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[22]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[23] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[20]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[23]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[24] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[24]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[24]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[24]_i_1 + (.CI(\minTimeCounter_low_reg[20]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[24]_i_1_n_0 ,\minTimeCounter_low_reg[24]_i_1_n_1 ,\minTimeCounter_low_reg[24]_i_1_n_2 ,\minTimeCounter_low_reg[24]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[24]_i_1_n_4 ,\minTimeCounter_low_reg[24]_i_1_n_5 ,\minTimeCounter_low_reg[24]_i_1_n_6 ,\minTimeCounter_low_reg[24]_i_1_n_7 }), + .S(minTimeCounter_low_reg[27:24])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[25] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[24]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[25]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[26] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[24]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[26]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[27] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[24]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[27]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[28] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[28]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[28]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[28]_i_1 + (.CI(\minTimeCounter_low_reg[24]_i_1_n_0 ), + .CO({\NLW_minTimeCounter_low_reg[28]_i_1_CO_UNCONNECTED [3],\minTimeCounter_low_reg[28]_i_1_n_1 ,\minTimeCounter_low_reg[28]_i_1_n_2 ,\minTimeCounter_low_reg[28]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[28]_i_1_n_4 ,\minTimeCounter_low_reg[28]_i_1_n_5 ,\minTimeCounter_low_reg[28]_i_1_n_6 ,\minTimeCounter_low_reg[28]_i_1_n_7 }), + .S(minTimeCounter_low_reg[31:28])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[29] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[28]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[29]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[2] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[0]_i_3_n_5 ), + .Q(minTimeCounter_low_reg[2]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[30] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[28]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[30]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[31] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[28]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[31]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[3] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[0]_i_3_n_4 ), + .Q(minTimeCounter_low_reg[3]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[4] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[4]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[4]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[4]_i_1 + (.CI(\minTimeCounter_low_reg[0]_i_3_n_0 ), + .CO({\minTimeCounter_low_reg[4]_i_1_n_0 ,\minTimeCounter_low_reg[4]_i_1_n_1 ,\minTimeCounter_low_reg[4]_i_1_n_2 ,\minTimeCounter_low_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[4]_i_1_n_4 ,\minTimeCounter_low_reg[4]_i_1_n_5 ,\minTimeCounter_low_reg[4]_i_1_n_6 ,\minTimeCounter_low_reg[4]_i_1_n_7 }), + .S(minTimeCounter_low_reg[7:4])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[5] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[4]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[5]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[6] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[4]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[6]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[7] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[4]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[7]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[8] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[8]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[8]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[8]_i_1 + (.CI(\minTimeCounter_low_reg[4]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[8]_i_1_n_0 ,\minTimeCounter_low_reg[8]_i_1_n_1 ,\minTimeCounter_low_reg[8]_i_1_n_2 ,\minTimeCounter_low_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[8]_i_1_n_4 ,\minTimeCounter_low_reg[8]_i_1_n_5 ,\minTimeCounter_low_reg[8]_i_1_n_6 ,\minTimeCounter_low_reg[8]_i_1_n_7 }), + .S(minTimeCounter_low_reg[11:8])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[9] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[8]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[9]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'hEEFFEEEEE200E2E2)) + minTimeEr_i_1 + (.I0(minTimeEr_i_2_n_0), + .I1(minTimeEr_i_3_n_0), + .I2(minTimeEr_i_4_n_0), + .I3(minTimeEr_i_5_n_0), + .I4(minTimeEr_i_6_n_0), + .I5(minTimeEr_reg_0), + .O(minTimeEr_i_1_n_0)); + LUT4 #( + .INIT(16'h0111)) + minTimeEr_i_2 + (.I0(reset), + .I1(breaking_en), + .I2(minTimeEr_i_6_n_0), + .I3(minTimeEr_i_7_n_0), + .O(minTimeEr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h2)) + minTimeEr_i_3 + (.I0(breaking_en), + .I1(reset), + .O(minTimeEr_i_3_n_0)); + LUT6 #( + .INIT(64'h040404FF00000000)) + minTimeEr_i_4 + (.I0(minTimeOK_low), + .I1(key2_reg_n_0), + .I2(key2_prev), + .I3(minTimeEr_i_8_n_0), + .I4(minTimeOK_high), + .I5(minTime_En), + .O(minTimeEr_i_4_n_0)); + LUT6 #( + .INIT(64'h55555555F755F7F7)) + minTimeEr_i_5 + (.I0(minTimeEr_i_9_n_0), + .I1(key2_prev), + .I2(key2_reg_n_0), + .I3(key1_reg_n_0), + .I4(key1_prev), + .I5(minTimeEr_i_7_n_0), + .O(minTimeEr_i_5_n_0)); + LUT6 #( + .INIT(64'hFBFFFFFFBBFBFBFF)) + minTimeEr_i_6 + (.I0(minTimeOK_low), + .I1(minTime_En), + .I2(key3_prev), + .I3(key3_reg_n_0), + .I4(key4_reg_n_0), + .I5(key4_prev), + .O(minTimeEr_i_6_n_0)); + LUT6 #( + .INIT(64'hFFDFDDDDFFDFFFDF)) + minTimeEr_i_7 + (.I0(minTime_En), + .I1(minTimeOK_high), + .I2(key2_reg_n_0), + .I3(key2_prev), + .I4(key1_prev), + .I5(key1_reg_n_0), + .O(minTimeEr_i_7_n_0)); + LUT2 #( + .INIT(4'hB)) + minTimeEr_i_8 + (.I0(key1_prev), + .I1(key1_reg_n_0), + .O(minTimeEr_i_8_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h1)) + minTimeEr_i_9 + (.I0(breaking_en), + .I1(reset), + .O(minTimeEr_i_9_n_0)); + FDRE #( + .INIT(1'b0)) + minTimeEr_reg + (.C(externalCLK), + .CE(1'b1), + .D(minTimeEr_i_1_n_0), + .Q(minTimeEr_reg_0), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h00AB)) + minTimeOK_high_i_1 + (.I0(minTimeOK_high), + .I1(ltOp__31_carry__2_n_0), + .I2(reset), + .I3(\minTimeCounter_high[0]_i_1_n_0 ), + .O(minTimeOK_high_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + minTimeOK_high_reg + (.C(externalCLK), + .CE(1'b1), + .D(minTimeOK_high_i_1_n_0), + .Q(minTimeOK_high), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'h00AB)) + minTimeOK_low_i_1 + (.I0(minTimeOK_low), + .I1(ltOp__15_carry__2_n_0), + .I2(reset), + .I3(\minTimeCounter_low[0]_i_1_n_0 ), + .O(minTimeOK_low_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + minTimeOK_low_reg + (.C(externalCLK), + .CE(1'b1), + .D(minTimeOK_low_i_1_n_0), + .Q(minTimeOK_low), + .R(1'b0)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2_sim_netlist.vhdl b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2_sim_netlist.vhdl new file mode 100644 index 0000000..9a26cee --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2_sim_netlist.vhdl @@ -0,0 +1,4183 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Fri Jun 11 07:49:57 2021 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top Inverter_3lvl_P0N_3lvl_0_2 -prefix +-- Inverter_3lvl_P0N_3lvl_0_2_ Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.vhdl +-- Design : Inverter_3lvl_P0N_3lvl_0_4 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Inverter_3lvl_P0N_3lvl_0_2_P0N_3lvl is + port ( + minTimeEr_reg_0 : out STD_LOGIC; + PWM_out_0 : out STD_LOGIC; + PWM_out_1 : out STD_LOGIC; + PWM_out_2 : out STD_LOGIC; + PWM_out_3 : out STD_LOGIC; + reset : in STD_LOGIC; + externalCLK : in STD_LOGIC; + TKin0 : in STD_LOGIC; + TKin1 : in STD_LOGIC; + breaking_en : in STD_LOGIC; + er : in STD_LOGIC; + ready : in STD_LOGIC; + minTime_En : in STD_LOGIC; + deadTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + minTime : in STD_LOGIC_VECTOR ( 31 downto 0 ) + ); +end Inverter_3lvl_P0N_3lvl_0_2_P0N_3lvl; + +architecture STRUCTURE of Inverter_3lvl_P0N_3lvl_0_2_P0N_3lvl is + signal \FSM_onehot_lineconfig[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[0]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[1]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[2]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[2]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[3]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[4]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[5]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[5]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[5]_i_3_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_3_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_4_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_5_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_6_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[0]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[1]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[2]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[3]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[4]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[5]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[6]\ : STD_LOGIC; + signal PWM_out_0_i_1_n_0 : STD_LOGIC; + signal PWM_out_1_i_1_n_0 : STD_LOGIC; + signal PWM_out_2_i_1_n_0 : STD_LOGIC; + signal PWM_out_3_i_1_n_0 : STD_LOGIC; + signal TKin0_triggered : STD_LOGIC; + signal TKin0_triggered28_out : STD_LOGIC; + signal TKin0_triggered_i_1_n_0 : STD_LOGIC; + signal TKin1_triggered : STD_LOGIC; + signal TKin1_triggered_i_1_n_0 : STD_LOGIC; + signal \TimeCounter[0]_i_2_n_0\ : STD_LOGIC; + signal TimeCounter_reg : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \TimeCounter_reg[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_7\ : STD_LOGIC; + signal deadTimeCounterReset_i_1_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_2_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_3_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_4_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_5_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_6_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_7_n_0 : STD_LOGIC; + signal deadTimeCounterReset_reg_n_0 : STD_LOGIC; + signal deadTimeOK : STD_LOGIC; + signal deadTimeOK_i_1_n_0 : STD_LOGIC; + signal key1_i_1_n_0 : STD_LOGIC; + signal key1_i_2_n_0 : STD_LOGIC; + signal key1_prev : STD_LOGIC; + signal key1_reg_n_0 : STD_LOGIC; + signal key2_i_2_n_0 : STD_LOGIC; + signal key2_prev : STD_LOGIC; + signal key2_reg_n_0 : STD_LOGIC; + signal key3 : STD_LOGIC; + signal key3_i_1_n_0 : STD_LOGIC; + signal key3_prev : STD_LOGIC; + signal key3_reg_n_0 : STD_LOGIC; + signal key4_i_1_n_0 : STD_LOGIC; + signal key4_prev : STD_LOGIC; + signal key4_reg_n_0 : STD_LOGIC; + signal \ltOp__15_carry__0_i_1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_3_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_4_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_5_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_6_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_7_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_8_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_n_1\ : STD_LOGIC; + signal \ltOp__15_carry__0_n_2\ : STD_LOGIC; + signal \ltOp__15_carry__0_n_3\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_3_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_4_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_5_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_6_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_7_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_8_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_n_1\ : STD_LOGIC; + signal \ltOp__15_carry__1_n_2\ : STD_LOGIC; + signal \ltOp__15_carry__1_n_3\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_3_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_4_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_5_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_6_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_7_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_8_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_n_1\ : STD_LOGIC; + signal \ltOp__15_carry__2_n_2\ : STD_LOGIC; + signal \ltOp__15_carry__2_n_3\ : STD_LOGIC; + signal \ltOp__15_carry_i_1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_3_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_4_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_5_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_6_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_7_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_8_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_n_1\ : STD_LOGIC; + signal \ltOp__15_carry_n_2\ : STD_LOGIC; + signal \ltOp__15_carry_n_3\ : STD_LOGIC; + signal \ltOp__31_carry__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry__0_n_1\ : STD_LOGIC; + signal \ltOp__31_carry__0_n_2\ : STD_LOGIC; + signal \ltOp__31_carry__0_n_3\ : STD_LOGIC; + signal \ltOp__31_carry__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry__1_n_1\ : STD_LOGIC; + signal \ltOp__31_carry__1_n_2\ : STD_LOGIC; + signal \ltOp__31_carry__1_n_3\ : STD_LOGIC; + signal \ltOp__31_carry__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry__2_n_1\ : STD_LOGIC; + signal \ltOp__31_carry__2_n_2\ : STD_LOGIC; + signal \ltOp__31_carry__2_n_3\ : STD_LOGIC; + signal \ltOp__31_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_1__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_2__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_3__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_3_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_4__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_4_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_5__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_5_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_6__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_6_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_7__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_7_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_8__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_8_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_n_1\ : STD_LOGIC; + signal \ltOp__31_carry_n_2\ : STD_LOGIC; + signal \ltOp__31_carry_n_3\ : STD_LOGIC; + signal \ltOp_carry__0_i_1_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_2_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_3_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_4_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_5_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_6_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_7_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_8_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_i_1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_2_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_3_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_4_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_5_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_6_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_7_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_8_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_i_1_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_2_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_3_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_4_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_5_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_6_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_7_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_8_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal minTimeCounter_high : STD_LOGIC; + signal \minTimeCounter_high[0]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high[0]_i_4_n_0\ : STD_LOGIC; + signal minTimeCounter_high_reg : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \minTimeCounter_high_reg[0]_i_3_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_7\ : STD_LOGIC; + signal minTimeCounter_low : STD_LOGIC; + signal \minTimeCounter_low[0]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low[0]_i_4_n_0\ : STD_LOGIC; + signal \minTimeCounter_low[0]_i_5_n_0\ : STD_LOGIC; + signal minTimeCounter_low_reg : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \minTimeCounter_low_reg[0]_i_3_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_7\ : STD_LOGIC; + signal minTimeEr_i_1_n_0 : STD_LOGIC; + signal minTimeEr_i_2_n_0 : STD_LOGIC; + signal minTimeEr_i_3_n_0 : STD_LOGIC; + signal minTimeEr_i_4_n_0 : STD_LOGIC; + signal minTimeEr_i_5_n_0 : STD_LOGIC; + signal minTimeEr_i_6_n_0 : STD_LOGIC; + signal minTimeEr_i_7_n_0 : STD_LOGIC; + signal minTimeEr_i_8_n_0 : STD_LOGIC; + signal minTimeEr_i_9_n_0 : STD_LOGIC; + signal \^mintimeer_reg_0\ : STD_LOGIC; + signal minTimeOK_high : STD_LOGIC; + signal minTimeOK_high_i_1_n_0 : STD_LOGIC; + signal minTimeOK_low : STD_LOGIC; + signal minTimeOK_low_i_1_n_0 : STD_LOGIC; + signal p_0_in : STD_LOGIC; + signal sel : STD_LOGIC; + signal \NLW_TimeCounter_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_ltOp__15_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__15_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__15_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__15_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__31_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__31_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__31_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__31_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_minTimeCounter_high_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_minTimeCounter_low_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[0]_i_2\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[2]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[5]_i_2\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[6]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[6]_i_3\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[6]_i_6\ : label is "soft_lutpair2"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[0]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[1]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[2]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[3]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[4]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[5]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[6]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute SOFT_HLUTNM of PWM_out_0_i_1 : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of PWM_out_1_i_1 : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of deadTimeCounterReset_i_2 : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of deadTimeCounterReset_i_5 : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of deadTimeCounterReset_i_6 : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of deadTimeOK_i_1 : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of key1_i_2 : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of minTimeEr_i_3 : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of minTimeEr_i_9 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of minTimeOK_high_i_1 : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of minTimeOK_low_i_1 : label is "soft_lutpair3"; +begin + minTimeEr_reg_0 <= \^mintimeer_reg_0\; +\FSM_onehot_lineconfig[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFE00000000" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I4 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I5 => \FSM_onehot_lineconfig[0]_i_2_n_0\, + O => \FSM_onehot_lineconfig[0]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[0]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => TKin1, + I1 => TKin0, + O => \FSM_onehot_lineconfig[0]_i_2_n_0\ + ); +\FSM_onehot_lineconfig[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1000FFFF00000000" + ) + port map ( + I0 => TKin1, + I1 => TKin1_triggered, + I2 => TKin0_triggered, + I3 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I4 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I5 => TKin0, + O => \FSM_onehot_lineconfig[1]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00EFEF0F" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I2 => \FSM_onehot_lineconfig[2]_i_2_n_0\, + I3 => TKin0, + I4 => TKin1, + O => \FSM_onehot_lineconfig[2]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"900990099009FFFF" + ) + port map ( + I0 => TKin1, + I1 => TKin1_triggered, + I2 => TKin0, + I3 => TKin0_triggered, + I4 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I5 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + O => \FSM_onehot_lineconfig[2]_i_2_n_0\ + ); +\FSM_onehot_lineconfig[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000055D50000" + ) + port map ( + I0 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I2 => TKin1_triggered, + I3 => TKin0_triggered, + I4 => TKin1, + I5 => TKin0, + O => \FSM_onehot_lineconfig[3]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2230" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I1 => TKin0, + I2 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I3 => TKin1, + O => \FSM_onehot_lineconfig[4]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0CFF0C0D00050005" + ) + port map ( + I0 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I2 => TKin1, + I3 => TKin0, + I4 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I5 => \FSM_onehot_lineconfig[5]_i_3_n_0\, + O => \FSM_onehot_lineconfig[5]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[5]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + O => \FSM_onehot_lineconfig[5]_i_2_n_0\ + ); +\FSM_onehot_lineconfig[5]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TKin0_triggered, + I1 => TKin0, + I2 => TKin1_triggered, + I3 => TKin1, + O => \FSM_onehot_lineconfig[5]_i_3_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => \FSM_onehot_lineconfig[6]_i_3_n_0\, + I1 => \FSM_onehot_lineconfig[6]_i_4_n_0\, + I2 => breaking_en, + O => \FSM_onehot_lineconfig[6]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"5504" + ) + port map ( + I0 => TKin1, + I1 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I2 => TKin0, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + O => \FSM_onehot_lineconfig[6]_i_2_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFEECAE" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I2 => TKin1, + I3 => TKin0, + I4 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + O => \FSM_onehot_lineconfig[6]_i_3_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AABAAAAAFFFFAAAA" + ) + port map ( + I0 => \FSM_onehot_lineconfig[6]_i_5_n_0\, + I1 => er, + I2 => ready, + I3 => \FSM_onehot_lineconfig[6]_i_6_n_0\, + I4 => deadTimeOK, + I5 => \FSM_onehot_lineconfig[2]_i_2_n_0\, + O => \FSM_onehot_lineconfig[6]_i_4_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FC88A0A8" + ) + port map ( + I0 => deadTimeOK, + I1 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I3 => TKin1, + I4 => TKin0, + O => \FSM_onehot_lineconfig[6]_i_5_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF232323" + ) + port map ( + I0 => deadTimeCounterReset_reg_n_0, + I1 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I3 => TKin1, + I4 => TKin0, + O => \FSM_onehot_lineconfig[6]_i_6_n_0\ + ); +\FSM_onehot_lineconfig_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[0]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[0]\, + S => reset + ); +\FSM_onehot_lineconfig_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[1]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[1]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[2]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[2]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[3]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[3]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[4]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[4]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[5]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[5]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[6]_i_2_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[6]\, + R => reset + ); +PWM_out_0_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFEF" + ) + port map ( + I0 => key1_reg_n_0, + I1 => er, + I2 => ready, + I3 => \^mintimeer_reg_0\, + O => PWM_out_0_i_1_n_0 + ); +PWM_out_0_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => PWM_out_0_i_1_n_0, + Q => PWM_out_0, + R => '0' + ); +PWM_out_1_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFEF" + ) + port map ( + I0 => key2_reg_n_0, + I1 => er, + I2 => ready, + I3 => \^mintimeer_reg_0\, + O => PWM_out_1_i_1_n_0 + ); +PWM_out_1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => PWM_out_1_i_1_n_0, + Q => PWM_out_1, + R => '0' + ); +PWM_out_2_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFEF" + ) + port map ( + I0 => key3_reg_n_0, + I1 => \^mintimeer_reg_0\, + I2 => ready, + I3 => er, + I4 => breaking_en, + O => PWM_out_2_i_1_n_0 + ); +PWM_out_2_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => PWM_out_2_i_1_n_0, + Q => PWM_out_2, + R => '0' + ); +PWM_out_3_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFEF" + ) + port map ( + I0 => key4_reg_n_0, + I1 => \^mintimeer_reg_0\, + I2 => ready, + I3 => er, + I4 => breaking_en, + O => PWM_out_3_i_1_n_0 + ); +PWM_out_3_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => PWM_out_3_i_1_n_0, + Q => PWM_out_3, + R => '0' + ); +TKin0_triggered_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA08FFFFAA080000" + ) + port map ( + I0 => TKin0, + I1 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I2 => TKin1, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I4 => TKin0_triggered28_out, + I5 => TKin0_triggered, + O => TKin0_triggered_i_1_n_0 + ); +TKin0_triggered_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => TKin0_triggered_i_1_n_0, + Q => TKin0_triggered, + R => '0' + ); +TKin1_triggered_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA08FFFFAA080000" + ) + port map ( + I0 => TKin1, + I1 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I2 => TKin0, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I4 => TKin0_triggered28_out, + I5 => TKin1_triggered, + O => TKin1_triggered_i_1_n_0 + ); +TKin1_triggered_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"22AA22A820AA2020" + ) + port map ( + I0 => minTimeEr_i_9_n_0, + I1 => TKin1, + I2 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I3 => TKin0, + I4 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I5 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + O => TKin0_triggered28_out + ); +TKin1_triggered_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => TKin1_triggered_i_1_n_0, + Q => TKin1_triggered, + R => '0' + ); +\TimeCounter[0]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => TimeCounter_reg(0), + O => \TimeCounter[0]_i_2_n_0\ + ); +\TimeCounter_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[0]_i_1_n_7\, + Q => TimeCounter_reg(0), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[0]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \TimeCounter_reg[0]_i_1_n_0\, + CO(2) => \TimeCounter_reg[0]_i_1_n_1\, + CO(1) => \TimeCounter_reg[0]_i_1_n_2\, + CO(0) => \TimeCounter_reg[0]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \TimeCounter_reg[0]_i_1_n_4\, + O(2) => \TimeCounter_reg[0]_i_1_n_5\, + O(1) => \TimeCounter_reg[0]_i_1_n_6\, + O(0) => \TimeCounter_reg[0]_i_1_n_7\, + S(3 downto 1) => TimeCounter_reg(3 downto 1), + S(0) => \TimeCounter[0]_i_2_n_0\ + ); +\TimeCounter_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[8]_i_1_n_5\, + Q => TimeCounter_reg(10), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[8]_i_1_n_4\, + Q => TimeCounter_reg(11), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[12]_i_1_n_7\, + Q => TimeCounter_reg(12), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[8]_i_1_n_0\, + CO(3) => \TimeCounter_reg[12]_i_1_n_0\, + CO(2) => \TimeCounter_reg[12]_i_1_n_1\, + CO(1) => \TimeCounter_reg[12]_i_1_n_2\, + CO(0) => \TimeCounter_reg[12]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[12]_i_1_n_4\, + O(2) => \TimeCounter_reg[12]_i_1_n_5\, + O(1) => \TimeCounter_reg[12]_i_1_n_6\, + O(0) => \TimeCounter_reg[12]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(15 downto 12) + ); +\TimeCounter_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[12]_i_1_n_6\, + Q => TimeCounter_reg(13), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[12]_i_1_n_5\, + Q => TimeCounter_reg(14), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[12]_i_1_n_4\, + Q => TimeCounter_reg(15), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[16]_i_1_n_7\, + Q => TimeCounter_reg(16), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[16]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[12]_i_1_n_0\, + CO(3) => \TimeCounter_reg[16]_i_1_n_0\, + CO(2) => \TimeCounter_reg[16]_i_1_n_1\, + CO(1) => \TimeCounter_reg[16]_i_1_n_2\, + CO(0) => \TimeCounter_reg[16]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[16]_i_1_n_4\, + O(2) => \TimeCounter_reg[16]_i_1_n_5\, + O(1) => \TimeCounter_reg[16]_i_1_n_6\, + O(0) => \TimeCounter_reg[16]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(19 downto 16) + ); +\TimeCounter_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[16]_i_1_n_6\, + Q => TimeCounter_reg(17), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[16]_i_1_n_5\, + Q => TimeCounter_reg(18), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[16]_i_1_n_4\, + Q => TimeCounter_reg(19), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[0]_i_1_n_6\, + Q => TimeCounter_reg(1), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[20]_i_1_n_7\, + Q => TimeCounter_reg(20), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[20]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[16]_i_1_n_0\, + CO(3) => \TimeCounter_reg[20]_i_1_n_0\, + CO(2) => \TimeCounter_reg[20]_i_1_n_1\, + CO(1) => \TimeCounter_reg[20]_i_1_n_2\, + CO(0) => \TimeCounter_reg[20]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[20]_i_1_n_4\, + O(2) => \TimeCounter_reg[20]_i_1_n_5\, + O(1) => \TimeCounter_reg[20]_i_1_n_6\, + O(0) => \TimeCounter_reg[20]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(23 downto 20) + ); +\TimeCounter_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[20]_i_1_n_6\, + Q => TimeCounter_reg(21), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[20]_i_1_n_5\, + Q => TimeCounter_reg(22), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[20]_i_1_n_4\, + Q => TimeCounter_reg(23), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[24]_i_1_n_7\, + Q => TimeCounter_reg(24), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[24]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[20]_i_1_n_0\, + CO(3) => \TimeCounter_reg[24]_i_1_n_0\, + CO(2) => \TimeCounter_reg[24]_i_1_n_1\, + CO(1) => \TimeCounter_reg[24]_i_1_n_2\, + CO(0) => \TimeCounter_reg[24]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[24]_i_1_n_4\, + O(2) => \TimeCounter_reg[24]_i_1_n_5\, + O(1) => \TimeCounter_reg[24]_i_1_n_6\, + O(0) => \TimeCounter_reg[24]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(27 downto 24) + ); +\TimeCounter_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[24]_i_1_n_6\, + Q => TimeCounter_reg(25), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[24]_i_1_n_5\, + Q => TimeCounter_reg(26), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[24]_i_1_n_4\, + Q => TimeCounter_reg(27), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[28]_i_1_n_7\, + Q => TimeCounter_reg(28), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[28]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[24]_i_1_n_0\, + CO(3) => \NLW_TimeCounter_reg[28]_i_1_CO_UNCONNECTED\(3), + CO(2) => \TimeCounter_reg[28]_i_1_n_1\, + CO(1) => \TimeCounter_reg[28]_i_1_n_2\, + CO(0) => \TimeCounter_reg[28]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[28]_i_1_n_4\, + O(2) => \TimeCounter_reg[28]_i_1_n_5\, + O(1) => \TimeCounter_reg[28]_i_1_n_6\, + O(0) => \TimeCounter_reg[28]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(31 downto 28) + ); +\TimeCounter_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[28]_i_1_n_6\, + Q => TimeCounter_reg(29), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[0]_i_1_n_5\, + Q => TimeCounter_reg(2), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[28]_i_1_n_5\, + Q => TimeCounter_reg(30), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[28]_i_1_n_4\, + Q => TimeCounter_reg(31), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[0]_i_1_n_4\, + Q => TimeCounter_reg(3), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[4]_i_1_n_7\, + Q => TimeCounter_reg(4), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[0]_i_1_n_0\, + CO(3) => \TimeCounter_reg[4]_i_1_n_0\, + CO(2) => \TimeCounter_reg[4]_i_1_n_1\, + CO(1) => \TimeCounter_reg[4]_i_1_n_2\, + CO(0) => \TimeCounter_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[4]_i_1_n_4\, + O(2) => \TimeCounter_reg[4]_i_1_n_5\, + O(1) => \TimeCounter_reg[4]_i_1_n_6\, + O(0) => \TimeCounter_reg[4]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(7 downto 4) + ); +\TimeCounter_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[4]_i_1_n_6\, + Q => TimeCounter_reg(5), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[4]_i_1_n_5\, + Q => TimeCounter_reg(6), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[4]_i_1_n_4\, + Q => TimeCounter_reg(7), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[8]_i_1_n_7\, + Q => TimeCounter_reg(8), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[4]_i_1_n_0\, + CO(3) => \TimeCounter_reg[8]_i_1_n_0\, + CO(2) => \TimeCounter_reg[8]_i_1_n_1\, + CO(1) => \TimeCounter_reg[8]_i_1_n_2\, + CO(0) => \TimeCounter_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[8]_i_1_n_4\, + O(2) => \TimeCounter_reg[8]_i_1_n_5\, + O(1) => \TimeCounter_reg[8]_i_1_n_6\, + O(0) => \TimeCounter_reg[8]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(11 downto 8) + ); +\TimeCounter_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[8]_i_1_n_6\, + Q => TimeCounter_reg(9), + R => deadTimeCounterReset_reg_n_0 + ); +deadTimeCounterReset_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFE0000000E" + ) + port map ( + I0 => deadTimeCounterReset_i_2_n_0, + I1 => \FSM_onehot_lineconfig[6]_i_4_n_0\, + I2 => reset, + I3 => breaking_en, + I4 => deadTimeCounterReset_i_3_n_0, + I5 => deadTimeCounterReset_reg_n_0, + O => deadTimeCounterReset_i_1_n_0 + ); +deadTimeCounterReset_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + O => deadTimeCounterReset_i_2_n_0 + ); +deadTimeCounterReset_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000022220020" + ) + port map ( + I0 => deadTimeCounterReset_i_4_n_0, + I1 => deadTimeCounterReset_i_2_n_0, + I2 => deadTimeCounterReset_i_5_n_0, + I3 => deadTimeCounterReset_i_6_n_0, + I4 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I5 => deadTimeCounterReset_i_7_n_0, + O => deadTimeCounterReset_i_3_n_0 + ); +deadTimeCounterReset_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"555D555555555555" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I1 => deadTimeOK, + I2 => TKin1, + I3 => TKin1_triggered, + I4 => TKin0, + I5 => TKin0_triggered, + O => deadTimeCounterReset_i_4_n_0 + ); +deadTimeCounterReset_i_5: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => deadTimeOK, + I1 => ready, + I2 => er, + O => deadTimeCounterReset_i_5_n_0 + ); +deadTimeCounterReset_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"F777" + ) + port map ( + I0 => TKin0, + I1 => TKin1, + I2 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I3 => deadTimeCounterReset_reg_n_0, + O => deadTimeCounterReset_i_6_n_0 + ); +deadTimeCounterReset_i_7: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAA2AAAAAAAAAA" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I1 => TKin1, + I2 => TKin0, + I3 => deadTimeOK, + I4 => TKin0_triggered, + I5 => TKin1_triggered, + O => deadTimeCounterReset_i_7_n_0 + ); +deadTimeCounterReset_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => '1', + D => deadTimeCounterReset_i_1_n_0, + Q => deadTimeCounterReset_reg_n_0, + R => '0' + ); +deadTimeOK_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"0D" + ) + port map ( + I0 => sel, + I1 => deadTimeOK, + I2 => deadTimeCounterReset_reg_n_0, + O => deadTimeOK_i_1_n_0 + ); +deadTimeOK_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => deadTimeOK_i_1_n_0, + Q => deadTimeOK, + R => '0' + ); +key1_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"DDDDDDD0DDDDDDDD" + ) + port map ( + I0 => breaking_en, + I1 => TKin0, + I2 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I4 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I5 => key1_i_2_n_0, + O => key1_i_1_n_0 + ); +key1_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I3 => breaking_en, + O => key1_i_2_n_0 + ); +key1_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key1_reg_n_0, + Q => key1_prev, + R => '0' + ); +key1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key1_i_1_n_0, + Q => key1_reg_n_0, + R => '0' + ); +key2_i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => reset, + O => p_0_in + ); +key2_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAFFFFFFFC" + ) + port map ( + I0 => TKin1, + I1 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I4 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I5 => breaking_en, + O => key2_i_2_n_0 + ); +key2_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key2_reg_n_0, + Q => key2_prev, + R => '0' + ); +key2_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key2_i_2_n_0, + Q => key2_reg_n_0, + R => '0' + ); +key3_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAFFFFAAAAFCFF" + ) + port map ( + I0 => key3_reg_n_0, + I1 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I3 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I4 => reset, + I5 => breaking_en, + O => key3_i_1_n_0 + ); +key3_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key3_reg_n_0, + Q => key3_prev, + R => '0' + ); +key3_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => key3_i_1_n_0, + Q => key3_reg_n_0, + R => '0' + ); +key4_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAFFFFAAAAFFFC" + ) + port map ( + I0 => key4_reg_n_0, + I1 => key3, + I2 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I4 => reset, + I5 => breaking_en, + O => key4_i_1_n_0 + ); +key4_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + O => key3 + ); +key4_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key4_reg_n_0, + Q => key4_prev, + R => '0' + ); +key4_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => key4_i_1_n_0, + Q => key4_reg_n_0, + R => '0' + ); +\ltOp__15_carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \ltOp__15_carry_n_0\, + CO(2) => \ltOp__15_carry_n_1\, + CO(1) => \ltOp__15_carry_n_2\, + CO(0) => \ltOp__15_carry_n_3\, + CYINIT => '0', + DI(3) => \ltOp__15_carry_i_1_n_0\, + DI(2) => \ltOp__15_carry_i_2_n_0\, + DI(1) => \ltOp__15_carry_i_3_n_0\, + DI(0) => \ltOp__15_carry_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__15_carry_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__15_carry_i_5_n_0\, + S(2) => \ltOp__15_carry_i_6_n_0\, + S(1) => \ltOp__15_carry_i_7_n_0\, + S(0) => \ltOp__15_carry_i_8_n_0\ + ); +\ltOp__15_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__15_carry_n_0\, + CO(3) => \ltOp__15_carry__0_n_0\, + CO(2) => \ltOp__15_carry__0_n_1\, + CO(1) => \ltOp__15_carry__0_n_2\, + CO(0) => \ltOp__15_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp__15_carry__0_i_1_n_0\, + DI(2) => \ltOp__15_carry__0_i_2_n_0\, + DI(1) => \ltOp__15_carry__0_i_3_n_0\, + DI(0) => \ltOp__15_carry__0_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__15_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__15_carry__0_i_5_n_0\, + S(2) => \ltOp__15_carry__0_i_6_n_0\, + S(1) => \ltOp__15_carry__0_i_7_n_0\, + S(0) => \ltOp__15_carry__0_i_8_n_0\ + ); +\ltOp__15_carry__0_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(15), + I1 => minTimeCounter_low_reg(15), + I2 => minTime(14), + I3 => minTimeCounter_low_reg(14), + O => \ltOp__15_carry__0_i_1_n_0\ + ); +\ltOp__15_carry__0_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(13), + I1 => minTimeCounter_low_reg(13), + I2 => minTime(12), + I3 => minTimeCounter_low_reg(12), + O => \ltOp__15_carry__0_i_2_n_0\ + ); +\ltOp__15_carry__0_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(11), + I1 => minTimeCounter_low_reg(11), + I2 => minTime(10), + I3 => minTimeCounter_low_reg(10), + O => \ltOp__15_carry__0_i_3_n_0\ + ); +\ltOp__15_carry__0_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(9), + I1 => minTimeCounter_low_reg(9), + I2 => minTime(8), + I3 => minTimeCounter_low_reg(8), + O => \ltOp__15_carry__0_i_4_n_0\ + ); +\ltOp__15_carry__0_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(15), + I1 => minTime(15), + I2 => minTimeCounter_low_reg(14), + I3 => minTime(14), + O => \ltOp__15_carry__0_i_5_n_0\ + ); +\ltOp__15_carry__0_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(13), + I1 => minTime(13), + I2 => minTimeCounter_low_reg(12), + I3 => minTime(12), + O => \ltOp__15_carry__0_i_6_n_0\ + ); +\ltOp__15_carry__0_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(11), + I1 => minTime(11), + I2 => minTimeCounter_low_reg(10), + I3 => minTime(10), + O => \ltOp__15_carry__0_i_7_n_0\ + ); +\ltOp__15_carry__0_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(9), + I1 => minTime(9), + I2 => minTimeCounter_low_reg(8), + I3 => minTime(8), + O => \ltOp__15_carry__0_i_8_n_0\ + ); +\ltOp__15_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__15_carry__0_n_0\, + CO(3) => \ltOp__15_carry__1_n_0\, + CO(2) => \ltOp__15_carry__1_n_1\, + CO(1) => \ltOp__15_carry__1_n_2\, + CO(0) => \ltOp__15_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp__15_carry__1_i_1_n_0\, + DI(2) => \ltOp__15_carry__1_i_2_n_0\, + DI(1) => \ltOp__15_carry__1_i_3_n_0\, + DI(0) => \ltOp__15_carry__1_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__15_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__15_carry__1_i_5_n_0\, + S(2) => \ltOp__15_carry__1_i_6_n_0\, + S(1) => \ltOp__15_carry__1_i_7_n_0\, + S(0) => \ltOp__15_carry__1_i_8_n_0\ + ); +\ltOp__15_carry__1_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(23), + I1 => minTimeCounter_low_reg(23), + I2 => minTime(22), + I3 => minTimeCounter_low_reg(22), + O => \ltOp__15_carry__1_i_1_n_0\ + ); +\ltOp__15_carry__1_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(21), + I1 => minTimeCounter_low_reg(21), + I2 => minTime(20), + I3 => minTimeCounter_low_reg(20), + O => \ltOp__15_carry__1_i_2_n_0\ + ); +\ltOp__15_carry__1_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(19), + I1 => minTimeCounter_low_reg(19), + I2 => minTime(18), + I3 => minTimeCounter_low_reg(18), + O => \ltOp__15_carry__1_i_3_n_0\ + ); +\ltOp__15_carry__1_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(17), + I1 => minTimeCounter_low_reg(17), + I2 => minTime(16), + I3 => minTimeCounter_low_reg(16), + O => \ltOp__15_carry__1_i_4_n_0\ + ); +\ltOp__15_carry__1_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(23), + I1 => minTime(23), + I2 => minTimeCounter_low_reg(22), + I3 => minTime(22), + O => \ltOp__15_carry__1_i_5_n_0\ + ); +\ltOp__15_carry__1_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(21), + I1 => minTime(21), + I2 => minTimeCounter_low_reg(20), + I3 => minTime(20), + O => \ltOp__15_carry__1_i_6_n_0\ + ); +\ltOp__15_carry__1_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(19), + I1 => minTime(19), + I2 => minTimeCounter_low_reg(18), + I3 => minTime(18), + O => \ltOp__15_carry__1_i_7_n_0\ + ); +\ltOp__15_carry__1_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(17), + I1 => minTime(17), + I2 => minTimeCounter_low_reg(16), + I3 => minTime(16), + O => \ltOp__15_carry__1_i_8_n_0\ + ); +\ltOp__15_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__15_carry__1_n_0\, + CO(3) => \ltOp__15_carry__2_n_0\, + CO(2) => \ltOp__15_carry__2_n_1\, + CO(1) => \ltOp__15_carry__2_n_2\, + CO(0) => \ltOp__15_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp__15_carry__2_i_1_n_0\, + DI(2) => \ltOp__15_carry__2_i_2_n_0\, + DI(1) => \ltOp__15_carry__2_i_3_n_0\, + DI(0) => \ltOp__15_carry__2_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__15_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__15_carry__2_i_5_n_0\, + S(2) => \ltOp__15_carry__2_i_6_n_0\, + S(1) => \ltOp__15_carry__2_i_7_n_0\, + S(0) => \ltOp__15_carry__2_i_8_n_0\ + ); +\ltOp__15_carry__2_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(31), + I1 => minTimeCounter_low_reg(31), + I2 => minTime(30), + I3 => minTimeCounter_low_reg(30), + O => \ltOp__15_carry__2_i_1_n_0\ + ); +\ltOp__15_carry__2_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(29), + I1 => minTimeCounter_low_reg(29), + I2 => minTime(28), + I3 => minTimeCounter_low_reg(28), + O => \ltOp__15_carry__2_i_2_n_0\ + ); +\ltOp__15_carry__2_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(27), + I1 => minTimeCounter_low_reg(27), + I2 => minTime(26), + I3 => minTimeCounter_low_reg(26), + O => \ltOp__15_carry__2_i_3_n_0\ + ); +\ltOp__15_carry__2_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(25), + I1 => minTimeCounter_low_reg(25), + I2 => minTime(24), + I3 => minTimeCounter_low_reg(24), + O => \ltOp__15_carry__2_i_4_n_0\ + ); +\ltOp__15_carry__2_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(31), + I1 => minTime(31), + I2 => minTimeCounter_low_reg(30), + I3 => minTime(30), + O => \ltOp__15_carry__2_i_5_n_0\ + ); +\ltOp__15_carry__2_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(29), + I1 => minTime(29), + I2 => minTimeCounter_low_reg(28), + I3 => minTime(28), + O => \ltOp__15_carry__2_i_6_n_0\ + ); +\ltOp__15_carry__2_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(27), + I1 => minTime(27), + I2 => minTimeCounter_low_reg(26), + I3 => minTime(26), + O => \ltOp__15_carry__2_i_7_n_0\ + ); +\ltOp__15_carry__2_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(25), + I1 => minTime(25), + I2 => minTimeCounter_low_reg(24), + I3 => minTime(24), + O => \ltOp__15_carry__2_i_8_n_0\ + ); +\ltOp__15_carry_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(7), + I1 => minTimeCounter_low_reg(7), + I2 => minTime(6), + I3 => minTimeCounter_low_reg(6), + O => \ltOp__15_carry_i_1_n_0\ + ); +\ltOp__15_carry_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(5), + I1 => minTimeCounter_low_reg(5), + I2 => minTime(4), + I3 => minTimeCounter_low_reg(4), + O => \ltOp__15_carry_i_2_n_0\ + ); +\ltOp__15_carry_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(3), + I1 => minTimeCounter_low_reg(3), + I2 => minTime(2), + I3 => minTimeCounter_low_reg(2), + O => \ltOp__15_carry_i_3_n_0\ + ); +\ltOp__15_carry_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(1), + I1 => minTimeCounter_low_reg(1), + I2 => minTime(0), + I3 => minTimeCounter_low_reg(0), + O => \ltOp__15_carry_i_4_n_0\ + ); +\ltOp__15_carry_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(7), + I1 => minTime(7), + I2 => minTimeCounter_low_reg(6), + I3 => minTime(6), + O => \ltOp__15_carry_i_5_n_0\ + ); +\ltOp__15_carry_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(5), + I1 => minTime(5), + I2 => minTimeCounter_low_reg(4), + I3 => minTime(4), + O => \ltOp__15_carry_i_6_n_0\ + ); +\ltOp__15_carry_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(3), + I1 => minTime(3), + I2 => minTimeCounter_low_reg(2), + I3 => minTime(2), + O => \ltOp__15_carry_i_7_n_0\ + ); +\ltOp__15_carry_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(1), + I1 => minTime(1), + I2 => minTimeCounter_low_reg(0), + I3 => minTime(0), + O => \ltOp__15_carry_i_8_n_0\ + ); +\ltOp__31_carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \ltOp__31_carry_n_0\, + CO(2) => \ltOp__31_carry_n_1\, + CO(1) => \ltOp__31_carry_n_2\, + CO(0) => \ltOp__31_carry_n_3\, + CYINIT => '0', + DI(3) => \ltOp__31_carry_i_1_n_0\, + DI(2) => \ltOp__31_carry_i_2_n_0\, + DI(1) => \ltOp__31_carry_i_3_n_0\, + DI(0) => \ltOp__31_carry_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__31_carry_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__31_carry_i_5_n_0\, + S(2) => \ltOp__31_carry_i_6_n_0\, + S(1) => \ltOp__31_carry_i_7_n_0\, + S(0) => \ltOp__31_carry_i_8_n_0\ + ); +\ltOp__31_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__31_carry_n_0\, + CO(3) => \ltOp__31_carry__0_n_0\, + CO(2) => \ltOp__31_carry__0_n_1\, + CO(1) => \ltOp__31_carry__0_n_2\, + CO(0) => \ltOp__31_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp__31_carry_i_1__0_n_0\, + DI(2) => \ltOp__31_carry_i_2__0_n_0\, + DI(1) => \ltOp__31_carry_i_3__0_n_0\, + DI(0) => \ltOp__31_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp__31_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__31_carry_i_5__0_n_0\, + S(2) => \ltOp__31_carry_i_6__0_n_0\, + S(1) => \ltOp__31_carry_i_7__0_n_0\, + S(0) => \ltOp__31_carry_i_8__0_n_0\ + ); +\ltOp__31_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__31_carry__0_n_0\, + CO(3) => \ltOp__31_carry__1_n_0\, + CO(2) => \ltOp__31_carry__1_n_1\, + CO(1) => \ltOp__31_carry__1_n_2\, + CO(0) => \ltOp__31_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp__31_carry_i_1__1_n_0\, + DI(2) => \ltOp__31_carry_i_2__1_n_0\, + DI(1) => \ltOp__31_carry_i_3__1_n_0\, + DI(0) => \ltOp__31_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp__31_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__31_carry_i_5__1_n_0\, + S(2) => \ltOp__31_carry_i_6__1_n_0\, + S(1) => \ltOp__31_carry_i_7__1_n_0\, + S(0) => \ltOp__31_carry_i_8__1_n_0\ + ); +\ltOp__31_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__31_carry__1_n_0\, + CO(3) => \ltOp__31_carry__2_n_0\, + CO(2) => \ltOp__31_carry__2_n_1\, + CO(1) => \ltOp__31_carry__2_n_2\, + CO(0) => \ltOp__31_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp__31_carry_i_1__2_n_0\, + DI(2) => \ltOp__31_carry_i_2__2_n_0\, + DI(1) => \ltOp__31_carry_i_3__2_n_0\, + DI(0) => \ltOp__31_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp__31_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__31_carry_i_5__2_n_0\, + S(2) => \ltOp__31_carry_i_6__2_n_0\, + S(1) => \ltOp__31_carry_i_7__2_n_0\, + S(0) => \ltOp__31_carry_i_8__2_n_0\ + ); +\ltOp__31_carry_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(7), + I1 => minTimeCounter_high_reg(7), + I2 => minTime(6), + I3 => minTimeCounter_high_reg(6), + O => \ltOp__31_carry_i_1_n_0\ + ); +\ltOp__31_carry_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(15), + I1 => minTimeCounter_high_reg(15), + I2 => minTime(14), + I3 => minTimeCounter_high_reg(14), + O => \ltOp__31_carry_i_1__0_n_0\ + ); +\ltOp__31_carry_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(23), + I1 => minTimeCounter_high_reg(23), + I2 => minTime(22), + I3 => minTimeCounter_high_reg(22), + O => \ltOp__31_carry_i_1__1_n_0\ + ); +\ltOp__31_carry_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(31), + I1 => minTimeCounter_high_reg(31), + I2 => minTime(30), + I3 => minTimeCounter_high_reg(30), + O => \ltOp__31_carry_i_1__2_n_0\ + ); +\ltOp__31_carry_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(5), + I1 => minTimeCounter_high_reg(5), + I2 => minTime(4), + I3 => minTimeCounter_high_reg(4), + O => \ltOp__31_carry_i_2_n_0\ + ); +\ltOp__31_carry_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(13), + I1 => minTimeCounter_high_reg(13), + I2 => minTime(12), + I3 => minTimeCounter_high_reg(12), + O => \ltOp__31_carry_i_2__0_n_0\ + ); +\ltOp__31_carry_i_2__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(21), + I1 => minTimeCounter_high_reg(21), + I2 => minTime(20), + I3 => minTimeCounter_high_reg(20), + O => \ltOp__31_carry_i_2__1_n_0\ + ); +\ltOp__31_carry_i_2__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(29), + I1 => minTimeCounter_high_reg(29), + I2 => minTime(28), + I3 => minTimeCounter_high_reg(28), + O => \ltOp__31_carry_i_2__2_n_0\ + ); +\ltOp__31_carry_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(3), + I1 => minTimeCounter_high_reg(3), + I2 => minTime(2), + I3 => minTimeCounter_high_reg(2), + O => \ltOp__31_carry_i_3_n_0\ + ); +\ltOp__31_carry_i_3__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(11), + I1 => minTimeCounter_high_reg(11), + I2 => minTime(10), + I3 => minTimeCounter_high_reg(10), + O => \ltOp__31_carry_i_3__0_n_0\ + ); +\ltOp__31_carry_i_3__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(19), + I1 => minTimeCounter_high_reg(19), + I2 => minTime(18), + I3 => minTimeCounter_high_reg(18), + O => \ltOp__31_carry_i_3__1_n_0\ + ); +\ltOp__31_carry_i_3__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(27), + I1 => minTimeCounter_high_reg(27), + I2 => minTime(26), + I3 => minTimeCounter_high_reg(26), + O => \ltOp__31_carry_i_3__2_n_0\ + ); +\ltOp__31_carry_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(1), + I1 => minTimeCounter_high_reg(1), + I2 => minTime(0), + I3 => minTimeCounter_high_reg(0), + O => \ltOp__31_carry_i_4_n_0\ + ); +\ltOp__31_carry_i_4__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(9), + I1 => minTimeCounter_high_reg(9), + I2 => minTime(8), + I3 => minTimeCounter_high_reg(8), + O => \ltOp__31_carry_i_4__0_n_0\ + ); +\ltOp__31_carry_i_4__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(17), + I1 => minTimeCounter_high_reg(17), + I2 => minTime(16), + I3 => minTimeCounter_high_reg(16), + O => \ltOp__31_carry_i_4__1_n_0\ + ); +\ltOp__31_carry_i_4__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(25), + I1 => minTimeCounter_high_reg(25), + I2 => minTime(24), + I3 => minTimeCounter_high_reg(24), + O => \ltOp__31_carry_i_4__2_n_0\ + ); +\ltOp__31_carry_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(7), + I1 => minTime(7), + I2 => minTimeCounter_high_reg(6), + I3 => minTime(6), + O => \ltOp__31_carry_i_5_n_0\ + ); +\ltOp__31_carry_i_5__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(15), + I1 => minTime(15), + I2 => minTimeCounter_high_reg(14), + I3 => minTime(14), + O => \ltOp__31_carry_i_5__0_n_0\ + ); +\ltOp__31_carry_i_5__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(23), + I1 => minTime(23), + I2 => minTimeCounter_high_reg(22), + I3 => minTime(22), + O => \ltOp__31_carry_i_5__1_n_0\ + ); +\ltOp__31_carry_i_5__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(31), + I1 => minTime(31), + I2 => minTimeCounter_high_reg(30), + I3 => minTime(30), + O => \ltOp__31_carry_i_5__2_n_0\ + ); +\ltOp__31_carry_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(5), + I1 => minTime(5), + I2 => minTimeCounter_high_reg(4), + I3 => minTime(4), + O => \ltOp__31_carry_i_6_n_0\ + ); +\ltOp__31_carry_i_6__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(13), + I1 => minTime(13), + I2 => minTimeCounter_high_reg(12), + I3 => minTime(12), + O => \ltOp__31_carry_i_6__0_n_0\ + ); +\ltOp__31_carry_i_6__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(21), + I1 => minTime(21), + I2 => minTimeCounter_high_reg(20), + I3 => minTime(20), + O => \ltOp__31_carry_i_6__1_n_0\ + ); +\ltOp__31_carry_i_6__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(29), + I1 => minTime(29), + I2 => minTimeCounter_high_reg(28), + I3 => minTime(28), + O => \ltOp__31_carry_i_6__2_n_0\ + ); +\ltOp__31_carry_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(3), + I1 => minTime(3), + I2 => minTimeCounter_high_reg(2), + I3 => minTime(2), + O => \ltOp__31_carry_i_7_n_0\ + ); +\ltOp__31_carry_i_7__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(11), + I1 => minTime(11), + I2 => minTimeCounter_high_reg(10), + I3 => minTime(10), + O => \ltOp__31_carry_i_7__0_n_0\ + ); +\ltOp__31_carry_i_7__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(19), + I1 => minTime(19), + I2 => minTimeCounter_high_reg(18), + I3 => minTime(18), + O => \ltOp__31_carry_i_7__1_n_0\ + ); +\ltOp__31_carry_i_7__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(27), + I1 => minTime(27), + I2 => minTimeCounter_high_reg(26), + I3 => minTime(26), + O => \ltOp__31_carry_i_7__2_n_0\ + ); +\ltOp__31_carry_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(1), + I1 => minTime(1), + I2 => minTimeCounter_high_reg(0), + I3 => minTime(0), + O => \ltOp__31_carry_i_8_n_0\ + ); +\ltOp__31_carry_i_8__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(9), + I1 => minTime(9), + I2 => minTimeCounter_high_reg(8), + I3 => minTime(8), + O => \ltOp__31_carry_i_8__0_n_0\ + ); +\ltOp__31_carry_i_8__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(17), + I1 => minTime(17), + I2 => minTimeCounter_high_reg(16), + I3 => minTime(16), + O => \ltOp__31_carry_i_8__1_n_0\ + ); +\ltOp__31_carry_i_8__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(25), + I1 => minTime(25), + I2 => minTimeCounter_high_reg(24), + I3 => minTime(24), + O => \ltOp__31_carry_i_8__2_n_0\ + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry__0_i_1_n_0\, + DI(2) => \ltOp_carry__0_i_2_n_0\, + DI(1) => \ltOp_carry__0_i_3_n_0\, + DI(0) => \ltOp_carry__0_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry__0_i_5_n_0\, + S(2) => \ltOp_carry__0_i_6_n_0\, + S(1) => \ltOp_carry__0_i_7_n_0\, + S(0) => \ltOp_carry__0_i_8_n_0\ + ); +\ltOp_carry__0_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(15), + I1 => TimeCounter_reg(15), + I2 => deadTime(14), + I3 => TimeCounter_reg(14), + O => \ltOp_carry__0_i_1_n_0\ + ); +\ltOp_carry__0_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(13), + I1 => TimeCounter_reg(13), + I2 => deadTime(12), + I3 => TimeCounter_reg(12), + O => \ltOp_carry__0_i_2_n_0\ + ); +\ltOp_carry__0_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(11), + I1 => TimeCounter_reg(11), + I2 => deadTime(10), + I3 => TimeCounter_reg(10), + O => \ltOp_carry__0_i_3_n_0\ + ); +\ltOp_carry__0_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(9), + I1 => TimeCounter_reg(9), + I2 => deadTime(8), + I3 => TimeCounter_reg(8), + O => \ltOp_carry__0_i_4_n_0\ + ); +\ltOp_carry__0_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(15), + I1 => deadTime(15), + I2 => TimeCounter_reg(14), + I3 => deadTime(14), + O => \ltOp_carry__0_i_5_n_0\ + ); +\ltOp_carry__0_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(13), + I1 => deadTime(13), + I2 => TimeCounter_reg(12), + I3 => deadTime(12), + O => \ltOp_carry__0_i_6_n_0\ + ); +\ltOp_carry__0_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(11), + I1 => deadTime(11), + I2 => TimeCounter_reg(10), + I3 => deadTime(10), + O => \ltOp_carry__0_i_7_n_0\ + ); +\ltOp_carry__0_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(9), + I1 => deadTime(9), + I2 => TimeCounter_reg(8), + I3 => deadTime(8), + O => \ltOp_carry__0_i_8_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry__1_i_1_n_0\, + DI(2) => \ltOp_carry__1_i_2_n_0\, + DI(1) => \ltOp_carry__1_i_3_n_0\, + DI(0) => \ltOp_carry__1_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry__1_i_5_n_0\, + S(2) => \ltOp_carry__1_i_6_n_0\, + S(1) => \ltOp_carry__1_i_7_n_0\, + S(0) => \ltOp_carry__1_i_8_n_0\ + ); +\ltOp_carry__1_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(23), + I1 => TimeCounter_reg(23), + I2 => deadTime(22), + I3 => TimeCounter_reg(22), + O => \ltOp_carry__1_i_1_n_0\ + ); +\ltOp_carry__1_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(21), + I1 => TimeCounter_reg(21), + I2 => deadTime(20), + I3 => TimeCounter_reg(20), + O => \ltOp_carry__1_i_2_n_0\ + ); +\ltOp_carry__1_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(19), + I1 => TimeCounter_reg(19), + I2 => deadTime(18), + I3 => TimeCounter_reg(18), + O => \ltOp_carry__1_i_3_n_0\ + ); +\ltOp_carry__1_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(17), + I1 => TimeCounter_reg(17), + I2 => deadTime(16), + I3 => TimeCounter_reg(16), + O => \ltOp_carry__1_i_4_n_0\ + ); +\ltOp_carry__1_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(23), + I1 => deadTime(23), + I2 => TimeCounter_reg(22), + I3 => deadTime(22), + O => \ltOp_carry__1_i_5_n_0\ + ); +\ltOp_carry__1_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(21), + I1 => deadTime(21), + I2 => TimeCounter_reg(20), + I3 => deadTime(20), + O => \ltOp_carry__1_i_6_n_0\ + ); +\ltOp_carry__1_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(19), + I1 => deadTime(19), + I2 => TimeCounter_reg(18), + I3 => deadTime(18), + O => \ltOp_carry__1_i_7_n_0\ + ); +\ltOp_carry__1_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(17), + I1 => deadTime(17), + I2 => TimeCounter_reg(16), + I3 => deadTime(16), + O => \ltOp_carry__1_i_8_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => sel, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry__2_i_1_n_0\, + DI(2) => \ltOp_carry__2_i_2_n_0\, + DI(1) => \ltOp_carry__2_i_3_n_0\, + DI(0) => \ltOp_carry__2_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry__2_i_5_n_0\, + S(2) => \ltOp_carry__2_i_6_n_0\, + S(1) => \ltOp_carry__2_i_7_n_0\, + S(0) => \ltOp_carry__2_i_8_n_0\ + ); +\ltOp_carry__2_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(31), + I1 => TimeCounter_reg(31), + I2 => deadTime(30), + I3 => TimeCounter_reg(30), + O => \ltOp_carry__2_i_1_n_0\ + ); +\ltOp_carry__2_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(29), + I1 => TimeCounter_reg(29), + I2 => deadTime(28), + I3 => TimeCounter_reg(28), + O => \ltOp_carry__2_i_2_n_0\ + ); +\ltOp_carry__2_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(27), + I1 => TimeCounter_reg(27), + I2 => deadTime(26), + I3 => TimeCounter_reg(26), + O => \ltOp_carry__2_i_3_n_0\ + ); +\ltOp_carry__2_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(25), + I1 => TimeCounter_reg(25), + I2 => deadTime(24), + I3 => TimeCounter_reg(24), + O => \ltOp_carry__2_i_4_n_0\ + ); +\ltOp_carry__2_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(31), + I1 => deadTime(31), + I2 => TimeCounter_reg(30), + I3 => deadTime(30), + O => \ltOp_carry__2_i_5_n_0\ + ); +\ltOp_carry__2_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(29), + I1 => deadTime(29), + I2 => TimeCounter_reg(28), + I3 => deadTime(28), + O => \ltOp_carry__2_i_6_n_0\ + ); +\ltOp_carry__2_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(27), + I1 => deadTime(27), + I2 => TimeCounter_reg(26), + I3 => deadTime(26), + O => \ltOp_carry__2_i_7_n_0\ + ); +\ltOp_carry__2_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(25), + I1 => deadTime(25), + I2 => TimeCounter_reg(24), + I3 => deadTime(24), + O => \ltOp_carry__2_i_8_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(7), + I1 => TimeCounter_reg(7), + I2 => deadTime(6), + I3 => TimeCounter_reg(6), + O => ltOp_carry_i_1_n_0 + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(5), + I1 => TimeCounter_reg(5), + I2 => deadTime(4), + I3 => TimeCounter_reg(4), + O => ltOp_carry_i_2_n_0 + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(3), + I1 => TimeCounter_reg(3), + I2 => deadTime(2), + I3 => TimeCounter_reg(2), + O => ltOp_carry_i_3_n_0 + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(1), + I1 => TimeCounter_reg(1), + I2 => deadTime(0), + I3 => TimeCounter_reg(0), + O => ltOp_carry_i_4_n_0 + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(7), + I1 => deadTime(7), + I2 => TimeCounter_reg(6), + I3 => deadTime(6), + O => ltOp_carry_i_5_n_0 + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(5), + I1 => deadTime(5), + I2 => TimeCounter_reg(4), + I3 => deadTime(4), + O => ltOp_carry_i_6_n_0 + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(3), + I1 => deadTime(3), + I2 => TimeCounter_reg(2), + I3 => deadTime(2), + O => ltOp_carry_i_7_n_0 + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(1), + I1 => deadTime(1), + I2 => TimeCounter_reg(0), + I3 => deadTime(0), + O => ltOp_carry_i_8_n_0 + ); +\minTimeCounter_high[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000022222F22" + ) + port map ( + I0 => key1_prev, + I1 => key1_reg_n_0, + I2 => key2_reg_n_0, + I3 => key2_prev, + I4 => breaking_en, + I5 => reset, + O => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high[0]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \ltOp__31_carry__2_n_0\, + I1 => reset, + O => minTimeCounter_high + ); +\minTimeCounter_high[0]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => minTimeCounter_high_reg(0), + O => \minTimeCounter_high[0]_i_4_n_0\ + ); +\minTimeCounter_high_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[0]_i_3_n_7\, + Q => minTimeCounter_high_reg(0), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[0]_i_3\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \minTimeCounter_high_reg[0]_i_3_n_0\, + CO(2) => \minTimeCounter_high_reg[0]_i_3_n_1\, + CO(1) => \minTimeCounter_high_reg[0]_i_3_n_2\, + CO(0) => \minTimeCounter_high_reg[0]_i_3_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \minTimeCounter_high_reg[0]_i_3_n_4\, + O(2) => \minTimeCounter_high_reg[0]_i_3_n_5\, + O(1) => \minTimeCounter_high_reg[0]_i_3_n_6\, + O(0) => \minTimeCounter_high_reg[0]_i_3_n_7\, + S(3 downto 1) => minTimeCounter_high_reg(3 downto 1), + S(0) => \minTimeCounter_high[0]_i_4_n_0\ + ); +\minTimeCounter_high_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[8]_i_1_n_5\, + Q => minTimeCounter_high_reg(10), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[8]_i_1_n_4\, + Q => minTimeCounter_high_reg(11), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[12]_i_1_n_7\, + Q => minTimeCounter_high_reg(12), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[8]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[12]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[12]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[12]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[12]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[12]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[12]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[12]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[12]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(15 downto 12) + ); +\minTimeCounter_high_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[12]_i_1_n_6\, + Q => minTimeCounter_high_reg(13), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[12]_i_1_n_5\, + Q => minTimeCounter_high_reg(14), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[12]_i_1_n_4\, + Q => minTimeCounter_high_reg(15), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[16]_i_1_n_7\, + Q => minTimeCounter_high_reg(16), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[16]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[12]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[16]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[16]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[16]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[16]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[16]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[16]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[16]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[16]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(19 downto 16) + ); +\minTimeCounter_high_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[16]_i_1_n_6\, + Q => minTimeCounter_high_reg(17), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[16]_i_1_n_5\, + Q => minTimeCounter_high_reg(18), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[16]_i_1_n_4\, + Q => minTimeCounter_high_reg(19), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[0]_i_3_n_6\, + Q => minTimeCounter_high_reg(1), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[20]_i_1_n_7\, + Q => minTimeCounter_high_reg(20), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[20]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[16]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[20]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[20]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[20]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[20]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[20]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[20]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[20]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[20]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(23 downto 20) + ); +\minTimeCounter_high_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[20]_i_1_n_6\, + Q => minTimeCounter_high_reg(21), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[20]_i_1_n_5\, + Q => minTimeCounter_high_reg(22), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[20]_i_1_n_4\, + Q => minTimeCounter_high_reg(23), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[24]_i_1_n_7\, + Q => minTimeCounter_high_reg(24), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[24]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[20]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[24]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[24]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[24]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[24]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[24]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[24]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[24]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[24]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(27 downto 24) + ); +\minTimeCounter_high_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[24]_i_1_n_6\, + Q => minTimeCounter_high_reg(25), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[24]_i_1_n_5\, + Q => minTimeCounter_high_reg(26), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[24]_i_1_n_4\, + Q => minTimeCounter_high_reg(27), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[28]_i_1_n_7\, + Q => minTimeCounter_high_reg(28), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[28]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[24]_i_1_n_0\, + CO(3) => \NLW_minTimeCounter_high_reg[28]_i_1_CO_UNCONNECTED\(3), + CO(2) => \minTimeCounter_high_reg[28]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[28]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[28]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[28]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[28]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[28]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[28]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(31 downto 28) + ); +\minTimeCounter_high_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[28]_i_1_n_6\, + Q => minTimeCounter_high_reg(29), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[0]_i_3_n_5\, + Q => minTimeCounter_high_reg(2), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[28]_i_1_n_5\, + Q => minTimeCounter_high_reg(30), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[28]_i_1_n_4\, + Q => minTimeCounter_high_reg(31), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[0]_i_3_n_4\, + Q => minTimeCounter_high_reg(3), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[4]_i_1_n_7\, + Q => minTimeCounter_high_reg(4), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[0]_i_3_n_0\, + CO(3) => \minTimeCounter_high_reg[4]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[4]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[4]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[4]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[4]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[4]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[4]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(7 downto 4) + ); +\minTimeCounter_high_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[4]_i_1_n_6\, + Q => minTimeCounter_high_reg(5), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[4]_i_1_n_5\, + Q => minTimeCounter_high_reg(6), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[4]_i_1_n_4\, + Q => minTimeCounter_high_reg(7), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[8]_i_1_n_7\, + Q => minTimeCounter_high_reg(8), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[4]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[8]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[8]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[8]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[8]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[8]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[8]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[8]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(11 downto 8) + ); +\minTimeCounter_high_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[8]_i_1_n_6\, + Q => minTimeCounter_high_reg(9), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_low[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000440F" + ) + port map ( + I0 => key2_reg_n_0, + I1 => key2_prev, + I2 => \minTimeCounter_low[0]_i_4_n_0\, + I3 => breaking_en, + I4 => reset, + O => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low[0]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \ltOp__15_carry__2_n_0\, + I1 => reset, + O => minTimeCounter_low + ); +\minTimeCounter_low[0]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"D0DD" + ) + port map ( + I0 => key4_prev, + I1 => key4_reg_n_0, + I2 => key3_reg_n_0, + I3 => key3_prev, + O => \minTimeCounter_low[0]_i_4_n_0\ + ); +\minTimeCounter_low[0]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => minTimeCounter_low_reg(0), + O => \minTimeCounter_low[0]_i_5_n_0\ + ); +\minTimeCounter_low_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[0]_i_3_n_7\, + Q => minTimeCounter_low_reg(0), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[0]_i_3\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \minTimeCounter_low_reg[0]_i_3_n_0\, + CO(2) => \minTimeCounter_low_reg[0]_i_3_n_1\, + CO(1) => \minTimeCounter_low_reg[0]_i_3_n_2\, + CO(0) => \minTimeCounter_low_reg[0]_i_3_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \minTimeCounter_low_reg[0]_i_3_n_4\, + O(2) => \minTimeCounter_low_reg[0]_i_3_n_5\, + O(1) => \minTimeCounter_low_reg[0]_i_3_n_6\, + O(0) => \minTimeCounter_low_reg[0]_i_3_n_7\, + S(3 downto 1) => minTimeCounter_low_reg(3 downto 1), + S(0) => \minTimeCounter_low[0]_i_5_n_0\ + ); +\minTimeCounter_low_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[8]_i_1_n_5\, + Q => minTimeCounter_low_reg(10), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[8]_i_1_n_4\, + Q => minTimeCounter_low_reg(11), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[12]_i_1_n_7\, + Q => minTimeCounter_low_reg(12), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[8]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[12]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[12]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[12]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[12]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[12]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[12]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[12]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[12]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(15 downto 12) + ); +\minTimeCounter_low_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[12]_i_1_n_6\, + Q => minTimeCounter_low_reg(13), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[12]_i_1_n_5\, + Q => minTimeCounter_low_reg(14), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[12]_i_1_n_4\, + Q => minTimeCounter_low_reg(15), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[16]_i_1_n_7\, + Q => minTimeCounter_low_reg(16), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[16]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[12]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[16]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[16]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[16]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[16]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[16]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[16]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[16]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[16]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(19 downto 16) + ); +\minTimeCounter_low_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[16]_i_1_n_6\, + Q => minTimeCounter_low_reg(17), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[16]_i_1_n_5\, + Q => minTimeCounter_low_reg(18), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[16]_i_1_n_4\, + Q => minTimeCounter_low_reg(19), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[0]_i_3_n_6\, + Q => minTimeCounter_low_reg(1), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[20]_i_1_n_7\, + Q => minTimeCounter_low_reg(20), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[20]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[16]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[20]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[20]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[20]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[20]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[20]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[20]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[20]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[20]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(23 downto 20) + ); +\minTimeCounter_low_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[20]_i_1_n_6\, + Q => minTimeCounter_low_reg(21), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[20]_i_1_n_5\, + Q => minTimeCounter_low_reg(22), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[20]_i_1_n_4\, + Q => minTimeCounter_low_reg(23), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[24]_i_1_n_7\, + Q => minTimeCounter_low_reg(24), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[24]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[20]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[24]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[24]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[24]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[24]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[24]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[24]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[24]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[24]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(27 downto 24) + ); +\minTimeCounter_low_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[24]_i_1_n_6\, + Q => minTimeCounter_low_reg(25), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[24]_i_1_n_5\, + Q => minTimeCounter_low_reg(26), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[24]_i_1_n_4\, + Q => minTimeCounter_low_reg(27), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[28]_i_1_n_7\, + Q => minTimeCounter_low_reg(28), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[28]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[24]_i_1_n_0\, + CO(3) => \NLW_minTimeCounter_low_reg[28]_i_1_CO_UNCONNECTED\(3), + CO(2) => \minTimeCounter_low_reg[28]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[28]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[28]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[28]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[28]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[28]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[28]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(31 downto 28) + ); +\minTimeCounter_low_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[28]_i_1_n_6\, + Q => minTimeCounter_low_reg(29), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[0]_i_3_n_5\, + Q => minTimeCounter_low_reg(2), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[28]_i_1_n_5\, + Q => minTimeCounter_low_reg(30), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[28]_i_1_n_4\, + Q => minTimeCounter_low_reg(31), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[0]_i_3_n_4\, + Q => minTimeCounter_low_reg(3), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[4]_i_1_n_7\, + Q => minTimeCounter_low_reg(4), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[0]_i_3_n_0\, + CO(3) => \minTimeCounter_low_reg[4]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[4]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[4]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[4]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[4]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[4]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[4]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(7 downto 4) + ); +\minTimeCounter_low_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[4]_i_1_n_6\, + Q => minTimeCounter_low_reg(5), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[4]_i_1_n_5\, + Q => minTimeCounter_low_reg(6), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[4]_i_1_n_4\, + Q => minTimeCounter_low_reg(7), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[8]_i_1_n_7\, + Q => minTimeCounter_low_reg(8), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[4]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[8]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[8]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[8]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[8]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[8]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[8]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[8]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(11 downto 8) + ); +\minTimeCounter_low_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[8]_i_1_n_6\, + Q => minTimeCounter_low_reg(9), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +minTimeEr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"EEFFEEEEE200E2E2" + ) + port map ( + I0 => minTimeEr_i_2_n_0, + I1 => minTimeEr_i_3_n_0, + I2 => minTimeEr_i_4_n_0, + I3 => minTimeEr_i_5_n_0, + I4 => minTimeEr_i_6_n_0, + I5 => \^mintimeer_reg_0\, + O => minTimeEr_i_1_n_0 + ); +minTimeEr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"0111" + ) + port map ( + I0 => reset, + I1 => breaking_en, + I2 => minTimeEr_i_6_n_0, + I3 => minTimeEr_i_7_n_0, + O => minTimeEr_i_2_n_0 + ); +minTimeEr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => breaking_en, + I1 => reset, + O => minTimeEr_i_3_n_0 + ); +minTimeEr_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"040404FF00000000" + ) + port map ( + I0 => minTimeOK_low, + I1 => key2_reg_n_0, + I2 => key2_prev, + I3 => minTimeEr_i_8_n_0, + I4 => minTimeOK_high, + I5 => minTime_En, + O => minTimeEr_i_4_n_0 + ); +minTimeEr_i_5: unisim.vcomponents.LUT6 + generic map( + INIT => X"55555555F755F7F7" + ) + port map ( + I0 => minTimeEr_i_9_n_0, + I1 => key2_prev, + I2 => key2_reg_n_0, + I3 => key1_reg_n_0, + I4 => key1_prev, + I5 => minTimeEr_i_7_n_0, + O => minTimeEr_i_5_n_0 + ); +minTimeEr_i_6: unisim.vcomponents.LUT6 + generic map( + INIT => X"FBFFFFFFBBFBFBFF" + ) + port map ( + I0 => minTimeOK_low, + I1 => minTime_En, + I2 => key3_prev, + I3 => key3_reg_n_0, + I4 => key4_reg_n_0, + I5 => key4_prev, + O => minTimeEr_i_6_n_0 + ); +minTimeEr_i_7: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFDFDDDDFFDFFFDF" + ) + port map ( + I0 => minTime_En, + I1 => minTimeOK_high, + I2 => key2_reg_n_0, + I3 => key2_prev, + I4 => key1_prev, + I5 => key1_reg_n_0, + O => minTimeEr_i_7_n_0 + ); +minTimeEr_i_8: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => key1_prev, + I1 => key1_reg_n_0, + O => minTimeEr_i_8_n_0 + ); +minTimeEr_i_9: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => breaking_en, + I1 => reset, + O => minTimeEr_i_9_n_0 + ); +minTimeEr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => '1', + D => minTimeEr_i_1_n_0, + Q => \^mintimeer_reg_0\, + R => '0' + ); +minTimeOK_high_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"00AB" + ) + port map ( + I0 => minTimeOK_high, + I1 => \ltOp__31_carry__2_n_0\, + I2 => reset, + I3 => \minTimeCounter_high[0]_i_1_n_0\, + O => minTimeOK_high_i_1_n_0 + ); +minTimeOK_high_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => minTimeOK_high_i_1_n_0, + Q => minTimeOK_high, + R => '0' + ); +minTimeOK_low_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"00AB" + ) + port map ( + I0 => minTimeOK_low, + I1 => \ltOp__15_carry__2_n_0\, + I2 => reset, + I3 => \minTimeCounter_low[0]_i_1_n_0\, + O => minTimeOK_low_i_1_n_0 + ); +minTimeOK_low_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => minTimeOK_low_i_1_n_0, + Q => minTimeOK_low, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Inverter_3lvl_P0N_3lvl_0_2 is + port ( + externalCLK : in STD_LOGIC; + ready : in STD_LOGIC; + reset : in STD_LOGIC; + deadTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + minTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + er : in STD_LOGIC; + minTime_En : in STD_LOGIC; + minTimeEr : out STD_LOGIC; + TKin0 : in STD_LOGIC; + TKin1 : in STD_LOGIC; + breaking_en : in STD_LOGIC; + PWM_out_0 : out STD_LOGIC; + PWM_out_1 : out STD_LOGIC; + PWM_out_2 : out STD_LOGIC; + PWM_out_3 : out STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of Inverter_3lvl_P0N_3lvl_0_2 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of Inverter_3lvl_P0N_3lvl_0_2 : entity is "Inverter_3lvl_P0N_3lvl_0_4,P0N_3lvl,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of Inverter_3lvl_P0N_3lvl_0_2 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of Inverter_3lvl_P0N_3lvl_0_2 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of Inverter_3lvl_P0N_3lvl_0_2 : entity is "P0N_3lvl,Vivado 2019.1"; +end Inverter_3lvl_P0N_3lvl_0_2; + +architecture STRUCTURE of Inverter_3lvl_P0N_3lvl_0_2 is + attribute x_interface_info : string; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.Inverter_3lvl_P0N_3lvl_0_2_P0N_3lvl + port map ( + PWM_out_0 => PWM_out_0, + PWM_out_1 => PWM_out_1, + PWM_out_2 => PWM_out_2, + PWM_out_3 => PWM_out_3, + TKin0 => TKin0, + TKin1 => TKin1, + breaking_en => breaking_en, + deadTime(31 downto 0) => deadTime(31 downto 0), + er => er, + externalCLK => externalCLK, + minTime(31 downto 0) => minTime(31 downto 0), + minTimeEr_reg_0 => minTimeEr, + minTime_En => minTime_En, + ready => ready, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2_stub.v b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2_stub.v new file mode 100644 index 0000000..cbc420a --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2_stub.v @@ -0,0 +1,35 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Fri Jun 11 07:49:57 2021 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top Inverter_3lvl_P0N_3lvl_0_2 -prefix +// Inverter_3lvl_P0N_3lvl_0_2_ Inverter_3lvl_P0N_3lvl_0_4_stub.v +// Design : Inverter_3lvl_P0N_3lvl_0_4 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "P0N_3lvl,Vivado 2019.1" *) +module Inverter_3lvl_P0N_3lvl_0_2(externalCLK, ready, reset, deadTime, minTime, er, + minTime_En, minTimeEr, TKin0, TKin1, breaking_en, PWM_out_0, PWM_out_1, PWM_out_2, PWM_out_3) +/* synthesis syn_black_box black_box_pad_pin="externalCLK,ready,reset,deadTime[31:0],minTime[31:0],er,minTime_En,minTimeEr,TKin0,TKin1,breaking_en,PWM_out_0,PWM_out_1,PWM_out_2,PWM_out_3" */; + input externalCLK; + input ready; + input reset; + input [31:0]deadTime; + input [31:0]minTime; + input er; + input minTime_En; + output minTimeEr; + input TKin0; + input TKin1; + input breaking_en; + output PWM_out_0; + output PWM_out_1; + output PWM_out_2; + output PWM_out_3; +endmodule diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2_stub.vhdl b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2_stub.vhdl new file mode 100644 index 0000000..ff7489d --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_2/Inverter_3lvl_P0N_3lvl_0_2_stub.vhdl @@ -0,0 +1,44 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Fri Jun 11 07:49:57 2021 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top Inverter_3lvl_P0N_3lvl_0_2 -prefix +-- Inverter_3lvl_P0N_3lvl_0_2_ Inverter_3lvl_P0N_3lvl_0_4_stub.vhdl +-- Design : Inverter_3lvl_P0N_3lvl_0_4 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Inverter_3lvl_P0N_3lvl_0_2 is + Port ( + externalCLK : in STD_LOGIC; + ready : in STD_LOGIC; + reset : in STD_LOGIC; + deadTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + minTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + er : in STD_LOGIC; + minTime_En : in STD_LOGIC; + minTimeEr : out STD_LOGIC; + TKin0 : in STD_LOGIC; + TKin1 : in STD_LOGIC; + breaking_en : in STD_LOGIC; + PWM_out_0 : out STD_LOGIC; + PWM_out_1 : out STD_LOGIC; + PWM_out_2 : out STD_LOGIC; + PWM_out_3 : out STD_LOGIC + ); + +end Inverter_3lvl_P0N_3lvl_0_2; + +architecture stub of Inverter_3lvl_P0N_3lvl_0_2 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "externalCLK,ready,reset,deadTime[31:0],minTime[31:0],er,minTime_En,minTimeEr,TKin0,TKin1,breaking_en,PWM_out_0,PWM_out_1,PWM_out_2,PWM_out_3"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "P0N_3lvl,Vivado 2019.1"; +begin +end; diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3.dcp 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z@a?$$OG^f3Y0be{G-M3`dK+AJ0px*JJ5wXfopV+IV1*P1)c@;sa8dwe5i0`}HHhRN zNb<*gT5()Dsx(TxeI}gbOgSI!ozOqQIv{hkBXwfWEfG^G8ofIHUWTJ2} zQQ$k?0z<3jzr58`Swx3uV!#sejC?Z)Q zRAH3x_Th&t(Vaal#Sk2aeeyQspWRj7Q&z|9fRz{eUa( c0O;5@;QKm>MN3Go+>-?l6d3&MJ61;j0PtiZN&o-= literal 0 HcmV?d00001 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3.xml b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3.xml index 670eb6d..e970327 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3.xml +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3.xml @@ -133,6 +133,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:44:44 UTC 2023 + + + outputProductCRC + 9:1b21de40 + + + @@ -407,6 +425,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + Inverter_3lvl_P0N_3lvl_0_3.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_0_3_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_0_3_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_0_3_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_0_3_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + P0N_3lvl_v1_0 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3_sim_netlist.v b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3_sim_netlist.v similarity index 99% rename from LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3_sim_netlist.v rename to LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3_sim_netlist.v index 65e5c93..30cc760 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3_sim_netlist.v +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3_sim_netlist.v @@ -3,19 +3,19 @@ // Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 // Date : Fri Jun 11 07:49:57 2021 // Host : STAS-W10 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_3_sim_netlist.v -// Design : Inverter_3lvl_P0N_3lvl_0_3 +// Command : write_verilog -force -mode funcsim -rename_top Inverter_3lvl_P0N_3lvl_0_3 -prefix +// Inverter_3lvl_P0N_3lvl_0_3_ Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.v +// Design : Inverter_3lvl_P0N_3lvl_0_4 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. // Device : xc7z020clg484-3 // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps -(* CHECK_LICENSE_TYPE = "Inverter_3lvl_P0N_3lvl_0_3,P0N_3lvl,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* CHECK_LICENSE_TYPE = "Inverter_3lvl_P0N_3lvl_0_4,P0N_3lvl,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) (* x_core_info = "P0N_3lvl,Vivado 2019.1" *) (* NotValidForBitStream *) -module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix +module Inverter_3lvl_P0N_3lvl_0_3 (externalCLK, ready, reset, @@ -63,7 +63,7 @@ module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix wire ready; wire reset; - decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_P0N_3lvl U0 + Inverter_3lvl_P0N_3lvl_0_3_P0N_3lvl U0 (.PWM_out_0(PWM_out_0), .PWM_out_1(PWM_out_1), .PWM_out_2(PWM_out_2), @@ -81,7 +81,7 @@ module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix .reset(reset)); endmodule -module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_P0N_3lvl +module Inverter_3lvl_P0N_3lvl_0_3_P0N_3lvl (minTimeEr_reg_0, PWM_out_0, PWM_out_1, diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3_sim_netlist.vhdl b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3_sim_netlist.vhdl similarity index 99% rename from LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3_sim_netlist.vhdl rename to LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3_sim_netlist.vhdl index 3e269b1..b742777 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3_sim_netlist.vhdl +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3_sim_netlist.vhdl @@ -3,9 +3,9 @@ -- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 -- Date : Fri Jun 11 07:49:57 2021 -- Host : STAS-W10 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix --- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_3_sim_netlist.vhdl --- Design : Inverter_3lvl_P0N_3lvl_0_3 +-- Command : write_vhdl -force -mode funcsim -rename_top Inverter_3lvl_P0N_3lvl_0_3 -prefix +-- Inverter_3lvl_P0N_3lvl_0_3_ Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.vhdl +-- Design : Inverter_3lvl_P0N_3lvl_0_4 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-3 @@ -14,7 +14,7 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_P0N_3lvl is +entity Inverter_3lvl_P0N_3lvl_0_3_P0N_3lvl is port ( minTimeEr_reg_0 : out STD_LOGIC; PWM_out_0 : out STD_LOGIC; @@ -32,9 +32,9 @@ entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_P0N_3lvl is deadTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); minTime : in STD_LOGIC_VECTOR ( 31 downto 0 ) ); -end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_P0N_3lvl; +end Inverter_3lvl_P0N_3lvl_0_3_P0N_3lvl; -architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_P0N_3lvl is +architecture STRUCTURE of Inverter_3lvl_P0N_3lvl_0_3_P0N_3lvl is signal \FSM_onehot_lineconfig[0]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_lineconfig[0]_i_2_n_0\ : STD_LOGIC; signal \FSM_onehot_lineconfig[1]_i_1_n_0\ : STD_LOGIC; @@ -4126,7 +4126,7 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +entity Inverter_3lvl_P0N_3lvl_0_3 is port ( externalCLK : in STD_LOGIC; ready : in STD_LOGIC; @@ -4145,24 +4145,24 @@ entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is PWM_out_3 : out STD_LOGIC ); attribute NotValidForBitStream : boolean; - attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; + attribute NotValidForBitStream of Inverter_3lvl_P0N_3lvl_0_3 : entity is true; attribute CHECK_LICENSE_TYPE : string; - attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "Inverter_3lvl_P0N_3lvl_0_3,P0N_3lvl,{}"; + attribute CHECK_LICENSE_TYPE of Inverter_3lvl_P0N_3lvl_0_3 : entity is "Inverter_3lvl_P0N_3lvl_0_4,P0N_3lvl,{}"; attribute downgradeipidentifiedwarnings : string; - attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; + attribute downgradeipidentifiedwarnings of Inverter_3lvl_P0N_3lvl_0_3 : entity is "yes"; attribute ip_definition_source : string; - attribute ip_definition_source of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "package_project"; + attribute ip_definition_source of Inverter_3lvl_P0N_3lvl_0_3 : entity is "package_project"; attribute x_core_info : string; - attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "P0N_3lvl,Vivado 2019.1"; -end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + attribute x_core_info of Inverter_3lvl_P0N_3lvl_0_3 : entity is "P0N_3lvl,Vivado 2019.1"; +end Inverter_3lvl_P0N_3lvl_0_3; -architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +architecture STRUCTURE of Inverter_3lvl_P0N_3lvl_0_3 is attribute x_interface_info : string; attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; attribute x_interface_parameter : string; attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; begin -U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_P0N_3lvl +U0: entity work.Inverter_3lvl_P0N_3lvl_0_3_P0N_3lvl port map ( PWM_out_0 => PWM_out_0, PWM_out_1 => PWM_out_1, diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3_stub.v b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3_stub.v similarity index 83% rename from LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3_stub.v rename to LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3_stub.v index 9c33677..1165215 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3_stub.v +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3_stub.v @@ -3,9 +3,9 @@ // Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 // Date : Fri Jun 11 07:49:57 2021 // Host : STAS-W10 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_3_stub.v -// Design : Inverter_3lvl_P0N_3lvl_0_3 +// Command : write_verilog -force -mode synth_stub -rename_top Inverter_3lvl_P0N_3lvl_0_3 -prefix +// Inverter_3lvl_P0N_3lvl_0_3_ Inverter_3lvl_P0N_3lvl_0_4_stub.v +// Design : Inverter_3lvl_P0N_3lvl_0_4 // Purpose : Stub declaration of top-level module interface // Device : xc7z020clg484-3 // -------------------------------------------------------------------------------- @@ -14,7 +14,7 @@ // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. (* x_core_info = "P0N_3lvl,Vivado 2019.1" *) -module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(externalCLK, ready, reset, deadTime, minTime, er, +module Inverter_3lvl_P0N_3lvl_0_3(externalCLK, ready, reset, deadTime, minTime, er, minTime_En, minTimeEr, TKin0, TKin1, breaking_en, PWM_out_0, PWM_out_1, PWM_out_2, PWM_out_3) /* synthesis syn_black_box black_box_pad_pin="externalCLK,ready,reset,deadTime[31:0],minTime[31:0],er,minTime_En,minTimeEr,TKin0,TKin1,breaking_en,PWM_out_0,PWM_out_1,PWM_out_2,PWM_out_3" */; input externalCLK; diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3_stub.vhdl b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3_stub.vhdl similarity index 81% rename from LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3_stub.vhdl rename to LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3_stub.vhdl index 750a509..fe2825c 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3_stub.vhdl +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3_stub.vhdl @@ -3,16 +3,16 @@ -- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 -- Date : Fri Jun 11 07:49:57 2021 -- Host : STAS-W10 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix --- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_3_stub.vhdl --- Design : Inverter_3lvl_P0N_3lvl_0_3 +-- Command : write_vhdl -force -mode synth_stub -rename_top Inverter_3lvl_P0N_3lvl_0_3 -prefix +-- Inverter_3lvl_P0N_3lvl_0_3_ Inverter_3lvl_P0N_3lvl_0_4_stub.vhdl +-- Design : Inverter_3lvl_P0N_3lvl_0_4 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z020clg484-3 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +entity Inverter_3lvl_P0N_3lvl_0_3 is Port ( externalCLK : in STD_LOGIC; ready : in STD_LOGIC; @@ -31,9 +31,9 @@ entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is PWM_out_3 : out STD_LOGIC ); -end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; +end Inverter_3lvl_P0N_3lvl_0_3; -architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +architecture stub of Inverter_3lvl_P0N_3lvl_0_3 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; diff --git 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ztvvBiRyRA$(&WXU&uC{|fepXO#Jgl3@Ac9sSD*p)&#t(ew=NwH%g#;mtVl+g^VCnj z{*%YOno_IVZldJ#XgkDnb5{AvoH)g&(>`jNvQ!jEa;)ue$G)?rNmnAcH|T~Q}GW9PD}TE5==lJh%iKzLkDh%mF7ig9`%F=N?q~PH`yI~rSEYH-PU~$hUjHu2ZRM!7U z$xCfyiJY{ATkUd<$w(Fqb}i?E(AvmlB(_4nSE)FCnb07I zp6_f~ym0wJQkydc-{@Q=$q`FRo7EN$xKl`cXi&UMq>aorRBovnKAURf_6Wz#_5Y#Yl zV`ALLt@)HK`LLcb@?>3|L+O-jnyA*o_c2BNmb}PUl$+jq!#mN~UZy7^+Fn;EhoUBmE%Qa99RHF$`wMX=*CO;A zH;bxthfB294_!>7v`qh1F_)w5*S`p9Wy|e^Zuhi3NS_KPxfIVc+Gjde5XV$(6zKg^G@u?*hQaY){w=D_B+$*r#TB$T@?srKy(e`n6%H`B{z0`&!l zI)z$(rM*wG!#JEucNq8usb2z*m$gwGaGvx2hwa~A4{F`timRqj}@@n$D$3y<#!FbJuRmC*x!9Gk}WyEC)a!LBLC#ARWDK z>jnt@b2H#O2{sUj16bV^;1yI8u{(1^`ND#{am-4p3Kr!zOhF)1or56J-R}U|QW<`z?uko^L=3iHy38sB<(CX5YWv6#_p-!l|93@EcR!i{d|Z76xxrO zmo85U`>rc%TsW53roY`OQ+FpMp*AtgdoEJ LxVIP952gEGskkh^ literal 0 HcmV?d00001 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4.xml b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4.xml index 96d0cea..fc5f0ea 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4.xml +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4.xml @@ -133,6 +133,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:44:44 UTC 2023 + + + outputProductCRC + 9:fda5c6e7 + + + @@ -407,6 +425,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + Inverter_3lvl_P0N_3lvl_0_4.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_0_4_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_0_4_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + P0N_3lvl_v1_0 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.v b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.v new file mode 100644 index 0000000..4e02765 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.v @@ -0,0 +1,3131 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Fri Jun 11 07:49:57 2021 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top Inverter_3lvl_P0N_3lvl_0_4 -prefix +// Inverter_3lvl_P0N_3lvl_0_4_ Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.v +// Design : Inverter_3lvl_P0N_3lvl_0_4 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "Inverter_3lvl_P0N_3lvl_0_4,P0N_3lvl,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "P0N_3lvl,Vivado 2019.1" *) +(* NotValidForBitStream *) +module Inverter_3lvl_P0N_3lvl_0_4 + (externalCLK, + ready, + reset, + deadTime, + minTime, + er, + minTime_En, + minTimeEr, + TKin0, + TKin1, + breaking_en, + PWM_out_0, + PWM_out_1, + PWM_out_2, + PWM_out_3); + input externalCLK; + input ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + input [31:0]deadTime; + input [31:0]minTime; + input er; + input minTime_En; + output minTimeEr; + input TKin0; + input TKin1; + input breaking_en; + output PWM_out_0; + output PWM_out_1; + output PWM_out_2; + output PWM_out_3; + + wire PWM_out_0; + wire PWM_out_1; + wire PWM_out_2; + wire PWM_out_3; + wire TKin0; + wire TKin1; + wire breaking_en; + wire [31:0]deadTime; + wire er; + wire externalCLK; + wire [31:0]minTime; + wire minTimeEr; + wire minTime_En; + wire ready; + wire reset; + + Inverter_3lvl_P0N_3lvl_0_4_P0N_3lvl U0 + (.PWM_out_0(PWM_out_0), + .PWM_out_1(PWM_out_1), + .PWM_out_2(PWM_out_2), + .PWM_out_3(PWM_out_3), + .TKin0(TKin0), + .TKin1(TKin1), + .breaking_en(breaking_en), + .deadTime(deadTime), + .er(er), + .externalCLK(externalCLK), + .minTime(minTime), + .minTimeEr_reg_0(minTimeEr), + .minTime_En(minTime_En), + .ready(ready), + .reset(reset)); +endmodule + +module Inverter_3lvl_P0N_3lvl_0_4_P0N_3lvl + (minTimeEr_reg_0, + PWM_out_0, + PWM_out_1, + PWM_out_2, + PWM_out_3, + reset, + externalCLK, + TKin0, + TKin1, + breaking_en, + er, + ready, + minTime_En, + deadTime, + minTime); + output minTimeEr_reg_0; + output PWM_out_0; + output PWM_out_1; + output PWM_out_2; + output PWM_out_3; + input reset; + input externalCLK; + input TKin0; + input TKin1; + input breaking_en; + input er; + input ready; + input minTime_En; + input [31:0]deadTime; + input [31:0]minTime; + + wire \FSM_onehot_lineconfig[0]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[0]_i_2_n_0 ; + wire \FSM_onehot_lineconfig[1]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[2]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[2]_i_2_n_0 ; + wire \FSM_onehot_lineconfig[3]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[4]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[5]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[5]_i_2_n_0 ; + wire \FSM_onehot_lineconfig[5]_i_3_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_2_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_3_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_4_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_5_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_6_n_0 ; + wire \FSM_onehot_lineconfig_reg_n_0_[0] ; + wire \FSM_onehot_lineconfig_reg_n_0_[1] ; + wire \FSM_onehot_lineconfig_reg_n_0_[2] ; + wire \FSM_onehot_lineconfig_reg_n_0_[3] ; + wire \FSM_onehot_lineconfig_reg_n_0_[4] ; + wire \FSM_onehot_lineconfig_reg_n_0_[5] ; + wire \FSM_onehot_lineconfig_reg_n_0_[6] ; + wire PWM_out_0; + wire PWM_out_0_i_1_n_0; + wire PWM_out_1; + wire PWM_out_1_i_1_n_0; + wire PWM_out_2; + wire PWM_out_2_i_1_n_0; + wire PWM_out_3; + wire PWM_out_3_i_1_n_0; + wire TKin0; + wire TKin0_triggered; + wire TKin0_triggered28_out; + wire TKin0_triggered_i_1_n_0; + wire TKin1; + wire TKin1_triggered; + wire TKin1_triggered_i_1_n_0; + wire \TimeCounter[0]_i_2_n_0 ; + wire [31:0]TimeCounter_reg; + wire \TimeCounter_reg[0]_i_1_n_0 ; + wire \TimeCounter_reg[0]_i_1_n_1 ; + wire \TimeCounter_reg[0]_i_1_n_2 ; + wire \TimeCounter_reg[0]_i_1_n_3 ; + wire \TimeCounter_reg[0]_i_1_n_4 ; + wire \TimeCounter_reg[0]_i_1_n_5 ; + wire \TimeCounter_reg[0]_i_1_n_6 ; + wire \TimeCounter_reg[0]_i_1_n_7 ; + wire \TimeCounter_reg[12]_i_1_n_0 ; + wire \TimeCounter_reg[12]_i_1_n_1 ; + wire \TimeCounter_reg[12]_i_1_n_2 ; + wire \TimeCounter_reg[12]_i_1_n_3 ; + wire \TimeCounter_reg[12]_i_1_n_4 ; + wire \TimeCounter_reg[12]_i_1_n_5 ; + wire \TimeCounter_reg[12]_i_1_n_6 ; + wire \TimeCounter_reg[12]_i_1_n_7 ; + wire \TimeCounter_reg[16]_i_1_n_0 ; + wire \TimeCounter_reg[16]_i_1_n_1 ; + wire \TimeCounter_reg[16]_i_1_n_2 ; + wire \TimeCounter_reg[16]_i_1_n_3 ; + wire \TimeCounter_reg[16]_i_1_n_4 ; + wire \TimeCounter_reg[16]_i_1_n_5 ; + wire \TimeCounter_reg[16]_i_1_n_6 ; + wire \TimeCounter_reg[16]_i_1_n_7 ; + wire \TimeCounter_reg[20]_i_1_n_0 ; + wire \TimeCounter_reg[20]_i_1_n_1 ; + wire \TimeCounter_reg[20]_i_1_n_2 ; + wire \TimeCounter_reg[20]_i_1_n_3 ; + wire \TimeCounter_reg[20]_i_1_n_4 ; + wire \TimeCounter_reg[20]_i_1_n_5 ; + wire \TimeCounter_reg[20]_i_1_n_6 ; + wire \TimeCounter_reg[20]_i_1_n_7 ; + wire \TimeCounter_reg[24]_i_1_n_0 ; + wire \TimeCounter_reg[24]_i_1_n_1 ; + wire \TimeCounter_reg[24]_i_1_n_2 ; + wire \TimeCounter_reg[24]_i_1_n_3 ; + wire \TimeCounter_reg[24]_i_1_n_4 ; + wire \TimeCounter_reg[24]_i_1_n_5 ; + wire \TimeCounter_reg[24]_i_1_n_6 ; + wire \TimeCounter_reg[24]_i_1_n_7 ; + wire \TimeCounter_reg[28]_i_1_n_1 ; + wire \TimeCounter_reg[28]_i_1_n_2 ; + wire \TimeCounter_reg[28]_i_1_n_3 ; + wire \TimeCounter_reg[28]_i_1_n_4 ; + wire \TimeCounter_reg[28]_i_1_n_5 ; + wire \TimeCounter_reg[28]_i_1_n_6 ; + wire \TimeCounter_reg[28]_i_1_n_7 ; + wire \TimeCounter_reg[4]_i_1_n_0 ; + wire \TimeCounter_reg[4]_i_1_n_1 ; + wire \TimeCounter_reg[4]_i_1_n_2 ; + wire \TimeCounter_reg[4]_i_1_n_3 ; + wire \TimeCounter_reg[4]_i_1_n_4 ; + wire \TimeCounter_reg[4]_i_1_n_5 ; + wire \TimeCounter_reg[4]_i_1_n_6 ; + wire \TimeCounter_reg[4]_i_1_n_7 ; + wire \TimeCounter_reg[8]_i_1_n_0 ; + wire \TimeCounter_reg[8]_i_1_n_1 ; + wire \TimeCounter_reg[8]_i_1_n_2 ; + wire \TimeCounter_reg[8]_i_1_n_3 ; + wire \TimeCounter_reg[8]_i_1_n_4 ; + wire \TimeCounter_reg[8]_i_1_n_5 ; + wire \TimeCounter_reg[8]_i_1_n_6 ; + wire \TimeCounter_reg[8]_i_1_n_7 ; + wire breaking_en; + wire [31:0]deadTime; + wire deadTimeCounterReset_i_1_n_0; + wire deadTimeCounterReset_i_2_n_0; + wire deadTimeCounterReset_i_3_n_0; + wire deadTimeCounterReset_i_4_n_0; + wire deadTimeCounterReset_i_5_n_0; + wire deadTimeCounterReset_i_6_n_0; + wire deadTimeCounterReset_i_7_n_0; + wire deadTimeCounterReset_reg_n_0; + wire deadTimeOK; + wire deadTimeOK_i_1_n_0; + wire er; + wire externalCLK; + wire key1_i_1_n_0; + wire key1_i_2_n_0; + wire key1_prev; + wire key1_reg_n_0; + wire key2_i_2_n_0; + wire key2_prev; + wire key2_reg_n_0; + wire key3; + wire key3_i_1_n_0; + wire key3_prev; + wire key3_reg_n_0; + wire key4_i_1_n_0; + wire key4_prev; + wire key4_reg_n_0; + wire ltOp__15_carry__0_i_1_n_0; + wire ltOp__15_carry__0_i_2_n_0; + wire ltOp__15_carry__0_i_3_n_0; + wire ltOp__15_carry__0_i_4_n_0; + wire ltOp__15_carry__0_i_5_n_0; + wire ltOp__15_carry__0_i_6_n_0; + wire ltOp__15_carry__0_i_7_n_0; + wire ltOp__15_carry__0_i_8_n_0; + wire ltOp__15_carry__0_n_0; + wire ltOp__15_carry__0_n_1; + wire ltOp__15_carry__0_n_2; + wire ltOp__15_carry__0_n_3; + wire ltOp__15_carry__1_i_1_n_0; + wire ltOp__15_carry__1_i_2_n_0; + wire ltOp__15_carry__1_i_3_n_0; + wire ltOp__15_carry__1_i_4_n_0; + wire ltOp__15_carry__1_i_5_n_0; + wire ltOp__15_carry__1_i_6_n_0; + wire ltOp__15_carry__1_i_7_n_0; + wire ltOp__15_carry__1_i_8_n_0; + wire ltOp__15_carry__1_n_0; + wire ltOp__15_carry__1_n_1; + wire ltOp__15_carry__1_n_2; + wire ltOp__15_carry__1_n_3; + wire ltOp__15_carry__2_i_1_n_0; + wire ltOp__15_carry__2_i_2_n_0; + wire ltOp__15_carry__2_i_3_n_0; + wire ltOp__15_carry__2_i_4_n_0; + wire ltOp__15_carry__2_i_5_n_0; + wire ltOp__15_carry__2_i_6_n_0; + wire ltOp__15_carry__2_i_7_n_0; + wire ltOp__15_carry__2_i_8_n_0; + wire ltOp__15_carry__2_n_0; + wire ltOp__15_carry__2_n_1; + wire ltOp__15_carry__2_n_2; + wire ltOp__15_carry__2_n_3; + wire ltOp__15_carry_i_1_n_0; + wire ltOp__15_carry_i_2_n_0; + wire ltOp__15_carry_i_3_n_0; + wire ltOp__15_carry_i_4_n_0; + wire ltOp__15_carry_i_5_n_0; + wire ltOp__15_carry_i_6_n_0; + wire ltOp__15_carry_i_7_n_0; + wire ltOp__15_carry_i_8_n_0; + wire ltOp__15_carry_n_0; + wire ltOp__15_carry_n_1; + wire ltOp__15_carry_n_2; + wire ltOp__15_carry_n_3; + wire ltOp__31_carry__0_n_0; + wire ltOp__31_carry__0_n_1; + wire ltOp__31_carry__0_n_2; + wire ltOp__31_carry__0_n_3; + wire ltOp__31_carry__1_n_0; + wire ltOp__31_carry__1_n_1; + wire ltOp__31_carry__1_n_2; + wire ltOp__31_carry__1_n_3; + wire ltOp__31_carry__2_n_0; + wire ltOp__31_carry__2_n_1; + wire ltOp__31_carry__2_n_2; + wire ltOp__31_carry__2_n_3; + wire ltOp__31_carry_i_1__0_n_0; + wire ltOp__31_carry_i_1__1_n_0; + wire ltOp__31_carry_i_1__2_n_0; + wire ltOp__31_carry_i_1_n_0; + wire ltOp__31_carry_i_2__0_n_0; + wire ltOp__31_carry_i_2__1_n_0; + wire ltOp__31_carry_i_2__2_n_0; + wire ltOp__31_carry_i_2_n_0; + wire ltOp__31_carry_i_3__0_n_0; + wire ltOp__31_carry_i_3__1_n_0; + wire ltOp__31_carry_i_3__2_n_0; + wire ltOp__31_carry_i_3_n_0; + wire ltOp__31_carry_i_4__0_n_0; + wire ltOp__31_carry_i_4__1_n_0; + wire ltOp__31_carry_i_4__2_n_0; + wire ltOp__31_carry_i_4_n_0; + wire ltOp__31_carry_i_5__0_n_0; + wire ltOp__31_carry_i_5__1_n_0; + wire ltOp__31_carry_i_5__2_n_0; + wire ltOp__31_carry_i_5_n_0; + wire ltOp__31_carry_i_6__0_n_0; + wire ltOp__31_carry_i_6__1_n_0; + wire ltOp__31_carry_i_6__2_n_0; + wire ltOp__31_carry_i_6_n_0; + wire ltOp__31_carry_i_7__0_n_0; + wire ltOp__31_carry_i_7__1_n_0; + wire ltOp__31_carry_i_7__2_n_0; + wire ltOp__31_carry_i_7_n_0; + wire ltOp__31_carry_i_8__0_n_0; + wire ltOp__31_carry_i_8__1_n_0; + wire ltOp__31_carry_i_8__2_n_0; + wire ltOp__31_carry_i_8_n_0; + wire ltOp__31_carry_n_0; + wire ltOp__31_carry_n_1; + wire ltOp__31_carry_n_2; + wire ltOp__31_carry_n_3; + wire ltOp_carry__0_i_1_n_0; + wire ltOp_carry__0_i_2_n_0; + wire ltOp_carry__0_i_3_n_0; + wire ltOp_carry__0_i_4_n_0; + wire ltOp_carry__0_i_5_n_0; + wire ltOp_carry__0_i_6_n_0; + wire ltOp_carry__0_i_7_n_0; + wire ltOp_carry__0_i_8_n_0; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_i_1_n_0; + wire ltOp_carry__1_i_2_n_0; + wire ltOp_carry__1_i_3_n_0; + wire ltOp_carry__1_i_4_n_0; + wire ltOp_carry__1_i_5_n_0; + wire ltOp_carry__1_i_6_n_0; + wire ltOp_carry__1_i_7_n_0; + wire ltOp_carry__1_i_8_n_0; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_i_1_n_0; + wire ltOp_carry__2_i_2_n_0; + wire ltOp_carry__2_i_3_n_0; + wire ltOp_carry__2_i_4_n_0; + wire ltOp_carry__2_i_5_n_0; + wire ltOp_carry__2_i_6_n_0; + wire ltOp_carry__2_i_7_n_0; + wire ltOp_carry__2_i_8_n_0; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [31:0]minTime; + wire minTimeCounter_high; + wire \minTimeCounter_high[0]_i_1_n_0 ; + wire \minTimeCounter_high[0]_i_4_n_0 ; + wire [31:0]minTimeCounter_high_reg; + wire \minTimeCounter_high_reg[0]_i_3_n_0 ; + wire \minTimeCounter_high_reg[0]_i_3_n_1 ; + wire \minTimeCounter_high_reg[0]_i_3_n_2 ; + wire \minTimeCounter_high_reg[0]_i_3_n_3 ; + wire \minTimeCounter_high_reg[0]_i_3_n_4 ; + wire \minTimeCounter_high_reg[0]_i_3_n_5 ; + wire \minTimeCounter_high_reg[0]_i_3_n_6 ; + wire \minTimeCounter_high_reg[0]_i_3_n_7 ; + wire \minTimeCounter_high_reg[12]_i_1_n_0 ; + wire \minTimeCounter_high_reg[12]_i_1_n_1 ; + wire \minTimeCounter_high_reg[12]_i_1_n_2 ; + wire \minTimeCounter_high_reg[12]_i_1_n_3 ; + wire \minTimeCounter_high_reg[12]_i_1_n_4 ; + wire \minTimeCounter_high_reg[12]_i_1_n_5 ; + wire \minTimeCounter_high_reg[12]_i_1_n_6 ; + wire \minTimeCounter_high_reg[12]_i_1_n_7 ; + wire \minTimeCounter_high_reg[16]_i_1_n_0 ; + wire \minTimeCounter_high_reg[16]_i_1_n_1 ; + wire \minTimeCounter_high_reg[16]_i_1_n_2 ; + wire \minTimeCounter_high_reg[16]_i_1_n_3 ; + wire \minTimeCounter_high_reg[16]_i_1_n_4 ; + wire \minTimeCounter_high_reg[16]_i_1_n_5 ; + wire \minTimeCounter_high_reg[16]_i_1_n_6 ; + wire \minTimeCounter_high_reg[16]_i_1_n_7 ; + wire \minTimeCounter_high_reg[20]_i_1_n_0 ; + wire \minTimeCounter_high_reg[20]_i_1_n_1 ; + wire \minTimeCounter_high_reg[20]_i_1_n_2 ; + wire \minTimeCounter_high_reg[20]_i_1_n_3 ; + wire \minTimeCounter_high_reg[20]_i_1_n_4 ; + wire \minTimeCounter_high_reg[20]_i_1_n_5 ; + wire \minTimeCounter_high_reg[20]_i_1_n_6 ; + wire \minTimeCounter_high_reg[20]_i_1_n_7 ; + wire \minTimeCounter_high_reg[24]_i_1_n_0 ; + wire \minTimeCounter_high_reg[24]_i_1_n_1 ; + wire \minTimeCounter_high_reg[24]_i_1_n_2 ; + wire \minTimeCounter_high_reg[24]_i_1_n_3 ; + wire \minTimeCounter_high_reg[24]_i_1_n_4 ; + wire \minTimeCounter_high_reg[24]_i_1_n_5 ; + wire \minTimeCounter_high_reg[24]_i_1_n_6 ; + wire \minTimeCounter_high_reg[24]_i_1_n_7 ; + wire \minTimeCounter_high_reg[28]_i_1_n_1 ; + wire \minTimeCounter_high_reg[28]_i_1_n_2 ; + wire \minTimeCounter_high_reg[28]_i_1_n_3 ; + wire \minTimeCounter_high_reg[28]_i_1_n_4 ; + wire \minTimeCounter_high_reg[28]_i_1_n_5 ; + wire \minTimeCounter_high_reg[28]_i_1_n_6 ; + wire \minTimeCounter_high_reg[28]_i_1_n_7 ; + wire \minTimeCounter_high_reg[4]_i_1_n_0 ; + wire \minTimeCounter_high_reg[4]_i_1_n_1 ; + wire \minTimeCounter_high_reg[4]_i_1_n_2 ; + wire \minTimeCounter_high_reg[4]_i_1_n_3 ; + wire \minTimeCounter_high_reg[4]_i_1_n_4 ; + wire \minTimeCounter_high_reg[4]_i_1_n_5 ; + wire \minTimeCounter_high_reg[4]_i_1_n_6 ; + wire \minTimeCounter_high_reg[4]_i_1_n_7 ; + wire \minTimeCounter_high_reg[8]_i_1_n_0 ; + wire \minTimeCounter_high_reg[8]_i_1_n_1 ; + wire \minTimeCounter_high_reg[8]_i_1_n_2 ; + wire \minTimeCounter_high_reg[8]_i_1_n_3 ; + wire \minTimeCounter_high_reg[8]_i_1_n_4 ; + wire \minTimeCounter_high_reg[8]_i_1_n_5 ; + wire \minTimeCounter_high_reg[8]_i_1_n_6 ; + wire \minTimeCounter_high_reg[8]_i_1_n_7 ; + wire minTimeCounter_low; + wire \minTimeCounter_low[0]_i_1_n_0 ; + wire \minTimeCounter_low[0]_i_4_n_0 ; + wire \minTimeCounter_low[0]_i_5_n_0 ; + wire [31:0]minTimeCounter_low_reg; + wire \minTimeCounter_low_reg[0]_i_3_n_0 ; + wire \minTimeCounter_low_reg[0]_i_3_n_1 ; + wire \minTimeCounter_low_reg[0]_i_3_n_2 ; + wire \minTimeCounter_low_reg[0]_i_3_n_3 ; + wire \minTimeCounter_low_reg[0]_i_3_n_4 ; + wire \minTimeCounter_low_reg[0]_i_3_n_5 ; + wire \minTimeCounter_low_reg[0]_i_3_n_6 ; + wire \minTimeCounter_low_reg[0]_i_3_n_7 ; + wire \minTimeCounter_low_reg[12]_i_1_n_0 ; + wire \minTimeCounter_low_reg[12]_i_1_n_1 ; + wire \minTimeCounter_low_reg[12]_i_1_n_2 ; + wire \minTimeCounter_low_reg[12]_i_1_n_3 ; + wire \minTimeCounter_low_reg[12]_i_1_n_4 ; + wire \minTimeCounter_low_reg[12]_i_1_n_5 ; + wire \minTimeCounter_low_reg[12]_i_1_n_6 ; + wire \minTimeCounter_low_reg[12]_i_1_n_7 ; + wire \minTimeCounter_low_reg[16]_i_1_n_0 ; + wire \minTimeCounter_low_reg[16]_i_1_n_1 ; + wire \minTimeCounter_low_reg[16]_i_1_n_2 ; + wire \minTimeCounter_low_reg[16]_i_1_n_3 ; + wire \minTimeCounter_low_reg[16]_i_1_n_4 ; + wire \minTimeCounter_low_reg[16]_i_1_n_5 ; + wire \minTimeCounter_low_reg[16]_i_1_n_6 ; + wire \minTimeCounter_low_reg[16]_i_1_n_7 ; + wire \minTimeCounter_low_reg[20]_i_1_n_0 ; + wire \minTimeCounter_low_reg[20]_i_1_n_1 ; + wire \minTimeCounter_low_reg[20]_i_1_n_2 ; + wire \minTimeCounter_low_reg[20]_i_1_n_3 ; + wire \minTimeCounter_low_reg[20]_i_1_n_4 ; + wire \minTimeCounter_low_reg[20]_i_1_n_5 ; + wire \minTimeCounter_low_reg[20]_i_1_n_6 ; + wire \minTimeCounter_low_reg[20]_i_1_n_7 ; + wire \minTimeCounter_low_reg[24]_i_1_n_0 ; + wire \minTimeCounter_low_reg[24]_i_1_n_1 ; + wire \minTimeCounter_low_reg[24]_i_1_n_2 ; + wire \minTimeCounter_low_reg[24]_i_1_n_3 ; + wire \minTimeCounter_low_reg[24]_i_1_n_4 ; + wire \minTimeCounter_low_reg[24]_i_1_n_5 ; + wire \minTimeCounter_low_reg[24]_i_1_n_6 ; + wire \minTimeCounter_low_reg[24]_i_1_n_7 ; + wire \minTimeCounter_low_reg[28]_i_1_n_1 ; + wire \minTimeCounter_low_reg[28]_i_1_n_2 ; + wire \minTimeCounter_low_reg[28]_i_1_n_3 ; + wire \minTimeCounter_low_reg[28]_i_1_n_4 ; + wire \minTimeCounter_low_reg[28]_i_1_n_5 ; + wire \minTimeCounter_low_reg[28]_i_1_n_6 ; + wire \minTimeCounter_low_reg[28]_i_1_n_7 ; + wire \minTimeCounter_low_reg[4]_i_1_n_0 ; + wire \minTimeCounter_low_reg[4]_i_1_n_1 ; + wire \minTimeCounter_low_reg[4]_i_1_n_2 ; + wire \minTimeCounter_low_reg[4]_i_1_n_3 ; + wire \minTimeCounter_low_reg[4]_i_1_n_4 ; + wire \minTimeCounter_low_reg[4]_i_1_n_5 ; + wire \minTimeCounter_low_reg[4]_i_1_n_6 ; + wire \minTimeCounter_low_reg[4]_i_1_n_7 ; + wire \minTimeCounter_low_reg[8]_i_1_n_0 ; + wire \minTimeCounter_low_reg[8]_i_1_n_1 ; + wire \minTimeCounter_low_reg[8]_i_1_n_2 ; + wire \minTimeCounter_low_reg[8]_i_1_n_3 ; + wire \minTimeCounter_low_reg[8]_i_1_n_4 ; + wire \minTimeCounter_low_reg[8]_i_1_n_5 ; + wire \minTimeCounter_low_reg[8]_i_1_n_6 ; + wire \minTimeCounter_low_reg[8]_i_1_n_7 ; + wire minTimeEr_i_1_n_0; + wire minTimeEr_i_2_n_0; + wire minTimeEr_i_3_n_0; + wire minTimeEr_i_4_n_0; + wire minTimeEr_i_5_n_0; + wire minTimeEr_i_6_n_0; + wire minTimeEr_i_7_n_0; + wire minTimeEr_i_8_n_0; + wire minTimeEr_i_9_n_0; + wire minTimeEr_reg_0; + wire minTimeOK_high; + wire minTimeOK_high_i_1_n_0; + wire minTimeOK_low; + wire minTimeOK_low_i_1_n_0; + wire minTime_En; + wire p_0_in; + wire ready; + wire reset; + wire sel; + wire [3:3]\NLW_TimeCounter_reg[28]_i_1_CO_UNCONNECTED ; + wire [3:0]NLW_ltOp__15_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp__15_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp__15_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp__15_carry__2_O_UNCONNECTED; + wire [3:0]NLW_ltOp__31_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp__31_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp__31_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp__31_carry__2_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + wire [3:3]\NLW_minTimeCounter_high_reg[28]_i_1_CO_UNCONNECTED ; + wire [3:3]\NLW_minTimeCounter_low_reg[28]_i_1_CO_UNCONNECTED ; + + LUT6 #( + .INIT(64'hFFFFFFFE00000000)) + \FSM_onehot_lineconfig[0]_i_1 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I4(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I5(\FSM_onehot_lineconfig[0]_i_2_n_0 ), + .O(\FSM_onehot_lineconfig[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_lineconfig[0]_i_2 + (.I0(TKin1), + .I1(TKin0), + .O(\FSM_onehot_lineconfig[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'h1000FFFF00000000)) + \FSM_onehot_lineconfig[1]_i_1 + (.I0(TKin1), + .I1(TKin1_triggered), + .I2(TKin0_triggered), + .I3(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I4(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I5(TKin0), + .O(\FSM_onehot_lineconfig[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h00EFEF0F)) + \FSM_onehot_lineconfig[2]_i_1 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I2(\FSM_onehot_lineconfig[2]_i_2_n_0 ), + .I3(TKin0), + .I4(TKin1), + .O(\FSM_onehot_lineconfig[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'h900990099009FFFF)) + \FSM_onehot_lineconfig[2]_i_2 + (.I0(TKin1), + .I1(TKin1_triggered), + .I2(TKin0), + .I3(TKin0_triggered), + .I4(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I5(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .O(\FSM_onehot_lineconfig[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0000000055D50000)) + \FSM_onehot_lineconfig[3]_i_1 + (.I0(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I2(TKin1_triggered), + .I3(TKin0_triggered), + .I4(TKin1), + .I5(TKin0), + .O(\FSM_onehot_lineconfig[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT4 #( + .INIT(16'h2230)) + \FSM_onehot_lineconfig[4]_i_1 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I1(TKin0), + .I2(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I3(TKin1), + .O(\FSM_onehot_lineconfig[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0CFF0C0D00050005)) + \FSM_onehot_lineconfig[5]_i_1 + (.I0(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I2(TKin1), + .I3(TKin0), + .I4(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I5(\FSM_onehot_lineconfig[5]_i_3_n_0 ), + .O(\FSM_onehot_lineconfig[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h1)) + \FSM_onehot_lineconfig[5]_i_2 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .O(\FSM_onehot_lineconfig[5]_i_2_n_0 )); + LUT4 #( + .INIT(16'h9009)) + \FSM_onehot_lineconfig[5]_i_3 + (.I0(TKin0_triggered), + .I1(TKin0), + .I2(TKin1_triggered), + .I3(TKin1), + .O(\FSM_onehot_lineconfig[5]_i_3_n_0 )); + LUT3 #( + .INIT(8'h0E)) + \FSM_onehot_lineconfig[6]_i_1 + (.I0(\FSM_onehot_lineconfig[6]_i_3_n_0 ), + .I1(\FSM_onehot_lineconfig[6]_i_4_n_0 ), + .I2(breaking_en), + .O(\FSM_onehot_lineconfig[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT4 #( + .INIT(16'h5504)) + \FSM_onehot_lineconfig[6]_i_2 + (.I0(TKin1), + .I1(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I2(TKin0), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .O(\FSM_onehot_lineconfig[6]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'hFFFEECAE)) + \FSM_onehot_lineconfig[6]_i_3 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I2(TKin1), + .I3(TKin0), + .I4(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .O(\FSM_onehot_lineconfig[6]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAABAAAAAFFFFAAAA)) + \FSM_onehot_lineconfig[6]_i_4 + (.I0(\FSM_onehot_lineconfig[6]_i_5_n_0 ), + .I1(er), + .I2(ready), + .I3(\FSM_onehot_lineconfig[6]_i_6_n_0 ), + .I4(deadTimeOK), + .I5(\FSM_onehot_lineconfig[2]_i_2_n_0 ), + .O(\FSM_onehot_lineconfig[6]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFC88A0A8)) + \FSM_onehot_lineconfig[6]_i_5 + (.I0(deadTimeOK), + .I1(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I3(TKin1), + .I4(TKin0), + .O(\FSM_onehot_lineconfig[6]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'hFF232323)) + \FSM_onehot_lineconfig[6]_i_6 + (.I0(deadTimeCounterReset_reg_n_0), + .I1(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I3(TKin1), + .I4(TKin0), + .O(\FSM_onehot_lineconfig[6]_i_6_n_0 )); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDSE #( + .INIT(1'b1)) + \FSM_onehot_lineconfig_reg[0] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[0]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .S(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[1] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[1]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[2] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[2]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[3] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[3]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[4] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[4]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[5] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[5]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[6] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[6]_i_2_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT4 #( + .INIT(16'hFFEF)) + PWM_out_0_i_1 + (.I0(key1_reg_n_0), + .I1(er), + .I2(ready), + .I3(minTimeEr_reg_0), + .O(PWM_out_0_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + PWM_out_0_reg + (.C(externalCLK), + .CE(1'b1), + .D(PWM_out_0_i_1_n_0), + .Q(PWM_out_0), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT4 #( + .INIT(16'hFFEF)) + PWM_out_1_i_1 + (.I0(key2_reg_n_0), + .I1(er), + .I2(ready), + .I3(minTimeEr_reg_0), + .O(PWM_out_1_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + PWM_out_1_reg + (.C(externalCLK), + .CE(1'b1), + .D(PWM_out_1_i_1_n_0), + .Q(PWM_out_1), + .R(1'b0)); + LUT5 #( + .INIT(32'hFFFFFFEF)) + PWM_out_2_i_1 + (.I0(key3_reg_n_0), + .I1(minTimeEr_reg_0), + .I2(ready), + .I3(er), + .I4(breaking_en), + .O(PWM_out_2_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + PWM_out_2_reg + (.C(externalCLK), + .CE(1'b1), + .D(PWM_out_2_i_1_n_0), + .Q(PWM_out_2), + .R(1'b0)); + LUT5 #( + .INIT(32'hFFFFFFEF)) + PWM_out_3_i_1 + (.I0(key4_reg_n_0), + .I1(minTimeEr_reg_0), + .I2(ready), + .I3(er), + .I4(breaking_en), + .O(PWM_out_3_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + PWM_out_3_reg + (.C(externalCLK), + .CE(1'b1), + .D(PWM_out_3_i_1_n_0), + .Q(PWM_out_3), + .R(1'b0)); + LUT6 #( + .INIT(64'hAA08FFFFAA080000)) + TKin0_triggered_i_1 + (.I0(TKin0), + .I1(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I2(TKin1), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I4(TKin0_triggered28_out), + .I5(TKin0_triggered), + .O(TKin0_triggered_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + TKin0_triggered_reg + (.C(externalCLK), + .CE(1'b1), + .D(TKin0_triggered_i_1_n_0), + .Q(TKin0_triggered), + .R(1'b0)); + LUT6 #( + .INIT(64'hAA08FFFFAA080000)) + TKin1_triggered_i_1 + (.I0(TKin1), + .I1(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I2(TKin0), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I4(TKin0_triggered28_out), + .I5(TKin1_triggered), + .O(TKin1_triggered_i_1_n_0)); + LUT6 #( + .INIT(64'h22AA22A820AA2020)) + TKin1_triggered_i_2 + (.I0(minTimeEr_i_9_n_0), + .I1(TKin1), + .I2(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I3(TKin0), + .I4(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I5(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .O(TKin0_triggered28_out)); + FDRE #( + .INIT(1'b1)) + TKin1_triggered_reg + (.C(externalCLK), + .CE(1'b1), + .D(TKin1_triggered_i_1_n_0), + .Q(TKin1_triggered), + .R(1'b0)); + LUT1 #( + .INIT(2'h1)) + \TimeCounter[0]_i_2 + (.I0(TimeCounter_reg[0]), + .O(\TimeCounter[0]_i_2_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[0] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[0]_i_1_n_7 ), + .Q(TimeCounter_reg[0]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[0]_i_1 + (.CI(1'b0), + .CO({\TimeCounter_reg[0]_i_1_n_0 ,\TimeCounter_reg[0]_i_1_n_1 ,\TimeCounter_reg[0]_i_1_n_2 ,\TimeCounter_reg[0]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\TimeCounter_reg[0]_i_1_n_4 ,\TimeCounter_reg[0]_i_1_n_5 ,\TimeCounter_reg[0]_i_1_n_6 ,\TimeCounter_reg[0]_i_1_n_7 }), + .S({TimeCounter_reg[3:1],\TimeCounter[0]_i_2_n_0 })); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[10] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[8]_i_1_n_5 ), + .Q(TimeCounter_reg[10]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[11] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[8]_i_1_n_4 ), + .Q(TimeCounter_reg[11]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[12] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[12]_i_1_n_7 ), + .Q(TimeCounter_reg[12]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[12]_i_1 + (.CI(\TimeCounter_reg[8]_i_1_n_0 ), + .CO({\TimeCounter_reg[12]_i_1_n_0 ,\TimeCounter_reg[12]_i_1_n_1 ,\TimeCounter_reg[12]_i_1_n_2 ,\TimeCounter_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[12]_i_1_n_4 ,\TimeCounter_reg[12]_i_1_n_5 ,\TimeCounter_reg[12]_i_1_n_6 ,\TimeCounter_reg[12]_i_1_n_7 }), + .S(TimeCounter_reg[15:12])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[13] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[12]_i_1_n_6 ), + .Q(TimeCounter_reg[13]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[14] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[12]_i_1_n_5 ), + .Q(TimeCounter_reg[14]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[15] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[12]_i_1_n_4 ), + .Q(TimeCounter_reg[15]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[16] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[16]_i_1_n_7 ), + .Q(TimeCounter_reg[16]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[16]_i_1 + (.CI(\TimeCounter_reg[12]_i_1_n_0 ), + .CO({\TimeCounter_reg[16]_i_1_n_0 ,\TimeCounter_reg[16]_i_1_n_1 ,\TimeCounter_reg[16]_i_1_n_2 ,\TimeCounter_reg[16]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[16]_i_1_n_4 ,\TimeCounter_reg[16]_i_1_n_5 ,\TimeCounter_reg[16]_i_1_n_6 ,\TimeCounter_reg[16]_i_1_n_7 }), + .S(TimeCounter_reg[19:16])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[17] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[16]_i_1_n_6 ), + .Q(TimeCounter_reg[17]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[18] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[16]_i_1_n_5 ), + .Q(TimeCounter_reg[18]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[19] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[16]_i_1_n_4 ), + .Q(TimeCounter_reg[19]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[1] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[0]_i_1_n_6 ), + .Q(TimeCounter_reg[1]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[20] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[20]_i_1_n_7 ), + .Q(TimeCounter_reg[20]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[20]_i_1 + (.CI(\TimeCounter_reg[16]_i_1_n_0 ), + .CO({\TimeCounter_reg[20]_i_1_n_0 ,\TimeCounter_reg[20]_i_1_n_1 ,\TimeCounter_reg[20]_i_1_n_2 ,\TimeCounter_reg[20]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[20]_i_1_n_4 ,\TimeCounter_reg[20]_i_1_n_5 ,\TimeCounter_reg[20]_i_1_n_6 ,\TimeCounter_reg[20]_i_1_n_7 }), + .S(TimeCounter_reg[23:20])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[21] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[20]_i_1_n_6 ), + .Q(TimeCounter_reg[21]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[22] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[20]_i_1_n_5 ), + .Q(TimeCounter_reg[22]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[23] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[20]_i_1_n_4 ), + .Q(TimeCounter_reg[23]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[24] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[24]_i_1_n_7 ), + .Q(TimeCounter_reg[24]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[24]_i_1 + (.CI(\TimeCounter_reg[20]_i_1_n_0 ), + .CO({\TimeCounter_reg[24]_i_1_n_0 ,\TimeCounter_reg[24]_i_1_n_1 ,\TimeCounter_reg[24]_i_1_n_2 ,\TimeCounter_reg[24]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[24]_i_1_n_4 ,\TimeCounter_reg[24]_i_1_n_5 ,\TimeCounter_reg[24]_i_1_n_6 ,\TimeCounter_reg[24]_i_1_n_7 }), + .S(TimeCounter_reg[27:24])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[25] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[24]_i_1_n_6 ), + .Q(TimeCounter_reg[25]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[26] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[24]_i_1_n_5 ), + .Q(TimeCounter_reg[26]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[27] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[24]_i_1_n_4 ), + .Q(TimeCounter_reg[27]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[28] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[28]_i_1_n_7 ), + .Q(TimeCounter_reg[28]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[28]_i_1 + (.CI(\TimeCounter_reg[24]_i_1_n_0 ), + .CO({\NLW_TimeCounter_reg[28]_i_1_CO_UNCONNECTED [3],\TimeCounter_reg[28]_i_1_n_1 ,\TimeCounter_reg[28]_i_1_n_2 ,\TimeCounter_reg[28]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[28]_i_1_n_4 ,\TimeCounter_reg[28]_i_1_n_5 ,\TimeCounter_reg[28]_i_1_n_6 ,\TimeCounter_reg[28]_i_1_n_7 }), + .S(TimeCounter_reg[31:28])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[29] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[28]_i_1_n_6 ), + .Q(TimeCounter_reg[29]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[2] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[0]_i_1_n_5 ), + .Q(TimeCounter_reg[2]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[30] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[28]_i_1_n_5 ), + .Q(TimeCounter_reg[30]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[31] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[28]_i_1_n_4 ), + .Q(TimeCounter_reg[31]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[3] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[0]_i_1_n_4 ), + .Q(TimeCounter_reg[3]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[4] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[4]_i_1_n_7 ), + .Q(TimeCounter_reg[4]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[4]_i_1 + (.CI(\TimeCounter_reg[0]_i_1_n_0 ), + .CO({\TimeCounter_reg[4]_i_1_n_0 ,\TimeCounter_reg[4]_i_1_n_1 ,\TimeCounter_reg[4]_i_1_n_2 ,\TimeCounter_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[4]_i_1_n_4 ,\TimeCounter_reg[4]_i_1_n_5 ,\TimeCounter_reg[4]_i_1_n_6 ,\TimeCounter_reg[4]_i_1_n_7 }), + .S(TimeCounter_reg[7:4])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[5] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[4]_i_1_n_6 ), + .Q(TimeCounter_reg[5]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[6] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[4]_i_1_n_5 ), + .Q(TimeCounter_reg[6]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[7] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[4]_i_1_n_4 ), + .Q(TimeCounter_reg[7]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[8] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[8]_i_1_n_7 ), + .Q(TimeCounter_reg[8]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[8]_i_1 + (.CI(\TimeCounter_reg[4]_i_1_n_0 ), + .CO({\TimeCounter_reg[8]_i_1_n_0 ,\TimeCounter_reg[8]_i_1_n_1 ,\TimeCounter_reg[8]_i_1_n_2 ,\TimeCounter_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[8]_i_1_n_4 ,\TimeCounter_reg[8]_i_1_n_5 ,\TimeCounter_reg[8]_i_1_n_6 ,\TimeCounter_reg[8]_i_1_n_7 }), + .S(TimeCounter_reg[11:8])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[9] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[8]_i_1_n_6 ), + .Q(TimeCounter_reg[9]), + .R(deadTimeCounterReset_reg_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFE0000000E)) + deadTimeCounterReset_i_1 + (.I0(deadTimeCounterReset_i_2_n_0), + .I1(\FSM_onehot_lineconfig[6]_i_4_n_0 ), + .I2(reset), + .I3(breaking_en), + .I4(deadTimeCounterReset_i_3_n_0), + .I5(deadTimeCounterReset_reg_n_0), + .O(deadTimeCounterReset_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'hFE)) + deadTimeCounterReset_i_2 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .O(deadTimeCounterReset_i_2_n_0)); + LUT6 #( + .INIT(64'h0000000022220020)) + deadTimeCounterReset_i_3 + (.I0(deadTimeCounterReset_i_4_n_0), + .I1(deadTimeCounterReset_i_2_n_0), + .I2(deadTimeCounterReset_i_5_n_0), + .I3(deadTimeCounterReset_i_6_n_0), + .I4(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I5(deadTimeCounterReset_i_7_n_0), + .O(deadTimeCounterReset_i_3_n_0)); + LUT6 #( + .INIT(64'h555D555555555555)) + deadTimeCounterReset_i_4 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I1(deadTimeOK), + .I2(TKin1), + .I3(TKin1_triggered), + .I4(TKin0), + .I5(TKin0_triggered), + .O(deadTimeCounterReset_i_4_n_0)); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT3 #( + .INIT(8'h08)) + deadTimeCounterReset_i_5 + (.I0(deadTimeOK), + .I1(ready), + .I2(er), + .O(deadTimeCounterReset_i_5_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT4 #( + .INIT(16'hF777)) + deadTimeCounterReset_i_6 + (.I0(TKin0), + .I1(TKin1), + .I2(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I3(deadTimeCounterReset_reg_n_0), + .O(deadTimeCounterReset_i_6_n_0)); + LUT6 #( + .INIT(64'hAAAAA2AAAAAAAAAA)) + deadTimeCounterReset_i_7 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I1(TKin1), + .I2(TKin0), + .I3(deadTimeOK), + .I4(TKin0_triggered), + .I5(TKin1_triggered), + .O(deadTimeCounterReset_i_7_n_0)); + FDRE #( + .INIT(1'b0)) + deadTimeCounterReset_reg + (.C(externalCLK), + .CE(1'b1), + .D(deadTimeCounterReset_i_1_n_0), + .Q(deadTimeCounterReset_reg_n_0), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT3 #( + .INIT(8'h0D)) + deadTimeOK_i_1 + (.I0(sel), + .I1(deadTimeOK), + .I2(deadTimeCounterReset_reg_n_0), + .O(deadTimeOK_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + deadTimeOK_reg + (.C(externalCLK), + .CE(1'b1), + .D(deadTimeOK_i_1_n_0), + .Q(deadTimeOK), + .R(1'b0)); + LUT6 #( + .INIT(64'hDDDDDDD0DDDDDDDD)) + key1_i_1 + (.I0(breaking_en), + .I1(TKin0), + .I2(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I4(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I5(key1_i_2_n_0), + .O(key1_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT4 #( + .INIT(16'h0001)) + key1_i_2 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I3(breaking_en), + .O(key1_i_2_n_0)); + FDRE #( + .INIT(1'b1)) + key1_prev_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key1_reg_n_0), + .Q(key1_prev), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + key1_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key1_i_1_n_0), + .Q(key1_reg_n_0), + .R(1'b0)); + LUT1 #( + .INIT(2'h1)) + key2_i_1 + (.I0(reset), + .O(p_0_in)); + LUT6 #( + .INIT(64'hAAAAAAAAFFFFFFFC)) + key2_i_2 + (.I0(TKin1), + .I1(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I4(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I5(breaking_en), + .O(key2_i_2_n_0)); + FDRE #( + .INIT(1'b1)) + key2_prev_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key2_reg_n_0), + .Q(key2_prev), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + key2_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key2_i_2_n_0), + .Q(key2_reg_n_0), + .R(1'b0)); + LUT6 #( + .INIT(64'hAAAAFFFFAAAAFCFF)) + key3_i_1 + (.I0(key3_reg_n_0), + .I1(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I3(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I4(reset), + .I5(breaking_en), + .O(key3_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + key3_prev_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key3_reg_n_0), + .Q(key3_prev), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + key3_reg + (.C(externalCLK), + .CE(1'b1), + .D(key3_i_1_n_0), + .Q(key3_reg_n_0), + .R(1'b0)); + LUT6 #( + .INIT(64'hAAAAFFFFAAAAFFFC)) + key4_i_1 + (.I0(key4_reg_n_0), + .I1(key3), + .I2(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I4(reset), + .I5(breaking_en), + .O(key4_i_1_n_0)); + LUT4 #( + .INIT(16'hFFFE)) + key4_i_2 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .O(key3)); + FDRE #( + .INIT(1'b1)) + key4_prev_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key4_reg_n_0), + .Q(key4_prev), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + key4_reg + (.C(externalCLK), + .CE(1'b1), + .D(key4_i_1_n_0), + .Q(key4_reg_n_0), + .R(1'b0)); + CARRY4 ltOp__15_carry + (.CI(1'b0), + .CO({ltOp__15_carry_n_0,ltOp__15_carry_n_1,ltOp__15_carry_n_2,ltOp__15_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp__15_carry_i_1_n_0,ltOp__15_carry_i_2_n_0,ltOp__15_carry_i_3_n_0,ltOp__15_carry_i_4_n_0}), + .O(NLW_ltOp__15_carry_O_UNCONNECTED[3:0]), + .S({ltOp__15_carry_i_5_n_0,ltOp__15_carry_i_6_n_0,ltOp__15_carry_i_7_n_0,ltOp__15_carry_i_8_n_0})); + CARRY4 ltOp__15_carry__0 + (.CI(ltOp__15_carry_n_0), + .CO({ltOp__15_carry__0_n_0,ltOp__15_carry__0_n_1,ltOp__15_carry__0_n_2,ltOp__15_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp__15_carry__0_i_1_n_0,ltOp__15_carry__0_i_2_n_0,ltOp__15_carry__0_i_3_n_0,ltOp__15_carry__0_i_4_n_0}), + .O(NLW_ltOp__15_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp__15_carry__0_i_5_n_0,ltOp__15_carry__0_i_6_n_0,ltOp__15_carry__0_i_7_n_0,ltOp__15_carry__0_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__0_i_1 + (.I0(minTime[15]), + .I1(minTimeCounter_low_reg[15]), + .I2(minTime[14]), + .I3(minTimeCounter_low_reg[14]), + .O(ltOp__15_carry__0_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__0_i_2 + (.I0(minTime[13]), + .I1(minTimeCounter_low_reg[13]), + .I2(minTime[12]), + .I3(minTimeCounter_low_reg[12]), + .O(ltOp__15_carry__0_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__0_i_3 + (.I0(minTime[11]), + .I1(minTimeCounter_low_reg[11]), + .I2(minTime[10]), + .I3(minTimeCounter_low_reg[10]), + .O(ltOp__15_carry__0_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__0_i_4 + (.I0(minTime[9]), + .I1(minTimeCounter_low_reg[9]), + .I2(minTime[8]), + .I3(minTimeCounter_low_reg[8]), + .O(ltOp__15_carry__0_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__0_i_5 + (.I0(minTimeCounter_low_reg[15]), + .I1(minTime[15]), + .I2(minTimeCounter_low_reg[14]), + .I3(minTime[14]), + .O(ltOp__15_carry__0_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__0_i_6 + (.I0(minTimeCounter_low_reg[13]), + .I1(minTime[13]), + .I2(minTimeCounter_low_reg[12]), + .I3(minTime[12]), + .O(ltOp__15_carry__0_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__0_i_7 + (.I0(minTimeCounter_low_reg[11]), + .I1(minTime[11]), + .I2(minTimeCounter_low_reg[10]), + .I3(minTime[10]), + .O(ltOp__15_carry__0_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__0_i_8 + (.I0(minTimeCounter_low_reg[9]), + .I1(minTime[9]), + .I2(minTimeCounter_low_reg[8]), + .I3(minTime[8]), + .O(ltOp__15_carry__0_i_8_n_0)); + CARRY4 ltOp__15_carry__1 + (.CI(ltOp__15_carry__0_n_0), + .CO({ltOp__15_carry__1_n_0,ltOp__15_carry__1_n_1,ltOp__15_carry__1_n_2,ltOp__15_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp__15_carry__1_i_1_n_0,ltOp__15_carry__1_i_2_n_0,ltOp__15_carry__1_i_3_n_0,ltOp__15_carry__1_i_4_n_0}), + .O(NLW_ltOp__15_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp__15_carry__1_i_5_n_0,ltOp__15_carry__1_i_6_n_0,ltOp__15_carry__1_i_7_n_0,ltOp__15_carry__1_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__1_i_1 + (.I0(minTime[23]), + .I1(minTimeCounter_low_reg[23]), + .I2(minTime[22]), + .I3(minTimeCounter_low_reg[22]), + .O(ltOp__15_carry__1_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__1_i_2 + (.I0(minTime[21]), + .I1(minTimeCounter_low_reg[21]), + .I2(minTime[20]), + .I3(minTimeCounter_low_reg[20]), + .O(ltOp__15_carry__1_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__1_i_3 + (.I0(minTime[19]), + .I1(minTimeCounter_low_reg[19]), + .I2(minTime[18]), + .I3(minTimeCounter_low_reg[18]), + .O(ltOp__15_carry__1_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__1_i_4 + (.I0(minTime[17]), + .I1(minTimeCounter_low_reg[17]), + .I2(minTime[16]), + .I3(minTimeCounter_low_reg[16]), + .O(ltOp__15_carry__1_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__1_i_5 + (.I0(minTimeCounter_low_reg[23]), + .I1(minTime[23]), + .I2(minTimeCounter_low_reg[22]), + .I3(minTime[22]), + .O(ltOp__15_carry__1_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__1_i_6 + (.I0(minTimeCounter_low_reg[21]), + .I1(minTime[21]), + .I2(minTimeCounter_low_reg[20]), + .I3(minTime[20]), + .O(ltOp__15_carry__1_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__1_i_7 + (.I0(minTimeCounter_low_reg[19]), + .I1(minTime[19]), + .I2(minTimeCounter_low_reg[18]), + .I3(minTime[18]), + .O(ltOp__15_carry__1_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__1_i_8 + (.I0(minTimeCounter_low_reg[17]), + .I1(minTime[17]), + .I2(minTimeCounter_low_reg[16]), + .I3(minTime[16]), + .O(ltOp__15_carry__1_i_8_n_0)); + CARRY4 ltOp__15_carry__2 + (.CI(ltOp__15_carry__1_n_0), + .CO({ltOp__15_carry__2_n_0,ltOp__15_carry__2_n_1,ltOp__15_carry__2_n_2,ltOp__15_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp__15_carry__2_i_1_n_0,ltOp__15_carry__2_i_2_n_0,ltOp__15_carry__2_i_3_n_0,ltOp__15_carry__2_i_4_n_0}), + .O(NLW_ltOp__15_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp__15_carry__2_i_5_n_0,ltOp__15_carry__2_i_6_n_0,ltOp__15_carry__2_i_7_n_0,ltOp__15_carry__2_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__2_i_1 + (.I0(minTime[31]), + .I1(minTimeCounter_low_reg[31]), + .I2(minTime[30]), + .I3(minTimeCounter_low_reg[30]), + .O(ltOp__15_carry__2_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__2_i_2 + (.I0(minTime[29]), + .I1(minTimeCounter_low_reg[29]), + .I2(minTime[28]), + .I3(minTimeCounter_low_reg[28]), + .O(ltOp__15_carry__2_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__2_i_3 + (.I0(minTime[27]), + .I1(minTimeCounter_low_reg[27]), + .I2(minTime[26]), + .I3(minTimeCounter_low_reg[26]), + .O(ltOp__15_carry__2_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__2_i_4 + (.I0(minTime[25]), + .I1(minTimeCounter_low_reg[25]), + .I2(minTime[24]), + .I3(minTimeCounter_low_reg[24]), + .O(ltOp__15_carry__2_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__2_i_5 + (.I0(minTimeCounter_low_reg[31]), + .I1(minTime[31]), + .I2(minTimeCounter_low_reg[30]), + .I3(minTime[30]), + .O(ltOp__15_carry__2_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__2_i_6 + (.I0(minTimeCounter_low_reg[29]), + .I1(minTime[29]), + .I2(minTimeCounter_low_reg[28]), + .I3(minTime[28]), + .O(ltOp__15_carry__2_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__2_i_7 + (.I0(minTimeCounter_low_reg[27]), + .I1(minTime[27]), + .I2(minTimeCounter_low_reg[26]), + .I3(minTime[26]), + .O(ltOp__15_carry__2_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__2_i_8 + (.I0(minTimeCounter_low_reg[25]), + .I1(minTime[25]), + .I2(minTimeCounter_low_reg[24]), + .I3(minTime[24]), + .O(ltOp__15_carry__2_i_8_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry_i_1 + (.I0(minTime[7]), + .I1(minTimeCounter_low_reg[7]), + .I2(minTime[6]), + .I3(minTimeCounter_low_reg[6]), + .O(ltOp__15_carry_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry_i_2 + (.I0(minTime[5]), + .I1(minTimeCounter_low_reg[5]), + .I2(minTime[4]), + .I3(minTimeCounter_low_reg[4]), + .O(ltOp__15_carry_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry_i_3 + (.I0(minTime[3]), + .I1(minTimeCounter_low_reg[3]), + .I2(minTime[2]), + .I3(minTimeCounter_low_reg[2]), + .O(ltOp__15_carry_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry_i_4 + (.I0(minTime[1]), + .I1(minTimeCounter_low_reg[1]), + .I2(minTime[0]), + .I3(minTimeCounter_low_reg[0]), + .O(ltOp__15_carry_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry_i_5 + (.I0(minTimeCounter_low_reg[7]), + .I1(minTime[7]), + .I2(minTimeCounter_low_reg[6]), + .I3(minTime[6]), + .O(ltOp__15_carry_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry_i_6 + (.I0(minTimeCounter_low_reg[5]), + .I1(minTime[5]), + .I2(minTimeCounter_low_reg[4]), + .I3(minTime[4]), + .O(ltOp__15_carry_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry_i_7 + (.I0(minTimeCounter_low_reg[3]), + .I1(minTime[3]), + .I2(minTimeCounter_low_reg[2]), + .I3(minTime[2]), + .O(ltOp__15_carry_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry_i_8 + (.I0(minTimeCounter_low_reg[1]), + .I1(minTime[1]), + .I2(minTimeCounter_low_reg[0]), + .I3(minTime[0]), + .O(ltOp__15_carry_i_8_n_0)); + CARRY4 ltOp__31_carry + (.CI(1'b0), + .CO({ltOp__31_carry_n_0,ltOp__31_carry_n_1,ltOp__31_carry_n_2,ltOp__31_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp__31_carry_i_1_n_0,ltOp__31_carry_i_2_n_0,ltOp__31_carry_i_3_n_0,ltOp__31_carry_i_4_n_0}), + .O(NLW_ltOp__31_carry_O_UNCONNECTED[3:0]), + .S({ltOp__31_carry_i_5_n_0,ltOp__31_carry_i_6_n_0,ltOp__31_carry_i_7_n_0,ltOp__31_carry_i_8_n_0})); + CARRY4 ltOp__31_carry__0 + (.CI(ltOp__31_carry_n_0), + .CO({ltOp__31_carry__0_n_0,ltOp__31_carry__0_n_1,ltOp__31_carry__0_n_2,ltOp__31_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp__31_carry_i_1__0_n_0,ltOp__31_carry_i_2__0_n_0,ltOp__31_carry_i_3__0_n_0,ltOp__31_carry_i_4__0_n_0}), + .O(NLW_ltOp__31_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp__31_carry_i_5__0_n_0,ltOp__31_carry_i_6__0_n_0,ltOp__31_carry_i_7__0_n_0,ltOp__31_carry_i_8__0_n_0})); + CARRY4 ltOp__31_carry__1 + (.CI(ltOp__31_carry__0_n_0), + .CO({ltOp__31_carry__1_n_0,ltOp__31_carry__1_n_1,ltOp__31_carry__1_n_2,ltOp__31_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp__31_carry_i_1__1_n_0,ltOp__31_carry_i_2__1_n_0,ltOp__31_carry_i_3__1_n_0,ltOp__31_carry_i_4__1_n_0}), + .O(NLW_ltOp__31_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp__31_carry_i_5__1_n_0,ltOp__31_carry_i_6__1_n_0,ltOp__31_carry_i_7__1_n_0,ltOp__31_carry_i_8__1_n_0})); + CARRY4 ltOp__31_carry__2 + (.CI(ltOp__31_carry__1_n_0), + .CO({ltOp__31_carry__2_n_0,ltOp__31_carry__2_n_1,ltOp__31_carry__2_n_2,ltOp__31_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp__31_carry_i_1__2_n_0,ltOp__31_carry_i_2__2_n_0,ltOp__31_carry_i_3__2_n_0,ltOp__31_carry_i_4__2_n_0}), + .O(NLW_ltOp__31_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp__31_carry_i_5__2_n_0,ltOp__31_carry_i_6__2_n_0,ltOp__31_carry_i_7__2_n_0,ltOp__31_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_1 + (.I0(minTime[7]), + .I1(minTimeCounter_high_reg[7]), + .I2(minTime[6]), + .I3(minTimeCounter_high_reg[6]), + .O(ltOp__31_carry_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_1__0 + (.I0(minTime[15]), + .I1(minTimeCounter_high_reg[15]), + .I2(minTime[14]), + .I3(minTimeCounter_high_reg[14]), + .O(ltOp__31_carry_i_1__0_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_1__1 + (.I0(minTime[23]), + .I1(minTimeCounter_high_reg[23]), + .I2(minTime[22]), + .I3(minTimeCounter_high_reg[22]), + .O(ltOp__31_carry_i_1__1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_1__2 + (.I0(minTime[31]), + .I1(minTimeCounter_high_reg[31]), + .I2(minTime[30]), + .I3(minTimeCounter_high_reg[30]), + .O(ltOp__31_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_2 + (.I0(minTime[5]), + .I1(minTimeCounter_high_reg[5]), + .I2(minTime[4]), + .I3(minTimeCounter_high_reg[4]), + .O(ltOp__31_carry_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_2__0 + (.I0(minTime[13]), + .I1(minTimeCounter_high_reg[13]), + .I2(minTime[12]), + .I3(minTimeCounter_high_reg[12]), + .O(ltOp__31_carry_i_2__0_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_2__1 + (.I0(minTime[21]), + .I1(minTimeCounter_high_reg[21]), + .I2(minTime[20]), + .I3(minTimeCounter_high_reg[20]), + .O(ltOp__31_carry_i_2__1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_2__2 + (.I0(minTime[29]), + .I1(minTimeCounter_high_reg[29]), + .I2(minTime[28]), + .I3(minTimeCounter_high_reg[28]), + .O(ltOp__31_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_3 + (.I0(minTime[3]), + .I1(minTimeCounter_high_reg[3]), + .I2(minTime[2]), + .I3(minTimeCounter_high_reg[2]), + .O(ltOp__31_carry_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_3__0 + (.I0(minTime[11]), + .I1(minTimeCounter_high_reg[11]), + .I2(minTime[10]), + .I3(minTimeCounter_high_reg[10]), + .O(ltOp__31_carry_i_3__0_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_3__1 + (.I0(minTime[19]), + .I1(minTimeCounter_high_reg[19]), + .I2(minTime[18]), + .I3(minTimeCounter_high_reg[18]), + .O(ltOp__31_carry_i_3__1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_3__2 + (.I0(minTime[27]), + .I1(minTimeCounter_high_reg[27]), + .I2(minTime[26]), + .I3(minTimeCounter_high_reg[26]), + .O(ltOp__31_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_4 + (.I0(minTime[1]), + .I1(minTimeCounter_high_reg[1]), + .I2(minTime[0]), + .I3(minTimeCounter_high_reg[0]), + .O(ltOp__31_carry_i_4_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_4__0 + (.I0(minTime[9]), + .I1(minTimeCounter_high_reg[9]), + .I2(minTime[8]), + .I3(minTimeCounter_high_reg[8]), + .O(ltOp__31_carry_i_4__0_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_4__1 + (.I0(minTime[17]), + .I1(minTimeCounter_high_reg[17]), + .I2(minTime[16]), + .I3(minTimeCounter_high_reg[16]), + .O(ltOp__31_carry_i_4__1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_4__2 + (.I0(minTime[25]), + .I1(minTimeCounter_high_reg[25]), + .I2(minTime[24]), + .I3(minTimeCounter_high_reg[24]), + .O(ltOp__31_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_5 + (.I0(minTimeCounter_high_reg[7]), + .I1(minTime[7]), + .I2(minTimeCounter_high_reg[6]), + .I3(minTime[6]), + .O(ltOp__31_carry_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_5__0 + (.I0(minTimeCounter_high_reg[15]), + .I1(minTime[15]), + .I2(minTimeCounter_high_reg[14]), + .I3(minTime[14]), + .O(ltOp__31_carry_i_5__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_5__1 + (.I0(minTimeCounter_high_reg[23]), + .I1(minTime[23]), + .I2(minTimeCounter_high_reg[22]), + .I3(minTime[22]), + .O(ltOp__31_carry_i_5__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_5__2 + (.I0(minTimeCounter_high_reg[31]), + .I1(minTime[31]), + .I2(minTimeCounter_high_reg[30]), + .I3(minTime[30]), + .O(ltOp__31_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_6 + (.I0(minTimeCounter_high_reg[5]), + .I1(minTime[5]), + .I2(minTimeCounter_high_reg[4]), + .I3(minTime[4]), + .O(ltOp__31_carry_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_6__0 + (.I0(minTimeCounter_high_reg[13]), + .I1(minTime[13]), + .I2(minTimeCounter_high_reg[12]), + .I3(minTime[12]), + .O(ltOp__31_carry_i_6__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_6__1 + (.I0(minTimeCounter_high_reg[21]), + .I1(minTime[21]), + .I2(minTimeCounter_high_reg[20]), + .I3(minTime[20]), + .O(ltOp__31_carry_i_6__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_6__2 + (.I0(minTimeCounter_high_reg[29]), + .I1(minTime[29]), + .I2(minTimeCounter_high_reg[28]), + .I3(minTime[28]), + .O(ltOp__31_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_7 + (.I0(minTimeCounter_high_reg[3]), + .I1(minTime[3]), + .I2(minTimeCounter_high_reg[2]), + .I3(minTime[2]), + .O(ltOp__31_carry_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_7__0 + (.I0(minTimeCounter_high_reg[11]), + .I1(minTime[11]), + .I2(minTimeCounter_high_reg[10]), + .I3(minTime[10]), + .O(ltOp__31_carry_i_7__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_7__1 + (.I0(minTimeCounter_high_reg[19]), + .I1(minTime[19]), + .I2(minTimeCounter_high_reg[18]), + .I3(minTime[18]), + .O(ltOp__31_carry_i_7__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_7__2 + (.I0(minTimeCounter_high_reg[27]), + .I1(minTime[27]), + .I2(minTimeCounter_high_reg[26]), + .I3(minTime[26]), + .O(ltOp__31_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_8 + (.I0(minTimeCounter_high_reg[1]), + .I1(minTime[1]), + .I2(minTimeCounter_high_reg[0]), + .I3(minTime[0]), + .O(ltOp__31_carry_i_8_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_8__0 + (.I0(minTimeCounter_high_reg[9]), + .I1(minTime[9]), + .I2(minTimeCounter_high_reg[8]), + .I3(minTime[8]), + .O(ltOp__31_carry_i_8__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_8__1 + (.I0(minTimeCounter_high_reg[17]), + .I1(minTime[17]), + .I2(minTimeCounter_high_reg[16]), + .I3(minTime[16]), + .O(ltOp__31_carry_i_8__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_8__2 + (.I0(minTimeCounter_high_reg[25]), + .I1(minTime[25]), + .I2(minTimeCounter_high_reg[24]), + .I3(minTime[24]), + .O(ltOp__31_carry_i_8__2_n_0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry__0_i_1_n_0,ltOp_carry__0_i_2_n_0,ltOp_carry__0_i_3_n_0,ltOp_carry__0_i_4_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry__0_i_5_n_0,ltOp_carry__0_i_6_n_0,ltOp_carry__0_i_7_n_0,ltOp_carry__0_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__0_i_1 + (.I0(deadTime[15]), + .I1(TimeCounter_reg[15]), + .I2(deadTime[14]), + .I3(TimeCounter_reg[14]), + .O(ltOp_carry__0_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__0_i_2 + (.I0(deadTime[13]), + .I1(TimeCounter_reg[13]), + .I2(deadTime[12]), + .I3(TimeCounter_reg[12]), + .O(ltOp_carry__0_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__0_i_3 + (.I0(deadTime[11]), + .I1(TimeCounter_reg[11]), + .I2(deadTime[10]), + .I3(TimeCounter_reg[10]), + .O(ltOp_carry__0_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__0_i_4 + (.I0(deadTime[9]), + .I1(TimeCounter_reg[9]), + .I2(deadTime[8]), + .I3(TimeCounter_reg[8]), + .O(ltOp_carry__0_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__0_i_5 + (.I0(TimeCounter_reg[15]), + .I1(deadTime[15]), + .I2(TimeCounter_reg[14]), + .I3(deadTime[14]), + .O(ltOp_carry__0_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__0_i_6 + (.I0(TimeCounter_reg[13]), + .I1(deadTime[13]), + .I2(TimeCounter_reg[12]), + .I3(deadTime[12]), + .O(ltOp_carry__0_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__0_i_7 + (.I0(TimeCounter_reg[11]), + .I1(deadTime[11]), + .I2(TimeCounter_reg[10]), + .I3(deadTime[10]), + .O(ltOp_carry__0_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__0_i_8 + (.I0(TimeCounter_reg[9]), + .I1(deadTime[9]), + .I2(TimeCounter_reg[8]), + .I3(deadTime[8]), + .O(ltOp_carry__0_i_8_n_0)); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry__1_i_1_n_0,ltOp_carry__1_i_2_n_0,ltOp_carry__1_i_3_n_0,ltOp_carry__1_i_4_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry__1_i_5_n_0,ltOp_carry__1_i_6_n_0,ltOp_carry__1_i_7_n_0,ltOp_carry__1_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__1_i_1 + (.I0(deadTime[23]), + .I1(TimeCounter_reg[23]), + .I2(deadTime[22]), + .I3(TimeCounter_reg[22]), + .O(ltOp_carry__1_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__1_i_2 + (.I0(deadTime[21]), + .I1(TimeCounter_reg[21]), + .I2(deadTime[20]), + .I3(TimeCounter_reg[20]), + .O(ltOp_carry__1_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__1_i_3 + (.I0(deadTime[19]), + .I1(TimeCounter_reg[19]), + .I2(deadTime[18]), + .I3(TimeCounter_reg[18]), + .O(ltOp_carry__1_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__1_i_4 + (.I0(deadTime[17]), + .I1(TimeCounter_reg[17]), + .I2(deadTime[16]), + .I3(TimeCounter_reg[16]), + .O(ltOp_carry__1_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__1_i_5 + (.I0(TimeCounter_reg[23]), + .I1(deadTime[23]), + .I2(TimeCounter_reg[22]), + .I3(deadTime[22]), + .O(ltOp_carry__1_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__1_i_6 + (.I0(TimeCounter_reg[21]), + .I1(deadTime[21]), + .I2(TimeCounter_reg[20]), + .I3(deadTime[20]), + .O(ltOp_carry__1_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__1_i_7 + (.I0(TimeCounter_reg[19]), + .I1(deadTime[19]), + .I2(TimeCounter_reg[18]), + .I3(deadTime[18]), + .O(ltOp_carry__1_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__1_i_8 + (.I0(TimeCounter_reg[17]), + .I1(deadTime[17]), + .I2(TimeCounter_reg[16]), + .I3(deadTime[16]), + .O(ltOp_carry__1_i_8_n_0)); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({sel,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry__2_i_1_n_0,ltOp_carry__2_i_2_n_0,ltOp_carry__2_i_3_n_0,ltOp_carry__2_i_4_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry__2_i_5_n_0,ltOp_carry__2_i_6_n_0,ltOp_carry__2_i_7_n_0,ltOp_carry__2_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__2_i_1 + (.I0(deadTime[31]), + .I1(TimeCounter_reg[31]), + .I2(deadTime[30]), + .I3(TimeCounter_reg[30]), + .O(ltOp_carry__2_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__2_i_2 + (.I0(deadTime[29]), + .I1(TimeCounter_reg[29]), + .I2(deadTime[28]), + .I3(TimeCounter_reg[28]), + .O(ltOp_carry__2_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__2_i_3 + (.I0(deadTime[27]), + .I1(TimeCounter_reg[27]), + .I2(deadTime[26]), + .I3(TimeCounter_reg[26]), + .O(ltOp_carry__2_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__2_i_4 + (.I0(deadTime[25]), + .I1(TimeCounter_reg[25]), + .I2(deadTime[24]), + .I3(TimeCounter_reg[24]), + .O(ltOp_carry__2_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__2_i_5 + (.I0(TimeCounter_reg[31]), + .I1(deadTime[31]), + .I2(TimeCounter_reg[30]), + .I3(deadTime[30]), + .O(ltOp_carry__2_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__2_i_6 + (.I0(TimeCounter_reg[29]), + .I1(deadTime[29]), + .I2(TimeCounter_reg[28]), + .I3(deadTime[28]), + .O(ltOp_carry__2_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__2_i_7 + (.I0(TimeCounter_reg[27]), + .I1(deadTime[27]), + .I2(TimeCounter_reg[26]), + .I3(deadTime[26]), + .O(ltOp_carry__2_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__2_i_8 + (.I0(TimeCounter_reg[25]), + .I1(deadTime[25]), + .I2(TimeCounter_reg[24]), + .I3(deadTime[24]), + .O(ltOp_carry__2_i_8_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry_i_1 + (.I0(deadTime[7]), + .I1(TimeCounter_reg[7]), + .I2(deadTime[6]), + .I3(TimeCounter_reg[6]), + .O(ltOp_carry_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry_i_2 + (.I0(deadTime[5]), + .I1(TimeCounter_reg[5]), + .I2(deadTime[4]), + .I3(TimeCounter_reg[4]), + .O(ltOp_carry_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry_i_3 + (.I0(deadTime[3]), + .I1(TimeCounter_reg[3]), + .I2(deadTime[2]), + .I3(TimeCounter_reg[2]), + .O(ltOp_carry_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry_i_4 + (.I0(deadTime[1]), + .I1(TimeCounter_reg[1]), + .I2(deadTime[0]), + .I3(TimeCounter_reg[0]), + .O(ltOp_carry_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(TimeCounter_reg[7]), + .I1(deadTime[7]), + .I2(TimeCounter_reg[6]), + .I3(deadTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(TimeCounter_reg[5]), + .I1(deadTime[5]), + .I2(TimeCounter_reg[4]), + .I3(deadTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(TimeCounter_reg[3]), + .I1(deadTime[3]), + .I2(TimeCounter_reg[2]), + .I3(deadTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(TimeCounter_reg[1]), + .I1(deadTime[1]), + .I2(TimeCounter_reg[0]), + .I3(deadTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT6 #( + .INIT(64'h0000000022222F22)) + \minTimeCounter_high[0]_i_1 + (.I0(key1_prev), + .I1(key1_reg_n_0), + .I2(key2_reg_n_0), + .I3(key2_prev), + .I4(breaking_en), + .I5(reset), + .O(\minTimeCounter_high[0]_i_1_n_0 )); + LUT2 #( + .INIT(4'h2)) + \minTimeCounter_high[0]_i_2 + (.I0(ltOp__31_carry__2_n_0), + .I1(reset), + .O(minTimeCounter_high)); + LUT1 #( + .INIT(2'h1)) + \minTimeCounter_high[0]_i_4 + (.I0(minTimeCounter_high_reg[0]), + .O(\minTimeCounter_high[0]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[0] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[0]_i_3_n_7 ), + .Q(minTimeCounter_high_reg[0]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[0]_i_3 + (.CI(1'b0), + .CO({\minTimeCounter_high_reg[0]_i_3_n_0 ,\minTimeCounter_high_reg[0]_i_3_n_1 ,\minTimeCounter_high_reg[0]_i_3_n_2 ,\minTimeCounter_high_reg[0]_i_3_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\minTimeCounter_high_reg[0]_i_3_n_4 ,\minTimeCounter_high_reg[0]_i_3_n_5 ,\minTimeCounter_high_reg[0]_i_3_n_6 ,\minTimeCounter_high_reg[0]_i_3_n_7 }), + .S({minTimeCounter_high_reg[3:1],\minTimeCounter_high[0]_i_4_n_0 })); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[10] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[8]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[10]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[11] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[8]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[11]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[12] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[12]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[12]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[12]_i_1 + (.CI(\minTimeCounter_high_reg[8]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[12]_i_1_n_0 ,\minTimeCounter_high_reg[12]_i_1_n_1 ,\minTimeCounter_high_reg[12]_i_1_n_2 ,\minTimeCounter_high_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[12]_i_1_n_4 ,\minTimeCounter_high_reg[12]_i_1_n_5 ,\minTimeCounter_high_reg[12]_i_1_n_6 ,\minTimeCounter_high_reg[12]_i_1_n_7 }), + .S(minTimeCounter_high_reg[15:12])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[13] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[12]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[13]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[14] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[12]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[14]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[15] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[12]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[15]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[16] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[16]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[16]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[16]_i_1 + (.CI(\minTimeCounter_high_reg[12]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[16]_i_1_n_0 ,\minTimeCounter_high_reg[16]_i_1_n_1 ,\minTimeCounter_high_reg[16]_i_1_n_2 ,\minTimeCounter_high_reg[16]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[16]_i_1_n_4 ,\minTimeCounter_high_reg[16]_i_1_n_5 ,\minTimeCounter_high_reg[16]_i_1_n_6 ,\minTimeCounter_high_reg[16]_i_1_n_7 }), + .S(minTimeCounter_high_reg[19:16])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[17] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[16]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[17]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[18] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[16]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[18]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[19] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[16]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[19]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[1] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[0]_i_3_n_6 ), + .Q(minTimeCounter_high_reg[1]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[20] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[20]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[20]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[20]_i_1 + (.CI(\minTimeCounter_high_reg[16]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[20]_i_1_n_0 ,\minTimeCounter_high_reg[20]_i_1_n_1 ,\minTimeCounter_high_reg[20]_i_1_n_2 ,\minTimeCounter_high_reg[20]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[20]_i_1_n_4 ,\minTimeCounter_high_reg[20]_i_1_n_5 ,\minTimeCounter_high_reg[20]_i_1_n_6 ,\minTimeCounter_high_reg[20]_i_1_n_7 }), + .S(minTimeCounter_high_reg[23:20])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[21] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[20]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[21]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[22] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[20]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[22]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[23] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[20]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[23]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[24] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[24]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[24]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[24]_i_1 + (.CI(\minTimeCounter_high_reg[20]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[24]_i_1_n_0 ,\minTimeCounter_high_reg[24]_i_1_n_1 ,\minTimeCounter_high_reg[24]_i_1_n_2 ,\minTimeCounter_high_reg[24]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[24]_i_1_n_4 ,\minTimeCounter_high_reg[24]_i_1_n_5 ,\minTimeCounter_high_reg[24]_i_1_n_6 ,\minTimeCounter_high_reg[24]_i_1_n_7 }), + .S(minTimeCounter_high_reg[27:24])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[25] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[24]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[25]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[26] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[24]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[26]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[27] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[24]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[27]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[28] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[28]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[28]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[28]_i_1 + (.CI(\minTimeCounter_high_reg[24]_i_1_n_0 ), + .CO({\NLW_minTimeCounter_high_reg[28]_i_1_CO_UNCONNECTED [3],\minTimeCounter_high_reg[28]_i_1_n_1 ,\minTimeCounter_high_reg[28]_i_1_n_2 ,\minTimeCounter_high_reg[28]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[28]_i_1_n_4 ,\minTimeCounter_high_reg[28]_i_1_n_5 ,\minTimeCounter_high_reg[28]_i_1_n_6 ,\minTimeCounter_high_reg[28]_i_1_n_7 }), + .S(minTimeCounter_high_reg[31:28])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[29] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[28]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[29]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[2] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[0]_i_3_n_5 ), + .Q(minTimeCounter_high_reg[2]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[30] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[28]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[30]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[31] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[28]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[31]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[3] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[0]_i_3_n_4 ), + .Q(minTimeCounter_high_reg[3]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[4] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[4]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[4]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[4]_i_1 + (.CI(\minTimeCounter_high_reg[0]_i_3_n_0 ), + .CO({\minTimeCounter_high_reg[4]_i_1_n_0 ,\minTimeCounter_high_reg[4]_i_1_n_1 ,\minTimeCounter_high_reg[4]_i_1_n_2 ,\minTimeCounter_high_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[4]_i_1_n_4 ,\minTimeCounter_high_reg[4]_i_1_n_5 ,\minTimeCounter_high_reg[4]_i_1_n_6 ,\minTimeCounter_high_reg[4]_i_1_n_7 }), + .S(minTimeCounter_high_reg[7:4])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[5] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[4]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[5]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[6] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[4]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[6]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[7] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[4]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[7]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[8] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[8]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[8]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[8]_i_1 + (.CI(\minTimeCounter_high_reg[4]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[8]_i_1_n_0 ,\minTimeCounter_high_reg[8]_i_1_n_1 ,\minTimeCounter_high_reg[8]_i_1_n_2 ,\minTimeCounter_high_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[8]_i_1_n_4 ,\minTimeCounter_high_reg[8]_i_1_n_5 ,\minTimeCounter_high_reg[8]_i_1_n_6 ,\minTimeCounter_high_reg[8]_i_1_n_7 }), + .S(minTimeCounter_high_reg[11:8])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[9] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[8]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[9]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + LUT5 #( + .INIT(32'h0000440F)) + \minTimeCounter_low[0]_i_1 + (.I0(key2_reg_n_0), + .I1(key2_prev), + .I2(\minTimeCounter_low[0]_i_4_n_0 ), + .I3(breaking_en), + .I4(reset), + .O(\minTimeCounter_low[0]_i_1_n_0 )); + LUT2 #( + .INIT(4'h2)) + \minTimeCounter_low[0]_i_2 + (.I0(ltOp__15_carry__2_n_0), + .I1(reset), + .O(minTimeCounter_low)); + LUT4 #( + .INIT(16'hD0DD)) + \minTimeCounter_low[0]_i_4 + (.I0(key4_prev), + .I1(key4_reg_n_0), + .I2(key3_reg_n_0), + .I3(key3_prev), + .O(\minTimeCounter_low[0]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \minTimeCounter_low[0]_i_5 + (.I0(minTimeCounter_low_reg[0]), + .O(\minTimeCounter_low[0]_i_5_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[0] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[0]_i_3_n_7 ), + .Q(minTimeCounter_low_reg[0]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[0]_i_3 + (.CI(1'b0), + .CO({\minTimeCounter_low_reg[0]_i_3_n_0 ,\minTimeCounter_low_reg[0]_i_3_n_1 ,\minTimeCounter_low_reg[0]_i_3_n_2 ,\minTimeCounter_low_reg[0]_i_3_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\minTimeCounter_low_reg[0]_i_3_n_4 ,\minTimeCounter_low_reg[0]_i_3_n_5 ,\minTimeCounter_low_reg[0]_i_3_n_6 ,\minTimeCounter_low_reg[0]_i_3_n_7 }), + .S({minTimeCounter_low_reg[3:1],\minTimeCounter_low[0]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[10] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[8]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[10]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[11] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[8]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[11]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[12] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[12]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[12]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[12]_i_1 + (.CI(\minTimeCounter_low_reg[8]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[12]_i_1_n_0 ,\minTimeCounter_low_reg[12]_i_1_n_1 ,\minTimeCounter_low_reg[12]_i_1_n_2 ,\minTimeCounter_low_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[12]_i_1_n_4 ,\minTimeCounter_low_reg[12]_i_1_n_5 ,\minTimeCounter_low_reg[12]_i_1_n_6 ,\minTimeCounter_low_reg[12]_i_1_n_7 }), + .S(minTimeCounter_low_reg[15:12])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[13] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[12]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[13]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[14] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[12]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[14]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[15] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[12]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[15]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[16] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[16]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[16]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[16]_i_1 + (.CI(\minTimeCounter_low_reg[12]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[16]_i_1_n_0 ,\minTimeCounter_low_reg[16]_i_1_n_1 ,\minTimeCounter_low_reg[16]_i_1_n_2 ,\minTimeCounter_low_reg[16]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[16]_i_1_n_4 ,\minTimeCounter_low_reg[16]_i_1_n_5 ,\minTimeCounter_low_reg[16]_i_1_n_6 ,\minTimeCounter_low_reg[16]_i_1_n_7 }), + .S(minTimeCounter_low_reg[19:16])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[17] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[16]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[17]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[18] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[16]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[18]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[19] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[16]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[19]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[1] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[0]_i_3_n_6 ), + .Q(minTimeCounter_low_reg[1]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[20] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[20]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[20]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[20]_i_1 + (.CI(\minTimeCounter_low_reg[16]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[20]_i_1_n_0 ,\minTimeCounter_low_reg[20]_i_1_n_1 ,\minTimeCounter_low_reg[20]_i_1_n_2 ,\minTimeCounter_low_reg[20]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[20]_i_1_n_4 ,\minTimeCounter_low_reg[20]_i_1_n_5 ,\minTimeCounter_low_reg[20]_i_1_n_6 ,\minTimeCounter_low_reg[20]_i_1_n_7 }), + .S(minTimeCounter_low_reg[23:20])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[21] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[20]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[21]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[22] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[20]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[22]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[23] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[20]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[23]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[24] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[24]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[24]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[24]_i_1 + (.CI(\minTimeCounter_low_reg[20]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[24]_i_1_n_0 ,\minTimeCounter_low_reg[24]_i_1_n_1 ,\minTimeCounter_low_reg[24]_i_1_n_2 ,\minTimeCounter_low_reg[24]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[24]_i_1_n_4 ,\minTimeCounter_low_reg[24]_i_1_n_5 ,\minTimeCounter_low_reg[24]_i_1_n_6 ,\minTimeCounter_low_reg[24]_i_1_n_7 }), + .S(minTimeCounter_low_reg[27:24])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[25] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[24]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[25]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[26] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[24]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[26]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[27] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[24]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[27]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[28] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[28]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[28]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[28]_i_1 + (.CI(\minTimeCounter_low_reg[24]_i_1_n_0 ), + .CO({\NLW_minTimeCounter_low_reg[28]_i_1_CO_UNCONNECTED [3],\minTimeCounter_low_reg[28]_i_1_n_1 ,\minTimeCounter_low_reg[28]_i_1_n_2 ,\minTimeCounter_low_reg[28]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[28]_i_1_n_4 ,\minTimeCounter_low_reg[28]_i_1_n_5 ,\minTimeCounter_low_reg[28]_i_1_n_6 ,\minTimeCounter_low_reg[28]_i_1_n_7 }), + .S(minTimeCounter_low_reg[31:28])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[29] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[28]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[29]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[2] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[0]_i_3_n_5 ), + .Q(minTimeCounter_low_reg[2]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[30] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[28]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[30]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[31] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[28]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[31]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[3] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[0]_i_3_n_4 ), + .Q(minTimeCounter_low_reg[3]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[4] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[4]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[4]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[4]_i_1 + (.CI(\minTimeCounter_low_reg[0]_i_3_n_0 ), + .CO({\minTimeCounter_low_reg[4]_i_1_n_0 ,\minTimeCounter_low_reg[4]_i_1_n_1 ,\minTimeCounter_low_reg[4]_i_1_n_2 ,\minTimeCounter_low_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[4]_i_1_n_4 ,\minTimeCounter_low_reg[4]_i_1_n_5 ,\minTimeCounter_low_reg[4]_i_1_n_6 ,\minTimeCounter_low_reg[4]_i_1_n_7 }), + .S(minTimeCounter_low_reg[7:4])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[5] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[4]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[5]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[6] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[4]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[6]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[7] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[4]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[7]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[8] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[8]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[8]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[8]_i_1 + (.CI(\minTimeCounter_low_reg[4]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[8]_i_1_n_0 ,\minTimeCounter_low_reg[8]_i_1_n_1 ,\minTimeCounter_low_reg[8]_i_1_n_2 ,\minTimeCounter_low_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[8]_i_1_n_4 ,\minTimeCounter_low_reg[8]_i_1_n_5 ,\minTimeCounter_low_reg[8]_i_1_n_6 ,\minTimeCounter_low_reg[8]_i_1_n_7 }), + .S(minTimeCounter_low_reg[11:8])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[9] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[8]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[9]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'hEEFFEEEEE200E2E2)) + minTimeEr_i_1 + (.I0(minTimeEr_i_2_n_0), + .I1(minTimeEr_i_3_n_0), + .I2(minTimeEr_i_4_n_0), + .I3(minTimeEr_i_5_n_0), + .I4(minTimeEr_i_6_n_0), + .I5(minTimeEr_reg_0), + .O(minTimeEr_i_1_n_0)); + LUT4 #( + .INIT(16'h0111)) + minTimeEr_i_2 + (.I0(reset), + .I1(breaking_en), + .I2(minTimeEr_i_6_n_0), + .I3(minTimeEr_i_7_n_0), + .O(minTimeEr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h2)) + minTimeEr_i_3 + (.I0(breaking_en), + .I1(reset), + .O(minTimeEr_i_3_n_0)); + LUT6 #( + .INIT(64'h040404FF00000000)) + minTimeEr_i_4 + (.I0(minTimeOK_low), + .I1(key2_reg_n_0), + .I2(key2_prev), + .I3(minTimeEr_i_8_n_0), + .I4(minTimeOK_high), + .I5(minTime_En), + .O(minTimeEr_i_4_n_0)); + LUT6 #( + .INIT(64'h55555555F755F7F7)) + minTimeEr_i_5 + (.I0(minTimeEr_i_9_n_0), + .I1(key2_prev), + .I2(key2_reg_n_0), + .I3(key1_reg_n_0), + .I4(key1_prev), + .I5(minTimeEr_i_7_n_0), + .O(minTimeEr_i_5_n_0)); + LUT6 #( + .INIT(64'hFBFFFFFFBBFBFBFF)) + minTimeEr_i_6 + (.I0(minTimeOK_low), + .I1(minTime_En), + .I2(key3_prev), + .I3(key3_reg_n_0), + .I4(key4_reg_n_0), + .I5(key4_prev), + .O(minTimeEr_i_6_n_0)); + LUT6 #( + .INIT(64'hFFDFDDDDFFDFFFDF)) + minTimeEr_i_7 + (.I0(minTime_En), + .I1(minTimeOK_high), + .I2(key2_reg_n_0), + .I3(key2_prev), + .I4(key1_prev), + .I5(key1_reg_n_0), + .O(minTimeEr_i_7_n_0)); + LUT2 #( + .INIT(4'hB)) + minTimeEr_i_8 + (.I0(key1_prev), + .I1(key1_reg_n_0), + .O(minTimeEr_i_8_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h1)) + minTimeEr_i_9 + (.I0(breaking_en), + .I1(reset), + .O(minTimeEr_i_9_n_0)); + FDRE #( + .INIT(1'b0)) + minTimeEr_reg + (.C(externalCLK), + .CE(1'b1), + .D(minTimeEr_i_1_n_0), + .Q(minTimeEr_reg_0), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h00AB)) + minTimeOK_high_i_1 + (.I0(minTimeOK_high), + .I1(ltOp__31_carry__2_n_0), + .I2(reset), + .I3(\minTimeCounter_high[0]_i_1_n_0 ), + .O(minTimeOK_high_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + minTimeOK_high_reg + (.C(externalCLK), + .CE(1'b1), + .D(minTimeOK_high_i_1_n_0), + .Q(minTimeOK_high), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'h00AB)) + minTimeOK_low_i_1 + (.I0(minTimeOK_low), + .I1(ltOp__15_carry__2_n_0), + .I2(reset), + .I3(\minTimeCounter_low[0]_i_1_n_0 ), + .O(minTimeOK_low_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + minTimeOK_low_reg + (.C(externalCLK), + .CE(1'b1), + .D(minTimeOK_low_i_1_n_0), + .Q(minTimeOK_low), + .R(1'b0)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.vhdl b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.vhdl new file mode 100644 index 0000000..0d98d04 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.vhdl @@ -0,0 +1,4183 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Fri Jun 11 07:49:57 2021 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top Inverter_3lvl_P0N_3lvl_0_4 -prefix +-- Inverter_3lvl_P0N_3lvl_0_4_ Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.vhdl +-- Design : Inverter_3lvl_P0N_3lvl_0_4 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Inverter_3lvl_P0N_3lvl_0_4_P0N_3lvl is + port ( + minTimeEr_reg_0 : out STD_LOGIC; + PWM_out_0 : out STD_LOGIC; + PWM_out_1 : out STD_LOGIC; + PWM_out_2 : out STD_LOGIC; + PWM_out_3 : out STD_LOGIC; + reset : in STD_LOGIC; + externalCLK : in STD_LOGIC; + TKin0 : in STD_LOGIC; + TKin1 : in STD_LOGIC; + breaking_en : in STD_LOGIC; + er : in STD_LOGIC; + ready : in STD_LOGIC; + minTime_En : in STD_LOGIC; + deadTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + minTime : in STD_LOGIC_VECTOR ( 31 downto 0 ) + ); +end Inverter_3lvl_P0N_3lvl_0_4_P0N_3lvl; + +architecture STRUCTURE of Inverter_3lvl_P0N_3lvl_0_4_P0N_3lvl is + signal \FSM_onehot_lineconfig[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[0]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[1]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[2]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[2]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[3]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[4]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[5]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[5]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[5]_i_3_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_3_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_4_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_5_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_6_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[0]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[1]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[2]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[3]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[4]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[5]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[6]\ : STD_LOGIC; + signal PWM_out_0_i_1_n_0 : STD_LOGIC; + signal PWM_out_1_i_1_n_0 : STD_LOGIC; + signal PWM_out_2_i_1_n_0 : STD_LOGIC; + signal PWM_out_3_i_1_n_0 : STD_LOGIC; + signal TKin0_triggered : STD_LOGIC; + signal TKin0_triggered28_out : STD_LOGIC; + signal TKin0_triggered_i_1_n_0 : STD_LOGIC; + signal TKin1_triggered : STD_LOGIC; + signal TKin1_triggered_i_1_n_0 : STD_LOGIC; + signal \TimeCounter[0]_i_2_n_0\ : STD_LOGIC; + signal TimeCounter_reg : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \TimeCounter_reg[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_7\ : STD_LOGIC; + signal deadTimeCounterReset_i_1_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_2_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_3_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_4_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_5_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_6_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_7_n_0 : STD_LOGIC; + signal deadTimeCounterReset_reg_n_0 : STD_LOGIC; + signal deadTimeOK : STD_LOGIC; + signal deadTimeOK_i_1_n_0 : STD_LOGIC; + signal key1_i_1_n_0 : STD_LOGIC; + signal key1_i_2_n_0 : STD_LOGIC; + signal key1_prev : STD_LOGIC; + signal key1_reg_n_0 : STD_LOGIC; + signal key2_i_2_n_0 : STD_LOGIC; + signal key2_prev : STD_LOGIC; + signal key2_reg_n_0 : STD_LOGIC; + signal key3 : STD_LOGIC; + signal key3_i_1_n_0 : STD_LOGIC; + signal key3_prev : STD_LOGIC; + signal key3_reg_n_0 : STD_LOGIC; + signal key4_i_1_n_0 : STD_LOGIC; + signal key4_prev : STD_LOGIC; + signal key4_reg_n_0 : STD_LOGIC; + signal \ltOp__15_carry__0_i_1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_3_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_4_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_5_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_6_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_7_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_8_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_n_1\ : STD_LOGIC; + signal \ltOp__15_carry__0_n_2\ : STD_LOGIC; + signal \ltOp__15_carry__0_n_3\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_3_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_4_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_5_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_6_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_7_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_8_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_n_1\ : STD_LOGIC; + signal \ltOp__15_carry__1_n_2\ : STD_LOGIC; + signal \ltOp__15_carry__1_n_3\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_3_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_4_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_5_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_6_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_7_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_8_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_n_1\ : STD_LOGIC; + signal \ltOp__15_carry__2_n_2\ : STD_LOGIC; + signal \ltOp__15_carry__2_n_3\ : STD_LOGIC; + signal \ltOp__15_carry_i_1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_3_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_4_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_5_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_6_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_7_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_8_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_n_1\ : STD_LOGIC; + signal \ltOp__15_carry_n_2\ : STD_LOGIC; + signal \ltOp__15_carry_n_3\ : STD_LOGIC; + signal \ltOp__31_carry__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry__0_n_1\ : STD_LOGIC; + signal \ltOp__31_carry__0_n_2\ : STD_LOGIC; + signal \ltOp__31_carry__0_n_3\ : STD_LOGIC; + signal \ltOp__31_carry__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry__1_n_1\ : STD_LOGIC; + signal \ltOp__31_carry__1_n_2\ : STD_LOGIC; + signal \ltOp__31_carry__1_n_3\ : STD_LOGIC; + signal \ltOp__31_carry__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry__2_n_1\ : STD_LOGIC; + signal \ltOp__31_carry__2_n_2\ : STD_LOGIC; + signal \ltOp__31_carry__2_n_3\ : STD_LOGIC; + signal \ltOp__31_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_1__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_2__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_3__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_3_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_4__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_4_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_5__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_5_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_6__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_6_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_7__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_7_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_8__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_8_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_n_1\ : STD_LOGIC; + signal \ltOp__31_carry_n_2\ : STD_LOGIC; + signal \ltOp__31_carry_n_3\ : STD_LOGIC; + signal \ltOp_carry__0_i_1_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_2_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_3_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_4_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_5_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_6_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_7_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_8_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_i_1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_2_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_3_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_4_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_5_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_6_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_7_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_8_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_i_1_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_2_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_3_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_4_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_5_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_6_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_7_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_8_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal minTimeCounter_high : STD_LOGIC; + signal \minTimeCounter_high[0]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high[0]_i_4_n_0\ : STD_LOGIC; + signal minTimeCounter_high_reg : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \minTimeCounter_high_reg[0]_i_3_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_7\ : STD_LOGIC; + signal minTimeCounter_low : STD_LOGIC; + signal \minTimeCounter_low[0]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low[0]_i_4_n_0\ : STD_LOGIC; + signal \minTimeCounter_low[0]_i_5_n_0\ : STD_LOGIC; + signal minTimeCounter_low_reg : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \minTimeCounter_low_reg[0]_i_3_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_7\ : STD_LOGIC; + signal minTimeEr_i_1_n_0 : STD_LOGIC; + signal minTimeEr_i_2_n_0 : STD_LOGIC; + signal minTimeEr_i_3_n_0 : STD_LOGIC; + signal minTimeEr_i_4_n_0 : STD_LOGIC; + signal minTimeEr_i_5_n_0 : STD_LOGIC; + signal minTimeEr_i_6_n_0 : STD_LOGIC; + signal minTimeEr_i_7_n_0 : STD_LOGIC; + signal minTimeEr_i_8_n_0 : STD_LOGIC; + signal minTimeEr_i_9_n_0 : STD_LOGIC; + signal \^mintimeer_reg_0\ : STD_LOGIC; + signal minTimeOK_high : STD_LOGIC; + signal minTimeOK_high_i_1_n_0 : STD_LOGIC; + signal minTimeOK_low : STD_LOGIC; + signal minTimeOK_low_i_1_n_0 : STD_LOGIC; + signal p_0_in : STD_LOGIC; + signal sel : STD_LOGIC; + signal \NLW_TimeCounter_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_ltOp__15_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__15_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__15_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__15_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__31_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__31_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__31_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__31_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_minTimeCounter_high_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_minTimeCounter_low_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[0]_i_2\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[2]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[5]_i_2\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[6]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[6]_i_3\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[6]_i_6\ : label is "soft_lutpair2"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[0]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[1]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[2]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[3]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[4]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[5]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[6]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute SOFT_HLUTNM of PWM_out_0_i_1 : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of PWM_out_1_i_1 : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of deadTimeCounterReset_i_2 : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of deadTimeCounterReset_i_5 : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of deadTimeCounterReset_i_6 : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of deadTimeOK_i_1 : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of key1_i_2 : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of minTimeEr_i_3 : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of minTimeEr_i_9 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of minTimeOK_high_i_1 : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of minTimeOK_low_i_1 : label is "soft_lutpair3"; +begin + minTimeEr_reg_0 <= \^mintimeer_reg_0\; +\FSM_onehot_lineconfig[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFE00000000" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I4 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I5 => \FSM_onehot_lineconfig[0]_i_2_n_0\, + O => \FSM_onehot_lineconfig[0]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[0]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => TKin1, + I1 => TKin0, + O => \FSM_onehot_lineconfig[0]_i_2_n_0\ + ); +\FSM_onehot_lineconfig[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1000FFFF00000000" + ) + port map ( + I0 => TKin1, + I1 => TKin1_triggered, + I2 => TKin0_triggered, + I3 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I4 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I5 => TKin0, + O => \FSM_onehot_lineconfig[1]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00EFEF0F" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I2 => \FSM_onehot_lineconfig[2]_i_2_n_0\, + I3 => TKin0, + I4 => TKin1, + O => \FSM_onehot_lineconfig[2]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"900990099009FFFF" + ) + port map ( + I0 => TKin1, + I1 => TKin1_triggered, + I2 => TKin0, + I3 => TKin0_triggered, + I4 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I5 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + O => \FSM_onehot_lineconfig[2]_i_2_n_0\ + ); +\FSM_onehot_lineconfig[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000055D50000" + ) + port map ( + I0 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I2 => TKin1_triggered, + I3 => TKin0_triggered, + I4 => TKin1, + I5 => TKin0, + O => \FSM_onehot_lineconfig[3]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2230" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I1 => TKin0, + I2 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I3 => TKin1, + O => \FSM_onehot_lineconfig[4]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0CFF0C0D00050005" + ) + port map ( + I0 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I2 => TKin1, + I3 => TKin0, + I4 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I5 => \FSM_onehot_lineconfig[5]_i_3_n_0\, + O => \FSM_onehot_lineconfig[5]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[5]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + O => \FSM_onehot_lineconfig[5]_i_2_n_0\ + ); +\FSM_onehot_lineconfig[5]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TKin0_triggered, + I1 => TKin0, + I2 => TKin1_triggered, + I3 => TKin1, + O => \FSM_onehot_lineconfig[5]_i_3_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => \FSM_onehot_lineconfig[6]_i_3_n_0\, + I1 => \FSM_onehot_lineconfig[6]_i_4_n_0\, + I2 => breaking_en, + O => \FSM_onehot_lineconfig[6]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"5504" + ) + port map ( + I0 => TKin1, + I1 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I2 => TKin0, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + O => \FSM_onehot_lineconfig[6]_i_2_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFEECAE" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I2 => TKin1, + I3 => TKin0, + I4 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + O => \FSM_onehot_lineconfig[6]_i_3_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AABAAAAAFFFFAAAA" + ) + port map ( + I0 => \FSM_onehot_lineconfig[6]_i_5_n_0\, + I1 => er, + I2 => ready, + I3 => \FSM_onehot_lineconfig[6]_i_6_n_0\, + I4 => deadTimeOK, + I5 => \FSM_onehot_lineconfig[2]_i_2_n_0\, + O => \FSM_onehot_lineconfig[6]_i_4_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FC88A0A8" + ) + port map ( + I0 => deadTimeOK, + I1 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I3 => TKin1, + I4 => TKin0, + O => \FSM_onehot_lineconfig[6]_i_5_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF232323" + ) + port map ( + I0 => deadTimeCounterReset_reg_n_0, + I1 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I3 => TKin1, + I4 => TKin0, + O => \FSM_onehot_lineconfig[6]_i_6_n_0\ + ); +\FSM_onehot_lineconfig_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[0]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[0]\, + S => reset + ); +\FSM_onehot_lineconfig_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[1]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[1]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[2]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[2]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[3]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[3]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[4]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[4]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[5]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[5]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[6]_i_2_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[6]\, + R => reset + ); +PWM_out_0_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFEF" + ) + port map ( + I0 => key1_reg_n_0, + I1 => er, + I2 => ready, + I3 => \^mintimeer_reg_0\, + O => PWM_out_0_i_1_n_0 + ); +PWM_out_0_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => PWM_out_0_i_1_n_0, + Q => PWM_out_0, + R => '0' + ); +PWM_out_1_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFEF" + ) + port map ( + I0 => key2_reg_n_0, + I1 => er, + I2 => ready, + I3 => \^mintimeer_reg_0\, + O => PWM_out_1_i_1_n_0 + ); +PWM_out_1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => PWM_out_1_i_1_n_0, + Q => PWM_out_1, + R => '0' + ); +PWM_out_2_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFEF" + ) + port map ( + I0 => key3_reg_n_0, + I1 => \^mintimeer_reg_0\, + I2 => ready, + I3 => er, + I4 => breaking_en, + O => PWM_out_2_i_1_n_0 + ); +PWM_out_2_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => PWM_out_2_i_1_n_0, + Q => PWM_out_2, + R => '0' + ); +PWM_out_3_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFEF" + ) + port map ( + I0 => key4_reg_n_0, + I1 => \^mintimeer_reg_0\, + I2 => ready, + I3 => er, + I4 => breaking_en, + O => PWM_out_3_i_1_n_0 + ); +PWM_out_3_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => PWM_out_3_i_1_n_0, + Q => PWM_out_3, + R => '0' + ); +TKin0_triggered_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA08FFFFAA080000" + ) + port map ( + I0 => TKin0, + I1 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I2 => TKin1, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I4 => TKin0_triggered28_out, + I5 => TKin0_triggered, + O => TKin0_triggered_i_1_n_0 + ); +TKin0_triggered_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => TKin0_triggered_i_1_n_0, + Q => TKin0_triggered, + R => '0' + ); +TKin1_triggered_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA08FFFFAA080000" + ) + port map ( + I0 => TKin1, + I1 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I2 => TKin0, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I4 => TKin0_triggered28_out, + I5 => TKin1_triggered, + O => TKin1_triggered_i_1_n_0 + ); +TKin1_triggered_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"22AA22A820AA2020" + ) + port map ( + I0 => minTimeEr_i_9_n_0, + I1 => TKin1, + I2 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I3 => TKin0, + I4 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I5 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + O => TKin0_triggered28_out + ); +TKin1_triggered_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => TKin1_triggered_i_1_n_0, + Q => TKin1_triggered, + R => '0' + ); +\TimeCounter[0]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => TimeCounter_reg(0), + O => \TimeCounter[0]_i_2_n_0\ + ); +\TimeCounter_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[0]_i_1_n_7\, + Q => TimeCounter_reg(0), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[0]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \TimeCounter_reg[0]_i_1_n_0\, + CO(2) => \TimeCounter_reg[0]_i_1_n_1\, + CO(1) => \TimeCounter_reg[0]_i_1_n_2\, + CO(0) => \TimeCounter_reg[0]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \TimeCounter_reg[0]_i_1_n_4\, + O(2) => \TimeCounter_reg[0]_i_1_n_5\, + O(1) => \TimeCounter_reg[0]_i_1_n_6\, + O(0) => \TimeCounter_reg[0]_i_1_n_7\, + S(3 downto 1) => TimeCounter_reg(3 downto 1), + S(0) => \TimeCounter[0]_i_2_n_0\ + ); +\TimeCounter_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[8]_i_1_n_5\, + Q => TimeCounter_reg(10), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[8]_i_1_n_4\, + Q => TimeCounter_reg(11), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[12]_i_1_n_7\, + Q => TimeCounter_reg(12), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[8]_i_1_n_0\, + CO(3) => \TimeCounter_reg[12]_i_1_n_0\, + CO(2) => \TimeCounter_reg[12]_i_1_n_1\, + CO(1) => \TimeCounter_reg[12]_i_1_n_2\, + CO(0) => \TimeCounter_reg[12]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[12]_i_1_n_4\, + O(2) => \TimeCounter_reg[12]_i_1_n_5\, + O(1) => \TimeCounter_reg[12]_i_1_n_6\, + O(0) => \TimeCounter_reg[12]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(15 downto 12) + ); +\TimeCounter_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[12]_i_1_n_6\, + Q => TimeCounter_reg(13), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[12]_i_1_n_5\, + Q => TimeCounter_reg(14), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[12]_i_1_n_4\, + Q => TimeCounter_reg(15), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[16]_i_1_n_7\, + Q => TimeCounter_reg(16), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[16]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[12]_i_1_n_0\, + CO(3) => \TimeCounter_reg[16]_i_1_n_0\, + CO(2) => \TimeCounter_reg[16]_i_1_n_1\, + CO(1) => \TimeCounter_reg[16]_i_1_n_2\, + CO(0) => \TimeCounter_reg[16]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[16]_i_1_n_4\, + O(2) => \TimeCounter_reg[16]_i_1_n_5\, + O(1) => \TimeCounter_reg[16]_i_1_n_6\, + O(0) => \TimeCounter_reg[16]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(19 downto 16) + ); +\TimeCounter_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[16]_i_1_n_6\, + Q => TimeCounter_reg(17), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[16]_i_1_n_5\, + Q => TimeCounter_reg(18), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[16]_i_1_n_4\, + Q => TimeCounter_reg(19), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[0]_i_1_n_6\, + Q => TimeCounter_reg(1), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[20]_i_1_n_7\, + Q => TimeCounter_reg(20), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[20]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[16]_i_1_n_0\, + CO(3) => \TimeCounter_reg[20]_i_1_n_0\, + CO(2) => \TimeCounter_reg[20]_i_1_n_1\, + CO(1) => \TimeCounter_reg[20]_i_1_n_2\, + CO(0) => \TimeCounter_reg[20]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[20]_i_1_n_4\, + O(2) => \TimeCounter_reg[20]_i_1_n_5\, + O(1) => \TimeCounter_reg[20]_i_1_n_6\, + O(0) => \TimeCounter_reg[20]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(23 downto 20) + ); +\TimeCounter_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[20]_i_1_n_6\, + Q => TimeCounter_reg(21), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[20]_i_1_n_5\, + Q => TimeCounter_reg(22), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[20]_i_1_n_4\, + Q => TimeCounter_reg(23), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[24]_i_1_n_7\, + Q => TimeCounter_reg(24), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[24]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[20]_i_1_n_0\, + CO(3) => \TimeCounter_reg[24]_i_1_n_0\, + CO(2) => \TimeCounter_reg[24]_i_1_n_1\, + CO(1) => \TimeCounter_reg[24]_i_1_n_2\, + CO(0) => \TimeCounter_reg[24]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[24]_i_1_n_4\, + O(2) => \TimeCounter_reg[24]_i_1_n_5\, + O(1) => \TimeCounter_reg[24]_i_1_n_6\, + O(0) => \TimeCounter_reg[24]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(27 downto 24) + ); +\TimeCounter_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[24]_i_1_n_6\, + Q => TimeCounter_reg(25), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[24]_i_1_n_5\, + Q => TimeCounter_reg(26), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[24]_i_1_n_4\, + Q => TimeCounter_reg(27), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[28]_i_1_n_7\, + Q => TimeCounter_reg(28), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[28]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[24]_i_1_n_0\, + CO(3) => \NLW_TimeCounter_reg[28]_i_1_CO_UNCONNECTED\(3), + CO(2) => \TimeCounter_reg[28]_i_1_n_1\, + CO(1) => \TimeCounter_reg[28]_i_1_n_2\, + CO(0) => \TimeCounter_reg[28]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[28]_i_1_n_4\, + O(2) => \TimeCounter_reg[28]_i_1_n_5\, + O(1) => \TimeCounter_reg[28]_i_1_n_6\, + O(0) => \TimeCounter_reg[28]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(31 downto 28) + ); +\TimeCounter_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[28]_i_1_n_6\, + Q => TimeCounter_reg(29), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[0]_i_1_n_5\, + Q => TimeCounter_reg(2), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[28]_i_1_n_5\, + Q => TimeCounter_reg(30), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[28]_i_1_n_4\, + Q => TimeCounter_reg(31), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[0]_i_1_n_4\, + Q => TimeCounter_reg(3), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[4]_i_1_n_7\, + Q => TimeCounter_reg(4), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[0]_i_1_n_0\, + CO(3) => \TimeCounter_reg[4]_i_1_n_0\, + CO(2) => \TimeCounter_reg[4]_i_1_n_1\, + CO(1) => \TimeCounter_reg[4]_i_1_n_2\, + CO(0) => \TimeCounter_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[4]_i_1_n_4\, + O(2) => \TimeCounter_reg[4]_i_1_n_5\, + O(1) => \TimeCounter_reg[4]_i_1_n_6\, + O(0) => \TimeCounter_reg[4]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(7 downto 4) + ); +\TimeCounter_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[4]_i_1_n_6\, + Q => TimeCounter_reg(5), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[4]_i_1_n_5\, + Q => TimeCounter_reg(6), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[4]_i_1_n_4\, + Q => TimeCounter_reg(7), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[8]_i_1_n_7\, + Q => TimeCounter_reg(8), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[4]_i_1_n_0\, + CO(3) => \TimeCounter_reg[8]_i_1_n_0\, + CO(2) => \TimeCounter_reg[8]_i_1_n_1\, + CO(1) => \TimeCounter_reg[8]_i_1_n_2\, + CO(0) => \TimeCounter_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[8]_i_1_n_4\, + O(2) => \TimeCounter_reg[8]_i_1_n_5\, + O(1) => \TimeCounter_reg[8]_i_1_n_6\, + O(0) => \TimeCounter_reg[8]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(11 downto 8) + ); +\TimeCounter_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[8]_i_1_n_6\, + Q => TimeCounter_reg(9), + R => deadTimeCounterReset_reg_n_0 + ); +deadTimeCounterReset_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFE0000000E" + ) + port map ( + I0 => deadTimeCounterReset_i_2_n_0, + I1 => \FSM_onehot_lineconfig[6]_i_4_n_0\, + I2 => reset, + I3 => breaking_en, + I4 => deadTimeCounterReset_i_3_n_0, + I5 => deadTimeCounterReset_reg_n_0, + O => deadTimeCounterReset_i_1_n_0 + ); +deadTimeCounterReset_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + O => deadTimeCounterReset_i_2_n_0 + ); +deadTimeCounterReset_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000022220020" + ) + port map ( + I0 => deadTimeCounterReset_i_4_n_0, + I1 => deadTimeCounterReset_i_2_n_0, + I2 => deadTimeCounterReset_i_5_n_0, + I3 => deadTimeCounterReset_i_6_n_0, + I4 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I5 => deadTimeCounterReset_i_7_n_0, + O => deadTimeCounterReset_i_3_n_0 + ); +deadTimeCounterReset_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"555D555555555555" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I1 => deadTimeOK, + I2 => TKin1, + I3 => TKin1_triggered, + I4 => TKin0, + I5 => TKin0_triggered, + O => deadTimeCounterReset_i_4_n_0 + ); +deadTimeCounterReset_i_5: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => deadTimeOK, + I1 => ready, + I2 => er, + O => deadTimeCounterReset_i_5_n_0 + ); +deadTimeCounterReset_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"F777" + ) + port map ( + I0 => TKin0, + I1 => TKin1, + I2 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I3 => deadTimeCounterReset_reg_n_0, + O => deadTimeCounterReset_i_6_n_0 + ); +deadTimeCounterReset_i_7: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAA2AAAAAAAAAA" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I1 => TKin1, + I2 => TKin0, + I3 => deadTimeOK, + I4 => TKin0_triggered, + I5 => TKin1_triggered, + O => deadTimeCounterReset_i_7_n_0 + ); +deadTimeCounterReset_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => '1', + D => deadTimeCounterReset_i_1_n_0, + Q => deadTimeCounterReset_reg_n_0, + R => '0' + ); +deadTimeOK_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"0D" + ) + port map ( + I0 => sel, + I1 => deadTimeOK, + I2 => deadTimeCounterReset_reg_n_0, + O => deadTimeOK_i_1_n_0 + ); +deadTimeOK_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => deadTimeOK_i_1_n_0, + Q => deadTimeOK, + R => '0' + ); +key1_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"DDDDDDD0DDDDDDDD" + ) + port map ( + I0 => breaking_en, + I1 => TKin0, + I2 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I4 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I5 => key1_i_2_n_0, + O => key1_i_1_n_0 + ); +key1_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I3 => breaking_en, + O => key1_i_2_n_0 + ); +key1_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key1_reg_n_0, + Q => key1_prev, + R => '0' + ); +key1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key1_i_1_n_0, + Q => key1_reg_n_0, + R => '0' + ); +key2_i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => reset, + O => p_0_in + ); +key2_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAFFFFFFFC" + ) + port map ( + I0 => TKin1, + I1 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I4 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I5 => breaking_en, + O => key2_i_2_n_0 + ); +key2_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key2_reg_n_0, + Q => key2_prev, + R => '0' + ); +key2_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key2_i_2_n_0, + Q => key2_reg_n_0, + R => '0' + ); +key3_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAFFFFAAAAFCFF" + ) + port map ( + I0 => key3_reg_n_0, + I1 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I3 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I4 => reset, + I5 => breaking_en, + O => key3_i_1_n_0 + ); +key3_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key3_reg_n_0, + Q => key3_prev, + R => '0' + ); +key3_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => key3_i_1_n_0, + Q => key3_reg_n_0, + R => '0' + ); +key4_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAFFFFAAAAFFFC" + ) + port map ( + I0 => key4_reg_n_0, + I1 => key3, + I2 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I4 => reset, + I5 => breaking_en, + O => key4_i_1_n_0 + ); +key4_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + O => key3 + ); +key4_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key4_reg_n_0, + Q => key4_prev, + R => '0' + ); +key4_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => key4_i_1_n_0, + Q => key4_reg_n_0, + R => '0' + ); +\ltOp__15_carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \ltOp__15_carry_n_0\, + CO(2) => \ltOp__15_carry_n_1\, + CO(1) => \ltOp__15_carry_n_2\, + CO(0) => \ltOp__15_carry_n_3\, + CYINIT => '0', + DI(3) => \ltOp__15_carry_i_1_n_0\, + DI(2) => \ltOp__15_carry_i_2_n_0\, + DI(1) => \ltOp__15_carry_i_3_n_0\, + DI(0) => \ltOp__15_carry_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__15_carry_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__15_carry_i_5_n_0\, + S(2) => \ltOp__15_carry_i_6_n_0\, + S(1) => \ltOp__15_carry_i_7_n_0\, + S(0) => \ltOp__15_carry_i_8_n_0\ + ); +\ltOp__15_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__15_carry_n_0\, + CO(3) => \ltOp__15_carry__0_n_0\, + CO(2) => \ltOp__15_carry__0_n_1\, + CO(1) => \ltOp__15_carry__0_n_2\, + CO(0) => \ltOp__15_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp__15_carry__0_i_1_n_0\, + DI(2) => \ltOp__15_carry__0_i_2_n_0\, + DI(1) => \ltOp__15_carry__0_i_3_n_0\, + DI(0) => \ltOp__15_carry__0_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__15_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__15_carry__0_i_5_n_0\, + S(2) => \ltOp__15_carry__0_i_6_n_0\, + S(1) => \ltOp__15_carry__0_i_7_n_0\, + S(0) => \ltOp__15_carry__0_i_8_n_0\ + ); +\ltOp__15_carry__0_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(15), + I1 => minTimeCounter_low_reg(15), + I2 => minTime(14), + I3 => minTimeCounter_low_reg(14), + O => \ltOp__15_carry__0_i_1_n_0\ + ); +\ltOp__15_carry__0_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(13), + I1 => minTimeCounter_low_reg(13), + I2 => minTime(12), + I3 => minTimeCounter_low_reg(12), + O => \ltOp__15_carry__0_i_2_n_0\ + ); +\ltOp__15_carry__0_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(11), + I1 => minTimeCounter_low_reg(11), + I2 => minTime(10), + I3 => minTimeCounter_low_reg(10), + O => \ltOp__15_carry__0_i_3_n_0\ + ); +\ltOp__15_carry__0_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(9), + I1 => minTimeCounter_low_reg(9), + I2 => minTime(8), + I3 => minTimeCounter_low_reg(8), + O => \ltOp__15_carry__0_i_4_n_0\ + ); +\ltOp__15_carry__0_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(15), + I1 => minTime(15), + I2 => minTimeCounter_low_reg(14), + I3 => minTime(14), + O => \ltOp__15_carry__0_i_5_n_0\ + ); +\ltOp__15_carry__0_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(13), + I1 => minTime(13), + I2 => minTimeCounter_low_reg(12), + I3 => minTime(12), + O => \ltOp__15_carry__0_i_6_n_0\ + ); +\ltOp__15_carry__0_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(11), + I1 => minTime(11), + I2 => minTimeCounter_low_reg(10), + I3 => minTime(10), + O => \ltOp__15_carry__0_i_7_n_0\ + ); +\ltOp__15_carry__0_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(9), + I1 => minTime(9), + I2 => minTimeCounter_low_reg(8), + I3 => minTime(8), + O => \ltOp__15_carry__0_i_8_n_0\ + ); +\ltOp__15_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__15_carry__0_n_0\, + CO(3) => \ltOp__15_carry__1_n_0\, + CO(2) => \ltOp__15_carry__1_n_1\, + CO(1) => \ltOp__15_carry__1_n_2\, + CO(0) => \ltOp__15_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp__15_carry__1_i_1_n_0\, + DI(2) => \ltOp__15_carry__1_i_2_n_0\, + DI(1) => \ltOp__15_carry__1_i_3_n_0\, + DI(0) => \ltOp__15_carry__1_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__15_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__15_carry__1_i_5_n_0\, + S(2) => \ltOp__15_carry__1_i_6_n_0\, + S(1) => \ltOp__15_carry__1_i_7_n_0\, + S(0) => \ltOp__15_carry__1_i_8_n_0\ + ); +\ltOp__15_carry__1_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(23), + I1 => minTimeCounter_low_reg(23), + I2 => minTime(22), + I3 => minTimeCounter_low_reg(22), + O => \ltOp__15_carry__1_i_1_n_0\ + ); +\ltOp__15_carry__1_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(21), + I1 => minTimeCounter_low_reg(21), + I2 => minTime(20), + I3 => minTimeCounter_low_reg(20), + O => \ltOp__15_carry__1_i_2_n_0\ + ); +\ltOp__15_carry__1_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(19), + I1 => minTimeCounter_low_reg(19), + I2 => minTime(18), + I3 => minTimeCounter_low_reg(18), + O => \ltOp__15_carry__1_i_3_n_0\ + ); +\ltOp__15_carry__1_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(17), + I1 => minTimeCounter_low_reg(17), + I2 => minTime(16), + I3 => minTimeCounter_low_reg(16), + O => \ltOp__15_carry__1_i_4_n_0\ + ); +\ltOp__15_carry__1_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(23), + I1 => minTime(23), + I2 => minTimeCounter_low_reg(22), + I3 => minTime(22), + O => \ltOp__15_carry__1_i_5_n_0\ + ); +\ltOp__15_carry__1_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(21), + I1 => minTime(21), + I2 => minTimeCounter_low_reg(20), + I3 => minTime(20), + O => \ltOp__15_carry__1_i_6_n_0\ + ); +\ltOp__15_carry__1_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(19), + I1 => minTime(19), + I2 => minTimeCounter_low_reg(18), + I3 => minTime(18), + O => \ltOp__15_carry__1_i_7_n_0\ + ); +\ltOp__15_carry__1_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(17), + I1 => minTime(17), + I2 => minTimeCounter_low_reg(16), + I3 => minTime(16), + O => \ltOp__15_carry__1_i_8_n_0\ + ); +\ltOp__15_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__15_carry__1_n_0\, + CO(3) => \ltOp__15_carry__2_n_0\, + CO(2) => \ltOp__15_carry__2_n_1\, + CO(1) => \ltOp__15_carry__2_n_2\, + CO(0) => \ltOp__15_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp__15_carry__2_i_1_n_0\, + DI(2) => \ltOp__15_carry__2_i_2_n_0\, + DI(1) => \ltOp__15_carry__2_i_3_n_0\, + DI(0) => \ltOp__15_carry__2_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__15_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__15_carry__2_i_5_n_0\, + S(2) => \ltOp__15_carry__2_i_6_n_0\, + S(1) => \ltOp__15_carry__2_i_7_n_0\, + S(0) => \ltOp__15_carry__2_i_8_n_0\ + ); +\ltOp__15_carry__2_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(31), + I1 => minTimeCounter_low_reg(31), + I2 => minTime(30), + I3 => minTimeCounter_low_reg(30), + O => \ltOp__15_carry__2_i_1_n_0\ + ); +\ltOp__15_carry__2_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(29), + I1 => minTimeCounter_low_reg(29), + I2 => minTime(28), + I3 => minTimeCounter_low_reg(28), + O => \ltOp__15_carry__2_i_2_n_0\ + ); +\ltOp__15_carry__2_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(27), + I1 => minTimeCounter_low_reg(27), + I2 => minTime(26), + I3 => minTimeCounter_low_reg(26), + O => \ltOp__15_carry__2_i_3_n_0\ + ); +\ltOp__15_carry__2_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(25), + I1 => minTimeCounter_low_reg(25), + I2 => minTime(24), + I3 => minTimeCounter_low_reg(24), + O => \ltOp__15_carry__2_i_4_n_0\ + ); +\ltOp__15_carry__2_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(31), + I1 => minTime(31), + I2 => minTimeCounter_low_reg(30), + I3 => minTime(30), + O => \ltOp__15_carry__2_i_5_n_0\ + ); +\ltOp__15_carry__2_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(29), + I1 => minTime(29), + I2 => minTimeCounter_low_reg(28), + I3 => minTime(28), + O => \ltOp__15_carry__2_i_6_n_0\ + ); +\ltOp__15_carry__2_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(27), + I1 => minTime(27), + I2 => minTimeCounter_low_reg(26), + I3 => minTime(26), + O => \ltOp__15_carry__2_i_7_n_0\ + ); +\ltOp__15_carry__2_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(25), + I1 => minTime(25), + I2 => minTimeCounter_low_reg(24), + I3 => minTime(24), + O => \ltOp__15_carry__2_i_8_n_0\ + ); +\ltOp__15_carry_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(7), + I1 => minTimeCounter_low_reg(7), + I2 => minTime(6), + I3 => minTimeCounter_low_reg(6), + O => \ltOp__15_carry_i_1_n_0\ + ); +\ltOp__15_carry_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(5), + I1 => minTimeCounter_low_reg(5), + I2 => minTime(4), + I3 => minTimeCounter_low_reg(4), + O => \ltOp__15_carry_i_2_n_0\ + ); +\ltOp__15_carry_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(3), + I1 => minTimeCounter_low_reg(3), + I2 => minTime(2), + I3 => minTimeCounter_low_reg(2), + O => \ltOp__15_carry_i_3_n_0\ + ); +\ltOp__15_carry_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(1), + I1 => minTimeCounter_low_reg(1), + I2 => minTime(0), + I3 => minTimeCounter_low_reg(0), + O => \ltOp__15_carry_i_4_n_0\ + ); +\ltOp__15_carry_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(7), + I1 => minTime(7), + I2 => minTimeCounter_low_reg(6), + I3 => minTime(6), + O => \ltOp__15_carry_i_5_n_0\ + ); +\ltOp__15_carry_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(5), + I1 => minTime(5), + I2 => minTimeCounter_low_reg(4), + I3 => minTime(4), + O => \ltOp__15_carry_i_6_n_0\ + ); +\ltOp__15_carry_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(3), + I1 => minTime(3), + I2 => minTimeCounter_low_reg(2), + I3 => minTime(2), + O => \ltOp__15_carry_i_7_n_0\ + ); +\ltOp__15_carry_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(1), + I1 => minTime(1), + I2 => minTimeCounter_low_reg(0), + I3 => minTime(0), + O => \ltOp__15_carry_i_8_n_0\ + ); +\ltOp__31_carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \ltOp__31_carry_n_0\, + CO(2) => \ltOp__31_carry_n_1\, + CO(1) => \ltOp__31_carry_n_2\, + CO(0) => \ltOp__31_carry_n_3\, + CYINIT => '0', + DI(3) => \ltOp__31_carry_i_1_n_0\, + DI(2) => \ltOp__31_carry_i_2_n_0\, + DI(1) => \ltOp__31_carry_i_3_n_0\, + DI(0) => \ltOp__31_carry_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__31_carry_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__31_carry_i_5_n_0\, + S(2) => \ltOp__31_carry_i_6_n_0\, + S(1) => \ltOp__31_carry_i_7_n_0\, + S(0) => \ltOp__31_carry_i_8_n_0\ + ); +\ltOp__31_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__31_carry_n_0\, + CO(3) => \ltOp__31_carry__0_n_0\, + CO(2) => \ltOp__31_carry__0_n_1\, + CO(1) => \ltOp__31_carry__0_n_2\, + CO(0) => \ltOp__31_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp__31_carry_i_1__0_n_0\, + DI(2) => \ltOp__31_carry_i_2__0_n_0\, + DI(1) => \ltOp__31_carry_i_3__0_n_0\, + DI(0) => \ltOp__31_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp__31_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__31_carry_i_5__0_n_0\, + S(2) => \ltOp__31_carry_i_6__0_n_0\, + S(1) => \ltOp__31_carry_i_7__0_n_0\, + S(0) => \ltOp__31_carry_i_8__0_n_0\ + ); +\ltOp__31_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__31_carry__0_n_0\, + CO(3) => \ltOp__31_carry__1_n_0\, + CO(2) => \ltOp__31_carry__1_n_1\, + CO(1) => \ltOp__31_carry__1_n_2\, + CO(0) => \ltOp__31_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp__31_carry_i_1__1_n_0\, + DI(2) => \ltOp__31_carry_i_2__1_n_0\, + DI(1) => \ltOp__31_carry_i_3__1_n_0\, + DI(0) => \ltOp__31_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp__31_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__31_carry_i_5__1_n_0\, + S(2) => \ltOp__31_carry_i_6__1_n_0\, + S(1) => \ltOp__31_carry_i_7__1_n_0\, + S(0) => \ltOp__31_carry_i_8__1_n_0\ + ); +\ltOp__31_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__31_carry__1_n_0\, + CO(3) => \ltOp__31_carry__2_n_0\, + CO(2) => \ltOp__31_carry__2_n_1\, + CO(1) => \ltOp__31_carry__2_n_2\, + CO(0) => \ltOp__31_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp__31_carry_i_1__2_n_0\, + DI(2) => \ltOp__31_carry_i_2__2_n_0\, + DI(1) => \ltOp__31_carry_i_3__2_n_0\, + DI(0) => \ltOp__31_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp__31_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__31_carry_i_5__2_n_0\, + S(2) => \ltOp__31_carry_i_6__2_n_0\, + S(1) => \ltOp__31_carry_i_7__2_n_0\, + S(0) => \ltOp__31_carry_i_8__2_n_0\ + ); +\ltOp__31_carry_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(7), + I1 => minTimeCounter_high_reg(7), + I2 => minTime(6), + I3 => minTimeCounter_high_reg(6), + O => \ltOp__31_carry_i_1_n_0\ + ); +\ltOp__31_carry_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(15), + I1 => minTimeCounter_high_reg(15), + I2 => minTime(14), + I3 => minTimeCounter_high_reg(14), + O => \ltOp__31_carry_i_1__0_n_0\ + ); +\ltOp__31_carry_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(23), + I1 => minTimeCounter_high_reg(23), + I2 => minTime(22), + I3 => minTimeCounter_high_reg(22), + O => \ltOp__31_carry_i_1__1_n_0\ + ); +\ltOp__31_carry_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(31), + I1 => minTimeCounter_high_reg(31), + I2 => minTime(30), + I3 => minTimeCounter_high_reg(30), + O => \ltOp__31_carry_i_1__2_n_0\ + ); +\ltOp__31_carry_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(5), + I1 => minTimeCounter_high_reg(5), + I2 => minTime(4), + I3 => minTimeCounter_high_reg(4), + O => \ltOp__31_carry_i_2_n_0\ + ); +\ltOp__31_carry_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(13), + I1 => minTimeCounter_high_reg(13), + I2 => minTime(12), + I3 => minTimeCounter_high_reg(12), + O => \ltOp__31_carry_i_2__0_n_0\ + ); +\ltOp__31_carry_i_2__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(21), + I1 => minTimeCounter_high_reg(21), + I2 => minTime(20), + I3 => minTimeCounter_high_reg(20), + O => \ltOp__31_carry_i_2__1_n_0\ + ); +\ltOp__31_carry_i_2__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(29), + I1 => minTimeCounter_high_reg(29), + I2 => minTime(28), + I3 => minTimeCounter_high_reg(28), + O => \ltOp__31_carry_i_2__2_n_0\ + ); +\ltOp__31_carry_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(3), + I1 => minTimeCounter_high_reg(3), + I2 => minTime(2), + I3 => minTimeCounter_high_reg(2), + O => \ltOp__31_carry_i_3_n_0\ + ); +\ltOp__31_carry_i_3__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(11), + I1 => minTimeCounter_high_reg(11), + I2 => minTime(10), + I3 => minTimeCounter_high_reg(10), + O => \ltOp__31_carry_i_3__0_n_0\ + ); +\ltOp__31_carry_i_3__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(19), + I1 => minTimeCounter_high_reg(19), + I2 => minTime(18), + I3 => minTimeCounter_high_reg(18), + O => \ltOp__31_carry_i_3__1_n_0\ + ); +\ltOp__31_carry_i_3__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(27), + I1 => minTimeCounter_high_reg(27), + I2 => minTime(26), + I3 => minTimeCounter_high_reg(26), + O => \ltOp__31_carry_i_3__2_n_0\ + ); +\ltOp__31_carry_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(1), + I1 => minTimeCounter_high_reg(1), + I2 => minTime(0), + I3 => minTimeCounter_high_reg(0), + O => \ltOp__31_carry_i_4_n_0\ + ); +\ltOp__31_carry_i_4__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(9), + I1 => minTimeCounter_high_reg(9), + I2 => minTime(8), + I3 => minTimeCounter_high_reg(8), + O => \ltOp__31_carry_i_4__0_n_0\ + ); +\ltOp__31_carry_i_4__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(17), + I1 => minTimeCounter_high_reg(17), + I2 => minTime(16), + I3 => minTimeCounter_high_reg(16), + O => \ltOp__31_carry_i_4__1_n_0\ + ); +\ltOp__31_carry_i_4__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(25), + I1 => minTimeCounter_high_reg(25), + I2 => minTime(24), + I3 => minTimeCounter_high_reg(24), + O => \ltOp__31_carry_i_4__2_n_0\ + ); +\ltOp__31_carry_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(7), + I1 => minTime(7), + I2 => minTimeCounter_high_reg(6), + I3 => minTime(6), + O => \ltOp__31_carry_i_5_n_0\ + ); +\ltOp__31_carry_i_5__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(15), + I1 => minTime(15), + I2 => minTimeCounter_high_reg(14), + I3 => minTime(14), + O => \ltOp__31_carry_i_5__0_n_0\ + ); +\ltOp__31_carry_i_5__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(23), + I1 => minTime(23), + I2 => minTimeCounter_high_reg(22), + I3 => minTime(22), + O => \ltOp__31_carry_i_5__1_n_0\ + ); +\ltOp__31_carry_i_5__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(31), + I1 => minTime(31), + I2 => minTimeCounter_high_reg(30), + I3 => minTime(30), + O => \ltOp__31_carry_i_5__2_n_0\ + ); +\ltOp__31_carry_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(5), + I1 => minTime(5), + I2 => minTimeCounter_high_reg(4), + I3 => minTime(4), + O => \ltOp__31_carry_i_6_n_0\ + ); +\ltOp__31_carry_i_6__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(13), + I1 => minTime(13), + I2 => minTimeCounter_high_reg(12), + I3 => minTime(12), + O => \ltOp__31_carry_i_6__0_n_0\ + ); +\ltOp__31_carry_i_6__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(21), + I1 => minTime(21), + I2 => minTimeCounter_high_reg(20), + I3 => minTime(20), + O => \ltOp__31_carry_i_6__1_n_0\ + ); +\ltOp__31_carry_i_6__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(29), + I1 => minTime(29), + I2 => minTimeCounter_high_reg(28), + I3 => minTime(28), + O => \ltOp__31_carry_i_6__2_n_0\ + ); +\ltOp__31_carry_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(3), + I1 => minTime(3), + I2 => minTimeCounter_high_reg(2), + I3 => minTime(2), + O => \ltOp__31_carry_i_7_n_0\ + ); +\ltOp__31_carry_i_7__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(11), + I1 => minTime(11), + I2 => minTimeCounter_high_reg(10), + I3 => minTime(10), + O => \ltOp__31_carry_i_7__0_n_0\ + ); +\ltOp__31_carry_i_7__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(19), + I1 => minTime(19), + I2 => minTimeCounter_high_reg(18), + I3 => minTime(18), + O => \ltOp__31_carry_i_7__1_n_0\ + ); +\ltOp__31_carry_i_7__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(27), + I1 => minTime(27), + I2 => minTimeCounter_high_reg(26), + I3 => minTime(26), + O => \ltOp__31_carry_i_7__2_n_0\ + ); +\ltOp__31_carry_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(1), + I1 => minTime(1), + I2 => minTimeCounter_high_reg(0), + I3 => minTime(0), + O => \ltOp__31_carry_i_8_n_0\ + ); +\ltOp__31_carry_i_8__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(9), + I1 => minTime(9), + I2 => minTimeCounter_high_reg(8), + I3 => minTime(8), + O => \ltOp__31_carry_i_8__0_n_0\ + ); +\ltOp__31_carry_i_8__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(17), + I1 => minTime(17), + I2 => minTimeCounter_high_reg(16), + I3 => minTime(16), + O => \ltOp__31_carry_i_8__1_n_0\ + ); +\ltOp__31_carry_i_8__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(25), + I1 => minTime(25), + I2 => minTimeCounter_high_reg(24), + I3 => minTime(24), + O => \ltOp__31_carry_i_8__2_n_0\ + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry__0_i_1_n_0\, + DI(2) => \ltOp_carry__0_i_2_n_0\, + DI(1) => \ltOp_carry__0_i_3_n_0\, + DI(0) => \ltOp_carry__0_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry__0_i_5_n_0\, + S(2) => \ltOp_carry__0_i_6_n_0\, + S(1) => \ltOp_carry__0_i_7_n_0\, + S(0) => \ltOp_carry__0_i_8_n_0\ + ); +\ltOp_carry__0_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(15), + I1 => TimeCounter_reg(15), + I2 => deadTime(14), + I3 => TimeCounter_reg(14), + O => \ltOp_carry__0_i_1_n_0\ + ); +\ltOp_carry__0_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(13), + I1 => TimeCounter_reg(13), + I2 => deadTime(12), + I3 => TimeCounter_reg(12), + O => \ltOp_carry__0_i_2_n_0\ + ); +\ltOp_carry__0_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(11), + I1 => TimeCounter_reg(11), + I2 => deadTime(10), + I3 => TimeCounter_reg(10), + O => \ltOp_carry__0_i_3_n_0\ + ); +\ltOp_carry__0_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(9), + I1 => TimeCounter_reg(9), + I2 => deadTime(8), + I3 => TimeCounter_reg(8), + O => \ltOp_carry__0_i_4_n_0\ + ); +\ltOp_carry__0_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(15), + I1 => deadTime(15), + I2 => TimeCounter_reg(14), + I3 => deadTime(14), + O => \ltOp_carry__0_i_5_n_0\ + ); +\ltOp_carry__0_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(13), + I1 => deadTime(13), + I2 => TimeCounter_reg(12), + I3 => deadTime(12), + O => \ltOp_carry__0_i_6_n_0\ + ); +\ltOp_carry__0_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(11), + I1 => deadTime(11), + I2 => TimeCounter_reg(10), + I3 => deadTime(10), + O => \ltOp_carry__0_i_7_n_0\ + ); +\ltOp_carry__0_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(9), + I1 => deadTime(9), + I2 => TimeCounter_reg(8), + I3 => deadTime(8), + O => \ltOp_carry__0_i_8_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry__1_i_1_n_0\, + DI(2) => \ltOp_carry__1_i_2_n_0\, + DI(1) => \ltOp_carry__1_i_3_n_0\, + DI(0) => \ltOp_carry__1_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry__1_i_5_n_0\, + S(2) => \ltOp_carry__1_i_6_n_0\, + S(1) => \ltOp_carry__1_i_7_n_0\, + S(0) => \ltOp_carry__1_i_8_n_0\ + ); +\ltOp_carry__1_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(23), + I1 => TimeCounter_reg(23), + I2 => deadTime(22), + I3 => TimeCounter_reg(22), + O => \ltOp_carry__1_i_1_n_0\ + ); +\ltOp_carry__1_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(21), + I1 => TimeCounter_reg(21), + I2 => deadTime(20), + I3 => TimeCounter_reg(20), + O => \ltOp_carry__1_i_2_n_0\ + ); +\ltOp_carry__1_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(19), + I1 => TimeCounter_reg(19), + I2 => deadTime(18), + I3 => TimeCounter_reg(18), + O => \ltOp_carry__1_i_3_n_0\ + ); +\ltOp_carry__1_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(17), + I1 => TimeCounter_reg(17), + I2 => deadTime(16), + I3 => TimeCounter_reg(16), + O => \ltOp_carry__1_i_4_n_0\ + ); +\ltOp_carry__1_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(23), + I1 => deadTime(23), + I2 => TimeCounter_reg(22), + I3 => deadTime(22), + O => \ltOp_carry__1_i_5_n_0\ + ); +\ltOp_carry__1_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(21), + I1 => deadTime(21), + I2 => TimeCounter_reg(20), + I3 => deadTime(20), + O => \ltOp_carry__1_i_6_n_0\ + ); +\ltOp_carry__1_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(19), + I1 => deadTime(19), + I2 => TimeCounter_reg(18), + I3 => deadTime(18), + O => \ltOp_carry__1_i_7_n_0\ + ); +\ltOp_carry__1_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(17), + I1 => deadTime(17), + I2 => TimeCounter_reg(16), + I3 => deadTime(16), + O => \ltOp_carry__1_i_8_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => sel, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry__2_i_1_n_0\, + DI(2) => \ltOp_carry__2_i_2_n_0\, + DI(1) => \ltOp_carry__2_i_3_n_0\, + DI(0) => \ltOp_carry__2_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry__2_i_5_n_0\, + S(2) => \ltOp_carry__2_i_6_n_0\, + S(1) => \ltOp_carry__2_i_7_n_0\, + S(0) => \ltOp_carry__2_i_8_n_0\ + ); +\ltOp_carry__2_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(31), + I1 => TimeCounter_reg(31), + I2 => deadTime(30), + I3 => TimeCounter_reg(30), + O => \ltOp_carry__2_i_1_n_0\ + ); +\ltOp_carry__2_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(29), + I1 => TimeCounter_reg(29), + I2 => deadTime(28), + I3 => TimeCounter_reg(28), + O => \ltOp_carry__2_i_2_n_0\ + ); +\ltOp_carry__2_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(27), + I1 => TimeCounter_reg(27), + I2 => deadTime(26), + I3 => TimeCounter_reg(26), + O => \ltOp_carry__2_i_3_n_0\ + ); +\ltOp_carry__2_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(25), + I1 => TimeCounter_reg(25), + I2 => deadTime(24), + I3 => TimeCounter_reg(24), + O => \ltOp_carry__2_i_4_n_0\ + ); +\ltOp_carry__2_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(31), + I1 => deadTime(31), + I2 => TimeCounter_reg(30), + I3 => deadTime(30), + O => \ltOp_carry__2_i_5_n_0\ + ); +\ltOp_carry__2_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(29), + I1 => deadTime(29), + I2 => TimeCounter_reg(28), + I3 => deadTime(28), + O => \ltOp_carry__2_i_6_n_0\ + ); +\ltOp_carry__2_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(27), + I1 => deadTime(27), + I2 => TimeCounter_reg(26), + I3 => deadTime(26), + O => \ltOp_carry__2_i_7_n_0\ + ); +\ltOp_carry__2_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(25), + I1 => deadTime(25), + I2 => TimeCounter_reg(24), + I3 => deadTime(24), + O => \ltOp_carry__2_i_8_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(7), + I1 => TimeCounter_reg(7), + I2 => deadTime(6), + I3 => TimeCounter_reg(6), + O => ltOp_carry_i_1_n_0 + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(5), + I1 => TimeCounter_reg(5), + I2 => deadTime(4), + I3 => TimeCounter_reg(4), + O => ltOp_carry_i_2_n_0 + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(3), + I1 => TimeCounter_reg(3), + I2 => deadTime(2), + I3 => TimeCounter_reg(2), + O => ltOp_carry_i_3_n_0 + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(1), + I1 => TimeCounter_reg(1), + I2 => deadTime(0), + I3 => TimeCounter_reg(0), + O => ltOp_carry_i_4_n_0 + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(7), + I1 => deadTime(7), + I2 => TimeCounter_reg(6), + I3 => deadTime(6), + O => ltOp_carry_i_5_n_0 + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(5), + I1 => deadTime(5), + I2 => TimeCounter_reg(4), + I3 => deadTime(4), + O => ltOp_carry_i_6_n_0 + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(3), + I1 => deadTime(3), + I2 => TimeCounter_reg(2), + I3 => deadTime(2), + O => ltOp_carry_i_7_n_0 + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(1), + I1 => deadTime(1), + I2 => TimeCounter_reg(0), + I3 => deadTime(0), + O => ltOp_carry_i_8_n_0 + ); +\minTimeCounter_high[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000022222F22" + ) + port map ( + I0 => key1_prev, + I1 => key1_reg_n_0, + I2 => key2_reg_n_0, + I3 => key2_prev, + I4 => breaking_en, + I5 => reset, + O => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high[0]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \ltOp__31_carry__2_n_0\, + I1 => reset, + O => minTimeCounter_high + ); +\minTimeCounter_high[0]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => minTimeCounter_high_reg(0), + O => \minTimeCounter_high[0]_i_4_n_0\ + ); +\minTimeCounter_high_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[0]_i_3_n_7\, + Q => minTimeCounter_high_reg(0), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[0]_i_3\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \minTimeCounter_high_reg[0]_i_3_n_0\, + CO(2) => \minTimeCounter_high_reg[0]_i_3_n_1\, + CO(1) => \minTimeCounter_high_reg[0]_i_3_n_2\, + CO(0) => \minTimeCounter_high_reg[0]_i_3_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \minTimeCounter_high_reg[0]_i_3_n_4\, + O(2) => \minTimeCounter_high_reg[0]_i_3_n_5\, + O(1) => \minTimeCounter_high_reg[0]_i_3_n_6\, + O(0) => \minTimeCounter_high_reg[0]_i_3_n_7\, + S(3 downto 1) => minTimeCounter_high_reg(3 downto 1), + S(0) => \minTimeCounter_high[0]_i_4_n_0\ + ); +\minTimeCounter_high_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[8]_i_1_n_5\, + Q => minTimeCounter_high_reg(10), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[8]_i_1_n_4\, + Q => minTimeCounter_high_reg(11), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[12]_i_1_n_7\, + Q => minTimeCounter_high_reg(12), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[8]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[12]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[12]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[12]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[12]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[12]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[12]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[12]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[12]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(15 downto 12) + ); +\minTimeCounter_high_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[12]_i_1_n_6\, + Q => minTimeCounter_high_reg(13), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[12]_i_1_n_5\, + Q => minTimeCounter_high_reg(14), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[12]_i_1_n_4\, + Q => minTimeCounter_high_reg(15), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[16]_i_1_n_7\, + Q => minTimeCounter_high_reg(16), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[16]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[12]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[16]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[16]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[16]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[16]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[16]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[16]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[16]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[16]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(19 downto 16) + ); +\minTimeCounter_high_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[16]_i_1_n_6\, + Q => minTimeCounter_high_reg(17), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[16]_i_1_n_5\, + Q => minTimeCounter_high_reg(18), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[16]_i_1_n_4\, + Q => minTimeCounter_high_reg(19), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[0]_i_3_n_6\, + Q => minTimeCounter_high_reg(1), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[20]_i_1_n_7\, + Q => minTimeCounter_high_reg(20), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[20]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[16]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[20]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[20]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[20]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[20]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[20]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[20]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[20]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[20]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(23 downto 20) + ); +\minTimeCounter_high_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[20]_i_1_n_6\, + Q => minTimeCounter_high_reg(21), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[20]_i_1_n_5\, + Q => minTimeCounter_high_reg(22), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[20]_i_1_n_4\, + Q => minTimeCounter_high_reg(23), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[24]_i_1_n_7\, + Q => minTimeCounter_high_reg(24), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[24]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[20]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[24]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[24]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[24]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[24]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[24]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[24]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[24]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[24]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(27 downto 24) + ); +\minTimeCounter_high_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[24]_i_1_n_6\, + Q => minTimeCounter_high_reg(25), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[24]_i_1_n_5\, + Q => minTimeCounter_high_reg(26), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[24]_i_1_n_4\, + Q => minTimeCounter_high_reg(27), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[28]_i_1_n_7\, + Q => minTimeCounter_high_reg(28), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[28]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[24]_i_1_n_0\, + CO(3) => \NLW_minTimeCounter_high_reg[28]_i_1_CO_UNCONNECTED\(3), + CO(2) => \minTimeCounter_high_reg[28]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[28]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[28]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[28]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[28]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[28]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[28]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(31 downto 28) + ); +\minTimeCounter_high_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[28]_i_1_n_6\, + Q => minTimeCounter_high_reg(29), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[0]_i_3_n_5\, + Q => minTimeCounter_high_reg(2), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[28]_i_1_n_5\, + Q => minTimeCounter_high_reg(30), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[28]_i_1_n_4\, + Q => minTimeCounter_high_reg(31), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[0]_i_3_n_4\, + Q => minTimeCounter_high_reg(3), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[4]_i_1_n_7\, + Q => minTimeCounter_high_reg(4), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[0]_i_3_n_0\, + CO(3) => \minTimeCounter_high_reg[4]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[4]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[4]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[4]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[4]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[4]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[4]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(7 downto 4) + ); +\minTimeCounter_high_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[4]_i_1_n_6\, + Q => minTimeCounter_high_reg(5), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[4]_i_1_n_5\, + Q => minTimeCounter_high_reg(6), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[4]_i_1_n_4\, + Q => minTimeCounter_high_reg(7), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[8]_i_1_n_7\, + Q => minTimeCounter_high_reg(8), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[4]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[8]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[8]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[8]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[8]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[8]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[8]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[8]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(11 downto 8) + ); +\minTimeCounter_high_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[8]_i_1_n_6\, + Q => minTimeCounter_high_reg(9), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_low[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000440F" + ) + port map ( + I0 => key2_reg_n_0, + I1 => key2_prev, + I2 => \minTimeCounter_low[0]_i_4_n_0\, + I3 => breaking_en, + I4 => reset, + O => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low[0]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \ltOp__15_carry__2_n_0\, + I1 => reset, + O => minTimeCounter_low + ); +\minTimeCounter_low[0]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"D0DD" + ) + port map ( + I0 => key4_prev, + I1 => key4_reg_n_0, + I2 => key3_reg_n_0, + I3 => key3_prev, + O => \minTimeCounter_low[0]_i_4_n_0\ + ); +\minTimeCounter_low[0]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => minTimeCounter_low_reg(0), + O => \minTimeCounter_low[0]_i_5_n_0\ + ); +\minTimeCounter_low_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[0]_i_3_n_7\, + Q => minTimeCounter_low_reg(0), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[0]_i_3\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \minTimeCounter_low_reg[0]_i_3_n_0\, + CO(2) => \minTimeCounter_low_reg[0]_i_3_n_1\, + CO(1) => \minTimeCounter_low_reg[0]_i_3_n_2\, + CO(0) => \minTimeCounter_low_reg[0]_i_3_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \minTimeCounter_low_reg[0]_i_3_n_4\, + O(2) => \minTimeCounter_low_reg[0]_i_3_n_5\, + O(1) => \minTimeCounter_low_reg[0]_i_3_n_6\, + O(0) => \minTimeCounter_low_reg[0]_i_3_n_7\, + S(3 downto 1) => minTimeCounter_low_reg(3 downto 1), + S(0) => \minTimeCounter_low[0]_i_5_n_0\ + ); +\minTimeCounter_low_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[8]_i_1_n_5\, + Q => minTimeCounter_low_reg(10), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[8]_i_1_n_4\, + Q => minTimeCounter_low_reg(11), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[12]_i_1_n_7\, + Q => minTimeCounter_low_reg(12), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[8]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[12]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[12]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[12]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[12]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[12]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[12]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[12]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[12]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(15 downto 12) + ); +\minTimeCounter_low_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[12]_i_1_n_6\, + Q => minTimeCounter_low_reg(13), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[12]_i_1_n_5\, + Q => minTimeCounter_low_reg(14), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[12]_i_1_n_4\, + Q => minTimeCounter_low_reg(15), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[16]_i_1_n_7\, + Q => minTimeCounter_low_reg(16), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[16]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[12]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[16]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[16]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[16]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[16]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[16]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[16]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[16]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[16]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(19 downto 16) + ); +\minTimeCounter_low_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[16]_i_1_n_6\, + Q => minTimeCounter_low_reg(17), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[16]_i_1_n_5\, + Q => minTimeCounter_low_reg(18), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[16]_i_1_n_4\, + Q => minTimeCounter_low_reg(19), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[0]_i_3_n_6\, + Q => minTimeCounter_low_reg(1), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[20]_i_1_n_7\, + Q => minTimeCounter_low_reg(20), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[20]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[16]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[20]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[20]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[20]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[20]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[20]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[20]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[20]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[20]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(23 downto 20) + ); +\minTimeCounter_low_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[20]_i_1_n_6\, + Q => minTimeCounter_low_reg(21), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[20]_i_1_n_5\, + Q => minTimeCounter_low_reg(22), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[20]_i_1_n_4\, + Q => minTimeCounter_low_reg(23), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[24]_i_1_n_7\, + Q => minTimeCounter_low_reg(24), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[24]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[20]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[24]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[24]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[24]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[24]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[24]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[24]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[24]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[24]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(27 downto 24) + ); +\minTimeCounter_low_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[24]_i_1_n_6\, + Q => minTimeCounter_low_reg(25), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[24]_i_1_n_5\, + Q => minTimeCounter_low_reg(26), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[24]_i_1_n_4\, + Q => minTimeCounter_low_reg(27), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[28]_i_1_n_7\, + Q => minTimeCounter_low_reg(28), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[28]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[24]_i_1_n_0\, + CO(3) => \NLW_minTimeCounter_low_reg[28]_i_1_CO_UNCONNECTED\(3), + CO(2) => \minTimeCounter_low_reg[28]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[28]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[28]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[28]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[28]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[28]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[28]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(31 downto 28) + ); +\minTimeCounter_low_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[28]_i_1_n_6\, + Q => minTimeCounter_low_reg(29), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[0]_i_3_n_5\, + Q => minTimeCounter_low_reg(2), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[28]_i_1_n_5\, + Q => minTimeCounter_low_reg(30), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[28]_i_1_n_4\, + Q => minTimeCounter_low_reg(31), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[0]_i_3_n_4\, + Q => minTimeCounter_low_reg(3), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[4]_i_1_n_7\, + Q => minTimeCounter_low_reg(4), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[0]_i_3_n_0\, + CO(3) => \minTimeCounter_low_reg[4]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[4]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[4]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[4]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[4]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[4]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[4]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(7 downto 4) + ); +\minTimeCounter_low_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[4]_i_1_n_6\, + Q => minTimeCounter_low_reg(5), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[4]_i_1_n_5\, + Q => minTimeCounter_low_reg(6), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[4]_i_1_n_4\, + Q => minTimeCounter_low_reg(7), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[8]_i_1_n_7\, + Q => minTimeCounter_low_reg(8), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[4]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[8]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[8]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[8]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[8]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[8]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[8]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[8]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(11 downto 8) + ); +\minTimeCounter_low_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[8]_i_1_n_6\, + Q => minTimeCounter_low_reg(9), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +minTimeEr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"EEFFEEEEE200E2E2" + ) + port map ( + I0 => minTimeEr_i_2_n_0, + I1 => minTimeEr_i_3_n_0, + I2 => minTimeEr_i_4_n_0, + I3 => minTimeEr_i_5_n_0, + I4 => minTimeEr_i_6_n_0, + I5 => \^mintimeer_reg_0\, + O => minTimeEr_i_1_n_0 + ); +minTimeEr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"0111" + ) + port map ( + I0 => reset, + I1 => breaking_en, + I2 => minTimeEr_i_6_n_0, + I3 => minTimeEr_i_7_n_0, + O => minTimeEr_i_2_n_0 + ); +minTimeEr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => breaking_en, + I1 => reset, + O => minTimeEr_i_3_n_0 + ); +minTimeEr_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"040404FF00000000" + ) + port map ( + I0 => minTimeOK_low, + I1 => key2_reg_n_0, + I2 => key2_prev, + I3 => minTimeEr_i_8_n_0, + I4 => minTimeOK_high, + I5 => minTime_En, + O => minTimeEr_i_4_n_0 + ); +minTimeEr_i_5: unisim.vcomponents.LUT6 + generic map( + INIT => X"55555555F755F7F7" + ) + port map ( + I0 => minTimeEr_i_9_n_0, + I1 => key2_prev, + I2 => key2_reg_n_0, + I3 => key1_reg_n_0, + I4 => key1_prev, + I5 => minTimeEr_i_7_n_0, + O => minTimeEr_i_5_n_0 + ); +minTimeEr_i_6: unisim.vcomponents.LUT6 + generic map( + INIT => X"FBFFFFFFBBFBFBFF" + ) + port map ( + I0 => minTimeOK_low, + I1 => minTime_En, + I2 => key3_prev, + I3 => key3_reg_n_0, + I4 => key4_reg_n_0, + I5 => key4_prev, + O => minTimeEr_i_6_n_0 + ); +minTimeEr_i_7: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFDFDDDDFFDFFFDF" + ) + port map ( + I0 => minTime_En, + I1 => minTimeOK_high, + I2 => key2_reg_n_0, + I3 => key2_prev, + I4 => key1_prev, + I5 => key1_reg_n_0, + O => minTimeEr_i_7_n_0 + ); +minTimeEr_i_8: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => key1_prev, + I1 => key1_reg_n_0, + O => minTimeEr_i_8_n_0 + ); +minTimeEr_i_9: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => breaking_en, + I1 => reset, + O => minTimeEr_i_9_n_0 + ); +minTimeEr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => '1', + D => minTimeEr_i_1_n_0, + Q => \^mintimeer_reg_0\, + R => '0' + ); +minTimeOK_high_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"00AB" + ) + port map ( + I0 => minTimeOK_high, + I1 => \ltOp__31_carry__2_n_0\, + I2 => reset, + I3 => \minTimeCounter_high[0]_i_1_n_0\, + O => minTimeOK_high_i_1_n_0 + ); +minTimeOK_high_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => minTimeOK_high_i_1_n_0, + Q => minTimeOK_high, + R => '0' + ); +minTimeOK_low_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"00AB" + ) + port map ( + I0 => minTimeOK_low, + I1 => \ltOp__15_carry__2_n_0\, + I2 => reset, + I3 => \minTimeCounter_low[0]_i_1_n_0\, + O => minTimeOK_low_i_1_n_0 + ); +minTimeOK_low_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => minTimeOK_low_i_1_n_0, + Q => minTimeOK_low, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Inverter_3lvl_P0N_3lvl_0_4 is + port ( + externalCLK : in STD_LOGIC; + ready : in STD_LOGIC; + reset : in STD_LOGIC; + deadTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + minTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + er : in STD_LOGIC; + minTime_En : in STD_LOGIC; + minTimeEr : out STD_LOGIC; + TKin0 : in STD_LOGIC; + TKin1 : in STD_LOGIC; + breaking_en : in STD_LOGIC; + PWM_out_0 : out STD_LOGIC; + PWM_out_1 : out STD_LOGIC; + PWM_out_2 : out STD_LOGIC; + PWM_out_3 : out STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of Inverter_3lvl_P0N_3lvl_0_4 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of Inverter_3lvl_P0N_3lvl_0_4 : entity is "Inverter_3lvl_P0N_3lvl_0_4,P0N_3lvl,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of Inverter_3lvl_P0N_3lvl_0_4 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of Inverter_3lvl_P0N_3lvl_0_4 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of Inverter_3lvl_P0N_3lvl_0_4 : entity is "P0N_3lvl,Vivado 2019.1"; +end Inverter_3lvl_P0N_3lvl_0_4; + +architecture STRUCTURE of Inverter_3lvl_P0N_3lvl_0_4 is + attribute x_interface_info : string; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.Inverter_3lvl_P0N_3lvl_0_4_P0N_3lvl + port map ( + PWM_out_0 => PWM_out_0, + PWM_out_1 => PWM_out_1, + PWM_out_2 => PWM_out_2, + PWM_out_3 => PWM_out_3, + TKin0 => TKin0, + TKin1 => TKin1, + breaking_en => breaking_en, + deadTime(31 downto 0) => deadTime(31 downto 0), + er => er, + externalCLK => externalCLK, + minTime(31 downto 0) => minTime(31 downto 0), + minTimeEr_reg_0 => minTimeEr, + minTime_En => minTime_En, + ready => ready, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_stub.v b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_stub.v new file mode 100644 index 0000000..015b1b3 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_stub.v @@ -0,0 +1,35 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Fri Jun 11 07:49:57 2021 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top Inverter_3lvl_P0N_3lvl_0_4 -prefix +// Inverter_3lvl_P0N_3lvl_0_4_ Inverter_3lvl_P0N_3lvl_0_4_stub.v +// Design : Inverter_3lvl_P0N_3lvl_0_4 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "P0N_3lvl,Vivado 2019.1" *) +module Inverter_3lvl_P0N_3lvl_0_4(externalCLK, ready, reset, deadTime, minTime, er, + minTime_En, minTimeEr, TKin0, TKin1, breaking_en, PWM_out_0, PWM_out_1, PWM_out_2, PWM_out_3) +/* synthesis syn_black_box black_box_pad_pin="externalCLK,ready,reset,deadTime[31:0],minTime[31:0],er,minTime_En,minTimeEr,TKin0,TKin1,breaking_en,PWM_out_0,PWM_out_1,PWM_out_2,PWM_out_3" */; + input externalCLK; + input ready; + input reset; + input [31:0]deadTime; + input [31:0]minTime; + input er; + input minTime_En; + output minTimeEr; + input TKin0; + input TKin1; + input breaking_en; + output PWM_out_0; + output PWM_out_1; + output PWM_out_2; + output PWM_out_3; +endmodule diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_stub.vhdl b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_stub.vhdl new file mode 100644 index 0000000..ce4a751 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_4/Inverter_3lvl_P0N_3lvl_0_4_stub.vhdl @@ -0,0 +1,44 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Fri Jun 11 07:49:57 2021 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top Inverter_3lvl_P0N_3lvl_0_4 -prefix +-- Inverter_3lvl_P0N_3lvl_0_4_ Inverter_3lvl_P0N_3lvl_0_4_stub.vhdl +-- Design : Inverter_3lvl_P0N_3lvl_0_4 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Inverter_3lvl_P0N_3lvl_0_4 is + Port ( + externalCLK : in STD_LOGIC; + ready : in STD_LOGIC; + reset : in STD_LOGIC; + deadTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + minTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + er : in STD_LOGIC; + minTime_En : in STD_LOGIC; + minTimeEr : out STD_LOGIC; + TKin0 : in STD_LOGIC; + TKin1 : in STD_LOGIC; + breaking_en : in STD_LOGIC; + PWM_out_0 : out STD_LOGIC; + PWM_out_1 : out STD_LOGIC; + PWM_out_2 : out STD_LOGIC; + PWM_out_3 : out STD_LOGIC + ); + +end Inverter_3lvl_P0N_3lvl_0_4; + +architecture stub of Inverter_3lvl_P0N_3lvl_0_4 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "externalCLK,ready,reset,deadTime[31:0],minTime[31:0],er,minTime_En,minTimeEr,TKin0,TKin1,breaking_en,PWM_out_0,PWM_out_1,PWM_out_2,PWM_out_3"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "P0N_3lvl,Vivado 2019.1"; +begin +end; diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/Inverter_3lvl_P0N_3lvl_0_5.dcp b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5.dcp similarity index 99% rename from LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_5_synth_1/Inverter_3lvl_P0N_3lvl_0_5.dcp rename to LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5.dcp index 3f4693fe18c0b0a14780b0cfb6cf70e11593276f..c3293e2fec1d9f07e3dff61364f1966e0af012fc 100644 GIT binary patch delta 28 hcmdn8n0d=$<_%G2Sf<4;4%-}eMw}JQnp}C&8UVQ84153p delta 28 hcmdn8n0d=$<_%G2SUl`b2W^f!BhCtDO|HCX4FIt#3+ey> diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5.xml b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5.xml index 7ccc5fc..6f34d23 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5.xml +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5.xml @@ -133,6 +133,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:44:45 UTC 2023 + + + outputProductCRC + 9:dcff1806 + + + @@ -407,6 +425,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + Inverter_3lvl_P0N_3lvl_0_5.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_0_5_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_0_5_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_0_5_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_0_5_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + P0N_3lvl_v1_0 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5_sim_netlist.v b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5_sim_netlist.v new file mode 100644 index 0000000..305c5a8 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5_sim_netlist.v @@ -0,0 +1,3131 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Fri Jun 11 07:49:57 2021 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top Inverter_3lvl_P0N_3lvl_0_5 -prefix +// Inverter_3lvl_P0N_3lvl_0_5_ Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.v +// Design : Inverter_3lvl_P0N_3lvl_0_4 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "Inverter_3lvl_P0N_3lvl_0_4,P0N_3lvl,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "P0N_3lvl,Vivado 2019.1" *) +(* NotValidForBitStream *) +module Inverter_3lvl_P0N_3lvl_0_5 + (externalCLK, + ready, + reset, + deadTime, + minTime, + er, + minTime_En, + minTimeEr, + TKin0, + TKin1, + breaking_en, + PWM_out_0, + PWM_out_1, + PWM_out_2, + PWM_out_3); + input externalCLK; + input ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + input [31:0]deadTime; + input [31:0]minTime; + input er; + input minTime_En; + output minTimeEr; + input TKin0; + input TKin1; + input breaking_en; + output PWM_out_0; + output PWM_out_1; + output PWM_out_2; + output PWM_out_3; + + wire PWM_out_0; + wire PWM_out_1; + wire PWM_out_2; + wire PWM_out_3; + wire TKin0; + wire TKin1; + wire breaking_en; + wire [31:0]deadTime; + wire er; + wire externalCLK; + wire [31:0]minTime; + wire minTimeEr; + wire minTime_En; + wire ready; + wire reset; + + Inverter_3lvl_P0N_3lvl_0_5_P0N_3lvl U0 + (.PWM_out_0(PWM_out_0), + .PWM_out_1(PWM_out_1), + .PWM_out_2(PWM_out_2), + .PWM_out_3(PWM_out_3), + .TKin0(TKin0), + .TKin1(TKin1), + .breaking_en(breaking_en), + .deadTime(deadTime), + .er(er), + .externalCLK(externalCLK), + .minTime(minTime), + .minTimeEr_reg_0(minTimeEr), + .minTime_En(minTime_En), + .ready(ready), + .reset(reset)); +endmodule + +module Inverter_3lvl_P0N_3lvl_0_5_P0N_3lvl + (minTimeEr_reg_0, + PWM_out_0, + PWM_out_1, + PWM_out_2, + PWM_out_3, + reset, + externalCLK, + TKin0, + TKin1, + breaking_en, + er, + ready, + minTime_En, + deadTime, + minTime); + output minTimeEr_reg_0; + output PWM_out_0; + output PWM_out_1; + output PWM_out_2; + output PWM_out_3; + input reset; + input externalCLK; + input TKin0; + input TKin1; + input breaking_en; + input er; + input ready; + input minTime_En; + input [31:0]deadTime; + input [31:0]minTime; + + wire \FSM_onehot_lineconfig[0]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[0]_i_2_n_0 ; + wire \FSM_onehot_lineconfig[1]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[2]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[2]_i_2_n_0 ; + wire \FSM_onehot_lineconfig[3]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[4]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[5]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[5]_i_2_n_0 ; + wire \FSM_onehot_lineconfig[5]_i_3_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_2_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_3_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_4_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_5_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_6_n_0 ; + wire \FSM_onehot_lineconfig_reg_n_0_[0] ; + wire \FSM_onehot_lineconfig_reg_n_0_[1] ; + wire \FSM_onehot_lineconfig_reg_n_0_[2] ; + wire \FSM_onehot_lineconfig_reg_n_0_[3] ; + wire \FSM_onehot_lineconfig_reg_n_0_[4] ; + wire \FSM_onehot_lineconfig_reg_n_0_[5] ; + wire \FSM_onehot_lineconfig_reg_n_0_[6] ; + wire PWM_out_0; + wire PWM_out_0_i_1_n_0; + wire PWM_out_1; + wire PWM_out_1_i_1_n_0; + wire PWM_out_2; + wire PWM_out_2_i_1_n_0; + wire PWM_out_3; + wire PWM_out_3_i_1_n_0; + wire TKin0; + wire TKin0_triggered; + wire TKin0_triggered28_out; + wire TKin0_triggered_i_1_n_0; + wire TKin1; + wire TKin1_triggered; + wire TKin1_triggered_i_1_n_0; + wire \TimeCounter[0]_i_2_n_0 ; + wire [31:0]TimeCounter_reg; + wire \TimeCounter_reg[0]_i_1_n_0 ; + wire \TimeCounter_reg[0]_i_1_n_1 ; + wire \TimeCounter_reg[0]_i_1_n_2 ; + wire \TimeCounter_reg[0]_i_1_n_3 ; + wire \TimeCounter_reg[0]_i_1_n_4 ; + wire \TimeCounter_reg[0]_i_1_n_5 ; + wire \TimeCounter_reg[0]_i_1_n_6 ; + wire \TimeCounter_reg[0]_i_1_n_7 ; + wire \TimeCounter_reg[12]_i_1_n_0 ; + wire \TimeCounter_reg[12]_i_1_n_1 ; + wire \TimeCounter_reg[12]_i_1_n_2 ; + wire \TimeCounter_reg[12]_i_1_n_3 ; + wire \TimeCounter_reg[12]_i_1_n_4 ; + wire \TimeCounter_reg[12]_i_1_n_5 ; + wire \TimeCounter_reg[12]_i_1_n_6 ; + wire \TimeCounter_reg[12]_i_1_n_7 ; + wire \TimeCounter_reg[16]_i_1_n_0 ; + wire \TimeCounter_reg[16]_i_1_n_1 ; + wire \TimeCounter_reg[16]_i_1_n_2 ; + wire \TimeCounter_reg[16]_i_1_n_3 ; + wire \TimeCounter_reg[16]_i_1_n_4 ; + wire \TimeCounter_reg[16]_i_1_n_5 ; + wire \TimeCounter_reg[16]_i_1_n_6 ; + wire \TimeCounter_reg[16]_i_1_n_7 ; + wire \TimeCounter_reg[20]_i_1_n_0 ; + wire \TimeCounter_reg[20]_i_1_n_1 ; + wire \TimeCounter_reg[20]_i_1_n_2 ; + wire \TimeCounter_reg[20]_i_1_n_3 ; + wire \TimeCounter_reg[20]_i_1_n_4 ; + wire \TimeCounter_reg[20]_i_1_n_5 ; + wire \TimeCounter_reg[20]_i_1_n_6 ; + wire \TimeCounter_reg[20]_i_1_n_7 ; + wire \TimeCounter_reg[24]_i_1_n_0 ; + wire \TimeCounter_reg[24]_i_1_n_1 ; + wire \TimeCounter_reg[24]_i_1_n_2 ; + wire \TimeCounter_reg[24]_i_1_n_3 ; + wire \TimeCounter_reg[24]_i_1_n_4 ; + wire \TimeCounter_reg[24]_i_1_n_5 ; + wire \TimeCounter_reg[24]_i_1_n_6 ; + wire \TimeCounter_reg[24]_i_1_n_7 ; + wire \TimeCounter_reg[28]_i_1_n_1 ; + wire \TimeCounter_reg[28]_i_1_n_2 ; + wire \TimeCounter_reg[28]_i_1_n_3 ; + wire \TimeCounter_reg[28]_i_1_n_4 ; + wire \TimeCounter_reg[28]_i_1_n_5 ; + wire \TimeCounter_reg[28]_i_1_n_6 ; + wire \TimeCounter_reg[28]_i_1_n_7 ; + wire \TimeCounter_reg[4]_i_1_n_0 ; + wire \TimeCounter_reg[4]_i_1_n_1 ; + wire \TimeCounter_reg[4]_i_1_n_2 ; + wire \TimeCounter_reg[4]_i_1_n_3 ; + wire \TimeCounter_reg[4]_i_1_n_4 ; + wire \TimeCounter_reg[4]_i_1_n_5 ; + wire \TimeCounter_reg[4]_i_1_n_6 ; + wire \TimeCounter_reg[4]_i_1_n_7 ; + wire \TimeCounter_reg[8]_i_1_n_0 ; + wire \TimeCounter_reg[8]_i_1_n_1 ; + wire \TimeCounter_reg[8]_i_1_n_2 ; + wire \TimeCounter_reg[8]_i_1_n_3 ; + wire \TimeCounter_reg[8]_i_1_n_4 ; + wire \TimeCounter_reg[8]_i_1_n_5 ; + wire \TimeCounter_reg[8]_i_1_n_6 ; + wire \TimeCounter_reg[8]_i_1_n_7 ; + wire breaking_en; + wire [31:0]deadTime; + wire deadTimeCounterReset_i_1_n_0; + wire deadTimeCounterReset_i_2_n_0; + wire deadTimeCounterReset_i_3_n_0; + wire deadTimeCounterReset_i_4_n_0; + wire deadTimeCounterReset_i_5_n_0; + wire deadTimeCounterReset_i_6_n_0; + wire deadTimeCounterReset_i_7_n_0; + wire deadTimeCounterReset_reg_n_0; + wire deadTimeOK; + wire deadTimeOK_i_1_n_0; + wire er; + wire externalCLK; + wire key1_i_1_n_0; + wire key1_i_2_n_0; + wire key1_prev; + wire key1_reg_n_0; + wire key2_i_2_n_0; + wire key2_prev; + wire key2_reg_n_0; + wire key3; + wire key3_i_1_n_0; + wire key3_prev; + wire key3_reg_n_0; + wire key4_i_1_n_0; + wire key4_prev; + wire key4_reg_n_0; + wire ltOp__15_carry__0_i_1_n_0; + wire ltOp__15_carry__0_i_2_n_0; + wire ltOp__15_carry__0_i_3_n_0; + wire ltOp__15_carry__0_i_4_n_0; + wire ltOp__15_carry__0_i_5_n_0; + wire ltOp__15_carry__0_i_6_n_0; + wire ltOp__15_carry__0_i_7_n_0; + wire ltOp__15_carry__0_i_8_n_0; + wire ltOp__15_carry__0_n_0; + wire ltOp__15_carry__0_n_1; + wire ltOp__15_carry__0_n_2; + wire ltOp__15_carry__0_n_3; + wire ltOp__15_carry__1_i_1_n_0; + wire ltOp__15_carry__1_i_2_n_0; + wire ltOp__15_carry__1_i_3_n_0; + wire ltOp__15_carry__1_i_4_n_0; + wire ltOp__15_carry__1_i_5_n_0; + wire ltOp__15_carry__1_i_6_n_0; + wire ltOp__15_carry__1_i_7_n_0; + wire ltOp__15_carry__1_i_8_n_0; + wire ltOp__15_carry__1_n_0; + wire ltOp__15_carry__1_n_1; + wire ltOp__15_carry__1_n_2; + wire ltOp__15_carry__1_n_3; + wire ltOp__15_carry__2_i_1_n_0; + wire ltOp__15_carry__2_i_2_n_0; + wire ltOp__15_carry__2_i_3_n_0; + wire ltOp__15_carry__2_i_4_n_0; + wire ltOp__15_carry__2_i_5_n_0; + wire ltOp__15_carry__2_i_6_n_0; + wire ltOp__15_carry__2_i_7_n_0; + wire ltOp__15_carry__2_i_8_n_0; + wire ltOp__15_carry__2_n_0; + wire ltOp__15_carry__2_n_1; + wire ltOp__15_carry__2_n_2; + wire ltOp__15_carry__2_n_3; + wire ltOp__15_carry_i_1_n_0; + wire ltOp__15_carry_i_2_n_0; + wire ltOp__15_carry_i_3_n_0; + wire ltOp__15_carry_i_4_n_0; + wire ltOp__15_carry_i_5_n_0; + wire ltOp__15_carry_i_6_n_0; + wire ltOp__15_carry_i_7_n_0; + wire ltOp__15_carry_i_8_n_0; + wire ltOp__15_carry_n_0; + wire ltOp__15_carry_n_1; + wire ltOp__15_carry_n_2; + wire ltOp__15_carry_n_3; + wire ltOp__31_carry__0_n_0; + wire ltOp__31_carry__0_n_1; + wire ltOp__31_carry__0_n_2; + wire ltOp__31_carry__0_n_3; + wire ltOp__31_carry__1_n_0; + wire ltOp__31_carry__1_n_1; + wire ltOp__31_carry__1_n_2; + wire ltOp__31_carry__1_n_3; + wire ltOp__31_carry__2_n_0; + wire ltOp__31_carry__2_n_1; + wire ltOp__31_carry__2_n_2; + wire ltOp__31_carry__2_n_3; + wire ltOp__31_carry_i_1__0_n_0; + wire ltOp__31_carry_i_1__1_n_0; + wire ltOp__31_carry_i_1__2_n_0; + wire ltOp__31_carry_i_1_n_0; + wire ltOp__31_carry_i_2__0_n_0; + wire ltOp__31_carry_i_2__1_n_0; + wire ltOp__31_carry_i_2__2_n_0; + wire ltOp__31_carry_i_2_n_0; + wire ltOp__31_carry_i_3__0_n_0; + wire ltOp__31_carry_i_3__1_n_0; + wire ltOp__31_carry_i_3__2_n_0; + wire ltOp__31_carry_i_3_n_0; + wire ltOp__31_carry_i_4__0_n_0; + wire ltOp__31_carry_i_4__1_n_0; + wire ltOp__31_carry_i_4__2_n_0; + wire ltOp__31_carry_i_4_n_0; + wire ltOp__31_carry_i_5__0_n_0; + wire ltOp__31_carry_i_5__1_n_0; + wire ltOp__31_carry_i_5__2_n_0; + wire ltOp__31_carry_i_5_n_0; + wire ltOp__31_carry_i_6__0_n_0; + wire ltOp__31_carry_i_6__1_n_0; + wire ltOp__31_carry_i_6__2_n_0; + wire ltOp__31_carry_i_6_n_0; + wire ltOp__31_carry_i_7__0_n_0; + wire ltOp__31_carry_i_7__1_n_0; + wire ltOp__31_carry_i_7__2_n_0; + wire ltOp__31_carry_i_7_n_0; + wire ltOp__31_carry_i_8__0_n_0; + wire ltOp__31_carry_i_8__1_n_0; + wire ltOp__31_carry_i_8__2_n_0; + wire ltOp__31_carry_i_8_n_0; + wire ltOp__31_carry_n_0; + wire ltOp__31_carry_n_1; + wire ltOp__31_carry_n_2; + wire ltOp__31_carry_n_3; + wire ltOp_carry__0_i_1_n_0; + wire ltOp_carry__0_i_2_n_0; + wire ltOp_carry__0_i_3_n_0; + wire ltOp_carry__0_i_4_n_0; + wire ltOp_carry__0_i_5_n_0; + wire ltOp_carry__0_i_6_n_0; + wire ltOp_carry__0_i_7_n_0; + wire ltOp_carry__0_i_8_n_0; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_i_1_n_0; + wire ltOp_carry__1_i_2_n_0; + wire ltOp_carry__1_i_3_n_0; + wire ltOp_carry__1_i_4_n_0; + wire ltOp_carry__1_i_5_n_0; + wire ltOp_carry__1_i_6_n_0; + wire ltOp_carry__1_i_7_n_0; + wire ltOp_carry__1_i_8_n_0; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_i_1_n_0; + wire ltOp_carry__2_i_2_n_0; + wire ltOp_carry__2_i_3_n_0; + wire ltOp_carry__2_i_4_n_0; + wire ltOp_carry__2_i_5_n_0; + wire ltOp_carry__2_i_6_n_0; + wire ltOp_carry__2_i_7_n_0; + wire ltOp_carry__2_i_8_n_0; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [31:0]minTime; + wire minTimeCounter_high; + wire \minTimeCounter_high[0]_i_1_n_0 ; + wire \minTimeCounter_high[0]_i_4_n_0 ; + wire [31:0]minTimeCounter_high_reg; + wire \minTimeCounter_high_reg[0]_i_3_n_0 ; + wire \minTimeCounter_high_reg[0]_i_3_n_1 ; + wire \minTimeCounter_high_reg[0]_i_3_n_2 ; + wire \minTimeCounter_high_reg[0]_i_3_n_3 ; + wire \minTimeCounter_high_reg[0]_i_3_n_4 ; + wire \minTimeCounter_high_reg[0]_i_3_n_5 ; + wire \minTimeCounter_high_reg[0]_i_3_n_6 ; + wire \minTimeCounter_high_reg[0]_i_3_n_7 ; + wire \minTimeCounter_high_reg[12]_i_1_n_0 ; + wire \minTimeCounter_high_reg[12]_i_1_n_1 ; + wire \minTimeCounter_high_reg[12]_i_1_n_2 ; + wire \minTimeCounter_high_reg[12]_i_1_n_3 ; + wire \minTimeCounter_high_reg[12]_i_1_n_4 ; + wire \minTimeCounter_high_reg[12]_i_1_n_5 ; + wire \minTimeCounter_high_reg[12]_i_1_n_6 ; + wire \minTimeCounter_high_reg[12]_i_1_n_7 ; + wire \minTimeCounter_high_reg[16]_i_1_n_0 ; + wire \minTimeCounter_high_reg[16]_i_1_n_1 ; + wire \minTimeCounter_high_reg[16]_i_1_n_2 ; + wire \minTimeCounter_high_reg[16]_i_1_n_3 ; + wire \minTimeCounter_high_reg[16]_i_1_n_4 ; + wire \minTimeCounter_high_reg[16]_i_1_n_5 ; + wire \minTimeCounter_high_reg[16]_i_1_n_6 ; + wire \minTimeCounter_high_reg[16]_i_1_n_7 ; + wire \minTimeCounter_high_reg[20]_i_1_n_0 ; + wire \minTimeCounter_high_reg[20]_i_1_n_1 ; + wire \minTimeCounter_high_reg[20]_i_1_n_2 ; + wire \minTimeCounter_high_reg[20]_i_1_n_3 ; + wire \minTimeCounter_high_reg[20]_i_1_n_4 ; + wire \minTimeCounter_high_reg[20]_i_1_n_5 ; + wire \minTimeCounter_high_reg[20]_i_1_n_6 ; + wire \minTimeCounter_high_reg[20]_i_1_n_7 ; + wire \minTimeCounter_high_reg[24]_i_1_n_0 ; + wire \minTimeCounter_high_reg[24]_i_1_n_1 ; + wire \minTimeCounter_high_reg[24]_i_1_n_2 ; + wire \minTimeCounter_high_reg[24]_i_1_n_3 ; + wire \minTimeCounter_high_reg[24]_i_1_n_4 ; + wire \minTimeCounter_high_reg[24]_i_1_n_5 ; + wire \minTimeCounter_high_reg[24]_i_1_n_6 ; + wire \minTimeCounter_high_reg[24]_i_1_n_7 ; + wire \minTimeCounter_high_reg[28]_i_1_n_1 ; + wire \minTimeCounter_high_reg[28]_i_1_n_2 ; + wire \minTimeCounter_high_reg[28]_i_1_n_3 ; + wire \minTimeCounter_high_reg[28]_i_1_n_4 ; + wire \minTimeCounter_high_reg[28]_i_1_n_5 ; + wire \minTimeCounter_high_reg[28]_i_1_n_6 ; + wire \minTimeCounter_high_reg[28]_i_1_n_7 ; + wire \minTimeCounter_high_reg[4]_i_1_n_0 ; + wire \minTimeCounter_high_reg[4]_i_1_n_1 ; + wire \minTimeCounter_high_reg[4]_i_1_n_2 ; + wire \minTimeCounter_high_reg[4]_i_1_n_3 ; + wire \minTimeCounter_high_reg[4]_i_1_n_4 ; + wire \minTimeCounter_high_reg[4]_i_1_n_5 ; + wire \minTimeCounter_high_reg[4]_i_1_n_6 ; + wire \minTimeCounter_high_reg[4]_i_1_n_7 ; + wire \minTimeCounter_high_reg[8]_i_1_n_0 ; + wire \minTimeCounter_high_reg[8]_i_1_n_1 ; + wire \minTimeCounter_high_reg[8]_i_1_n_2 ; + wire \minTimeCounter_high_reg[8]_i_1_n_3 ; + wire \minTimeCounter_high_reg[8]_i_1_n_4 ; + wire \minTimeCounter_high_reg[8]_i_1_n_5 ; + wire \minTimeCounter_high_reg[8]_i_1_n_6 ; + wire \minTimeCounter_high_reg[8]_i_1_n_7 ; + wire minTimeCounter_low; + wire \minTimeCounter_low[0]_i_1_n_0 ; + wire \minTimeCounter_low[0]_i_4_n_0 ; + wire \minTimeCounter_low[0]_i_5_n_0 ; + wire [31:0]minTimeCounter_low_reg; + wire \minTimeCounter_low_reg[0]_i_3_n_0 ; + wire \minTimeCounter_low_reg[0]_i_3_n_1 ; + wire \minTimeCounter_low_reg[0]_i_3_n_2 ; + wire \minTimeCounter_low_reg[0]_i_3_n_3 ; + wire \minTimeCounter_low_reg[0]_i_3_n_4 ; + wire \minTimeCounter_low_reg[0]_i_3_n_5 ; + wire \minTimeCounter_low_reg[0]_i_3_n_6 ; + wire \minTimeCounter_low_reg[0]_i_3_n_7 ; + wire \minTimeCounter_low_reg[12]_i_1_n_0 ; + wire \minTimeCounter_low_reg[12]_i_1_n_1 ; + wire \minTimeCounter_low_reg[12]_i_1_n_2 ; + wire \minTimeCounter_low_reg[12]_i_1_n_3 ; + wire \minTimeCounter_low_reg[12]_i_1_n_4 ; + wire \minTimeCounter_low_reg[12]_i_1_n_5 ; + wire \minTimeCounter_low_reg[12]_i_1_n_6 ; + wire \minTimeCounter_low_reg[12]_i_1_n_7 ; + wire \minTimeCounter_low_reg[16]_i_1_n_0 ; + wire \minTimeCounter_low_reg[16]_i_1_n_1 ; + wire \minTimeCounter_low_reg[16]_i_1_n_2 ; + wire \minTimeCounter_low_reg[16]_i_1_n_3 ; + wire \minTimeCounter_low_reg[16]_i_1_n_4 ; + wire \minTimeCounter_low_reg[16]_i_1_n_5 ; + wire \minTimeCounter_low_reg[16]_i_1_n_6 ; + wire \minTimeCounter_low_reg[16]_i_1_n_7 ; + wire \minTimeCounter_low_reg[20]_i_1_n_0 ; + wire \minTimeCounter_low_reg[20]_i_1_n_1 ; + wire \minTimeCounter_low_reg[20]_i_1_n_2 ; + wire \minTimeCounter_low_reg[20]_i_1_n_3 ; + wire \minTimeCounter_low_reg[20]_i_1_n_4 ; + wire \minTimeCounter_low_reg[20]_i_1_n_5 ; + wire \minTimeCounter_low_reg[20]_i_1_n_6 ; + wire \minTimeCounter_low_reg[20]_i_1_n_7 ; + wire \minTimeCounter_low_reg[24]_i_1_n_0 ; + wire \minTimeCounter_low_reg[24]_i_1_n_1 ; + wire \minTimeCounter_low_reg[24]_i_1_n_2 ; + wire \minTimeCounter_low_reg[24]_i_1_n_3 ; + wire \minTimeCounter_low_reg[24]_i_1_n_4 ; + wire \minTimeCounter_low_reg[24]_i_1_n_5 ; + wire \minTimeCounter_low_reg[24]_i_1_n_6 ; + wire \minTimeCounter_low_reg[24]_i_1_n_7 ; + wire \minTimeCounter_low_reg[28]_i_1_n_1 ; + wire \minTimeCounter_low_reg[28]_i_1_n_2 ; + wire \minTimeCounter_low_reg[28]_i_1_n_3 ; + wire \minTimeCounter_low_reg[28]_i_1_n_4 ; + wire \minTimeCounter_low_reg[28]_i_1_n_5 ; + wire \minTimeCounter_low_reg[28]_i_1_n_6 ; + wire \minTimeCounter_low_reg[28]_i_1_n_7 ; + wire \minTimeCounter_low_reg[4]_i_1_n_0 ; + wire \minTimeCounter_low_reg[4]_i_1_n_1 ; + wire \minTimeCounter_low_reg[4]_i_1_n_2 ; + wire \minTimeCounter_low_reg[4]_i_1_n_3 ; + wire \minTimeCounter_low_reg[4]_i_1_n_4 ; + wire \minTimeCounter_low_reg[4]_i_1_n_5 ; + wire \minTimeCounter_low_reg[4]_i_1_n_6 ; + wire \minTimeCounter_low_reg[4]_i_1_n_7 ; + wire \minTimeCounter_low_reg[8]_i_1_n_0 ; + wire \minTimeCounter_low_reg[8]_i_1_n_1 ; + wire \minTimeCounter_low_reg[8]_i_1_n_2 ; + wire \minTimeCounter_low_reg[8]_i_1_n_3 ; + wire \minTimeCounter_low_reg[8]_i_1_n_4 ; + wire \minTimeCounter_low_reg[8]_i_1_n_5 ; + wire \minTimeCounter_low_reg[8]_i_1_n_6 ; + wire \minTimeCounter_low_reg[8]_i_1_n_7 ; + wire minTimeEr_i_1_n_0; + wire minTimeEr_i_2_n_0; + wire minTimeEr_i_3_n_0; + wire minTimeEr_i_4_n_0; + wire minTimeEr_i_5_n_0; + wire minTimeEr_i_6_n_0; + wire minTimeEr_i_7_n_0; + wire minTimeEr_i_8_n_0; + wire minTimeEr_i_9_n_0; + wire minTimeEr_reg_0; + wire minTimeOK_high; + wire minTimeOK_high_i_1_n_0; + wire minTimeOK_low; + wire minTimeOK_low_i_1_n_0; + wire minTime_En; + wire p_0_in; + wire ready; + wire reset; + wire sel; + wire [3:3]\NLW_TimeCounter_reg[28]_i_1_CO_UNCONNECTED ; + wire [3:0]NLW_ltOp__15_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp__15_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp__15_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp__15_carry__2_O_UNCONNECTED; + wire [3:0]NLW_ltOp__31_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp__31_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp__31_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp__31_carry__2_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + wire [3:3]\NLW_minTimeCounter_high_reg[28]_i_1_CO_UNCONNECTED ; + wire [3:3]\NLW_minTimeCounter_low_reg[28]_i_1_CO_UNCONNECTED ; + + LUT6 #( + .INIT(64'hFFFFFFFE00000000)) + \FSM_onehot_lineconfig[0]_i_1 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I4(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I5(\FSM_onehot_lineconfig[0]_i_2_n_0 ), + .O(\FSM_onehot_lineconfig[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_lineconfig[0]_i_2 + (.I0(TKin1), + .I1(TKin0), + .O(\FSM_onehot_lineconfig[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'h1000FFFF00000000)) + \FSM_onehot_lineconfig[1]_i_1 + (.I0(TKin1), + .I1(TKin1_triggered), + .I2(TKin0_triggered), + .I3(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I4(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I5(TKin0), + .O(\FSM_onehot_lineconfig[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h00EFEF0F)) + \FSM_onehot_lineconfig[2]_i_1 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I2(\FSM_onehot_lineconfig[2]_i_2_n_0 ), + .I3(TKin0), + .I4(TKin1), + .O(\FSM_onehot_lineconfig[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'h900990099009FFFF)) + \FSM_onehot_lineconfig[2]_i_2 + (.I0(TKin1), + .I1(TKin1_triggered), + .I2(TKin0), + .I3(TKin0_triggered), + .I4(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I5(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .O(\FSM_onehot_lineconfig[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0000000055D50000)) + \FSM_onehot_lineconfig[3]_i_1 + (.I0(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I2(TKin1_triggered), + .I3(TKin0_triggered), + .I4(TKin1), + .I5(TKin0), + .O(\FSM_onehot_lineconfig[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT4 #( + .INIT(16'h2230)) + \FSM_onehot_lineconfig[4]_i_1 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I1(TKin0), + .I2(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I3(TKin1), + .O(\FSM_onehot_lineconfig[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0CFF0C0D00050005)) + \FSM_onehot_lineconfig[5]_i_1 + (.I0(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I2(TKin1), + .I3(TKin0), + .I4(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I5(\FSM_onehot_lineconfig[5]_i_3_n_0 ), + .O(\FSM_onehot_lineconfig[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h1)) + \FSM_onehot_lineconfig[5]_i_2 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .O(\FSM_onehot_lineconfig[5]_i_2_n_0 )); + LUT4 #( + .INIT(16'h9009)) + \FSM_onehot_lineconfig[5]_i_3 + (.I0(TKin0_triggered), + .I1(TKin0), + .I2(TKin1_triggered), + .I3(TKin1), + .O(\FSM_onehot_lineconfig[5]_i_3_n_0 )); + LUT3 #( + .INIT(8'h0E)) + \FSM_onehot_lineconfig[6]_i_1 + (.I0(\FSM_onehot_lineconfig[6]_i_3_n_0 ), + .I1(\FSM_onehot_lineconfig[6]_i_4_n_0 ), + .I2(breaking_en), + .O(\FSM_onehot_lineconfig[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT4 #( + .INIT(16'h5504)) + \FSM_onehot_lineconfig[6]_i_2 + (.I0(TKin1), + .I1(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I2(TKin0), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .O(\FSM_onehot_lineconfig[6]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'hFFFEECAE)) + \FSM_onehot_lineconfig[6]_i_3 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I2(TKin1), + .I3(TKin0), + .I4(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .O(\FSM_onehot_lineconfig[6]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAABAAAAAFFFFAAAA)) + \FSM_onehot_lineconfig[6]_i_4 + (.I0(\FSM_onehot_lineconfig[6]_i_5_n_0 ), + .I1(er), + .I2(ready), + .I3(\FSM_onehot_lineconfig[6]_i_6_n_0 ), + .I4(deadTimeOK), + .I5(\FSM_onehot_lineconfig[2]_i_2_n_0 ), + .O(\FSM_onehot_lineconfig[6]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFC88A0A8)) + \FSM_onehot_lineconfig[6]_i_5 + (.I0(deadTimeOK), + .I1(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I3(TKin1), + .I4(TKin0), + .O(\FSM_onehot_lineconfig[6]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'hFF232323)) + \FSM_onehot_lineconfig[6]_i_6 + (.I0(deadTimeCounterReset_reg_n_0), + .I1(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I3(TKin1), + .I4(TKin0), + .O(\FSM_onehot_lineconfig[6]_i_6_n_0 )); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDSE #( + .INIT(1'b1)) + \FSM_onehot_lineconfig_reg[0] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[0]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .S(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[1] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[1]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[2] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[2]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[3] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[3]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[4] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[4]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[5] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[5]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[6] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[6]_i_2_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT4 #( + .INIT(16'hFFEF)) + PWM_out_0_i_1 + (.I0(key1_reg_n_0), + .I1(er), + .I2(ready), + .I3(minTimeEr_reg_0), + .O(PWM_out_0_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + PWM_out_0_reg + (.C(externalCLK), + .CE(1'b1), + .D(PWM_out_0_i_1_n_0), + .Q(PWM_out_0), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT4 #( + .INIT(16'hFFEF)) + PWM_out_1_i_1 + (.I0(key2_reg_n_0), + .I1(er), + .I2(ready), + .I3(minTimeEr_reg_0), + .O(PWM_out_1_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + PWM_out_1_reg + (.C(externalCLK), + .CE(1'b1), + .D(PWM_out_1_i_1_n_0), + .Q(PWM_out_1), + .R(1'b0)); + LUT5 #( + .INIT(32'hFFFFFFEF)) + PWM_out_2_i_1 + (.I0(key3_reg_n_0), + .I1(minTimeEr_reg_0), + .I2(ready), + .I3(er), + .I4(breaking_en), + .O(PWM_out_2_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + PWM_out_2_reg + (.C(externalCLK), + .CE(1'b1), + .D(PWM_out_2_i_1_n_0), + .Q(PWM_out_2), + .R(1'b0)); + LUT5 #( + .INIT(32'hFFFFFFEF)) + PWM_out_3_i_1 + (.I0(key4_reg_n_0), + .I1(minTimeEr_reg_0), + .I2(ready), + .I3(er), + .I4(breaking_en), + .O(PWM_out_3_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + PWM_out_3_reg + (.C(externalCLK), + .CE(1'b1), + .D(PWM_out_3_i_1_n_0), + .Q(PWM_out_3), + .R(1'b0)); + LUT6 #( + .INIT(64'hAA08FFFFAA080000)) + TKin0_triggered_i_1 + (.I0(TKin0), + .I1(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I2(TKin1), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I4(TKin0_triggered28_out), + .I5(TKin0_triggered), + .O(TKin0_triggered_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + TKin0_triggered_reg + (.C(externalCLK), + .CE(1'b1), + .D(TKin0_triggered_i_1_n_0), + .Q(TKin0_triggered), + .R(1'b0)); + LUT6 #( + .INIT(64'hAA08FFFFAA080000)) + TKin1_triggered_i_1 + (.I0(TKin1), + .I1(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I2(TKin0), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I4(TKin0_triggered28_out), + .I5(TKin1_triggered), + .O(TKin1_triggered_i_1_n_0)); + LUT6 #( + .INIT(64'h22AA22A820AA2020)) + TKin1_triggered_i_2 + (.I0(minTimeEr_i_9_n_0), + .I1(TKin1), + .I2(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I3(TKin0), + .I4(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I5(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .O(TKin0_triggered28_out)); + FDRE #( + .INIT(1'b1)) + TKin1_triggered_reg + (.C(externalCLK), + .CE(1'b1), + .D(TKin1_triggered_i_1_n_0), + .Q(TKin1_triggered), + .R(1'b0)); + LUT1 #( + .INIT(2'h1)) + \TimeCounter[0]_i_2 + (.I0(TimeCounter_reg[0]), + .O(\TimeCounter[0]_i_2_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[0] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[0]_i_1_n_7 ), + .Q(TimeCounter_reg[0]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[0]_i_1 + (.CI(1'b0), + .CO({\TimeCounter_reg[0]_i_1_n_0 ,\TimeCounter_reg[0]_i_1_n_1 ,\TimeCounter_reg[0]_i_1_n_2 ,\TimeCounter_reg[0]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\TimeCounter_reg[0]_i_1_n_4 ,\TimeCounter_reg[0]_i_1_n_5 ,\TimeCounter_reg[0]_i_1_n_6 ,\TimeCounter_reg[0]_i_1_n_7 }), + .S({TimeCounter_reg[3:1],\TimeCounter[0]_i_2_n_0 })); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[10] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[8]_i_1_n_5 ), + .Q(TimeCounter_reg[10]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[11] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[8]_i_1_n_4 ), + .Q(TimeCounter_reg[11]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[12] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[12]_i_1_n_7 ), + .Q(TimeCounter_reg[12]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[12]_i_1 + (.CI(\TimeCounter_reg[8]_i_1_n_0 ), + .CO({\TimeCounter_reg[12]_i_1_n_0 ,\TimeCounter_reg[12]_i_1_n_1 ,\TimeCounter_reg[12]_i_1_n_2 ,\TimeCounter_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[12]_i_1_n_4 ,\TimeCounter_reg[12]_i_1_n_5 ,\TimeCounter_reg[12]_i_1_n_6 ,\TimeCounter_reg[12]_i_1_n_7 }), + .S(TimeCounter_reg[15:12])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[13] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[12]_i_1_n_6 ), + .Q(TimeCounter_reg[13]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[14] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[12]_i_1_n_5 ), + .Q(TimeCounter_reg[14]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[15] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[12]_i_1_n_4 ), + .Q(TimeCounter_reg[15]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[16] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[16]_i_1_n_7 ), + .Q(TimeCounter_reg[16]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[16]_i_1 + (.CI(\TimeCounter_reg[12]_i_1_n_0 ), + .CO({\TimeCounter_reg[16]_i_1_n_0 ,\TimeCounter_reg[16]_i_1_n_1 ,\TimeCounter_reg[16]_i_1_n_2 ,\TimeCounter_reg[16]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[16]_i_1_n_4 ,\TimeCounter_reg[16]_i_1_n_5 ,\TimeCounter_reg[16]_i_1_n_6 ,\TimeCounter_reg[16]_i_1_n_7 }), + .S(TimeCounter_reg[19:16])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[17] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[16]_i_1_n_6 ), + .Q(TimeCounter_reg[17]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[18] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[16]_i_1_n_5 ), + .Q(TimeCounter_reg[18]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[19] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[16]_i_1_n_4 ), + .Q(TimeCounter_reg[19]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[1] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[0]_i_1_n_6 ), + .Q(TimeCounter_reg[1]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[20] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[20]_i_1_n_7 ), + .Q(TimeCounter_reg[20]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[20]_i_1 + (.CI(\TimeCounter_reg[16]_i_1_n_0 ), + .CO({\TimeCounter_reg[20]_i_1_n_0 ,\TimeCounter_reg[20]_i_1_n_1 ,\TimeCounter_reg[20]_i_1_n_2 ,\TimeCounter_reg[20]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[20]_i_1_n_4 ,\TimeCounter_reg[20]_i_1_n_5 ,\TimeCounter_reg[20]_i_1_n_6 ,\TimeCounter_reg[20]_i_1_n_7 }), + .S(TimeCounter_reg[23:20])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[21] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[20]_i_1_n_6 ), + .Q(TimeCounter_reg[21]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[22] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[20]_i_1_n_5 ), + .Q(TimeCounter_reg[22]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[23] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[20]_i_1_n_4 ), + .Q(TimeCounter_reg[23]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[24] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[24]_i_1_n_7 ), + .Q(TimeCounter_reg[24]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[24]_i_1 + (.CI(\TimeCounter_reg[20]_i_1_n_0 ), + .CO({\TimeCounter_reg[24]_i_1_n_0 ,\TimeCounter_reg[24]_i_1_n_1 ,\TimeCounter_reg[24]_i_1_n_2 ,\TimeCounter_reg[24]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[24]_i_1_n_4 ,\TimeCounter_reg[24]_i_1_n_5 ,\TimeCounter_reg[24]_i_1_n_6 ,\TimeCounter_reg[24]_i_1_n_7 }), + .S(TimeCounter_reg[27:24])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[25] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[24]_i_1_n_6 ), + .Q(TimeCounter_reg[25]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[26] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[24]_i_1_n_5 ), + .Q(TimeCounter_reg[26]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[27] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[24]_i_1_n_4 ), + .Q(TimeCounter_reg[27]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[28] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[28]_i_1_n_7 ), + .Q(TimeCounter_reg[28]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[28]_i_1 + (.CI(\TimeCounter_reg[24]_i_1_n_0 ), + .CO({\NLW_TimeCounter_reg[28]_i_1_CO_UNCONNECTED [3],\TimeCounter_reg[28]_i_1_n_1 ,\TimeCounter_reg[28]_i_1_n_2 ,\TimeCounter_reg[28]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[28]_i_1_n_4 ,\TimeCounter_reg[28]_i_1_n_5 ,\TimeCounter_reg[28]_i_1_n_6 ,\TimeCounter_reg[28]_i_1_n_7 }), + .S(TimeCounter_reg[31:28])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[29] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[28]_i_1_n_6 ), + .Q(TimeCounter_reg[29]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[2] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[0]_i_1_n_5 ), + .Q(TimeCounter_reg[2]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[30] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[28]_i_1_n_5 ), + .Q(TimeCounter_reg[30]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[31] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[28]_i_1_n_4 ), + .Q(TimeCounter_reg[31]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[3] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[0]_i_1_n_4 ), + .Q(TimeCounter_reg[3]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[4] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[4]_i_1_n_7 ), + .Q(TimeCounter_reg[4]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[4]_i_1 + (.CI(\TimeCounter_reg[0]_i_1_n_0 ), + .CO({\TimeCounter_reg[4]_i_1_n_0 ,\TimeCounter_reg[4]_i_1_n_1 ,\TimeCounter_reg[4]_i_1_n_2 ,\TimeCounter_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[4]_i_1_n_4 ,\TimeCounter_reg[4]_i_1_n_5 ,\TimeCounter_reg[4]_i_1_n_6 ,\TimeCounter_reg[4]_i_1_n_7 }), + .S(TimeCounter_reg[7:4])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[5] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[4]_i_1_n_6 ), + .Q(TimeCounter_reg[5]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[6] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[4]_i_1_n_5 ), + .Q(TimeCounter_reg[6]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[7] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[4]_i_1_n_4 ), + .Q(TimeCounter_reg[7]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[8] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[8]_i_1_n_7 ), + .Q(TimeCounter_reg[8]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[8]_i_1 + (.CI(\TimeCounter_reg[4]_i_1_n_0 ), + .CO({\TimeCounter_reg[8]_i_1_n_0 ,\TimeCounter_reg[8]_i_1_n_1 ,\TimeCounter_reg[8]_i_1_n_2 ,\TimeCounter_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[8]_i_1_n_4 ,\TimeCounter_reg[8]_i_1_n_5 ,\TimeCounter_reg[8]_i_1_n_6 ,\TimeCounter_reg[8]_i_1_n_7 }), + .S(TimeCounter_reg[11:8])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[9] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[8]_i_1_n_6 ), + .Q(TimeCounter_reg[9]), + .R(deadTimeCounterReset_reg_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFE0000000E)) + deadTimeCounterReset_i_1 + (.I0(deadTimeCounterReset_i_2_n_0), + .I1(\FSM_onehot_lineconfig[6]_i_4_n_0 ), + .I2(reset), + .I3(breaking_en), + .I4(deadTimeCounterReset_i_3_n_0), + .I5(deadTimeCounterReset_reg_n_0), + .O(deadTimeCounterReset_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'hFE)) + deadTimeCounterReset_i_2 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .O(deadTimeCounterReset_i_2_n_0)); + LUT6 #( + .INIT(64'h0000000022220020)) + deadTimeCounterReset_i_3 + (.I0(deadTimeCounterReset_i_4_n_0), + .I1(deadTimeCounterReset_i_2_n_0), + .I2(deadTimeCounterReset_i_5_n_0), + .I3(deadTimeCounterReset_i_6_n_0), + .I4(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I5(deadTimeCounterReset_i_7_n_0), + .O(deadTimeCounterReset_i_3_n_0)); + LUT6 #( + .INIT(64'h555D555555555555)) + deadTimeCounterReset_i_4 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I1(deadTimeOK), + .I2(TKin1), + .I3(TKin1_triggered), + .I4(TKin0), + .I5(TKin0_triggered), + .O(deadTimeCounterReset_i_4_n_0)); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT3 #( + .INIT(8'h08)) + deadTimeCounterReset_i_5 + (.I0(deadTimeOK), + .I1(ready), + .I2(er), + .O(deadTimeCounterReset_i_5_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT4 #( + .INIT(16'hF777)) + deadTimeCounterReset_i_6 + (.I0(TKin0), + .I1(TKin1), + .I2(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I3(deadTimeCounterReset_reg_n_0), + .O(deadTimeCounterReset_i_6_n_0)); + LUT6 #( + .INIT(64'hAAAAA2AAAAAAAAAA)) + deadTimeCounterReset_i_7 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I1(TKin1), + .I2(TKin0), + .I3(deadTimeOK), + .I4(TKin0_triggered), + .I5(TKin1_triggered), + .O(deadTimeCounterReset_i_7_n_0)); + FDRE #( + .INIT(1'b0)) + deadTimeCounterReset_reg + (.C(externalCLK), + .CE(1'b1), + .D(deadTimeCounterReset_i_1_n_0), + .Q(deadTimeCounterReset_reg_n_0), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT3 #( + .INIT(8'h0D)) + deadTimeOK_i_1 + (.I0(sel), + .I1(deadTimeOK), + .I2(deadTimeCounterReset_reg_n_0), + .O(deadTimeOK_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + deadTimeOK_reg + (.C(externalCLK), + .CE(1'b1), + .D(deadTimeOK_i_1_n_0), + .Q(deadTimeOK), + .R(1'b0)); + LUT6 #( + .INIT(64'hDDDDDDD0DDDDDDDD)) + key1_i_1 + (.I0(breaking_en), + .I1(TKin0), + .I2(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I4(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I5(key1_i_2_n_0), + .O(key1_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT4 #( + .INIT(16'h0001)) + key1_i_2 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I3(breaking_en), + .O(key1_i_2_n_0)); + FDRE #( + .INIT(1'b1)) + key1_prev_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key1_reg_n_0), + .Q(key1_prev), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + key1_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key1_i_1_n_0), + .Q(key1_reg_n_0), + .R(1'b0)); + LUT1 #( + .INIT(2'h1)) + key2_i_1 + (.I0(reset), + .O(p_0_in)); + LUT6 #( + .INIT(64'hAAAAAAAAFFFFFFFC)) + key2_i_2 + (.I0(TKin1), + .I1(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I4(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I5(breaking_en), + .O(key2_i_2_n_0)); + FDRE #( + .INIT(1'b1)) + key2_prev_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key2_reg_n_0), + .Q(key2_prev), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + key2_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key2_i_2_n_0), + .Q(key2_reg_n_0), + .R(1'b0)); + LUT6 #( + .INIT(64'hAAAAFFFFAAAAFCFF)) + key3_i_1 + (.I0(key3_reg_n_0), + .I1(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I3(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I4(reset), + .I5(breaking_en), + .O(key3_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + key3_prev_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key3_reg_n_0), + .Q(key3_prev), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + key3_reg + (.C(externalCLK), + .CE(1'b1), + .D(key3_i_1_n_0), + .Q(key3_reg_n_0), + .R(1'b0)); + LUT6 #( + .INIT(64'hAAAAFFFFAAAAFFFC)) + key4_i_1 + (.I0(key4_reg_n_0), + .I1(key3), + .I2(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I4(reset), + .I5(breaking_en), + .O(key4_i_1_n_0)); + LUT4 #( + .INIT(16'hFFFE)) + key4_i_2 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .O(key3)); + FDRE #( + .INIT(1'b1)) + key4_prev_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key4_reg_n_0), + .Q(key4_prev), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + key4_reg + (.C(externalCLK), + .CE(1'b1), + .D(key4_i_1_n_0), + .Q(key4_reg_n_0), + .R(1'b0)); + CARRY4 ltOp__15_carry + (.CI(1'b0), + .CO({ltOp__15_carry_n_0,ltOp__15_carry_n_1,ltOp__15_carry_n_2,ltOp__15_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp__15_carry_i_1_n_0,ltOp__15_carry_i_2_n_0,ltOp__15_carry_i_3_n_0,ltOp__15_carry_i_4_n_0}), + .O(NLW_ltOp__15_carry_O_UNCONNECTED[3:0]), + .S({ltOp__15_carry_i_5_n_0,ltOp__15_carry_i_6_n_0,ltOp__15_carry_i_7_n_0,ltOp__15_carry_i_8_n_0})); + CARRY4 ltOp__15_carry__0 + (.CI(ltOp__15_carry_n_0), + .CO({ltOp__15_carry__0_n_0,ltOp__15_carry__0_n_1,ltOp__15_carry__0_n_2,ltOp__15_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp__15_carry__0_i_1_n_0,ltOp__15_carry__0_i_2_n_0,ltOp__15_carry__0_i_3_n_0,ltOp__15_carry__0_i_4_n_0}), + .O(NLW_ltOp__15_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp__15_carry__0_i_5_n_0,ltOp__15_carry__0_i_6_n_0,ltOp__15_carry__0_i_7_n_0,ltOp__15_carry__0_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__0_i_1 + (.I0(minTime[15]), + .I1(minTimeCounter_low_reg[15]), + .I2(minTime[14]), + .I3(minTimeCounter_low_reg[14]), + .O(ltOp__15_carry__0_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__0_i_2 + (.I0(minTime[13]), + .I1(minTimeCounter_low_reg[13]), + .I2(minTime[12]), + .I3(minTimeCounter_low_reg[12]), + .O(ltOp__15_carry__0_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__0_i_3 + (.I0(minTime[11]), + .I1(minTimeCounter_low_reg[11]), + .I2(minTime[10]), + .I3(minTimeCounter_low_reg[10]), + .O(ltOp__15_carry__0_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__0_i_4 + (.I0(minTime[9]), + .I1(minTimeCounter_low_reg[9]), + .I2(minTime[8]), + .I3(minTimeCounter_low_reg[8]), + .O(ltOp__15_carry__0_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__0_i_5 + (.I0(minTimeCounter_low_reg[15]), + .I1(minTime[15]), + .I2(minTimeCounter_low_reg[14]), + .I3(minTime[14]), + .O(ltOp__15_carry__0_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__0_i_6 + (.I0(minTimeCounter_low_reg[13]), + .I1(minTime[13]), + .I2(minTimeCounter_low_reg[12]), + .I3(minTime[12]), + .O(ltOp__15_carry__0_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__0_i_7 + (.I0(minTimeCounter_low_reg[11]), + .I1(minTime[11]), + .I2(minTimeCounter_low_reg[10]), + .I3(minTime[10]), + .O(ltOp__15_carry__0_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__0_i_8 + (.I0(minTimeCounter_low_reg[9]), + .I1(minTime[9]), + .I2(minTimeCounter_low_reg[8]), + .I3(minTime[8]), + .O(ltOp__15_carry__0_i_8_n_0)); + CARRY4 ltOp__15_carry__1 + (.CI(ltOp__15_carry__0_n_0), + .CO({ltOp__15_carry__1_n_0,ltOp__15_carry__1_n_1,ltOp__15_carry__1_n_2,ltOp__15_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp__15_carry__1_i_1_n_0,ltOp__15_carry__1_i_2_n_0,ltOp__15_carry__1_i_3_n_0,ltOp__15_carry__1_i_4_n_0}), + .O(NLW_ltOp__15_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp__15_carry__1_i_5_n_0,ltOp__15_carry__1_i_6_n_0,ltOp__15_carry__1_i_7_n_0,ltOp__15_carry__1_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__1_i_1 + (.I0(minTime[23]), + .I1(minTimeCounter_low_reg[23]), + .I2(minTime[22]), + .I3(minTimeCounter_low_reg[22]), + .O(ltOp__15_carry__1_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__1_i_2 + (.I0(minTime[21]), + .I1(minTimeCounter_low_reg[21]), + .I2(minTime[20]), + .I3(minTimeCounter_low_reg[20]), + .O(ltOp__15_carry__1_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__1_i_3 + (.I0(minTime[19]), + .I1(minTimeCounter_low_reg[19]), + .I2(minTime[18]), + .I3(minTimeCounter_low_reg[18]), + .O(ltOp__15_carry__1_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__1_i_4 + (.I0(minTime[17]), + .I1(minTimeCounter_low_reg[17]), + .I2(minTime[16]), + .I3(minTimeCounter_low_reg[16]), + .O(ltOp__15_carry__1_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__1_i_5 + (.I0(minTimeCounter_low_reg[23]), + .I1(minTime[23]), + .I2(minTimeCounter_low_reg[22]), + .I3(minTime[22]), + .O(ltOp__15_carry__1_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__1_i_6 + (.I0(minTimeCounter_low_reg[21]), + .I1(minTime[21]), + .I2(minTimeCounter_low_reg[20]), + .I3(minTime[20]), + .O(ltOp__15_carry__1_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__1_i_7 + (.I0(minTimeCounter_low_reg[19]), + .I1(minTime[19]), + .I2(minTimeCounter_low_reg[18]), + .I3(minTime[18]), + .O(ltOp__15_carry__1_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__1_i_8 + (.I0(minTimeCounter_low_reg[17]), + .I1(minTime[17]), + .I2(minTimeCounter_low_reg[16]), + .I3(minTime[16]), + .O(ltOp__15_carry__1_i_8_n_0)); + CARRY4 ltOp__15_carry__2 + (.CI(ltOp__15_carry__1_n_0), + .CO({ltOp__15_carry__2_n_0,ltOp__15_carry__2_n_1,ltOp__15_carry__2_n_2,ltOp__15_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp__15_carry__2_i_1_n_0,ltOp__15_carry__2_i_2_n_0,ltOp__15_carry__2_i_3_n_0,ltOp__15_carry__2_i_4_n_0}), + .O(NLW_ltOp__15_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp__15_carry__2_i_5_n_0,ltOp__15_carry__2_i_6_n_0,ltOp__15_carry__2_i_7_n_0,ltOp__15_carry__2_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__2_i_1 + (.I0(minTime[31]), + .I1(minTimeCounter_low_reg[31]), + .I2(minTime[30]), + .I3(minTimeCounter_low_reg[30]), + .O(ltOp__15_carry__2_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__2_i_2 + (.I0(minTime[29]), + .I1(minTimeCounter_low_reg[29]), + .I2(minTime[28]), + .I3(minTimeCounter_low_reg[28]), + .O(ltOp__15_carry__2_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__2_i_3 + (.I0(minTime[27]), + .I1(minTimeCounter_low_reg[27]), + .I2(minTime[26]), + .I3(minTimeCounter_low_reg[26]), + .O(ltOp__15_carry__2_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__2_i_4 + (.I0(minTime[25]), + .I1(minTimeCounter_low_reg[25]), + .I2(minTime[24]), + .I3(minTimeCounter_low_reg[24]), + .O(ltOp__15_carry__2_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__2_i_5 + (.I0(minTimeCounter_low_reg[31]), + .I1(minTime[31]), + .I2(minTimeCounter_low_reg[30]), + .I3(minTime[30]), + .O(ltOp__15_carry__2_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__2_i_6 + (.I0(minTimeCounter_low_reg[29]), + .I1(minTime[29]), + .I2(minTimeCounter_low_reg[28]), + .I3(minTime[28]), + .O(ltOp__15_carry__2_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__2_i_7 + (.I0(minTimeCounter_low_reg[27]), + .I1(minTime[27]), + .I2(minTimeCounter_low_reg[26]), + .I3(minTime[26]), + .O(ltOp__15_carry__2_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__2_i_8 + (.I0(minTimeCounter_low_reg[25]), + .I1(minTime[25]), + .I2(minTimeCounter_low_reg[24]), + .I3(minTime[24]), + .O(ltOp__15_carry__2_i_8_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry_i_1 + (.I0(minTime[7]), + .I1(minTimeCounter_low_reg[7]), + .I2(minTime[6]), + .I3(minTimeCounter_low_reg[6]), + .O(ltOp__15_carry_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry_i_2 + (.I0(minTime[5]), + .I1(minTimeCounter_low_reg[5]), + .I2(minTime[4]), + .I3(minTimeCounter_low_reg[4]), + .O(ltOp__15_carry_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry_i_3 + (.I0(minTime[3]), + .I1(minTimeCounter_low_reg[3]), + .I2(minTime[2]), + .I3(minTimeCounter_low_reg[2]), + .O(ltOp__15_carry_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry_i_4 + (.I0(minTime[1]), + .I1(minTimeCounter_low_reg[1]), + .I2(minTime[0]), + .I3(minTimeCounter_low_reg[0]), + .O(ltOp__15_carry_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry_i_5 + (.I0(minTimeCounter_low_reg[7]), + .I1(minTime[7]), + .I2(minTimeCounter_low_reg[6]), + .I3(minTime[6]), + .O(ltOp__15_carry_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry_i_6 + (.I0(minTimeCounter_low_reg[5]), + .I1(minTime[5]), + .I2(minTimeCounter_low_reg[4]), + .I3(minTime[4]), + .O(ltOp__15_carry_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry_i_7 + (.I0(minTimeCounter_low_reg[3]), + .I1(minTime[3]), + .I2(minTimeCounter_low_reg[2]), + .I3(minTime[2]), + .O(ltOp__15_carry_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry_i_8 + (.I0(minTimeCounter_low_reg[1]), + .I1(minTime[1]), + .I2(minTimeCounter_low_reg[0]), + .I3(minTime[0]), + .O(ltOp__15_carry_i_8_n_0)); + CARRY4 ltOp__31_carry + (.CI(1'b0), + .CO({ltOp__31_carry_n_0,ltOp__31_carry_n_1,ltOp__31_carry_n_2,ltOp__31_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp__31_carry_i_1_n_0,ltOp__31_carry_i_2_n_0,ltOp__31_carry_i_3_n_0,ltOp__31_carry_i_4_n_0}), + .O(NLW_ltOp__31_carry_O_UNCONNECTED[3:0]), + .S({ltOp__31_carry_i_5_n_0,ltOp__31_carry_i_6_n_0,ltOp__31_carry_i_7_n_0,ltOp__31_carry_i_8_n_0})); + CARRY4 ltOp__31_carry__0 + (.CI(ltOp__31_carry_n_0), + .CO({ltOp__31_carry__0_n_0,ltOp__31_carry__0_n_1,ltOp__31_carry__0_n_2,ltOp__31_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp__31_carry_i_1__0_n_0,ltOp__31_carry_i_2__0_n_0,ltOp__31_carry_i_3__0_n_0,ltOp__31_carry_i_4__0_n_0}), + .O(NLW_ltOp__31_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp__31_carry_i_5__0_n_0,ltOp__31_carry_i_6__0_n_0,ltOp__31_carry_i_7__0_n_0,ltOp__31_carry_i_8__0_n_0})); + CARRY4 ltOp__31_carry__1 + (.CI(ltOp__31_carry__0_n_0), + .CO({ltOp__31_carry__1_n_0,ltOp__31_carry__1_n_1,ltOp__31_carry__1_n_2,ltOp__31_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp__31_carry_i_1__1_n_0,ltOp__31_carry_i_2__1_n_0,ltOp__31_carry_i_3__1_n_0,ltOp__31_carry_i_4__1_n_0}), + .O(NLW_ltOp__31_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp__31_carry_i_5__1_n_0,ltOp__31_carry_i_6__1_n_0,ltOp__31_carry_i_7__1_n_0,ltOp__31_carry_i_8__1_n_0})); + CARRY4 ltOp__31_carry__2 + (.CI(ltOp__31_carry__1_n_0), + .CO({ltOp__31_carry__2_n_0,ltOp__31_carry__2_n_1,ltOp__31_carry__2_n_2,ltOp__31_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp__31_carry_i_1__2_n_0,ltOp__31_carry_i_2__2_n_0,ltOp__31_carry_i_3__2_n_0,ltOp__31_carry_i_4__2_n_0}), + .O(NLW_ltOp__31_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp__31_carry_i_5__2_n_0,ltOp__31_carry_i_6__2_n_0,ltOp__31_carry_i_7__2_n_0,ltOp__31_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_1 + (.I0(minTime[7]), + .I1(minTimeCounter_high_reg[7]), + .I2(minTime[6]), + .I3(minTimeCounter_high_reg[6]), + .O(ltOp__31_carry_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_1__0 + (.I0(minTime[15]), + .I1(minTimeCounter_high_reg[15]), + .I2(minTime[14]), + .I3(minTimeCounter_high_reg[14]), + .O(ltOp__31_carry_i_1__0_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_1__1 + (.I0(minTime[23]), + .I1(minTimeCounter_high_reg[23]), + .I2(minTime[22]), + .I3(minTimeCounter_high_reg[22]), + .O(ltOp__31_carry_i_1__1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_1__2 + (.I0(minTime[31]), + .I1(minTimeCounter_high_reg[31]), + .I2(minTime[30]), + .I3(minTimeCounter_high_reg[30]), + .O(ltOp__31_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_2 + (.I0(minTime[5]), + .I1(minTimeCounter_high_reg[5]), + .I2(minTime[4]), + .I3(minTimeCounter_high_reg[4]), + .O(ltOp__31_carry_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_2__0 + (.I0(minTime[13]), + .I1(minTimeCounter_high_reg[13]), + .I2(minTime[12]), + .I3(minTimeCounter_high_reg[12]), + .O(ltOp__31_carry_i_2__0_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_2__1 + (.I0(minTime[21]), + .I1(minTimeCounter_high_reg[21]), + .I2(minTime[20]), + .I3(minTimeCounter_high_reg[20]), + .O(ltOp__31_carry_i_2__1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_2__2 + (.I0(minTime[29]), + .I1(minTimeCounter_high_reg[29]), + .I2(minTime[28]), + .I3(minTimeCounter_high_reg[28]), + .O(ltOp__31_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_3 + (.I0(minTime[3]), + .I1(minTimeCounter_high_reg[3]), + .I2(minTime[2]), + .I3(minTimeCounter_high_reg[2]), + .O(ltOp__31_carry_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_3__0 + (.I0(minTime[11]), + .I1(minTimeCounter_high_reg[11]), + .I2(minTime[10]), + .I3(minTimeCounter_high_reg[10]), + .O(ltOp__31_carry_i_3__0_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_3__1 + (.I0(minTime[19]), + .I1(minTimeCounter_high_reg[19]), + .I2(minTime[18]), + .I3(minTimeCounter_high_reg[18]), + .O(ltOp__31_carry_i_3__1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_3__2 + (.I0(minTime[27]), + .I1(minTimeCounter_high_reg[27]), + .I2(minTime[26]), + .I3(minTimeCounter_high_reg[26]), + .O(ltOp__31_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_4 + (.I0(minTime[1]), + .I1(minTimeCounter_high_reg[1]), + .I2(minTime[0]), + .I3(minTimeCounter_high_reg[0]), + .O(ltOp__31_carry_i_4_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_4__0 + (.I0(minTime[9]), + .I1(minTimeCounter_high_reg[9]), + .I2(minTime[8]), + .I3(minTimeCounter_high_reg[8]), + .O(ltOp__31_carry_i_4__0_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_4__1 + (.I0(minTime[17]), + .I1(minTimeCounter_high_reg[17]), + .I2(minTime[16]), + .I3(minTimeCounter_high_reg[16]), + .O(ltOp__31_carry_i_4__1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_4__2 + (.I0(minTime[25]), + .I1(minTimeCounter_high_reg[25]), + .I2(minTime[24]), + .I3(minTimeCounter_high_reg[24]), + .O(ltOp__31_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_5 + (.I0(minTimeCounter_high_reg[7]), + .I1(minTime[7]), + .I2(minTimeCounter_high_reg[6]), + .I3(minTime[6]), + .O(ltOp__31_carry_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_5__0 + (.I0(minTimeCounter_high_reg[15]), + .I1(minTime[15]), + .I2(minTimeCounter_high_reg[14]), + .I3(minTime[14]), + .O(ltOp__31_carry_i_5__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_5__1 + (.I0(minTimeCounter_high_reg[23]), + .I1(minTime[23]), + .I2(minTimeCounter_high_reg[22]), + .I3(minTime[22]), + .O(ltOp__31_carry_i_5__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_5__2 + (.I0(minTimeCounter_high_reg[31]), + .I1(minTime[31]), + .I2(minTimeCounter_high_reg[30]), + .I3(minTime[30]), + .O(ltOp__31_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_6 + (.I0(minTimeCounter_high_reg[5]), + .I1(minTime[5]), + .I2(minTimeCounter_high_reg[4]), + .I3(minTime[4]), + .O(ltOp__31_carry_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_6__0 + (.I0(minTimeCounter_high_reg[13]), + .I1(minTime[13]), + .I2(minTimeCounter_high_reg[12]), + .I3(minTime[12]), + .O(ltOp__31_carry_i_6__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_6__1 + (.I0(minTimeCounter_high_reg[21]), + .I1(minTime[21]), + .I2(minTimeCounter_high_reg[20]), + .I3(minTime[20]), + .O(ltOp__31_carry_i_6__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_6__2 + (.I0(minTimeCounter_high_reg[29]), + .I1(minTime[29]), + .I2(minTimeCounter_high_reg[28]), + .I3(minTime[28]), + .O(ltOp__31_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_7 + (.I0(minTimeCounter_high_reg[3]), + .I1(minTime[3]), + .I2(minTimeCounter_high_reg[2]), + .I3(minTime[2]), + .O(ltOp__31_carry_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_7__0 + (.I0(minTimeCounter_high_reg[11]), + .I1(minTime[11]), + .I2(minTimeCounter_high_reg[10]), + .I3(minTime[10]), + .O(ltOp__31_carry_i_7__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_7__1 + (.I0(minTimeCounter_high_reg[19]), + .I1(minTime[19]), + .I2(minTimeCounter_high_reg[18]), + .I3(minTime[18]), + .O(ltOp__31_carry_i_7__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_7__2 + (.I0(minTimeCounter_high_reg[27]), + .I1(minTime[27]), + .I2(minTimeCounter_high_reg[26]), + .I3(minTime[26]), + .O(ltOp__31_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_8 + (.I0(minTimeCounter_high_reg[1]), + .I1(minTime[1]), + .I2(minTimeCounter_high_reg[0]), + .I3(minTime[0]), + .O(ltOp__31_carry_i_8_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_8__0 + (.I0(minTimeCounter_high_reg[9]), + .I1(minTime[9]), + .I2(minTimeCounter_high_reg[8]), + .I3(minTime[8]), + .O(ltOp__31_carry_i_8__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_8__1 + (.I0(minTimeCounter_high_reg[17]), + .I1(minTime[17]), + .I2(minTimeCounter_high_reg[16]), + .I3(minTime[16]), + .O(ltOp__31_carry_i_8__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_8__2 + (.I0(minTimeCounter_high_reg[25]), + .I1(minTime[25]), + .I2(minTimeCounter_high_reg[24]), + .I3(minTime[24]), + .O(ltOp__31_carry_i_8__2_n_0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry__0_i_1_n_0,ltOp_carry__0_i_2_n_0,ltOp_carry__0_i_3_n_0,ltOp_carry__0_i_4_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry__0_i_5_n_0,ltOp_carry__0_i_6_n_0,ltOp_carry__0_i_7_n_0,ltOp_carry__0_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__0_i_1 + (.I0(deadTime[15]), + .I1(TimeCounter_reg[15]), + .I2(deadTime[14]), + .I3(TimeCounter_reg[14]), + .O(ltOp_carry__0_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__0_i_2 + (.I0(deadTime[13]), + .I1(TimeCounter_reg[13]), + .I2(deadTime[12]), + .I3(TimeCounter_reg[12]), + .O(ltOp_carry__0_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__0_i_3 + (.I0(deadTime[11]), + .I1(TimeCounter_reg[11]), + .I2(deadTime[10]), + .I3(TimeCounter_reg[10]), + .O(ltOp_carry__0_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__0_i_4 + (.I0(deadTime[9]), + .I1(TimeCounter_reg[9]), + .I2(deadTime[8]), + .I3(TimeCounter_reg[8]), + .O(ltOp_carry__0_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__0_i_5 + (.I0(TimeCounter_reg[15]), + .I1(deadTime[15]), + .I2(TimeCounter_reg[14]), + .I3(deadTime[14]), + .O(ltOp_carry__0_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__0_i_6 + (.I0(TimeCounter_reg[13]), + .I1(deadTime[13]), + .I2(TimeCounter_reg[12]), + .I3(deadTime[12]), + .O(ltOp_carry__0_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__0_i_7 + (.I0(TimeCounter_reg[11]), + .I1(deadTime[11]), + .I2(TimeCounter_reg[10]), + .I3(deadTime[10]), + .O(ltOp_carry__0_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__0_i_8 + (.I0(TimeCounter_reg[9]), + .I1(deadTime[9]), + .I2(TimeCounter_reg[8]), + .I3(deadTime[8]), + .O(ltOp_carry__0_i_8_n_0)); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry__1_i_1_n_0,ltOp_carry__1_i_2_n_0,ltOp_carry__1_i_3_n_0,ltOp_carry__1_i_4_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry__1_i_5_n_0,ltOp_carry__1_i_6_n_0,ltOp_carry__1_i_7_n_0,ltOp_carry__1_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__1_i_1 + (.I0(deadTime[23]), + .I1(TimeCounter_reg[23]), + .I2(deadTime[22]), + .I3(TimeCounter_reg[22]), + .O(ltOp_carry__1_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__1_i_2 + (.I0(deadTime[21]), + .I1(TimeCounter_reg[21]), + .I2(deadTime[20]), + .I3(TimeCounter_reg[20]), + .O(ltOp_carry__1_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__1_i_3 + (.I0(deadTime[19]), + .I1(TimeCounter_reg[19]), + .I2(deadTime[18]), + .I3(TimeCounter_reg[18]), + .O(ltOp_carry__1_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__1_i_4 + (.I0(deadTime[17]), + .I1(TimeCounter_reg[17]), + .I2(deadTime[16]), + .I3(TimeCounter_reg[16]), + .O(ltOp_carry__1_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__1_i_5 + (.I0(TimeCounter_reg[23]), + .I1(deadTime[23]), + .I2(TimeCounter_reg[22]), + .I3(deadTime[22]), + .O(ltOp_carry__1_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__1_i_6 + (.I0(TimeCounter_reg[21]), + .I1(deadTime[21]), + .I2(TimeCounter_reg[20]), + .I3(deadTime[20]), + .O(ltOp_carry__1_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__1_i_7 + (.I0(TimeCounter_reg[19]), + .I1(deadTime[19]), + .I2(TimeCounter_reg[18]), + .I3(deadTime[18]), + .O(ltOp_carry__1_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__1_i_8 + (.I0(TimeCounter_reg[17]), + .I1(deadTime[17]), + .I2(TimeCounter_reg[16]), + .I3(deadTime[16]), + .O(ltOp_carry__1_i_8_n_0)); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({sel,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry__2_i_1_n_0,ltOp_carry__2_i_2_n_0,ltOp_carry__2_i_3_n_0,ltOp_carry__2_i_4_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry__2_i_5_n_0,ltOp_carry__2_i_6_n_0,ltOp_carry__2_i_7_n_0,ltOp_carry__2_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__2_i_1 + (.I0(deadTime[31]), + .I1(TimeCounter_reg[31]), + .I2(deadTime[30]), + .I3(TimeCounter_reg[30]), + .O(ltOp_carry__2_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__2_i_2 + (.I0(deadTime[29]), + .I1(TimeCounter_reg[29]), + .I2(deadTime[28]), + .I3(TimeCounter_reg[28]), + .O(ltOp_carry__2_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__2_i_3 + (.I0(deadTime[27]), + .I1(TimeCounter_reg[27]), + .I2(deadTime[26]), + .I3(TimeCounter_reg[26]), + .O(ltOp_carry__2_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__2_i_4 + (.I0(deadTime[25]), + .I1(TimeCounter_reg[25]), + .I2(deadTime[24]), + .I3(TimeCounter_reg[24]), + .O(ltOp_carry__2_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__2_i_5 + (.I0(TimeCounter_reg[31]), + .I1(deadTime[31]), + .I2(TimeCounter_reg[30]), + .I3(deadTime[30]), + .O(ltOp_carry__2_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__2_i_6 + (.I0(TimeCounter_reg[29]), + .I1(deadTime[29]), + .I2(TimeCounter_reg[28]), + .I3(deadTime[28]), + .O(ltOp_carry__2_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__2_i_7 + (.I0(TimeCounter_reg[27]), + .I1(deadTime[27]), + .I2(TimeCounter_reg[26]), + .I3(deadTime[26]), + .O(ltOp_carry__2_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__2_i_8 + (.I0(TimeCounter_reg[25]), + .I1(deadTime[25]), + .I2(TimeCounter_reg[24]), + .I3(deadTime[24]), + .O(ltOp_carry__2_i_8_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry_i_1 + (.I0(deadTime[7]), + .I1(TimeCounter_reg[7]), + .I2(deadTime[6]), + .I3(TimeCounter_reg[6]), + .O(ltOp_carry_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry_i_2 + (.I0(deadTime[5]), + .I1(TimeCounter_reg[5]), + .I2(deadTime[4]), + .I3(TimeCounter_reg[4]), + .O(ltOp_carry_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry_i_3 + (.I0(deadTime[3]), + .I1(TimeCounter_reg[3]), + .I2(deadTime[2]), + .I3(TimeCounter_reg[2]), + .O(ltOp_carry_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry_i_4 + (.I0(deadTime[1]), + .I1(TimeCounter_reg[1]), + .I2(deadTime[0]), + .I3(TimeCounter_reg[0]), + .O(ltOp_carry_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(TimeCounter_reg[7]), + .I1(deadTime[7]), + .I2(TimeCounter_reg[6]), + .I3(deadTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(TimeCounter_reg[5]), + .I1(deadTime[5]), + .I2(TimeCounter_reg[4]), + .I3(deadTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(TimeCounter_reg[3]), + .I1(deadTime[3]), + .I2(TimeCounter_reg[2]), + .I3(deadTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(TimeCounter_reg[1]), + .I1(deadTime[1]), + .I2(TimeCounter_reg[0]), + .I3(deadTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT6 #( + .INIT(64'h0000000022222F22)) + \minTimeCounter_high[0]_i_1 + (.I0(key1_prev), + .I1(key1_reg_n_0), + .I2(key2_reg_n_0), + .I3(key2_prev), + .I4(breaking_en), + .I5(reset), + .O(\minTimeCounter_high[0]_i_1_n_0 )); + LUT2 #( + .INIT(4'h2)) + \minTimeCounter_high[0]_i_2 + (.I0(ltOp__31_carry__2_n_0), + .I1(reset), + .O(minTimeCounter_high)); + LUT1 #( + .INIT(2'h1)) + \minTimeCounter_high[0]_i_4 + (.I0(minTimeCounter_high_reg[0]), + .O(\minTimeCounter_high[0]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[0] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[0]_i_3_n_7 ), + .Q(minTimeCounter_high_reg[0]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[0]_i_3 + (.CI(1'b0), + .CO({\minTimeCounter_high_reg[0]_i_3_n_0 ,\minTimeCounter_high_reg[0]_i_3_n_1 ,\minTimeCounter_high_reg[0]_i_3_n_2 ,\minTimeCounter_high_reg[0]_i_3_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\minTimeCounter_high_reg[0]_i_3_n_4 ,\minTimeCounter_high_reg[0]_i_3_n_5 ,\minTimeCounter_high_reg[0]_i_3_n_6 ,\minTimeCounter_high_reg[0]_i_3_n_7 }), + .S({minTimeCounter_high_reg[3:1],\minTimeCounter_high[0]_i_4_n_0 })); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[10] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[8]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[10]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[11] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[8]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[11]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[12] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[12]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[12]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[12]_i_1 + (.CI(\minTimeCounter_high_reg[8]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[12]_i_1_n_0 ,\minTimeCounter_high_reg[12]_i_1_n_1 ,\minTimeCounter_high_reg[12]_i_1_n_2 ,\minTimeCounter_high_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[12]_i_1_n_4 ,\minTimeCounter_high_reg[12]_i_1_n_5 ,\minTimeCounter_high_reg[12]_i_1_n_6 ,\minTimeCounter_high_reg[12]_i_1_n_7 }), + .S(minTimeCounter_high_reg[15:12])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[13] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[12]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[13]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[14] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[12]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[14]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[15] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[12]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[15]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[16] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[16]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[16]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[16]_i_1 + (.CI(\minTimeCounter_high_reg[12]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[16]_i_1_n_0 ,\minTimeCounter_high_reg[16]_i_1_n_1 ,\minTimeCounter_high_reg[16]_i_1_n_2 ,\minTimeCounter_high_reg[16]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[16]_i_1_n_4 ,\minTimeCounter_high_reg[16]_i_1_n_5 ,\minTimeCounter_high_reg[16]_i_1_n_6 ,\minTimeCounter_high_reg[16]_i_1_n_7 }), + .S(minTimeCounter_high_reg[19:16])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[17] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[16]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[17]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[18] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[16]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[18]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[19] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[16]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[19]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[1] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[0]_i_3_n_6 ), + .Q(minTimeCounter_high_reg[1]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[20] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[20]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[20]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[20]_i_1 + (.CI(\minTimeCounter_high_reg[16]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[20]_i_1_n_0 ,\minTimeCounter_high_reg[20]_i_1_n_1 ,\minTimeCounter_high_reg[20]_i_1_n_2 ,\minTimeCounter_high_reg[20]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[20]_i_1_n_4 ,\minTimeCounter_high_reg[20]_i_1_n_5 ,\minTimeCounter_high_reg[20]_i_1_n_6 ,\minTimeCounter_high_reg[20]_i_1_n_7 }), + .S(minTimeCounter_high_reg[23:20])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[21] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[20]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[21]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[22] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[20]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[22]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[23] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[20]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[23]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[24] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[24]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[24]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[24]_i_1 + (.CI(\minTimeCounter_high_reg[20]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[24]_i_1_n_0 ,\minTimeCounter_high_reg[24]_i_1_n_1 ,\minTimeCounter_high_reg[24]_i_1_n_2 ,\minTimeCounter_high_reg[24]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[24]_i_1_n_4 ,\minTimeCounter_high_reg[24]_i_1_n_5 ,\minTimeCounter_high_reg[24]_i_1_n_6 ,\minTimeCounter_high_reg[24]_i_1_n_7 }), + .S(minTimeCounter_high_reg[27:24])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[25] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[24]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[25]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[26] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[24]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[26]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[27] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[24]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[27]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[28] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[28]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[28]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[28]_i_1 + (.CI(\minTimeCounter_high_reg[24]_i_1_n_0 ), + .CO({\NLW_minTimeCounter_high_reg[28]_i_1_CO_UNCONNECTED [3],\minTimeCounter_high_reg[28]_i_1_n_1 ,\minTimeCounter_high_reg[28]_i_1_n_2 ,\minTimeCounter_high_reg[28]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[28]_i_1_n_4 ,\minTimeCounter_high_reg[28]_i_1_n_5 ,\minTimeCounter_high_reg[28]_i_1_n_6 ,\minTimeCounter_high_reg[28]_i_1_n_7 }), + .S(minTimeCounter_high_reg[31:28])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[29] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[28]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[29]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[2] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[0]_i_3_n_5 ), + .Q(minTimeCounter_high_reg[2]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[30] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[28]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[30]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[31] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[28]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[31]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[3] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[0]_i_3_n_4 ), + .Q(minTimeCounter_high_reg[3]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[4] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[4]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[4]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[4]_i_1 + (.CI(\minTimeCounter_high_reg[0]_i_3_n_0 ), + .CO({\minTimeCounter_high_reg[4]_i_1_n_0 ,\minTimeCounter_high_reg[4]_i_1_n_1 ,\minTimeCounter_high_reg[4]_i_1_n_2 ,\minTimeCounter_high_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[4]_i_1_n_4 ,\minTimeCounter_high_reg[4]_i_1_n_5 ,\minTimeCounter_high_reg[4]_i_1_n_6 ,\minTimeCounter_high_reg[4]_i_1_n_7 }), + .S(minTimeCounter_high_reg[7:4])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[5] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[4]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[5]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[6] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[4]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[6]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[7] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[4]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[7]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[8] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[8]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[8]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[8]_i_1 + (.CI(\minTimeCounter_high_reg[4]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[8]_i_1_n_0 ,\minTimeCounter_high_reg[8]_i_1_n_1 ,\minTimeCounter_high_reg[8]_i_1_n_2 ,\minTimeCounter_high_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[8]_i_1_n_4 ,\minTimeCounter_high_reg[8]_i_1_n_5 ,\minTimeCounter_high_reg[8]_i_1_n_6 ,\minTimeCounter_high_reg[8]_i_1_n_7 }), + .S(minTimeCounter_high_reg[11:8])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[9] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[8]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[9]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + LUT5 #( + .INIT(32'h0000440F)) + \minTimeCounter_low[0]_i_1 + (.I0(key2_reg_n_0), + .I1(key2_prev), + .I2(\minTimeCounter_low[0]_i_4_n_0 ), + .I3(breaking_en), + .I4(reset), + .O(\minTimeCounter_low[0]_i_1_n_0 )); + LUT2 #( + .INIT(4'h2)) + \minTimeCounter_low[0]_i_2 + (.I0(ltOp__15_carry__2_n_0), + .I1(reset), + .O(minTimeCounter_low)); + LUT4 #( + .INIT(16'hD0DD)) + \minTimeCounter_low[0]_i_4 + (.I0(key4_prev), + .I1(key4_reg_n_0), + .I2(key3_reg_n_0), + .I3(key3_prev), + .O(\minTimeCounter_low[0]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \minTimeCounter_low[0]_i_5 + (.I0(minTimeCounter_low_reg[0]), + .O(\minTimeCounter_low[0]_i_5_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[0] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[0]_i_3_n_7 ), + .Q(minTimeCounter_low_reg[0]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[0]_i_3 + (.CI(1'b0), + .CO({\minTimeCounter_low_reg[0]_i_3_n_0 ,\minTimeCounter_low_reg[0]_i_3_n_1 ,\minTimeCounter_low_reg[0]_i_3_n_2 ,\minTimeCounter_low_reg[0]_i_3_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\minTimeCounter_low_reg[0]_i_3_n_4 ,\minTimeCounter_low_reg[0]_i_3_n_5 ,\minTimeCounter_low_reg[0]_i_3_n_6 ,\minTimeCounter_low_reg[0]_i_3_n_7 }), + .S({minTimeCounter_low_reg[3:1],\minTimeCounter_low[0]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[10] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[8]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[10]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[11] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[8]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[11]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[12] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[12]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[12]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[12]_i_1 + (.CI(\minTimeCounter_low_reg[8]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[12]_i_1_n_0 ,\minTimeCounter_low_reg[12]_i_1_n_1 ,\minTimeCounter_low_reg[12]_i_1_n_2 ,\minTimeCounter_low_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[12]_i_1_n_4 ,\minTimeCounter_low_reg[12]_i_1_n_5 ,\minTimeCounter_low_reg[12]_i_1_n_6 ,\minTimeCounter_low_reg[12]_i_1_n_7 }), + .S(minTimeCounter_low_reg[15:12])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[13] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[12]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[13]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[14] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[12]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[14]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[15] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[12]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[15]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[16] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[16]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[16]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[16]_i_1 + (.CI(\minTimeCounter_low_reg[12]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[16]_i_1_n_0 ,\minTimeCounter_low_reg[16]_i_1_n_1 ,\minTimeCounter_low_reg[16]_i_1_n_2 ,\minTimeCounter_low_reg[16]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[16]_i_1_n_4 ,\minTimeCounter_low_reg[16]_i_1_n_5 ,\minTimeCounter_low_reg[16]_i_1_n_6 ,\minTimeCounter_low_reg[16]_i_1_n_7 }), + .S(minTimeCounter_low_reg[19:16])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[17] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[16]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[17]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[18] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[16]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[18]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[19] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[16]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[19]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[1] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[0]_i_3_n_6 ), + .Q(minTimeCounter_low_reg[1]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[20] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[20]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[20]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[20]_i_1 + (.CI(\minTimeCounter_low_reg[16]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[20]_i_1_n_0 ,\minTimeCounter_low_reg[20]_i_1_n_1 ,\minTimeCounter_low_reg[20]_i_1_n_2 ,\minTimeCounter_low_reg[20]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[20]_i_1_n_4 ,\minTimeCounter_low_reg[20]_i_1_n_5 ,\minTimeCounter_low_reg[20]_i_1_n_6 ,\minTimeCounter_low_reg[20]_i_1_n_7 }), + .S(minTimeCounter_low_reg[23:20])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[21] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[20]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[21]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[22] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[20]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[22]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[23] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[20]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[23]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[24] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[24]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[24]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[24]_i_1 + (.CI(\minTimeCounter_low_reg[20]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[24]_i_1_n_0 ,\minTimeCounter_low_reg[24]_i_1_n_1 ,\minTimeCounter_low_reg[24]_i_1_n_2 ,\minTimeCounter_low_reg[24]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[24]_i_1_n_4 ,\minTimeCounter_low_reg[24]_i_1_n_5 ,\minTimeCounter_low_reg[24]_i_1_n_6 ,\minTimeCounter_low_reg[24]_i_1_n_7 }), + .S(minTimeCounter_low_reg[27:24])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[25] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[24]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[25]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[26] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[24]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[26]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[27] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[24]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[27]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[28] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[28]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[28]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[28]_i_1 + (.CI(\minTimeCounter_low_reg[24]_i_1_n_0 ), + .CO({\NLW_minTimeCounter_low_reg[28]_i_1_CO_UNCONNECTED [3],\minTimeCounter_low_reg[28]_i_1_n_1 ,\minTimeCounter_low_reg[28]_i_1_n_2 ,\minTimeCounter_low_reg[28]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[28]_i_1_n_4 ,\minTimeCounter_low_reg[28]_i_1_n_5 ,\minTimeCounter_low_reg[28]_i_1_n_6 ,\minTimeCounter_low_reg[28]_i_1_n_7 }), + .S(minTimeCounter_low_reg[31:28])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[29] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[28]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[29]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[2] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[0]_i_3_n_5 ), + .Q(minTimeCounter_low_reg[2]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[30] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[28]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[30]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[31] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[28]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[31]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[3] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[0]_i_3_n_4 ), + .Q(minTimeCounter_low_reg[3]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[4] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[4]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[4]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[4]_i_1 + (.CI(\minTimeCounter_low_reg[0]_i_3_n_0 ), + .CO({\minTimeCounter_low_reg[4]_i_1_n_0 ,\minTimeCounter_low_reg[4]_i_1_n_1 ,\minTimeCounter_low_reg[4]_i_1_n_2 ,\minTimeCounter_low_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[4]_i_1_n_4 ,\minTimeCounter_low_reg[4]_i_1_n_5 ,\minTimeCounter_low_reg[4]_i_1_n_6 ,\minTimeCounter_low_reg[4]_i_1_n_7 }), + .S(minTimeCounter_low_reg[7:4])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[5] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[4]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[5]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[6] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[4]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[6]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[7] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[4]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[7]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[8] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[8]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[8]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[8]_i_1 + (.CI(\minTimeCounter_low_reg[4]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[8]_i_1_n_0 ,\minTimeCounter_low_reg[8]_i_1_n_1 ,\minTimeCounter_low_reg[8]_i_1_n_2 ,\minTimeCounter_low_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[8]_i_1_n_4 ,\minTimeCounter_low_reg[8]_i_1_n_5 ,\minTimeCounter_low_reg[8]_i_1_n_6 ,\minTimeCounter_low_reg[8]_i_1_n_7 }), + .S(minTimeCounter_low_reg[11:8])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[9] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[8]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[9]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'hEEFFEEEEE200E2E2)) + minTimeEr_i_1 + (.I0(minTimeEr_i_2_n_0), + .I1(minTimeEr_i_3_n_0), + .I2(minTimeEr_i_4_n_0), + .I3(minTimeEr_i_5_n_0), + .I4(minTimeEr_i_6_n_0), + .I5(minTimeEr_reg_0), + .O(minTimeEr_i_1_n_0)); + LUT4 #( + .INIT(16'h0111)) + minTimeEr_i_2 + (.I0(reset), + .I1(breaking_en), + .I2(minTimeEr_i_6_n_0), + .I3(minTimeEr_i_7_n_0), + .O(minTimeEr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h2)) + minTimeEr_i_3 + (.I0(breaking_en), + .I1(reset), + .O(minTimeEr_i_3_n_0)); + LUT6 #( + .INIT(64'h040404FF00000000)) + minTimeEr_i_4 + (.I0(minTimeOK_low), + .I1(key2_reg_n_0), + .I2(key2_prev), + .I3(minTimeEr_i_8_n_0), + .I4(minTimeOK_high), + .I5(minTime_En), + .O(minTimeEr_i_4_n_0)); + LUT6 #( + .INIT(64'h55555555F755F7F7)) + minTimeEr_i_5 + (.I0(minTimeEr_i_9_n_0), + .I1(key2_prev), + .I2(key2_reg_n_0), + .I3(key1_reg_n_0), + .I4(key1_prev), + .I5(minTimeEr_i_7_n_0), + .O(minTimeEr_i_5_n_0)); + LUT6 #( + .INIT(64'hFBFFFFFFBBFBFBFF)) + minTimeEr_i_6 + (.I0(minTimeOK_low), + .I1(minTime_En), + .I2(key3_prev), + .I3(key3_reg_n_0), + .I4(key4_reg_n_0), + .I5(key4_prev), + .O(minTimeEr_i_6_n_0)); + LUT6 #( + .INIT(64'hFFDFDDDDFFDFFFDF)) + minTimeEr_i_7 + (.I0(minTime_En), + .I1(minTimeOK_high), + .I2(key2_reg_n_0), + .I3(key2_prev), + .I4(key1_prev), + .I5(key1_reg_n_0), + .O(minTimeEr_i_7_n_0)); + LUT2 #( + .INIT(4'hB)) + minTimeEr_i_8 + (.I0(key1_prev), + .I1(key1_reg_n_0), + .O(minTimeEr_i_8_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h1)) + minTimeEr_i_9 + (.I0(breaking_en), + .I1(reset), + .O(minTimeEr_i_9_n_0)); + FDRE #( + .INIT(1'b0)) + minTimeEr_reg + (.C(externalCLK), + .CE(1'b1), + .D(minTimeEr_i_1_n_0), + .Q(minTimeEr_reg_0), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h00AB)) + minTimeOK_high_i_1 + (.I0(minTimeOK_high), + .I1(ltOp__31_carry__2_n_0), + .I2(reset), + .I3(\minTimeCounter_high[0]_i_1_n_0 ), + .O(minTimeOK_high_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + minTimeOK_high_reg + (.C(externalCLK), + .CE(1'b1), + .D(minTimeOK_high_i_1_n_0), + .Q(minTimeOK_high), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'h00AB)) + minTimeOK_low_i_1 + (.I0(minTimeOK_low), + .I1(ltOp__15_carry__2_n_0), + .I2(reset), + .I3(\minTimeCounter_low[0]_i_1_n_0 ), + .O(minTimeOK_low_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + minTimeOK_low_reg + (.C(externalCLK), + .CE(1'b1), + .D(minTimeOK_low_i_1_n_0), + .Q(minTimeOK_low), + .R(1'b0)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5_sim_netlist.vhdl b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5_sim_netlist.vhdl new file mode 100644 index 0000000..01d0df4 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5_sim_netlist.vhdl @@ -0,0 +1,4183 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Fri Jun 11 07:49:57 2021 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top Inverter_3lvl_P0N_3lvl_0_5 -prefix +-- Inverter_3lvl_P0N_3lvl_0_5_ Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.vhdl +-- Design : Inverter_3lvl_P0N_3lvl_0_4 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Inverter_3lvl_P0N_3lvl_0_5_P0N_3lvl is + port ( + minTimeEr_reg_0 : out STD_LOGIC; + PWM_out_0 : out STD_LOGIC; + PWM_out_1 : out STD_LOGIC; + PWM_out_2 : out STD_LOGIC; + PWM_out_3 : out STD_LOGIC; + reset : in STD_LOGIC; + externalCLK : in STD_LOGIC; + TKin0 : in STD_LOGIC; + TKin1 : in STD_LOGIC; + breaking_en : in STD_LOGIC; + er : in STD_LOGIC; + ready : in STD_LOGIC; + minTime_En : in STD_LOGIC; + deadTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + minTime : in STD_LOGIC_VECTOR ( 31 downto 0 ) + ); +end Inverter_3lvl_P0N_3lvl_0_5_P0N_3lvl; + +architecture STRUCTURE of Inverter_3lvl_P0N_3lvl_0_5_P0N_3lvl is + signal \FSM_onehot_lineconfig[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[0]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[1]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[2]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[2]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[3]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[4]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[5]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[5]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[5]_i_3_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_3_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_4_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_5_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_6_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[0]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[1]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[2]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[3]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[4]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[5]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[6]\ : STD_LOGIC; + signal PWM_out_0_i_1_n_0 : STD_LOGIC; + signal PWM_out_1_i_1_n_0 : STD_LOGIC; + signal PWM_out_2_i_1_n_0 : STD_LOGIC; + signal PWM_out_3_i_1_n_0 : STD_LOGIC; + signal TKin0_triggered : STD_LOGIC; + signal TKin0_triggered28_out : STD_LOGIC; + signal TKin0_triggered_i_1_n_0 : STD_LOGIC; + signal TKin1_triggered : STD_LOGIC; + signal TKin1_triggered_i_1_n_0 : STD_LOGIC; + signal \TimeCounter[0]_i_2_n_0\ : STD_LOGIC; + signal TimeCounter_reg : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \TimeCounter_reg[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_7\ : STD_LOGIC; + signal deadTimeCounterReset_i_1_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_2_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_3_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_4_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_5_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_6_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_7_n_0 : STD_LOGIC; + signal deadTimeCounterReset_reg_n_0 : STD_LOGIC; + signal deadTimeOK : STD_LOGIC; + signal deadTimeOK_i_1_n_0 : STD_LOGIC; + signal key1_i_1_n_0 : STD_LOGIC; + signal key1_i_2_n_0 : STD_LOGIC; + signal key1_prev : STD_LOGIC; + signal key1_reg_n_0 : STD_LOGIC; + signal key2_i_2_n_0 : STD_LOGIC; + signal key2_prev : STD_LOGIC; + signal key2_reg_n_0 : STD_LOGIC; + signal key3 : STD_LOGIC; + signal key3_i_1_n_0 : STD_LOGIC; + signal key3_prev : STD_LOGIC; + signal key3_reg_n_0 : STD_LOGIC; + signal key4_i_1_n_0 : STD_LOGIC; + signal key4_prev : STD_LOGIC; + signal key4_reg_n_0 : STD_LOGIC; + signal \ltOp__15_carry__0_i_1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_3_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_4_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_5_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_6_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_7_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_8_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_n_1\ : STD_LOGIC; + signal \ltOp__15_carry__0_n_2\ : STD_LOGIC; + signal \ltOp__15_carry__0_n_3\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_3_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_4_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_5_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_6_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_7_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_8_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_n_1\ : STD_LOGIC; + signal \ltOp__15_carry__1_n_2\ : STD_LOGIC; + signal \ltOp__15_carry__1_n_3\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_3_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_4_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_5_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_6_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_7_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_8_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_n_1\ : STD_LOGIC; + signal \ltOp__15_carry__2_n_2\ : STD_LOGIC; + signal \ltOp__15_carry__2_n_3\ : STD_LOGIC; + signal \ltOp__15_carry_i_1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_3_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_4_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_5_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_6_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_7_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_8_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_n_1\ : STD_LOGIC; + signal \ltOp__15_carry_n_2\ : STD_LOGIC; + signal \ltOp__15_carry_n_3\ : STD_LOGIC; + signal \ltOp__31_carry__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry__0_n_1\ : STD_LOGIC; + signal \ltOp__31_carry__0_n_2\ : STD_LOGIC; + signal \ltOp__31_carry__0_n_3\ : STD_LOGIC; + signal \ltOp__31_carry__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry__1_n_1\ : STD_LOGIC; + signal \ltOp__31_carry__1_n_2\ : STD_LOGIC; + signal \ltOp__31_carry__1_n_3\ : STD_LOGIC; + signal \ltOp__31_carry__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry__2_n_1\ : STD_LOGIC; + signal \ltOp__31_carry__2_n_2\ : STD_LOGIC; + signal \ltOp__31_carry__2_n_3\ : STD_LOGIC; + signal \ltOp__31_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_1__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_2__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_3__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_3_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_4__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_4_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_5__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_5_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_6__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_6_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_7__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_7_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_8__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_8_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_n_1\ : STD_LOGIC; + signal \ltOp__31_carry_n_2\ : STD_LOGIC; + signal \ltOp__31_carry_n_3\ : STD_LOGIC; + signal \ltOp_carry__0_i_1_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_2_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_3_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_4_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_5_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_6_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_7_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_8_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_i_1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_2_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_3_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_4_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_5_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_6_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_7_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_8_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_i_1_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_2_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_3_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_4_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_5_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_6_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_7_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_8_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal minTimeCounter_high : STD_LOGIC; + signal \minTimeCounter_high[0]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high[0]_i_4_n_0\ : STD_LOGIC; + signal minTimeCounter_high_reg : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \minTimeCounter_high_reg[0]_i_3_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_7\ : STD_LOGIC; + signal minTimeCounter_low : STD_LOGIC; + signal \minTimeCounter_low[0]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low[0]_i_4_n_0\ : STD_LOGIC; + signal \minTimeCounter_low[0]_i_5_n_0\ : STD_LOGIC; + signal minTimeCounter_low_reg : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \minTimeCounter_low_reg[0]_i_3_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_7\ : STD_LOGIC; + signal minTimeEr_i_1_n_0 : STD_LOGIC; + signal minTimeEr_i_2_n_0 : STD_LOGIC; + signal minTimeEr_i_3_n_0 : STD_LOGIC; + signal minTimeEr_i_4_n_0 : STD_LOGIC; + signal minTimeEr_i_5_n_0 : STD_LOGIC; + signal minTimeEr_i_6_n_0 : STD_LOGIC; + signal minTimeEr_i_7_n_0 : STD_LOGIC; + signal minTimeEr_i_8_n_0 : STD_LOGIC; + signal minTimeEr_i_9_n_0 : STD_LOGIC; + signal \^mintimeer_reg_0\ : STD_LOGIC; + signal minTimeOK_high : STD_LOGIC; + signal minTimeOK_high_i_1_n_0 : STD_LOGIC; + signal minTimeOK_low : STD_LOGIC; + signal minTimeOK_low_i_1_n_0 : STD_LOGIC; + signal p_0_in : STD_LOGIC; + signal sel : STD_LOGIC; + signal \NLW_TimeCounter_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_ltOp__15_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__15_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__15_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__15_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__31_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__31_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__31_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__31_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_minTimeCounter_high_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_minTimeCounter_low_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[0]_i_2\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[2]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[5]_i_2\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[6]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[6]_i_3\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[6]_i_6\ : label is "soft_lutpair2"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[0]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[1]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[2]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[3]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[4]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[5]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[6]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute SOFT_HLUTNM of PWM_out_0_i_1 : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of PWM_out_1_i_1 : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of deadTimeCounterReset_i_2 : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of deadTimeCounterReset_i_5 : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of deadTimeCounterReset_i_6 : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of deadTimeOK_i_1 : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of key1_i_2 : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of minTimeEr_i_3 : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of minTimeEr_i_9 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of minTimeOK_high_i_1 : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of minTimeOK_low_i_1 : label is "soft_lutpair3"; +begin + minTimeEr_reg_0 <= \^mintimeer_reg_0\; +\FSM_onehot_lineconfig[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFE00000000" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I4 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I5 => \FSM_onehot_lineconfig[0]_i_2_n_0\, + O => \FSM_onehot_lineconfig[0]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[0]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => TKin1, + I1 => TKin0, + O => \FSM_onehot_lineconfig[0]_i_2_n_0\ + ); +\FSM_onehot_lineconfig[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1000FFFF00000000" + ) + port map ( + I0 => TKin1, + I1 => TKin1_triggered, + I2 => TKin0_triggered, + I3 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I4 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I5 => TKin0, + O => \FSM_onehot_lineconfig[1]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00EFEF0F" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I2 => \FSM_onehot_lineconfig[2]_i_2_n_0\, + I3 => TKin0, + I4 => TKin1, + O => \FSM_onehot_lineconfig[2]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"900990099009FFFF" + ) + port map ( + I0 => TKin1, + I1 => TKin1_triggered, + I2 => TKin0, + I3 => TKin0_triggered, + I4 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I5 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + O => \FSM_onehot_lineconfig[2]_i_2_n_0\ + ); +\FSM_onehot_lineconfig[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000055D50000" + ) + port map ( + I0 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I2 => TKin1_triggered, + I3 => TKin0_triggered, + I4 => TKin1, + I5 => TKin0, + O => \FSM_onehot_lineconfig[3]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2230" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I1 => TKin0, + I2 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I3 => TKin1, + O => \FSM_onehot_lineconfig[4]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0CFF0C0D00050005" + ) + port map ( + I0 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I2 => TKin1, + I3 => TKin0, + I4 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I5 => \FSM_onehot_lineconfig[5]_i_3_n_0\, + O => \FSM_onehot_lineconfig[5]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[5]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + O => \FSM_onehot_lineconfig[5]_i_2_n_0\ + ); +\FSM_onehot_lineconfig[5]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TKin0_triggered, + I1 => TKin0, + I2 => TKin1_triggered, + I3 => TKin1, + O => \FSM_onehot_lineconfig[5]_i_3_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => \FSM_onehot_lineconfig[6]_i_3_n_0\, + I1 => \FSM_onehot_lineconfig[6]_i_4_n_0\, + I2 => breaking_en, + O => \FSM_onehot_lineconfig[6]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"5504" + ) + port map ( + I0 => TKin1, + I1 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I2 => TKin0, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + O => \FSM_onehot_lineconfig[6]_i_2_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFEECAE" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I2 => TKin1, + I3 => TKin0, + I4 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + O => \FSM_onehot_lineconfig[6]_i_3_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AABAAAAAFFFFAAAA" + ) + port map ( + I0 => \FSM_onehot_lineconfig[6]_i_5_n_0\, + I1 => er, + I2 => ready, + I3 => \FSM_onehot_lineconfig[6]_i_6_n_0\, + I4 => deadTimeOK, + I5 => \FSM_onehot_lineconfig[2]_i_2_n_0\, + O => \FSM_onehot_lineconfig[6]_i_4_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FC88A0A8" + ) + port map ( + I0 => deadTimeOK, + I1 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I3 => TKin1, + I4 => TKin0, + O => \FSM_onehot_lineconfig[6]_i_5_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF232323" + ) + port map ( + I0 => deadTimeCounterReset_reg_n_0, + I1 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I3 => TKin1, + I4 => TKin0, + O => \FSM_onehot_lineconfig[6]_i_6_n_0\ + ); +\FSM_onehot_lineconfig_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[0]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[0]\, + S => reset + ); +\FSM_onehot_lineconfig_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[1]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[1]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[2]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[2]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[3]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[3]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[4]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[4]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[5]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[5]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[6]_i_2_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[6]\, + R => reset + ); +PWM_out_0_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFEF" + ) + port map ( + I0 => key1_reg_n_0, + I1 => er, + I2 => ready, + I3 => \^mintimeer_reg_0\, + O => PWM_out_0_i_1_n_0 + ); +PWM_out_0_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => PWM_out_0_i_1_n_0, + Q => PWM_out_0, + R => '0' + ); +PWM_out_1_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFEF" + ) + port map ( + I0 => key2_reg_n_0, + I1 => er, + I2 => ready, + I3 => \^mintimeer_reg_0\, + O => PWM_out_1_i_1_n_0 + ); +PWM_out_1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => PWM_out_1_i_1_n_0, + Q => PWM_out_1, + R => '0' + ); +PWM_out_2_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFEF" + ) + port map ( + I0 => key3_reg_n_0, + I1 => \^mintimeer_reg_0\, + I2 => ready, + I3 => er, + I4 => breaking_en, + O => PWM_out_2_i_1_n_0 + ); +PWM_out_2_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => PWM_out_2_i_1_n_0, + Q => PWM_out_2, + R => '0' + ); +PWM_out_3_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFEF" + ) + port map ( + I0 => key4_reg_n_0, + I1 => \^mintimeer_reg_0\, + I2 => ready, + I3 => er, + I4 => breaking_en, + O => PWM_out_3_i_1_n_0 + ); +PWM_out_3_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => PWM_out_3_i_1_n_0, + Q => PWM_out_3, + R => '0' + ); +TKin0_triggered_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA08FFFFAA080000" + ) + port map ( + I0 => TKin0, + I1 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I2 => TKin1, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I4 => TKin0_triggered28_out, + I5 => TKin0_triggered, + O => TKin0_triggered_i_1_n_0 + ); +TKin0_triggered_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => TKin0_triggered_i_1_n_0, + Q => TKin0_triggered, + R => '0' + ); +TKin1_triggered_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA08FFFFAA080000" + ) + port map ( + I0 => TKin1, + I1 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I2 => TKin0, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I4 => TKin0_triggered28_out, + I5 => TKin1_triggered, + O => TKin1_triggered_i_1_n_0 + ); +TKin1_triggered_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"22AA22A820AA2020" + ) + port map ( + I0 => minTimeEr_i_9_n_0, + I1 => TKin1, + I2 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I3 => TKin0, + I4 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I5 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + O => TKin0_triggered28_out + ); +TKin1_triggered_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => TKin1_triggered_i_1_n_0, + Q => TKin1_triggered, + R => '0' + ); +\TimeCounter[0]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => TimeCounter_reg(0), + O => \TimeCounter[0]_i_2_n_0\ + ); +\TimeCounter_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[0]_i_1_n_7\, + Q => TimeCounter_reg(0), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[0]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \TimeCounter_reg[0]_i_1_n_0\, + CO(2) => \TimeCounter_reg[0]_i_1_n_1\, + CO(1) => \TimeCounter_reg[0]_i_1_n_2\, + CO(0) => \TimeCounter_reg[0]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \TimeCounter_reg[0]_i_1_n_4\, + O(2) => \TimeCounter_reg[0]_i_1_n_5\, + O(1) => \TimeCounter_reg[0]_i_1_n_6\, + O(0) => \TimeCounter_reg[0]_i_1_n_7\, + S(3 downto 1) => TimeCounter_reg(3 downto 1), + S(0) => \TimeCounter[0]_i_2_n_0\ + ); +\TimeCounter_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[8]_i_1_n_5\, + Q => TimeCounter_reg(10), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[8]_i_1_n_4\, + Q => TimeCounter_reg(11), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[12]_i_1_n_7\, + Q => TimeCounter_reg(12), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[8]_i_1_n_0\, + CO(3) => \TimeCounter_reg[12]_i_1_n_0\, + CO(2) => \TimeCounter_reg[12]_i_1_n_1\, + CO(1) => \TimeCounter_reg[12]_i_1_n_2\, + CO(0) => \TimeCounter_reg[12]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[12]_i_1_n_4\, + O(2) => \TimeCounter_reg[12]_i_1_n_5\, + O(1) => \TimeCounter_reg[12]_i_1_n_6\, + O(0) => \TimeCounter_reg[12]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(15 downto 12) + ); +\TimeCounter_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[12]_i_1_n_6\, + Q => TimeCounter_reg(13), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[12]_i_1_n_5\, + Q => TimeCounter_reg(14), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[12]_i_1_n_4\, + Q => TimeCounter_reg(15), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[16]_i_1_n_7\, + Q => TimeCounter_reg(16), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[16]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[12]_i_1_n_0\, + CO(3) => \TimeCounter_reg[16]_i_1_n_0\, + CO(2) => \TimeCounter_reg[16]_i_1_n_1\, + CO(1) => \TimeCounter_reg[16]_i_1_n_2\, + CO(0) => \TimeCounter_reg[16]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[16]_i_1_n_4\, + O(2) => \TimeCounter_reg[16]_i_1_n_5\, + O(1) => \TimeCounter_reg[16]_i_1_n_6\, + O(0) => \TimeCounter_reg[16]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(19 downto 16) + ); +\TimeCounter_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[16]_i_1_n_6\, + Q => TimeCounter_reg(17), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[16]_i_1_n_5\, + Q => TimeCounter_reg(18), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[16]_i_1_n_4\, + Q => TimeCounter_reg(19), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[0]_i_1_n_6\, + Q => TimeCounter_reg(1), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[20]_i_1_n_7\, + Q => TimeCounter_reg(20), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[20]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[16]_i_1_n_0\, + CO(3) => \TimeCounter_reg[20]_i_1_n_0\, + CO(2) => \TimeCounter_reg[20]_i_1_n_1\, + CO(1) => \TimeCounter_reg[20]_i_1_n_2\, + CO(0) => \TimeCounter_reg[20]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[20]_i_1_n_4\, + O(2) => \TimeCounter_reg[20]_i_1_n_5\, + O(1) => \TimeCounter_reg[20]_i_1_n_6\, + O(0) => \TimeCounter_reg[20]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(23 downto 20) + ); +\TimeCounter_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[20]_i_1_n_6\, + Q => TimeCounter_reg(21), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[20]_i_1_n_5\, + Q => TimeCounter_reg(22), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[20]_i_1_n_4\, + Q => TimeCounter_reg(23), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[24]_i_1_n_7\, + Q => TimeCounter_reg(24), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[24]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[20]_i_1_n_0\, + CO(3) => \TimeCounter_reg[24]_i_1_n_0\, + CO(2) => \TimeCounter_reg[24]_i_1_n_1\, + CO(1) => \TimeCounter_reg[24]_i_1_n_2\, + CO(0) => \TimeCounter_reg[24]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[24]_i_1_n_4\, + O(2) => \TimeCounter_reg[24]_i_1_n_5\, + O(1) => \TimeCounter_reg[24]_i_1_n_6\, + O(0) => \TimeCounter_reg[24]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(27 downto 24) + ); +\TimeCounter_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[24]_i_1_n_6\, + Q => TimeCounter_reg(25), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[24]_i_1_n_5\, + Q => TimeCounter_reg(26), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[24]_i_1_n_4\, + Q => TimeCounter_reg(27), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[28]_i_1_n_7\, + Q => TimeCounter_reg(28), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[28]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[24]_i_1_n_0\, + CO(3) => \NLW_TimeCounter_reg[28]_i_1_CO_UNCONNECTED\(3), + CO(2) => \TimeCounter_reg[28]_i_1_n_1\, + CO(1) => \TimeCounter_reg[28]_i_1_n_2\, + CO(0) => \TimeCounter_reg[28]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[28]_i_1_n_4\, + O(2) => \TimeCounter_reg[28]_i_1_n_5\, + O(1) => \TimeCounter_reg[28]_i_1_n_6\, + O(0) => \TimeCounter_reg[28]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(31 downto 28) + ); +\TimeCounter_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[28]_i_1_n_6\, + Q => TimeCounter_reg(29), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[0]_i_1_n_5\, + Q => TimeCounter_reg(2), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[28]_i_1_n_5\, + Q => TimeCounter_reg(30), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[28]_i_1_n_4\, + Q => TimeCounter_reg(31), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[0]_i_1_n_4\, + Q => TimeCounter_reg(3), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[4]_i_1_n_7\, + Q => TimeCounter_reg(4), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[0]_i_1_n_0\, + CO(3) => \TimeCounter_reg[4]_i_1_n_0\, + CO(2) => \TimeCounter_reg[4]_i_1_n_1\, + CO(1) => \TimeCounter_reg[4]_i_1_n_2\, + CO(0) => \TimeCounter_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[4]_i_1_n_4\, + O(2) => \TimeCounter_reg[4]_i_1_n_5\, + O(1) => \TimeCounter_reg[4]_i_1_n_6\, + O(0) => \TimeCounter_reg[4]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(7 downto 4) + ); +\TimeCounter_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[4]_i_1_n_6\, + Q => TimeCounter_reg(5), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[4]_i_1_n_5\, + Q => TimeCounter_reg(6), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[4]_i_1_n_4\, + Q => TimeCounter_reg(7), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[8]_i_1_n_7\, + Q => TimeCounter_reg(8), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[4]_i_1_n_0\, + CO(3) => \TimeCounter_reg[8]_i_1_n_0\, + CO(2) => \TimeCounter_reg[8]_i_1_n_1\, + CO(1) => \TimeCounter_reg[8]_i_1_n_2\, + CO(0) => \TimeCounter_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[8]_i_1_n_4\, + O(2) => \TimeCounter_reg[8]_i_1_n_5\, + O(1) => \TimeCounter_reg[8]_i_1_n_6\, + O(0) => \TimeCounter_reg[8]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(11 downto 8) + ); +\TimeCounter_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[8]_i_1_n_6\, + Q => TimeCounter_reg(9), + R => deadTimeCounterReset_reg_n_0 + ); +deadTimeCounterReset_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFE0000000E" + ) + port map ( + I0 => deadTimeCounterReset_i_2_n_0, + I1 => \FSM_onehot_lineconfig[6]_i_4_n_0\, + I2 => reset, + I3 => breaking_en, + I4 => deadTimeCounterReset_i_3_n_0, + I5 => deadTimeCounterReset_reg_n_0, + O => deadTimeCounterReset_i_1_n_0 + ); +deadTimeCounterReset_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + O => deadTimeCounterReset_i_2_n_0 + ); +deadTimeCounterReset_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000022220020" + ) + port map ( + I0 => deadTimeCounterReset_i_4_n_0, + I1 => deadTimeCounterReset_i_2_n_0, + I2 => deadTimeCounterReset_i_5_n_0, + I3 => deadTimeCounterReset_i_6_n_0, + I4 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I5 => deadTimeCounterReset_i_7_n_0, + O => deadTimeCounterReset_i_3_n_0 + ); +deadTimeCounterReset_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"555D555555555555" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I1 => deadTimeOK, + I2 => TKin1, + I3 => TKin1_triggered, + I4 => TKin0, + I5 => TKin0_triggered, + O => deadTimeCounterReset_i_4_n_0 + ); +deadTimeCounterReset_i_5: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => deadTimeOK, + I1 => ready, + I2 => er, + O => deadTimeCounterReset_i_5_n_0 + ); +deadTimeCounterReset_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"F777" + ) + port map ( + I0 => TKin0, + I1 => TKin1, + I2 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I3 => deadTimeCounterReset_reg_n_0, + O => deadTimeCounterReset_i_6_n_0 + ); +deadTimeCounterReset_i_7: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAA2AAAAAAAAAA" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I1 => TKin1, + I2 => TKin0, + I3 => deadTimeOK, + I4 => TKin0_triggered, + I5 => TKin1_triggered, + O => deadTimeCounterReset_i_7_n_0 + ); +deadTimeCounterReset_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => '1', + D => deadTimeCounterReset_i_1_n_0, + Q => deadTimeCounterReset_reg_n_0, + R => '0' + ); +deadTimeOK_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"0D" + ) + port map ( + I0 => sel, + I1 => deadTimeOK, + I2 => deadTimeCounterReset_reg_n_0, + O => deadTimeOK_i_1_n_0 + ); +deadTimeOK_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => deadTimeOK_i_1_n_0, + Q => deadTimeOK, + R => '0' + ); +key1_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"DDDDDDD0DDDDDDDD" + ) + port map ( + I0 => breaking_en, + I1 => TKin0, + I2 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I4 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I5 => key1_i_2_n_0, + O => key1_i_1_n_0 + ); +key1_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I3 => breaking_en, + O => key1_i_2_n_0 + ); +key1_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key1_reg_n_0, + Q => key1_prev, + R => '0' + ); +key1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key1_i_1_n_0, + Q => key1_reg_n_0, + R => '0' + ); +key2_i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => reset, + O => p_0_in + ); +key2_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAFFFFFFFC" + ) + port map ( + I0 => TKin1, + I1 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I4 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I5 => breaking_en, + O => key2_i_2_n_0 + ); +key2_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key2_reg_n_0, + Q => key2_prev, + R => '0' + ); +key2_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key2_i_2_n_0, + Q => key2_reg_n_0, + R => '0' + ); +key3_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAFFFFAAAAFCFF" + ) + port map ( + I0 => key3_reg_n_0, + I1 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I3 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I4 => reset, + I5 => breaking_en, + O => key3_i_1_n_0 + ); +key3_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key3_reg_n_0, + Q => key3_prev, + R => '0' + ); +key3_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => key3_i_1_n_0, + Q => key3_reg_n_0, + R => '0' + ); +key4_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAFFFFAAAAFFFC" + ) + port map ( + I0 => key4_reg_n_0, + I1 => key3, + I2 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I4 => reset, + I5 => breaking_en, + O => key4_i_1_n_0 + ); +key4_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + O => key3 + ); +key4_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key4_reg_n_0, + Q => key4_prev, + R => '0' + ); +key4_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => key4_i_1_n_0, + Q => key4_reg_n_0, + R => '0' + ); +\ltOp__15_carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \ltOp__15_carry_n_0\, + CO(2) => \ltOp__15_carry_n_1\, + CO(1) => \ltOp__15_carry_n_2\, + CO(0) => \ltOp__15_carry_n_3\, + CYINIT => '0', + DI(3) => \ltOp__15_carry_i_1_n_0\, + DI(2) => \ltOp__15_carry_i_2_n_0\, + DI(1) => \ltOp__15_carry_i_3_n_0\, + DI(0) => \ltOp__15_carry_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__15_carry_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__15_carry_i_5_n_0\, + S(2) => \ltOp__15_carry_i_6_n_0\, + S(1) => \ltOp__15_carry_i_7_n_0\, + S(0) => \ltOp__15_carry_i_8_n_0\ + ); +\ltOp__15_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__15_carry_n_0\, + CO(3) => \ltOp__15_carry__0_n_0\, + CO(2) => \ltOp__15_carry__0_n_1\, + CO(1) => \ltOp__15_carry__0_n_2\, + CO(0) => \ltOp__15_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp__15_carry__0_i_1_n_0\, + DI(2) => \ltOp__15_carry__0_i_2_n_0\, + DI(1) => \ltOp__15_carry__0_i_3_n_0\, + DI(0) => \ltOp__15_carry__0_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__15_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__15_carry__0_i_5_n_0\, + S(2) => \ltOp__15_carry__0_i_6_n_0\, + S(1) => \ltOp__15_carry__0_i_7_n_0\, + S(0) => \ltOp__15_carry__0_i_8_n_0\ + ); +\ltOp__15_carry__0_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(15), + I1 => minTimeCounter_low_reg(15), + I2 => minTime(14), + I3 => minTimeCounter_low_reg(14), + O => \ltOp__15_carry__0_i_1_n_0\ + ); +\ltOp__15_carry__0_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(13), + I1 => minTimeCounter_low_reg(13), + I2 => minTime(12), + I3 => minTimeCounter_low_reg(12), + O => \ltOp__15_carry__0_i_2_n_0\ + ); +\ltOp__15_carry__0_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(11), + I1 => minTimeCounter_low_reg(11), + I2 => minTime(10), + I3 => minTimeCounter_low_reg(10), + O => \ltOp__15_carry__0_i_3_n_0\ + ); +\ltOp__15_carry__0_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(9), + I1 => minTimeCounter_low_reg(9), + I2 => minTime(8), + I3 => minTimeCounter_low_reg(8), + O => \ltOp__15_carry__0_i_4_n_0\ + ); +\ltOp__15_carry__0_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(15), + I1 => minTime(15), + I2 => minTimeCounter_low_reg(14), + I3 => minTime(14), + O => \ltOp__15_carry__0_i_5_n_0\ + ); +\ltOp__15_carry__0_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(13), + I1 => minTime(13), + I2 => minTimeCounter_low_reg(12), + I3 => minTime(12), + O => \ltOp__15_carry__0_i_6_n_0\ + ); +\ltOp__15_carry__0_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(11), + I1 => minTime(11), + I2 => minTimeCounter_low_reg(10), + I3 => minTime(10), + O => \ltOp__15_carry__0_i_7_n_0\ + ); +\ltOp__15_carry__0_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(9), + I1 => minTime(9), + I2 => minTimeCounter_low_reg(8), + I3 => minTime(8), + O => \ltOp__15_carry__0_i_8_n_0\ + ); +\ltOp__15_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__15_carry__0_n_0\, + CO(3) => \ltOp__15_carry__1_n_0\, + CO(2) => \ltOp__15_carry__1_n_1\, + CO(1) => \ltOp__15_carry__1_n_2\, + CO(0) => \ltOp__15_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp__15_carry__1_i_1_n_0\, + DI(2) => \ltOp__15_carry__1_i_2_n_0\, + DI(1) => \ltOp__15_carry__1_i_3_n_0\, + DI(0) => \ltOp__15_carry__1_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__15_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__15_carry__1_i_5_n_0\, + S(2) => \ltOp__15_carry__1_i_6_n_0\, + S(1) => \ltOp__15_carry__1_i_7_n_0\, + S(0) => \ltOp__15_carry__1_i_8_n_0\ + ); +\ltOp__15_carry__1_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(23), + I1 => minTimeCounter_low_reg(23), + I2 => minTime(22), + I3 => minTimeCounter_low_reg(22), + O => \ltOp__15_carry__1_i_1_n_0\ + ); +\ltOp__15_carry__1_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(21), + I1 => minTimeCounter_low_reg(21), + I2 => minTime(20), + I3 => minTimeCounter_low_reg(20), + O => \ltOp__15_carry__1_i_2_n_0\ + ); +\ltOp__15_carry__1_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(19), + I1 => minTimeCounter_low_reg(19), + I2 => minTime(18), + I3 => minTimeCounter_low_reg(18), + O => \ltOp__15_carry__1_i_3_n_0\ + ); +\ltOp__15_carry__1_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(17), + I1 => minTimeCounter_low_reg(17), + I2 => minTime(16), + I3 => minTimeCounter_low_reg(16), + O => \ltOp__15_carry__1_i_4_n_0\ + ); +\ltOp__15_carry__1_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(23), + I1 => minTime(23), + I2 => minTimeCounter_low_reg(22), + I3 => minTime(22), + O => \ltOp__15_carry__1_i_5_n_0\ + ); +\ltOp__15_carry__1_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(21), + I1 => minTime(21), + I2 => minTimeCounter_low_reg(20), + I3 => minTime(20), + O => \ltOp__15_carry__1_i_6_n_0\ + ); +\ltOp__15_carry__1_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(19), + I1 => minTime(19), + I2 => minTimeCounter_low_reg(18), + I3 => minTime(18), + O => \ltOp__15_carry__1_i_7_n_0\ + ); +\ltOp__15_carry__1_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(17), + I1 => minTime(17), + I2 => minTimeCounter_low_reg(16), + I3 => minTime(16), + O => \ltOp__15_carry__1_i_8_n_0\ + ); +\ltOp__15_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__15_carry__1_n_0\, + CO(3) => \ltOp__15_carry__2_n_0\, + CO(2) => \ltOp__15_carry__2_n_1\, + CO(1) => \ltOp__15_carry__2_n_2\, + CO(0) => \ltOp__15_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp__15_carry__2_i_1_n_0\, + DI(2) => \ltOp__15_carry__2_i_2_n_0\, + DI(1) => \ltOp__15_carry__2_i_3_n_0\, + DI(0) => \ltOp__15_carry__2_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__15_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__15_carry__2_i_5_n_0\, + S(2) => \ltOp__15_carry__2_i_6_n_0\, + S(1) => \ltOp__15_carry__2_i_7_n_0\, + S(0) => \ltOp__15_carry__2_i_8_n_0\ + ); +\ltOp__15_carry__2_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(31), + I1 => minTimeCounter_low_reg(31), + I2 => minTime(30), + I3 => minTimeCounter_low_reg(30), + O => \ltOp__15_carry__2_i_1_n_0\ + ); +\ltOp__15_carry__2_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(29), + I1 => minTimeCounter_low_reg(29), + I2 => minTime(28), + I3 => minTimeCounter_low_reg(28), + O => \ltOp__15_carry__2_i_2_n_0\ + ); +\ltOp__15_carry__2_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(27), + I1 => minTimeCounter_low_reg(27), + I2 => minTime(26), + I3 => minTimeCounter_low_reg(26), + O => \ltOp__15_carry__2_i_3_n_0\ + ); +\ltOp__15_carry__2_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(25), + I1 => minTimeCounter_low_reg(25), + I2 => minTime(24), + I3 => minTimeCounter_low_reg(24), + O => \ltOp__15_carry__2_i_4_n_0\ + ); +\ltOp__15_carry__2_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(31), + I1 => minTime(31), + I2 => minTimeCounter_low_reg(30), + I3 => minTime(30), + O => \ltOp__15_carry__2_i_5_n_0\ + ); +\ltOp__15_carry__2_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(29), + I1 => minTime(29), + I2 => minTimeCounter_low_reg(28), + I3 => minTime(28), + O => \ltOp__15_carry__2_i_6_n_0\ + ); +\ltOp__15_carry__2_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(27), + I1 => minTime(27), + I2 => minTimeCounter_low_reg(26), + I3 => minTime(26), + O => \ltOp__15_carry__2_i_7_n_0\ + ); +\ltOp__15_carry__2_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(25), + I1 => minTime(25), + I2 => minTimeCounter_low_reg(24), + I3 => minTime(24), + O => \ltOp__15_carry__2_i_8_n_0\ + ); +\ltOp__15_carry_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(7), + I1 => minTimeCounter_low_reg(7), + I2 => minTime(6), + I3 => minTimeCounter_low_reg(6), + O => \ltOp__15_carry_i_1_n_0\ + ); +\ltOp__15_carry_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(5), + I1 => minTimeCounter_low_reg(5), + I2 => minTime(4), + I3 => minTimeCounter_low_reg(4), + O => \ltOp__15_carry_i_2_n_0\ + ); +\ltOp__15_carry_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(3), + I1 => minTimeCounter_low_reg(3), + I2 => minTime(2), + I3 => minTimeCounter_low_reg(2), + O => \ltOp__15_carry_i_3_n_0\ + ); +\ltOp__15_carry_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(1), + I1 => minTimeCounter_low_reg(1), + I2 => minTime(0), + I3 => minTimeCounter_low_reg(0), + O => \ltOp__15_carry_i_4_n_0\ + ); +\ltOp__15_carry_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(7), + I1 => minTime(7), + I2 => minTimeCounter_low_reg(6), + I3 => minTime(6), + O => \ltOp__15_carry_i_5_n_0\ + ); +\ltOp__15_carry_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(5), + I1 => minTime(5), + I2 => minTimeCounter_low_reg(4), + I3 => minTime(4), + O => \ltOp__15_carry_i_6_n_0\ + ); +\ltOp__15_carry_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(3), + I1 => minTime(3), + I2 => minTimeCounter_low_reg(2), + I3 => minTime(2), + O => \ltOp__15_carry_i_7_n_0\ + ); +\ltOp__15_carry_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(1), + I1 => minTime(1), + I2 => minTimeCounter_low_reg(0), + I3 => minTime(0), + O => \ltOp__15_carry_i_8_n_0\ + ); +\ltOp__31_carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \ltOp__31_carry_n_0\, + CO(2) => \ltOp__31_carry_n_1\, + CO(1) => \ltOp__31_carry_n_2\, + CO(0) => \ltOp__31_carry_n_3\, + CYINIT => '0', + DI(3) => \ltOp__31_carry_i_1_n_0\, + DI(2) => \ltOp__31_carry_i_2_n_0\, + DI(1) => \ltOp__31_carry_i_3_n_0\, + DI(0) => \ltOp__31_carry_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__31_carry_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__31_carry_i_5_n_0\, + S(2) => \ltOp__31_carry_i_6_n_0\, + S(1) => \ltOp__31_carry_i_7_n_0\, + S(0) => \ltOp__31_carry_i_8_n_0\ + ); +\ltOp__31_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__31_carry_n_0\, + CO(3) => \ltOp__31_carry__0_n_0\, + CO(2) => \ltOp__31_carry__0_n_1\, + CO(1) => \ltOp__31_carry__0_n_2\, + CO(0) => \ltOp__31_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp__31_carry_i_1__0_n_0\, + DI(2) => \ltOp__31_carry_i_2__0_n_0\, + DI(1) => \ltOp__31_carry_i_3__0_n_0\, + DI(0) => \ltOp__31_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp__31_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__31_carry_i_5__0_n_0\, + S(2) => \ltOp__31_carry_i_6__0_n_0\, + S(1) => \ltOp__31_carry_i_7__0_n_0\, + S(0) => \ltOp__31_carry_i_8__0_n_0\ + ); +\ltOp__31_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__31_carry__0_n_0\, + CO(3) => \ltOp__31_carry__1_n_0\, + CO(2) => \ltOp__31_carry__1_n_1\, + CO(1) => \ltOp__31_carry__1_n_2\, + CO(0) => \ltOp__31_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp__31_carry_i_1__1_n_0\, + DI(2) => \ltOp__31_carry_i_2__1_n_0\, + DI(1) => \ltOp__31_carry_i_3__1_n_0\, + DI(0) => \ltOp__31_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp__31_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__31_carry_i_5__1_n_0\, + S(2) => \ltOp__31_carry_i_6__1_n_0\, + S(1) => \ltOp__31_carry_i_7__1_n_0\, + S(0) => \ltOp__31_carry_i_8__1_n_0\ + ); +\ltOp__31_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__31_carry__1_n_0\, + CO(3) => \ltOp__31_carry__2_n_0\, + CO(2) => \ltOp__31_carry__2_n_1\, + CO(1) => \ltOp__31_carry__2_n_2\, + CO(0) => \ltOp__31_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp__31_carry_i_1__2_n_0\, + DI(2) => \ltOp__31_carry_i_2__2_n_0\, + DI(1) => \ltOp__31_carry_i_3__2_n_0\, + DI(0) => \ltOp__31_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp__31_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__31_carry_i_5__2_n_0\, + S(2) => \ltOp__31_carry_i_6__2_n_0\, + S(1) => \ltOp__31_carry_i_7__2_n_0\, + S(0) => \ltOp__31_carry_i_8__2_n_0\ + ); +\ltOp__31_carry_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(7), + I1 => minTimeCounter_high_reg(7), + I2 => minTime(6), + I3 => minTimeCounter_high_reg(6), + O => \ltOp__31_carry_i_1_n_0\ + ); +\ltOp__31_carry_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(15), + I1 => minTimeCounter_high_reg(15), + I2 => minTime(14), + I3 => minTimeCounter_high_reg(14), + O => \ltOp__31_carry_i_1__0_n_0\ + ); +\ltOp__31_carry_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(23), + I1 => minTimeCounter_high_reg(23), + I2 => minTime(22), + I3 => minTimeCounter_high_reg(22), + O => \ltOp__31_carry_i_1__1_n_0\ + ); +\ltOp__31_carry_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(31), + I1 => minTimeCounter_high_reg(31), + I2 => minTime(30), + I3 => minTimeCounter_high_reg(30), + O => \ltOp__31_carry_i_1__2_n_0\ + ); +\ltOp__31_carry_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(5), + I1 => minTimeCounter_high_reg(5), + I2 => minTime(4), + I3 => minTimeCounter_high_reg(4), + O => \ltOp__31_carry_i_2_n_0\ + ); +\ltOp__31_carry_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(13), + I1 => minTimeCounter_high_reg(13), + I2 => minTime(12), + I3 => minTimeCounter_high_reg(12), + O => \ltOp__31_carry_i_2__0_n_0\ + ); +\ltOp__31_carry_i_2__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(21), + I1 => minTimeCounter_high_reg(21), + I2 => minTime(20), + I3 => minTimeCounter_high_reg(20), + O => \ltOp__31_carry_i_2__1_n_0\ + ); +\ltOp__31_carry_i_2__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(29), + I1 => minTimeCounter_high_reg(29), + I2 => minTime(28), + I3 => minTimeCounter_high_reg(28), + O => \ltOp__31_carry_i_2__2_n_0\ + ); +\ltOp__31_carry_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(3), + I1 => minTimeCounter_high_reg(3), + I2 => minTime(2), + I3 => minTimeCounter_high_reg(2), + O => \ltOp__31_carry_i_3_n_0\ + ); +\ltOp__31_carry_i_3__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(11), + I1 => minTimeCounter_high_reg(11), + I2 => minTime(10), + I3 => minTimeCounter_high_reg(10), + O => \ltOp__31_carry_i_3__0_n_0\ + ); +\ltOp__31_carry_i_3__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(19), + I1 => minTimeCounter_high_reg(19), + I2 => minTime(18), + I3 => minTimeCounter_high_reg(18), + O => \ltOp__31_carry_i_3__1_n_0\ + ); +\ltOp__31_carry_i_3__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(27), + I1 => minTimeCounter_high_reg(27), + I2 => minTime(26), + I3 => minTimeCounter_high_reg(26), + O => \ltOp__31_carry_i_3__2_n_0\ + ); +\ltOp__31_carry_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(1), + I1 => minTimeCounter_high_reg(1), + I2 => minTime(0), + I3 => minTimeCounter_high_reg(0), + O => \ltOp__31_carry_i_4_n_0\ + ); +\ltOp__31_carry_i_4__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(9), + I1 => minTimeCounter_high_reg(9), + I2 => minTime(8), + I3 => minTimeCounter_high_reg(8), + O => \ltOp__31_carry_i_4__0_n_0\ + ); +\ltOp__31_carry_i_4__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(17), + I1 => minTimeCounter_high_reg(17), + I2 => minTime(16), + I3 => minTimeCounter_high_reg(16), + O => \ltOp__31_carry_i_4__1_n_0\ + ); +\ltOp__31_carry_i_4__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(25), + I1 => minTimeCounter_high_reg(25), + I2 => minTime(24), + I3 => minTimeCounter_high_reg(24), + O => \ltOp__31_carry_i_4__2_n_0\ + ); +\ltOp__31_carry_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(7), + I1 => minTime(7), + I2 => minTimeCounter_high_reg(6), + I3 => minTime(6), + O => \ltOp__31_carry_i_5_n_0\ + ); +\ltOp__31_carry_i_5__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(15), + I1 => minTime(15), + I2 => minTimeCounter_high_reg(14), + I3 => minTime(14), + O => \ltOp__31_carry_i_5__0_n_0\ + ); +\ltOp__31_carry_i_5__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(23), + I1 => minTime(23), + I2 => minTimeCounter_high_reg(22), + I3 => minTime(22), + O => \ltOp__31_carry_i_5__1_n_0\ + ); +\ltOp__31_carry_i_5__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(31), + I1 => minTime(31), + I2 => minTimeCounter_high_reg(30), + I3 => minTime(30), + O => \ltOp__31_carry_i_5__2_n_0\ + ); +\ltOp__31_carry_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(5), + I1 => minTime(5), + I2 => minTimeCounter_high_reg(4), + I3 => minTime(4), + O => \ltOp__31_carry_i_6_n_0\ + ); +\ltOp__31_carry_i_6__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(13), + I1 => minTime(13), + I2 => minTimeCounter_high_reg(12), + I3 => minTime(12), + O => \ltOp__31_carry_i_6__0_n_0\ + ); +\ltOp__31_carry_i_6__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(21), + I1 => minTime(21), + I2 => minTimeCounter_high_reg(20), + I3 => minTime(20), + O => \ltOp__31_carry_i_6__1_n_0\ + ); +\ltOp__31_carry_i_6__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(29), + I1 => minTime(29), + I2 => minTimeCounter_high_reg(28), + I3 => minTime(28), + O => \ltOp__31_carry_i_6__2_n_0\ + ); +\ltOp__31_carry_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(3), + I1 => minTime(3), + I2 => minTimeCounter_high_reg(2), + I3 => minTime(2), + O => \ltOp__31_carry_i_7_n_0\ + ); +\ltOp__31_carry_i_7__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(11), + I1 => minTime(11), + I2 => minTimeCounter_high_reg(10), + I3 => minTime(10), + O => \ltOp__31_carry_i_7__0_n_0\ + ); +\ltOp__31_carry_i_7__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(19), + I1 => minTime(19), + I2 => minTimeCounter_high_reg(18), + I3 => minTime(18), + O => \ltOp__31_carry_i_7__1_n_0\ + ); +\ltOp__31_carry_i_7__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(27), + I1 => minTime(27), + I2 => minTimeCounter_high_reg(26), + I3 => minTime(26), + O => \ltOp__31_carry_i_7__2_n_0\ + ); +\ltOp__31_carry_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(1), + I1 => minTime(1), + I2 => minTimeCounter_high_reg(0), + I3 => minTime(0), + O => \ltOp__31_carry_i_8_n_0\ + ); +\ltOp__31_carry_i_8__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(9), + I1 => minTime(9), + I2 => minTimeCounter_high_reg(8), + I3 => minTime(8), + O => \ltOp__31_carry_i_8__0_n_0\ + ); +\ltOp__31_carry_i_8__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(17), + I1 => minTime(17), + I2 => minTimeCounter_high_reg(16), + I3 => minTime(16), + O => \ltOp__31_carry_i_8__1_n_0\ + ); +\ltOp__31_carry_i_8__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(25), + I1 => minTime(25), + I2 => minTimeCounter_high_reg(24), + I3 => minTime(24), + O => \ltOp__31_carry_i_8__2_n_0\ + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry__0_i_1_n_0\, + DI(2) => \ltOp_carry__0_i_2_n_0\, + DI(1) => \ltOp_carry__0_i_3_n_0\, + DI(0) => \ltOp_carry__0_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry__0_i_5_n_0\, + S(2) => \ltOp_carry__0_i_6_n_0\, + S(1) => \ltOp_carry__0_i_7_n_0\, + S(0) => \ltOp_carry__0_i_8_n_0\ + ); +\ltOp_carry__0_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(15), + I1 => TimeCounter_reg(15), + I2 => deadTime(14), + I3 => TimeCounter_reg(14), + O => \ltOp_carry__0_i_1_n_0\ + ); +\ltOp_carry__0_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(13), + I1 => TimeCounter_reg(13), + I2 => deadTime(12), + I3 => TimeCounter_reg(12), + O => \ltOp_carry__0_i_2_n_0\ + ); +\ltOp_carry__0_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(11), + I1 => TimeCounter_reg(11), + I2 => deadTime(10), + I3 => TimeCounter_reg(10), + O => \ltOp_carry__0_i_3_n_0\ + ); +\ltOp_carry__0_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(9), + I1 => TimeCounter_reg(9), + I2 => deadTime(8), + I3 => TimeCounter_reg(8), + O => \ltOp_carry__0_i_4_n_0\ + ); +\ltOp_carry__0_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(15), + I1 => deadTime(15), + I2 => TimeCounter_reg(14), + I3 => deadTime(14), + O => \ltOp_carry__0_i_5_n_0\ + ); +\ltOp_carry__0_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(13), + I1 => deadTime(13), + I2 => TimeCounter_reg(12), + I3 => deadTime(12), + O => \ltOp_carry__0_i_6_n_0\ + ); +\ltOp_carry__0_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(11), + I1 => deadTime(11), + I2 => TimeCounter_reg(10), + I3 => deadTime(10), + O => \ltOp_carry__0_i_7_n_0\ + ); +\ltOp_carry__0_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(9), + I1 => deadTime(9), + I2 => TimeCounter_reg(8), + I3 => deadTime(8), + O => \ltOp_carry__0_i_8_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry__1_i_1_n_0\, + DI(2) => \ltOp_carry__1_i_2_n_0\, + DI(1) => \ltOp_carry__1_i_3_n_0\, + DI(0) => \ltOp_carry__1_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry__1_i_5_n_0\, + S(2) => \ltOp_carry__1_i_6_n_0\, + S(1) => \ltOp_carry__1_i_7_n_0\, + S(0) => \ltOp_carry__1_i_8_n_0\ + ); +\ltOp_carry__1_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(23), + I1 => TimeCounter_reg(23), + I2 => deadTime(22), + I3 => TimeCounter_reg(22), + O => \ltOp_carry__1_i_1_n_0\ + ); +\ltOp_carry__1_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(21), + I1 => TimeCounter_reg(21), + I2 => deadTime(20), + I3 => TimeCounter_reg(20), + O => \ltOp_carry__1_i_2_n_0\ + ); +\ltOp_carry__1_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(19), + I1 => TimeCounter_reg(19), + I2 => deadTime(18), + I3 => TimeCounter_reg(18), + O => \ltOp_carry__1_i_3_n_0\ + ); +\ltOp_carry__1_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(17), + I1 => TimeCounter_reg(17), + I2 => deadTime(16), + I3 => TimeCounter_reg(16), + O => \ltOp_carry__1_i_4_n_0\ + ); +\ltOp_carry__1_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(23), + I1 => deadTime(23), + I2 => TimeCounter_reg(22), + I3 => deadTime(22), + O => \ltOp_carry__1_i_5_n_0\ + ); +\ltOp_carry__1_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(21), + I1 => deadTime(21), + I2 => TimeCounter_reg(20), + I3 => deadTime(20), + O => \ltOp_carry__1_i_6_n_0\ + ); +\ltOp_carry__1_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(19), + I1 => deadTime(19), + I2 => TimeCounter_reg(18), + I3 => deadTime(18), + O => \ltOp_carry__1_i_7_n_0\ + ); +\ltOp_carry__1_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(17), + I1 => deadTime(17), + I2 => TimeCounter_reg(16), + I3 => deadTime(16), + O => \ltOp_carry__1_i_8_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => sel, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry__2_i_1_n_0\, + DI(2) => \ltOp_carry__2_i_2_n_0\, + DI(1) => \ltOp_carry__2_i_3_n_0\, + DI(0) => \ltOp_carry__2_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry__2_i_5_n_0\, + S(2) => \ltOp_carry__2_i_6_n_0\, + S(1) => \ltOp_carry__2_i_7_n_0\, + S(0) => \ltOp_carry__2_i_8_n_0\ + ); +\ltOp_carry__2_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(31), + I1 => TimeCounter_reg(31), + I2 => deadTime(30), + I3 => TimeCounter_reg(30), + O => \ltOp_carry__2_i_1_n_0\ + ); +\ltOp_carry__2_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(29), + I1 => TimeCounter_reg(29), + I2 => deadTime(28), + I3 => TimeCounter_reg(28), + O => \ltOp_carry__2_i_2_n_0\ + ); +\ltOp_carry__2_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(27), + I1 => TimeCounter_reg(27), + I2 => deadTime(26), + I3 => TimeCounter_reg(26), + O => \ltOp_carry__2_i_3_n_0\ + ); +\ltOp_carry__2_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(25), + I1 => TimeCounter_reg(25), + I2 => deadTime(24), + I3 => TimeCounter_reg(24), + O => \ltOp_carry__2_i_4_n_0\ + ); +\ltOp_carry__2_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(31), + I1 => deadTime(31), + I2 => TimeCounter_reg(30), + I3 => deadTime(30), + O => \ltOp_carry__2_i_5_n_0\ + ); +\ltOp_carry__2_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(29), + I1 => deadTime(29), + I2 => TimeCounter_reg(28), + I3 => deadTime(28), + O => \ltOp_carry__2_i_6_n_0\ + ); +\ltOp_carry__2_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(27), + I1 => deadTime(27), + I2 => TimeCounter_reg(26), + I3 => deadTime(26), + O => \ltOp_carry__2_i_7_n_0\ + ); +\ltOp_carry__2_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(25), + I1 => deadTime(25), + I2 => TimeCounter_reg(24), + I3 => deadTime(24), + O => \ltOp_carry__2_i_8_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(7), + I1 => TimeCounter_reg(7), + I2 => deadTime(6), + I3 => TimeCounter_reg(6), + O => ltOp_carry_i_1_n_0 + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(5), + I1 => TimeCounter_reg(5), + I2 => deadTime(4), + I3 => TimeCounter_reg(4), + O => ltOp_carry_i_2_n_0 + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(3), + I1 => TimeCounter_reg(3), + I2 => deadTime(2), + I3 => TimeCounter_reg(2), + O => ltOp_carry_i_3_n_0 + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(1), + I1 => TimeCounter_reg(1), + I2 => deadTime(0), + I3 => TimeCounter_reg(0), + O => ltOp_carry_i_4_n_0 + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(7), + I1 => deadTime(7), + I2 => TimeCounter_reg(6), + I3 => deadTime(6), + O => ltOp_carry_i_5_n_0 + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(5), + I1 => deadTime(5), + I2 => TimeCounter_reg(4), + I3 => deadTime(4), + O => ltOp_carry_i_6_n_0 + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(3), + I1 => deadTime(3), + I2 => TimeCounter_reg(2), + I3 => deadTime(2), + O => ltOp_carry_i_7_n_0 + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(1), + I1 => deadTime(1), + I2 => TimeCounter_reg(0), + I3 => deadTime(0), + O => ltOp_carry_i_8_n_0 + ); +\minTimeCounter_high[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000022222F22" + ) + port map ( + I0 => key1_prev, + I1 => key1_reg_n_0, + I2 => key2_reg_n_0, + I3 => key2_prev, + I4 => breaking_en, + I5 => reset, + O => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high[0]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \ltOp__31_carry__2_n_0\, + I1 => reset, + O => minTimeCounter_high + ); +\minTimeCounter_high[0]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => minTimeCounter_high_reg(0), + O => \minTimeCounter_high[0]_i_4_n_0\ + ); +\minTimeCounter_high_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[0]_i_3_n_7\, + Q => minTimeCounter_high_reg(0), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[0]_i_3\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \minTimeCounter_high_reg[0]_i_3_n_0\, + CO(2) => \minTimeCounter_high_reg[0]_i_3_n_1\, + CO(1) => \minTimeCounter_high_reg[0]_i_3_n_2\, + CO(0) => \minTimeCounter_high_reg[0]_i_3_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \minTimeCounter_high_reg[0]_i_3_n_4\, + O(2) => \minTimeCounter_high_reg[0]_i_3_n_5\, + O(1) => \minTimeCounter_high_reg[0]_i_3_n_6\, + O(0) => \minTimeCounter_high_reg[0]_i_3_n_7\, + S(3 downto 1) => minTimeCounter_high_reg(3 downto 1), + S(0) => \minTimeCounter_high[0]_i_4_n_0\ + ); +\minTimeCounter_high_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[8]_i_1_n_5\, + Q => minTimeCounter_high_reg(10), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[8]_i_1_n_4\, + Q => minTimeCounter_high_reg(11), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[12]_i_1_n_7\, + Q => minTimeCounter_high_reg(12), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[8]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[12]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[12]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[12]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[12]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[12]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[12]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[12]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[12]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(15 downto 12) + ); +\minTimeCounter_high_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[12]_i_1_n_6\, + Q => minTimeCounter_high_reg(13), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[12]_i_1_n_5\, + Q => minTimeCounter_high_reg(14), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[12]_i_1_n_4\, + Q => minTimeCounter_high_reg(15), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[16]_i_1_n_7\, + Q => minTimeCounter_high_reg(16), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[16]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[12]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[16]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[16]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[16]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[16]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[16]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[16]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[16]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[16]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(19 downto 16) + ); +\minTimeCounter_high_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[16]_i_1_n_6\, + Q => minTimeCounter_high_reg(17), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[16]_i_1_n_5\, + Q => minTimeCounter_high_reg(18), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[16]_i_1_n_4\, + Q => minTimeCounter_high_reg(19), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[0]_i_3_n_6\, + Q => minTimeCounter_high_reg(1), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[20]_i_1_n_7\, + Q => minTimeCounter_high_reg(20), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[20]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[16]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[20]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[20]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[20]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[20]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[20]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[20]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[20]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[20]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(23 downto 20) + ); +\minTimeCounter_high_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[20]_i_1_n_6\, + Q => minTimeCounter_high_reg(21), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[20]_i_1_n_5\, + Q => minTimeCounter_high_reg(22), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[20]_i_1_n_4\, + Q => minTimeCounter_high_reg(23), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[24]_i_1_n_7\, + Q => minTimeCounter_high_reg(24), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[24]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[20]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[24]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[24]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[24]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[24]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[24]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[24]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[24]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[24]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(27 downto 24) + ); +\minTimeCounter_high_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[24]_i_1_n_6\, + Q => minTimeCounter_high_reg(25), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[24]_i_1_n_5\, + Q => minTimeCounter_high_reg(26), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[24]_i_1_n_4\, + Q => minTimeCounter_high_reg(27), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[28]_i_1_n_7\, + Q => minTimeCounter_high_reg(28), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[28]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[24]_i_1_n_0\, + CO(3) => \NLW_minTimeCounter_high_reg[28]_i_1_CO_UNCONNECTED\(3), + CO(2) => \minTimeCounter_high_reg[28]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[28]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[28]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[28]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[28]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[28]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[28]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(31 downto 28) + ); +\minTimeCounter_high_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[28]_i_1_n_6\, + Q => minTimeCounter_high_reg(29), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[0]_i_3_n_5\, + Q => minTimeCounter_high_reg(2), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[28]_i_1_n_5\, + Q => minTimeCounter_high_reg(30), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[28]_i_1_n_4\, + Q => minTimeCounter_high_reg(31), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[0]_i_3_n_4\, + Q => minTimeCounter_high_reg(3), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[4]_i_1_n_7\, + Q => minTimeCounter_high_reg(4), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[0]_i_3_n_0\, + CO(3) => \minTimeCounter_high_reg[4]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[4]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[4]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[4]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[4]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[4]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[4]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(7 downto 4) + ); +\minTimeCounter_high_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[4]_i_1_n_6\, + Q => minTimeCounter_high_reg(5), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[4]_i_1_n_5\, + Q => minTimeCounter_high_reg(6), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[4]_i_1_n_4\, + Q => minTimeCounter_high_reg(7), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[8]_i_1_n_7\, + Q => minTimeCounter_high_reg(8), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[4]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[8]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[8]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[8]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[8]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[8]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[8]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[8]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(11 downto 8) + ); +\minTimeCounter_high_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[8]_i_1_n_6\, + Q => minTimeCounter_high_reg(9), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_low[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000440F" + ) + port map ( + I0 => key2_reg_n_0, + I1 => key2_prev, + I2 => \minTimeCounter_low[0]_i_4_n_0\, + I3 => breaking_en, + I4 => reset, + O => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low[0]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \ltOp__15_carry__2_n_0\, + I1 => reset, + O => minTimeCounter_low + ); +\minTimeCounter_low[0]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"D0DD" + ) + port map ( + I0 => key4_prev, + I1 => key4_reg_n_0, + I2 => key3_reg_n_0, + I3 => key3_prev, + O => \minTimeCounter_low[0]_i_4_n_0\ + ); +\minTimeCounter_low[0]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => minTimeCounter_low_reg(0), + O => \minTimeCounter_low[0]_i_5_n_0\ + ); +\minTimeCounter_low_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[0]_i_3_n_7\, + Q => minTimeCounter_low_reg(0), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[0]_i_3\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \minTimeCounter_low_reg[0]_i_3_n_0\, + CO(2) => \minTimeCounter_low_reg[0]_i_3_n_1\, + CO(1) => \minTimeCounter_low_reg[0]_i_3_n_2\, + CO(0) => \minTimeCounter_low_reg[0]_i_3_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \minTimeCounter_low_reg[0]_i_3_n_4\, + O(2) => \minTimeCounter_low_reg[0]_i_3_n_5\, + O(1) => \minTimeCounter_low_reg[0]_i_3_n_6\, + O(0) => \minTimeCounter_low_reg[0]_i_3_n_7\, + S(3 downto 1) => minTimeCounter_low_reg(3 downto 1), + S(0) => \minTimeCounter_low[0]_i_5_n_0\ + ); +\minTimeCounter_low_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[8]_i_1_n_5\, + Q => minTimeCounter_low_reg(10), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[8]_i_1_n_4\, + Q => minTimeCounter_low_reg(11), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[12]_i_1_n_7\, + Q => minTimeCounter_low_reg(12), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[8]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[12]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[12]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[12]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[12]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[12]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[12]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[12]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[12]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(15 downto 12) + ); +\minTimeCounter_low_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[12]_i_1_n_6\, + Q => minTimeCounter_low_reg(13), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[12]_i_1_n_5\, + Q => minTimeCounter_low_reg(14), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[12]_i_1_n_4\, + Q => minTimeCounter_low_reg(15), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[16]_i_1_n_7\, + Q => minTimeCounter_low_reg(16), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[16]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[12]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[16]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[16]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[16]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[16]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[16]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[16]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[16]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[16]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(19 downto 16) + ); +\minTimeCounter_low_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[16]_i_1_n_6\, + Q => minTimeCounter_low_reg(17), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[16]_i_1_n_5\, + Q => minTimeCounter_low_reg(18), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[16]_i_1_n_4\, + Q => minTimeCounter_low_reg(19), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[0]_i_3_n_6\, + Q => minTimeCounter_low_reg(1), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[20]_i_1_n_7\, + Q => minTimeCounter_low_reg(20), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[20]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[16]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[20]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[20]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[20]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[20]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[20]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[20]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[20]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[20]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(23 downto 20) + ); +\minTimeCounter_low_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[20]_i_1_n_6\, + Q => minTimeCounter_low_reg(21), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[20]_i_1_n_5\, + Q => minTimeCounter_low_reg(22), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[20]_i_1_n_4\, + Q => minTimeCounter_low_reg(23), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[24]_i_1_n_7\, + Q => minTimeCounter_low_reg(24), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[24]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[20]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[24]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[24]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[24]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[24]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[24]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[24]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[24]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[24]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(27 downto 24) + ); +\minTimeCounter_low_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[24]_i_1_n_6\, + Q => minTimeCounter_low_reg(25), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[24]_i_1_n_5\, + Q => minTimeCounter_low_reg(26), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[24]_i_1_n_4\, + Q => minTimeCounter_low_reg(27), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[28]_i_1_n_7\, + Q => minTimeCounter_low_reg(28), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[28]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[24]_i_1_n_0\, + CO(3) => \NLW_minTimeCounter_low_reg[28]_i_1_CO_UNCONNECTED\(3), + CO(2) => \minTimeCounter_low_reg[28]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[28]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[28]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[28]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[28]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[28]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[28]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(31 downto 28) + ); +\minTimeCounter_low_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[28]_i_1_n_6\, + Q => minTimeCounter_low_reg(29), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[0]_i_3_n_5\, + Q => minTimeCounter_low_reg(2), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[28]_i_1_n_5\, + Q => minTimeCounter_low_reg(30), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[28]_i_1_n_4\, + Q => minTimeCounter_low_reg(31), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[0]_i_3_n_4\, + Q => minTimeCounter_low_reg(3), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[4]_i_1_n_7\, + Q => minTimeCounter_low_reg(4), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[0]_i_3_n_0\, + CO(3) => \minTimeCounter_low_reg[4]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[4]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[4]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[4]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[4]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[4]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[4]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(7 downto 4) + ); +\minTimeCounter_low_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[4]_i_1_n_6\, + Q => minTimeCounter_low_reg(5), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[4]_i_1_n_5\, + Q => minTimeCounter_low_reg(6), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[4]_i_1_n_4\, + Q => minTimeCounter_low_reg(7), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[8]_i_1_n_7\, + Q => minTimeCounter_low_reg(8), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[4]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[8]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[8]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[8]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[8]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[8]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[8]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[8]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(11 downto 8) + ); +\minTimeCounter_low_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[8]_i_1_n_6\, + Q => minTimeCounter_low_reg(9), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +minTimeEr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"EEFFEEEEE200E2E2" + ) + port map ( + I0 => minTimeEr_i_2_n_0, + I1 => minTimeEr_i_3_n_0, + I2 => minTimeEr_i_4_n_0, + I3 => minTimeEr_i_5_n_0, + I4 => minTimeEr_i_6_n_0, + I5 => \^mintimeer_reg_0\, + O => minTimeEr_i_1_n_0 + ); +minTimeEr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"0111" + ) + port map ( + I0 => reset, + I1 => breaking_en, + I2 => minTimeEr_i_6_n_0, + I3 => minTimeEr_i_7_n_0, + O => minTimeEr_i_2_n_0 + ); +minTimeEr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => breaking_en, + I1 => reset, + O => minTimeEr_i_3_n_0 + ); +minTimeEr_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"040404FF00000000" + ) + port map ( + I0 => minTimeOK_low, + I1 => key2_reg_n_0, + I2 => key2_prev, + I3 => minTimeEr_i_8_n_0, + I4 => minTimeOK_high, + I5 => minTime_En, + O => minTimeEr_i_4_n_0 + ); +minTimeEr_i_5: unisim.vcomponents.LUT6 + generic map( + INIT => X"55555555F755F7F7" + ) + port map ( + I0 => minTimeEr_i_9_n_0, + I1 => key2_prev, + I2 => key2_reg_n_0, + I3 => key1_reg_n_0, + I4 => key1_prev, + I5 => minTimeEr_i_7_n_0, + O => minTimeEr_i_5_n_0 + ); +minTimeEr_i_6: unisim.vcomponents.LUT6 + generic map( + INIT => X"FBFFFFFFBBFBFBFF" + ) + port map ( + I0 => minTimeOK_low, + I1 => minTime_En, + I2 => key3_prev, + I3 => key3_reg_n_0, + I4 => key4_reg_n_0, + I5 => key4_prev, + O => minTimeEr_i_6_n_0 + ); +minTimeEr_i_7: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFDFDDDDFFDFFFDF" + ) + port map ( + I0 => minTime_En, + I1 => minTimeOK_high, + I2 => key2_reg_n_0, + I3 => key2_prev, + I4 => key1_prev, + I5 => key1_reg_n_0, + O => minTimeEr_i_7_n_0 + ); +minTimeEr_i_8: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => key1_prev, + I1 => key1_reg_n_0, + O => minTimeEr_i_8_n_0 + ); +minTimeEr_i_9: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => breaking_en, + I1 => reset, + O => minTimeEr_i_9_n_0 + ); +minTimeEr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => '1', + D => minTimeEr_i_1_n_0, + Q => \^mintimeer_reg_0\, + R => '0' + ); +minTimeOK_high_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"00AB" + ) + port map ( + I0 => minTimeOK_high, + I1 => \ltOp__31_carry__2_n_0\, + I2 => reset, + I3 => \minTimeCounter_high[0]_i_1_n_0\, + O => minTimeOK_high_i_1_n_0 + ); +minTimeOK_high_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => minTimeOK_high_i_1_n_0, + Q => minTimeOK_high, + R => '0' + ); +minTimeOK_low_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"00AB" + ) + port map ( + I0 => minTimeOK_low, + I1 => \ltOp__15_carry__2_n_0\, + I2 => reset, + I3 => \minTimeCounter_low[0]_i_1_n_0\, + O => minTimeOK_low_i_1_n_0 + ); +minTimeOK_low_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => minTimeOK_low_i_1_n_0, + Q => minTimeOK_low, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Inverter_3lvl_P0N_3lvl_0_5 is + port ( + externalCLK : in STD_LOGIC; + ready : in STD_LOGIC; + reset : in STD_LOGIC; + deadTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + minTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + er : in STD_LOGIC; + minTime_En : in STD_LOGIC; + minTimeEr : out STD_LOGIC; + TKin0 : in STD_LOGIC; + TKin1 : in STD_LOGIC; + breaking_en : in STD_LOGIC; + PWM_out_0 : out STD_LOGIC; + PWM_out_1 : out STD_LOGIC; + PWM_out_2 : out STD_LOGIC; + PWM_out_3 : out STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of Inverter_3lvl_P0N_3lvl_0_5 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of Inverter_3lvl_P0N_3lvl_0_5 : entity is "Inverter_3lvl_P0N_3lvl_0_4,P0N_3lvl,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of Inverter_3lvl_P0N_3lvl_0_5 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of Inverter_3lvl_P0N_3lvl_0_5 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of Inverter_3lvl_P0N_3lvl_0_5 : entity is "P0N_3lvl,Vivado 2019.1"; +end Inverter_3lvl_P0N_3lvl_0_5; + +architecture STRUCTURE of Inverter_3lvl_P0N_3lvl_0_5 is + attribute x_interface_info : string; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.Inverter_3lvl_P0N_3lvl_0_5_P0N_3lvl + port map ( + PWM_out_0 => PWM_out_0, + PWM_out_1 => PWM_out_1, + PWM_out_2 => PWM_out_2, + PWM_out_3 => PWM_out_3, + TKin0 => TKin0, + TKin1 => TKin1, + breaking_en => breaking_en, + deadTime(31 downto 0) => deadTime(31 downto 0), + er => er, + externalCLK => externalCLK, + minTime(31 downto 0) => minTime(31 downto 0), + minTimeEr_reg_0 => minTimeEr, + minTime_En => minTime_En, + ready => ready, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5_stub.v b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5_stub.v new file mode 100644 index 0000000..1e241b3 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5_stub.v @@ -0,0 +1,35 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Fri Jun 11 07:49:57 2021 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top Inverter_3lvl_P0N_3lvl_0_5 -prefix +// Inverter_3lvl_P0N_3lvl_0_5_ Inverter_3lvl_P0N_3lvl_0_4_stub.v +// Design : Inverter_3lvl_P0N_3lvl_0_4 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "P0N_3lvl,Vivado 2019.1" *) +module Inverter_3lvl_P0N_3lvl_0_5(externalCLK, ready, reset, deadTime, minTime, er, + minTime_En, minTimeEr, TKin0, TKin1, breaking_en, PWM_out_0, PWM_out_1, PWM_out_2, PWM_out_3) +/* synthesis syn_black_box black_box_pad_pin="externalCLK,ready,reset,deadTime[31:0],minTime[31:0],er,minTime_En,minTimeEr,TKin0,TKin1,breaking_en,PWM_out_0,PWM_out_1,PWM_out_2,PWM_out_3" */; + input externalCLK; + input ready; + input reset; + input [31:0]deadTime; + input [31:0]minTime; + input er; + input minTime_En; + output minTimeEr; + input TKin0; + input TKin1; + input breaking_en; + output PWM_out_0; + output PWM_out_1; + output PWM_out_2; + output PWM_out_3; +endmodule diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5_stub.vhdl b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5_stub.vhdl new file mode 100644 index 0000000..8161b25 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_5/Inverter_3lvl_P0N_3lvl_0_5_stub.vhdl @@ -0,0 +1,44 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Fri Jun 11 07:49:57 2021 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top Inverter_3lvl_P0N_3lvl_0_5 -prefix +-- Inverter_3lvl_P0N_3lvl_0_5_ Inverter_3lvl_P0N_3lvl_0_4_stub.vhdl +-- Design : Inverter_3lvl_P0N_3lvl_0_4 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Inverter_3lvl_P0N_3lvl_0_5 is + Port ( + externalCLK : in STD_LOGIC; + ready : in STD_LOGIC; + reset : in STD_LOGIC; + deadTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + minTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + er : in STD_LOGIC; + minTime_En : in STD_LOGIC; + minTimeEr : out STD_LOGIC; + TKin0 : in STD_LOGIC; + TKin1 : in STD_LOGIC; + breaking_en : in STD_LOGIC; + PWM_out_0 : out STD_LOGIC; + PWM_out_1 : out STD_LOGIC; + PWM_out_2 : out STD_LOGIC; + PWM_out_3 : out STD_LOGIC + ); + +end Inverter_3lvl_P0N_3lvl_0_5; + +architecture stub of Inverter_3lvl_P0N_3lvl_0_5 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "externalCLK,ready,reset,deadTime[31:0],minTime[31:0],er,minTime_En,minTimeEr,TKin0,TKin1,breaking_en,PWM_out_0,PWM_out_1,PWM_out_2,PWM_out_3"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "P0N_3lvl,Vivado 2019.1"; +begin +end; diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/Inverter_3lvl_P0N_3lvl_1_0.dcp b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0.dcp similarity index 99% rename from LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_0_synth_1/Inverter_3lvl_P0N_3lvl_1_0.dcp rename to LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0.dcp index bca1845fc68d3126366a30139dd937c26ff52f5c..aa970c3221b82bd8f9682c88afccd0a687d4706e 100644 GIT binary patch delta 28 hcmdn7n0d!y<_%G2Sf<4;4%-}eMw%7Onp}I)8UVTL42%E( delta 28 hcmdn7n0d!y<_%G2SX}H*2W^f!Bh3nCO|HFY4FIvv3-SN} diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0.xml b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0.xml index 05dcef9..9efe829 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0.xml +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0.xml @@ -133,6 +133,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:44:45 UTC 2023 + + + outputProductCRC + 9:5ec0a147 + + + @@ -407,6 +425,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + Inverter_3lvl_P0N_3lvl_1_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_1_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_1_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_1_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_1_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + P0N_3lvl_v1_0 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0_sim_netlist.v b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0_sim_netlist.v new file mode 100644 index 0000000..fe44d10 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0_sim_netlist.v @@ -0,0 +1,3131 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Fri Jun 11 07:49:57 2021 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top Inverter_3lvl_P0N_3lvl_1_0 -prefix +// Inverter_3lvl_P0N_3lvl_1_0_ Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.v +// Design : Inverter_3lvl_P0N_3lvl_0_4 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "Inverter_3lvl_P0N_3lvl_0_4,P0N_3lvl,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "P0N_3lvl,Vivado 2019.1" *) +(* NotValidForBitStream *) +module Inverter_3lvl_P0N_3lvl_1_0 + (externalCLK, + ready, + reset, + deadTime, + minTime, + er, + minTime_En, + minTimeEr, + TKin0, + TKin1, + breaking_en, + PWM_out_0, + PWM_out_1, + PWM_out_2, + PWM_out_3); + input externalCLK; + input ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + input [31:0]deadTime; + input [31:0]minTime; + input er; + input minTime_En; + output minTimeEr; + input TKin0; + input TKin1; + input breaking_en; + output PWM_out_0; + output PWM_out_1; + output PWM_out_2; + output PWM_out_3; + + wire PWM_out_0; + wire PWM_out_1; + wire PWM_out_2; + wire PWM_out_3; + wire TKin0; + wire TKin1; + wire breaking_en; + wire [31:0]deadTime; + wire er; + wire externalCLK; + wire [31:0]minTime; + wire minTimeEr; + wire minTime_En; + wire ready; + wire reset; + + Inverter_3lvl_P0N_3lvl_1_0_P0N_3lvl U0 + (.PWM_out_0(PWM_out_0), + .PWM_out_1(PWM_out_1), + .PWM_out_2(PWM_out_2), + .PWM_out_3(PWM_out_3), + .TKin0(TKin0), + .TKin1(TKin1), + .breaking_en(breaking_en), + .deadTime(deadTime), + .er(er), + .externalCLK(externalCLK), + .minTime(minTime), + .minTimeEr_reg_0(minTimeEr), + .minTime_En(minTime_En), + .ready(ready), + .reset(reset)); +endmodule + +module Inverter_3lvl_P0N_3lvl_1_0_P0N_3lvl + (minTimeEr_reg_0, + PWM_out_0, + PWM_out_1, + PWM_out_2, + PWM_out_3, + reset, + externalCLK, + TKin0, + TKin1, + breaking_en, + er, + ready, + minTime_En, + deadTime, + minTime); + output minTimeEr_reg_0; + output PWM_out_0; + output PWM_out_1; + output PWM_out_2; + output PWM_out_3; + input reset; + input externalCLK; + input TKin0; + input TKin1; + input breaking_en; + input er; + input ready; + input minTime_En; + input [31:0]deadTime; + input [31:0]minTime; + + wire \FSM_onehot_lineconfig[0]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[0]_i_2_n_0 ; + wire \FSM_onehot_lineconfig[1]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[2]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[2]_i_2_n_0 ; + wire \FSM_onehot_lineconfig[3]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[4]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[5]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[5]_i_2_n_0 ; + wire \FSM_onehot_lineconfig[5]_i_3_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_2_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_3_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_4_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_5_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_6_n_0 ; + wire \FSM_onehot_lineconfig_reg_n_0_[0] ; + wire \FSM_onehot_lineconfig_reg_n_0_[1] ; + wire \FSM_onehot_lineconfig_reg_n_0_[2] ; + wire \FSM_onehot_lineconfig_reg_n_0_[3] ; + wire \FSM_onehot_lineconfig_reg_n_0_[4] ; + wire \FSM_onehot_lineconfig_reg_n_0_[5] ; + wire \FSM_onehot_lineconfig_reg_n_0_[6] ; + wire PWM_out_0; + wire PWM_out_0_i_1_n_0; + wire PWM_out_1; + wire PWM_out_1_i_1_n_0; + wire PWM_out_2; + wire PWM_out_2_i_1_n_0; + wire PWM_out_3; + wire PWM_out_3_i_1_n_0; + wire TKin0; + wire TKin0_triggered; + wire TKin0_triggered28_out; + wire TKin0_triggered_i_1_n_0; + wire TKin1; + wire TKin1_triggered; + wire TKin1_triggered_i_1_n_0; + wire \TimeCounter[0]_i_2_n_0 ; + wire [31:0]TimeCounter_reg; + wire \TimeCounter_reg[0]_i_1_n_0 ; + wire \TimeCounter_reg[0]_i_1_n_1 ; + wire \TimeCounter_reg[0]_i_1_n_2 ; + wire \TimeCounter_reg[0]_i_1_n_3 ; + wire \TimeCounter_reg[0]_i_1_n_4 ; + wire \TimeCounter_reg[0]_i_1_n_5 ; + wire \TimeCounter_reg[0]_i_1_n_6 ; + wire \TimeCounter_reg[0]_i_1_n_7 ; + wire \TimeCounter_reg[12]_i_1_n_0 ; + wire \TimeCounter_reg[12]_i_1_n_1 ; + wire \TimeCounter_reg[12]_i_1_n_2 ; + wire \TimeCounter_reg[12]_i_1_n_3 ; + wire \TimeCounter_reg[12]_i_1_n_4 ; + wire \TimeCounter_reg[12]_i_1_n_5 ; + wire \TimeCounter_reg[12]_i_1_n_6 ; + wire \TimeCounter_reg[12]_i_1_n_7 ; + wire \TimeCounter_reg[16]_i_1_n_0 ; + wire \TimeCounter_reg[16]_i_1_n_1 ; + wire \TimeCounter_reg[16]_i_1_n_2 ; + wire \TimeCounter_reg[16]_i_1_n_3 ; + wire \TimeCounter_reg[16]_i_1_n_4 ; + wire \TimeCounter_reg[16]_i_1_n_5 ; + wire \TimeCounter_reg[16]_i_1_n_6 ; + wire \TimeCounter_reg[16]_i_1_n_7 ; + wire \TimeCounter_reg[20]_i_1_n_0 ; + wire \TimeCounter_reg[20]_i_1_n_1 ; + wire \TimeCounter_reg[20]_i_1_n_2 ; + wire \TimeCounter_reg[20]_i_1_n_3 ; + wire \TimeCounter_reg[20]_i_1_n_4 ; + wire \TimeCounter_reg[20]_i_1_n_5 ; + wire \TimeCounter_reg[20]_i_1_n_6 ; + wire \TimeCounter_reg[20]_i_1_n_7 ; + wire \TimeCounter_reg[24]_i_1_n_0 ; + wire \TimeCounter_reg[24]_i_1_n_1 ; + wire \TimeCounter_reg[24]_i_1_n_2 ; + wire \TimeCounter_reg[24]_i_1_n_3 ; + wire \TimeCounter_reg[24]_i_1_n_4 ; + wire \TimeCounter_reg[24]_i_1_n_5 ; + wire \TimeCounter_reg[24]_i_1_n_6 ; + wire \TimeCounter_reg[24]_i_1_n_7 ; + wire \TimeCounter_reg[28]_i_1_n_1 ; + wire \TimeCounter_reg[28]_i_1_n_2 ; + wire \TimeCounter_reg[28]_i_1_n_3 ; + wire \TimeCounter_reg[28]_i_1_n_4 ; + wire \TimeCounter_reg[28]_i_1_n_5 ; + wire \TimeCounter_reg[28]_i_1_n_6 ; + wire \TimeCounter_reg[28]_i_1_n_7 ; + wire \TimeCounter_reg[4]_i_1_n_0 ; + wire \TimeCounter_reg[4]_i_1_n_1 ; + wire \TimeCounter_reg[4]_i_1_n_2 ; + wire \TimeCounter_reg[4]_i_1_n_3 ; + wire \TimeCounter_reg[4]_i_1_n_4 ; + wire \TimeCounter_reg[4]_i_1_n_5 ; + wire \TimeCounter_reg[4]_i_1_n_6 ; + wire \TimeCounter_reg[4]_i_1_n_7 ; + wire \TimeCounter_reg[8]_i_1_n_0 ; + wire \TimeCounter_reg[8]_i_1_n_1 ; + wire \TimeCounter_reg[8]_i_1_n_2 ; + wire \TimeCounter_reg[8]_i_1_n_3 ; + wire \TimeCounter_reg[8]_i_1_n_4 ; + wire \TimeCounter_reg[8]_i_1_n_5 ; + wire \TimeCounter_reg[8]_i_1_n_6 ; + wire \TimeCounter_reg[8]_i_1_n_7 ; + wire breaking_en; + wire [31:0]deadTime; + wire deadTimeCounterReset_i_1_n_0; + wire deadTimeCounterReset_i_2_n_0; + wire deadTimeCounterReset_i_3_n_0; + wire deadTimeCounterReset_i_4_n_0; + wire deadTimeCounterReset_i_5_n_0; + wire deadTimeCounterReset_i_6_n_0; + wire deadTimeCounterReset_i_7_n_0; + wire deadTimeCounterReset_reg_n_0; + wire deadTimeOK; + wire deadTimeOK_i_1_n_0; + wire er; + wire externalCLK; + wire key1_i_1_n_0; + wire key1_i_2_n_0; + wire key1_prev; + wire key1_reg_n_0; + wire key2_i_2_n_0; + wire key2_prev; + wire key2_reg_n_0; + wire key3; + wire key3_i_1_n_0; + wire key3_prev; + wire key3_reg_n_0; + wire key4_i_1_n_0; + wire key4_prev; + wire key4_reg_n_0; + wire ltOp__15_carry__0_i_1_n_0; + wire ltOp__15_carry__0_i_2_n_0; + wire ltOp__15_carry__0_i_3_n_0; + wire ltOp__15_carry__0_i_4_n_0; + wire ltOp__15_carry__0_i_5_n_0; + wire ltOp__15_carry__0_i_6_n_0; + wire ltOp__15_carry__0_i_7_n_0; + wire ltOp__15_carry__0_i_8_n_0; + wire ltOp__15_carry__0_n_0; + wire ltOp__15_carry__0_n_1; + wire ltOp__15_carry__0_n_2; + wire ltOp__15_carry__0_n_3; + wire ltOp__15_carry__1_i_1_n_0; + wire ltOp__15_carry__1_i_2_n_0; + wire ltOp__15_carry__1_i_3_n_0; + wire ltOp__15_carry__1_i_4_n_0; + wire ltOp__15_carry__1_i_5_n_0; + wire ltOp__15_carry__1_i_6_n_0; + wire ltOp__15_carry__1_i_7_n_0; + wire ltOp__15_carry__1_i_8_n_0; + wire ltOp__15_carry__1_n_0; + wire ltOp__15_carry__1_n_1; + wire ltOp__15_carry__1_n_2; + wire ltOp__15_carry__1_n_3; + wire ltOp__15_carry__2_i_1_n_0; + wire ltOp__15_carry__2_i_2_n_0; + wire ltOp__15_carry__2_i_3_n_0; + wire ltOp__15_carry__2_i_4_n_0; + wire ltOp__15_carry__2_i_5_n_0; + wire ltOp__15_carry__2_i_6_n_0; + wire ltOp__15_carry__2_i_7_n_0; + wire ltOp__15_carry__2_i_8_n_0; + wire ltOp__15_carry__2_n_0; + wire ltOp__15_carry__2_n_1; + wire ltOp__15_carry__2_n_2; + wire ltOp__15_carry__2_n_3; + wire ltOp__15_carry_i_1_n_0; + wire ltOp__15_carry_i_2_n_0; + wire ltOp__15_carry_i_3_n_0; + wire ltOp__15_carry_i_4_n_0; + wire ltOp__15_carry_i_5_n_0; + wire ltOp__15_carry_i_6_n_0; + wire ltOp__15_carry_i_7_n_0; + wire ltOp__15_carry_i_8_n_0; + wire ltOp__15_carry_n_0; + wire ltOp__15_carry_n_1; + wire ltOp__15_carry_n_2; + wire ltOp__15_carry_n_3; + wire ltOp__31_carry__0_n_0; + wire ltOp__31_carry__0_n_1; + wire ltOp__31_carry__0_n_2; + wire ltOp__31_carry__0_n_3; + wire ltOp__31_carry__1_n_0; + wire ltOp__31_carry__1_n_1; + wire ltOp__31_carry__1_n_2; + wire ltOp__31_carry__1_n_3; + wire ltOp__31_carry__2_n_0; + wire ltOp__31_carry__2_n_1; + wire ltOp__31_carry__2_n_2; + wire ltOp__31_carry__2_n_3; + wire ltOp__31_carry_i_1__0_n_0; + wire ltOp__31_carry_i_1__1_n_0; + wire ltOp__31_carry_i_1__2_n_0; + wire ltOp__31_carry_i_1_n_0; + wire ltOp__31_carry_i_2__0_n_0; + wire ltOp__31_carry_i_2__1_n_0; + wire ltOp__31_carry_i_2__2_n_0; + wire ltOp__31_carry_i_2_n_0; + wire ltOp__31_carry_i_3__0_n_0; + wire ltOp__31_carry_i_3__1_n_0; + wire ltOp__31_carry_i_3__2_n_0; + wire ltOp__31_carry_i_3_n_0; + wire ltOp__31_carry_i_4__0_n_0; + wire ltOp__31_carry_i_4__1_n_0; + wire ltOp__31_carry_i_4__2_n_0; + wire ltOp__31_carry_i_4_n_0; + wire ltOp__31_carry_i_5__0_n_0; + wire ltOp__31_carry_i_5__1_n_0; + wire ltOp__31_carry_i_5__2_n_0; + wire ltOp__31_carry_i_5_n_0; + wire ltOp__31_carry_i_6__0_n_0; + wire ltOp__31_carry_i_6__1_n_0; + wire ltOp__31_carry_i_6__2_n_0; + wire ltOp__31_carry_i_6_n_0; + wire ltOp__31_carry_i_7__0_n_0; + wire ltOp__31_carry_i_7__1_n_0; + wire ltOp__31_carry_i_7__2_n_0; + wire ltOp__31_carry_i_7_n_0; + wire ltOp__31_carry_i_8__0_n_0; + wire ltOp__31_carry_i_8__1_n_0; + wire ltOp__31_carry_i_8__2_n_0; + wire ltOp__31_carry_i_8_n_0; + wire ltOp__31_carry_n_0; + wire ltOp__31_carry_n_1; + wire ltOp__31_carry_n_2; + wire ltOp__31_carry_n_3; + wire ltOp_carry__0_i_1_n_0; + wire ltOp_carry__0_i_2_n_0; + wire ltOp_carry__0_i_3_n_0; + wire ltOp_carry__0_i_4_n_0; + wire ltOp_carry__0_i_5_n_0; + wire ltOp_carry__0_i_6_n_0; + wire ltOp_carry__0_i_7_n_0; + wire ltOp_carry__0_i_8_n_0; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_i_1_n_0; + wire ltOp_carry__1_i_2_n_0; + wire ltOp_carry__1_i_3_n_0; + wire ltOp_carry__1_i_4_n_0; + wire ltOp_carry__1_i_5_n_0; + wire ltOp_carry__1_i_6_n_0; + wire ltOp_carry__1_i_7_n_0; + wire ltOp_carry__1_i_8_n_0; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_i_1_n_0; + wire ltOp_carry__2_i_2_n_0; + wire ltOp_carry__2_i_3_n_0; + wire ltOp_carry__2_i_4_n_0; + wire ltOp_carry__2_i_5_n_0; + wire ltOp_carry__2_i_6_n_0; + wire ltOp_carry__2_i_7_n_0; + wire ltOp_carry__2_i_8_n_0; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [31:0]minTime; + wire minTimeCounter_high; + wire \minTimeCounter_high[0]_i_1_n_0 ; + wire \minTimeCounter_high[0]_i_4_n_0 ; + wire [31:0]minTimeCounter_high_reg; + wire \minTimeCounter_high_reg[0]_i_3_n_0 ; + wire \minTimeCounter_high_reg[0]_i_3_n_1 ; + wire \minTimeCounter_high_reg[0]_i_3_n_2 ; + wire \minTimeCounter_high_reg[0]_i_3_n_3 ; + wire \minTimeCounter_high_reg[0]_i_3_n_4 ; + wire \minTimeCounter_high_reg[0]_i_3_n_5 ; + wire \minTimeCounter_high_reg[0]_i_3_n_6 ; + wire \minTimeCounter_high_reg[0]_i_3_n_7 ; + wire \minTimeCounter_high_reg[12]_i_1_n_0 ; + wire \minTimeCounter_high_reg[12]_i_1_n_1 ; + wire \minTimeCounter_high_reg[12]_i_1_n_2 ; + wire \minTimeCounter_high_reg[12]_i_1_n_3 ; + wire \minTimeCounter_high_reg[12]_i_1_n_4 ; + wire \minTimeCounter_high_reg[12]_i_1_n_5 ; + wire \minTimeCounter_high_reg[12]_i_1_n_6 ; + wire \minTimeCounter_high_reg[12]_i_1_n_7 ; + wire \minTimeCounter_high_reg[16]_i_1_n_0 ; + wire \minTimeCounter_high_reg[16]_i_1_n_1 ; + wire \minTimeCounter_high_reg[16]_i_1_n_2 ; + wire \minTimeCounter_high_reg[16]_i_1_n_3 ; + wire \minTimeCounter_high_reg[16]_i_1_n_4 ; + wire \minTimeCounter_high_reg[16]_i_1_n_5 ; + wire \minTimeCounter_high_reg[16]_i_1_n_6 ; + wire \minTimeCounter_high_reg[16]_i_1_n_7 ; + wire \minTimeCounter_high_reg[20]_i_1_n_0 ; + wire \minTimeCounter_high_reg[20]_i_1_n_1 ; + wire \minTimeCounter_high_reg[20]_i_1_n_2 ; + wire \minTimeCounter_high_reg[20]_i_1_n_3 ; + wire \minTimeCounter_high_reg[20]_i_1_n_4 ; + wire \minTimeCounter_high_reg[20]_i_1_n_5 ; + wire \minTimeCounter_high_reg[20]_i_1_n_6 ; + wire \minTimeCounter_high_reg[20]_i_1_n_7 ; + wire \minTimeCounter_high_reg[24]_i_1_n_0 ; + wire \minTimeCounter_high_reg[24]_i_1_n_1 ; + wire \minTimeCounter_high_reg[24]_i_1_n_2 ; + wire \minTimeCounter_high_reg[24]_i_1_n_3 ; + wire \minTimeCounter_high_reg[24]_i_1_n_4 ; + wire \minTimeCounter_high_reg[24]_i_1_n_5 ; + wire \minTimeCounter_high_reg[24]_i_1_n_6 ; + wire \minTimeCounter_high_reg[24]_i_1_n_7 ; + wire \minTimeCounter_high_reg[28]_i_1_n_1 ; + wire \minTimeCounter_high_reg[28]_i_1_n_2 ; + wire \minTimeCounter_high_reg[28]_i_1_n_3 ; + wire \minTimeCounter_high_reg[28]_i_1_n_4 ; + wire \minTimeCounter_high_reg[28]_i_1_n_5 ; + wire \minTimeCounter_high_reg[28]_i_1_n_6 ; + wire \minTimeCounter_high_reg[28]_i_1_n_7 ; + wire \minTimeCounter_high_reg[4]_i_1_n_0 ; + wire \minTimeCounter_high_reg[4]_i_1_n_1 ; + wire \minTimeCounter_high_reg[4]_i_1_n_2 ; + wire \minTimeCounter_high_reg[4]_i_1_n_3 ; + wire \minTimeCounter_high_reg[4]_i_1_n_4 ; + wire \minTimeCounter_high_reg[4]_i_1_n_5 ; + wire \minTimeCounter_high_reg[4]_i_1_n_6 ; + wire \minTimeCounter_high_reg[4]_i_1_n_7 ; + wire \minTimeCounter_high_reg[8]_i_1_n_0 ; + wire \minTimeCounter_high_reg[8]_i_1_n_1 ; + wire \minTimeCounter_high_reg[8]_i_1_n_2 ; + wire \minTimeCounter_high_reg[8]_i_1_n_3 ; + wire \minTimeCounter_high_reg[8]_i_1_n_4 ; + wire \minTimeCounter_high_reg[8]_i_1_n_5 ; + wire \minTimeCounter_high_reg[8]_i_1_n_6 ; + wire \minTimeCounter_high_reg[8]_i_1_n_7 ; + wire minTimeCounter_low; + wire \minTimeCounter_low[0]_i_1_n_0 ; + wire \minTimeCounter_low[0]_i_4_n_0 ; + wire \minTimeCounter_low[0]_i_5_n_0 ; + wire [31:0]minTimeCounter_low_reg; + wire \minTimeCounter_low_reg[0]_i_3_n_0 ; + wire \minTimeCounter_low_reg[0]_i_3_n_1 ; + wire \minTimeCounter_low_reg[0]_i_3_n_2 ; + wire \minTimeCounter_low_reg[0]_i_3_n_3 ; + wire \minTimeCounter_low_reg[0]_i_3_n_4 ; + wire \minTimeCounter_low_reg[0]_i_3_n_5 ; + wire \minTimeCounter_low_reg[0]_i_3_n_6 ; + wire \minTimeCounter_low_reg[0]_i_3_n_7 ; + wire \minTimeCounter_low_reg[12]_i_1_n_0 ; + wire \minTimeCounter_low_reg[12]_i_1_n_1 ; + wire \minTimeCounter_low_reg[12]_i_1_n_2 ; + wire \minTimeCounter_low_reg[12]_i_1_n_3 ; + wire \minTimeCounter_low_reg[12]_i_1_n_4 ; + wire \minTimeCounter_low_reg[12]_i_1_n_5 ; + wire \minTimeCounter_low_reg[12]_i_1_n_6 ; + wire \minTimeCounter_low_reg[12]_i_1_n_7 ; + wire \minTimeCounter_low_reg[16]_i_1_n_0 ; + wire \minTimeCounter_low_reg[16]_i_1_n_1 ; + wire \minTimeCounter_low_reg[16]_i_1_n_2 ; + wire \minTimeCounter_low_reg[16]_i_1_n_3 ; + wire \minTimeCounter_low_reg[16]_i_1_n_4 ; + wire \minTimeCounter_low_reg[16]_i_1_n_5 ; + wire \minTimeCounter_low_reg[16]_i_1_n_6 ; + wire \minTimeCounter_low_reg[16]_i_1_n_7 ; + wire \minTimeCounter_low_reg[20]_i_1_n_0 ; + wire \minTimeCounter_low_reg[20]_i_1_n_1 ; + wire \minTimeCounter_low_reg[20]_i_1_n_2 ; + wire \minTimeCounter_low_reg[20]_i_1_n_3 ; + wire \minTimeCounter_low_reg[20]_i_1_n_4 ; + wire \minTimeCounter_low_reg[20]_i_1_n_5 ; + wire \minTimeCounter_low_reg[20]_i_1_n_6 ; + wire \minTimeCounter_low_reg[20]_i_1_n_7 ; + wire \minTimeCounter_low_reg[24]_i_1_n_0 ; + wire \minTimeCounter_low_reg[24]_i_1_n_1 ; + wire \minTimeCounter_low_reg[24]_i_1_n_2 ; + wire \minTimeCounter_low_reg[24]_i_1_n_3 ; + wire \minTimeCounter_low_reg[24]_i_1_n_4 ; + wire \minTimeCounter_low_reg[24]_i_1_n_5 ; + wire \minTimeCounter_low_reg[24]_i_1_n_6 ; + wire \minTimeCounter_low_reg[24]_i_1_n_7 ; + wire \minTimeCounter_low_reg[28]_i_1_n_1 ; + wire \minTimeCounter_low_reg[28]_i_1_n_2 ; + wire \minTimeCounter_low_reg[28]_i_1_n_3 ; + wire \minTimeCounter_low_reg[28]_i_1_n_4 ; + wire \minTimeCounter_low_reg[28]_i_1_n_5 ; + wire \minTimeCounter_low_reg[28]_i_1_n_6 ; + wire \minTimeCounter_low_reg[28]_i_1_n_7 ; + wire \minTimeCounter_low_reg[4]_i_1_n_0 ; + wire \minTimeCounter_low_reg[4]_i_1_n_1 ; + wire \minTimeCounter_low_reg[4]_i_1_n_2 ; + wire \minTimeCounter_low_reg[4]_i_1_n_3 ; + wire \minTimeCounter_low_reg[4]_i_1_n_4 ; + wire \minTimeCounter_low_reg[4]_i_1_n_5 ; + wire \minTimeCounter_low_reg[4]_i_1_n_6 ; + wire \minTimeCounter_low_reg[4]_i_1_n_7 ; + wire \minTimeCounter_low_reg[8]_i_1_n_0 ; + wire \minTimeCounter_low_reg[8]_i_1_n_1 ; + wire \minTimeCounter_low_reg[8]_i_1_n_2 ; + wire \minTimeCounter_low_reg[8]_i_1_n_3 ; + wire \minTimeCounter_low_reg[8]_i_1_n_4 ; + wire \minTimeCounter_low_reg[8]_i_1_n_5 ; + wire \minTimeCounter_low_reg[8]_i_1_n_6 ; + wire \minTimeCounter_low_reg[8]_i_1_n_7 ; + wire minTimeEr_i_1_n_0; + wire minTimeEr_i_2_n_0; + wire minTimeEr_i_3_n_0; + wire minTimeEr_i_4_n_0; + wire minTimeEr_i_5_n_0; + wire minTimeEr_i_6_n_0; + wire minTimeEr_i_7_n_0; + wire minTimeEr_i_8_n_0; + wire minTimeEr_i_9_n_0; + wire minTimeEr_reg_0; + wire minTimeOK_high; + wire minTimeOK_high_i_1_n_0; + wire minTimeOK_low; + wire minTimeOK_low_i_1_n_0; + wire minTime_En; + wire p_0_in; + wire ready; + wire reset; + wire sel; + wire [3:3]\NLW_TimeCounter_reg[28]_i_1_CO_UNCONNECTED ; + wire [3:0]NLW_ltOp__15_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp__15_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp__15_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp__15_carry__2_O_UNCONNECTED; + wire [3:0]NLW_ltOp__31_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp__31_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp__31_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp__31_carry__2_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + wire [3:3]\NLW_minTimeCounter_high_reg[28]_i_1_CO_UNCONNECTED ; + wire [3:3]\NLW_minTimeCounter_low_reg[28]_i_1_CO_UNCONNECTED ; + + LUT6 #( + .INIT(64'hFFFFFFFE00000000)) + \FSM_onehot_lineconfig[0]_i_1 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I4(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I5(\FSM_onehot_lineconfig[0]_i_2_n_0 ), + .O(\FSM_onehot_lineconfig[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_lineconfig[0]_i_2 + (.I0(TKin1), + .I1(TKin0), + .O(\FSM_onehot_lineconfig[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'h1000FFFF00000000)) + \FSM_onehot_lineconfig[1]_i_1 + (.I0(TKin1), + .I1(TKin1_triggered), + .I2(TKin0_triggered), + .I3(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I4(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I5(TKin0), + .O(\FSM_onehot_lineconfig[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h00EFEF0F)) + \FSM_onehot_lineconfig[2]_i_1 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I2(\FSM_onehot_lineconfig[2]_i_2_n_0 ), + .I3(TKin0), + .I4(TKin1), + .O(\FSM_onehot_lineconfig[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'h900990099009FFFF)) + \FSM_onehot_lineconfig[2]_i_2 + (.I0(TKin1), + .I1(TKin1_triggered), + .I2(TKin0), + .I3(TKin0_triggered), + .I4(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I5(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .O(\FSM_onehot_lineconfig[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0000000055D50000)) + \FSM_onehot_lineconfig[3]_i_1 + (.I0(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I2(TKin1_triggered), + .I3(TKin0_triggered), + .I4(TKin1), + .I5(TKin0), + .O(\FSM_onehot_lineconfig[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT4 #( + .INIT(16'h2230)) + \FSM_onehot_lineconfig[4]_i_1 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I1(TKin0), + .I2(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I3(TKin1), + .O(\FSM_onehot_lineconfig[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0CFF0C0D00050005)) + \FSM_onehot_lineconfig[5]_i_1 + (.I0(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I2(TKin1), + .I3(TKin0), + .I4(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I5(\FSM_onehot_lineconfig[5]_i_3_n_0 ), + .O(\FSM_onehot_lineconfig[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h1)) + \FSM_onehot_lineconfig[5]_i_2 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .O(\FSM_onehot_lineconfig[5]_i_2_n_0 )); + LUT4 #( + .INIT(16'h9009)) + \FSM_onehot_lineconfig[5]_i_3 + (.I0(TKin0_triggered), + .I1(TKin0), + .I2(TKin1_triggered), + .I3(TKin1), + .O(\FSM_onehot_lineconfig[5]_i_3_n_0 )); + LUT3 #( + .INIT(8'h0E)) + \FSM_onehot_lineconfig[6]_i_1 + (.I0(\FSM_onehot_lineconfig[6]_i_3_n_0 ), + .I1(\FSM_onehot_lineconfig[6]_i_4_n_0 ), + .I2(breaking_en), + .O(\FSM_onehot_lineconfig[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT4 #( + .INIT(16'h5504)) + \FSM_onehot_lineconfig[6]_i_2 + (.I0(TKin1), + .I1(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I2(TKin0), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .O(\FSM_onehot_lineconfig[6]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'hFFFEECAE)) + \FSM_onehot_lineconfig[6]_i_3 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I2(TKin1), + .I3(TKin0), + .I4(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .O(\FSM_onehot_lineconfig[6]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAABAAAAAFFFFAAAA)) + \FSM_onehot_lineconfig[6]_i_4 + (.I0(\FSM_onehot_lineconfig[6]_i_5_n_0 ), + .I1(er), + .I2(ready), + .I3(\FSM_onehot_lineconfig[6]_i_6_n_0 ), + .I4(deadTimeOK), + .I5(\FSM_onehot_lineconfig[2]_i_2_n_0 ), + .O(\FSM_onehot_lineconfig[6]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFC88A0A8)) + \FSM_onehot_lineconfig[6]_i_5 + (.I0(deadTimeOK), + .I1(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I3(TKin1), + .I4(TKin0), + .O(\FSM_onehot_lineconfig[6]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'hFF232323)) + \FSM_onehot_lineconfig[6]_i_6 + (.I0(deadTimeCounterReset_reg_n_0), + .I1(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I3(TKin1), + .I4(TKin0), + .O(\FSM_onehot_lineconfig[6]_i_6_n_0 )); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDSE #( + .INIT(1'b1)) + \FSM_onehot_lineconfig_reg[0] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[0]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .S(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[1] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[1]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[2] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[2]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[3] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[3]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[4] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[4]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[5] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[5]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[6] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[6]_i_2_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT4 #( + .INIT(16'hFFEF)) + PWM_out_0_i_1 + (.I0(key1_reg_n_0), + .I1(er), + .I2(ready), + .I3(minTimeEr_reg_0), + .O(PWM_out_0_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + PWM_out_0_reg + (.C(externalCLK), + .CE(1'b1), + .D(PWM_out_0_i_1_n_0), + .Q(PWM_out_0), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT4 #( + .INIT(16'hFFEF)) + PWM_out_1_i_1 + (.I0(key2_reg_n_0), + .I1(er), + .I2(ready), + .I3(minTimeEr_reg_0), + .O(PWM_out_1_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + PWM_out_1_reg + (.C(externalCLK), + .CE(1'b1), + .D(PWM_out_1_i_1_n_0), + .Q(PWM_out_1), + .R(1'b0)); + LUT5 #( + .INIT(32'hFFFFFFEF)) + PWM_out_2_i_1 + (.I0(key3_reg_n_0), + .I1(minTimeEr_reg_0), + .I2(ready), + .I3(er), + .I4(breaking_en), + .O(PWM_out_2_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + PWM_out_2_reg + (.C(externalCLK), + .CE(1'b1), + .D(PWM_out_2_i_1_n_0), + .Q(PWM_out_2), + .R(1'b0)); + LUT5 #( + .INIT(32'hFFFFFFEF)) + PWM_out_3_i_1 + (.I0(key4_reg_n_0), + .I1(minTimeEr_reg_0), + .I2(ready), + .I3(er), + .I4(breaking_en), + .O(PWM_out_3_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + PWM_out_3_reg + (.C(externalCLK), + .CE(1'b1), + .D(PWM_out_3_i_1_n_0), + .Q(PWM_out_3), + .R(1'b0)); + LUT6 #( + .INIT(64'hAA08FFFFAA080000)) + TKin0_triggered_i_1 + (.I0(TKin0), + .I1(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I2(TKin1), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I4(TKin0_triggered28_out), + .I5(TKin0_triggered), + .O(TKin0_triggered_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + TKin0_triggered_reg + (.C(externalCLK), + .CE(1'b1), + .D(TKin0_triggered_i_1_n_0), + .Q(TKin0_triggered), + .R(1'b0)); + LUT6 #( + .INIT(64'hAA08FFFFAA080000)) + TKin1_triggered_i_1 + (.I0(TKin1), + .I1(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I2(TKin0), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I4(TKin0_triggered28_out), + .I5(TKin1_triggered), + .O(TKin1_triggered_i_1_n_0)); + LUT6 #( + .INIT(64'h22AA22A820AA2020)) + TKin1_triggered_i_2 + (.I0(minTimeEr_i_9_n_0), + .I1(TKin1), + .I2(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I3(TKin0), + .I4(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I5(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .O(TKin0_triggered28_out)); + FDRE #( + .INIT(1'b1)) + TKin1_triggered_reg + (.C(externalCLK), + .CE(1'b1), + .D(TKin1_triggered_i_1_n_0), + .Q(TKin1_triggered), + .R(1'b0)); + LUT1 #( + .INIT(2'h1)) + \TimeCounter[0]_i_2 + (.I0(TimeCounter_reg[0]), + .O(\TimeCounter[0]_i_2_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[0] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[0]_i_1_n_7 ), + .Q(TimeCounter_reg[0]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[0]_i_1 + (.CI(1'b0), + .CO({\TimeCounter_reg[0]_i_1_n_0 ,\TimeCounter_reg[0]_i_1_n_1 ,\TimeCounter_reg[0]_i_1_n_2 ,\TimeCounter_reg[0]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\TimeCounter_reg[0]_i_1_n_4 ,\TimeCounter_reg[0]_i_1_n_5 ,\TimeCounter_reg[0]_i_1_n_6 ,\TimeCounter_reg[0]_i_1_n_7 }), + .S({TimeCounter_reg[3:1],\TimeCounter[0]_i_2_n_0 })); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[10] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[8]_i_1_n_5 ), + .Q(TimeCounter_reg[10]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[11] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[8]_i_1_n_4 ), + .Q(TimeCounter_reg[11]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[12] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[12]_i_1_n_7 ), + .Q(TimeCounter_reg[12]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[12]_i_1 + (.CI(\TimeCounter_reg[8]_i_1_n_0 ), + .CO({\TimeCounter_reg[12]_i_1_n_0 ,\TimeCounter_reg[12]_i_1_n_1 ,\TimeCounter_reg[12]_i_1_n_2 ,\TimeCounter_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[12]_i_1_n_4 ,\TimeCounter_reg[12]_i_1_n_5 ,\TimeCounter_reg[12]_i_1_n_6 ,\TimeCounter_reg[12]_i_1_n_7 }), + .S(TimeCounter_reg[15:12])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[13] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[12]_i_1_n_6 ), + .Q(TimeCounter_reg[13]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[14] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[12]_i_1_n_5 ), + .Q(TimeCounter_reg[14]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[15] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[12]_i_1_n_4 ), + .Q(TimeCounter_reg[15]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[16] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[16]_i_1_n_7 ), + .Q(TimeCounter_reg[16]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[16]_i_1 + (.CI(\TimeCounter_reg[12]_i_1_n_0 ), + .CO({\TimeCounter_reg[16]_i_1_n_0 ,\TimeCounter_reg[16]_i_1_n_1 ,\TimeCounter_reg[16]_i_1_n_2 ,\TimeCounter_reg[16]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[16]_i_1_n_4 ,\TimeCounter_reg[16]_i_1_n_5 ,\TimeCounter_reg[16]_i_1_n_6 ,\TimeCounter_reg[16]_i_1_n_7 }), + .S(TimeCounter_reg[19:16])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[17] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[16]_i_1_n_6 ), + .Q(TimeCounter_reg[17]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[18] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[16]_i_1_n_5 ), + .Q(TimeCounter_reg[18]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[19] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[16]_i_1_n_4 ), + .Q(TimeCounter_reg[19]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[1] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[0]_i_1_n_6 ), + .Q(TimeCounter_reg[1]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[20] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[20]_i_1_n_7 ), + .Q(TimeCounter_reg[20]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[20]_i_1 + (.CI(\TimeCounter_reg[16]_i_1_n_0 ), + .CO({\TimeCounter_reg[20]_i_1_n_0 ,\TimeCounter_reg[20]_i_1_n_1 ,\TimeCounter_reg[20]_i_1_n_2 ,\TimeCounter_reg[20]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[20]_i_1_n_4 ,\TimeCounter_reg[20]_i_1_n_5 ,\TimeCounter_reg[20]_i_1_n_6 ,\TimeCounter_reg[20]_i_1_n_7 }), + .S(TimeCounter_reg[23:20])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[21] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[20]_i_1_n_6 ), + .Q(TimeCounter_reg[21]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[22] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[20]_i_1_n_5 ), + .Q(TimeCounter_reg[22]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[23] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[20]_i_1_n_4 ), + .Q(TimeCounter_reg[23]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[24] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[24]_i_1_n_7 ), + .Q(TimeCounter_reg[24]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[24]_i_1 + (.CI(\TimeCounter_reg[20]_i_1_n_0 ), + .CO({\TimeCounter_reg[24]_i_1_n_0 ,\TimeCounter_reg[24]_i_1_n_1 ,\TimeCounter_reg[24]_i_1_n_2 ,\TimeCounter_reg[24]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[24]_i_1_n_4 ,\TimeCounter_reg[24]_i_1_n_5 ,\TimeCounter_reg[24]_i_1_n_6 ,\TimeCounter_reg[24]_i_1_n_7 }), + .S(TimeCounter_reg[27:24])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[25] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[24]_i_1_n_6 ), + .Q(TimeCounter_reg[25]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[26] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[24]_i_1_n_5 ), + .Q(TimeCounter_reg[26]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[27] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[24]_i_1_n_4 ), + .Q(TimeCounter_reg[27]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[28] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[28]_i_1_n_7 ), + .Q(TimeCounter_reg[28]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[28]_i_1 + (.CI(\TimeCounter_reg[24]_i_1_n_0 ), + .CO({\NLW_TimeCounter_reg[28]_i_1_CO_UNCONNECTED [3],\TimeCounter_reg[28]_i_1_n_1 ,\TimeCounter_reg[28]_i_1_n_2 ,\TimeCounter_reg[28]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[28]_i_1_n_4 ,\TimeCounter_reg[28]_i_1_n_5 ,\TimeCounter_reg[28]_i_1_n_6 ,\TimeCounter_reg[28]_i_1_n_7 }), + .S(TimeCounter_reg[31:28])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[29] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[28]_i_1_n_6 ), + .Q(TimeCounter_reg[29]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[2] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[0]_i_1_n_5 ), + .Q(TimeCounter_reg[2]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[30] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[28]_i_1_n_5 ), + .Q(TimeCounter_reg[30]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[31] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[28]_i_1_n_4 ), + .Q(TimeCounter_reg[31]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[3] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[0]_i_1_n_4 ), + .Q(TimeCounter_reg[3]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[4] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[4]_i_1_n_7 ), + .Q(TimeCounter_reg[4]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[4]_i_1 + (.CI(\TimeCounter_reg[0]_i_1_n_0 ), + .CO({\TimeCounter_reg[4]_i_1_n_0 ,\TimeCounter_reg[4]_i_1_n_1 ,\TimeCounter_reg[4]_i_1_n_2 ,\TimeCounter_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[4]_i_1_n_4 ,\TimeCounter_reg[4]_i_1_n_5 ,\TimeCounter_reg[4]_i_1_n_6 ,\TimeCounter_reg[4]_i_1_n_7 }), + .S(TimeCounter_reg[7:4])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[5] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[4]_i_1_n_6 ), + .Q(TimeCounter_reg[5]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[6] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[4]_i_1_n_5 ), + .Q(TimeCounter_reg[6]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[7] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[4]_i_1_n_4 ), + .Q(TimeCounter_reg[7]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[8] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[8]_i_1_n_7 ), + .Q(TimeCounter_reg[8]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[8]_i_1 + (.CI(\TimeCounter_reg[4]_i_1_n_0 ), + .CO({\TimeCounter_reg[8]_i_1_n_0 ,\TimeCounter_reg[8]_i_1_n_1 ,\TimeCounter_reg[8]_i_1_n_2 ,\TimeCounter_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[8]_i_1_n_4 ,\TimeCounter_reg[8]_i_1_n_5 ,\TimeCounter_reg[8]_i_1_n_6 ,\TimeCounter_reg[8]_i_1_n_7 }), + .S(TimeCounter_reg[11:8])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[9] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[8]_i_1_n_6 ), + .Q(TimeCounter_reg[9]), + .R(deadTimeCounterReset_reg_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFE0000000E)) + deadTimeCounterReset_i_1 + (.I0(deadTimeCounterReset_i_2_n_0), + .I1(\FSM_onehot_lineconfig[6]_i_4_n_0 ), + .I2(reset), + .I3(breaking_en), + .I4(deadTimeCounterReset_i_3_n_0), + .I5(deadTimeCounterReset_reg_n_0), + .O(deadTimeCounterReset_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'hFE)) + deadTimeCounterReset_i_2 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .O(deadTimeCounterReset_i_2_n_0)); + LUT6 #( + .INIT(64'h0000000022220020)) + deadTimeCounterReset_i_3 + (.I0(deadTimeCounterReset_i_4_n_0), + .I1(deadTimeCounterReset_i_2_n_0), + .I2(deadTimeCounterReset_i_5_n_0), + .I3(deadTimeCounterReset_i_6_n_0), + .I4(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I5(deadTimeCounterReset_i_7_n_0), + .O(deadTimeCounterReset_i_3_n_0)); + LUT6 #( + .INIT(64'h555D555555555555)) + deadTimeCounterReset_i_4 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I1(deadTimeOK), + .I2(TKin1), + .I3(TKin1_triggered), + .I4(TKin0), + .I5(TKin0_triggered), + .O(deadTimeCounterReset_i_4_n_0)); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT3 #( + .INIT(8'h08)) + deadTimeCounterReset_i_5 + (.I0(deadTimeOK), + .I1(ready), + .I2(er), + .O(deadTimeCounterReset_i_5_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT4 #( + .INIT(16'hF777)) + deadTimeCounterReset_i_6 + (.I0(TKin0), + .I1(TKin1), + .I2(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I3(deadTimeCounterReset_reg_n_0), + .O(deadTimeCounterReset_i_6_n_0)); + LUT6 #( + .INIT(64'hAAAAA2AAAAAAAAAA)) + deadTimeCounterReset_i_7 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I1(TKin1), + .I2(TKin0), + .I3(deadTimeOK), + .I4(TKin0_triggered), + .I5(TKin1_triggered), + .O(deadTimeCounterReset_i_7_n_0)); + FDRE #( + .INIT(1'b0)) + deadTimeCounterReset_reg + (.C(externalCLK), + .CE(1'b1), + .D(deadTimeCounterReset_i_1_n_0), + .Q(deadTimeCounterReset_reg_n_0), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT3 #( + .INIT(8'h0D)) + deadTimeOK_i_1 + (.I0(sel), + .I1(deadTimeOK), + .I2(deadTimeCounterReset_reg_n_0), + .O(deadTimeOK_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + deadTimeOK_reg + (.C(externalCLK), + .CE(1'b1), + .D(deadTimeOK_i_1_n_0), + .Q(deadTimeOK), + .R(1'b0)); + LUT6 #( + .INIT(64'hDDDDDDD0DDDDDDDD)) + key1_i_1 + (.I0(breaking_en), + .I1(TKin0), + .I2(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I4(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I5(key1_i_2_n_0), + .O(key1_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT4 #( + .INIT(16'h0001)) + key1_i_2 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I3(breaking_en), + .O(key1_i_2_n_0)); + FDRE #( + .INIT(1'b1)) + key1_prev_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key1_reg_n_0), + .Q(key1_prev), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + key1_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key1_i_1_n_0), + .Q(key1_reg_n_0), + .R(1'b0)); + LUT1 #( + .INIT(2'h1)) + key2_i_1 + (.I0(reset), + .O(p_0_in)); + LUT6 #( + .INIT(64'hAAAAAAAAFFFFFFFC)) + key2_i_2 + (.I0(TKin1), + .I1(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I4(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I5(breaking_en), + .O(key2_i_2_n_0)); + FDRE #( + .INIT(1'b1)) + key2_prev_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key2_reg_n_0), + .Q(key2_prev), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + key2_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key2_i_2_n_0), + .Q(key2_reg_n_0), + .R(1'b0)); + LUT6 #( + .INIT(64'hAAAAFFFFAAAAFCFF)) + key3_i_1 + (.I0(key3_reg_n_0), + .I1(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I3(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I4(reset), + .I5(breaking_en), + .O(key3_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + key3_prev_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key3_reg_n_0), + .Q(key3_prev), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + key3_reg + (.C(externalCLK), + .CE(1'b1), + .D(key3_i_1_n_0), + .Q(key3_reg_n_0), + .R(1'b0)); + LUT6 #( + .INIT(64'hAAAAFFFFAAAAFFFC)) + key4_i_1 + (.I0(key4_reg_n_0), + .I1(key3), + .I2(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I4(reset), + .I5(breaking_en), + .O(key4_i_1_n_0)); + LUT4 #( + .INIT(16'hFFFE)) + key4_i_2 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .O(key3)); + FDRE #( + .INIT(1'b1)) + key4_prev_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key4_reg_n_0), + .Q(key4_prev), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + key4_reg + (.C(externalCLK), + .CE(1'b1), + .D(key4_i_1_n_0), + .Q(key4_reg_n_0), + .R(1'b0)); + CARRY4 ltOp__15_carry + (.CI(1'b0), + .CO({ltOp__15_carry_n_0,ltOp__15_carry_n_1,ltOp__15_carry_n_2,ltOp__15_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp__15_carry_i_1_n_0,ltOp__15_carry_i_2_n_0,ltOp__15_carry_i_3_n_0,ltOp__15_carry_i_4_n_0}), + .O(NLW_ltOp__15_carry_O_UNCONNECTED[3:0]), + .S({ltOp__15_carry_i_5_n_0,ltOp__15_carry_i_6_n_0,ltOp__15_carry_i_7_n_0,ltOp__15_carry_i_8_n_0})); + CARRY4 ltOp__15_carry__0 + (.CI(ltOp__15_carry_n_0), + .CO({ltOp__15_carry__0_n_0,ltOp__15_carry__0_n_1,ltOp__15_carry__0_n_2,ltOp__15_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp__15_carry__0_i_1_n_0,ltOp__15_carry__0_i_2_n_0,ltOp__15_carry__0_i_3_n_0,ltOp__15_carry__0_i_4_n_0}), + .O(NLW_ltOp__15_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp__15_carry__0_i_5_n_0,ltOp__15_carry__0_i_6_n_0,ltOp__15_carry__0_i_7_n_0,ltOp__15_carry__0_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__0_i_1 + (.I0(minTime[15]), + .I1(minTimeCounter_low_reg[15]), + .I2(minTime[14]), + .I3(minTimeCounter_low_reg[14]), + .O(ltOp__15_carry__0_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__0_i_2 + (.I0(minTime[13]), + .I1(minTimeCounter_low_reg[13]), + .I2(minTime[12]), + .I3(minTimeCounter_low_reg[12]), + .O(ltOp__15_carry__0_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__0_i_3 + (.I0(minTime[11]), + .I1(minTimeCounter_low_reg[11]), + .I2(minTime[10]), + .I3(minTimeCounter_low_reg[10]), + .O(ltOp__15_carry__0_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__0_i_4 + (.I0(minTime[9]), + .I1(minTimeCounter_low_reg[9]), + .I2(minTime[8]), + .I3(minTimeCounter_low_reg[8]), + .O(ltOp__15_carry__0_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__0_i_5 + (.I0(minTimeCounter_low_reg[15]), + .I1(minTime[15]), + .I2(minTimeCounter_low_reg[14]), + .I3(minTime[14]), + .O(ltOp__15_carry__0_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__0_i_6 + (.I0(minTimeCounter_low_reg[13]), + .I1(minTime[13]), + .I2(minTimeCounter_low_reg[12]), + .I3(minTime[12]), + .O(ltOp__15_carry__0_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__0_i_7 + (.I0(minTimeCounter_low_reg[11]), + .I1(minTime[11]), + .I2(minTimeCounter_low_reg[10]), + .I3(minTime[10]), + .O(ltOp__15_carry__0_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__0_i_8 + (.I0(minTimeCounter_low_reg[9]), + .I1(minTime[9]), + .I2(minTimeCounter_low_reg[8]), + .I3(minTime[8]), + .O(ltOp__15_carry__0_i_8_n_0)); + CARRY4 ltOp__15_carry__1 + (.CI(ltOp__15_carry__0_n_0), + .CO({ltOp__15_carry__1_n_0,ltOp__15_carry__1_n_1,ltOp__15_carry__1_n_2,ltOp__15_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp__15_carry__1_i_1_n_0,ltOp__15_carry__1_i_2_n_0,ltOp__15_carry__1_i_3_n_0,ltOp__15_carry__1_i_4_n_0}), + .O(NLW_ltOp__15_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp__15_carry__1_i_5_n_0,ltOp__15_carry__1_i_6_n_0,ltOp__15_carry__1_i_7_n_0,ltOp__15_carry__1_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__1_i_1 + (.I0(minTime[23]), + .I1(minTimeCounter_low_reg[23]), + .I2(minTime[22]), + .I3(minTimeCounter_low_reg[22]), + .O(ltOp__15_carry__1_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__1_i_2 + (.I0(minTime[21]), + .I1(minTimeCounter_low_reg[21]), + .I2(minTime[20]), + .I3(minTimeCounter_low_reg[20]), + .O(ltOp__15_carry__1_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__1_i_3 + (.I0(minTime[19]), + .I1(minTimeCounter_low_reg[19]), + .I2(minTime[18]), + .I3(minTimeCounter_low_reg[18]), + .O(ltOp__15_carry__1_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__1_i_4 + (.I0(minTime[17]), + .I1(minTimeCounter_low_reg[17]), + .I2(minTime[16]), + .I3(minTimeCounter_low_reg[16]), + .O(ltOp__15_carry__1_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__1_i_5 + (.I0(minTimeCounter_low_reg[23]), + .I1(minTime[23]), + .I2(minTimeCounter_low_reg[22]), + .I3(minTime[22]), + .O(ltOp__15_carry__1_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__1_i_6 + (.I0(minTimeCounter_low_reg[21]), + .I1(minTime[21]), + .I2(minTimeCounter_low_reg[20]), + .I3(minTime[20]), + .O(ltOp__15_carry__1_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__1_i_7 + (.I0(minTimeCounter_low_reg[19]), + .I1(minTime[19]), + .I2(minTimeCounter_low_reg[18]), + .I3(minTime[18]), + .O(ltOp__15_carry__1_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__1_i_8 + (.I0(minTimeCounter_low_reg[17]), + .I1(minTime[17]), + .I2(minTimeCounter_low_reg[16]), + .I3(minTime[16]), + .O(ltOp__15_carry__1_i_8_n_0)); + CARRY4 ltOp__15_carry__2 + (.CI(ltOp__15_carry__1_n_0), + .CO({ltOp__15_carry__2_n_0,ltOp__15_carry__2_n_1,ltOp__15_carry__2_n_2,ltOp__15_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp__15_carry__2_i_1_n_0,ltOp__15_carry__2_i_2_n_0,ltOp__15_carry__2_i_3_n_0,ltOp__15_carry__2_i_4_n_0}), + .O(NLW_ltOp__15_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp__15_carry__2_i_5_n_0,ltOp__15_carry__2_i_6_n_0,ltOp__15_carry__2_i_7_n_0,ltOp__15_carry__2_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__2_i_1 + (.I0(minTime[31]), + .I1(minTimeCounter_low_reg[31]), + .I2(minTime[30]), + .I3(minTimeCounter_low_reg[30]), + .O(ltOp__15_carry__2_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__2_i_2 + (.I0(minTime[29]), + .I1(minTimeCounter_low_reg[29]), + .I2(minTime[28]), + .I3(minTimeCounter_low_reg[28]), + .O(ltOp__15_carry__2_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__2_i_3 + (.I0(minTime[27]), + .I1(minTimeCounter_low_reg[27]), + .I2(minTime[26]), + .I3(minTimeCounter_low_reg[26]), + .O(ltOp__15_carry__2_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__2_i_4 + (.I0(minTime[25]), + .I1(minTimeCounter_low_reg[25]), + .I2(minTime[24]), + .I3(minTimeCounter_low_reg[24]), + .O(ltOp__15_carry__2_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__2_i_5 + (.I0(minTimeCounter_low_reg[31]), + .I1(minTime[31]), + .I2(minTimeCounter_low_reg[30]), + .I3(minTime[30]), + .O(ltOp__15_carry__2_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__2_i_6 + (.I0(minTimeCounter_low_reg[29]), + .I1(minTime[29]), + .I2(minTimeCounter_low_reg[28]), + .I3(minTime[28]), + .O(ltOp__15_carry__2_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__2_i_7 + (.I0(minTimeCounter_low_reg[27]), + .I1(minTime[27]), + .I2(minTimeCounter_low_reg[26]), + .I3(minTime[26]), + .O(ltOp__15_carry__2_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__2_i_8 + (.I0(minTimeCounter_low_reg[25]), + .I1(minTime[25]), + .I2(minTimeCounter_low_reg[24]), + .I3(minTime[24]), + .O(ltOp__15_carry__2_i_8_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry_i_1 + (.I0(minTime[7]), + .I1(minTimeCounter_low_reg[7]), + .I2(minTime[6]), + .I3(minTimeCounter_low_reg[6]), + .O(ltOp__15_carry_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry_i_2 + (.I0(minTime[5]), + .I1(minTimeCounter_low_reg[5]), + .I2(minTime[4]), + .I3(minTimeCounter_low_reg[4]), + .O(ltOp__15_carry_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry_i_3 + (.I0(minTime[3]), + .I1(minTimeCounter_low_reg[3]), + .I2(minTime[2]), + .I3(minTimeCounter_low_reg[2]), + .O(ltOp__15_carry_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry_i_4 + (.I0(minTime[1]), + .I1(minTimeCounter_low_reg[1]), + .I2(minTime[0]), + .I3(minTimeCounter_low_reg[0]), + .O(ltOp__15_carry_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry_i_5 + (.I0(minTimeCounter_low_reg[7]), + .I1(minTime[7]), + .I2(minTimeCounter_low_reg[6]), + .I3(minTime[6]), + .O(ltOp__15_carry_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry_i_6 + (.I0(minTimeCounter_low_reg[5]), + .I1(minTime[5]), + .I2(minTimeCounter_low_reg[4]), + .I3(minTime[4]), + .O(ltOp__15_carry_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry_i_7 + (.I0(minTimeCounter_low_reg[3]), + .I1(minTime[3]), + .I2(minTimeCounter_low_reg[2]), + .I3(minTime[2]), + .O(ltOp__15_carry_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry_i_8 + (.I0(minTimeCounter_low_reg[1]), + .I1(minTime[1]), + .I2(minTimeCounter_low_reg[0]), + .I3(minTime[0]), + .O(ltOp__15_carry_i_8_n_0)); + CARRY4 ltOp__31_carry + (.CI(1'b0), + .CO({ltOp__31_carry_n_0,ltOp__31_carry_n_1,ltOp__31_carry_n_2,ltOp__31_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp__31_carry_i_1_n_0,ltOp__31_carry_i_2_n_0,ltOp__31_carry_i_3_n_0,ltOp__31_carry_i_4_n_0}), + .O(NLW_ltOp__31_carry_O_UNCONNECTED[3:0]), + .S({ltOp__31_carry_i_5_n_0,ltOp__31_carry_i_6_n_0,ltOp__31_carry_i_7_n_0,ltOp__31_carry_i_8_n_0})); + CARRY4 ltOp__31_carry__0 + (.CI(ltOp__31_carry_n_0), + .CO({ltOp__31_carry__0_n_0,ltOp__31_carry__0_n_1,ltOp__31_carry__0_n_2,ltOp__31_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp__31_carry_i_1__0_n_0,ltOp__31_carry_i_2__0_n_0,ltOp__31_carry_i_3__0_n_0,ltOp__31_carry_i_4__0_n_0}), + .O(NLW_ltOp__31_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp__31_carry_i_5__0_n_0,ltOp__31_carry_i_6__0_n_0,ltOp__31_carry_i_7__0_n_0,ltOp__31_carry_i_8__0_n_0})); + CARRY4 ltOp__31_carry__1 + (.CI(ltOp__31_carry__0_n_0), + .CO({ltOp__31_carry__1_n_0,ltOp__31_carry__1_n_1,ltOp__31_carry__1_n_2,ltOp__31_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp__31_carry_i_1__1_n_0,ltOp__31_carry_i_2__1_n_0,ltOp__31_carry_i_3__1_n_0,ltOp__31_carry_i_4__1_n_0}), + .O(NLW_ltOp__31_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp__31_carry_i_5__1_n_0,ltOp__31_carry_i_6__1_n_0,ltOp__31_carry_i_7__1_n_0,ltOp__31_carry_i_8__1_n_0})); + CARRY4 ltOp__31_carry__2 + (.CI(ltOp__31_carry__1_n_0), + .CO({ltOp__31_carry__2_n_0,ltOp__31_carry__2_n_1,ltOp__31_carry__2_n_2,ltOp__31_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp__31_carry_i_1__2_n_0,ltOp__31_carry_i_2__2_n_0,ltOp__31_carry_i_3__2_n_0,ltOp__31_carry_i_4__2_n_0}), + .O(NLW_ltOp__31_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp__31_carry_i_5__2_n_0,ltOp__31_carry_i_6__2_n_0,ltOp__31_carry_i_7__2_n_0,ltOp__31_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_1 + (.I0(minTime[7]), + .I1(minTimeCounter_high_reg[7]), + .I2(minTime[6]), + .I3(minTimeCounter_high_reg[6]), + .O(ltOp__31_carry_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_1__0 + (.I0(minTime[15]), + .I1(minTimeCounter_high_reg[15]), + .I2(minTime[14]), + .I3(minTimeCounter_high_reg[14]), + .O(ltOp__31_carry_i_1__0_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_1__1 + (.I0(minTime[23]), + .I1(minTimeCounter_high_reg[23]), + .I2(minTime[22]), + .I3(minTimeCounter_high_reg[22]), + .O(ltOp__31_carry_i_1__1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_1__2 + (.I0(minTime[31]), + .I1(minTimeCounter_high_reg[31]), + .I2(minTime[30]), + .I3(minTimeCounter_high_reg[30]), + .O(ltOp__31_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_2 + (.I0(minTime[5]), + .I1(minTimeCounter_high_reg[5]), + .I2(minTime[4]), + .I3(minTimeCounter_high_reg[4]), + .O(ltOp__31_carry_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_2__0 + (.I0(minTime[13]), + .I1(minTimeCounter_high_reg[13]), + .I2(minTime[12]), + .I3(minTimeCounter_high_reg[12]), + .O(ltOp__31_carry_i_2__0_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_2__1 + (.I0(minTime[21]), + .I1(minTimeCounter_high_reg[21]), + .I2(minTime[20]), + .I3(minTimeCounter_high_reg[20]), + .O(ltOp__31_carry_i_2__1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_2__2 + (.I0(minTime[29]), + .I1(minTimeCounter_high_reg[29]), + .I2(minTime[28]), + .I3(minTimeCounter_high_reg[28]), + .O(ltOp__31_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_3 + (.I0(minTime[3]), + .I1(minTimeCounter_high_reg[3]), + .I2(minTime[2]), + .I3(minTimeCounter_high_reg[2]), + .O(ltOp__31_carry_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_3__0 + (.I0(minTime[11]), + .I1(minTimeCounter_high_reg[11]), + .I2(minTime[10]), + .I3(minTimeCounter_high_reg[10]), + .O(ltOp__31_carry_i_3__0_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_3__1 + (.I0(minTime[19]), + .I1(minTimeCounter_high_reg[19]), + .I2(minTime[18]), + .I3(minTimeCounter_high_reg[18]), + .O(ltOp__31_carry_i_3__1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_3__2 + (.I0(minTime[27]), + .I1(minTimeCounter_high_reg[27]), + .I2(minTime[26]), + .I3(minTimeCounter_high_reg[26]), + .O(ltOp__31_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_4 + (.I0(minTime[1]), + .I1(minTimeCounter_high_reg[1]), + .I2(minTime[0]), + .I3(minTimeCounter_high_reg[0]), + .O(ltOp__31_carry_i_4_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_4__0 + (.I0(minTime[9]), + .I1(minTimeCounter_high_reg[9]), + .I2(minTime[8]), + .I3(minTimeCounter_high_reg[8]), + .O(ltOp__31_carry_i_4__0_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_4__1 + (.I0(minTime[17]), + .I1(minTimeCounter_high_reg[17]), + .I2(minTime[16]), + .I3(minTimeCounter_high_reg[16]), + .O(ltOp__31_carry_i_4__1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_4__2 + (.I0(minTime[25]), + .I1(minTimeCounter_high_reg[25]), + .I2(minTime[24]), + .I3(minTimeCounter_high_reg[24]), + .O(ltOp__31_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_5 + (.I0(minTimeCounter_high_reg[7]), + .I1(minTime[7]), + .I2(minTimeCounter_high_reg[6]), + .I3(minTime[6]), + .O(ltOp__31_carry_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_5__0 + (.I0(minTimeCounter_high_reg[15]), + .I1(minTime[15]), + .I2(minTimeCounter_high_reg[14]), + .I3(minTime[14]), + .O(ltOp__31_carry_i_5__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_5__1 + (.I0(minTimeCounter_high_reg[23]), + .I1(minTime[23]), + .I2(minTimeCounter_high_reg[22]), + .I3(minTime[22]), + .O(ltOp__31_carry_i_5__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_5__2 + (.I0(minTimeCounter_high_reg[31]), + .I1(minTime[31]), + .I2(minTimeCounter_high_reg[30]), + .I3(minTime[30]), + .O(ltOp__31_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_6 + (.I0(minTimeCounter_high_reg[5]), + .I1(minTime[5]), + .I2(minTimeCounter_high_reg[4]), + .I3(minTime[4]), + .O(ltOp__31_carry_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_6__0 + (.I0(minTimeCounter_high_reg[13]), + .I1(minTime[13]), + .I2(minTimeCounter_high_reg[12]), + .I3(minTime[12]), + .O(ltOp__31_carry_i_6__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_6__1 + (.I0(minTimeCounter_high_reg[21]), + .I1(minTime[21]), + .I2(minTimeCounter_high_reg[20]), + .I3(minTime[20]), + .O(ltOp__31_carry_i_6__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_6__2 + (.I0(minTimeCounter_high_reg[29]), + .I1(minTime[29]), + .I2(minTimeCounter_high_reg[28]), + .I3(minTime[28]), + .O(ltOp__31_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_7 + (.I0(minTimeCounter_high_reg[3]), + .I1(minTime[3]), + .I2(minTimeCounter_high_reg[2]), + .I3(minTime[2]), + .O(ltOp__31_carry_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_7__0 + (.I0(minTimeCounter_high_reg[11]), + .I1(minTime[11]), + .I2(minTimeCounter_high_reg[10]), + .I3(minTime[10]), + .O(ltOp__31_carry_i_7__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_7__1 + (.I0(minTimeCounter_high_reg[19]), + .I1(minTime[19]), + .I2(minTimeCounter_high_reg[18]), + .I3(minTime[18]), + .O(ltOp__31_carry_i_7__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_7__2 + (.I0(minTimeCounter_high_reg[27]), + .I1(minTime[27]), + .I2(minTimeCounter_high_reg[26]), + .I3(minTime[26]), + .O(ltOp__31_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_8 + (.I0(minTimeCounter_high_reg[1]), + .I1(minTime[1]), + .I2(minTimeCounter_high_reg[0]), + .I3(minTime[0]), + .O(ltOp__31_carry_i_8_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_8__0 + (.I0(minTimeCounter_high_reg[9]), + .I1(minTime[9]), + .I2(minTimeCounter_high_reg[8]), + .I3(minTime[8]), + .O(ltOp__31_carry_i_8__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_8__1 + (.I0(minTimeCounter_high_reg[17]), + .I1(minTime[17]), + .I2(minTimeCounter_high_reg[16]), + .I3(minTime[16]), + .O(ltOp__31_carry_i_8__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_8__2 + (.I0(minTimeCounter_high_reg[25]), + .I1(minTime[25]), + .I2(minTimeCounter_high_reg[24]), + .I3(minTime[24]), + .O(ltOp__31_carry_i_8__2_n_0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry__0_i_1_n_0,ltOp_carry__0_i_2_n_0,ltOp_carry__0_i_3_n_0,ltOp_carry__0_i_4_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry__0_i_5_n_0,ltOp_carry__0_i_6_n_0,ltOp_carry__0_i_7_n_0,ltOp_carry__0_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__0_i_1 + (.I0(deadTime[15]), + .I1(TimeCounter_reg[15]), + .I2(deadTime[14]), + .I3(TimeCounter_reg[14]), + .O(ltOp_carry__0_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__0_i_2 + (.I0(deadTime[13]), + .I1(TimeCounter_reg[13]), + .I2(deadTime[12]), + .I3(TimeCounter_reg[12]), + .O(ltOp_carry__0_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__0_i_3 + (.I0(deadTime[11]), + .I1(TimeCounter_reg[11]), + .I2(deadTime[10]), + .I3(TimeCounter_reg[10]), + .O(ltOp_carry__0_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__0_i_4 + (.I0(deadTime[9]), + .I1(TimeCounter_reg[9]), + .I2(deadTime[8]), + .I3(TimeCounter_reg[8]), + .O(ltOp_carry__0_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__0_i_5 + (.I0(TimeCounter_reg[15]), + .I1(deadTime[15]), + .I2(TimeCounter_reg[14]), + .I3(deadTime[14]), + .O(ltOp_carry__0_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__0_i_6 + (.I0(TimeCounter_reg[13]), + .I1(deadTime[13]), + .I2(TimeCounter_reg[12]), + .I3(deadTime[12]), + .O(ltOp_carry__0_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__0_i_7 + (.I0(TimeCounter_reg[11]), + .I1(deadTime[11]), + .I2(TimeCounter_reg[10]), + .I3(deadTime[10]), + .O(ltOp_carry__0_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__0_i_8 + (.I0(TimeCounter_reg[9]), + .I1(deadTime[9]), + .I2(TimeCounter_reg[8]), + .I3(deadTime[8]), + .O(ltOp_carry__0_i_8_n_0)); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry__1_i_1_n_0,ltOp_carry__1_i_2_n_0,ltOp_carry__1_i_3_n_0,ltOp_carry__1_i_4_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry__1_i_5_n_0,ltOp_carry__1_i_6_n_0,ltOp_carry__1_i_7_n_0,ltOp_carry__1_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__1_i_1 + (.I0(deadTime[23]), + .I1(TimeCounter_reg[23]), + .I2(deadTime[22]), + .I3(TimeCounter_reg[22]), + .O(ltOp_carry__1_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__1_i_2 + (.I0(deadTime[21]), + .I1(TimeCounter_reg[21]), + .I2(deadTime[20]), + .I3(TimeCounter_reg[20]), + .O(ltOp_carry__1_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__1_i_3 + (.I0(deadTime[19]), + .I1(TimeCounter_reg[19]), + .I2(deadTime[18]), + .I3(TimeCounter_reg[18]), + .O(ltOp_carry__1_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__1_i_4 + (.I0(deadTime[17]), + .I1(TimeCounter_reg[17]), + .I2(deadTime[16]), + .I3(TimeCounter_reg[16]), + .O(ltOp_carry__1_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__1_i_5 + (.I0(TimeCounter_reg[23]), + .I1(deadTime[23]), + .I2(TimeCounter_reg[22]), + .I3(deadTime[22]), + .O(ltOp_carry__1_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__1_i_6 + (.I0(TimeCounter_reg[21]), + .I1(deadTime[21]), + .I2(TimeCounter_reg[20]), + .I3(deadTime[20]), + .O(ltOp_carry__1_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__1_i_7 + (.I0(TimeCounter_reg[19]), + .I1(deadTime[19]), + .I2(TimeCounter_reg[18]), + .I3(deadTime[18]), + .O(ltOp_carry__1_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__1_i_8 + (.I0(TimeCounter_reg[17]), + .I1(deadTime[17]), + .I2(TimeCounter_reg[16]), + .I3(deadTime[16]), + .O(ltOp_carry__1_i_8_n_0)); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({sel,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry__2_i_1_n_0,ltOp_carry__2_i_2_n_0,ltOp_carry__2_i_3_n_0,ltOp_carry__2_i_4_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry__2_i_5_n_0,ltOp_carry__2_i_6_n_0,ltOp_carry__2_i_7_n_0,ltOp_carry__2_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__2_i_1 + (.I0(deadTime[31]), + .I1(TimeCounter_reg[31]), + .I2(deadTime[30]), + .I3(TimeCounter_reg[30]), + .O(ltOp_carry__2_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__2_i_2 + (.I0(deadTime[29]), + .I1(TimeCounter_reg[29]), + .I2(deadTime[28]), + .I3(TimeCounter_reg[28]), + .O(ltOp_carry__2_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__2_i_3 + (.I0(deadTime[27]), + .I1(TimeCounter_reg[27]), + .I2(deadTime[26]), + .I3(TimeCounter_reg[26]), + .O(ltOp_carry__2_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__2_i_4 + (.I0(deadTime[25]), + .I1(TimeCounter_reg[25]), + .I2(deadTime[24]), + .I3(TimeCounter_reg[24]), + .O(ltOp_carry__2_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__2_i_5 + (.I0(TimeCounter_reg[31]), + .I1(deadTime[31]), + .I2(TimeCounter_reg[30]), + .I3(deadTime[30]), + .O(ltOp_carry__2_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__2_i_6 + (.I0(TimeCounter_reg[29]), + .I1(deadTime[29]), + .I2(TimeCounter_reg[28]), + .I3(deadTime[28]), + .O(ltOp_carry__2_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__2_i_7 + (.I0(TimeCounter_reg[27]), + .I1(deadTime[27]), + .I2(TimeCounter_reg[26]), + .I3(deadTime[26]), + .O(ltOp_carry__2_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__2_i_8 + (.I0(TimeCounter_reg[25]), + .I1(deadTime[25]), + .I2(TimeCounter_reg[24]), + .I3(deadTime[24]), + .O(ltOp_carry__2_i_8_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry_i_1 + (.I0(deadTime[7]), + .I1(TimeCounter_reg[7]), + .I2(deadTime[6]), + .I3(TimeCounter_reg[6]), + .O(ltOp_carry_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry_i_2 + (.I0(deadTime[5]), + .I1(TimeCounter_reg[5]), + .I2(deadTime[4]), + .I3(TimeCounter_reg[4]), + .O(ltOp_carry_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry_i_3 + (.I0(deadTime[3]), + .I1(TimeCounter_reg[3]), + .I2(deadTime[2]), + .I3(TimeCounter_reg[2]), + .O(ltOp_carry_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry_i_4 + (.I0(deadTime[1]), + .I1(TimeCounter_reg[1]), + .I2(deadTime[0]), + .I3(TimeCounter_reg[0]), + .O(ltOp_carry_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(TimeCounter_reg[7]), + .I1(deadTime[7]), + .I2(TimeCounter_reg[6]), + .I3(deadTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(TimeCounter_reg[5]), + .I1(deadTime[5]), + .I2(TimeCounter_reg[4]), + .I3(deadTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(TimeCounter_reg[3]), + .I1(deadTime[3]), + .I2(TimeCounter_reg[2]), + .I3(deadTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(TimeCounter_reg[1]), + .I1(deadTime[1]), + .I2(TimeCounter_reg[0]), + .I3(deadTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT6 #( + .INIT(64'h0000000022222F22)) + \minTimeCounter_high[0]_i_1 + (.I0(key1_prev), + .I1(key1_reg_n_0), + .I2(key2_reg_n_0), + .I3(key2_prev), + .I4(breaking_en), + .I5(reset), + .O(\minTimeCounter_high[0]_i_1_n_0 )); + LUT2 #( + .INIT(4'h2)) + \minTimeCounter_high[0]_i_2 + (.I0(ltOp__31_carry__2_n_0), + .I1(reset), + .O(minTimeCounter_high)); + LUT1 #( + .INIT(2'h1)) + \minTimeCounter_high[0]_i_4 + (.I0(minTimeCounter_high_reg[0]), + .O(\minTimeCounter_high[0]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[0] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[0]_i_3_n_7 ), + .Q(minTimeCounter_high_reg[0]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[0]_i_3 + (.CI(1'b0), + .CO({\minTimeCounter_high_reg[0]_i_3_n_0 ,\minTimeCounter_high_reg[0]_i_3_n_1 ,\minTimeCounter_high_reg[0]_i_3_n_2 ,\minTimeCounter_high_reg[0]_i_3_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\minTimeCounter_high_reg[0]_i_3_n_4 ,\minTimeCounter_high_reg[0]_i_3_n_5 ,\minTimeCounter_high_reg[0]_i_3_n_6 ,\minTimeCounter_high_reg[0]_i_3_n_7 }), + .S({minTimeCounter_high_reg[3:1],\minTimeCounter_high[0]_i_4_n_0 })); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[10] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[8]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[10]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[11] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[8]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[11]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[12] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[12]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[12]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[12]_i_1 + (.CI(\minTimeCounter_high_reg[8]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[12]_i_1_n_0 ,\minTimeCounter_high_reg[12]_i_1_n_1 ,\minTimeCounter_high_reg[12]_i_1_n_2 ,\minTimeCounter_high_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[12]_i_1_n_4 ,\minTimeCounter_high_reg[12]_i_1_n_5 ,\minTimeCounter_high_reg[12]_i_1_n_6 ,\minTimeCounter_high_reg[12]_i_1_n_7 }), + .S(minTimeCounter_high_reg[15:12])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[13] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[12]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[13]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[14] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[12]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[14]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[15] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[12]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[15]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[16] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[16]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[16]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[16]_i_1 + (.CI(\minTimeCounter_high_reg[12]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[16]_i_1_n_0 ,\minTimeCounter_high_reg[16]_i_1_n_1 ,\minTimeCounter_high_reg[16]_i_1_n_2 ,\minTimeCounter_high_reg[16]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[16]_i_1_n_4 ,\minTimeCounter_high_reg[16]_i_1_n_5 ,\minTimeCounter_high_reg[16]_i_1_n_6 ,\minTimeCounter_high_reg[16]_i_1_n_7 }), + .S(minTimeCounter_high_reg[19:16])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[17] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[16]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[17]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[18] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[16]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[18]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[19] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[16]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[19]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[1] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[0]_i_3_n_6 ), + .Q(minTimeCounter_high_reg[1]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[20] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[20]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[20]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[20]_i_1 + (.CI(\minTimeCounter_high_reg[16]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[20]_i_1_n_0 ,\minTimeCounter_high_reg[20]_i_1_n_1 ,\minTimeCounter_high_reg[20]_i_1_n_2 ,\minTimeCounter_high_reg[20]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[20]_i_1_n_4 ,\minTimeCounter_high_reg[20]_i_1_n_5 ,\minTimeCounter_high_reg[20]_i_1_n_6 ,\minTimeCounter_high_reg[20]_i_1_n_7 }), + .S(minTimeCounter_high_reg[23:20])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[21] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[20]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[21]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[22] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[20]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[22]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[23] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[20]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[23]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[24] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[24]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[24]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[24]_i_1 + (.CI(\minTimeCounter_high_reg[20]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[24]_i_1_n_0 ,\minTimeCounter_high_reg[24]_i_1_n_1 ,\minTimeCounter_high_reg[24]_i_1_n_2 ,\minTimeCounter_high_reg[24]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[24]_i_1_n_4 ,\minTimeCounter_high_reg[24]_i_1_n_5 ,\minTimeCounter_high_reg[24]_i_1_n_6 ,\minTimeCounter_high_reg[24]_i_1_n_7 }), + .S(minTimeCounter_high_reg[27:24])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[25] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[24]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[25]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[26] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[24]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[26]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[27] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[24]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[27]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[28] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[28]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[28]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[28]_i_1 + (.CI(\minTimeCounter_high_reg[24]_i_1_n_0 ), + .CO({\NLW_minTimeCounter_high_reg[28]_i_1_CO_UNCONNECTED [3],\minTimeCounter_high_reg[28]_i_1_n_1 ,\minTimeCounter_high_reg[28]_i_1_n_2 ,\minTimeCounter_high_reg[28]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[28]_i_1_n_4 ,\minTimeCounter_high_reg[28]_i_1_n_5 ,\minTimeCounter_high_reg[28]_i_1_n_6 ,\minTimeCounter_high_reg[28]_i_1_n_7 }), + .S(minTimeCounter_high_reg[31:28])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[29] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[28]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[29]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[2] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[0]_i_3_n_5 ), + .Q(minTimeCounter_high_reg[2]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[30] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[28]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[30]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[31] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[28]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[31]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[3] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[0]_i_3_n_4 ), + .Q(minTimeCounter_high_reg[3]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[4] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[4]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[4]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[4]_i_1 + (.CI(\minTimeCounter_high_reg[0]_i_3_n_0 ), + .CO({\minTimeCounter_high_reg[4]_i_1_n_0 ,\minTimeCounter_high_reg[4]_i_1_n_1 ,\minTimeCounter_high_reg[4]_i_1_n_2 ,\minTimeCounter_high_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[4]_i_1_n_4 ,\minTimeCounter_high_reg[4]_i_1_n_5 ,\minTimeCounter_high_reg[4]_i_1_n_6 ,\minTimeCounter_high_reg[4]_i_1_n_7 }), + .S(minTimeCounter_high_reg[7:4])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[5] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[4]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[5]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[6] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[4]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[6]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[7] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[4]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[7]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[8] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[8]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[8]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[8]_i_1 + (.CI(\minTimeCounter_high_reg[4]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[8]_i_1_n_0 ,\minTimeCounter_high_reg[8]_i_1_n_1 ,\minTimeCounter_high_reg[8]_i_1_n_2 ,\minTimeCounter_high_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[8]_i_1_n_4 ,\minTimeCounter_high_reg[8]_i_1_n_5 ,\minTimeCounter_high_reg[8]_i_1_n_6 ,\minTimeCounter_high_reg[8]_i_1_n_7 }), + .S(minTimeCounter_high_reg[11:8])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[9] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[8]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[9]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + LUT5 #( + .INIT(32'h0000440F)) + \minTimeCounter_low[0]_i_1 + (.I0(key2_reg_n_0), + .I1(key2_prev), + .I2(\minTimeCounter_low[0]_i_4_n_0 ), + .I3(breaking_en), + .I4(reset), + .O(\minTimeCounter_low[0]_i_1_n_0 )); + LUT2 #( + .INIT(4'h2)) + \minTimeCounter_low[0]_i_2 + (.I0(ltOp__15_carry__2_n_0), + .I1(reset), + .O(minTimeCounter_low)); + LUT4 #( + .INIT(16'hD0DD)) + \minTimeCounter_low[0]_i_4 + (.I0(key4_prev), + .I1(key4_reg_n_0), + .I2(key3_reg_n_0), + .I3(key3_prev), + .O(\minTimeCounter_low[0]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \minTimeCounter_low[0]_i_5 + (.I0(minTimeCounter_low_reg[0]), + .O(\minTimeCounter_low[0]_i_5_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[0] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[0]_i_3_n_7 ), + .Q(minTimeCounter_low_reg[0]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[0]_i_3 + (.CI(1'b0), + .CO({\minTimeCounter_low_reg[0]_i_3_n_0 ,\minTimeCounter_low_reg[0]_i_3_n_1 ,\minTimeCounter_low_reg[0]_i_3_n_2 ,\minTimeCounter_low_reg[0]_i_3_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\minTimeCounter_low_reg[0]_i_3_n_4 ,\minTimeCounter_low_reg[0]_i_3_n_5 ,\minTimeCounter_low_reg[0]_i_3_n_6 ,\minTimeCounter_low_reg[0]_i_3_n_7 }), + .S({minTimeCounter_low_reg[3:1],\minTimeCounter_low[0]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[10] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[8]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[10]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[11] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[8]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[11]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[12] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[12]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[12]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[12]_i_1 + (.CI(\minTimeCounter_low_reg[8]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[12]_i_1_n_0 ,\minTimeCounter_low_reg[12]_i_1_n_1 ,\minTimeCounter_low_reg[12]_i_1_n_2 ,\minTimeCounter_low_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[12]_i_1_n_4 ,\minTimeCounter_low_reg[12]_i_1_n_5 ,\minTimeCounter_low_reg[12]_i_1_n_6 ,\minTimeCounter_low_reg[12]_i_1_n_7 }), + .S(minTimeCounter_low_reg[15:12])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[13] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[12]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[13]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[14] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[12]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[14]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[15] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[12]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[15]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[16] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[16]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[16]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[16]_i_1 + (.CI(\minTimeCounter_low_reg[12]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[16]_i_1_n_0 ,\minTimeCounter_low_reg[16]_i_1_n_1 ,\minTimeCounter_low_reg[16]_i_1_n_2 ,\minTimeCounter_low_reg[16]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[16]_i_1_n_4 ,\minTimeCounter_low_reg[16]_i_1_n_5 ,\minTimeCounter_low_reg[16]_i_1_n_6 ,\minTimeCounter_low_reg[16]_i_1_n_7 }), + .S(minTimeCounter_low_reg[19:16])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[17] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[16]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[17]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[18] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[16]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[18]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[19] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[16]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[19]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[1] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[0]_i_3_n_6 ), + .Q(minTimeCounter_low_reg[1]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[20] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[20]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[20]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[20]_i_1 + (.CI(\minTimeCounter_low_reg[16]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[20]_i_1_n_0 ,\minTimeCounter_low_reg[20]_i_1_n_1 ,\minTimeCounter_low_reg[20]_i_1_n_2 ,\minTimeCounter_low_reg[20]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[20]_i_1_n_4 ,\minTimeCounter_low_reg[20]_i_1_n_5 ,\minTimeCounter_low_reg[20]_i_1_n_6 ,\minTimeCounter_low_reg[20]_i_1_n_7 }), + .S(minTimeCounter_low_reg[23:20])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[21] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[20]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[21]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[22] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[20]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[22]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[23] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[20]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[23]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[24] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[24]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[24]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[24]_i_1 + (.CI(\minTimeCounter_low_reg[20]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[24]_i_1_n_0 ,\minTimeCounter_low_reg[24]_i_1_n_1 ,\minTimeCounter_low_reg[24]_i_1_n_2 ,\minTimeCounter_low_reg[24]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[24]_i_1_n_4 ,\minTimeCounter_low_reg[24]_i_1_n_5 ,\minTimeCounter_low_reg[24]_i_1_n_6 ,\minTimeCounter_low_reg[24]_i_1_n_7 }), + .S(minTimeCounter_low_reg[27:24])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[25] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[24]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[25]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[26] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[24]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[26]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[27] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[24]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[27]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[28] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[28]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[28]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[28]_i_1 + (.CI(\minTimeCounter_low_reg[24]_i_1_n_0 ), + .CO({\NLW_minTimeCounter_low_reg[28]_i_1_CO_UNCONNECTED [3],\minTimeCounter_low_reg[28]_i_1_n_1 ,\minTimeCounter_low_reg[28]_i_1_n_2 ,\minTimeCounter_low_reg[28]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[28]_i_1_n_4 ,\minTimeCounter_low_reg[28]_i_1_n_5 ,\minTimeCounter_low_reg[28]_i_1_n_6 ,\minTimeCounter_low_reg[28]_i_1_n_7 }), + .S(minTimeCounter_low_reg[31:28])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[29] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[28]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[29]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[2] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[0]_i_3_n_5 ), + .Q(minTimeCounter_low_reg[2]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[30] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[28]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[30]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[31] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[28]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[31]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[3] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[0]_i_3_n_4 ), + .Q(minTimeCounter_low_reg[3]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[4] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[4]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[4]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[4]_i_1 + (.CI(\minTimeCounter_low_reg[0]_i_3_n_0 ), + .CO({\minTimeCounter_low_reg[4]_i_1_n_0 ,\minTimeCounter_low_reg[4]_i_1_n_1 ,\minTimeCounter_low_reg[4]_i_1_n_2 ,\minTimeCounter_low_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[4]_i_1_n_4 ,\minTimeCounter_low_reg[4]_i_1_n_5 ,\minTimeCounter_low_reg[4]_i_1_n_6 ,\minTimeCounter_low_reg[4]_i_1_n_7 }), + .S(minTimeCounter_low_reg[7:4])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[5] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[4]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[5]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[6] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[4]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[6]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[7] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[4]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[7]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[8] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[8]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[8]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[8]_i_1 + (.CI(\minTimeCounter_low_reg[4]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[8]_i_1_n_0 ,\minTimeCounter_low_reg[8]_i_1_n_1 ,\minTimeCounter_low_reg[8]_i_1_n_2 ,\minTimeCounter_low_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[8]_i_1_n_4 ,\minTimeCounter_low_reg[8]_i_1_n_5 ,\minTimeCounter_low_reg[8]_i_1_n_6 ,\minTimeCounter_low_reg[8]_i_1_n_7 }), + .S(minTimeCounter_low_reg[11:8])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[9] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[8]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[9]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'hEEFFEEEEE200E2E2)) + minTimeEr_i_1 + (.I0(minTimeEr_i_2_n_0), + .I1(minTimeEr_i_3_n_0), + .I2(minTimeEr_i_4_n_0), + .I3(minTimeEr_i_5_n_0), + .I4(minTimeEr_i_6_n_0), + .I5(minTimeEr_reg_0), + .O(minTimeEr_i_1_n_0)); + LUT4 #( + .INIT(16'h0111)) + minTimeEr_i_2 + (.I0(reset), + .I1(breaking_en), + .I2(minTimeEr_i_6_n_0), + .I3(minTimeEr_i_7_n_0), + .O(minTimeEr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h2)) + minTimeEr_i_3 + (.I0(breaking_en), + .I1(reset), + .O(minTimeEr_i_3_n_0)); + LUT6 #( + .INIT(64'h040404FF00000000)) + minTimeEr_i_4 + (.I0(minTimeOK_low), + .I1(key2_reg_n_0), + .I2(key2_prev), + .I3(minTimeEr_i_8_n_0), + .I4(minTimeOK_high), + .I5(minTime_En), + .O(minTimeEr_i_4_n_0)); + LUT6 #( + .INIT(64'h55555555F755F7F7)) + minTimeEr_i_5 + (.I0(minTimeEr_i_9_n_0), + .I1(key2_prev), + .I2(key2_reg_n_0), + .I3(key1_reg_n_0), + .I4(key1_prev), + .I5(minTimeEr_i_7_n_0), + .O(minTimeEr_i_5_n_0)); + LUT6 #( + .INIT(64'hFBFFFFFFBBFBFBFF)) + minTimeEr_i_6 + (.I0(minTimeOK_low), + .I1(minTime_En), + .I2(key3_prev), + .I3(key3_reg_n_0), + .I4(key4_reg_n_0), + .I5(key4_prev), + .O(minTimeEr_i_6_n_0)); + LUT6 #( + .INIT(64'hFFDFDDDDFFDFFFDF)) + minTimeEr_i_7 + (.I0(minTime_En), + .I1(minTimeOK_high), + .I2(key2_reg_n_0), + .I3(key2_prev), + .I4(key1_prev), + .I5(key1_reg_n_0), + .O(minTimeEr_i_7_n_0)); + LUT2 #( + .INIT(4'hB)) + minTimeEr_i_8 + (.I0(key1_prev), + .I1(key1_reg_n_0), + .O(minTimeEr_i_8_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h1)) + minTimeEr_i_9 + (.I0(breaking_en), + .I1(reset), + .O(minTimeEr_i_9_n_0)); + FDRE #( + .INIT(1'b0)) + minTimeEr_reg + (.C(externalCLK), + .CE(1'b1), + .D(minTimeEr_i_1_n_0), + .Q(minTimeEr_reg_0), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h00AB)) + minTimeOK_high_i_1 + (.I0(minTimeOK_high), + .I1(ltOp__31_carry__2_n_0), + .I2(reset), + .I3(\minTimeCounter_high[0]_i_1_n_0 ), + .O(minTimeOK_high_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + minTimeOK_high_reg + (.C(externalCLK), + .CE(1'b1), + .D(minTimeOK_high_i_1_n_0), + .Q(minTimeOK_high), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'h00AB)) + minTimeOK_low_i_1 + (.I0(minTimeOK_low), + .I1(ltOp__15_carry__2_n_0), + .I2(reset), + .I3(\minTimeCounter_low[0]_i_1_n_0 ), + .O(minTimeOK_low_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + minTimeOK_low_reg + (.C(externalCLK), + .CE(1'b1), + .D(minTimeOK_low_i_1_n_0), + .Q(minTimeOK_low), + .R(1'b0)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0_sim_netlist.vhdl b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0_sim_netlist.vhdl new file mode 100644 index 0000000..cf6d214 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0_sim_netlist.vhdl @@ -0,0 +1,4183 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Fri Jun 11 07:49:57 2021 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top Inverter_3lvl_P0N_3lvl_1_0 -prefix +-- Inverter_3lvl_P0N_3lvl_1_0_ Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.vhdl +-- Design : Inverter_3lvl_P0N_3lvl_0_4 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Inverter_3lvl_P0N_3lvl_1_0_P0N_3lvl is + port ( + minTimeEr_reg_0 : out STD_LOGIC; + PWM_out_0 : out STD_LOGIC; + PWM_out_1 : out STD_LOGIC; + PWM_out_2 : out STD_LOGIC; + PWM_out_3 : out STD_LOGIC; + reset : in STD_LOGIC; + externalCLK : in STD_LOGIC; + TKin0 : in STD_LOGIC; + TKin1 : in STD_LOGIC; + breaking_en : in STD_LOGIC; + er : in STD_LOGIC; + ready : in STD_LOGIC; + minTime_En : in STD_LOGIC; + deadTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + minTime : in STD_LOGIC_VECTOR ( 31 downto 0 ) + ); +end Inverter_3lvl_P0N_3lvl_1_0_P0N_3lvl; + +architecture STRUCTURE of Inverter_3lvl_P0N_3lvl_1_0_P0N_3lvl is + signal \FSM_onehot_lineconfig[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[0]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[1]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[2]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[2]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[3]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[4]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[5]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[5]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[5]_i_3_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_3_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_4_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_5_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_6_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[0]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[1]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[2]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[3]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[4]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[5]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[6]\ : STD_LOGIC; + signal PWM_out_0_i_1_n_0 : STD_LOGIC; + signal PWM_out_1_i_1_n_0 : STD_LOGIC; + signal PWM_out_2_i_1_n_0 : STD_LOGIC; + signal PWM_out_3_i_1_n_0 : STD_LOGIC; + signal TKin0_triggered : STD_LOGIC; + signal TKin0_triggered28_out : STD_LOGIC; + signal TKin0_triggered_i_1_n_0 : STD_LOGIC; + signal TKin1_triggered : STD_LOGIC; + signal TKin1_triggered_i_1_n_0 : STD_LOGIC; + signal \TimeCounter[0]_i_2_n_0\ : STD_LOGIC; + signal TimeCounter_reg : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \TimeCounter_reg[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_7\ : STD_LOGIC; + signal deadTimeCounterReset_i_1_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_2_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_3_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_4_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_5_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_6_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_7_n_0 : STD_LOGIC; + signal deadTimeCounterReset_reg_n_0 : STD_LOGIC; + signal deadTimeOK : STD_LOGIC; + signal deadTimeOK_i_1_n_0 : STD_LOGIC; + signal key1_i_1_n_0 : STD_LOGIC; + signal key1_i_2_n_0 : STD_LOGIC; + signal key1_prev : STD_LOGIC; + signal key1_reg_n_0 : STD_LOGIC; + signal key2_i_2_n_0 : STD_LOGIC; + signal key2_prev : STD_LOGIC; + signal key2_reg_n_0 : STD_LOGIC; + signal key3 : STD_LOGIC; + signal key3_i_1_n_0 : STD_LOGIC; + signal key3_prev : STD_LOGIC; + signal key3_reg_n_0 : STD_LOGIC; + signal key4_i_1_n_0 : STD_LOGIC; + signal key4_prev : STD_LOGIC; + signal key4_reg_n_0 : STD_LOGIC; + signal \ltOp__15_carry__0_i_1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_3_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_4_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_5_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_6_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_7_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_8_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_n_1\ : STD_LOGIC; + signal \ltOp__15_carry__0_n_2\ : STD_LOGIC; + signal \ltOp__15_carry__0_n_3\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_3_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_4_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_5_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_6_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_7_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_8_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_n_1\ : STD_LOGIC; + signal \ltOp__15_carry__1_n_2\ : STD_LOGIC; + signal \ltOp__15_carry__1_n_3\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_3_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_4_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_5_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_6_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_7_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_8_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_n_1\ : STD_LOGIC; + signal \ltOp__15_carry__2_n_2\ : STD_LOGIC; + signal \ltOp__15_carry__2_n_3\ : STD_LOGIC; + signal \ltOp__15_carry_i_1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_3_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_4_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_5_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_6_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_7_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_8_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_n_1\ : STD_LOGIC; + signal \ltOp__15_carry_n_2\ : STD_LOGIC; + signal \ltOp__15_carry_n_3\ : STD_LOGIC; + signal \ltOp__31_carry__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry__0_n_1\ : STD_LOGIC; + signal \ltOp__31_carry__0_n_2\ : STD_LOGIC; + signal \ltOp__31_carry__0_n_3\ : STD_LOGIC; + signal \ltOp__31_carry__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry__1_n_1\ : STD_LOGIC; + signal \ltOp__31_carry__1_n_2\ : STD_LOGIC; + signal \ltOp__31_carry__1_n_3\ : STD_LOGIC; + signal \ltOp__31_carry__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry__2_n_1\ : STD_LOGIC; + signal \ltOp__31_carry__2_n_2\ : STD_LOGIC; + signal \ltOp__31_carry__2_n_3\ : STD_LOGIC; + signal \ltOp__31_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_1__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_2__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_3__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_3_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_4__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_4_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_5__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_5_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_6__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_6_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_7__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_7_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_8__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_8_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_n_1\ : STD_LOGIC; + signal \ltOp__31_carry_n_2\ : STD_LOGIC; + signal \ltOp__31_carry_n_3\ : STD_LOGIC; + signal \ltOp_carry__0_i_1_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_2_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_3_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_4_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_5_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_6_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_7_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_8_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_i_1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_2_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_3_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_4_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_5_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_6_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_7_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_8_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_i_1_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_2_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_3_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_4_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_5_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_6_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_7_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_8_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal minTimeCounter_high : STD_LOGIC; + signal \minTimeCounter_high[0]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high[0]_i_4_n_0\ : STD_LOGIC; + signal minTimeCounter_high_reg : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \minTimeCounter_high_reg[0]_i_3_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_7\ : STD_LOGIC; + signal minTimeCounter_low : STD_LOGIC; + signal \minTimeCounter_low[0]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low[0]_i_4_n_0\ : STD_LOGIC; + signal \minTimeCounter_low[0]_i_5_n_0\ : STD_LOGIC; + signal minTimeCounter_low_reg : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \minTimeCounter_low_reg[0]_i_3_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_7\ : STD_LOGIC; + signal minTimeEr_i_1_n_0 : STD_LOGIC; + signal minTimeEr_i_2_n_0 : STD_LOGIC; + signal minTimeEr_i_3_n_0 : STD_LOGIC; + signal minTimeEr_i_4_n_0 : STD_LOGIC; + signal minTimeEr_i_5_n_0 : STD_LOGIC; + signal minTimeEr_i_6_n_0 : STD_LOGIC; + signal minTimeEr_i_7_n_0 : STD_LOGIC; + signal minTimeEr_i_8_n_0 : STD_LOGIC; + signal minTimeEr_i_9_n_0 : STD_LOGIC; + signal \^mintimeer_reg_0\ : STD_LOGIC; + signal minTimeOK_high : STD_LOGIC; + signal minTimeOK_high_i_1_n_0 : STD_LOGIC; + signal minTimeOK_low : STD_LOGIC; + signal minTimeOK_low_i_1_n_0 : STD_LOGIC; + signal p_0_in : STD_LOGIC; + signal sel : STD_LOGIC; + signal \NLW_TimeCounter_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_ltOp__15_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__15_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__15_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__15_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__31_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__31_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__31_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__31_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_minTimeCounter_high_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_minTimeCounter_low_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[0]_i_2\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[2]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[5]_i_2\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[6]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[6]_i_3\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[6]_i_6\ : label is "soft_lutpair2"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[0]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[1]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[2]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[3]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[4]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[5]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[6]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute SOFT_HLUTNM of PWM_out_0_i_1 : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of PWM_out_1_i_1 : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of deadTimeCounterReset_i_2 : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of deadTimeCounterReset_i_5 : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of deadTimeCounterReset_i_6 : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of deadTimeOK_i_1 : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of key1_i_2 : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of minTimeEr_i_3 : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of minTimeEr_i_9 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of minTimeOK_high_i_1 : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of minTimeOK_low_i_1 : label is "soft_lutpair3"; +begin + minTimeEr_reg_0 <= \^mintimeer_reg_0\; +\FSM_onehot_lineconfig[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFE00000000" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I4 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I5 => \FSM_onehot_lineconfig[0]_i_2_n_0\, + O => \FSM_onehot_lineconfig[0]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[0]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => TKin1, + I1 => TKin0, + O => \FSM_onehot_lineconfig[0]_i_2_n_0\ + ); +\FSM_onehot_lineconfig[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1000FFFF00000000" + ) + port map ( + I0 => TKin1, + I1 => TKin1_triggered, + I2 => TKin0_triggered, + I3 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I4 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I5 => TKin0, + O => \FSM_onehot_lineconfig[1]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00EFEF0F" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I2 => \FSM_onehot_lineconfig[2]_i_2_n_0\, + I3 => TKin0, + I4 => TKin1, + O => \FSM_onehot_lineconfig[2]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"900990099009FFFF" + ) + port map ( + I0 => TKin1, + I1 => TKin1_triggered, + I2 => TKin0, + I3 => TKin0_triggered, + I4 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I5 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + O => \FSM_onehot_lineconfig[2]_i_2_n_0\ + ); +\FSM_onehot_lineconfig[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000055D50000" + ) + port map ( + I0 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I2 => TKin1_triggered, + I3 => TKin0_triggered, + I4 => TKin1, + I5 => TKin0, + O => \FSM_onehot_lineconfig[3]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2230" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I1 => TKin0, + I2 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I3 => TKin1, + O => \FSM_onehot_lineconfig[4]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0CFF0C0D00050005" + ) + port map ( + I0 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I2 => TKin1, + I3 => TKin0, + I4 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I5 => \FSM_onehot_lineconfig[5]_i_3_n_0\, + O => \FSM_onehot_lineconfig[5]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[5]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + O => \FSM_onehot_lineconfig[5]_i_2_n_0\ + ); +\FSM_onehot_lineconfig[5]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TKin0_triggered, + I1 => TKin0, + I2 => TKin1_triggered, + I3 => TKin1, + O => \FSM_onehot_lineconfig[5]_i_3_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => \FSM_onehot_lineconfig[6]_i_3_n_0\, + I1 => \FSM_onehot_lineconfig[6]_i_4_n_0\, + I2 => breaking_en, + O => \FSM_onehot_lineconfig[6]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"5504" + ) + port map ( + I0 => TKin1, + I1 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I2 => TKin0, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + O => \FSM_onehot_lineconfig[6]_i_2_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFEECAE" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I2 => TKin1, + I3 => TKin0, + I4 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + O => \FSM_onehot_lineconfig[6]_i_3_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AABAAAAAFFFFAAAA" + ) + port map ( + I0 => \FSM_onehot_lineconfig[6]_i_5_n_0\, + I1 => er, + I2 => ready, + I3 => \FSM_onehot_lineconfig[6]_i_6_n_0\, + I4 => deadTimeOK, + I5 => \FSM_onehot_lineconfig[2]_i_2_n_0\, + O => \FSM_onehot_lineconfig[6]_i_4_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FC88A0A8" + ) + port map ( + I0 => deadTimeOK, + I1 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I3 => TKin1, + I4 => TKin0, + O => \FSM_onehot_lineconfig[6]_i_5_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF232323" + ) + port map ( + I0 => deadTimeCounterReset_reg_n_0, + I1 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I3 => TKin1, + I4 => TKin0, + O => \FSM_onehot_lineconfig[6]_i_6_n_0\ + ); +\FSM_onehot_lineconfig_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[0]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[0]\, + S => reset + ); +\FSM_onehot_lineconfig_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[1]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[1]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[2]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[2]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[3]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[3]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[4]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[4]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[5]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[5]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[6]_i_2_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[6]\, + R => reset + ); +PWM_out_0_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFEF" + ) + port map ( + I0 => key1_reg_n_0, + I1 => er, + I2 => ready, + I3 => \^mintimeer_reg_0\, + O => PWM_out_0_i_1_n_0 + ); +PWM_out_0_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => PWM_out_0_i_1_n_0, + Q => PWM_out_0, + R => '0' + ); +PWM_out_1_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFEF" + ) + port map ( + I0 => key2_reg_n_0, + I1 => er, + I2 => ready, + I3 => \^mintimeer_reg_0\, + O => PWM_out_1_i_1_n_0 + ); +PWM_out_1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => PWM_out_1_i_1_n_0, + Q => PWM_out_1, + R => '0' + ); +PWM_out_2_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFEF" + ) + port map ( + I0 => key3_reg_n_0, + I1 => \^mintimeer_reg_0\, + I2 => ready, + I3 => er, + I4 => breaking_en, + O => PWM_out_2_i_1_n_0 + ); +PWM_out_2_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => PWM_out_2_i_1_n_0, + Q => PWM_out_2, + R => '0' + ); +PWM_out_3_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFEF" + ) + port map ( + I0 => key4_reg_n_0, + I1 => \^mintimeer_reg_0\, + I2 => ready, + I3 => er, + I4 => breaking_en, + O => PWM_out_3_i_1_n_0 + ); +PWM_out_3_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => PWM_out_3_i_1_n_0, + Q => PWM_out_3, + R => '0' + ); +TKin0_triggered_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA08FFFFAA080000" + ) + port map ( + I0 => TKin0, + I1 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I2 => TKin1, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I4 => TKin0_triggered28_out, + I5 => TKin0_triggered, + O => TKin0_triggered_i_1_n_0 + ); +TKin0_triggered_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => TKin0_triggered_i_1_n_0, + Q => TKin0_triggered, + R => '0' + ); +TKin1_triggered_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA08FFFFAA080000" + ) + port map ( + I0 => TKin1, + I1 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I2 => TKin0, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I4 => TKin0_triggered28_out, + I5 => TKin1_triggered, + O => TKin1_triggered_i_1_n_0 + ); +TKin1_triggered_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"22AA22A820AA2020" + ) + port map ( + I0 => minTimeEr_i_9_n_0, + I1 => TKin1, + I2 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I3 => TKin0, + I4 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I5 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + O => TKin0_triggered28_out + ); +TKin1_triggered_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => TKin1_triggered_i_1_n_0, + Q => TKin1_triggered, + R => '0' + ); +\TimeCounter[0]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => TimeCounter_reg(0), + O => \TimeCounter[0]_i_2_n_0\ + ); +\TimeCounter_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[0]_i_1_n_7\, + Q => TimeCounter_reg(0), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[0]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \TimeCounter_reg[0]_i_1_n_0\, + CO(2) => \TimeCounter_reg[0]_i_1_n_1\, + CO(1) => \TimeCounter_reg[0]_i_1_n_2\, + CO(0) => \TimeCounter_reg[0]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \TimeCounter_reg[0]_i_1_n_4\, + O(2) => \TimeCounter_reg[0]_i_1_n_5\, + O(1) => \TimeCounter_reg[0]_i_1_n_6\, + O(0) => \TimeCounter_reg[0]_i_1_n_7\, + S(3 downto 1) => TimeCounter_reg(3 downto 1), + S(0) => \TimeCounter[0]_i_2_n_0\ + ); +\TimeCounter_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[8]_i_1_n_5\, + Q => TimeCounter_reg(10), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[8]_i_1_n_4\, + Q => TimeCounter_reg(11), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[12]_i_1_n_7\, + Q => TimeCounter_reg(12), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[8]_i_1_n_0\, + CO(3) => \TimeCounter_reg[12]_i_1_n_0\, + CO(2) => \TimeCounter_reg[12]_i_1_n_1\, + CO(1) => \TimeCounter_reg[12]_i_1_n_2\, + CO(0) => \TimeCounter_reg[12]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[12]_i_1_n_4\, + O(2) => \TimeCounter_reg[12]_i_1_n_5\, + O(1) => \TimeCounter_reg[12]_i_1_n_6\, + O(0) => \TimeCounter_reg[12]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(15 downto 12) + ); +\TimeCounter_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[12]_i_1_n_6\, + Q => TimeCounter_reg(13), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[12]_i_1_n_5\, + Q => TimeCounter_reg(14), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[12]_i_1_n_4\, + Q => TimeCounter_reg(15), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[16]_i_1_n_7\, + Q => TimeCounter_reg(16), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[16]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[12]_i_1_n_0\, + CO(3) => \TimeCounter_reg[16]_i_1_n_0\, + CO(2) => \TimeCounter_reg[16]_i_1_n_1\, + CO(1) => \TimeCounter_reg[16]_i_1_n_2\, + CO(0) => \TimeCounter_reg[16]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[16]_i_1_n_4\, + O(2) => \TimeCounter_reg[16]_i_1_n_5\, + O(1) => \TimeCounter_reg[16]_i_1_n_6\, + O(0) => \TimeCounter_reg[16]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(19 downto 16) + ); +\TimeCounter_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[16]_i_1_n_6\, + Q => TimeCounter_reg(17), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[16]_i_1_n_5\, + Q => TimeCounter_reg(18), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[16]_i_1_n_4\, + Q => TimeCounter_reg(19), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[0]_i_1_n_6\, + Q => TimeCounter_reg(1), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[20]_i_1_n_7\, + Q => TimeCounter_reg(20), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[20]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[16]_i_1_n_0\, + CO(3) => \TimeCounter_reg[20]_i_1_n_0\, + CO(2) => \TimeCounter_reg[20]_i_1_n_1\, + CO(1) => \TimeCounter_reg[20]_i_1_n_2\, + CO(0) => \TimeCounter_reg[20]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[20]_i_1_n_4\, + O(2) => \TimeCounter_reg[20]_i_1_n_5\, + O(1) => \TimeCounter_reg[20]_i_1_n_6\, + O(0) => \TimeCounter_reg[20]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(23 downto 20) + ); +\TimeCounter_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[20]_i_1_n_6\, + Q => TimeCounter_reg(21), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[20]_i_1_n_5\, + Q => TimeCounter_reg(22), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[20]_i_1_n_4\, + Q => TimeCounter_reg(23), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[24]_i_1_n_7\, + Q => TimeCounter_reg(24), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[24]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[20]_i_1_n_0\, + CO(3) => \TimeCounter_reg[24]_i_1_n_0\, + CO(2) => \TimeCounter_reg[24]_i_1_n_1\, + CO(1) => \TimeCounter_reg[24]_i_1_n_2\, + CO(0) => \TimeCounter_reg[24]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[24]_i_1_n_4\, + O(2) => \TimeCounter_reg[24]_i_1_n_5\, + O(1) => \TimeCounter_reg[24]_i_1_n_6\, + O(0) => \TimeCounter_reg[24]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(27 downto 24) + ); +\TimeCounter_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[24]_i_1_n_6\, + Q => TimeCounter_reg(25), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[24]_i_1_n_5\, + Q => TimeCounter_reg(26), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[24]_i_1_n_4\, + Q => TimeCounter_reg(27), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[28]_i_1_n_7\, + Q => TimeCounter_reg(28), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[28]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[24]_i_1_n_0\, + CO(3) => \NLW_TimeCounter_reg[28]_i_1_CO_UNCONNECTED\(3), + CO(2) => \TimeCounter_reg[28]_i_1_n_1\, + CO(1) => \TimeCounter_reg[28]_i_1_n_2\, + CO(0) => \TimeCounter_reg[28]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[28]_i_1_n_4\, + O(2) => \TimeCounter_reg[28]_i_1_n_5\, + O(1) => \TimeCounter_reg[28]_i_1_n_6\, + O(0) => \TimeCounter_reg[28]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(31 downto 28) + ); +\TimeCounter_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[28]_i_1_n_6\, + Q => TimeCounter_reg(29), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[0]_i_1_n_5\, + Q => TimeCounter_reg(2), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[28]_i_1_n_5\, + Q => TimeCounter_reg(30), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[28]_i_1_n_4\, + Q => TimeCounter_reg(31), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[0]_i_1_n_4\, + Q => TimeCounter_reg(3), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[4]_i_1_n_7\, + Q => TimeCounter_reg(4), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[0]_i_1_n_0\, + CO(3) => \TimeCounter_reg[4]_i_1_n_0\, + CO(2) => \TimeCounter_reg[4]_i_1_n_1\, + CO(1) => \TimeCounter_reg[4]_i_1_n_2\, + CO(0) => \TimeCounter_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[4]_i_1_n_4\, + O(2) => \TimeCounter_reg[4]_i_1_n_5\, + O(1) => \TimeCounter_reg[4]_i_1_n_6\, + O(0) => \TimeCounter_reg[4]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(7 downto 4) + ); +\TimeCounter_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[4]_i_1_n_6\, + Q => TimeCounter_reg(5), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[4]_i_1_n_5\, + Q => TimeCounter_reg(6), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[4]_i_1_n_4\, + Q => TimeCounter_reg(7), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[8]_i_1_n_7\, + Q => TimeCounter_reg(8), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[4]_i_1_n_0\, + CO(3) => \TimeCounter_reg[8]_i_1_n_0\, + CO(2) => \TimeCounter_reg[8]_i_1_n_1\, + CO(1) => \TimeCounter_reg[8]_i_1_n_2\, + CO(0) => \TimeCounter_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[8]_i_1_n_4\, + O(2) => \TimeCounter_reg[8]_i_1_n_5\, + O(1) => \TimeCounter_reg[8]_i_1_n_6\, + O(0) => \TimeCounter_reg[8]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(11 downto 8) + ); +\TimeCounter_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[8]_i_1_n_6\, + Q => TimeCounter_reg(9), + R => deadTimeCounterReset_reg_n_0 + ); +deadTimeCounterReset_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFE0000000E" + ) + port map ( + I0 => deadTimeCounterReset_i_2_n_0, + I1 => \FSM_onehot_lineconfig[6]_i_4_n_0\, + I2 => reset, + I3 => breaking_en, + I4 => deadTimeCounterReset_i_3_n_0, + I5 => deadTimeCounterReset_reg_n_0, + O => deadTimeCounterReset_i_1_n_0 + ); +deadTimeCounterReset_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + O => deadTimeCounterReset_i_2_n_0 + ); +deadTimeCounterReset_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000022220020" + ) + port map ( + I0 => deadTimeCounterReset_i_4_n_0, + I1 => deadTimeCounterReset_i_2_n_0, + I2 => deadTimeCounterReset_i_5_n_0, + I3 => deadTimeCounterReset_i_6_n_0, + I4 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I5 => deadTimeCounterReset_i_7_n_0, + O => deadTimeCounterReset_i_3_n_0 + ); +deadTimeCounterReset_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"555D555555555555" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I1 => deadTimeOK, + I2 => TKin1, + I3 => TKin1_triggered, + I4 => TKin0, + I5 => TKin0_triggered, + O => deadTimeCounterReset_i_4_n_0 + ); +deadTimeCounterReset_i_5: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => deadTimeOK, + I1 => ready, + I2 => er, + O => deadTimeCounterReset_i_5_n_0 + ); +deadTimeCounterReset_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"F777" + ) + port map ( + I0 => TKin0, + I1 => TKin1, + I2 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I3 => deadTimeCounterReset_reg_n_0, + O => deadTimeCounterReset_i_6_n_0 + ); +deadTimeCounterReset_i_7: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAA2AAAAAAAAAA" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I1 => TKin1, + I2 => TKin0, + I3 => deadTimeOK, + I4 => TKin0_triggered, + I5 => TKin1_triggered, + O => deadTimeCounterReset_i_7_n_0 + ); +deadTimeCounterReset_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => '1', + D => deadTimeCounterReset_i_1_n_0, + Q => deadTimeCounterReset_reg_n_0, + R => '0' + ); +deadTimeOK_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"0D" + ) + port map ( + I0 => sel, + I1 => deadTimeOK, + I2 => deadTimeCounterReset_reg_n_0, + O => deadTimeOK_i_1_n_0 + ); +deadTimeOK_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => deadTimeOK_i_1_n_0, + Q => deadTimeOK, + R => '0' + ); +key1_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"DDDDDDD0DDDDDDDD" + ) + port map ( + I0 => breaking_en, + I1 => TKin0, + I2 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I4 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I5 => key1_i_2_n_0, + O => key1_i_1_n_0 + ); +key1_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I3 => breaking_en, + O => key1_i_2_n_0 + ); +key1_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key1_reg_n_0, + Q => key1_prev, + R => '0' + ); +key1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key1_i_1_n_0, + Q => key1_reg_n_0, + R => '0' + ); +key2_i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => reset, + O => p_0_in + ); +key2_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAFFFFFFFC" + ) + port map ( + I0 => TKin1, + I1 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I4 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I5 => breaking_en, + O => key2_i_2_n_0 + ); +key2_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key2_reg_n_0, + Q => key2_prev, + R => '0' + ); +key2_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key2_i_2_n_0, + Q => key2_reg_n_0, + R => '0' + ); +key3_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAFFFFAAAAFCFF" + ) + port map ( + I0 => key3_reg_n_0, + I1 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I3 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I4 => reset, + I5 => breaking_en, + O => key3_i_1_n_0 + ); +key3_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key3_reg_n_0, + Q => key3_prev, + R => '0' + ); +key3_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => key3_i_1_n_0, + Q => key3_reg_n_0, + R => '0' + ); +key4_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAFFFFAAAAFFFC" + ) + port map ( + I0 => key4_reg_n_0, + I1 => key3, + I2 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I4 => reset, + I5 => breaking_en, + O => key4_i_1_n_0 + ); +key4_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + O => key3 + ); +key4_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key4_reg_n_0, + Q => key4_prev, + R => '0' + ); +key4_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => key4_i_1_n_0, + Q => key4_reg_n_0, + R => '0' + ); +\ltOp__15_carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \ltOp__15_carry_n_0\, + CO(2) => \ltOp__15_carry_n_1\, + CO(1) => \ltOp__15_carry_n_2\, + CO(0) => \ltOp__15_carry_n_3\, + CYINIT => '0', + DI(3) => \ltOp__15_carry_i_1_n_0\, + DI(2) => \ltOp__15_carry_i_2_n_0\, + DI(1) => \ltOp__15_carry_i_3_n_0\, + DI(0) => \ltOp__15_carry_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__15_carry_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__15_carry_i_5_n_0\, + S(2) => \ltOp__15_carry_i_6_n_0\, + S(1) => \ltOp__15_carry_i_7_n_0\, + S(0) => \ltOp__15_carry_i_8_n_0\ + ); +\ltOp__15_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__15_carry_n_0\, + CO(3) => \ltOp__15_carry__0_n_0\, + CO(2) => \ltOp__15_carry__0_n_1\, + CO(1) => \ltOp__15_carry__0_n_2\, + CO(0) => \ltOp__15_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp__15_carry__0_i_1_n_0\, + DI(2) => \ltOp__15_carry__0_i_2_n_0\, + DI(1) => \ltOp__15_carry__0_i_3_n_0\, + DI(0) => \ltOp__15_carry__0_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__15_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__15_carry__0_i_5_n_0\, + S(2) => \ltOp__15_carry__0_i_6_n_0\, + S(1) => \ltOp__15_carry__0_i_7_n_0\, + S(0) => \ltOp__15_carry__0_i_8_n_0\ + ); +\ltOp__15_carry__0_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(15), + I1 => minTimeCounter_low_reg(15), + I2 => minTime(14), + I3 => minTimeCounter_low_reg(14), + O => \ltOp__15_carry__0_i_1_n_0\ + ); +\ltOp__15_carry__0_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(13), + I1 => minTimeCounter_low_reg(13), + I2 => minTime(12), + I3 => minTimeCounter_low_reg(12), + O => \ltOp__15_carry__0_i_2_n_0\ + ); +\ltOp__15_carry__0_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(11), + I1 => minTimeCounter_low_reg(11), + I2 => minTime(10), + I3 => minTimeCounter_low_reg(10), + O => \ltOp__15_carry__0_i_3_n_0\ + ); +\ltOp__15_carry__0_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(9), + I1 => minTimeCounter_low_reg(9), + I2 => minTime(8), + I3 => minTimeCounter_low_reg(8), + O => \ltOp__15_carry__0_i_4_n_0\ + ); +\ltOp__15_carry__0_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(15), + I1 => minTime(15), + I2 => minTimeCounter_low_reg(14), + I3 => minTime(14), + O => \ltOp__15_carry__0_i_5_n_0\ + ); +\ltOp__15_carry__0_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(13), + I1 => minTime(13), + I2 => minTimeCounter_low_reg(12), + I3 => minTime(12), + O => \ltOp__15_carry__0_i_6_n_0\ + ); +\ltOp__15_carry__0_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(11), + I1 => minTime(11), + I2 => minTimeCounter_low_reg(10), + I3 => minTime(10), + O => \ltOp__15_carry__0_i_7_n_0\ + ); +\ltOp__15_carry__0_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(9), + I1 => minTime(9), + I2 => minTimeCounter_low_reg(8), + I3 => minTime(8), + O => \ltOp__15_carry__0_i_8_n_0\ + ); +\ltOp__15_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__15_carry__0_n_0\, + CO(3) => \ltOp__15_carry__1_n_0\, + CO(2) => \ltOp__15_carry__1_n_1\, + CO(1) => \ltOp__15_carry__1_n_2\, + CO(0) => \ltOp__15_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp__15_carry__1_i_1_n_0\, + DI(2) => \ltOp__15_carry__1_i_2_n_0\, + DI(1) => \ltOp__15_carry__1_i_3_n_0\, + DI(0) => \ltOp__15_carry__1_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__15_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__15_carry__1_i_5_n_0\, + S(2) => \ltOp__15_carry__1_i_6_n_0\, + S(1) => \ltOp__15_carry__1_i_7_n_0\, + S(0) => \ltOp__15_carry__1_i_8_n_0\ + ); +\ltOp__15_carry__1_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(23), + I1 => minTimeCounter_low_reg(23), + I2 => minTime(22), + I3 => minTimeCounter_low_reg(22), + O => \ltOp__15_carry__1_i_1_n_0\ + ); +\ltOp__15_carry__1_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(21), + I1 => minTimeCounter_low_reg(21), + I2 => minTime(20), + I3 => minTimeCounter_low_reg(20), + O => \ltOp__15_carry__1_i_2_n_0\ + ); +\ltOp__15_carry__1_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(19), + I1 => minTimeCounter_low_reg(19), + I2 => minTime(18), + I3 => minTimeCounter_low_reg(18), + O => \ltOp__15_carry__1_i_3_n_0\ + ); +\ltOp__15_carry__1_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(17), + I1 => minTimeCounter_low_reg(17), + I2 => minTime(16), + I3 => minTimeCounter_low_reg(16), + O => \ltOp__15_carry__1_i_4_n_0\ + ); +\ltOp__15_carry__1_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(23), + I1 => minTime(23), + I2 => minTimeCounter_low_reg(22), + I3 => minTime(22), + O => \ltOp__15_carry__1_i_5_n_0\ + ); +\ltOp__15_carry__1_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(21), + I1 => minTime(21), + I2 => minTimeCounter_low_reg(20), + I3 => minTime(20), + O => \ltOp__15_carry__1_i_6_n_0\ + ); +\ltOp__15_carry__1_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(19), + I1 => minTime(19), + I2 => minTimeCounter_low_reg(18), + I3 => minTime(18), + O => \ltOp__15_carry__1_i_7_n_0\ + ); +\ltOp__15_carry__1_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(17), + I1 => minTime(17), + I2 => minTimeCounter_low_reg(16), + I3 => minTime(16), + O => \ltOp__15_carry__1_i_8_n_0\ + ); +\ltOp__15_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__15_carry__1_n_0\, + CO(3) => \ltOp__15_carry__2_n_0\, + CO(2) => \ltOp__15_carry__2_n_1\, + CO(1) => \ltOp__15_carry__2_n_2\, + CO(0) => \ltOp__15_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp__15_carry__2_i_1_n_0\, + DI(2) => \ltOp__15_carry__2_i_2_n_0\, + DI(1) => \ltOp__15_carry__2_i_3_n_0\, + DI(0) => \ltOp__15_carry__2_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__15_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__15_carry__2_i_5_n_0\, + S(2) => \ltOp__15_carry__2_i_6_n_0\, + S(1) => \ltOp__15_carry__2_i_7_n_0\, + S(0) => \ltOp__15_carry__2_i_8_n_0\ + ); +\ltOp__15_carry__2_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(31), + I1 => minTimeCounter_low_reg(31), + I2 => minTime(30), + I3 => minTimeCounter_low_reg(30), + O => \ltOp__15_carry__2_i_1_n_0\ + ); +\ltOp__15_carry__2_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(29), + I1 => minTimeCounter_low_reg(29), + I2 => minTime(28), + I3 => minTimeCounter_low_reg(28), + O => \ltOp__15_carry__2_i_2_n_0\ + ); +\ltOp__15_carry__2_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(27), + I1 => minTimeCounter_low_reg(27), + I2 => minTime(26), + I3 => minTimeCounter_low_reg(26), + O => \ltOp__15_carry__2_i_3_n_0\ + ); +\ltOp__15_carry__2_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(25), + I1 => minTimeCounter_low_reg(25), + I2 => minTime(24), + I3 => minTimeCounter_low_reg(24), + O => \ltOp__15_carry__2_i_4_n_0\ + ); +\ltOp__15_carry__2_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(31), + I1 => minTime(31), + I2 => minTimeCounter_low_reg(30), + I3 => minTime(30), + O => \ltOp__15_carry__2_i_5_n_0\ + ); +\ltOp__15_carry__2_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(29), + I1 => minTime(29), + I2 => minTimeCounter_low_reg(28), + I3 => minTime(28), + O => \ltOp__15_carry__2_i_6_n_0\ + ); +\ltOp__15_carry__2_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(27), + I1 => minTime(27), + I2 => minTimeCounter_low_reg(26), + I3 => minTime(26), + O => \ltOp__15_carry__2_i_7_n_0\ + ); +\ltOp__15_carry__2_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(25), + I1 => minTime(25), + I2 => minTimeCounter_low_reg(24), + I3 => minTime(24), + O => \ltOp__15_carry__2_i_8_n_0\ + ); +\ltOp__15_carry_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(7), + I1 => minTimeCounter_low_reg(7), + I2 => minTime(6), + I3 => minTimeCounter_low_reg(6), + O => \ltOp__15_carry_i_1_n_0\ + ); +\ltOp__15_carry_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(5), + I1 => minTimeCounter_low_reg(5), + I2 => minTime(4), + I3 => minTimeCounter_low_reg(4), + O => \ltOp__15_carry_i_2_n_0\ + ); +\ltOp__15_carry_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(3), + I1 => minTimeCounter_low_reg(3), + I2 => minTime(2), + I3 => minTimeCounter_low_reg(2), + O => \ltOp__15_carry_i_3_n_0\ + ); +\ltOp__15_carry_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(1), + I1 => minTimeCounter_low_reg(1), + I2 => minTime(0), + I3 => minTimeCounter_low_reg(0), + O => \ltOp__15_carry_i_4_n_0\ + ); +\ltOp__15_carry_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(7), + I1 => minTime(7), + I2 => minTimeCounter_low_reg(6), + I3 => minTime(6), + O => \ltOp__15_carry_i_5_n_0\ + ); +\ltOp__15_carry_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(5), + I1 => minTime(5), + I2 => minTimeCounter_low_reg(4), + I3 => minTime(4), + O => \ltOp__15_carry_i_6_n_0\ + ); +\ltOp__15_carry_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(3), + I1 => minTime(3), + I2 => minTimeCounter_low_reg(2), + I3 => minTime(2), + O => \ltOp__15_carry_i_7_n_0\ + ); +\ltOp__15_carry_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(1), + I1 => minTime(1), + I2 => minTimeCounter_low_reg(0), + I3 => minTime(0), + O => \ltOp__15_carry_i_8_n_0\ + ); +\ltOp__31_carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \ltOp__31_carry_n_0\, + CO(2) => \ltOp__31_carry_n_1\, + CO(1) => \ltOp__31_carry_n_2\, + CO(0) => \ltOp__31_carry_n_3\, + CYINIT => '0', + DI(3) => \ltOp__31_carry_i_1_n_0\, + DI(2) => \ltOp__31_carry_i_2_n_0\, + DI(1) => \ltOp__31_carry_i_3_n_0\, + DI(0) => \ltOp__31_carry_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__31_carry_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__31_carry_i_5_n_0\, + S(2) => \ltOp__31_carry_i_6_n_0\, + S(1) => \ltOp__31_carry_i_7_n_0\, + S(0) => \ltOp__31_carry_i_8_n_0\ + ); +\ltOp__31_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__31_carry_n_0\, + CO(3) => \ltOp__31_carry__0_n_0\, + CO(2) => \ltOp__31_carry__0_n_1\, + CO(1) => \ltOp__31_carry__0_n_2\, + CO(0) => \ltOp__31_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp__31_carry_i_1__0_n_0\, + DI(2) => \ltOp__31_carry_i_2__0_n_0\, + DI(1) => \ltOp__31_carry_i_3__0_n_0\, + DI(0) => \ltOp__31_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp__31_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__31_carry_i_5__0_n_0\, + S(2) => \ltOp__31_carry_i_6__0_n_0\, + S(1) => \ltOp__31_carry_i_7__0_n_0\, + S(0) => \ltOp__31_carry_i_8__0_n_0\ + ); +\ltOp__31_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__31_carry__0_n_0\, + CO(3) => \ltOp__31_carry__1_n_0\, + CO(2) => \ltOp__31_carry__1_n_1\, + CO(1) => \ltOp__31_carry__1_n_2\, + CO(0) => \ltOp__31_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp__31_carry_i_1__1_n_0\, + DI(2) => \ltOp__31_carry_i_2__1_n_0\, + DI(1) => \ltOp__31_carry_i_3__1_n_0\, + DI(0) => \ltOp__31_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp__31_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__31_carry_i_5__1_n_0\, + S(2) => \ltOp__31_carry_i_6__1_n_0\, + S(1) => \ltOp__31_carry_i_7__1_n_0\, + S(0) => \ltOp__31_carry_i_8__1_n_0\ + ); +\ltOp__31_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__31_carry__1_n_0\, + CO(3) => \ltOp__31_carry__2_n_0\, + CO(2) => \ltOp__31_carry__2_n_1\, + CO(1) => \ltOp__31_carry__2_n_2\, + CO(0) => \ltOp__31_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp__31_carry_i_1__2_n_0\, + DI(2) => \ltOp__31_carry_i_2__2_n_0\, + DI(1) => \ltOp__31_carry_i_3__2_n_0\, + DI(0) => \ltOp__31_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp__31_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__31_carry_i_5__2_n_0\, + S(2) => \ltOp__31_carry_i_6__2_n_0\, + S(1) => \ltOp__31_carry_i_7__2_n_0\, + S(0) => \ltOp__31_carry_i_8__2_n_0\ + ); +\ltOp__31_carry_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(7), + I1 => minTimeCounter_high_reg(7), + I2 => minTime(6), + I3 => minTimeCounter_high_reg(6), + O => \ltOp__31_carry_i_1_n_0\ + ); +\ltOp__31_carry_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(15), + I1 => minTimeCounter_high_reg(15), + I2 => minTime(14), + I3 => minTimeCounter_high_reg(14), + O => \ltOp__31_carry_i_1__0_n_0\ + ); +\ltOp__31_carry_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(23), + I1 => minTimeCounter_high_reg(23), + I2 => minTime(22), + I3 => minTimeCounter_high_reg(22), + O => \ltOp__31_carry_i_1__1_n_0\ + ); +\ltOp__31_carry_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(31), + I1 => minTimeCounter_high_reg(31), + I2 => minTime(30), + I3 => minTimeCounter_high_reg(30), + O => \ltOp__31_carry_i_1__2_n_0\ + ); +\ltOp__31_carry_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(5), + I1 => minTimeCounter_high_reg(5), + I2 => minTime(4), + I3 => minTimeCounter_high_reg(4), + O => \ltOp__31_carry_i_2_n_0\ + ); +\ltOp__31_carry_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(13), + I1 => minTimeCounter_high_reg(13), + I2 => minTime(12), + I3 => minTimeCounter_high_reg(12), + O => \ltOp__31_carry_i_2__0_n_0\ + ); +\ltOp__31_carry_i_2__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(21), + I1 => minTimeCounter_high_reg(21), + I2 => minTime(20), + I3 => minTimeCounter_high_reg(20), + O => \ltOp__31_carry_i_2__1_n_0\ + ); +\ltOp__31_carry_i_2__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(29), + I1 => minTimeCounter_high_reg(29), + I2 => minTime(28), + I3 => minTimeCounter_high_reg(28), + O => \ltOp__31_carry_i_2__2_n_0\ + ); +\ltOp__31_carry_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(3), + I1 => minTimeCounter_high_reg(3), + I2 => minTime(2), + I3 => minTimeCounter_high_reg(2), + O => \ltOp__31_carry_i_3_n_0\ + ); +\ltOp__31_carry_i_3__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(11), + I1 => minTimeCounter_high_reg(11), + I2 => minTime(10), + I3 => minTimeCounter_high_reg(10), + O => \ltOp__31_carry_i_3__0_n_0\ + ); +\ltOp__31_carry_i_3__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(19), + I1 => minTimeCounter_high_reg(19), + I2 => minTime(18), + I3 => minTimeCounter_high_reg(18), + O => \ltOp__31_carry_i_3__1_n_0\ + ); +\ltOp__31_carry_i_3__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(27), + I1 => minTimeCounter_high_reg(27), + I2 => minTime(26), + I3 => minTimeCounter_high_reg(26), + O => \ltOp__31_carry_i_3__2_n_0\ + ); +\ltOp__31_carry_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(1), + I1 => minTimeCounter_high_reg(1), + I2 => minTime(0), + I3 => minTimeCounter_high_reg(0), + O => \ltOp__31_carry_i_4_n_0\ + ); +\ltOp__31_carry_i_4__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(9), + I1 => minTimeCounter_high_reg(9), + I2 => minTime(8), + I3 => minTimeCounter_high_reg(8), + O => \ltOp__31_carry_i_4__0_n_0\ + ); +\ltOp__31_carry_i_4__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(17), + I1 => minTimeCounter_high_reg(17), + I2 => minTime(16), + I3 => minTimeCounter_high_reg(16), + O => \ltOp__31_carry_i_4__1_n_0\ + ); +\ltOp__31_carry_i_4__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(25), + I1 => minTimeCounter_high_reg(25), + I2 => minTime(24), + I3 => minTimeCounter_high_reg(24), + O => \ltOp__31_carry_i_4__2_n_0\ + ); +\ltOp__31_carry_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(7), + I1 => minTime(7), + I2 => minTimeCounter_high_reg(6), + I3 => minTime(6), + O => \ltOp__31_carry_i_5_n_0\ + ); +\ltOp__31_carry_i_5__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(15), + I1 => minTime(15), + I2 => minTimeCounter_high_reg(14), + I3 => minTime(14), + O => \ltOp__31_carry_i_5__0_n_0\ + ); +\ltOp__31_carry_i_5__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(23), + I1 => minTime(23), + I2 => minTimeCounter_high_reg(22), + I3 => minTime(22), + O => \ltOp__31_carry_i_5__1_n_0\ + ); +\ltOp__31_carry_i_5__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(31), + I1 => minTime(31), + I2 => minTimeCounter_high_reg(30), + I3 => minTime(30), + O => \ltOp__31_carry_i_5__2_n_0\ + ); +\ltOp__31_carry_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(5), + I1 => minTime(5), + I2 => minTimeCounter_high_reg(4), + I3 => minTime(4), + O => \ltOp__31_carry_i_6_n_0\ + ); +\ltOp__31_carry_i_6__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(13), + I1 => minTime(13), + I2 => minTimeCounter_high_reg(12), + I3 => minTime(12), + O => \ltOp__31_carry_i_6__0_n_0\ + ); +\ltOp__31_carry_i_6__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(21), + I1 => minTime(21), + I2 => minTimeCounter_high_reg(20), + I3 => minTime(20), + O => \ltOp__31_carry_i_6__1_n_0\ + ); +\ltOp__31_carry_i_6__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(29), + I1 => minTime(29), + I2 => minTimeCounter_high_reg(28), + I3 => minTime(28), + O => \ltOp__31_carry_i_6__2_n_0\ + ); +\ltOp__31_carry_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(3), + I1 => minTime(3), + I2 => minTimeCounter_high_reg(2), + I3 => minTime(2), + O => \ltOp__31_carry_i_7_n_0\ + ); +\ltOp__31_carry_i_7__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(11), + I1 => minTime(11), + I2 => minTimeCounter_high_reg(10), + I3 => minTime(10), + O => \ltOp__31_carry_i_7__0_n_0\ + ); +\ltOp__31_carry_i_7__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(19), + I1 => minTime(19), + I2 => minTimeCounter_high_reg(18), + I3 => minTime(18), + O => \ltOp__31_carry_i_7__1_n_0\ + ); +\ltOp__31_carry_i_7__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(27), + I1 => minTime(27), + I2 => minTimeCounter_high_reg(26), + I3 => minTime(26), + O => \ltOp__31_carry_i_7__2_n_0\ + ); +\ltOp__31_carry_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(1), + I1 => minTime(1), + I2 => minTimeCounter_high_reg(0), + I3 => minTime(0), + O => \ltOp__31_carry_i_8_n_0\ + ); +\ltOp__31_carry_i_8__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(9), + I1 => minTime(9), + I2 => minTimeCounter_high_reg(8), + I3 => minTime(8), + O => \ltOp__31_carry_i_8__0_n_0\ + ); +\ltOp__31_carry_i_8__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(17), + I1 => minTime(17), + I2 => minTimeCounter_high_reg(16), + I3 => minTime(16), + O => \ltOp__31_carry_i_8__1_n_0\ + ); +\ltOp__31_carry_i_8__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(25), + I1 => minTime(25), + I2 => minTimeCounter_high_reg(24), + I3 => minTime(24), + O => \ltOp__31_carry_i_8__2_n_0\ + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry__0_i_1_n_0\, + DI(2) => \ltOp_carry__0_i_2_n_0\, + DI(1) => \ltOp_carry__0_i_3_n_0\, + DI(0) => \ltOp_carry__0_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry__0_i_5_n_0\, + S(2) => \ltOp_carry__0_i_6_n_0\, + S(1) => \ltOp_carry__0_i_7_n_0\, + S(0) => \ltOp_carry__0_i_8_n_0\ + ); +\ltOp_carry__0_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(15), + I1 => TimeCounter_reg(15), + I2 => deadTime(14), + I3 => TimeCounter_reg(14), + O => \ltOp_carry__0_i_1_n_0\ + ); +\ltOp_carry__0_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(13), + I1 => TimeCounter_reg(13), + I2 => deadTime(12), + I3 => TimeCounter_reg(12), + O => \ltOp_carry__0_i_2_n_0\ + ); +\ltOp_carry__0_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(11), + I1 => TimeCounter_reg(11), + I2 => deadTime(10), + I3 => TimeCounter_reg(10), + O => \ltOp_carry__0_i_3_n_0\ + ); +\ltOp_carry__0_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(9), + I1 => TimeCounter_reg(9), + I2 => deadTime(8), + I3 => TimeCounter_reg(8), + O => \ltOp_carry__0_i_4_n_0\ + ); +\ltOp_carry__0_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(15), + I1 => deadTime(15), + I2 => TimeCounter_reg(14), + I3 => deadTime(14), + O => \ltOp_carry__0_i_5_n_0\ + ); +\ltOp_carry__0_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(13), + I1 => deadTime(13), + I2 => TimeCounter_reg(12), + I3 => deadTime(12), + O => \ltOp_carry__0_i_6_n_0\ + ); +\ltOp_carry__0_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(11), + I1 => deadTime(11), + I2 => TimeCounter_reg(10), + I3 => deadTime(10), + O => \ltOp_carry__0_i_7_n_0\ + ); +\ltOp_carry__0_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(9), + I1 => deadTime(9), + I2 => TimeCounter_reg(8), + I3 => deadTime(8), + O => \ltOp_carry__0_i_8_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry__1_i_1_n_0\, + DI(2) => \ltOp_carry__1_i_2_n_0\, + DI(1) => \ltOp_carry__1_i_3_n_0\, + DI(0) => \ltOp_carry__1_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry__1_i_5_n_0\, + S(2) => \ltOp_carry__1_i_6_n_0\, + S(1) => \ltOp_carry__1_i_7_n_0\, + S(0) => \ltOp_carry__1_i_8_n_0\ + ); +\ltOp_carry__1_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(23), + I1 => TimeCounter_reg(23), + I2 => deadTime(22), + I3 => TimeCounter_reg(22), + O => \ltOp_carry__1_i_1_n_0\ + ); +\ltOp_carry__1_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(21), + I1 => TimeCounter_reg(21), + I2 => deadTime(20), + I3 => TimeCounter_reg(20), + O => \ltOp_carry__1_i_2_n_0\ + ); +\ltOp_carry__1_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(19), + I1 => TimeCounter_reg(19), + I2 => deadTime(18), + I3 => TimeCounter_reg(18), + O => \ltOp_carry__1_i_3_n_0\ + ); +\ltOp_carry__1_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(17), + I1 => TimeCounter_reg(17), + I2 => deadTime(16), + I3 => TimeCounter_reg(16), + O => \ltOp_carry__1_i_4_n_0\ + ); +\ltOp_carry__1_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(23), + I1 => deadTime(23), + I2 => TimeCounter_reg(22), + I3 => deadTime(22), + O => \ltOp_carry__1_i_5_n_0\ + ); +\ltOp_carry__1_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(21), + I1 => deadTime(21), + I2 => TimeCounter_reg(20), + I3 => deadTime(20), + O => \ltOp_carry__1_i_6_n_0\ + ); +\ltOp_carry__1_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(19), + I1 => deadTime(19), + I2 => TimeCounter_reg(18), + I3 => deadTime(18), + O => \ltOp_carry__1_i_7_n_0\ + ); +\ltOp_carry__1_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(17), + I1 => deadTime(17), + I2 => TimeCounter_reg(16), + I3 => deadTime(16), + O => \ltOp_carry__1_i_8_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => sel, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry__2_i_1_n_0\, + DI(2) => \ltOp_carry__2_i_2_n_0\, + DI(1) => \ltOp_carry__2_i_3_n_0\, + DI(0) => \ltOp_carry__2_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry__2_i_5_n_0\, + S(2) => \ltOp_carry__2_i_6_n_0\, + S(1) => \ltOp_carry__2_i_7_n_0\, + S(0) => \ltOp_carry__2_i_8_n_0\ + ); +\ltOp_carry__2_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(31), + I1 => TimeCounter_reg(31), + I2 => deadTime(30), + I3 => TimeCounter_reg(30), + O => \ltOp_carry__2_i_1_n_0\ + ); +\ltOp_carry__2_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(29), + I1 => TimeCounter_reg(29), + I2 => deadTime(28), + I3 => TimeCounter_reg(28), + O => \ltOp_carry__2_i_2_n_0\ + ); +\ltOp_carry__2_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(27), + I1 => TimeCounter_reg(27), + I2 => deadTime(26), + I3 => TimeCounter_reg(26), + O => \ltOp_carry__2_i_3_n_0\ + ); +\ltOp_carry__2_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(25), + I1 => TimeCounter_reg(25), + I2 => deadTime(24), + I3 => TimeCounter_reg(24), + O => \ltOp_carry__2_i_4_n_0\ + ); +\ltOp_carry__2_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(31), + I1 => deadTime(31), + I2 => TimeCounter_reg(30), + I3 => deadTime(30), + O => \ltOp_carry__2_i_5_n_0\ + ); +\ltOp_carry__2_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(29), + I1 => deadTime(29), + I2 => TimeCounter_reg(28), + I3 => deadTime(28), + O => \ltOp_carry__2_i_6_n_0\ + ); +\ltOp_carry__2_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(27), + I1 => deadTime(27), + I2 => TimeCounter_reg(26), + I3 => deadTime(26), + O => \ltOp_carry__2_i_7_n_0\ + ); +\ltOp_carry__2_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(25), + I1 => deadTime(25), + I2 => TimeCounter_reg(24), + I3 => deadTime(24), + O => \ltOp_carry__2_i_8_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(7), + I1 => TimeCounter_reg(7), + I2 => deadTime(6), + I3 => TimeCounter_reg(6), + O => ltOp_carry_i_1_n_0 + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(5), + I1 => TimeCounter_reg(5), + I2 => deadTime(4), + I3 => TimeCounter_reg(4), + O => ltOp_carry_i_2_n_0 + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(3), + I1 => TimeCounter_reg(3), + I2 => deadTime(2), + I3 => TimeCounter_reg(2), + O => ltOp_carry_i_3_n_0 + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(1), + I1 => TimeCounter_reg(1), + I2 => deadTime(0), + I3 => TimeCounter_reg(0), + O => ltOp_carry_i_4_n_0 + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(7), + I1 => deadTime(7), + I2 => TimeCounter_reg(6), + I3 => deadTime(6), + O => ltOp_carry_i_5_n_0 + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(5), + I1 => deadTime(5), + I2 => TimeCounter_reg(4), + I3 => deadTime(4), + O => ltOp_carry_i_6_n_0 + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(3), + I1 => deadTime(3), + I2 => TimeCounter_reg(2), + I3 => deadTime(2), + O => ltOp_carry_i_7_n_0 + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(1), + I1 => deadTime(1), + I2 => TimeCounter_reg(0), + I3 => deadTime(0), + O => ltOp_carry_i_8_n_0 + ); +\minTimeCounter_high[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000022222F22" + ) + port map ( + I0 => key1_prev, + I1 => key1_reg_n_0, + I2 => key2_reg_n_0, + I3 => key2_prev, + I4 => breaking_en, + I5 => reset, + O => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high[0]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \ltOp__31_carry__2_n_0\, + I1 => reset, + O => minTimeCounter_high + ); +\minTimeCounter_high[0]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => minTimeCounter_high_reg(0), + O => \minTimeCounter_high[0]_i_4_n_0\ + ); +\minTimeCounter_high_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[0]_i_3_n_7\, + Q => minTimeCounter_high_reg(0), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[0]_i_3\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \minTimeCounter_high_reg[0]_i_3_n_0\, + CO(2) => \minTimeCounter_high_reg[0]_i_3_n_1\, + CO(1) => \minTimeCounter_high_reg[0]_i_3_n_2\, + CO(0) => \minTimeCounter_high_reg[0]_i_3_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \minTimeCounter_high_reg[0]_i_3_n_4\, + O(2) => \minTimeCounter_high_reg[0]_i_3_n_5\, + O(1) => \minTimeCounter_high_reg[0]_i_3_n_6\, + O(0) => \minTimeCounter_high_reg[0]_i_3_n_7\, + S(3 downto 1) => minTimeCounter_high_reg(3 downto 1), + S(0) => \minTimeCounter_high[0]_i_4_n_0\ + ); +\minTimeCounter_high_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[8]_i_1_n_5\, + Q => minTimeCounter_high_reg(10), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[8]_i_1_n_4\, + Q => minTimeCounter_high_reg(11), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[12]_i_1_n_7\, + Q => minTimeCounter_high_reg(12), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[8]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[12]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[12]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[12]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[12]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[12]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[12]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[12]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[12]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(15 downto 12) + ); +\minTimeCounter_high_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[12]_i_1_n_6\, + Q => minTimeCounter_high_reg(13), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[12]_i_1_n_5\, + Q => minTimeCounter_high_reg(14), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[12]_i_1_n_4\, + Q => minTimeCounter_high_reg(15), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[16]_i_1_n_7\, + Q => minTimeCounter_high_reg(16), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[16]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[12]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[16]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[16]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[16]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[16]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[16]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[16]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[16]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[16]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(19 downto 16) + ); +\minTimeCounter_high_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[16]_i_1_n_6\, + Q => minTimeCounter_high_reg(17), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[16]_i_1_n_5\, + Q => minTimeCounter_high_reg(18), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[16]_i_1_n_4\, + Q => minTimeCounter_high_reg(19), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[0]_i_3_n_6\, + Q => minTimeCounter_high_reg(1), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[20]_i_1_n_7\, + Q => minTimeCounter_high_reg(20), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[20]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[16]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[20]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[20]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[20]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[20]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[20]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[20]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[20]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[20]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(23 downto 20) + ); +\minTimeCounter_high_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[20]_i_1_n_6\, + Q => minTimeCounter_high_reg(21), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[20]_i_1_n_5\, + Q => minTimeCounter_high_reg(22), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[20]_i_1_n_4\, + Q => minTimeCounter_high_reg(23), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[24]_i_1_n_7\, + Q => minTimeCounter_high_reg(24), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[24]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[20]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[24]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[24]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[24]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[24]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[24]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[24]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[24]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[24]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(27 downto 24) + ); +\minTimeCounter_high_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[24]_i_1_n_6\, + Q => minTimeCounter_high_reg(25), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[24]_i_1_n_5\, + Q => minTimeCounter_high_reg(26), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[24]_i_1_n_4\, + Q => minTimeCounter_high_reg(27), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[28]_i_1_n_7\, + Q => minTimeCounter_high_reg(28), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[28]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[24]_i_1_n_0\, + CO(3) => \NLW_minTimeCounter_high_reg[28]_i_1_CO_UNCONNECTED\(3), + CO(2) => \minTimeCounter_high_reg[28]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[28]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[28]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[28]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[28]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[28]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[28]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(31 downto 28) + ); +\minTimeCounter_high_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[28]_i_1_n_6\, + Q => minTimeCounter_high_reg(29), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[0]_i_3_n_5\, + Q => minTimeCounter_high_reg(2), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[28]_i_1_n_5\, + Q => minTimeCounter_high_reg(30), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[28]_i_1_n_4\, + Q => minTimeCounter_high_reg(31), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[0]_i_3_n_4\, + Q => minTimeCounter_high_reg(3), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[4]_i_1_n_7\, + Q => minTimeCounter_high_reg(4), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[0]_i_3_n_0\, + CO(3) => \minTimeCounter_high_reg[4]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[4]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[4]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[4]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[4]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[4]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[4]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(7 downto 4) + ); +\minTimeCounter_high_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[4]_i_1_n_6\, + Q => minTimeCounter_high_reg(5), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[4]_i_1_n_5\, + Q => minTimeCounter_high_reg(6), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[4]_i_1_n_4\, + Q => minTimeCounter_high_reg(7), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[8]_i_1_n_7\, + Q => minTimeCounter_high_reg(8), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[4]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[8]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[8]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[8]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[8]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[8]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[8]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[8]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(11 downto 8) + ); +\minTimeCounter_high_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[8]_i_1_n_6\, + Q => minTimeCounter_high_reg(9), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_low[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000440F" + ) + port map ( + I0 => key2_reg_n_0, + I1 => key2_prev, + I2 => \minTimeCounter_low[0]_i_4_n_0\, + I3 => breaking_en, + I4 => reset, + O => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low[0]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \ltOp__15_carry__2_n_0\, + I1 => reset, + O => minTimeCounter_low + ); +\minTimeCounter_low[0]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"D0DD" + ) + port map ( + I0 => key4_prev, + I1 => key4_reg_n_0, + I2 => key3_reg_n_0, + I3 => key3_prev, + O => \minTimeCounter_low[0]_i_4_n_0\ + ); +\minTimeCounter_low[0]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => minTimeCounter_low_reg(0), + O => \minTimeCounter_low[0]_i_5_n_0\ + ); +\minTimeCounter_low_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[0]_i_3_n_7\, + Q => minTimeCounter_low_reg(0), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[0]_i_3\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \minTimeCounter_low_reg[0]_i_3_n_0\, + CO(2) => \minTimeCounter_low_reg[0]_i_3_n_1\, + CO(1) => \minTimeCounter_low_reg[0]_i_3_n_2\, + CO(0) => \minTimeCounter_low_reg[0]_i_3_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \minTimeCounter_low_reg[0]_i_3_n_4\, + O(2) => \minTimeCounter_low_reg[0]_i_3_n_5\, + O(1) => \minTimeCounter_low_reg[0]_i_3_n_6\, + O(0) => \minTimeCounter_low_reg[0]_i_3_n_7\, + S(3 downto 1) => minTimeCounter_low_reg(3 downto 1), + S(0) => \minTimeCounter_low[0]_i_5_n_0\ + ); +\minTimeCounter_low_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[8]_i_1_n_5\, + Q => minTimeCounter_low_reg(10), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[8]_i_1_n_4\, + Q => minTimeCounter_low_reg(11), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[12]_i_1_n_7\, + Q => minTimeCounter_low_reg(12), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[8]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[12]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[12]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[12]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[12]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[12]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[12]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[12]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[12]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(15 downto 12) + ); +\minTimeCounter_low_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[12]_i_1_n_6\, + Q => minTimeCounter_low_reg(13), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[12]_i_1_n_5\, + Q => minTimeCounter_low_reg(14), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[12]_i_1_n_4\, + Q => minTimeCounter_low_reg(15), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[16]_i_1_n_7\, + Q => minTimeCounter_low_reg(16), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[16]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[12]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[16]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[16]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[16]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[16]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[16]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[16]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[16]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[16]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(19 downto 16) + ); +\minTimeCounter_low_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[16]_i_1_n_6\, + Q => minTimeCounter_low_reg(17), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[16]_i_1_n_5\, + Q => minTimeCounter_low_reg(18), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[16]_i_1_n_4\, + Q => minTimeCounter_low_reg(19), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[0]_i_3_n_6\, + Q => minTimeCounter_low_reg(1), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[20]_i_1_n_7\, + Q => minTimeCounter_low_reg(20), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[20]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[16]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[20]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[20]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[20]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[20]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[20]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[20]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[20]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[20]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(23 downto 20) + ); +\minTimeCounter_low_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[20]_i_1_n_6\, + Q => minTimeCounter_low_reg(21), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[20]_i_1_n_5\, + Q => minTimeCounter_low_reg(22), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[20]_i_1_n_4\, + Q => minTimeCounter_low_reg(23), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[24]_i_1_n_7\, + Q => minTimeCounter_low_reg(24), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[24]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[20]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[24]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[24]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[24]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[24]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[24]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[24]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[24]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[24]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(27 downto 24) + ); +\minTimeCounter_low_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[24]_i_1_n_6\, + Q => minTimeCounter_low_reg(25), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[24]_i_1_n_5\, + Q => minTimeCounter_low_reg(26), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[24]_i_1_n_4\, + Q => minTimeCounter_low_reg(27), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[28]_i_1_n_7\, + Q => minTimeCounter_low_reg(28), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[28]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[24]_i_1_n_0\, + CO(3) => \NLW_minTimeCounter_low_reg[28]_i_1_CO_UNCONNECTED\(3), + CO(2) => \minTimeCounter_low_reg[28]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[28]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[28]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[28]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[28]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[28]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[28]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(31 downto 28) + ); +\minTimeCounter_low_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[28]_i_1_n_6\, + Q => minTimeCounter_low_reg(29), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[0]_i_3_n_5\, + Q => minTimeCounter_low_reg(2), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[28]_i_1_n_5\, + Q => minTimeCounter_low_reg(30), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[28]_i_1_n_4\, + Q => minTimeCounter_low_reg(31), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[0]_i_3_n_4\, + Q => minTimeCounter_low_reg(3), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[4]_i_1_n_7\, + Q => minTimeCounter_low_reg(4), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[0]_i_3_n_0\, + CO(3) => \minTimeCounter_low_reg[4]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[4]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[4]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[4]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[4]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[4]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[4]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(7 downto 4) + ); +\minTimeCounter_low_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[4]_i_1_n_6\, + Q => minTimeCounter_low_reg(5), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[4]_i_1_n_5\, + Q => minTimeCounter_low_reg(6), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[4]_i_1_n_4\, + Q => minTimeCounter_low_reg(7), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[8]_i_1_n_7\, + Q => minTimeCounter_low_reg(8), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[4]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[8]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[8]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[8]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[8]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[8]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[8]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[8]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(11 downto 8) + ); +\minTimeCounter_low_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[8]_i_1_n_6\, + Q => minTimeCounter_low_reg(9), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +minTimeEr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"EEFFEEEEE200E2E2" + ) + port map ( + I0 => minTimeEr_i_2_n_0, + I1 => minTimeEr_i_3_n_0, + I2 => minTimeEr_i_4_n_0, + I3 => minTimeEr_i_5_n_0, + I4 => minTimeEr_i_6_n_0, + I5 => \^mintimeer_reg_0\, + O => minTimeEr_i_1_n_0 + ); +minTimeEr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"0111" + ) + port map ( + I0 => reset, + I1 => breaking_en, + I2 => minTimeEr_i_6_n_0, + I3 => minTimeEr_i_7_n_0, + O => minTimeEr_i_2_n_0 + ); +minTimeEr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => breaking_en, + I1 => reset, + O => minTimeEr_i_3_n_0 + ); +minTimeEr_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"040404FF00000000" + ) + port map ( + I0 => minTimeOK_low, + I1 => key2_reg_n_0, + I2 => key2_prev, + I3 => minTimeEr_i_8_n_0, + I4 => minTimeOK_high, + I5 => minTime_En, + O => minTimeEr_i_4_n_0 + ); +minTimeEr_i_5: unisim.vcomponents.LUT6 + generic map( + INIT => X"55555555F755F7F7" + ) + port map ( + I0 => minTimeEr_i_9_n_0, + I1 => key2_prev, + I2 => key2_reg_n_0, + I3 => key1_reg_n_0, + I4 => key1_prev, + I5 => minTimeEr_i_7_n_0, + O => minTimeEr_i_5_n_0 + ); +minTimeEr_i_6: unisim.vcomponents.LUT6 + generic map( + INIT => X"FBFFFFFFBBFBFBFF" + ) + port map ( + I0 => minTimeOK_low, + I1 => minTime_En, + I2 => key3_prev, + I3 => key3_reg_n_0, + I4 => key4_reg_n_0, + I5 => key4_prev, + O => minTimeEr_i_6_n_0 + ); +minTimeEr_i_7: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFDFDDDDFFDFFFDF" + ) + port map ( + I0 => minTime_En, + I1 => minTimeOK_high, + I2 => key2_reg_n_0, + I3 => key2_prev, + I4 => key1_prev, + I5 => key1_reg_n_0, + O => minTimeEr_i_7_n_0 + ); +minTimeEr_i_8: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => key1_prev, + I1 => key1_reg_n_0, + O => minTimeEr_i_8_n_0 + ); +minTimeEr_i_9: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => breaking_en, + I1 => reset, + O => minTimeEr_i_9_n_0 + ); +minTimeEr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => '1', + D => minTimeEr_i_1_n_0, + Q => \^mintimeer_reg_0\, + R => '0' + ); +minTimeOK_high_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"00AB" + ) + port map ( + I0 => minTimeOK_high, + I1 => \ltOp__31_carry__2_n_0\, + I2 => reset, + I3 => \minTimeCounter_high[0]_i_1_n_0\, + O => minTimeOK_high_i_1_n_0 + ); +minTimeOK_high_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => minTimeOK_high_i_1_n_0, + Q => minTimeOK_high, + R => '0' + ); +minTimeOK_low_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"00AB" + ) + port map ( + I0 => minTimeOK_low, + I1 => \ltOp__15_carry__2_n_0\, + I2 => reset, + I3 => \minTimeCounter_low[0]_i_1_n_0\, + O => minTimeOK_low_i_1_n_0 + ); +minTimeOK_low_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => minTimeOK_low_i_1_n_0, + Q => minTimeOK_low, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Inverter_3lvl_P0N_3lvl_1_0 is + port ( + externalCLK : in STD_LOGIC; + ready : in STD_LOGIC; + reset : in STD_LOGIC; + deadTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + minTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + er : in STD_LOGIC; + minTime_En : in STD_LOGIC; + minTimeEr : out STD_LOGIC; + TKin0 : in STD_LOGIC; + TKin1 : in STD_LOGIC; + breaking_en : in STD_LOGIC; + PWM_out_0 : out STD_LOGIC; + PWM_out_1 : out STD_LOGIC; + PWM_out_2 : out STD_LOGIC; + PWM_out_3 : out STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of Inverter_3lvl_P0N_3lvl_1_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of Inverter_3lvl_P0N_3lvl_1_0 : entity is "Inverter_3lvl_P0N_3lvl_0_4,P0N_3lvl,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of Inverter_3lvl_P0N_3lvl_1_0 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of Inverter_3lvl_P0N_3lvl_1_0 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of Inverter_3lvl_P0N_3lvl_1_0 : entity is "P0N_3lvl,Vivado 2019.1"; +end Inverter_3lvl_P0N_3lvl_1_0; + +architecture STRUCTURE of Inverter_3lvl_P0N_3lvl_1_0 is + attribute x_interface_info : string; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.Inverter_3lvl_P0N_3lvl_1_0_P0N_3lvl + port map ( + PWM_out_0 => PWM_out_0, + PWM_out_1 => PWM_out_1, + PWM_out_2 => PWM_out_2, + PWM_out_3 => PWM_out_3, + TKin0 => TKin0, + TKin1 => TKin1, + breaking_en => breaking_en, + deadTime(31 downto 0) => deadTime(31 downto 0), + er => er, + externalCLK => externalCLK, + minTime(31 downto 0) => minTime(31 downto 0), + minTimeEr_reg_0 => minTimeEr, + minTime_En => minTime_En, + ready => ready, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0_stub.v b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0_stub.v new file mode 100644 index 0000000..f311144 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0_stub.v @@ -0,0 +1,35 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Fri Jun 11 07:49:57 2021 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top Inverter_3lvl_P0N_3lvl_1_0 -prefix +// Inverter_3lvl_P0N_3lvl_1_0_ Inverter_3lvl_P0N_3lvl_0_4_stub.v +// Design : Inverter_3lvl_P0N_3lvl_0_4 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "P0N_3lvl,Vivado 2019.1" *) +module Inverter_3lvl_P0N_3lvl_1_0(externalCLK, ready, reset, deadTime, minTime, er, + minTime_En, minTimeEr, TKin0, TKin1, breaking_en, PWM_out_0, PWM_out_1, PWM_out_2, PWM_out_3) +/* synthesis syn_black_box black_box_pad_pin="externalCLK,ready,reset,deadTime[31:0],minTime[31:0],er,minTime_En,minTimeEr,TKin0,TKin1,breaking_en,PWM_out_0,PWM_out_1,PWM_out_2,PWM_out_3" */; + input externalCLK; + input ready; + input reset; + input [31:0]deadTime; + input [31:0]minTime; + input er; + input minTime_En; + output minTimeEr; + input TKin0; + input TKin1; + input breaking_en; + output PWM_out_0; + output PWM_out_1; + output PWM_out_2; + output PWM_out_3; +endmodule diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0_stub.vhdl b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0_stub.vhdl new file mode 100644 index 0000000..f2c11a5 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_0/Inverter_3lvl_P0N_3lvl_1_0_stub.vhdl @@ -0,0 +1,44 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Fri Jun 11 07:49:57 2021 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top Inverter_3lvl_P0N_3lvl_1_0 -prefix +-- Inverter_3lvl_P0N_3lvl_1_0_ Inverter_3lvl_P0N_3lvl_0_4_stub.vhdl +-- Design : Inverter_3lvl_P0N_3lvl_0_4 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Inverter_3lvl_P0N_3lvl_1_0 is + Port ( + externalCLK : in STD_LOGIC; + ready : in STD_LOGIC; + reset : in STD_LOGIC; + deadTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + minTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + er : in STD_LOGIC; + minTime_En : in STD_LOGIC; + minTimeEr : out STD_LOGIC; + TKin0 : in STD_LOGIC; + TKin1 : in STD_LOGIC; + breaking_en : in STD_LOGIC; + PWM_out_0 : out STD_LOGIC; + PWM_out_1 : out STD_LOGIC; + PWM_out_2 : out STD_LOGIC; + PWM_out_3 : out STD_LOGIC + ); + +end Inverter_3lvl_P0N_3lvl_1_0; + +architecture stub of Inverter_3lvl_P0N_3lvl_1_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "externalCLK,ready,reset,deadTime[31:0],minTime[31:0],er,minTime_En,minTimeEr,TKin0,TKin1,breaking_en,PWM_out_0,PWM_out_1,PWM_out_2,PWM_out_3"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "P0N_3lvl,Vivado 2019.1"; +begin +end; diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/Inverter_3lvl_P0N_3lvl_1_1.dcp b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1.dcp similarity index 99% rename from LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_1_1_synth_1/Inverter_3lvl_P0N_3lvl_1_1.dcp rename to LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1.dcp index d68d23fb0a1990222dacca0538c9b322059385b7..b640fa4b3177253e692ea4f4a07e0f994b5e5c7b 100644 GIT binary patch delta 28 hcmdnKn0fnR<_%G2Sf<4;4%-}eMv4{8np|_y8UVSd42S># delta 28 hcmdnKn0fnR<_%G2SX}H*2W^f!BgG14O|H3U4FIu>3+?~_ diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1.xml b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1.xml index 71c44b9..dd31371 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1.xml +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1.xml @@ -133,6 +133,24 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed May 03 08:44:45 UTC 2023 + + + outputProductCRC + 9:7f9a7fa6 + + + @@ -407,6 +425,42 @@ xil_defaultlib + + xilinx_externalfiles_view_fileset + + Inverter_3lvl_P0N_3lvl_1_1.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_1_1_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_1_1_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_1_1_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Inverter_3lvl_P0N_3lvl_1_1_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + P0N_3lvl_v1_0 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1_sim_netlist.v b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1_sim_netlist.v new file mode 100644 index 0000000..631ce1a --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1_sim_netlist.v @@ -0,0 +1,3131 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Fri Jun 11 07:49:57 2021 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top Inverter_3lvl_P0N_3lvl_1_1 -prefix +// Inverter_3lvl_P0N_3lvl_1_1_ Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.v +// Design : Inverter_3lvl_P0N_3lvl_0_4 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "Inverter_3lvl_P0N_3lvl_0_4,P0N_3lvl,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) +(* x_core_info = "P0N_3lvl,Vivado 2019.1" *) +(* NotValidForBitStream *) +module Inverter_3lvl_P0N_3lvl_1_1 + (externalCLK, + ready, + reset, + deadTime, + minTime, + er, + minTime_En, + minTimeEr, + TKin0, + TKin1, + breaking_en, + PWM_out_0, + PWM_out_1, + PWM_out_2, + PWM_out_3); + input externalCLK; + input ready; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + input [31:0]deadTime; + input [31:0]minTime; + input er; + input minTime_En; + output minTimeEr; + input TKin0; + input TKin1; + input breaking_en; + output PWM_out_0; + output PWM_out_1; + output PWM_out_2; + output PWM_out_3; + + wire PWM_out_0; + wire PWM_out_1; + wire PWM_out_2; + wire PWM_out_3; + wire TKin0; + wire TKin1; + wire breaking_en; + wire [31:0]deadTime; + wire er; + wire externalCLK; + wire [31:0]minTime; + wire minTimeEr; + wire minTime_En; + wire ready; + wire reset; + + Inverter_3lvl_P0N_3lvl_1_1_P0N_3lvl U0 + (.PWM_out_0(PWM_out_0), + .PWM_out_1(PWM_out_1), + .PWM_out_2(PWM_out_2), + .PWM_out_3(PWM_out_3), + .TKin0(TKin0), + .TKin1(TKin1), + .breaking_en(breaking_en), + .deadTime(deadTime), + .er(er), + .externalCLK(externalCLK), + .minTime(minTime), + .minTimeEr_reg_0(minTimeEr), + .minTime_En(minTime_En), + .ready(ready), + .reset(reset)); +endmodule + +module Inverter_3lvl_P0N_3lvl_1_1_P0N_3lvl + (minTimeEr_reg_0, + PWM_out_0, + PWM_out_1, + PWM_out_2, + PWM_out_3, + reset, + externalCLK, + TKin0, + TKin1, + breaking_en, + er, + ready, + minTime_En, + deadTime, + minTime); + output minTimeEr_reg_0; + output PWM_out_0; + output PWM_out_1; + output PWM_out_2; + output PWM_out_3; + input reset; + input externalCLK; + input TKin0; + input TKin1; + input breaking_en; + input er; + input ready; + input minTime_En; + input [31:0]deadTime; + input [31:0]minTime; + + wire \FSM_onehot_lineconfig[0]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[0]_i_2_n_0 ; + wire \FSM_onehot_lineconfig[1]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[2]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[2]_i_2_n_0 ; + wire \FSM_onehot_lineconfig[3]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[4]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[5]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[5]_i_2_n_0 ; + wire \FSM_onehot_lineconfig[5]_i_3_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_1_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_2_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_3_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_4_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_5_n_0 ; + wire \FSM_onehot_lineconfig[6]_i_6_n_0 ; + wire \FSM_onehot_lineconfig_reg_n_0_[0] ; + wire \FSM_onehot_lineconfig_reg_n_0_[1] ; + wire \FSM_onehot_lineconfig_reg_n_0_[2] ; + wire \FSM_onehot_lineconfig_reg_n_0_[3] ; + wire \FSM_onehot_lineconfig_reg_n_0_[4] ; + wire \FSM_onehot_lineconfig_reg_n_0_[5] ; + wire \FSM_onehot_lineconfig_reg_n_0_[6] ; + wire PWM_out_0; + wire PWM_out_0_i_1_n_0; + wire PWM_out_1; + wire PWM_out_1_i_1_n_0; + wire PWM_out_2; + wire PWM_out_2_i_1_n_0; + wire PWM_out_3; + wire PWM_out_3_i_1_n_0; + wire TKin0; + wire TKin0_triggered; + wire TKin0_triggered28_out; + wire TKin0_triggered_i_1_n_0; + wire TKin1; + wire TKin1_triggered; + wire TKin1_triggered_i_1_n_0; + wire \TimeCounter[0]_i_2_n_0 ; + wire [31:0]TimeCounter_reg; + wire \TimeCounter_reg[0]_i_1_n_0 ; + wire \TimeCounter_reg[0]_i_1_n_1 ; + wire \TimeCounter_reg[0]_i_1_n_2 ; + wire \TimeCounter_reg[0]_i_1_n_3 ; + wire \TimeCounter_reg[0]_i_1_n_4 ; + wire \TimeCounter_reg[0]_i_1_n_5 ; + wire \TimeCounter_reg[0]_i_1_n_6 ; + wire \TimeCounter_reg[0]_i_1_n_7 ; + wire \TimeCounter_reg[12]_i_1_n_0 ; + wire \TimeCounter_reg[12]_i_1_n_1 ; + wire \TimeCounter_reg[12]_i_1_n_2 ; + wire \TimeCounter_reg[12]_i_1_n_3 ; + wire \TimeCounter_reg[12]_i_1_n_4 ; + wire \TimeCounter_reg[12]_i_1_n_5 ; + wire \TimeCounter_reg[12]_i_1_n_6 ; + wire \TimeCounter_reg[12]_i_1_n_7 ; + wire \TimeCounter_reg[16]_i_1_n_0 ; + wire \TimeCounter_reg[16]_i_1_n_1 ; + wire \TimeCounter_reg[16]_i_1_n_2 ; + wire \TimeCounter_reg[16]_i_1_n_3 ; + wire \TimeCounter_reg[16]_i_1_n_4 ; + wire \TimeCounter_reg[16]_i_1_n_5 ; + wire \TimeCounter_reg[16]_i_1_n_6 ; + wire \TimeCounter_reg[16]_i_1_n_7 ; + wire \TimeCounter_reg[20]_i_1_n_0 ; + wire \TimeCounter_reg[20]_i_1_n_1 ; + wire \TimeCounter_reg[20]_i_1_n_2 ; + wire \TimeCounter_reg[20]_i_1_n_3 ; + wire \TimeCounter_reg[20]_i_1_n_4 ; + wire \TimeCounter_reg[20]_i_1_n_5 ; + wire \TimeCounter_reg[20]_i_1_n_6 ; + wire \TimeCounter_reg[20]_i_1_n_7 ; + wire \TimeCounter_reg[24]_i_1_n_0 ; + wire \TimeCounter_reg[24]_i_1_n_1 ; + wire \TimeCounter_reg[24]_i_1_n_2 ; + wire \TimeCounter_reg[24]_i_1_n_3 ; + wire \TimeCounter_reg[24]_i_1_n_4 ; + wire \TimeCounter_reg[24]_i_1_n_5 ; + wire \TimeCounter_reg[24]_i_1_n_6 ; + wire \TimeCounter_reg[24]_i_1_n_7 ; + wire \TimeCounter_reg[28]_i_1_n_1 ; + wire \TimeCounter_reg[28]_i_1_n_2 ; + wire \TimeCounter_reg[28]_i_1_n_3 ; + wire \TimeCounter_reg[28]_i_1_n_4 ; + wire \TimeCounter_reg[28]_i_1_n_5 ; + wire \TimeCounter_reg[28]_i_1_n_6 ; + wire \TimeCounter_reg[28]_i_1_n_7 ; + wire \TimeCounter_reg[4]_i_1_n_0 ; + wire \TimeCounter_reg[4]_i_1_n_1 ; + wire \TimeCounter_reg[4]_i_1_n_2 ; + wire \TimeCounter_reg[4]_i_1_n_3 ; + wire \TimeCounter_reg[4]_i_1_n_4 ; + wire \TimeCounter_reg[4]_i_1_n_5 ; + wire \TimeCounter_reg[4]_i_1_n_6 ; + wire \TimeCounter_reg[4]_i_1_n_7 ; + wire \TimeCounter_reg[8]_i_1_n_0 ; + wire \TimeCounter_reg[8]_i_1_n_1 ; + wire \TimeCounter_reg[8]_i_1_n_2 ; + wire \TimeCounter_reg[8]_i_1_n_3 ; + wire \TimeCounter_reg[8]_i_1_n_4 ; + wire \TimeCounter_reg[8]_i_1_n_5 ; + wire \TimeCounter_reg[8]_i_1_n_6 ; + wire \TimeCounter_reg[8]_i_1_n_7 ; + wire breaking_en; + wire [31:0]deadTime; + wire deadTimeCounterReset_i_1_n_0; + wire deadTimeCounterReset_i_2_n_0; + wire deadTimeCounterReset_i_3_n_0; + wire deadTimeCounterReset_i_4_n_0; + wire deadTimeCounterReset_i_5_n_0; + wire deadTimeCounterReset_i_6_n_0; + wire deadTimeCounterReset_i_7_n_0; + wire deadTimeCounterReset_reg_n_0; + wire deadTimeOK; + wire deadTimeOK_i_1_n_0; + wire er; + wire externalCLK; + wire key1_i_1_n_0; + wire key1_i_2_n_0; + wire key1_prev; + wire key1_reg_n_0; + wire key2_i_2_n_0; + wire key2_prev; + wire key2_reg_n_0; + wire key3; + wire key3_i_1_n_0; + wire key3_prev; + wire key3_reg_n_0; + wire key4_i_1_n_0; + wire key4_prev; + wire key4_reg_n_0; + wire ltOp__15_carry__0_i_1_n_0; + wire ltOp__15_carry__0_i_2_n_0; + wire ltOp__15_carry__0_i_3_n_0; + wire ltOp__15_carry__0_i_4_n_0; + wire ltOp__15_carry__0_i_5_n_0; + wire ltOp__15_carry__0_i_6_n_0; + wire ltOp__15_carry__0_i_7_n_0; + wire ltOp__15_carry__0_i_8_n_0; + wire ltOp__15_carry__0_n_0; + wire ltOp__15_carry__0_n_1; + wire ltOp__15_carry__0_n_2; + wire ltOp__15_carry__0_n_3; + wire ltOp__15_carry__1_i_1_n_0; + wire ltOp__15_carry__1_i_2_n_0; + wire ltOp__15_carry__1_i_3_n_0; + wire ltOp__15_carry__1_i_4_n_0; + wire ltOp__15_carry__1_i_5_n_0; + wire ltOp__15_carry__1_i_6_n_0; + wire ltOp__15_carry__1_i_7_n_0; + wire ltOp__15_carry__1_i_8_n_0; + wire ltOp__15_carry__1_n_0; + wire ltOp__15_carry__1_n_1; + wire ltOp__15_carry__1_n_2; + wire ltOp__15_carry__1_n_3; + wire ltOp__15_carry__2_i_1_n_0; + wire ltOp__15_carry__2_i_2_n_0; + wire ltOp__15_carry__2_i_3_n_0; + wire ltOp__15_carry__2_i_4_n_0; + wire ltOp__15_carry__2_i_5_n_0; + wire ltOp__15_carry__2_i_6_n_0; + wire ltOp__15_carry__2_i_7_n_0; + wire ltOp__15_carry__2_i_8_n_0; + wire ltOp__15_carry__2_n_0; + wire ltOp__15_carry__2_n_1; + wire ltOp__15_carry__2_n_2; + wire ltOp__15_carry__2_n_3; + wire ltOp__15_carry_i_1_n_0; + wire ltOp__15_carry_i_2_n_0; + wire ltOp__15_carry_i_3_n_0; + wire ltOp__15_carry_i_4_n_0; + wire ltOp__15_carry_i_5_n_0; + wire ltOp__15_carry_i_6_n_0; + wire ltOp__15_carry_i_7_n_0; + wire ltOp__15_carry_i_8_n_0; + wire ltOp__15_carry_n_0; + wire ltOp__15_carry_n_1; + wire ltOp__15_carry_n_2; + wire ltOp__15_carry_n_3; + wire ltOp__31_carry__0_n_0; + wire ltOp__31_carry__0_n_1; + wire ltOp__31_carry__0_n_2; + wire ltOp__31_carry__0_n_3; + wire ltOp__31_carry__1_n_0; + wire ltOp__31_carry__1_n_1; + wire ltOp__31_carry__1_n_2; + wire ltOp__31_carry__1_n_3; + wire ltOp__31_carry__2_n_0; + wire ltOp__31_carry__2_n_1; + wire ltOp__31_carry__2_n_2; + wire ltOp__31_carry__2_n_3; + wire ltOp__31_carry_i_1__0_n_0; + wire ltOp__31_carry_i_1__1_n_0; + wire ltOp__31_carry_i_1__2_n_0; + wire ltOp__31_carry_i_1_n_0; + wire ltOp__31_carry_i_2__0_n_0; + wire ltOp__31_carry_i_2__1_n_0; + wire ltOp__31_carry_i_2__2_n_0; + wire ltOp__31_carry_i_2_n_0; + wire ltOp__31_carry_i_3__0_n_0; + wire ltOp__31_carry_i_3__1_n_0; + wire ltOp__31_carry_i_3__2_n_0; + wire ltOp__31_carry_i_3_n_0; + wire ltOp__31_carry_i_4__0_n_0; + wire ltOp__31_carry_i_4__1_n_0; + wire ltOp__31_carry_i_4__2_n_0; + wire ltOp__31_carry_i_4_n_0; + wire ltOp__31_carry_i_5__0_n_0; + wire ltOp__31_carry_i_5__1_n_0; + wire ltOp__31_carry_i_5__2_n_0; + wire ltOp__31_carry_i_5_n_0; + wire ltOp__31_carry_i_6__0_n_0; + wire ltOp__31_carry_i_6__1_n_0; + wire ltOp__31_carry_i_6__2_n_0; + wire ltOp__31_carry_i_6_n_0; + wire ltOp__31_carry_i_7__0_n_0; + wire ltOp__31_carry_i_7__1_n_0; + wire ltOp__31_carry_i_7__2_n_0; + wire ltOp__31_carry_i_7_n_0; + wire ltOp__31_carry_i_8__0_n_0; + wire ltOp__31_carry_i_8__1_n_0; + wire ltOp__31_carry_i_8__2_n_0; + wire ltOp__31_carry_i_8_n_0; + wire ltOp__31_carry_n_0; + wire ltOp__31_carry_n_1; + wire ltOp__31_carry_n_2; + wire ltOp__31_carry_n_3; + wire ltOp_carry__0_i_1_n_0; + wire ltOp_carry__0_i_2_n_0; + wire ltOp_carry__0_i_3_n_0; + wire ltOp_carry__0_i_4_n_0; + wire ltOp_carry__0_i_5_n_0; + wire ltOp_carry__0_i_6_n_0; + wire ltOp_carry__0_i_7_n_0; + wire ltOp_carry__0_i_8_n_0; + wire ltOp_carry__0_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry__1_i_1_n_0; + wire ltOp_carry__1_i_2_n_0; + wire ltOp_carry__1_i_3_n_0; + wire ltOp_carry__1_i_4_n_0; + wire ltOp_carry__1_i_5_n_0; + wire ltOp_carry__1_i_6_n_0; + wire ltOp_carry__1_i_7_n_0; + wire ltOp_carry__1_i_8_n_0; + wire ltOp_carry__1_n_0; + wire ltOp_carry__1_n_1; + wire ltOp_carry__1_n_2; + wire ltOp_carry__1_n_3; + wire ltOp_carry__2_i_1_n_0; + wire ltOp_carry__2_i_2_n_0; + wire ltOp_carry__2_i_3_n_0; + wire ltOp_carry__2_i_4_n_0; + wire ltOp_carry__2_i_5_n_0; + wire ltOp_carry__2_i_6_n_0; + wire ltOp_carry__2_i_7_n_0; + wire ltOp_carry__2_i_8_n_0; + wire ltOp_carry__2_n_1; + wire ltOp_carry__2_n_2; + wire ltOp_carry__2_n_3; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire [31:0]minTime; + wire minTimeCounter_high; + wire \minTimeCounter_high[0]_i_1_n_0 ; + wire \minTimeCounter_high[0]_i_4_n_0 ; + wire [31:0]minTimeCounter_high_reg; + wire \minTimeCounter_high_reg[0]_i_3_n_0 ; + wire \minTimeCounter_high_reg[0]_i_3_n_1 ; + wire \minTimeCounter_high_reg[0]_i_3_n_2 ; + wire \minTimeCounter_high_reg[0]_i_3_n_3 ; + wire \minTimeCounter_high_reg[0]_i_3_n_4 ; + wire \minTimeCounter_high_reg[0]_i_3_n_5 ; + wire \minTimeCounter_high_reg[0]_i_3_n_6 ; + wire \minTimeCounter_high_reg[0]_i_3_n_7 ; + wire \minTimeCounter_high_reg[12]_i_1_n_0 ; + wire \minTimeCounter_high_reg[12]_i_1_n_1 ; + wire \minTimeCounter_high_reg[12]_i_1_n_2 ; + wire \minTimeCounter_high_reg[12]_i_1_n_3 ; + wire \minTimeCounter_high_reg[12]_i_1_n_4 ; + wire \minTimeCounter_high_reg[12]_i_1_n_5 ; + wire \minTimeCounter_high_reg[12]_i_1_n_6 ; + wire \minTimeCounter_high_reg[12]_i_1_n_7 ; + wire \minTimeCounter_high_reg[16]_i_1_n_0 ; + wire \minTimeCounter_high_reg[16]_i_1_n_1 ; + wire \minTimeCounter_high_reg[16]_i_1_n_2 ; + wire \minTimeCounter_high_reg[16]_i_1_n_3 ; + wire \minTimeCounter_high_reg[16]_i_1_n_4 ; + wire \minTimeCounter_high_reg[16]_i_1_n_5 ; + wire \minTimeCounter_high_reg[16]_i_1_n_6 ; + wire \minTimeCounter_high_reg[16]_i_1_n_7 ; + wire \minTimeCounter_high_reg[20]_i_1_n_0 ; + wire \minTimeCounter_high_reg[20]_i_1_n_1 ; + wire \minTimeCounter_high_reg[20]_i_1_n_2 ; + wire \minTimeCounter_high_reg[20]_i_1_n_3 ; + wire \minTimeCounter_high_reg[20]_i_1_n_4 ; + wire \minTimeCounter_high_reg[20]_i_1_n_5 ; + wire \minTimeCounter_high_reg[20]_i_1_n_6 ; + wire \minTimeCounter_high_reg[20]_i_1_n_7 ; + wire \minTimeCounter_high_reg[24]_i_1_n_0 ; + wire \minTimeCounter_high_reg[24]_i_1_n_1 ; + wire \minTimeCounter_high_reg[24]_i_1_n_2 ; + wire \minTimeCounter_high_reg[24]_i_1_n_3 ; + wire \minTimeCounter_high_reg[24]_i_1_n_4 ; + wire \minTimeCounter_high_reg[24]_i_1_n_5 ; + wire \minTimeCounter_high_reg[24]_i_1_n_6 ; + wire \minTimeCounter_high_reg[24]_i_1_n_7 ; + wire \minTimeCounter_high_reg[28]_i_1_n_1 ; + wire \minTimeCounter_high_reg[28]_i_1_n_2 ; + wire \minTimeCounter_high_reg[28]_i_1_n_3 ; + wire \minTimeCounter_high_reg[28]_i_1_n_4 ; + wire \minTimeCounter_high_reg[28]_i_1_n_5 ; + wire \minTimeCounter_high_reg[28]_i_1_n_6 ; + wire \minTimeCounter_high_reg[28]_i_1_n_7 ; + wire \minTimeCounter_high_reg[4]_i_1_n_0 ; + wire \minTimeCounter_high_reg[4]_i_1_n_1 ; + wire \minTimeCounter_high_reg[4]_i_1_n_2 ; + wire \minTimeCounter_high_reg[4]_i_1_n_3 ; + wire \minTimeCounter_high_reg[4]_i_1_n_4 ; + wire \minTimeCounter_high_reg[4]_i_1_n_5 ; + wire \minTimeCounter_high_reg[4]_i_1_n_6 ; + wire \minTimeCounter_high_reg[4]_i_1_n_7 ; + wire \minTimeCounter_high_reg[8]_i_1_n_0 ; + wire \minTimeCounter_high_reg[8]_i_1_n_1 ; + wire \minTimeCounter_high_reg[8]_i_1_n_2 ; + wire \minTimeCounter_high_reg[8]_i_1_n_3 ; + wire \minTimeCounter_high_reg[8]_i_1_n_4 ; + wire \minTimeCounter_high_reg[8]_i_1_n_5 ; + wire \minTimeCounter_high_reg[8]_i_1_n_6 ; + wire \minTimeCounter_high_reg[8]_i_1_n_7 ; + wire minTimeCounter_low; + wire \minTimeCounter_low[0]_i_1_n_0 ; + wire \minTimeCounter_low[0]_i_4_n_0 ; + wire \minTimeCounter_low[0]_i_5_n_0 ; + wire [31:0]minTimeCounter_low_reg; + wire \minTimeCounter_low_reg[0]_i_3_n_0 ; + wire \minTimeCounter_low_reg[0]_i_3_n_1 ; + wire \minTimeCounter_low_reg[0]_i_3_n_2 ; + wire \minTimeCounter_low_reg[0]_i_3_n_3 ; + wire \minTimeCounter_low_reg[0]_i_3_n_4 ; + wire \minTimeCounter_low_reg[0]_i_3_n_5 ; + wire \minTimeCounter_low_reg[0]_i_3_n_6 ; + wire \minTimeCounter_low_reg[0]_i_3_n_7 ; + wire \minTimeCounter_low_reg[12]_i_1_n_0 ; + wire \minTimeCounter_low_reg[12]_i_1_n_1 ; + wire \minTimeCounter_low_reg[12]_i_1_n_2 ; + wire \minTimeCounter_low_reg[12]_i_1_n_3 ; + wire \minTimeCounter_low_reg[12]_i_1_n_4 ; + wire \minTimeCounter_low_reg[12]_i_1_n_5 ; + wire \minTimeCounter_low_reg[12]_i_1_n_6 ; + wire \minTimeCounter_low_reg[12]_i_1_n_7 ; + wire \minTimeCounter_low_reg[16]_i_1_n_0 ; + wire \minTimeCounter_low_reg[16]_i_1_n_1 ; + wire \minTimeCounter_low_reg[16]_i_1_n_2 ; + wire \minTimeCounter_low_reg[16]_i_1_n_3 ; + wire \minTimeCounter_low_reg[16]_i_1_n_4 ; + wire \minTimeCounter_low_reg[16]_i_1_n_5 ; + wire \minTimeCounter_low_reg[16]_i_1_n_6 ; + wire \minTimeCounter_low_reg[16]_i_1_n_7 ; + wire \minTimeCounter_low_reg[20]_i_1_n_0 ; + wire \minTimeCounter_low_reg[20]_i_1_n_1 ; + wire \minTimeCounter_low_reg[20]_i_1_n_2 ; + wire \minTimeCounter_low_reg[20]_i_1_n_3 ; + wire \minTimeCounter_low_reg[20]_i_1_n_4 ; + wire \minTimeCounter_low_reg[20]_i_1_n_5 ; + wire \minTimeCounter_low_reg[20]_i_1_n_6 ; + wire \minTimeCounter_low_reg[20]_i_1_n_7 ; + wire \minTimeCounter_low_reg[24]_i_1_n_0 ; + wire \minTimeCounter_low_reg[24]_i_1_n_1 ; + wire \minTimeCounter_low_reg[24]_i_1_n_2 ; + wire \minTimeCounter_low_reg[24]_i_1_n_3 ; + wire \minTimeCounter_low_reg[24]_i_1_n_4 ; + wire \minTimeCounter_low_reg[24]_i_1_n_5 ; + wire \minTimeCounter_low_reg[24]_i_1_n_6 ; + wire \minTimeCounter_low_reg[24]_i_1_n_7 ; + wire \minTimeCounter_low_reg[28]_i_1_n_1 ; + wire \minTimeCounter_low_reg[28]_i_1_n_2 ; + wire \minTimeCounter_low_reg[28]_i_1_n_3 ; + wire \minTimeCounter_low_reg[28]_i_1_n_4 ; + wire \minTimeCounter_low_reg[28]_i_1_n_5 ; + wire \minTimeCounter_low_reg[28]_i_1_n_6 ; + wire \minTimeCounter_low_reg[28]_i_1_n_7 ; + wire \minTimeCounter_low_reg[4]_i_1_n_0 ; + wire \minTimeCounter_low_reg[4]_i_1_n_1 ; + wire \minTimeCounter_low_reg[4]_i_1_n_2 ; + wire \minTimeCounter_low_reg[4]_i_1_n_3 ; + wire \minTimeCounter_low_reg[4]_i_1_n_4 ; + wire \minTimeCounter_low_reg[4]_i_1_n_5 ; + wire \minTimeCounter_low_reg[4]_i_1_n_6 ; + wire \minTimeCounter_low_reg[4]_i_1_n_7 ; + wire \minTimeCounter_low_reg[8]_i_1_n_0 ; + wire \minTimeCounter_low_reg[8]_i_1_n_1 ; + wire \minTimeCounter_low_reg[8]_i_1_n_2 ; + wire \minTimeCounter_low_reg[8]_i_1_n_3 ; + wire \minTimeCounter_low_reg[8]_i_1_n_4 ; + wire \minTimeCounter_low_reg[8]_i_1_n_5 ; + wire \minTimeCounter_low_reg[8]_i_1_n_6 ; + wire \minTimeCounter_low_reg[8]_i_1_n_7 ; + wire minTimeEr_i_1_n_0; + wire minTimeEr_i_2_n_0; + wire minTimeEr_i_3_n_0; + wire minTimeEr_i_4_n_0; + wire minTimeEr_i_5_n_0; + wire minTimeEr_i_6_n_0; + wire minTimeEr_i_7_n_0; + wire minTimeEr_i_8_n_0; + wire minTimeEr_i_9_n_0; + wire minTimeEr_reg_0; + wire minTimeOK_high; + wire minTimeOK_high_i_1_n_0; + wire minTimeOK_low; + wire minTimeOK_low_i_1_n_0; + wire minTime_En; + wire p_0_in; + wire ready; + wire reset; + wire sel; + wire [3:3]\NLW_TimeCounter_reg[28]_i_1_CO_UNCONNECTED ; + wire [3:0]NLW_ltOp__15_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp__15_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp__15_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp__15_carry__2_O_UNCONNECTED; + wire [3:0]NLW_ltOp__31_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp__31_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp__31_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp__31_carry__2_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__1_O_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__2_O_UNCONNECTED; + wire [3:3]\NLW_minTimeCounter_high_reg[28]_i_1_CO_UNCONNECTED ; + wire [3:3]\NLW_minTimeCounter_low_reg[28]_i_1_CO_UNCONNECTED ; + + LUT6 #( + .INIT(64'hFFFFFFFE00000000)) + \FSM_onehot_lineconfig[0]_i_1 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I4(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I5(\FSM_onehot_lineconfig[0]_i_2_n_0 ), + .O(\FSM_onehot_lineconfig[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_lineconfig[0]_i_2 + (.I0(TKin1), + .I1(TKin0), + .O(\FSM_onehot_lineconfig[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'h1000FFFF00000000)) + \FSM_onehot_lineconfig[1]_i_1 + (.I0(TKin1), + .I1(TKin1_triggered), + .I2(TKin0_triggered), + .I3(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I4(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I5(TKin0), + .O(\FSM_onehot_lineconfig[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h00EFEF0F)) + \FSM_onehot_lineconfig[2]_i_1 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I2(\FSM_onehot_lineconfig[2]_i_2_n_0 ), + .I3(TKin0), + .I4(TKin1), + .O(\FSM_onehot_lineconfig[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'h900990099009FFFF)) + \FSM_onehot_lineconfig[2]_i_2 + (.I0(TKin1), + .I1(TKin1_triggered), + .I2(TKin0), + .I3(TKin0_triggered), + .I4(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I5(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .O(\FSM_onehot_lineconfig[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0000000055D50000)) + \FSM_onehot_lineconfig[3]_i_1 + (.I0(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I2(TKin1_triggered), + .I3(TKin0_triggered), + .I4(TKin1), + .I5(TKin0), + .O(\FSM_onehot_lineconfig[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT4 #( + .INIT(16'h2230)) + \FSM_onehot_lineconfig[4]_i_1 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I1(TKin0), + .I2(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I3(TKin1), + .O(\FSM_onehot_lineconfig[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0CFF0C0D00050005)) + \FSM_onehot_lineconfig[5]_i_1 + (.I0(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I2(TKin1), + .I3(TKin0), + .I4(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I5(\FSM_onehot_lineconfig[5]_i_3_n_0 ), + .O(\FSM_onehot_lineconfig[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h1)) + \FSM_onehot_lineconfig[5]_i_2 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .O(\FSM_onehot_lineconfig[5]_i_2_n_0 )); + LUT4 #( + .INIT(16'h9009)) + \FSM_onehot_lineconfig[5]_i_3 + (.I0(TKin0_triggered), + .I1(TKin0), + .I2(TKin1_triggered), + .I3(TKin1), + .O(\FSM_onehot_lineconfig[5]_i_3_n_0 )); + LUT3 #( + .INIT(8'h0E)) + \FSM_onehot_lineconfig[6]_i_1 + (.I0(\FSM_onehot_lineconfig[6]_i_3_n_0 ), + .I1(\FSM_onehot_lineconfig[6]_i_4_n_0 ), + .I2(breaking_en), + .O(\FSM_onehot_lineconfig[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT4 #( + .INIT(16'h5504)) + \FSM_onehot_lineconfig[6]_i_2 + (.I0(TKin1), + .I1(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I2(TKin0), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .O(\FSM_onehot_lineconfig[6]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'hFFFEECAE)) + \FSM_onehot_lineconfig[6]_i_3 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I2(TKin1), + .I3(TKin0), + .I4(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .O(\FSM_onehot_lineconfig[6]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAABAAAAAFFFFAAAA)) + \FSM_onehot_lineconfig[6]_i_4 + (.I0(\FSM_onehot_lineconfig[6]_i_5_n_0 ), + .I1(er), + .I2(ready), + .I3(\FSM_onehot_lineconfig[6]_i_6_n_0 ), + .I4(deadTimeOK), + .I5(\FSM_onehot_lineconfig[2]_i_2_n_0 ), + .O(\FSM_onehot_lineconfig[6]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFC88A0A8)) + \FSM_onehot_lineconfig[6]_i_5 + (.I0(deadTimeOK), + .I1(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I3(TKin1), + .I4(TKin0), + .O(\FSM_onehot_lineconfig[6]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'hFF232323)) + \FSM_onehot_lineconfig[6]_i_6 + (.I0(deadTimeCounterReset_reg_n_0), + .I1(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I3(TKin1), + .I4(TKin0), + .O(\FSM_onehot_lineconfig[6]_i_6_n_0 )); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDSE #( + .INIT(1'b1)) + \FSM_onehot_lineconfig_reg[0] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[0]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .S(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[1] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[1]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[2] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[2]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[3] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[3]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[4] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[4]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[5] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[5]_i_1_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .R(reset)); + (* FSM_ENCODED_STATES = "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_lineconfig_reg[6] + (.C(externalCLK), + .CE(\FSM_onehot_lineconfig[6]_i_1_n_0 ), + .D(\FSM_onehot_lineconfig[6]_i_2_n_0 ), + .Q(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT4 #( + .INIT(16'hFFEF)) + PWM_out_0_i_1 + (.I0(key1_reg_n_0), + .I1(er), + .I2(ready), + .I3(minTimeEr_reg_0), + .O(PWM_out_0_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + PWM_out_0_reg + (.C(externalCLK), + .CE(1'b1), + .D(PWM_out_0_i_1_n_0), + .Q(PWM_out_0), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT4 #( + .INIT(16'hFFEF)) + PWM_out_1_i_1 + (.I0(key2_reg_n_0), + .I1(er), + .I2(ready), + .I3(minTimeEr_reg_0), + .O(PWM_out_1_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + PWM_out_1_reg + (.C(externalCLK), + .CE(1'b1), + .D(PWM_out_1_i_1_n_0), + .Q(PWM_out_1), + .R(1'b0)); + LUT5 #( + .INIT(32'hFFFFFFEF)) + PWM_out_2_i_1 + (.I0(key3_reg_n_0), + .I1(minTimeEr_reg_0), + .I2(ready), + .I3(er), + .I4(breaking_en), + .O(PWM_out_2_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + PWM_out_2_reg + (.C(externalCLK), + .CE(1'b1), + .D(PWM_out_2_i_1_n_0), + .Q(PWM_out_2), + .R(1'b0)); + LUT5 #( + .INIT(32'hFFFFFFEF)) + PWM_out_3_i_1 + (.I0(key4_reg_n_0), + .I1(minTimeEr_reg_0), + .I2(ready), + .I3(er), + .I4(breaking_en), + .O(PWM_out_3_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + PWM_out_3_reg + (.C(externalCLK), + .CE(1'b1), + .D(PWM_out_3_i_1_n_0), + .Q(PWM_out_3), + .R(1'b0)); + LUT6 #( + .INIT(64'hAA08FFFFAA080000)) + TKin0_triggered_i_1 + (.I0(TKin0), + .I1(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I2(TKin1), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I4(TKin0_triggered28_out), + .I5(TKin0_triggered), + .O(TKin0_triggered_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + TKin0_triggered_reg + (.C(externalCLK), + .CE(1'b1), + .D(TKin0_triggered_i_1_n_0), + .Q(TKin0_triggered), + .R(1'b0)); + LUT6 #( + .INIT(64'hAA08FFFFAA080000)) + TKin1_triggered_i_1 + (.I0(TKin1), + .I1(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I2(TKin0), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I4(TKin0_triggered28_out), + .I5(TKin1_triggered), + .O(TKin1_triggered_i_1_n_0)); + LUT6 #( + .INIT(64'h22AA22A820AA2020)) + TKin1_triggered_i_2 + (.I0(minTimeEr_i_9_n_0), + .I1(TKin1), + .I2(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I3(TKin0), + .I4(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I5(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .O(TKin0_triggered28_out)); + FDRE #( + .INIT(1'b1)) + TKin1_triggered_reg + (.C(externalCLK), + .CE(1'b1), + .D(TKin1_triggered_i_1_n_0), + .Q(TKin1_triggered), + .R(1'b0)); + LUT1 #( + .INIT(2'h1)) + \TimeCounter[0]_i_2 + (.I0(TimeCounter_reg[0]), + .O(\TimeCounter[0]_i_2_n_0 )); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[0] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[0]_i_1_n_7 ), + .Q(TimeCounter_reg[0]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[0]_i_1 + (.CI(1'b0), + .CO({\TimeCounter_reg[0]_i_1_n_0 ,\TimeCounter_reg[0]_i_1_n_1 ,\TimeCounter_reg[0]_i_1_n_2 ,\TimeCounter_reg[0]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\TimeCounter_reg[0]_i_1_n_4 ,\TimeCounter_reg[0]_i_1_n_5 ,\TimeCounter_reg[0]_i_1_n_6 ,\TimeCounter_reg[0]_i_1_n_7 }), + .S({TimeCounter_reg[3:1],\TimeCounter[0]_i_2_n_0 })); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[10] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[8]_i_1_n_5 ), + .Q(TimeCounter_reg[10]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[11] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[8]_i_1_n_4 ), + .Q(TimeCounter_reg[11]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[12] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[12]_i_1_n_7 ), + .Q(TimeCounter_reg[12]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[12]_i_1 + (.CI(\TimeCounter_reg[8]_i_1_n_0 ), + .CO({\TimeCounter_reg[12]_i_1_n_0 ,\TimeCounter_reg[12]_i_1_n_1 ,\TimeCounter_reg[12]_i_1_n_2 ,\TimeCounter_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[12]_i_1_n_4 ,\TimeCounter_reg[12]_i_1_n_5 ,\TimeCounter_reg[12]_i_1_n_6 ,\TimeCounter_reg[12]_i_1_n_7 }), + .S(TimeCounter_reg[15:12])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[13] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[12]_i_1_n_6 ), + .Q(TimeCounter_reg[13]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[14] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[12]_i_1_n_5 ), + .Q(TimeCounter_reg[14]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[15] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[12]_i_1_n_4 ), + .Q(TimeCounter_reg[15]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[16] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[16]_i_1_n_7 ), + .Q(TimeCounter_reg[16]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[16]_i_1 + (.CI(\TimeCounter_reg[12]_i_1_n_0 ), + .CO({\TimeCounter_reg[16]_i_1_n_0 ,\TimeCounter_reg[16]_i_1_n_1 ,\TimeCounter_reg[16]_i_1_n_2 ,\TimeCounter_reg[16]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[16]_i_1_n_4 ,\TimeCounter_reg[16]_i_1_n_5 ,\TimeCounter_reg[16]_i_1_n_6 ,\TimeCounter_reg[16]_i_1_n_7 }), + .S(TimeCounter_reg[19:16])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[17] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[16]_i_1_n_6 ), + .Q(TimeCounter_reg[17]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[18] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[16]_i_1_n_5 ), + .Q(TimeCounter_reg[18]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[19] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[16]_i_1_n_4 ), + .Q(TimeCounter_reg[19]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[1] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[0]_i_1_n_6 ), + .Q(TimeCounter_reg[1]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[20] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[20]_i_1_n_7 ), + .Q(TimeCounter_reg[20]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[20]_i_1 + (.CI(\TimeCounter_reg[16]_i_1_n_0 ), + .CO({\TimeCounter_reg[20]_i_1_n_0 ,\TimeCounter_reg[20]_i_1_n_1 ,\TimeCounter_reg[20]_i_1_n_2 ,\TimeCounter_reg[20]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[20]_i_1_n_4 ,\TimeCounter_reg[20]_i_1_n_5 ,\TimeCounter_reg[20]_i_1_n_6 ,\TimeCounter_reg[20]_i_1_n_7 }), + .S(TimeCounter_reg[23:20])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[21] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[20]_i_1_n_6 ), + .Q(TimeCounter_reg[21]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[22] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[20]_i_1_n_5 ), + .Q(TimeCounter_reg[22]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[23] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[20]_i_1_n_4 ), + .Q(TimeCounter_reg[23]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[24] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[24]_i_1_n_7 ), + .Q(TimeCounter_reg[24]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[24]_i_1 + (.CI(\TimeCounter_reg[20]_i_1_n_0 ), + .CO({\TimeCounter_reg[24]_i_1_n_0 ,\TimeCounter_reg[24]_i_1_n_1 ,\TimeCounter_reg[24]_i_1_n_2 ,\TimeCounter_reg[24]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[24]_i_1_n_4 ,\TimeCounter_reg[24]_i_1_n_5 ,\TimeCounter_reg[24]_i_1_n_6 ,\TimeCounter_reg[24]_i_1_n_7 }), + .S(TimeCounter_reg[27:24])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[25] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[24]_i_1_n_6 ), + .Q(TimeCounter_reg[25]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[26] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[24]_i_1_n_5 ), + .Q(TimeCounter_reg[26]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[27] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[24]_i_1_n_4 ), + .Q(TimeCounter_reg[27]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[28] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[28]_i_1_n_7 ), + .Q(TimeCounter_reg[28]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[28]_i_1 + (.CI(\TimeCounter_reg[24]_i_1_n_0 ), + .CO({\NLW_TimeCounter_reg[28]_i_1_CO_UNCONNECTED [3],\TimeCounter_reg[28]_i_1_n_1 ,\TimeCounter_reg[28]_i_1_n_2 ,\TimeCounter_reg[28]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[28]_i_1_n_4 ,\TimeCounter_reg[28]_i_1_n_5 ,\TimeCounter_reg[28]_i_1_n_6 ,\TimeCounter_reg[28]_i_1_n_7 }), + .S(TimeCounter_reg[31:28])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[29] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[28]_i_1_n_6 ), + .Q(TimeCounter_reg[29]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[2] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[0]_i_1_n_5 ), + .Q(TimeCounter_reg[2]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[30] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[28]_i_1_n_5 ), + .Q(TimeCounter_reg[30]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[31] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[28]_i_1_n_4 ), + .Q(TimeCounter_reg[31]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[3] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[0]_i_1_n_4 ), + .Q(TimeCounter_reg[3]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[4] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[4]_i_1_n_7 ), + .Q(TimeCounter_reg[4]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[4]_i_1 + (.CI(\TimeCounter_reg[0]_i_1_n_0 ), + .CO({\TimeCounter_reg[4]_i_1_n_0 ,\TimeCounter_reg[4]_i_1_n_1 ,\TimeCounter_reg[4]_i_1_n_2 ,\TimeCounter_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[4]_i_1_n_4 ,\TimeCounter_reg[4]_i_1_n_5 ,\TimeCounter_reg[4]_i_1_n_6 ,\TimeCounter_reg[4]_i_1_n_7 }), + .S(TimeCounter_reg[7:4])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[5] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[4]_i_1_n_6 ), + .Q(TimeCounter_reg[5]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[6] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[4]_i_1_n_5 ), + .Q(TimeCounter_reg[6]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[7] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[4]_i_1_n_4 ), + .Q(TimeCounter_reg[7]), + .R(deadTimeCounterReset_reg_n_0)); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[8] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[8]_i_1_n_7 ), + .Q(TimeCounter_reg[8]), + .R(deadTimeCounterReset_reg_n_0)); + CARRY4 \TimeCounter_reg[8]_i_1 + (.CI(\TimeCounter_reg[4]_i_1_n_0 ), + .CO({\TimeCounter_reg[8]_i_1_n_0 ,\TimeCounter_reg[8]_i_1_n_1 ,\TimeCounter_reg[8]_i_1_n_2 ,\TimeCounter_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\TimeCounter_reg[8]_i_1_n_4 ,\TimeCounter_reg[8]_i_1_n_5 ,\TimeCounter_reg[8]_i_1_n_6 ,\TimeCounter_reg[8]_i_1_n_7 }), + .S(TimeCounter_reg[11:8])); + FDRE #( + .INIT(1'b0)) + \TimeCounter_reg[9] + (.C(externalCLK), + .CE(sel), + .D(\TimeCounter_reg[8]_i_1_n_6 ), + .Q(TimeCounter_reg[9]), + .R(deadTimeCounterReset_reg_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFE0000000E)) + deadTimeCounterReset_i_1 + (.I0(deadTimeCounterReset_i_2_n_0), + .I1(\FSM_onehot_lineconfig[6]_i_4_n_0 ), + .I2(reset), + .I3(breaking_en), + .I4(deadTimeCounterReset_i_3_n_0), + .I5(deadTimeCounterReset_reg_n_0), + .O(deadTimeCounterReset_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'hFE)) + deadTimeCounterReset_i_2 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .O(deadTimeCounterReset_i_2_n_0)); + LUT6 #( + .INIT(64'h0000000022220020)) + deadTimeCounterReset_i_3 + (.I0(deadTimeCounterReset_i_4_n_0), + .I1(deadTimeCounterReset_i_2_n_0), + .I2(deadTimeCounterReset_i_5_n_0), + .I3(deadTimeCounterReset_i_6_n_0), + .I4(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I5(deadTimeCounterReset_i_7_n_0), + .O(deadTimeCounterReset_i_3_n_0)); + LUT6 #( + .INIT(64'h555D555555555555)) + deadTimeCounterReset_i_4 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I1(deadTimeOK), + .I2(TKin1), + .I3(TKin1_triggered), + .I4(TKin0), + .I5(TKin0_triggered), + .O(deadTimeCounterReset_i_4_n_0)); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT3 #( + .INIT(8'h08)) + deadTimeCounterReset_i_5 + (.I0(deadTimeOK), + .I1(ready), + .I2(er), + .O(deadTimeCounterReset_i_5_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT4 #( + .INIT(16'hF777)) + deadTimeCounterReset_i_6 + (.I0(TKin0), + .I1(TKin1), + .I2(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I3(deadTimeCounterReset_reg_n_0), + .O(deadTimeCounterReset_i_6_n_0)); + LUT6 #( + .INIT(64'hAAAAA2AAAAAAAAAA)) + deadTimeCounterReset_i_7 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I1(TKin1), + .I2(TKin0), + .I3(deadTimeOK), + .I4(TKin0_triggered), + .I5(TKin1_triggered), + .O(deadTimeCounterReset_i_7_n_0)); + FDRE #( + .INIT(1'b0)) + deadTimeCounterReset_reg + (.C(externalCLK), + .CE(1'b1), + .D(deadTimeCounterReset_i_1_n_0), + .Q(deadTimeCounterReset_reg_n_0), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT3 #( + .INIT(8'h0D)) + deadTimeOK_i_1 + (.I0(sel), + .I1(deadTimeOK), + .I2(deadTimeCounterReset_reg_n_0), + .O(deadTimeOK_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + deadTimeOK_reg + (.C(externalCLK), + .CE(1'b1), + .D(deadTimeOK_i_1_n_0), + .Q(deadTimeOK), + .R(1'b0)); + LUT6 #( + .INIT(64'hDDDDDDD0DDDDDDDD)) + key1_i_1 + (.I0(breaking_en), + .I1(TKin0), + .I2(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I4(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I5(key1_i_2_n_0), + .O(key1_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT4 #( + .INIT(16'h0001)) + key1_i_2 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I3(breaking_en), + .O(key1_i_2_n_0)); + FDRE #( + .INIT(1'b1)) + key1_prev_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key1_reg_n_0), + .Q(key1_prev), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + key1_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key1_i_1_n_0), + .Q(key1_reg_n_0), + .R(1'b0)); + LUT1 #( + .INIT(2'h1)) + key2_i_1 + (.I0(reset), + .O(p_0_in)); + LUT6 #( + .INIT(64'hAAAAAAAAFFFFFFFC)) + key2_i_2 + (.I0(TKin1), + .I1(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I4(\FSM_onehot_lineconfig_reg_n_0_[1] ), + .I5(breaking_en), + .O(key2_i_2_n_0)); + FDRE #( + .INIT(1'b1)) + key2_prev_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key2_reg_n_0), + .Q(key2_prev), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + key2_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key2_i_2_n_0), + .Q(key2_reg_n_0), + .R(1'b0)); + LUT6 #( + .INIT(64'hAAAAFFFFAAAAFCFF)) + key3_i_1 + (.I0(key3_reg_n_0), + .I1(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I3(\FSM_onehot_lineconfig[5]_i_2_n_0 ), + .I4(reset), + .I5(breaking_en), + .O(key3_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + key3_prev_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key3_reg_n_0), + .Q(key3_prev), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + key3_reg + (.C(externalCLK), + .CE(1'b1), + .D(key3_i_1_n_0), + .Q(key3_reg_n_0), + .R(1'b0)); + LUT6 #( + .INIT(64'hAAAAFFFFAAAAFFFC)) + key4_i_1 + (.I0(key4_reg_n_0), + .I1(key3), + .I2(\FSM_onehot_lineconfig_reg_n_0_[6] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[5] ), + .I4(reset), + .I5(breaking_en), + .O(key4_i_1_n_0)); + LUT4 #( + .INIT(16'hFFFE)) + key4_i_2 + (.I0(\FSM_onehot_lineconfig_reg_n_0_[2] ), + .I1(\FSM_onehot_lineconfig_reg_n_0_[0] ), + .I2(\FSM_onehot_lineconfig_reg_n_0_[4] ), + .I3(\FSM_onehot_lineconfig_reg_n_0_[3] ), + .O(key3)); + FDRE #( + .INIT(1'b1)) + key4_prev_reg + (.C(externalCLK), + .CE(p_0_in), + .D(key4_reg_n_0), + .Q(key4_prev), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + key4_reg + (.C(externalCLK), + .CE(1'b1), + .D(key4_i_1_n_0), + .Q(key4_reg_n_0), + .R(1'b0)); + CARRY4 ltOp__15_carry + (.CI(1'b0), + .CO({ltOp__15_carry_n_0,ltOp__15_carry_n_1,ltOp__15_carry_n_2,ltOp__15_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp__15_carry_i_1_n_0,ltOp__15_carry_i_2_n_0,ltOp__15_carry_i_3_n_0,ltOp__15_carry_i_4_n_0}), + .O(NLW_ltOp__15_carry_O_UNCONNECTED[3:0]), + .S({ltOp__15_carry_i_5_n_0,ltOp__15_carry_i_6_n_0,ltOp__15_carry_i_7_n_0,ltOp__15_carry_i_8_n_0})); + CARRY4 ltOp__15_carry__0 + (.CI(ltOp__15_carry_n_0), + .CO({ltOp__15_carry__0_n_0,ltOp__15_carry__0_n_1,ltOp__15_carry__0_n_2,ltOp__15_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp__15_carry__0_i_1_n_0,ltOp__15_carry__0_i_2_n_0,ltOp__15_carry__0_i_3_n_0,ltOp__15_carry__0_i_4_n_0}), + .O(NLW_ltOp__15_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp__15_carry__0_i_5_n_0,ltOp__15_carry__0_i_6_n_0,ltOp__15_carry__0_i_7_n_0,ltOp__15_carry__0_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__0_i_1 + (.I0(minTime[15]), + .I1(minTimeCounter_low_reg[15]), + .I2(minTime[14]), + .I3(minTimeCounter_low_reg[14]), + .O(ltOp__15_carry__0_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__0_i_2 + (.I0(minTime[13]), + .I1(minTimeCounter_low_reg[13]), + .I2(minTime[12]), + .I3(minTimeCounter_low_reg[12]), + .O(ltOp__15_carry__0_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__0_i_3 + (.I0(minTime[11]), + .I1(minTimeCounter_low_reg[11]), + .I2(minTime[10]), + .I3(minTimeCounter_low_reg[10]), + .O(ltOp__15_carry__0_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__0_i_4 + (.I0(minTime[9]), + .I1(minTimeCounter_low_reg[9]), + .I2(minTime[8]), + .I3(minTimeCounter_low_reg[8]), + .O(ltOp__15_carry__0_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__0_i_5 + (.I0(minTimeCounter_low_reg[15]), + .I1(minTime[15]), + .I2(minTimeCounter_low_reg[14]), + .I3(minTime[14]), + .O(ltOp__15_carry__0_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__0_i_6 + (.I0(minTimeCounter_low_reg[13]), + .I1(minTime[13]), + .I2(minTimeCounter_low_reg[12]), + .I3(minTime[12]), + .O(ltOp__15_carry__0_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__0_i_7 + (.I0(minTimeCounter_low_reg[11]), + .I1(minTime[11]), + .I2(minTimeCounter_low_reg[10]), + .I3(minTime[10]), + .O(ltOp__15_carry__0_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__0_i_8 + (.I0(minTimeCounter_low_reg[9]), + .I1(minTime[9]), + .I2(minTimeCounter_low_reg[8]), + .I3(minTime[8]), + .O(ltOp__15_carry__0_i_8_n_0)); + CARRY4 ltOp__15_carry__1 + (.CI(ltOp__15_carry__0_n_0), + .CO({ltOp__15_carry__1_n_0,ltOp__15_carry__1_n_1,ltOp__15_carry__1_n_2,ltOp__15_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp__15_carry__1_i_1_n_0,ltOp__15_carry__1_i_2_n_0,ltOp__15_carry__1_i_3_n_0,ltOp__15_carry__1_i_4_n_0}), + .O(NLW_ltOp__15_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp__15_carry__1_i_5_n_0,ltOp__15_carry__1_i_6_n_0,ltOp__15_carry__1_i_7_n_0,ltOp__15_carry__1_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__1_i_1 + (.I0(minTime[23]), + .I1(minTimeCounter_low_reg[23]), + .I2(minTime[22]), + .I3(minTimeCounter_low_reg[22]), + .O(ltOp__15_carry__1_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__1_i_2 + (.I0(minTime[21]), + .I1(minTimeCounter_low_reg[21]), + .I2(minTime[20]), + .I3(minTimeCounter_low_reg[20]), + .O(ltOp__15_carry__1_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__1_i_3 + (.I0(minTime[19]), + .I1(minTimeCounter_low_reg[19]), + .I2(minTime[18]), + .I3(minTimeCounter_low_reg[18]), + .O(ltOp__15_carry__1_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__1_i_4 + (.I0(minTime[17]), + .I1(minTimeCounter_low_reg[17]), + .I2(minTime[16]), + .I3(minTimeCounter_low_reg[16]), + .O(ltOp__15_carry__1_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__1_i_5 + (.I0(minTimeCounter_low_reg[23]), + .I1(minTime[23]), + .I2(minTimeCounter_low_reg[22]), + .I3(minTime[22]), + .O(ltOp__15_carry__1_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__1_i_6 + (.I0(minTimeCounter_low_reg[21]), + .I1(minTime[21]), + .I2(minTimeCounter_low_reg[20]), + .I3(minTime[20]), + .O(ltOp__15_carry__1_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__1_i_7 + (.I0(minTimeCounter_low_reg[19]), + .I1(minTime[19]), + .I2(minTimeCounter_low_reg[18]), + .I3(minTime[18]), + .O(ltOp__15_carry__1_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__1_i_8 + (.I0(minTimeCounter_low_reg[17]), + .I1(minTime[17]), + .I2(minTimeCounter_low_reg[16]), + .I3(minTime[16]), + .O(ltOp__15_carry__1_i_8_n_0)); + CARRY4 ltOp__15_carry__2 + (.CI(ltOp__15_carry__1_n_0), + .CO({ltOp__15_carry__2_n_0,ltOp__15_carry__2_n_1,ltOp__15_carry__2_n_2,ltOp__15_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp__15_carry__2_i_1_n_0,ltOp__15_carry__2_i_2_n_0,ltOp__15_carry__2_i_3_n_0,ltOp__15_carry__2_i_4_n_0}), + .O(NLW_ltOp__15_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp__15_carry__2_i_5_n_0,ltOp__15_carry__2_i_6_n_0,ltOp__15_carry__2_i_7_n_0,ltOp__15_carry__2_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__2_i_1 + (.I0(minTime[31]), + .I1(minTimeCounter_low_reg[31]), + .I2(minTime[30]), + .I3(minTimeCounter_low_reg[30]), + .O(ltOp__15_carry__2_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__2_i_2 + (.I0(minTime[29]), + .I1(minTimeCounter_low_reg[29]), + .I2(minTime[28]), + .I3(minTimeCounter_low_reg[28]), + .O(ltOp__15_carry__2_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__2_i_3 + (.I0(minTime[27]), + .I1(minTimeCounter_low_reg[27]), + .I2(minTime[26]), + .I3(minTimeCounter_low_reg[26]), + .O(ltOp__15_carry__2_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry__2_i_4 + (.I0(minTime[25]), + .I1(minTimeCounter_low_reg[25]), + .I2(minTime[24]), + .I3(minTimeCounter_low_reg[24]), + .O(ltOp__15_carry__2_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__2_i_5 + (.I0(minTimeCounter_low_reg[31]), + .I1(minTime[31]), + .I2(minTimeCounter_low_reg[30]), + .I3(minTime[30]), + .O(ltOp__15_carry__2_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__2_i_6 + (.I0(minTimeCounter_low_reg[29]), + .I1(minTime[29]), + .I2(minTimeCounter_low_reg[28]), + .I3(minTime[28]), + .O(ltOp__15_carry__2_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__2_i_7 + (.I0(minTimeCounter_low_reg[27]), + .I1(minTime[27]), + .I2(minTimeCounter_low_reg[26]), + .I3(minTime[26]), + .O(ltOp__15_carry__2_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry__2_i_8 + (.I0(minTimeCounter_low_reg[25]), + .I1(minTime[25]), + .I2(minTimeCounter_low_reg[24]), + .I3(minTime[24]), + .O(ltOp__15_carry__2_i_8_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry_i_1 + (.I0(minTime[7]), + .I1(minTimeCounter_low_reg[7]), + .I2(minTime[6]), + .I3(minTimeCounter_low_reg[6]), + .O(ltOp__15_carry_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry_i_2 + (.I0(minTime[5]), + .I1(minTimeCounter_low_reg[5]), + .I2(minTime[4]), + .I3(minTimeCounter_low_reg[4]), + .O(ltOp__15_carry_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry_i_3 + (.I0(minTime[3]), + .I1(minTimeCounter_low_reg[3]), + .I2(minTime[2]), + .I3(minTimeCounter_low_reg[2]), + .O(ltOp__15_carry_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__15_carry_i_4 + (.I0(minTime[1]), + .I1(minTimeCounter_low_reg[1]), + .I2(minTime[0]), + .I3(minTimeCounter_low_reg[0]), + .O(ltOp__15_carry_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry_i_5 + (.I0(minTimeCounter_low_reg[7]), + .I1(minTime[7]), + .I2(minTimeCounter_low_reg[6]), + .I3(minTime[6]), + .O(ltOp__15_carry_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry_i_6 + (.I0(minTimeCounter_low_reg[5]), + .I1(minTime[5]), + .I2(minTimeCounter_low_reg[4]), + .I3(minTime[4]), + .O(ltOp__15_carry_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry_i_7 + (.I0(minTimeCounter_low_reg[3]), + .I1(minTime[3]), + .I2(minTimeCounter_low_reg[2]), + .I3(minTime[2]), + .O(ltOp__15_carry_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__15_carry_i_8 + (.I0(minTimeCounter_low_reg[1]), + .I1(minTime[1]), + .I2(minTimeCounter_low_reg[0]), + .I3(minTime[0]), + .O(ltOp__15_carry_i_8_n_0)); + CARRY4 ltOp__31_carry + (.CI(1'b0), + .CO({ltOp__31_carry_n_0,ltOp__31_carry_n_1,ltOp__31_carry_n_2,ltOp__31_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp__31_carry_i_1_n_0,ltOp__31_carry_i_2_n_0,ltOp__31_carry_i_3_n_0,ltOp__31_carry_i_4_n_0}), + .O(NLW_ltOp__31_carry_O_UNCONNECTED[3:0]), + .S({ltOp__31_carry_i_5_n_0,ltOp__31_carry_i_6_n_0,ltOp__31_carry_i_7_n_0,ltOp__31_carry_i_8_n_0})); + CARRY4 ltOp__31_carry__0 + (.CI(ltOp__31_carry_n_0), + .CO({ltOp__31_carry__0_n_0,ltOp__31_carry__0_n_1,ltOp__31_carry__0_n_2,ltOp__31_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp__31_carry_i_1__0_n_0,ltOp__31_carry_i_2__0_n_0,ltOp__31_carry_i_3__0_n_0,ltOp__31_carry_i_4__0_n_0}), + .O(NLW_ltOp__31_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp__31_carry_i_5__0_n_0,ltOp__31_carry_i_6__0_n_0,ltOp__31_carry_i_7__0_n_0,ltOp__31_carry_i_8__0_n_0})); + CARRY4 ltOp__31_carry__1 + (.CI(ltOp__31_carry__0_n_0), + .CO({ltOp__31_carry__1_n_0,ltOp__31_carry__1_n_1,ltOp__31_carry__1_n_2,ltOp__31_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp__31_carry_i_1__1_n_0,ltOp__31_carry_i_2__1_n_0,ltOp__31_carry_i_3__1_n_0,ltOp__31_carry_i_4__1_n_0}), + .O(NLW_ltOp__31_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp__31_carry_i_5__1_n_0,ltOp__31_carry_i_6__1_n_0,ltOp__31_carry_i_7__1_n_0,ltOp__31_carry_i_8__1_n_0})); + CARRY4 ltOp__31_carry__2 + (.CI(ltOp__31_carry__1_n_0), + .CO({ltOp__31_carry__2_n_0,ltOp__31_carry__2_n_1,ltOp__31_carry__2_n_2,ltOp__31_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp__31_carry_i_1__2_n_0,ltOp__31_carry_i_2__2_n_0,ltOp__31_carry_i_3__2_n_0,ltOp__31_carry_i_4__2_n_0}), + .O(NLW_ltOp__31_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp__31_carry_i_5__2_n_0,ltOp__31_carry_i_6__2_n_0,ltOp__31_carry_i_7__2_n_0,ltOp__31_carry_i_8__2_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_1 + (.I0(minTime[7]), + .I1(minTimeCounter_high_reg[7]), + .I2(minTime[6]), + .I3(minTimeCounter_high_reg[6]), + .O(ltOp__31_carry_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_1__0 + (.I0(minTime[15]), + .I1(minTimeCounter_high_reg[15]), + .I2(minTime[14]), + .I3(minTimeCounter_high_reg[14]), + .O(ltOp__31_carry_i_1__0_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_1__1 + (.I0(minTime[23]), + .I1(minTimeCounter_high_reg[23]), + .I2(minTime[22]), + .I3(minTimeCounter_high_reg[22]), + .O(ltOp__31_carry_i_1__1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_1__2 + (.I0(minTime[31]), + .I1(minTimeCounter_high_reg[31]), + .I2(minTime[30]), + .I3(minTimeCounter_high_reg[30]), + .O(ltOp__31_carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_2 + (.I0(minTime[5]), + .I1(minTimeCounter_high_reg[5]), + .I2(minTime[4]), + .I3(minTimeCounter_high_reg[4]), + .O(ltOp__31_carry_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_2__0 + (.I0(minTime[13]), + .I1(minTimeCounter_high_reg[13]), + .I2(minTime[12]), + .I3(minTimeCounter_high_reg[12]), + .O(ltOp__31_carry_i_2__0_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_2__1 + (.I0(minTime[21]), + .I1(minTimeCounter_high_reg[21]), + .I2(minTime[20]), + .I3(minTimeCounter_high_reg[20]), + .O(ltOp__31_carry_i_2__1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_2__2 + (.I0(minTime[29]), + .I1(minTimeCounter_high_reg[29]), + .I2(minTime[28]), + .I3(minTimeCounter_high_reg[28]), + .O(ltOp__31_carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_3 + (.I0(minTime[3]), + .I1(minTimeCounter_high_reg[3]), + .I2(minTime[2]), + .I3(minTimeCounter_high_reg[2]), + .O(ltOp__31_carry_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_3__0 + (.I0(minTime[11]), + .I1(minTimeCounter_high_reg[11]), + .I2(minTime[10]), + .I3(minTimeCounter_high_reg[10]), + .O(ltOp__31_carry_i_3__0_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_3__1 + (.I0(minTime[19]), + .I1(minTimeCounter_high_reg[19]), + .I2(minTime[18]), + .I3(minTimeCounter_high_reg[18]), + .O(ltOp__31_carry_i_3__1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_3__2 + (.I0(minTime[27]), + .I1(minTimeCounter_high_reg[27]), + .I2(minTime[26]), + .I3(minTimeCounter_high_reg[26]), + .O(ltOp__31_carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_4 + (.I0(minTime[1]), + .I1(minTimeCounter_high_reg[1]), + .I2(minTime[0]), + .I3(minTimeCounter_high_reg[0]), + .O(ltOp__31_carry_i_4_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_4__0 + (.I0(minTime[9]), + .I1(minTimeCounter_high_reg[9]), + .I2(minTime[8]), + .I3(minTimeCounter_high_reg[8]), + .O(ltOp__31_carry_i_4__0_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_4__1 + (.I0(minTime[17]), + .I1(minTimeCounter_high_reg[17]), + .I2(minTime[16]), + .I3(minTimeCounter_high_reg[16]), + .O(ltOp__31_carry_i_4__1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp__31_carry_i_4__2 + (.I0(minTime[25]), + .I1(minTimeCounter_high_reg[25]), + .I2(minTime[24]), + .I3(minTimeCounter_high_reg[24]), + .O(ltOp__31_carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_5 + (.I0(minTimeCounter_high_reg[7]), + .I1(minTime[7]), + .I2(minTimeCounter_high_reg[6]), + .I3(minTime[6]), + .O(ltOp__31_carry_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_5__0 + (.I0(minTimeCounter_high_reg[15]), + .I1(minTime[15]), + .I2(minTimeCounter_high_reg[14]), + .I3(minTime[14]), + .O(ltOp__31_carry_i_5__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_5__1 + (.I0(minTimeCounter_high_reg[23]), + .I1(minTime[23]), + .I2(minTimeCounter_high_reg[22]), + .I3(minTime[22]), + .O(ltOp__31_carry_i_5__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_5__2 + (.I0(minTimeCounter_high_reg[31]), + .I1(minTime[31]), + .I2(minTimeCounter_high_reg[30]), + .I3(minTime[30]), + .O(ltOp__31_carry_i_5__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_6 + (.I0(minTimeCounter_high_reg[5]), + .I1(minTime[5]), + .I2(minTimeCounter_high_reg[4]), + .I3(minTime[4]), + .O(ltOp__31_carry_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_6__0 + (.I0(minTimeCounter_high_reg[13]), + .I1(minTime[13]), + .I2(minTimeCounter_high_reg[12]), + .I3(minTime[12]), + .O(ltOp__31_carry_i_6__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_6__1 + (.I0(minTimeCounter_high_reg[21]), + .I1(minTime[21]), + .I2(minTimeCounter_high_reg[20]), + .I3(minTime[20]), + .O(ltOp__31_carry_i_6__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_6__2 + (.I0(minTimeCounter_high_reg[29]), + .I1(minTime[29]), + .I2(minTimeCounter_high_reg[28]), + .I3(minTime[28]), + .O(ltOp__31_carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_7 + (.I0(minTimeCounter_high_reg[3]), + .I1(minTime[3]), + .I2(minTimeCounter_high_reg[2]), + .I3(minTime[2]), + .O(ltOp__31_carry_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_7__0 + (.I0(minTimeCounter_high_reg[11]), + .I1(minTime[11]), + .I2(minTimeCounter_high_reg[10]), + .I3(minTime[10]), + .O(ltOp__31_carry_i_7__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_7__1 + (.I0(minTimeCounter_high_reg[19]), + .I1(minTime[19]), + .I2(minTimeCounter_high_reg[18]), + .I3(minTime[18]), + .O(ltOp__31_carry_i_7__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_7__2 + (.I0(minTimeCounter_high_reg[27]), + .I1(minTime[27]), + .I2(minTimeCounter_high_reg[26]), + .I3(minTime[26]), + .O(ltOp__31_carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_8 + (.I0(minTimeCounter_high_reg[1]), + .I1(minTime[1]), + .I2(minTimeCounter_high_reg[0]), + .I3(minTime[0]), + .O(ltOp__31_carry_i_8_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_8__0 + (.I0(minTimeCounter_high_reg[9]), + .I1(minTime[9]), + .I2(minTimeCounter_high_reg[8]), + .I3(minTime[8]), + .O(ltOp__31_carry_i_8__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_8__1 + (.I0(minTimeCounter_high_reg[17]), + .I1(minTime[17]), + .I2(minTimeCounter_high_reg[16]), + .I3(minTime[16]), + .O(ltOp__31_carry_i_8__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp__31_carry_i_8__2 + (.I0(minTimeCounter_high_reg[25]), + .I1(minTime[25]), + .I2(minTimeCounter_high_reg[24]), + .I3(minTime[24]), + .O(ltOp__31_carry_i_8__2_n_0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({ltOp_carry__0_n_0,ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry__0_i_1_n_0,ltOp_carry__0_i_2_n_0,ltOp_carry__0_i_3_n_0,ltOp_carry__0_i_4_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({ltOp_carry__0_i_5_n_0,ltOp_carry__0_i_6_n_0,ltOp_carry__0_i_7_n_0,ltOp_carry__0_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__0_i_1 + (.I0(deadTime[15]), + .I1(TimeCounter_reg[15]), + .I2(deadTime[14]), + .I3(TimeCounter_reg[14]), + .O(ltOp_carry__0_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__0_i_2 + (.I0(deadTime[13]), + .I1(TimeCounter_reg[13]), + .I2(deadTime[12]), + .I3(TimeCounter_reg[12]), + .O(ltOp_carry__0_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__0_i_3 + (.I0(deadTime[11]), + .I1(TimeCounter_reg[11]), + .I2(deadTime[10]), + .I3(TimeCounter_reg[10]), + .O(ltOp_carry__0_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__0_i_4 + (.I0(deadTime[9]), + .I1(TimeCounter_reg[9]), + .I2(deadTime[8]), + .I3(TimeCounter_reg[8]), + .O(ltOp_carry__0_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__0_i_5 + (.I0(TimeCounter_reg[15]), + .I1(deadTime[15]), + .I2(TimeCounter_reg[14]), + .I3(deadTime[14]), + .O(ltOp_carry__0_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__0_i_6 + (.I0(TimeCounter_reg[13]), + .I1(deadTime[13]), + .I2(TimeCounter_reg[12]), + .I3(deadTime[12]), + .O(ltOp_carry__0_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__0_i_7 + (.I0(TimeCounter_reg[11]), + .I1(deadTime[11]), + .I2(TimeCounter_reg[10]), + .I3(deadTime[10]), + .O(ltOp_carry__0_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__0_i_8 + (.I0(TimeCounter_reg[9]), + .I1(deadTime[9]), + .I2(TimeCounter_reg[8]), + .I3(deadTime[8]), + .O(ltOp_carry__0_i_8_n_0)); + CARRY4 ltOp_carry__1 + (.CI(ltOp_carry__0_n_0), + .CO({ltOp_carry__1_n_0,ltOp_carry__1_n_1,ltOp_carry__1_n_2,ltOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry__1_i_1_n_0,ltOp_carry__1_i_2_n_0,ltOp_carry__1_i_3_n_0,ltOp_carry__1_i_4_n_0}), + .O(NLW_ltOp_carry__1_O_UNCONNECTED[3:0]), + .S({ltOp_carry__1_i_5_n_0,ltOp_carry__1_i_6_n_0,ltOp_carry__1_i_7_n_0,ltOp_carry__1_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__1_i_1 + (.I0(deadTime[23]), + .I1(TimeCounter_reg[23]), + .I2(deadTime[22]), + .I3(TimeCounter_reg[22]), + .O(ltOp_carry__1_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__1_i_2 + (.I0(deadTime[21]), + .I1(TimeCounter_reg[21]), + .I2(deadTime[20]), + .I3(TimeCounter_reg[20]), + .O(ltOp_carry__1_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__1_i_3 + (.I0(deadTime[19]), + .I1(TimeCounter_reg[19]), + .I2(deadTime[18]), + .I3(TimeCounter_reg[18]), + .O(ltOp_carry__1_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__1_i_4 + (.I0(deadTime[17]), + .I1(TimeCounter_reg[17]), + .I2(deadTime[16]), + .I3(TimeCounter_reg[16]), + .O(ltOp_carry__1_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__1_i_5 + (.I0(TimeCounter_reg[23]), + .I1(deadTime[23]), + .I2(TimeCounter_reg[22]), + .I3(deadTime[22]), + .O(ltOp_carry__1_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__1_i_6 + (.I0(TimeCounter_reg[21]), + .I1(deadTime[21]), + .I2(TimeCounter_reg[20]), + .I3(deadTime[20]), + .O(ltOp_carry__1_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__1_i_7 + (.I0(TimeCounter_reg[19]), + .I1(deadTime[19]), + .I2(TimeCounter_reg[18]), + .I3(deadTime[18]), + .O(ltOp_carry__1_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__1_i_8 + (.I0(TimeCounter_reg[17]), + .I1(deadTime[17]), + .I2(TimeCounter_reg[16]), + .I3(deadTime[16]), + .O(ltOp_carry__1_i_8_n_0)); + CARRY4 ltOp_carry__2 + (.CI(ltOp_carry__1_n_0), + .CO({sel,ltOp_carry__2_n_1,ltOp_carry__2_n_2,ltOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry__2_i_1_n_0,ltOp_carry__2_i_2_n_0,ltOp_carry__2_i_3_n_0,ltOp_carry__2_i_4_n_0}), + .O(NLW_ltOp_carry__2_O_UNCONNECTED[3:0]), + .S({ltOp_carry__2_i_5_n_0,ltOp_carry__2_i_6_n_0,ltOp_carry__2_i_7_n_0,ltOp_carry__2_i_8_n_0})); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__2_i_1 + (.I0(deadTime[31]), + .I1(TimeCounter_reg[31]), + .I2(deadTime[30]), + .I3(TimeCounter_reg[30]), + .O(ltOp_carry__2_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__2_i_2 + (.I0(deadTime[29]), + .I1(TimeCounter_reg[29]), + .I2(deadTime[28]), + .I3(TimeCounter_reg[28]), + .O(ltOp_carry__2_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__2_i_3 + (.I0(deadTime[27]), + .I1(TimeCounter_reg[27]), + .I2(deadTime[26]), + .I3(TimeCounter_reg[26]), + .O(ltOp_carry__2_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__2_i_4 + (.I0(deadTime[25]), + .I1(TimeCounter_reg[25]), + .I2(deadTime[24]), + .I3(TimeCounter_reg[24]), + .O(ltOp_carry__2_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__2_i_5 + (.I0(TimeCounter_reg[31]), + .I1(deadTime[31]), + .I2(TimeCounter_reg[30]), + .I3(deadTime[30]), + .O(ltOp_carry__2_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__2_i_6 + (.I0(TimeCounter_reg[29]), + .I1(deadTime[29]), + .I2(TimeCounter_reg[28]), + .I3(deadTime[28]), + .O(ltOp_carry__2_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__2_i_7 + (.I0(TimeCounter_reg[27]), + .I1(deadTime[27]), + .I2(TimeCounter_reg[26]), + .I3(deadTime[26]), + .O(ltOp_carry__2_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__2_i_8 + (.I0(TimeCounter_reg[25]), + .I1(deadTime[25]), + .I2(TimeCounter_reg[24]), + .I3(deadTime[24]), + .O(ltOp_carry__2_i_8_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry_i_1 + (.I0(deadTime[7]), + .I1(TimeCounter_reg[7]), + .I2(deadTime[6]), + .I3(TimeCounter_reg[6]), + .O(ltOp_carry_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry_i_2 + (.I0(deadTime[5]), + .I1(TimeCounter_reg[5]), + .I2(deadTime[4]), + .I3(TimeCounter_reg[4]), + .O(ltOp_carry_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry_i_3 + (.I0(deadTime[3]), + .I1(TimeCounter_reg[3]), + .I2(deadTime[2]), + .I3(TimeCounter_reg[2]), + .O(ltOp_carry_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry_i_4 + (.I0(deadTime[1]), + .I1(TimeCounter_reg[1]), + .I2(deadTime[0]), + .I3(TimeCounter_reg[0]), + .O(ltOp_carry_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(TimeCounter_reg[7]), + .I1(deadTime[7]), + .I2(TimeCounter_reg[6]), + .I3(deadTime[6]), + .O(ltOp_carry_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(TimeCounter_reg[5]), + .I1(deadTime[5]), + .I2(TimeCounter_reg[4]), + .I3(deadTime[4]), + .O(ltOp_carry_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(TimeCounter_reg[3]), + .I1(deadTime[3]), + .I2(TimeCounter_reg[2]), + .I3(deadTime[2]), + .O(ltOp_carry_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(TimeCounter_reg[1]), + .I1(deadTime[1]), + .I2(TimeCounter_reg[0]), + .I3(deadTime[0]), + .O(ltOp_carry_i_8_n_0)); + LUT6 #( + .INIT(64'h0000000022222F22)) + \minTimeCounter_high[0]_i_1 + (.I0(key1_prev), + .I1(key1_reg_n_0), + .I2(key2_reg_n_0), + .I3(key2_prev), + .I4(breaking_en), + .I5(reset), + .O(\minTimeCounter_high[0]_i_1_n_0 )); + LUT2 #( + .INIT(4'h2)) + \minTimeCounter_high[0]_i_2 + (.I0(ltOp__31_carry__2_n_0), + .I1(reset), + .O(minTimeCounter_high)); + LUT1 #( + .INIT(2'h1)) + \minTimeCounter_high[0]_i_4 + (.I0(minTimeCounter_high_reg[0]), + .O(\minTimeCounter_high[0]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[0] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[0]_i_3_n_7 ), + .Q(minTimeCounter_high_reg[0]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[0]_i_3 + (.CI(1'b0), + .CO({\minTimeCounter_high_reg[0]_i_3_n_0 ,\minTimeCounter_high_reg[0]_i_3_n_1 ,\minTimeCounter_high_reg[0]_i_3_n_2 ,\minTimeCounter_high_reg[0]_i_3_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\minTimeCounter_high_reg[0]_i_3_n_4 ,\minTimeCounter_high_reg[0]_i_3_n_5 ,\minTimeCounter_high_reg[0]_i_3_n_6 ,\minTimeCounter_high_reg[0]_i_3_n_7 }), + .S({minTimeCounter_high_reg[3:1],\minTimeCounter_high[0]_i_4_n_0 })); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[10] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[8]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[10]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[11] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[8]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[11]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[12] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[12]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[12]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[12]_i_1 + (.CI(\minTimeCounter_high_reg[8]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[12]_i_1_n_0 ,\minTimeCounter_high_reg[12]_i_1_n_1 ,\minTimeCounter_high_reg[12]_i_1_n_2 ,\minTimeCounter_high_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[12]_i_1_n_4 ,\minTimeCounter_high_reg[12]_i_1_n_5 ,\minTimeCounter_high_reg[12]_i_1_n_6 ,\minTimeCounter_high_reg[12]_i_1_n_7 }), + .S(minTimeCounter_high_reg[15:12])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[13] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[12]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[13]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[14] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[12]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[14]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[15] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[12]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[15]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[16] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[16]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[16]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[16]_i_1 + (.CI(\minTimeCounter_high_reg[12]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[16]_i_1_n_0 ,\minTimeCounter_high_reg[16]_i_1_n_1 ,\minTimeCounter_high_reg[16]_i_1_n_2 ,\minTimeCounter_high_reg[16]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[16]_i_1_n_4 ,\minTimeCounter_high_reg[16]_i_1_n_5 ,\minTimeCounter_high_reg[16]_i_1_n_6 ,\minTimeCounter_high_reg[16]_i_1_n_7 }), + .S(minTimeCounter_high_reg[19:16])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[17] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[16]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[17]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[18] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[16]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[18]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[19] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[16]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[19]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[1] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[0]_i_3_n_6 ), + .Q(minTimeCounter_high_reg[1]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[20] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[20]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[20]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[20]_i_1 + (.CI(\minTimeCounter_high_reg[16]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[20]_i_1_n_0 ,\minTimeCounter_high_reg[20]_i_1_n_1 ,\minTimeCounter_high_reg[20]_i_1_n_2 ,\minTimeCounter_high_reg[20]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[20]_i_1_n_4 ,\minTimeCounter_high_reg[20]_i_1_n_5 ,\minTimeCounter_high_reg[20]_i_1_n_6 ,\minTimeCounter_high_reg[20]_i_1_n_7 }), + .S(minTimeCounter_high_reg[23:20])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[21] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[20]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[21]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[22] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[20]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[22]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[23] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[20]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[23]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[24] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[24]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[24]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[24]_i_1 + (.CI(\minTimeCounter_high_reg[20]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[24]_i_1_n_0 ,\minTimeCounter_high_reg[24]_i_1_n_1 ,\minTimeCounter_high_reg[24]_i_1_n_2 ,\minTimeCounter_high_reg[24]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[24]_i_1_n_4 ,\minTimeCounter_high_reg[24]_i_1_n_5 ,\minTimeCounter_high_reg[24]_i_1_n_6 ,\minTimeCounter_high_reg[24]_i_1_n_7 }), + .S(minTimeCounter_high_reg[27:24])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[25] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[24]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[25]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[26] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[24]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[26]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[27] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[24]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[27]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[28] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[28]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[28]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[28]_i_1 + (.CI(\minTimeCounter_high_reg[24]_i_1_n_0 ), + .CO({\NLW_minTimeCounter_high_reg[28]_i_1_CO_UNCONNECTED [3],\minTimeCounter_high_reg[28]_i_1_n_1 ,\minTimeCounter_high_reg[28]_i_1_n_2 ,\minTimeCounter_high_reg[28]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[28]_i_1_n_4 ,\minTimeCounter_high_reg[28]_i_1_n_5 ,\minTimeCounter_high_reg[28]_i_1_n_6 ,\minTimeCounter_high_reg[28]_i_1_n_7 }), + .S(minTimeCounter_high_reg[31:28])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[29] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[28]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[29]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[2] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[0]_i_3_n_5 ), + .Q(minTimeCounter_high_reg[2]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[30] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[28]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[30]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[31] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[28]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[31]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[3] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[0]_i_3_n_4 ), + .Q(minTimeCounter_high_reg[3]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[4] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[4]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[4]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[4]_i_1 + (.CI(\minTimeCounter_high_reg[0]_i_3_n_0 ), + .CO({\minTimeCounter_high_reg[4]_i_1_n_0 ,\minTimeCounter_high_reg[4]_i_1_n_1 ,\minTimeCounter_high_reg[4]_i_1_n_2 ,\minTimeCounter_high_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[4]_i_1_n_4 ,\minTimeCounter_high_reg[4]_i_1_n_5 ,\minTimeCounter_high_reg[4]_i_1_n_6 ,\minTimeCounter_high_reg[4]_i_1_n_7 }), + .S(minTimeCounter_high_reg[7:4])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[5] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[4]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[5]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[6] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[4]_i_1_n_5 ), + .Q(minTimeCounter_high_reg[6]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[7] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[4]_i_1_n_4 ), + .Q(minTimeCounter_high_reg[7]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[8] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[8]_i_1_n_7 ), + .Q(minTimeCounter_high_reg[8]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_high_reg[8]_i_1 + (.CI(\minTimeCounter_high_reg[4]_i_1_n_0 ), + .CO({\minTimeCounter_high_reg[8]_i_1_n_0 ,\minTimeCounter_high_reg[8]_i_1_n_1 ,\minTimeCounter_high_reg[8]_i_1_n_2 ,\minTimeCounter_high_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_high_reg[8]_i_1_n_4 ,\minTimeCounter_high_reg[8]_i_1_n_5 ,\minTimeCounter_high_reg[8]_i_1_n_6 ,\minTimeCounter_high_reg[8]_i_1_n_7 }), + .S(minTimeCounter_high_reg[11:8])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_high_reg[9] + (.C(externalCLK), + .CE(minTimeCounter_high), + .D(\minTimeCounter_high_reg[8]_i_1_n_6 ), + .Q(minTimeCounter_high_reg[9]), + .R(\minTimeCounter_high[0]_i_1_n_0 )); + LUT5 #( + .INIT(32'h0000440F)) + \minTimeCounter_low[0]_i_1 + (.I0(key2_reg_n_0), + .I1(key2_prev), + .I2(\minTimeCounter_low[0]_i_4_n_0 ), + .I3(breaking_en), + .I4(reset), + .O(\minTimeCounter_low[0]_i_1_n_0 )); + LUT2 #( + .INIT(4'h2)) + \minTimeCounter_low[0]_i_2 + (.I0(ltOp__15_carry__2_n_0), + .I1(reset), + .O(minTimeCounter_low)); + LUT4 #( + .INIT(16'hD0DD)) + \minTimeCounter_low[0]_i_4 + (.I0(key4_prev), + .I1(key4_reg_n_0), + .I2(key3_reg_n_0), + .I3(key3_prev), + .O(\minTimeCounter_low[0]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \minTimeCounter_low[0]_i_5 + (.I0(minTimeCounter_low_reg[0]), + .O(\minTimeCounter_low[0]_i_5_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[0] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[0]_i_3_n_7 ), + .Q(minTimeCounter_low_reg[0]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[0]_i_3 + (.CI(1'b0), + .CO({\minTimeCounter_low_reg[0]_i_3_n_0 ,\minTimeCounter_low_reg[0]_i_3_n_1 ,\minTimeCounter_low_reg[0]_i_3_n_2 ,\minTimeCounter_low_reg[0]_i_3_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\minTimeCounter_low_reg[0]_i_3_n_4 ,\minTimeCounter_low_reg[0]_i_3_n_5 ,\minTimeCounter_low_reg[0]_i_3_n_6 ,\minTimeCounter_low_reg[0]_i_3_n_7 }), + .S({minTimeCounter_low_reg[3:1],\minTimeCounter_low[0]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[10] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[8]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[10]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[11] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[8]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[11]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[12] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[12]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[12]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[12]_i_1 + (.CI(\minTimeCounter_low_reg[8]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[12]_i_1_n_0 ,\minTimeCounter_low_reg[12]_i_1_n_1 ,\minTimeCounter_low_reg[12]_i_1_n_2 ,\minTimeCounter_low_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[12]_i_1_n_4 ,\minTimeCounter_low_reg[12]_i_1_n_5 ,\minTimeCounter_low_reg[12]_i_1_n_6 ,\minTimeCounter_low_reg[12]_i_1_n_7 }), + .S(minTimeCounter_low_reg[15:12])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[13] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[12]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[13]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[14] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[12]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[14]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[15] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[12]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[15]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[16] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[16]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[16]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[16]_i_1 + (.CI(\minTimeCounter_low_reg[12]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[16]_i_1_n_0 ,\minTimeCounter_low_reg[16]_i_1_n_1 ,\minTimeCounter_low_reg[16]_i_1_n_2 ,\minTimeCounter_low_reg[16]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[16]_i_1_n_4 ,\minTimeCounter_low_reg[16]_i_1_n_5 ,\minTimeCounter_low_reg[16]_i_1_n_6 ,\minTimeCounter_low_reg[16]_i_1_n_7 }), + .S(minTimeCounter_low_reg[19:16])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[17] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[16]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[17]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[18] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[16]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[18]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[19] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[16]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[19]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[1] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[0]_i_3_n_6 ), + .Q(minTimeCounter_low_reg[1]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[20] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[20]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[20]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[20]_i_1 + (.CI(\minTimeCounter_low_reg[16]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[20]_i_1_n_0 ,\minTimeCounter_low_reg[20]_i_1_n_1 ,\minTimeCounter_low_reg[20]_i_1_n_2 ,\minTimeCounter_low_reg[20]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[20]_i_1_n_4 ,\minTimeCounter_low_reg[20]_i_1_n_5 ,\minTimeCounter_low_reg[20]_i_1_n_6 ,\minTimeCounter_low_reg[20]_i_1_n_7 }), + .S(minTimeCounter_low_reg[23:20])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[21] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[20]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[21]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[22] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[20]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[22]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[23] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[20]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[23]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[24] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[24]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[24]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[24]_i_1 + (.CI(\minTimeCounter_low_reg[20]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[24]_i_1_n_0 ,\minTimeCounter_low_reg[24]_i_1_n_1 ,\minTimeCounter_low_reg[24]_i_1_n_2 ,\minTimeCounter_low_reg[24]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[24]_i_1_n_4 ,\minTimeCounter_low_reg[24]_i_1_n_5 ,\minTimeCounter_low_reg[24]_i_1_n_6 ,\minTimeCounter_low_reg[24]_i_1_n_7 }), + .S(minTimeCounter_low_reg[27:24])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[25] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[24]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[25]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[26] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[24]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[26]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[27] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[24]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[27]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[28] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[28]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[28]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[28]_i_1 + (.CI(\minTimeCounter_low_reg[24]_i_1_n_0 ), + .CO({\NLW_minTimeCounter_low_reg[28]_i_1_CO_UNCONNECTED [3],\minTimeCounter_low_reg[28]_i_1_n_1 ,\minTimeCounter_low_reg[28]_i_1_n_2 ,\minTimeCounter_low_reg[28]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[28]_i_1_n_4 ,\minTimeCounter_low_reg[28]_i_1_n_5 ,\minTimeCounter_low_reg[28]_i_1_n_6 ,\minTimeCounter_low_reg[28]_i_1_n_7 }), + .S(minTimeCounter_low_reg[31:28])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[29] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[28]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[29]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[2] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[0]_i_3_n_5 ), + .Q(minTimeCounter_low_reg[2]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[30] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[28]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[30]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[31] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[28]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[31]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[3] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[0]_i_3_n_4 ), + .Q(minTimeCounter_low_reg[3]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[4] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[4]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[4]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[4]_i_1 + (.CI(\minTimeCounter_low_reg[0]_i_3_n_0 ), + .CO({\minTimeCounter_low_reg[4]_i_1_n_0 ,\minTimeCounter_low_reg[4]_i_1_n_1 ,\minTimeCounter_low_reg[4]_i_1_n_2 ,\minTimeCounter_low_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[4]_i_1_n_4 ,\minTimeCounter_low_reg[4]_i_1_n_5 ,\minTimeCounter_low_reg[4]_i_1_n_6 ,\minTimeCounter_low_reg[4]_i_1_n_7 }), + .S(minTimeCounter_low_reg[7:4])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[5] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[4]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[5]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[6] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[4]_i_1_n_5 ), + .Q(minTimeCounter_low_reg[6]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[7] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[4]_i_1_n_4 ), + .Q(minTimeCounter_low_reg[7]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[8] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[8]_i_1_n_7 ), + .Q(minTimeCounter_low_reg[8]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + CARRY4 \minTimeCounter_low_reg[8]_i_1 + (.CI(\minTimeCounter_low_reg[4]_i_1_n_0 ), + .CO({\minTimeCounter_low_reg[8]_i_1_n_0 ,\minTimeCounter_low_reg[8]_i_1_n_1 ,\minTimeCounter_low_reg[8]_i_1_n_2 ,\minTimeCounter_low_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\minTimeCounter_low_reg[8]_i_1_n_4 ,\minTimeCounter_low_reg[8]_i_1_n_5 ,\minTimeCounter_low_reg[8]_i_1_n_6 ,\minTimeCounter_low_reg[8]_i_1_n_7 }), + .S(minTimeCounter_low_reg[11:8])); + FDRE #( + .INIT(1'b0)) + \minTimeCounter_low_reg[9] + (.C(externalCLK), + .CE(minTimeCounter_low), + .D(\minTimeCounter_low_reg[8]_i_1_n_6 ), + .Q(minTimeCounter_low_reg[9]), + .R(\minTimeCounter_low[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'hEEFFEEEEE200E2E2)) + minTimeEr_i_1 + (.I0(minTimeEr_i_2_n_0), + .I1(minTimeEr_i_3_n_0), + .I2(minTimeEr_i_4_n_0), + .I3(minTimeEr_i_5_n_0), + .I4(minTimeEr_i_6_n_0), + .I5(minTimeEr_reg_0), + .O(minTimeEr_i_1_n_0)); + LUT4 #( + .INIT(16'h0111)) + minTimeEr_i_2 + (.I0(reset), + .I1(breaking_en), + .I2(minTimeEr_i_6_n_0), + .I3(minTimeEr_i_7_n_0), + .O(minTimeEr_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h2)) + minTimeEr_i_3 + (.I0(breaking_en), + .I1(reset), + .O(minTimeEr_i_3_n_0)); + LUT6 #( + .INIT(64'h040404FF00000000)) + minTimeEr_i_4 + (.I0(minTimeOK_low), + .I1(key2_reg_n_0), + .I2(key2_prev), + .I3(minTimeEr_i_8_n_0), + .I4(minTimeOK_high), + .I5(minTime_En), + .O(minTimeEr_i_4_n_0)); + LUT6 #( + .INIT(64'h55555555F755F7F7)) + minTimeEr_i_5 + (.I0(minTimeEr_i_9_n_0), + .I1(key2_prev), + .I2(key2_reg_n_0), + .I3(key1_reg_n_0), + .I4(key1_prev), + .I5(minTimeEr_i_7_n_0), + .O(minTimeEr_i_5_n_0)); + LUT6 #( + .INIT(64'hFBFFFFFFBBFBFBFF)) + minTimeEr_i_6 + (.I0(minTimeOK_low), + .I1(minTime_En), + .I2(key3_prev), + .I3(key3_reg_n_0), + .I4(key4_reg_n_0), + .I5(key4_prev), + .O(minTimeEr_i_6_n_0)); + LUT6 #( + .INIT(64'hFFDFDDDDFFDFFFDF)) + minTimeEr_i_7 + (.I0(minTime_En), + .I1(minTimeOK_high), + .I2(key2_reg_n_0), + .I3(key2_prev), + .I4(key1_prev), + .I5(key1_reg_n_0), + .O(minTimeEr_i_7_n_0)); + LUT2 #( + .INIT(4'hB)) + minTimeEr_i_8 + (.I0(key1_prev), + .I1(key1_reg_n_0), + .O(minTimeEr_i_8_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h1)) + minTimeEr_i_9 + (.I0(breaking_en), + .I1(reset), + .O(minTimeEr_i_9_n_0)); + FDRE #( + .INIT(1'b0)) + minTimeEr_reg + (.C(externalCLK), + .CE(1'b1), + .D(minTimeEr_i_1_n_0), + .Q(minTimeEr_reg_0), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h00AB)) + minTimeOK_high_i_1 + (.I0(minTimeOK_high), + .I1(ltOp__31_carry__2_n_0), + .I2(reset), + .I3(\minTimeCounter_high[0]_i_1_n_0 ), + .O(minTimeOK_high_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + minTimeOK_high_reg + (.C(externalCLK), + .CE(1'b1), + .D(minTimeOK_high_i_1_n_0), + .Q(minTimeOK_high), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'h00AB)) + minTimeOK_low_i_1 + (.I0(minTimeOK_low), + .I1(ltOp__15_carry__2_n_0), + .I2(reset), + .I3(\minTimeCounter_low[0]_i_1_n_0 ), + .O(minTimeOK_low_i_1_n_0)); + FDRE #( + .INIT(1'b1)) + minTimeOK_low_reg + (.C(externalCLK), + .CE(1'b1), + .D(minTimeOK_low_i_1_n_0), + .Q(minTimeOK_low), + .R(1'b0)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1_sim_netlist.vhdl b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1_sim_netlist.vhdl new file mode 100644 index 0000000..a1cdce9 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1_sim_netlist.vhdl @@ -0,0 +1,4183 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Fri Jun 11 07:49:57 2021 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top Inverter_3lvl_P0N_3lvl_1_1 -prefix +-- Inverter_3lvl_P0N_3lvl_1_1_ Inverter_3lvl_P0N_3lvl_0_4_sim_netlist.vhdl +-- Design : Inverter_3lvl_P0N_3lvl_0_4 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Inverter_3lvl_P0N_3lvl_1_1_P0N_3lvl is + port ( + minTimeEr_reg_0 : out STD_LOGIC; + PWM_out_0 : out STD_LOGIC; + PWM_out_1 : out STD_LOGIC; + PWM_out_2 : out STD_LOGIC; + PWM_out_3 : out STD_LOGIC; + reset : in STD_LOGIC; + externalCLK : in STD_LOGIC; + TKin0 : in STD_LOGIC; + TKin1 : in STD_LOGIC; + breaking_en : in STD_LOGIC; + er : in STD_LOGIC; + ready : in STD_LOGIC; + minTime_En : in STD_LOGIC; + deadTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + minTime : in STD_LOGIC_VECTOR ( 31 downto 0 ) + ); +end Inverter_3lvl_P0N_3lvl_1_1_P0N_3lvl; + +architecture STRUCTURE of Inverter_3lvl_P0N_3lvl_1_1_P0N_3lvl is + signal \FSM_onehot_lineconfig[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[0]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[1]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[2]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[2]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[3]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[4]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[5]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[5]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[5]_i_3_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_3_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_4_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_5_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig[6]_i_6_n_0\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[0]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[1]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[2]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[3]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[4]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[5]\ : STD_LOGIC; + signal \FSM_onehot_lineconfig_reg_n_0_[6]\ : STD_LOGIC; + signal PWM_out_0_i_1_n_0 : STD_LOGIC; + signal PWM_out_1_i_1_n_0 : STD_LOGIC; + signal PWM_out_2_i_1_n_0 : STD_LOGIC; + signal PWM_out_3_i_1_n_0 : STD_LOGIC; + signal TKin0_triggered : STD_LOGIC; + signal TKin0_triggered28_out : STD_LOGIC; + signal TKin0_triggered_i_1_n_0 : STD_LOGIC; + signal TKin1_triggered : STD_LOGIC; + signal TKin1_triggered_i_1_n_0 : STD_LOGIC; + signal \TimeCounter[0]_i_2_n_0\ : STD_LOGIC; + signal TimeCounter_reg : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \TimeCounter_reg[0]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[0]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[12]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[16]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[20]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[24]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[28]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \TimeCounter_reg[8]_i_1_n_7\ : STD_LOGIC; + signal deadTimeCounterReset_i_1_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_2_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_3_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_4_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_5_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_6_n_0 : STD_LOGIC; + signal deadTimeCounterReset_i_7_n_0 : STD_LOGIC; + signal deadTimeCounterReset_reg_n_0 : STD_LOGIC; + signal deadTimeOK : STD_LOGIC; + signal deadTimeOK_i_1_n_0 : STD_LOGIC; + signal key1_i_1_n_0 : STD_LOGIC; + signal key1_i_2_n_0 : STD_LOGIC; + signal key1_prev : STD_LOGIC; + signal key1_reg_n_0 : STD_LOGIC; + signal key2_i_2_n_0 : STD_LOGIC; + signal key2_prev : STD_LOGIC; + signal key2_reg_n_0 : STD_LOGIC; + signal key3 : STD_LOGIC; + signal key3_i_1_n_0 : STD_LOGIC; + signal key3_prev : STD_LOGIC; + signal key3_reg_n_0 : STD_LOGIC; + signal key4_i_1_n_0 : STD_LOGIC; + signal key4_prev : STD_LOGIC; + signal key4_reg_n_0 : STD_LOGIC; + signal \ltOp__15_carry__0_i_1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_3_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_4_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_5_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_6_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_7_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_i_8_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__0_n_1\ : STD_LOGIC; + signal \ltOp__15_carry__0_n_2\ : STD_LOGIC; + signal \ltOp__15_carry__0_n_3\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_3_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_4_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_5_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_6_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_7_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_i_8_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__1_n_1\ : STD_LOGIC; + signal \ltOp__15_carry__1_n_2\ : STD_LOGIC; + signal \ltOp__15_carry__1_n_3\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_3_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_4_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_5_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_6_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_7_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_i_8_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry__2_n_1\ : STD_LOGIC; + signal \ltOp__15_carry__2_n_2\ : STD_LOGIC; + signal \ltOp__15_carry__2_n_3\ : STD_LOGIC; + signal \ltOp__15_carry_i_1_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_2_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_3_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_4_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_5_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_6_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_7_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_i_8_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_n_0\ : STD_LOGIC; + signal \ltOp__15_carry_n_1\ : STD_LOGIC; + signal \ltOp__15_carry_n_2\ : STD_LOGIC; + signal \ltOp__15_carry_n_3\ : STD_LOGIC; + signal \ltOp__31_carry__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry__0_n_1\ : STD_LOGIC; + signal \ltOp__31_carry__0_n_2\ : STD_LOGIC; + signal \ltOp__31_carry__0_n_3\ : STD_LOGIC; + signal \ltOp__31_carry__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry__1_n_1\ : STD_LOGIC; + signal \ltOp__31_carry__1_n_2\ : STD_LOGIC; + signal \ltOp__31_carry__1_n_3\ : STD_LOGIC; + signal \ltOp__31_carry__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry__2_n_1\ : STD_LOGIC; + signal \ltOp__31_carry__2_n_2\ : STD_LOGIC; + signal \ltOp__31_carry__2_n_3\ : STD_LOGIC; + signal \ltOp__31_carry_i_1__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_1__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_1__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_2__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_2__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_2__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_3__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_3__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_3__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_3_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_4__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_4__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_4__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_4_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_5__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_5__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_5__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_5_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_6__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_6__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_6__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_6_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_7__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_7__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_7__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_7_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_8__0_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_8__1_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_8__2_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_i_8_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_n_0\ : STD_LOGIC; + signal \ltOp__31_carry_n_1\ : STD_LOGIC; + signal \ltOp__31_carry_n_2\ : STD_LOGIC; + signal \ltOp__31_carry_n_3\ : STD_LOGIC; + signal \ltOp_carry__0_i_1_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_2_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_3_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_4_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_5_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_6_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_7_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_8_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal \ltOp_carry__1_i_1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_2_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_3_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_4_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_5_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_6_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_7_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_i_8_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_0\ : STD_LOGIC; + signal \ltOp_carry__1_n_1\ : STD_LOGIC; + signal \ltOp_carry__1_n_2\ : STD_LOGIC; + signal \ltOp_carry__1_n_3\ : STD_LOGIC; + signal \ltOp_carry__2_i_1_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_2_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_3_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_4_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_5_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_6_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_7_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_i_8_n_0\ : STD_LOGIC; + signal \ltOp_carry__2_n_1\ : STD_LOGIC; + signal \ltOp_carry__2_n_2\ : STD_LOGIC; + signal \ltOp_carry__2_n_3\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal minTimeCounter_high : STD_LOGIC; + signal \minTimeCounter_high[0]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high[0]_i_4_n_0\ : STD_LOGIC; + signal minTimeCounter_high_reg : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \minTimeCounter_high_reg[0]_i_3_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[0]_i_3_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[12]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[16]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[20]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[24]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[28]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_high_reg[8]_i_1_n_7\ : STD_LOGIC; + signal minTimeCounter_low : STD_LOGIC; + signal \minTimeCounter_low[0]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low[0]_i_4_n_0\ : STD_LOGIC; + signal \minTimeCounter_low[0]_i_5_n_0\ : STD_LOGIC; + signal minTimeCounter_low_reg : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \minTimeCounter_low_reg[0]_i_3_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[0]_i_3_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[12]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[16]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[20]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[24]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[28]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \minTimeCounter_low_reg[8]_i_1_n_7\ : STD_LOGIC; + signal minTimeEr_i_1_n_0 : STD_LOGIC; + signal minTimeEr_i_2_n_0 : STD_LOGIC; + signal minTimeEr_i_3_n_0 : STD_LOGIC; + signal minTimeEr_i_4_n_0 : STD_LOGIC; + signal minTimeEr_i_5_n_0 : STD_LOGIC; + signal minTimeEr_i_6_n_0 : STD_LOGIC; + signal minTimeEr_i_7_n_0 : STD_LOGIC; + signal minTimeEr_i_8_n_0 : STD_LOGIC; + signal minTimeEr_i_9_n_0 : STD_LOGIC; + signal \^mintimeer_reg_0\ : STD_LOGIC; + signal minTimeOK_high : STD_LOGIC; + signal minTimeOK_high_i_1_n_0 : STD_LOGIC; + signal minTimeOK_low : STD_LOGIC; + signal minTimeOK_low_i_1_n_0 : STD_LOGIC; + signal p_0_in : STD_LOGIC; + signal sel : STD_LOGIC; + signal \NLW_TimeCounter_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_ltOp__15_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__15_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__15_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__15_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__31_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__31_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__31_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp__31_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_minTimeCounter_high_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_minTimeCounter_low_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[0]_i_2\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[2]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[4]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[5]_i_2\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[6]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[6]_i_3\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \FSM_onehot_lineconfig[6]_i_6\ : label is "soft_lutpair2"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[0]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[1]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[2]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[3]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[4]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[5]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_lineconfig_reg[6]\ : label is "p:0001000,zero:0100000,n:0000010,zero_p:0010000,closed:0000001,tech_closed:0000100,zero_n:1000000"; + attribute SOFT_HLUTNM of PWM_out_0_i_1 : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of PWM_out_1_i_1 : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of deadTimeCounterReset_i_2 : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of deadTimeCounterReset_i_5 : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of deadTimeCounterReset_i_6 : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of deadTimeOK_i_1 : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of key1_i_2 : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of minTimeEr_i_3 : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of minTimeEr_i_9 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of minTimeOK_high_i_1 : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of minTimeOK_low_i_1 : label is "soft_lutpair3"; +begin + minTimeEr_reg_0 <= \^mintimeer_reg_0\; +\FSM_onehot_lineconfig[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFE00000000" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I4 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I5 => \FSM_onehot_lineconfig[0]_i_2_n_0\, + O => \FSM_onehot_lineconfig[0]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[0]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => TKin1, + I1 => TKin0, + O => \FSM_onehot_lineconfig[0]_i_2_n_0\ + ); +\FSM_onehot_lineconfig[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1000FFFF00000000" + ) + port map ( + I0 => TKin1, + I1 => TKin1_triggered, + I2 => TKin0_triggered, + I3 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I4 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I5 => TKin0, + O => \FSM_onehot_lineconfig[1]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00EFEF0F" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I2 => \FSM_onehot_lineconfig[2]_i_2_n_0\, + I3 => TKin0, + I4 => TKin1, + O => \FSM_onehot_lineconfig[2]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"900990099009FFFF" + ) + port map ( + I0 => TKin1, + I1 => TKin1_triggered, + I2 => TKin0, + I3 => TKin0_triggered, + I4 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I5 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + O => \FSM_onehot_lineconfig[2]_i_2_n_0\ + ); +\FSM_onehot_lineconfig[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000055D50000" + ) + port map ( + I0 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I2 => TKin1_triggered, + I3 => TKin0_triggered, + I4 => TKin1, + I5 => TKin0, + O => \FSM_onehot_lineconfig[3]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2230" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I1 => TKin0, + I2 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I3 => TKin1, + O => \FSM_onehot_lineconfig[4]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0CFF0C0D00050005" + ) + port map ( + I0 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I2 => TKin1, + I3 => TKin0, + I4 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I5 => \FSM_onehot_lineconfig[5]_i_3_n_0\, + O => \FSM_onehot_lineconfig[5]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[5]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + O => \FSM_onehot_lineconfig[5]_i_2_n_0\ + ); +\FSM_onehot_lineconfig[5]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TKin0_triggered, + I1 => TKin0, + I2 => TKin1_triggered, + I3 => TKin1, + O => \FSM_onehot_lineconfig[5]_i_3_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => \FSM_onehot_lineconfig[6]_i_3_n_0\, + I1 => \FSM_onehot_lineconfig[6]_i_4_n_0\, + I2 => breaking_en, + O => \FSM_onehot_lineconfig[6]_i_1_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"5504" + ) + port map ( + I0 => TKin1, + I1 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I2 => TKin0, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + O => \FSM_onehot_lineconfig[6]_i_2_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFEECAE" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I2 => TKin1, + I3 => TKin0, + I4 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + O => \FSM_onehot_lineconfig[6]_i_3_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AABAAAAAFFFFAAAA" + ) + port map ( + I0 => \FSM_onehot_lineconfig[6]_i_5_n_0\, + I1 => er, + I2 => ready, + I3 => \FSM_onehot_lineconfig[6]_i_6_n_0\, + I4 => deadTimeOK, + I5 => \FSM_onehot_lineconfig[2]_i_2_n_0\, + O => \FSM_onehot_lineconfig[6]_i_4_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FC88A0A8" + ) + port map ( + I0 => deadTimeOK, + I1 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I3 => TKin1, + I4 => TKin0, + O => \FSM_onehot_lineconfig[6]_i_5_n_0\ + ); +\FSM_onehot_lineconfig[6]_i_6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF232323" + ) + port map ( + I0 => deadTimeCounterReset_reg_n_0, + I1 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I3 => TKin1, + I4 => TKin0, + O => \FSM_onehot_lineconfig[6]_i_6_n_0\ + ); +\FSM_onehot_lineconfig_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[0]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[0]\, + S => reset + ); +\FSM_onehot_lineconfig_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[1]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[1]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[2]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[2]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[3]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[3]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[4]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[4]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[5]_i_1_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[5]\, + R => reset + ); +\FSM_onehot_lineconfig_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => \FSM_onehot_lineconfig[6]_i_1_n_0\, + D => \FSM_onehot_lineconfig[6]_i_2_n_0\, + Q => \FSM_onehot_lineconfig_reg_n_0_[6]\, + R => reset + ); +PWM_out_0_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFEF" + ) + port map ( + I0 => key1_reg_n_0, + I1 => er, + I2 => ready, + I3 => \^mintimeer_reg_0\, + O => PWM_out_0_i_1_n_0 + ); +PWM_out_0_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => PWM_out_0_i_1_n_0, + Q => PWM_out_0, + R => '0' + ); +PWM_out_1_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFEF" + ) + port map ( + I0 => key2_reg_n_0, + I1 => er, + I2 => ready, + I3 => \^mintimeer_reg_0\, + O => PWM_out_1_i_1_n_0 + ); +PWM_out_1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => PWM_out_1_i_1_n_0, + Q => PWM_out_1, + R => '0' + ); +PWM_out_2_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFEF" + ) + port map ( + I0 => key3_reg_n_0, + I1 => \^mintimeer_reg_0\, + I2 => ready, + I3 => er, + I4 => breaking_en, + O => PWM_out_2_i_1_n_0 + ); +PWM_out_2_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => PWM_out_2_i_1_n_0, + Q => PWM_out_2, + R => '0' + ); +PWM_out_3_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFEF" + ) + port map ( + I0 => key4_reg_n_0, + I1 => \^mintimeer_reg_0\, + I2 => ready, + I3 => er, + I4 => breaking_en, + O => PWM_out_3_i_1_n_0 + ); +PWM_out_3_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => PWM_out_3_i_1_n_0, + Q => PWM_out_3, + R => '0' + ); +TKin0_triggered_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA08FFFFAA080000" + ) + port map ( + I0 => TKin0, + I1 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I2 => TKin1, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I4 => TKin0_triggered28_out, + I5 => TKin0_triggered, + O => TKin0_triggered_i_1_n_0 + ); +TKin0_triggered_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => TKin0_triggered_i_1_n_0, + Q => TKin0_triggered, + R => '0' + ); +TKin1_triggered_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA08FFFFAA080000" + ) + port map ( + I0 => TKin1, + I1 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I2 => TKin0, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I4 => TKin0_triggered28_out, + I5 => TKin1_triggered, + O => TKin1_triggered_i_1_n_0 + ); +TKin1_triggered_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"22AA22A820AA2020" + ) + port map ( + I0 => minTimeEr_i_9_n_0, + I1 => TKin1, + I2 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I3 => TKin0, + I4 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I5 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + O => TKin0_triggered28_out + ); +TKin1_triggered_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => TKin1_triggered_i_1_n_0, + Q => TKin1_triggered, + R => '0' + ); +\TimeCounter[0]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => TimeCounter_reg(0), + O => \TimeCounter[0]_i_2_n_0\ + ); +\TimeCounter_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[0]_i_1_n_7\, + Q => TimeCounter_reg(0), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[0]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \TimeCounter_reg[0]_i_1_n_0\, + CO(2) => \TimeCounter_reg[0]_i_1_n_1\, + CO(1) => \TimeCounter_reg[0]_i_1_n_2\, + CO(0) => \TimeCounter_reg[0]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \TimeCounter_reg[0]_i_1_n_4\, + O(2) => \TimeCounter_reg[0]_i_1_n_5\, + O(1) => \TimeCounter_reg[0]_i_1_n_6\, + O(0) => \TimeCounter_reg[0]_i_1_n_7\, + S(3 downto 1) => TimeCounter_reg(3 downto 1), + S(0) => \TimeCounter[0]_i_2_n_0\ + ); +\TimeCounter_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[8]_i_1_n_5\, + Q => TimeCounter_reg(10), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[8]_i_1_n_4\, + Q => TimeCounter_reg(11), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[12]_i_1_n_7\, + Q => TimeCounter_reg(12), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[8]_i_1_n_0\, + CO(3) => \TimeCounter_reg[12]_i_1_n_0\, + CO(2) => \TimeCounter_reg[12]_i_1_n_1\, + CO(1) => \TimeCounter_reg[12]_i_1_n_2\, + CO(0) => \TimeCounter_reg[12]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[12]_i_1_n_4\, + O(2) => \TimeCounter_reg[12]_i_1_n_5\, + O(1) => \TimeCounter_reg[12]_i_1_n_6\, + O(0) => \TimeCounter_reg[12]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(15 downto 12) + ); +\TimeCounter_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[12]_i_1_n_6\, + Q => TimeCounter_reg(13), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[12]_i_1_n_5\, + Q => TimeCounter_reg(14), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[12]_i_1_n_4\, + Q => TimeCounter_reg(15), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[16]_i_1_n_7\, + Q => TimeCounter_reg(16), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[16]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[12]_i_1_n_0\, + CO(3) => \TimeCounter_reg[16]_i_1_n_0\, + CO(2) => \TimeCounter_reg[16]_i_1_n_1\, + CO(1) => \TimeCounter_reg[16]_i_1_n_2\, + CO(0) => \TimeCounter_reg[16]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[16]_i_1_n_4\, + O(2) => \TimeCounter_reg[16]_i_1_n_5\, + O(1) => \TimeCounter_reg[16]_i_1_n_6\, + O(0) => \TimeCounter_reg[16]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(19 downto 16) + ); +\TimeCounter_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[16]_i_1_n_6\, + Q => TimeCounter_reg(17), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[16]_i_1_n_5\, + Q => TimeCounter_reg(18), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[16]_i_1_n_4\, + Q => TimeCounter_reg(19), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[0]_i_1_n_6\, + Q => TimeCounter_reg(1), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[20]_i_1_n_7\, + Q => TimeCounter_reg(20), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[20]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[16]_i_1_n_0\, + CO(3) => \TimeCounter_reg[20]_i_1_n_0\, + CO(2) => \TimeCounter_reg[20]_i_1_n_1\, + CO(1) => \TimeCounter_reg[20]_i_1_n_2\, + CO(0) => \TimeCounter_reg[20]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[20]_i_1_n_4\, + O(2) => \TimeCounter_reg[20]_i_1_n_5\, + O(1) => \TimeCounter_reg[20]_i_1_n_6\, + O(0) => \TimeCounter_reg[20]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(23 downto 20) + ); +\TimeCounter_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[20]_i_1_n_6\, + Q => TimeCounter_reg(21), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[20]_i_1_n_5\, + Q => TimeCounter_reg(22), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[20]_i_1_n_4\, + Q => TimeCounter_reg(23), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[24]_i_1_n_7\, + Q => TimeCounter_reg(24), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[24]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[20]_i_1_n_0\, + CO(3) => \TimeCounter_reg[24]_i_1_n_0\, + CO(2) => \TimeCounter_reg[24]_i_1_n_1\, + CO(1) => \TimeCounter_reg[24]_i_1_n_2\, + CO(0) => \TimeCounter_reg[24]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[24]_i_1_n_4\, + O(2) => \TimeCounter_reg[24]_i_1_n_5\, + O(1) => \TimeCounter_reg[24]_i_1_n_6\, + O(0) => \TimeCounter_reg[24]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(27 downto 24) + ); +\TimeCounter_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[24]_i_1_n_6\, + Q => TimeCounter_reg(25), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[24]_i_1_n_5\, + Q => TimeCounter_reg(26), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[24]_i_1_n_4\, + Q => TimeCounter_reg(27), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[28]_i_1_n_7\, + Q => TimeCounter_reg(28), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[28]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[24]_i_1_n_0\, + CO(3) => \NLW_TimeCounter_reg[28]_i_1_CO_UNCONNECTED\(3), + CO(2) => \TimeCounter_reg[28]_i_1_n_1\, + CO(1) => \TimeCounter_reg[28]_i_1_n_2\, + CO(0) => \TimeCounter_reg[28]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[28]_i_1_n_4\, + O(2) => \TimeCounter_reg[28]_i_1_n_5\, + O(1) => \TimeCounter_reg[28]_i_1_n_6\, + O(0) => \TimeCounter_reg[28]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(31 downto 28) + ); +\TimeCounter_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[28]_i_1_n_6\, + Q => TimeCounter_reg(29), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[0]_i_1_n_5\, + Q => TimeCounter_reg(2), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[28]_i_1_n_5\, + Q => TimeCounter_reg(30), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[28]_i_1_n_4\, + Q => TimeCounter_reg(31), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[0]_i_1_n_4\, + Q => TimeCounter_reg(3), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[4]_i_1_n_7\, + Q => TimeCounter_reg(4), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[0]_i_1_n_0\, + CO(3) => \TimeCounter_reg[4]_i_1_n_0\, + CO(2) => \TimeCounter_reg[4]_i_1_n_1\, + CO(1) => \TimeCounter_reg[4]_i_1_n_2\, + CO(0) => \TimeCounter_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[4]_i_1_n_4\, + O(2) => \TimeCounter_reg[4]_i_1_n_5\, + O(1) => \TimeCounter_reg[4]_i_1_n_6\, + O(0) => \TimeCounter_reg[4]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(7 downto 4) + ); +\TimeCounter_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[4]_i_1_n_6\, + Q => TimeCounter_reg(5), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[4]_i_1_n_5\, + Q => TimeCounter_reg(6), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[4]_i_1_n_4\, + Q => TimeCounter_reg(7), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[8]_i_1_n_7\, + Q => TimeCounter_reg(8), + R => deadTimeCounterReset_reg_n_0 + ); +\TimeCounter_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \TimeCounter_reg[4]_i_1_n_0\, + CO(3) => \TimeCounter_reg[8]_i_1_n_0\, + CO(2) => \TimeCounter_reg[8]_i_1_n_1\, + CO(1) => \TimeCounter_reg[8]_i_1_n_2\, + CO(0) => \TimeCounter_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \TimeCounter_reg[8]_i_1_n_4\, + O(2) => \TimeCounter_reg[8]_i_1_n_5\, + O(1) => \TimeCounter_reg[8]_i_1_n_6\, + O(0) => \TimeCounter_reg[8]_i_1_n_7\, + S(3 downto 0) => TimeCounter_reg(11 downto 8) + ); +\TimeCounter_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => sel, + D => \TimeCounter_reg[8]_i_1_n_6\, + Q => TimeCounter_reg(9), + R => deadTimeCounterReset_reg_n_0 + ); +deadTimeCounterReset_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFE0000000E" + ) + port map ( + I0 => deadTimeCounterReset_i_2_n_0, + I1 => \FSM_onehot_lineconfig[6]_i_4_n_0\, + I2 => reset, + I3 => breaking_en, + I4 => deadTimeCounterReset_i_3_n_0, + I5 => deadTimeCounterReset_reg_n_0, + O => deadTimeCounterReset_i_1_n_0 + ); +deadTimeCounterReset_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + O => deadTimeCounterReset_i_2_n_0 + ); +deadTimeCounterReset_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000022220020" + ) + port map ( + I0 => deadTimeCounterReset_i_4_n_0, + I1 => deadTimeCounterReset_i_2_n_0, + I2 => deadTimeCounterReset_i_5_n_0, + I3 => deadTimeCounterReset_i_6_n_0, + I4 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I5 => deadTimeCounterReset_i_7_n_0, + O => deadTimeCounterReset_i_3_n_0 + ); +deadTimeCounterReset_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"555D555555555555" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I1 => deadTimeOK, + I2 => TKin1, + I3 => TKin1_triggered, + I4 => TKin0, + I5 => TKin0_triggered, + O => deadTimeCounterReset_i_4_n_0 + ); +deadTimeCounterReset_i_5: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => deadTimeOK, + I1 => ready, + I2 => er, + O => deadTimeCounterReset_i_5_n_0 + ); +deadTimeCounterReset_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"F777" + ) + port map ( + I0 => TKin0, + I1 => TKin1, + I2 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I3 => deadTimeCounterReset_reg_n_0, + O => deadTimeCounterReset_i_6_n_0 + ); +deadTimeCounterReset_i_7: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAA2AAAAAAAAAA" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I1 => TKin1, + I2 => TKin0, + I3 => deadTimeOK, + I4 => TKin0_triggered, + I5 => TKin1_triggered, + O => deadTimeCounterReset_i_7_n_0 + ); +deadTimeCounterReset_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => '1', + D => deadTimeCounterReset_i_1_n_0, + Q => deadTimeCounterReset_reg_n_0, + R => '0' + ); +deadTimeOK_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"0D" + ) + port map ( + I0 => sel, + I1 => deadTimeOK, + I2 => deadTimeCounterReset_reg_n_0, + O => deadTimeOK_i_1_n_0 + ); +deadTimeOK_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => deadTimeOK_i_1_n_0, + Q => deadTimeOK, + R => '0' + ); +key1_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"DDDDDDD0DDDDDDDD" + ) + port map ( + I0 => breaking_en, + I1 => TKin0, + I2 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I4 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I5 => key1_i_2_n_0, + O => key1_i_1_n_0 + ); +key1_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I3 => breaking_en, + O => key1_i_2_n_0 + ); +key1_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key1_reg_n_0, + Q => key1_prev, + R => '0' + ); +key1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key1_i_1_n_0, + Q => key1_reg_n_0, + R => '0' + ); +key2_i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => reset, + O => p_0_in + ); +key2_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAFFFFFFFC" + ) + port map ( + I0 => TKin1, + I1 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I4 => \FSM_onehot_lineconfig_reg_n_0_[1]\, + I5 => breaking_en, + O => key2_i_2_n_0 + ); +key2_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key2_reg_n_0, + Q => key2_prev, + R => '0' + ); +key2_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key2_i_2_n_0, + Q => key2_reg_n_0, + R => '0' + ); +key3_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAFFFFAAAAFCFF" + ) + port map ( + I0 => key3_reg_n_0, + I1 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I3 => \FSM_onehot_lineconfig[5]_i_2_n_0\, + I4 => reset, + I5 => breaking_en, + O => key3_i_1_n_0 + ); +key3_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key3_reg_n_0, + Q => key3_prev, + R => '0' + ); +key3_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => key3_i_1_n_0, + Q => key3_reg_n_0, + R => '0' + ); +key4_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAFFFFAAAAFFFC" + ) + port map ( + I0 => key4_reg_n_0, + I1 => key3, + I2 => \FSM_onehot_lineconfig_reg_n_0_[6]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[5]\, + I4 => reset, + I5 => breaking_en, + O => key4_i_1_n_0 + ); +key4_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \FSM_onehot_lineconfig_reg_n_0_[2]\, + I1 => \FSM_onehot_lineconfig_reg_n_0_[0]\, + I2 => \FSM_onehot_lineconfig_reg_n_0_[4]\, + I3 => \FSM_onehot_lineconfig_reg_n_0_[3]\, + O => key3 + ); +key4_prev_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => p_0_in, + D => key4_reg_n_0, + Q => key4_prev, + R => '0' + ); +key4_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => key4_i_1_n_0, + Q => key4_reg_n_0, + R => '0' + ); +\ltOp__15_carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \ltOp__15_carry_n_0\, + CO(2) => \ltOp__15_carry_n_1\, + CO(1) => \ltOp__15_carry_n_2\, + CO(0) => \ltOp__15_carry_n_3\, + CYINIT => '0', + DI(3) => \ltOp__15_carry_i_1_n_0\, + DI(2) => \ltOp__15_carry_i_2_n_0\, + DI(1) => \ltOp__15_carry_i_3_n_0\, + DI(0) => \ltOp__15_carry_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__15_carry_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__15_carry_i_5_n_0\, + S(2) => \ltOp__15_carry_i_6_n_0\, + S(1) => \ltOp__15_carry_i_7_n_0\, + S(0) => \ltOp__15_carry_i_8_n_0\ + ); +\ltOp__15_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__15_carry_n_0\, + CO(3) => \ltOp__15_carry__0_n_0\, + CO(2) => \ltOp__15_carry__0_n_1\, + CO(1) => \ltOp__15_carry__0_n_2\, + CO(0) => \ltOp__15_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp__15_carry__0_i_1_n_0\, + DI(2) => \ltOp__15_carry__0_i_2_n_0\, + DI(1) => \ltOp__15_carry__0_i_3_n_0\, + DI(0) => \ltOp__15_carry__0_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__15_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__15_carry__0_i_5_n_0\, + S(2) => \ltOp__15_carry__0_i_6_n_0\, + S(1) => \ltOp__15_carry__0_i_7_n_0\, + S(0) => \ltOp__15_carry__0_i_8_n_0\ + ); +\ltOp__15_carry__0_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(15), + I1 => minTimeCounter_low_reg(15), + I2 => minTime(14), + I3 => minTimeCounter_low_reg(14), + O => \ltOp__15_carry__0_i_1_n_0\ + ); +\ltOp__15_carry__0_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(13), + I1 => minTimeCounter_low_reg(13), + I2 => minTime(12), + I3 => minTimeCounter_low_reg(12), + O => \ltOp__15_carry__0_i_2_n_0\ + ); +\ltOp__15_carry__0_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(11), + I1 => minTimeCounter_low_reg(11), + I2 => minTime(10), + I3 => minTimeCounter_low_reg(10), + O => \ltOp__15_carry__0_i_3_n_0\ + ); +\ltOp__15_carry__0_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(9), + I1 => minTimeCounter_low_reg(9), + I2 => minTime(8), + I3 => minTimeCounter_low_reg(8), + O => \ltOp__15_carry__0_i_4_n_0\ + ); +\ltOp__15_carry__0_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(15), + I1 => minTime(15), + I2 => minTimeCounter_low_reg(14), + I3 => minTime(14), + O => \ltOp__15_carry__0_i_5_n_0\ + ); +\ltOp__15_carry__0_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(13), + I1 => minTime(13), + I2 => minTimeCounter_low_reg(12), + I3 => minTime(12), + O => \ltOp__15_carry__0_i_6_n_0\ + ); +\ltOp__15_carry__0_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(11), + I1 => minTime(11), + I2 => minTimeCounter_low_reg(10), + I3 => minTime(10), + O => \ltOp__15_carry__0_i_7_n_0\ + ); +\ltOp__15_carry__0_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(9), + I1 => minTime(9), + I2 => minTimeCounter_low_reg(8), + I3 => minTime(8), + O => \ltOp__15_carry__0_i_8_n_0\ + ); +\ltOp__15_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__15_carry__0_n_0\, + CO(3) => \ltOp__15_carry__1_n_0\, + CO(2) => \ltOp__15_carry__1_n_1\, + CO(1) => \ltOp__15_carry__1_n_2\, + CO(0) => \ltOp__15_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp__15_carry__1_i_1_n_0\, + DI(2) => \ltOp__15_carry__1_i_2_n_0\, + DI(1) => \ltOp__15_carry__1_i_3_n_0\, + DI(0) => \ltOp__15_carry__1_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__15_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__15_carry__1_i_5_n_0\, + S(2) => \ltOp__15_carry__1_i_6_n_0\, + S(1) => \ltOp__15_carry__1_i_7_n_0\, + S(0) => \ltOp__15_carry__1_i_8_n_0\ + ); +\ltOp__15_carry__1_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(23), + I1 => minTimeCounter_low_reg(23), + I2 => minTime(22), + I3 => minTimeCounter_low_reg(22), + O => \ltOp__15_carry__1_i_1_n_0\ + ); +\ltOp__15_carry__1_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(21), + I1 => minTimeCounter_low_reg(21), + I2 => minTime(20), + I3 => minTimeCounter_low_reg(20), + O => \ltOp__15_carry__1_i_2_n_0\ + ); +\ltOp__15_carry__1_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(19), + I1 => minTimeCounter_low_reg(19), + I2 => minTime(18), + I3 => minTimeCounter_low_reg(18), + O => \ltOp__15_carry__1_i_3_n_0\ + ); +\ltOp__15_carry__1_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(17), + I1 => minTimeCounter_low_reg(17), + I2 => minTime(16), + I3 => minTimeCounter_low_reg(16), + O => \ltOp__15_carry__1_i_4_n_0\ + ); +\ltOp__15_carry__1_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(23), + I1 => minTime(23), + I2 => minTimeCounter_low_reg(22), + I3 => minTime(22), + O => \ltOp__15_carry__1_i_5_n_0\ + ); +\ltOp__15_carry__1_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(21), + I1 => minTime(21), + I2 => minTimeCounter_low_reg(20), + I3 => minTime(20), + O => \ltOp__15_carry__1_i_6_n_0\ + ); +\ltOp__15_carry__1_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(19), + I1 => minTime(19), + I2 => minTimeCounter_low_reg(18), + I3 => minTime(18), + O => \ltOp__15_carry__1_i_7_n_0\ + ); +\ltOp__15_carry__1_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(17), + I1 => minTime(17), + I2 => minTimeCounter_low_reg(16), + I3 => minTime(16), + O => \ltOp__15_carry__1_i_8_n_0\ + ); +\ltOp__15_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__15_carry__1_n_0\, + CO(3) => \ltOp__15_carry__2_n_0\, + CO(2) => \ltOp__15_carry__2_n_1\, + CO(1) => \ltOp__15_carry__2_n_2\, + CO(0) => \ltOp__15_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp__15_carry__2_i_1_n_0\, + DI(2) => \ltOp__15_carry__2_i_2_n_0\, + DI(1) => \ltOp__15_carry__2_i_3_n_0\, + DI(0) => \ltOp__15_carry__2_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__15_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__15_carry__2_i_5_n_0\, + S(2) => \ltOp__15_carry__2_i_6_n_0\, + S(1) => \ltOp__15_carry__2_i_7_n_0\, + S(0) => \ltOp__15_carry__2_i_8_n_0\ + ); +\ltOp__15_carry__2_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(31), + I1 => minTimeCounter_low_reg(31), + I2 => minTime(30), + I3 => minTimeCounter_low_reg(30), + O => \ltOp__15_carry__2_i_1_n_0\ + ); +\ltOp__15_carry__2_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(29), + I1 => minTimeCounter_low_reg(29), + I2 => minTime(28), + I3 => minTimeCounter_low_reg(28), + O => \ltOp__15_carry__2_i_2_n_0\ + ); +\ltOp__15_carry__2_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(27), + I1 => minTimeCounter_low_reg(27), + I2 => minTime(26), + I3 => minTimeCounter_low_reg(26), + O => \ltOp__15_carry__2_i_3_n_0\ + ); +\ltOp__15_carry__2_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(25), + I1 => minTimeCounter_low_reg(25), + I2 => minTime(24), + I3 => minTimeCounter_low_reg(24), + O => \ltOp__15_carry__2_i_4_n_0\ + ); +\ltOp__15_carry__2_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(31), + I1 => minTime(31), + I2 => minTimeCounter_low_reg(30), + I3 => minTime(30), + O => \ltOp__15_carry__2_i_5_n_0\ + ); +\ltOp__15_carry__2_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(29), + I1 => minTime(29), + I2 => minTimeCounter_low_reg(28), + I3 => minTime(28), + O => \ltOp__15_carry__2_i_6_n_0\ + ); +\ltOp__15_carry__2_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(27), + I1 => minTime(27), + I2 => minTimeCounter_low_reg(26), + I3 => minTime(26), + O => \ltOp__15_carry__2_i_7_n_0\ + ); +\ltOp__15_carry__2_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(25), + I1 => minTime(25), + I2 => minTimeCounter_low_reg(24), + I3 => minTime(24), + O => \ltOp__15_carry__2_i_8_n_0\ + ); +\ltOp__15_carry_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(7), + I1 => minTimeCounter_low_reg(7), + I2 => minTime(6), + I3 => minTimeCounter_low_reg(6), + O => \ltOp__15_carry_i_1_n_0\ + ); +\ltOp__15_carry_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(5), + I1 => minTimeCounter_low_reg(5), + I2 => minTime(4), + I3 => minTimeCounter_low_reg(4), + O => \ltOp__15_carry_i_2_n_0\ + ); +\ltOp__15_carry_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(3), + I1 => minTimeCounter_low_reg(3), + I2 => minTime(2), + I3 => minTimeCounter_low_reg(2), + O => \ltOp__15_carry_i_3_n_0\ + ); +\ltOp__15_carry_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(1), + I1 => minTimeCounter_low_reg(1), + I2 => minTime(0), + I3 => minTimeCounter_low_reg(0), + O => \ltOp__15_carry_i_4_n_0\ + ); +\ltOp__15_carry_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(7), + I1 => minTime(7), + I2 => minTimeCounter_low_reg(6), + I3 => minTime(6), + O => \ltOp__15_carry_i_5_n_0\ + ); +\ltOp__15_carry_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(5), + I1 => minTime(5), + I2 => minTimeCounter_low_reg(4), + I3 => minTime(4), + O => \ltOp__15_carry_i_6_n_0\ + ); +\ltOp__15_carry_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(3), + I1 => minTime(3), + I2 => minTimeCounter_low_reg(2), + I3 => minTime(2), + O => \ltOp__15_carry_i_7_n_0\ + ); +\ltOp__15_carry_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_low_reg(1), + I1 => minTime(1), + I2 => minTimeCounter_low_reg(0), + I3 => minTime(0), + O => \ltOp__15_carry_i_8_n_0\ + ); +\ltOp__31_carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \ltOp__31_carry_n_0\, + CO(2) => \ltOp__31_carry_n_1\, + CO(1) => \ltOp__31_carry_n_2\, + CO(0) => \ltOp__31_carry_n_3\, + CYINIT => '0', + DI(3) => \ltOp__31_carry_i_1_n_0\, + DI(2) => \ltOp__31_carry_i_2_n_0\, + DI(1) => \ltOp__31_carry_i_3_n_0\, + DI(0) => \ltOp__31_carry_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp__31_carry_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__31_carry_i_5_n_0\, + S(2) => \ltOp__31_carry_i_6_n_0\, + S(1) => \ltOp__31_carry_i_7_n_0\, + S(0) => \ltOp__31_carry_i_8_n_0\ + ); +\ltOp__31_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__31_carry_n_0\, + CO(3) => \ltOp__31_carry__0_n_0\, + CO(2) => \ltOp__31_carry__0_n_1\, + CO(1) => \ltOp__31_carry__0_n_2\, + CO(0) => \ltOp__31_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp__31_carry_i_1__0_n_0\, + DI(2) => \ltOp__31_carry_i_2__0_n_0\, + DI(1) => \ltOp__31_carry_i_3__0_n_0\, + DI(0) => \ltOp__31_carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_ltOp__31_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__31_carry_i_5__0_n_0\, + S(2) => \ltOp__31_carry_i_6__0_n_0\, + S(1) => \ltOp__31_carry_i_7__0_n_0\, + S(0) => \ltOp__31_carry_i_8__0_n_0\ + ); +\ltOp__31_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__31_carry__0_n_0\, + CO(3) => \ltOp__31_carry__1_n_0\, + CO(2) => \ltOp__31_carry__1_n_1\, + CO(1) => \ltOp__31_carry__1_n_2\, + CO(0) => \ltOp__31_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp__31_carry_i_1__1_n_0\, + DI(2) => \ltOp__31_carry_i_2__1_n_0\, + DI(1) => \ltOp__31_carry_i_3__1_n_0\, + DI(0) => \ltOp__31_carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_ltOp__31_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__31_carry_i_5__1_n_0\, + S(2) => \ltOp__31_carry_i_6__1_n_0\, + S(1) => \ltOp__31_carry_i_7__1_n_0\, + S(0) => \ltOp__31_carry_i_8__1_n_0\ + ); +\ltOp__31_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp__31_carry__1_n_0\, + CO(3) => \ltOp__31_carry__2_n_0\, + CO(2) => \ltOp__31_carry__2_n_1\, + CO(1) => \ltOp__31_carry__2_n_2\, + CO(0) => \ltOp__31_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp__31_carry_i_1__2_n_0\, + DI(2) => \ltOp__31_carry_i_2__2_n_0\, + DI(1) => \ltOp__31_carry_i_3__2_n_0\, + DI(0) => \ltOp__31_carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp__31_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp__31_carry_i_5__2_n_0\, + S(2) => \ltOp__31_carry_i_6__2_n_0\, + S(1) => \ltOp__31_carry_i_7__2_n_0\, + S(0) => \ltOp__31_carry_i_8__2_n_0\ + ); +\ltOp__31_carry_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(7), + I1 => minTimeCounter_high_reg(7), + I2 => minTime(6), + I3 => minTimeCounter_high_reg(6), + O => \ltOp__31_carry_i_1_n_0\ + ); +\ltOp__31_carry_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(15), + I1 => minTimeCounter_high_reg(15), + I2 => minTime(14), + I3 => minTimeCounter_high_reg(14), + O => \ltOp__31_carry_i_1__0_n_0\ + ); +\ltOp__31_carry_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(23), + I1 => minTimeCounter_high_reg(23), + I2 => minTime(22), + I3 => minTimeCounter_high_reg(22), + O => \ltOp__31_carry_i_1__1_n_0\ + ); +\ltOp__31_carry_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(31), + I1 => minTimeCounter_high_reg(31), + I2 => minTime(30), + I3 => minTimeCounter_high_reg(30), + O => \ltOp__31_carry_i_1__2_n_0\ + ); +\ltOp__31_carry_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(5), + I1 => minTimeCounter_high_reg(5), + I2 => minTime(4), + I3 => minTimeCounter_high_reg(4), + O => \ltOp__31_carry_i_2_n_0\ + ); +\ltOp__31_carry_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(13), + I1 => minTimeCounter_high_reg(13), + I2 => minTime(12), + I3 => minTimeCounter_high_reg(12), + O => \ltOp__31_carry_i_2__0_n_0\ + ); +\ltOp__31_carry_i_2__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(21), + I1 => minTimeCounter_high_reg(21), + I2 => minTime(20), + I3 => minTimeCounter_high_reg(20), + O => \ltOp__31_carry_i_2__1_n_0\ + ); +\ltOp__31_carry_i_2__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(29), + I1 => minTimeCounter_high_reg(29), + I2 => minTime(28), + I3 => minTimeCounter_high_reg(28), + O => \ltOp__31_carry_i_2__2_n_0\ + ); +\ltOp__31_carry_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(3), + I1 => minTimeCounter_high_reg(3), + I2 => minTime(2), + I3 => minTimeCounter_high_reg(2), + O => \ltOp__31_carry_i_3_n_0\ + ); +\ltOp__31_carry_i_3__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(11), + I1 => minTimeCounter_high_reg(11), + I2 => minTime(10), + I3 => minTimeCounter_high_reg(10), + O => \ltOp__31_carry_i_3__0_n_0\ + ); +\ltOp__31_carry_i_3__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(19), + I1 => minTimeCounter_high_reg(19), + I2 => minTime(18), + I3 => minTimeCounter_high_reg(18), + O => \ltOp__31_carry_i_3__1_n_0\ + ); +\ltOp__31_carry_i_3__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(27), + I1 => minTimeCounter_high_reg(27), + I2 => minTime(26), + I3 => minTimeCounter_high_reg(26), + O => \ltOp__31_carry_i_3__2_n_0\ + ); +\ltOp__31_carry_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(1), + I1 => minTimeCounter_high_reg(1), + I2 => minTime(0), + I3 => minTimeCounter_high_reg(0), + O => \ltOp__31_carry_i_4_n_0\ + ); +\ltOp__31_carry_i_4__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(9), + I1 => minTimeCounter_high_reg(9), + I2 => minTime(8), + I3 => minTimeCounter_high_reg(8), + O => \ltOp__31_carry_i_4__0_n_0\ + ); +\ltOp__31_carry_i_4__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(17), + I1 => minTimeCounter_high_reg(17), + I2 => minTime(16), + I3 => minTimeCounter_high_reg(16), + O => \ltOp__31_carry_i_4__1_n_0\ + ); +\ltOp__31_carry_i_4__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => minTime(25), + I1 => minTimeCounter_high_reg(25), + I2 => minTime(24), + I3 => minTimeCounter_high_reg(24), + O => \ltOp__31_carry_i_4__2_n_0\ + ); +\ltOp__31_carry_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(7), + I1 => minTime(7), + I2 => minTimeCounter_high_reg(6), + I3 => minTime(6), + O => \ltOp__31_carry_i_5_n_0\ + ); +\ltOp__31_carry_i_5__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(15), + I1 => minTime(15), + I2 => minTimeCounter_high_reg(14), + I3 => minTime(14), + O => \ltOp__31_carry_i_5__0_n_0\ + ); +\ltOp__31_carry_i_5__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(23), + I1 => minTime(23), + I2 => minTimeCounter_high_reg(22), + I3 => minTime(22), + O => \ltOp__31_carry_i_5__1_n_0\ + ); +\ltOp__31_carry_i_5__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(31), + I1 => minTime(31), + I2 => minTimeCounter_high_reg(30), + I3 => minTime(30), + O => \ltOp__31_carry_i_5__2_n_0\ + ); +\ltOp__31_carry_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(5), + I1 => minTime(5), + I2 => minTimeCounter_high_reg(4), + I3 => minTime(4), + O => \ltOp__31_carry_i_6_n_0\ + ); +\ltOp__31_carry_i_6__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(13), + I1 => minTime(13), + I2 => minTimeCounter_high_reg(12), + I3 => minTime(12), + O => \ltOp__31_carry_i_6__0_n_0\ + ); +\ltOp__31_carry_i_6__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(21), + I1 => minTime(21), + I2 => minTimeCounter_high_reg(20), + I3 => minTime(20), + O => \ltOp__31_carry_i_6__1_n_0\ + ); +\ltOp__31_carry_i_6__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(29), + I1 => minTime(29), + I2 => minTimeCounter_high_reg(28), + I3 => minTime(28), + O => \ltOp__31_carry_i_6__2_n_0\ + ); +\ltOp__31_carry_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(3), + I1 => minTime(3), + I2 => minTimeCounter_high_reg(2), + I3 => minTime(2), + O => \ltOp__31_carry_i_7_n_0\ + ); +\ltOp__31_carry_i_7__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(11), + I1 => minTime(11), + I2 => minTimeCounter_high_reg(10), + I3 => minTime(10), + O => \ltOp__31_carry_i_7__0_n_0\ + ); +\ltOp__31_carry_i_7__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(19), + I1 => minTime(19), + I2 => minTimeCounter_high_reg(18), + I3 => minTime(18), + O => \ltOp__31_carry_i_7__1_n_0\ + ); +\ltOp__31_carry_i_7__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(27), + I1 => minTime(27), + I2 => minTimeCounter_high_reg(26), + I3 => minTime(26), + O => \ltOp__31_carry_i_7__2_n_0\ + ); +\ltOp__31_carry_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(1), + I1 => minTime(1), + I2 => minTimeCounter_high_reg(0), + I3 => minTime(0), + O => \ltOp__31_carry_i_8_n_0\ + ); +\ltOp__31_carry_i_8__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(9), + I1 => minTime(9), + I2 => minTimeCounter_high_reg(8), + I3 => minTime(8), + O => \ltOp__31_carry_i_8__0_n_0\ + ); +\ltOp__31_carry_i_8__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(17), + I1 => minTime(17), + I2 => minTimeCounter_high_reg(16), + I3 => minTime(16), + O => \ltOp__31_carry_i_8__1_n_0\ + ); +\ltOp__31_carry_i_8__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => minTimeCounter_high_reg(25), + I1 => minTime(25), + I2 => minTimeCounter_high_reg(24), + I3 => minTime(24), + O => \ltOp__31_carry_i_8__2_n_0\ + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \ltOp_carry__0_n_0\, + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry__0_i_1_n_0\, + DI(2) => \ltOp_carry__0_i_2_n_0\, + DI(1) => \ltOp_carry__0_i_3_n_0\, + DI(0) => \ltOp_carry__0_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry__0_i_5_n_0\, + S(2) => \ltOp_carry__0_i_6_n_0\, + S(1) => \ltOp_carry__0_i_7_n_0\, + S(0) => \ltOp_carry__0_i_8_n_0\ + ); +\ltOp_carry__0_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(15), + I1 => TimeCounter_reg(15), + I2 => deadTime(14), + I3 => TimeCounter_reg(14), + O => \ltOp_carry__0_i_1_n_0\ + ); +\ltOp_carry__0_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(13), + I1 => TimeCounter_reg(13), + I2 => deadTime(12), + I3 => TimeCounter_reg(12), + O => \ltOp_carry__0_i_2_n_0\ + ); +\ltOp_carry__0_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(11), + I1 => TimeCounter_reg(11), + I2 => deadTime(10), + I3 => TimeCounter_reg(10), + O => \ltOp_carry__0_i_3_n_0\ + ); +\ltOp_carry__0_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(9), + I1 => TimeCounter_reg(9), + I2 => deadTime(8), + I3 => TimeCounter_reg(8), + O => \ltOp_carry__0_i_4_n_0\ + ); +\ltOp_carry__0_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(15), + I1 => deadTime(15), + I2 => TimeCounter_reg(14), + I3 => deadTime(14), + O => \ltOp_carry__0_i_5_n_0\ + ); +\ltOp_carry__0_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(13), + I1 => deadTime(13), + I2 => TimeCounter_reg(12), + I3 => deadTime(12), + O => \ltOp_carry__0_i_6_n_0\ + ); +\ltOp_carry__0_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(11), + I1 => deadTime(11), + I2 => TimeCounter_reg(10), + I3 => deadTime(10), + O => \ltOp_carry__0_i_7_n_0\ + ); +\ltOp_carry__0_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(9), + I1 => deadTime(9), + I2 => TimeCounter_reg(8), + I3 => deadTime(8), + O => \ltOp_carry__0_i_8_n_0\ + ); +\ltOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__0_n_0\, + CO(3) => \ltOp_carry__1_n_0\, + CO(2) => \ltOp_carry__1_n_1\, + CO(1) => \ltOp_carry__1_n_2\, + CO(0) => \ltOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry__1_i_1_n_0\, + DI(2) => \ltOp_carry__1_i_2_n_0\, + DI(1) => \ltOp_carry__1_i_3_n_0\, + DI(0) => \ltOp_carry__1_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__1_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry__1_i_5_n_0\, + S(2) => \ltOp_carry__1_i_6_n_0\, + S(1) => \ltOp_carry__1_i_7_n_0\, + S(0) => \ltOp_carry__1_i_8_n_0\ + ); +\ltOp_carry__1_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(23), + I1 => TimeCounter_reg(23), + I2 => deadTime(22), + I3 => TimeCounter_reg(22), + O => \ltOp_carry__1_i_1_n_0\ + ); +\ltOp_carry__1_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(21), + I1 => TimeCounter_reg(21), + I2 => deadTime(20), + I3 => TimeCounter_reg(20), + O => \ltOp_carry__1_i_2_n_0\ + ); +\ltOp_carry__1_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(19), + I1 => TimeCounter_reg(19), + I2 => deadTime(18), + I3 => TimeCounter_reg(18), + O => \ltOp_carry__1_i_3_n_0\ + ); +\ltOp_carry__1_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(17), + I1 => TimeCounter_reg(17), + I2 => deadTime(16), + I3 => TimeCounter_reg(16), + O => \ltOp_carry__1_i_4_n_0\ + ); +\ltOp_carry__1_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(23), + I1 => deadTime(23), + I2 => TimeCounter_reg(22), + I3 => deadTime(22), + O => \ltOp_carry__1_i_5_n_0\ + ); +\ltOp_carry__1_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(21), + I1 => deadTime(21), + I2 => TimeCounter_reg(20), + I3 => deadTime(20), + O => \ltOp_carry__1_i_6_n_0\ + ); +\ltOp_carry__1_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(19), + I1 => deadTime(19), + I2 => TimeCounter_reg(18), + I3 => deadTime(18), + O => \ltOp_carry__1_i_7_n_0\ + ); +\ltOp_carry__1_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(17), + I1 => deadTime(17), + I2 => TimeCounter_reg(16), + I3 => deadTime(16), + O => \ltOp_carry__1_i_8_n_0\ + ); +\ltOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_carry__1_n_0\, + CO(3) => sel, + CO(2) => \ltOp_carry__2_n_1\, + CO(1) => \ltOp_carry__2_n_2\, + CO(0) => \ltOp_carry__2_n_3\, + CYINIT => '0', + DI(3) => \ltOp_carry__2_i_1_n_0\, + DI(2) => \ltOp_carry__2_i_2_n_0\, + DI(1) => \ltOp_carry__2_i_3_n_0\, + DI(0) => \ltOp_carry__2_i_4_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__2_O_UNCONNECTED\(3 downto 0), + S(3) => \ltOp_carry__2_i_5_n_0\, + S(2) => \ltOp_carry__2_i_6_n_0\, + S(1) => \ltOp_carry__2_i_7_n_0\, + S(0) => \ltOp_carry__2_i_8_n_0\ + ); +\ltOp_carry__2_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(31), + I1 => TimeCounter_reg(31), + I2 => deadTime(30), + I3 => TimeCounter_reg(30), + O => \ltOp_carry__2_i_1_n_0\ + ); +\ltOp_carry__2_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(29), + I1 => TimeCounter_reg(29), + I2 => deadTime(28), + I3 => TimeCounter_reg(28), + O => \ltOp_carry__2_i_2_n_0\ + ); +\ltOp_carry__2_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(27), + I1 => TimeCounter_reg(27), + I2 => deadTime(26), + I3 => TimeCounter_reg(26), + O => \ltOp_carry__2_i_3_n_0\ + ); +\ltOp_carry__2_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(25), + I1 => TimeCounter_reg(25), + I2 => deadTime(24), + I3 => TimeCounter_reg(24), + O => \ltOp_carry__2_i_4_n_0\ + ); +\ltOp_carry__2_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(31), + I1 => deadTime(31), + I2 => TimeCounter_reg(30), + I3 => deadTime(30), + O => \ltOp_carry__2_i_5_n_0\ + ); +\ltOp_carry__2_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(29), + I1 => deadTime(29), + I2 => TimeCounter_reg(28), + I3 => deadTime(28), + O => \ltOp_carry__2_i_6_n_0\ + ); +\ltOp_carry__2_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(27), + I1 => deadTime(27), + I2 => TimeCounter_reg(26), + I3 => deadTime(26), + O => \ltOp_carry__2_i_7_n_0\ + ); +\ltOp_carry__2_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(25), + I1 => deadTime(25), + I2 => TimeCounter_reg(24), + I3 => deadTime(24), + O => \ltOp_carry__2_i_8_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(7), + I1 => TimeCounter_reg(7), + I2 => deadTime(6), + I3 => TimeCounter_reg(6), + O => ltOp_carry_i_1_n_0 + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(5), + I1 => TimeCounter_reg(5), + I2 => deadTime(4), + I3 => TimeCounter_reg(4), + O => ltOp_carry_i_2_n_0 + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(3), + I1 => TimeCounter_reg(3), + I2 => deadTime(2), + I3 => TimeCounter_reg(2), + O => ltOp_carry_i_3_n_0 + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => deadTime(1), + I1 => TimeCounter_reg(1), + I2 => deadTime(0), + I3 => TimeCounter_reg(0), + O => ltOp_carry_i_4_n_0 + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(7), + I1 => deadTime(7), + I2 => TimeCounter_reg(6), + I3 => deadTime(6), + O => ltOp_carry_i_5_n_0 + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(5), + I1 => deadTime(5), + I2 => TimeCounter_reg(4), + I3 => deadTime(4), + O => ltOp_carry_i_6_n_0 + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(3), + I1 => deadTime(3), + I2 => TimeCounter_reg(2), + I3 => deadTime(2), + O => ltOp_carry_i_7_n_0 + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => TimeCounter_reg(1), + I1 => deadTime(1), + I2 => TimeCounter_reg(0), + I3 => deadTime(0), + O => ltOp_carry_i_8_n_0 + ); +\minTimeCounter_high[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000022222F22" + ) + port map ( + I0 => key1_prev, + I1 => key1_reg_n_0, + I2 => key2_reg_n_0, + I3 => key2_prev, + I4 => breaking_en, + I5 => reset, + O => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high[0]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \ltOp__31_carry__2_n_0\, + I1 => reset, + O => minTimeCounter_high + ); +\minTimeCounter_high[0]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => minTimeCounter_high_reg(0), + O => \minTimeCounter_high[0]_i_4_n_0\ + ); +\minTimeCounter_high_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[0]_i_3_n_7\, + Q => minTimeCounter_high_reg(0), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[0]_i_3\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \minTimeCounter_high_reg[0]_i_3_n_0\, + CO(2) => \minTimeCounter_high_reg[0]_i_3_n_1\, + CO(1) => \minTimeCounter_high_reg[0]_i_3_n_2\, + CO(0) => \minTimeCounter_high_reg[0]_i_3_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \minTimeCounter_high_reg[0]_i_3_n_4\, + O(2) => \minTimeCounter_high_reg[0]_i_3_n_5\, + O(1) => \minTimeCounter_high_reg[0]_i_3_n_6\, + O(0) => \minTimeCounter_high_reg[0]_i_3_n_7\, + S(3 downto 1) => minTimeCounter_high_reg(3 downto 1), + S(0) => \minTimeCounter_high[0]_i_4_n_0\ + ); +\minTimeCounter_high_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[8]_i_1_n_5\, + Q => minTimeCounter_high_reg(10), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[8]_i_1_n_4\, + Q => minTimeCounter_high_reg(11), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[12]_i_1_n_7\, + Q => minTimeCounter_high_reg(12), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[8]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[12]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[12]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[12]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[12]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[12]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[12]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[12]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[12]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(15 downto 12) + ); +\minTimeCounter_high_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[12]_i_1_n_6\, + Q => minTimeCounter_high_reg(13), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[12]_i_1_n_5\, + Q => minTimeCounter_high_reg(14), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[12]_i_1_n_4\, + Q => minTimeCounter_high_reg(15), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[16]_i_1_n_7\, + Q => minTimeCounter_high_reg(16), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[16]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[12]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[16]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[16]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[16]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[16]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[16]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[16]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[16]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[16]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(19 downto 16) + ); +\minTimeCounter_high_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[16]_i_1_n_6\, + Q => minTimeCounter_high_reg(17), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[16]_i_1_n_5\, + Q => minTimeCounter_high_reg(18), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[16]_i_1_n_4\, + Q => minTimeCounter_high_reg(19), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[0]_i_3_n_6\, + Q => minTimeCounter_high_reg(1), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[20]_i_1_n_7\, + Q => minTimeCounter_high_reg(20), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[20]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[16]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[20]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[20]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[20]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[20]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[20]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[20]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[20]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[20]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(23 downto 20) + ); +\minTimeCounter_high_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[20]_i_1_n_6\, + Q => minTimeCounter_high_reg(21), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[20]_i_1_n_5\, + Q => minTimeCounter_high_reg(22), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[20]_i_1_n_4\, + Q => minTimeCounter_high_reg(23), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[24]_i_1_n_7\, + Q => minTimeCounter_high_reg(24), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[24]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[20]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[24]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[24]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[24]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[24]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[24]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[24]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[24]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[24]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(27 downto 24) + ); +\minTimeCounter_high_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[24]_i_1_n_6\, + Q => minTimeCounter_high_reg(25), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[24]_i_1_n_5\, + Q => minTimeCounter_high_reg(26), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[24]_i_1_n_4\, + Q => minTimeCounter_high_reg(27), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[28]_i_1_n_7\, + Q => minTimeCounter_high_reg(28), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[28]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[24]_i_1_n_0\, + CO(3) => \NLW_minTimeCounter_high_reg[28]_i_1_CO_UNCONNECTED\(3), + CO(2) => \minTimeCounter_high_reg[28]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[28]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[28]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[28]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[28]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[28]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[28]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(31 downto 28) + ); +\minTimeCounter_high_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[28]_i_1_n_6\, + Q => minTimeCounter_high_reg(29), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[0]_i_3_n_5\, + Q => minTimeCounter_high_reg(2), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[28]_i_1_n_5\, + Q => minTimeCounter_high_reg(30), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[28]_i_1_n_4\, + Q => minTimeCounter_high_reg(31), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[0]_i_3_n_4\, + Q => minTimeCounter_high_reg(3), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[4]_i_1_n_7\, + Q => minTimeCounter_high_reg(4), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[0]_i_3_n_0\, + CO(3) => \minTimeCounter_high_reg[4]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[4]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[4]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[4]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[4]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[4]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[4]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(7 downto 4) + ); +\minTimeCounter_high_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[4]_i_1_n_6\, + Q => minTimeCounter_high_reg(5), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[4]_i_1_n_5\, + Q => minTimeCounter_high_reg(6), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[4]_i_1_n_4\, + Q => minTimeCounter_high_reg(7), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[8]_i_1_n_7\, + Q => minTimeCounter_high_reg(8), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_high_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_high_reg[4]_i_1_n_0\, + CO(3) => \minTimeCounter_high_reg[8]_i_1_n_0\, + CO(2) => \minTimeCounter_high_reg[8]_i_1_n_1\, + CO(1) => \minTimeCounter_high_reg[8]_i_1_n_2\, + CO(0) => \minTimeCounter_high_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_high_reg[8]_i_1_n_4\, + O(2) => \minTimeCounter_high_reg[8]_i_1_n_5\, + O(1) => \minTimeCounter_high_reg[8]_i_1_n_6\, + O(0) => \minTimeCounter_high_reg[8]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_high_reg(11 downto 8) + ); +\minTimeCounter_high_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_high, + D => \minTimeCounter_high_reg[8]_i_1_n_6\, + Q => minTimeCounter_high_reg(9), + R => \minTimeCounter_high[0]_i_1_n_0\ + ); +\minTimeCounter_low[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000440F" + ) + port map ( + I0 => key2_reg_n_0, + I1 => key2_prev, + I2 => \minTimeCounter_low[0]_i_4_n_0\, + I3 => breaking_en, + I4 => reset, + O => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low[0]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \ltOp__15_carry__2_n_0\, + I1 => reset, + O => minTimeCounter_low + ); +\minTimeCounter_low[0]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"D0DD" + ) + port map ( + I0 => key4_prev, + I1 => key4_reg_n_0, + I2 => key3_reg_n_0, + I3 => key3_prev, + O => \minTimeCounter_low[0]_i_4_n_0\ + ); +\minTimeCounter_low[0]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => minTimeCounter_low_reg(0), + O => \minTimeCounter_low[0]_i_5_n_0\ + ); +\minTimeCounter_low_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[0]_i_3_n_7\, + Q => minTimeCounter_low_reg(0), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[0]_i_3\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \minTimeCounter_low_reg[0]_i_3_n_0\, + CO(2) => \minTimeCounter_low_reg[0]_i_3_n_1\, + CO(1) => \minTimeCounter_low_reg[0]_i_3_n_2\, + CO(0) => \minTimeCounter_low_reg[0]_i_3_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \minTimeCounter_low_reg[0]_i_3_n_4\, + O(2) => \minTimeCounter_low_reg[0]_i_3_n_5\, + O(1) => \minTimeCounter_low_reg[0]_i_3_n_6\, + O(0) => \minTimeCounter_low_reg[0]_i_3_n_7\, + S(3 downto 1) => minTimeCounter_low_reg(3 downto 1), + S(0) => \minTimeCounter_low[0]_i_5_n_0\ + ); +\minTimeCounter_low_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[8]_i_1_n_5\, + Q => minTimeCounter_low_reg(10), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[8]_i_1_n_4\, + Q => minTimeCounter_low_reg(11), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[12]_i_1_n_7\, + Q => minTimeCounter_low_reg(12), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[8]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[12]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[12]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[12]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[12]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[12]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[12]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[12]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[12]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(15 downto 12) + ); +\minTimeCounter_low_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[12]_i_1_n_6\, + Q => minTimeCounter_low_reg(13), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[12]_i_1_n_5\, + Q => minTimeCounter_low_reg(14), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[12]_i_1_n_4\, + Q => minTimeCounter_low_reg(15), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[16]_i_1_n_7\, + Q => minTimeCounter_low_reg(16), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[16]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[12]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[16]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[16]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[16]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[16]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[16]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[16]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[16]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[16]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(19 downto 16) + ); +\minTimeCounter_low_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[16]_i_1_n_6\, + Q => minTimeCounter_low_reg(17), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[16]_i_1_n_5\, + Q => minTimeCounter_low_reg(18), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[16]_i_1_n_4\, + Q => minTimeCounter_low_reg(19), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[0]_i_3_n_6\, + Q => minTimeCounter_low_reg(1), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[20]_i_1_n_7\, + Q => minTimeCounter_low_reg(20), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[20]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[16]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[20]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[20]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[20]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[20]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[20]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[20]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[20]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[20]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(23 downto 20) + ); +\minTimeCounter_low_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[20]_i_1_n_6\, + Q => minTimeCounter_low_reg(21), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[20]_i_1_n_5\, + Q => minTimeCounter_low_reg(22), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[20]_i_1_n_4\, + Q => minTimeCounter_low_reg(23), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[24]_i_1_n_7\, + Q => minTimeCounter_low_reg(24), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[24]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[20]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[24]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[24]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[24]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[24]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[24]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[24]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[24]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[24]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(27 downto 24) + ); +\minTimeCounter_low_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[24]_i_1_n_6\, + Q => minTimeCounter_low_reg(25), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[24]_i_1_n_5\, + Q => minTimeCounter_low_reg(26), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[24]_i_1_n_4\, + Q => minTimeCounter_low_reg(27), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[28]_i_1_n_7\, + Q => minTimeCounter_low_reg(28), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[28]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[24]_i_1_n_0\, + CO(3) => \NLW_minTimeCounter_low_reg[28]_i_1_CO_UNCONNECTED\(3), + CO(2) => \minTimeCounter_low_reg[28]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[28]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[28]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[28]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[28]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[28]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[28]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(31 downto 28) + ); +\minTimeCounter_low_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[28]_i_1_n_6\, + Q => minTimeCounter_low_reg(29), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[0]_i_3_n_5\, + Q => minTimeCounter_low_reg(2), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[28]_i_1_n_5\, + Q => minTimeCounter_low_reg(30), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[28]_i_1_n_4\, + Q => minTimeCounter_low_reg(31), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[0]_i_3_n_4\, + Q => minTimeCounter_low_reg(3), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[4]_i_1_n_7\, + Q => minTimeCounter_low_reg(4), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[0]_i_3_n_0\, + CO(3) => \minTimeCounter_low_reg[4]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[4]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[4]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[4]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[4]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[4]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[4]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(7 downto 4) + ); +\minTimeCounter_low_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[4]_i_1_n_6\, + Q => minTimeCounter_low_reg(5), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[4]_i_1_n_5\, + Q => minTimeCounter_low_reg(6), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[4]_i_1_n_4\, + Q => minTimeCounter_low_reg(7), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[8]_i_1_n_7\, + Q => minTimeCounter_low_reg(8), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +\minTimeCounter_low_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minTimeCounter_low_reg[4]_i_1_n_0\, + CO(3) => \minTimeCounter_low_reg[8]_i_1_n_0\, + CO(2) => \minTimeCounter_low_reg[8]_i_1_n_1\, + CO(1) => \minTimeCounter_low_reg[8]_i_1_n_2\, + CO(0) => \minTimeCounter_low_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \minTimeCounter_low_reg[8]_i_1_n_4\, + O(2) => \minTimeCounter_low_reg[8]_i_1_n_5\, + O(1) => \minTimeCounter_low_reg[8]_i_1_n_6\, + O(0) => \minTimeCounter_low_reg[8]_i_1_n_7\, + S(3 downto 0) => minTimeCounter_low_reg(11 downto 8) + ); +\minTimeCounter_low_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => minTimeCounter_low, + D => \minTimeCounter_low_reg[8]_i_1_n_6\, + Q => minTimeCounter_low_reg(9), + R => \minTimeCounter_low[0]_i_1_n_0\ + ); +minTimeEr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"EEFFEEEEE200E2E2" + ) + port map ( + I0 => minTimeEr_i_2_n_0, + I1 => minTimeEr_i_3_n_0, + I2 => minTimeEr_i_4_n_0, + I3 => minTimeEr_i_5_n_0, + I4 => minTimeEr_i_6_n_0, + I5 => \^mintimeer_reg_0\, + O => minTimeEr_i_1_n_0 + ); +minTimeEr_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"0111" + ) + port map ( + I0 => reset, + I1 => breaking_en, + I2 => minTimeEr_i_6_n_0, + I3 => minTimeEr_i_7_n_0, + O => minTimeEr_i_2_n_0 + ); +minTimeEr_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => breaking_en, + I1 => reset, + O => minTimeEr_i_3_n_0 + ); +minTimeEr_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"040404FF00000000" + ) + port map ( + I0 => minTimeOK_low, + I1 => key2_reg_n_0, + I2 => key2_prev, + I3 => minTimeEr_i_8_n_0, + I4 => minTimeOK_high, + I5 => minTime_En, + O => minTimeEr_i_4_n_0 + ); +minTimeEr_i_5: unisim.vcomponents.LUT6 + generic map( + INIT => X"55555555F755F7F7" + ) + port map ( + I0 => minTimeEr_i_9_n_0, + I1 => key2_prev, + I2 => key2_reg_n_0, + I3 => key1_reg_n_0, + I4 => key1_prev, + I5 => minTimeEr_i_7_n_0, + O => minTimeEr_i_5_n_0 + ); +minTimeEr_i_6: unisim.vcomponents.LUT6 + generic map( + INIT => X"FBFFFFFFBBFBFBFF" + ) + port map ( + I0 => minTimeOK_low, + I1 => minTime_En, + I2 => key3_prev, + I3 => key3_reg_n_0, + I4 => key4_reg_n_0, + I5 => key4_prev, + O => minTimeEr_i_6_n_0 + ); +minTimeEr_i_7: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFDFDDDDFFDFFFDF" + ) + port map ( + I0 => minTime_En, + I1 => minTimeOK_high, + I2 => key2_reg_n_0, + I3 => key2_prev, + I4 => key1_prev, + I5 => key1_reg_n_0, + O => minTimeEr_i_7_n_0 + ); +minTimeEr_i_8: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => key1_prev, + I1 => key1_reg_n_0, + O => minTimeEr_i_8_n_0 + ); +minTimeEr_i_9: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => breaking_en, + I1 => reset, + O => minTimeEr_i_9_n_0 + ); +minTimeEr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => externalCLK, + CE => '1', + D => minTimeEr_i_1_n_0, + Q => \^mintimeer_reg_0\, + R => '0' + ); +minTimeOK_high_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"00AB" + ) + port map ( + I0 => minTimeOK_high, + I1 => \ltOp__31_carry__2_n_0\, + I2 => reset, + I3 => \minTimeCounter_high[0]_i_1_n_0\, + O => minTimeOK_high_i_1_n_0 + ); +minTimeOK_high_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => minTimeOK_high_i_1_n_0, + Q => minTimeOK_high, + R => '0' + ); +minTimeOK_low_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"00AB" + ) + port map ( + I0 => minTimeOK_low, + I1 => \ltOp__15_carry__2_n_0\, + I2 => reset, + I3 => \minTimeCounter_low[0]_i_1_n_0\, + O => minTimeOK_low_i_1_n_0 + ); +minTimeOK_low_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => externalCLK, + CE => '1', + D => minTimeOK_low_i_1_n_0, + Q => minTimeOK_low, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Inverter_3lvl_P0N_3lvl_1_1 is + port ( + externalCLK : in STD_LOGIC; + ready : in STD_LOGIC; + reset : in STD_LOGIC; + deadTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + minTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + er : in STD_LOGIC; + minTime_En : in STD_LOGIC; + minTimeEr : out STD_LOGIC; + TKin0 : in STD_LOGIC; + TKin1 : in STD_LOGIC; + breaking_en : in STD_LOGIC; + PWM_out_0 : out STD_LOGIC; + PWM_out_1 : out STD_LOGIC; + PWM_out_2 : out STD_LOGIC; + PWM_out_3 : out STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of Inverter_3lvl_P0N_3lvl_1_1 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of Inverter_3lvl_P0N_3lvl_1_1 : entity is "Inverter_3lvl_P0N_3lvl_0_4,P0N_3lvl,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of Inverter_3lvl_P0N_3lvl_1_1 : entity is "yes"; + attribute ip_definition_source : string; + attribute ip_definition_source of Inverter_3lvl_P0N_3lvl_1_1 : entity is "package_project"; + attribute x_core_info : string; + attribute x_core_info of Inverter_3lvl_P0N_3lvl_1_1 : entity is "P0N_3lvl,Vivado 2019.1"; +end Inverter_3lvl_P0N_3lvl_1_1; + +architecture STRUCTURE of Inverter_3lvl_P0N_3lvl_1_1 is + attribute x_interface_info : string; + attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; +begin +U0: entity work.Inverter_3lvl_P0N_3lvl_1_1_P0N_3lvl + port map ( + PWM_out_0 => PWM_out_0, + PWM_out_1 => PWM_out_1, + PWM_out_2 => PWM_out_2, + PWM_out_3 => PWM_out_3, + TKin0 => TKin0, + TKin1 => TKin1, + breaking_en => breaking_en, + deadTime(31 downto 0) => deadTime(31 downto 0), + er => er, + externalCLK => externalCLK, + minTime(31 downto 0) => minTime(31 downto 0), + minTimeEr_reg_0 => minTimeEr, + minTime_En => minTime_En, + ready => ready, + reset => reset + ); +end STRUCTURE; diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1_stub.v b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1_stub.v new file mode 100644 index 0000000..2501d99 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1_stub.v @@ -0,0 +1,35 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Fri Jun 11 07:49:57 2021 +// Host : STAS-W10 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top Inverter_3lvl_P0N_3lvl_1_1 -prefix +// Inverter_3lvl_P0N_3lvl_1_1_ Inverter_3lvl_P0N_3lvl_0_4_stub.v +// Design : Inverter_3lvl_P0N_3lvl_0_4 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg484-3 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "P0N_3lvl,Vivado 2019.1" *) +module Inverter_3lvl_P0N_3lvl_1_1(externalCLK, ready, reset, deadTime, minTime, er, + minTime_En, minTimeEr, TKin0, TKin1, breaking_en, PWM_out_0, PWM_out_1, PWM_out_2, PWM_out_3) +/* synthesis syn_black_box black_box_pad_pin="externalCLK,ready,reset,deadTime[31:0],minTime[31:0],er,minTime_En,minTimeEr,TKin0,TKin1,breaking_en,PWM_out_0,PWM_out_1,PWM_out_2,PWM_out_3" */; + input externalCLK; + input ready; + input reset; + input [31:0]deadTime; + input [31:0]minTime; + input er; + input minTime_En; + output minTimeEr; + input TKin0; + input TKin1; + input breaking_en; + output PWM_out_0; + output PWM_out_1; + output PWM_out_2; + output PWM_out_3; +endmodule diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1_stub.vhdl b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1_stub.vhdl new file mode 100644 index 0000000..35e9792 --- /dev/null +++ b/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_1_1/Inverter_3lvl_P0N_3lvl_1_1_stub.vhdl @@ -0,0 +1,44 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Fri Jun 11 07:49:57 2021 +-- Host : STAS-W10 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top Inverter_3lvl_P0N_3lvl_1_1 -prefix +-- Inverter_3lvl_P0N_3lvl_1_1_ Inverter_3lvl_P0N_3lvl_0_4_stub.vhdl +-- Design : Inverter_3lvl_P0N_3lvl_0_4 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg484-3 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Inverter_3lvl_P0N_3lvl_1_1 is + Port ( + externalCLK : in STD_LOGIC; + ready : in STD_LOGIC; + reset : in STD_LOGIC; + deadTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + minTime : in STD_LOGIC_VECTOR ( 31 downto 0 ); + er : in STD_LOGIC; + minTime_En : in STD_LOGIC; + minTimeEr : out STD_LOGIC; + TKin0 : in STD_LOGIC; + TKin1 : in STD_LOGIC; + breaking_en : in STD_LOGIC; + PWM_out_0 : out STD_LOGIC; + PWM_out_1 : out STD_LOGIC; + PWM_out_2 : out STD_LOGIC; + PWM_out_3 : out STD_LOGIC + ); + +end Inverter_3lvl_P0N_3lvl_1_1; + +architecture stub of Inverter_3lvl_P0N_3lvl_1_1 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "externalCLK,ready,reset,deadTime[31:0],minTime[31:0],er,minTime_En,minTimeEr,TKin0,TKin1,breaking_en,PWM_out_0,PWM_out_1,PWM_out_2,PWM_out_3"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "P0N_3lvl,Vivado 2019.1"; +begin +end; diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.xpr b/LIB/Inverter_3lvl/Inverter_3lvl.xpr index 00b5cca..21087b5 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.xpr +++ b/LIB/Inverter_3lvl/Inverter_3lvl.xpr @@ -3,7 +3,7 @@ - +

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-1,167 +0,0 @@ -# -# Synthesis run script generated by Vivado -# - -set TIME_start [clock seconds] -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -set_param project.vivado.isBlockSynthRun true -create_project -in_memory -part xc7z020clg484-3 - -set_param project.singleFileAddWarning.threshold 0 -set_param project.compositeFile.enableAutoGeneration 0 -set_param synth.vivado.isSynthRun true -set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.cache/wt [current_project] -set_property parent.project_path D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.xpr [current_project] -set_property default_lib xil_defaultlib [current_project] -set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/GITEA/UPzynq20_test/IP [current_project] -update_ip_catalog -set_property ip_output_repo d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.cache/ip [current_project] -set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3.xci - -# Mark all dcp files as not used in implementation to prevent them from being -# stitched into the results of this synthesis run. Any black boxes in the -# design are intentionally left as such for best results. Dcp files will be -# stitched into the design at a later time, either when this synthesis run is -# opened, or when it is stitched into a dependent implementation run. -foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { - set_property used_in_implementation false $dcp -} -set_param ips.enableIPCacheLiteLoad 1 - -set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1 -new_name Inverter_3lvl_P0N_3lvl_0_3 -ip [get_ips Inverter_3lvl_P0N_3lvl_0_3]] - -if { $cached_ip eq {} } { -close [open __synthesis_is_running__ w] - -synth_design -top Inverter_3lvl_P0N_3lvl_0_3 -part xc7z020clg484-3 -mode out_of_context - -#--------------------------------------------------------- -# Generate Checkpoint/Stub/Simulation Files For IP Cache -#--------------------------------------------------------- -# disable binary constraint mode for IPCache checkpoints -set_param constraints.enableBinaryConstraints false - -catch { - write_checkpoint -force -noxdef -rename_prefix Inverter_3lvl_P0N_3lvl_0_3_ Inverter_3lvl_P0N_3lvl_0_3.dcp - - set ipCachedFiles {} - write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_3_stub.v - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_0_3_stub.v - - write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_3_stub.vhdl - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_0_3_stub.vhdl - - write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_3_sim_netlist.v - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_0_3_sim_netlist.v - - write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Inverter_3lvl_P0N_3lvl_0_3_sim_netlist.vhdl - lappend ipCachedFiles Inverter_3lvl_P0N_3lvl_0_3_sim_netlist.vhdl -set TIME_taken [expr [clock seconds] - $TIME_start] - - config_ip_cache -add -dcp Inverter_3lvl_P0N_3lvl_0_3.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips Inverter_3lvl_P0N_3lvl_0_3] -} - -rename_ref -prefix_all Inverter_3lvl_P0N_3lvl_0_3_ - -# disable binary constraint mode for synth run checkpoints -set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef Inverter_3lvl_P0N_3lvl_0_3.dcp -create_report "Inverter_3lvl_P0N_3lvl_0_3_synth_1_synth_report_utilization_0" "report_utilization -file Inverter_3lvl_P0N_3lvl_0_3_utilization_synth.rpt -pb Inverter_3lvl_P0N_3lvl_0_3_utilization_synth.pb" - -if { [catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3.dcp D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3.dcp -} _RESULT ] } { - send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." - error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." -} - -if { [catch { - write_verilog -force -mode synth_stub D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode synth_stub D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_verilog -force -mode funcsim D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode funcsim D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - - -} else { - - -if { [catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3.dcp D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3.dcp -} _RESULT ] } { - send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." - error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3_stub.v D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3_stub.vhdl D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3_sim_netlist.v D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3_sim_netlist.vhdl D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -}; # end if cached_ip - -if {[file isdir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_0_3]} { - catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3_stub.v D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_0_3 - } -} - -if {[file isdir D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_0_3]} { - catch { - file copy -force D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/Inverter_3lvl_P0N_3lvl_0_3_stub.vhdl D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.ip_user_files/ip/Inverter_3lvl_P0N_3lvl_0_3 - } -} -file delete __synthesis_is_running__ -close [open __synthesis_is_complete__ w] diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3.vds b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3.vds deleted file mode 100644 index 8a7252f..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3.vds +++ /dev/null @@ -1,275 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1 (64-bit) -# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 -# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Fri Jun 11 07:49:17 2021 -# Process ID: 11024 -# Current directory: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1 -# Command line: vivado.exe -log Inverter_3lvl_P0N_3lvl_0_3.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_3.tcl -# Log file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3.vds -# Journal file: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1\vivado.jou -#----------------------------------------------------------- -source Inverter_3lvl_P0N_3lvl_0_3.tcl -notrace -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/UPzynq20_test/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/UPzynq20_test/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1'.) -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -Command: synth_design -top Inverter_3lvl_P0N_3lvl_0_3 -part xc7z020clg484-3 -mode out_of_context -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020' -INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 3136 ---------------------------------------------------------------------------------- -Starting Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 573.750 ; gain = 180.781 ---------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_3' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/synth/Inverter_3lvl_P0N_3lvl_0_3.vhd:76] -INFO: [Synth 8-3491] module 'P0N_3lvl' declared at 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:36' bound to instance 'U0' of component 'P0N_3lvl' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/synth/Inverter_3lvl_P0N_3lvl_0_3.vhd:109] -INFO: [Synth 8-638] synthesizing module 'P0N_3lvl' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:61] -WARNING: [Synth 8-6014] Unused sequential element TKin0_prev_reg was removed. [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:154] -WARNING: [Synth 8-6014] Unused sequential element TKin1_prev_reg was removed. [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:155] -INFO: [Synth 8-256] done synthesizing module 'P0N_3lvl' (1#1) [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:61] -INFO: [Synth 8-256] done synthesizing module 'Inverter_3lvl_P0N_3lvl_0_3' (2#1) [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/synth/Inverter_3lvl_P0N_3lvl_0_3.vhd:76] ---------------------------------------------------------------------------------- -Finished Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 638.348 ; gain = 245.379 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 638.348 ; gain = 245.379 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Loading Part and Timing Information ---------------------------------------------------------------------------------- -Loading part: xc7z020clg484-3 ---------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 638.348 ; gain = 245.379 ---------------------------------------------------------------------------------- -INFO: [Device 21-403] Loading part xc7z020clg484-3 -INFO: [Synth 8-4471] merging register 'minTimeEr_sig_reg' into 'minTimeEr_reg' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:98] -INFO: [Synth 8-802] inferred FSM for state register 'lineconfig_reg' in module 'P0N_3lvl' ---------------------------------------------------------------------------------------------------- - State | New Encoding | Previous Encoding ---------------------------------------------------------------------------------------------------- - closed | 0000001 | 000 - n | 0000010 | 110 - tech_closed | 0000100 | 001 - p | 0001000 | 101 - zero_p | 0010000 | 011 - zero | 0100000 | 010 - zero_n | 1000000 | 100 ---------------------------------------------------------------------------------------------------- -INFO: [Synth 8-3354] encoded FSM with state register 'lineconfig_reg' using encoding 'one-hot' in module 'P0N_3lvl' ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 638.348 ; gain = 245.379 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ -No constraint files found. ---------------------------------------------------------------------------------- -Start RTL Component Statistics ---------------------------------------------------------------------------------- -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 19 -+---Muxes : - 7 Input 7 Bit Muxes := 1 - 2 Input 7 Bit Muxes := 16 - 2 Input 1 Bit Muxes := 47 - 7 Input 1 Bit Muxes := 10 ---------------------------------------------------------------------------------- -Finished RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- -Hierarchical RTL Component report -Module P0N_3lvl -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 19 -+---Muxes : - 7 Input 7 Bit Muxes := 1 - 2 Input 7 Bit Muxes := 16 - 2 Input 1 Bit Muxes := 47 - 7 Input 1 Bit Muxes := 10 ---------------------------------------------------------------------------------- -Finished RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Part Resource Summary ---------------------------------------------------------------------------------- -Part Resources: -DSPs: 220 (col length:60) -BRAMs: 280 (col length: RAMB18 60 RAMB36 30) ---------------------------------------------------------------------------------- -Finished Part Resource Summary ---------------------------------------------------------------------------------- -No constraint files found. ---------------------------------------------------------------------------------- -Start Cross Boundary and Area Optimization ---------------------------------------------------------------------------------- -Warning: Parallel synthesis criteria is not met ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 802.023 ; gain = 409.055 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ -No constraint files found. ---------------------------------------------------------------------------------- -Start Timing Optimization ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 808.801 ; gain = 415.832 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Technology Mapping ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 808.977 ; gain = 416.008 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 808.977 ; gain = 416.008 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Renaming Generated Instances ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 808.977 ; gain = 416.008 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Rebuilding User Hierarchy ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 808.977 ; gain = 416.008 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Ports ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 808.977 ; gain = 416.008 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 808.977 ; gain = 416.008 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Nets ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 808.977 ; gain = 416.008 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Writing Synthesis Report ---------------------------------------------------------------------------------- - -Report BlackBoxes: -+-+--------------+----------+ -| |BlackBox name |Instances | -+-+--------------+----------+ -+-+--------------+----------+ - -Report Cell Usage: -+------+-------+------+ -| |Cell |Count | -+------+-------+------+ -|1 |CARRY4 | 36| -|2 |LUT1 | 4| -|3 |LUT2 | 7| -|4 |LUT3 | 4| -|5 |LUT4 | 108| -|6 |LUT5 | 7| -|7 |LUT6 | 23| -|8 |FDRE | 121| -|9 |FDSE | 1| -+------+-------+------+ - -Report Instance Areas: -+------+---------+---------+------+ -| |Instance |Module |Cells | -+------+---------+---------+------+ -|1 |top | | 311| -|2 | U0 |P0N_3lvl | 311| -+------+---------+---------+------+ ---------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 808.977 ; gain = 416.008 ---------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 808.977 ; gain = 416.008 -Synthesis Optimization Complete : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 808.977 ; gain = 416.008 -INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 36 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 925.750 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -INFO: [Common 17-83] Releasing license: Synthesis -20 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. -synth_design completed successfully -synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 925.750 ; gain = 537.621 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 925.750 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Common 17-1381] The checkpoint 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3.dcp' has been generated. -write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1380.430 ; gain = 454.680 -WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -WARNING: [IP_Flow 19-5475] Invalid IP Cache entry found. Please manually delete the directory 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.cache/ip/2019.1/fdc8b3b6ee8afc45' -WARNING: [Coretcl 2-1488] Problem adding IP cache entry: -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1380.586 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file Inverter_3lvl_P0N_3lvl_0_3_utilization_synth.rpt -pb Inverter_3lvl_P0N_3lvl_0_3_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Fri Jun 11 07:49:58 2021... diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3_utilization_synth.pb b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3_utilization_synth.pb deleted file mode 100644 index 8641ec5bc586b56d5651fdc89efd9a3e48bd2460..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 224 zcmd;LGcqu=)H9sKtPxzAo10ivsgR$hP+F3ilUbEml9`_e;%28-Dioy_=a&{Grxxp- z;xw0+;lg?Mr@Xr_zp{NR#K3UCX|FKD1%LNe5xo-@cD<4eKyX)*;X}LIQYjF7 ztvrbQ3nV?9k1BxJXH`MuTr~y;9_Ob(l7XSu2t?imk}=LpjX~_S79jF3h;%w?31UyO o;&2Leb9W92@;Pe<5}0exz|i3E6i6~KymbMQdtE^yt!^MT0GGTwl>h($ diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3_utilization_synth.rpt b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3_utilization_synth.rpt deleted file mode 100644 index cb14df2..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3_utilization_synth.rpt +++ /dev/null @@ -1,176 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------ -| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 -| Date : Fri Jun 11 07:49:58 2021 -| Host : STAS-W10 running 64-bit major release (build 9200) -| Command : report_utilization -file Inverter_3lvl_P0N_3lvl_0_3_utilization_synth.rpt -pb Inverter_3lvl_P0N_3lvl_0_3_utilization_synth.pb -| Design : Inverter_3lvl_P0N_3lvl_0_3 -| Device : 7z020clg484-3 -| Design State : Synthesized ------------------------------------------------------------------------------------------------------------------------------------------------ - -Utilization Design Information - -Table of Contents ------------------ -1. Slice Logic -1.1 Summary of Registers by Type -2. Memory -3. DSP -4. IO and GT Specific -5. Clocking -6. Specific Feature -7. Primitives -8. Black Boxes -9. Instantiated Netlists - -1. Slice Logic --------------- - -+-------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 96 | 0 | 53200 | 0.18 | -| LUT as Logic | 96 | 0 | 53200 | 0.18 | -| LUT as Memory | 0 | 0 | 17400 | 0.00 | -| Slice Registers | 122 | 0 | 106400 | 0.11 | -| Register as Flip Flop | 122 | 0 | 106400 | 0.11 | -| Register as Latch | 0 | 0 | 106400 | 0.00 | -| F7 Muxes | 0 | 0 | 26600 | 0.00 | -| F8 Muxes | 0 | 0 | 13300 | 0.00 | -+-------------------------+------+-------+-----------+-------+ -* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. - - -1.1 Summary of Registers by Type --------------------------------- - -+-------+--------------+-------------+--------------+ -| Total | Clock Enable | Synchronous | Asynchronous | -+-------+--------------+-------------+--------------+ -| 0 | _ | - | - | -| 0 | _ | - | Set | -| 0 | _ | - | Reset | -| 0 | _ | Set | - | -| 0 | _ | Reset | - | -| 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 0 | Yes | - | Reset | -| 1 | Yes | Set | - | -| 121 | Yes | Reset | - | -+-------+--------------+-------------+--------------+ - - -2. Memory ---------- - -+----------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------+------+-------+-----------+-------+ -| Block RAM Tile | 0 | 0 | 140 | 0.00 | -| RAMB36/FIFO* | 0 | 0 | 140 | 0.00 | -| RAMB18 | 0 | 0 | 280 | 0.00 | -+----------------+------+-------+-----------+-------+ -* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 - - -3. DSP ------- - -+-----------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------+------+-------+-----------+-------+ -| DSPs | 0 | 0 | 220 | 0.00 | -+-----------+------+-------+-----------+-------+ - - -4. IO and GT Specific ---------------------- - -+-----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 0 | 0 | 200 | 0.00 | -| Bonded IPADs | 0 | 0 | 2 | 0.00 | -| Bonded IOPADs | 0 | 0 | 130 | 0.00 | -| PHY_CONTROL | 0 | 0 | 4 | 0.00 | -| PHASER_REF | 0 | 0 | 4 | 0.00 | -| OUT_FIFO | 0 | 0 | 16 | 0.00 | -| IN_FIFO | 0 | 0 | 16 | 0.00 | -| IDELAYCTRL | 0 | 0 | 4 | 0.00 | -| IBUFDS | 0 | 0 | 192 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 16 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 16 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 200 | 0.00 | -| ILOGIC | 0 | 0 | 200 | 0.00 | -| OLOGIC | 0 | 0 | 200 | 0.00 | -+-----------------------------+------+-------+-----------+-------+ - - -5. Clocking ------------ - -+------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+------------+------+-------+-----------+-------+ -| BUFGCTRL | 0 | 0 | 32 | 0.00 | -| BUFIO | 0 | 0 | 16 | 0.00 | -| MMCME2_ADV | 0 | 0 | 4 | 0.00 | -| PLLE2_ADV | 0 | 0 | 4 | 0.00 | -| BUFMRCE | 0 | 0 | 8 | 0.00 | -| BUFHCE | 0 | 0 | 72 | 0.00 | -| BUFR | 0 | 0 | 16 | 0.00 | -+------------+------+-------+-----------+-------+ - - -6. Specific Feature -------------------- - -+-------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------+------+-------+-----------+-------+ -| BSCANE2 | 0 | 0 | 4 | 0.00 | -| CAPTUREE2 | 0 | 0 | 1 | 0.00 | -| DNA_PORT | 0 | 0 | 1 | 0.00 | -| EFUSE_USR | 0 | 0 | 1 | 0.00 | -| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | -| ICAPE2 | 0 | 0 | 2 | 0.00 | -| STARTUPE2 | 0 | 0 | 1 | 0.00 | -| XADC | 0 | 0 | 1 | 0.00 | -+-------------+------+-------+-----------+-------+ - - -7. Primitives -------------- - -+----------+------+---------------------+ -| Ref Name | Used | Functional Category | -+----------+------+---------------------+ -| FDRE | 121 | Flop & Latch | -| LUT4 | 108 | LUT | -| CARRY4 | 36 | CarryLogic | -| LUT6 | 23 | LUT | -| LUT5 | 7 | LUT | -| LUT2 | 7 | LUT | -| LUT3 | 4 | LUT | -| LUT1 | 4 | LUT | -| FDSE | 1 | Flop & Latch | -+----------+------+---------------------+ - - -8. Black Boxes --------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - -9. Instantiated Netlists ------------------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/__synthesis_is_complete__ b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/__synthesis_is_complete__ deleted file mode 100644 index e69de29..0000000 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/gen_run.xml b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/gen_run.xml deleted file mode 100644 index f633e3b..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/gen_run.xml +++ /dev/null @@ -1,54 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Vivado Synthesis Defaults - - - - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/htr.txt b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/htr.txt deleted file mode 100644 index b2e0fc3..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -REM -REM Vivado(TM) -REM htr.txt: a Vivado-generated description of how-to-repeat the -REM the basic steps of a run. Note that runme.bat/sh needs -REM to be invoked for Vivado to track run status. -REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -REM - -vivado -log Inverter_3lvl_P0N_3lvl_0_3.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_3.tcl diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/project.wdf b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/project.wdf deleted file mode 100644 index 66cddab..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/project.wdf +++ /dev/null @@ -1,44 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3131:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3131:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 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-70726f6a656374:69705f636f72655f636f6e7461696e65725c50304e5f336c766c5f76315f305f345c496e7665727465725f336c766c5f50304e5f336c766c5f305f32:636f72655f636f6e7461696e6572:66616c7365:00:00 -70726f6a656374:69705f636f72655f636f6e7461696e65725c50304e5f336c766c5f76315f305f345c496e7665727465725f336c766c5f50304e5f336c766c5f305f33:636f72655f636f6e7461696e6572:66616c7365:00:00 -70726f6a656374:69705f636f72655f636f6e7461696e65725c50304e5f336c766c5f76315f305f345c496e7665727465725f336c766c5f50304e5f336c766c5f305f34:636f72655f636f6e7461696e6572:66616c7365:00:00 -70726f6a656374:69705f636f72655f636f6e7461696e65725c50304e5f336c766c5f76315f305f345c496e7665727465725f336c766c5f50304e5f336c766c5f305f35:636f72655f636f6e7461696e6572:66616c7365:00:00 -70726f6a656374:69705f636f72655f636f6e7461696e65725c50304e5f336c766c5f76315f305f345c496e7665727465725f336c766c5f50304e5f336c766c5f315f30:636f72655f636f6e7461696e6572:66616c7365:00:00 -70726f6a656374:69705f636f72655f636f6e7461696e65725c50304e5f336c766c5f76315f305f345c496e7665727465725f336c766c5f50304e5f336c766c5f315f31:636f72655f636f6e7461696e6572:66616c7365:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:35:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:35:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:35:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:35:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:35:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:35:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:35:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3535323030373536376161373461663938353435666431303963343433336437:506172656e742050412070726f6a656374204944:00 -eof:2238049497 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/rundef.js b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/rundef.js deleted file mode 100644 index 2ca3dc8..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/rundef.js +++ /dev/null @@ -1,36 +0,0 @@ -// -// Vivado(TM) -// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.1/bin;"; -} else { - PathVal = "D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.1/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; -eval( EAInclude(ISEJScriptLib) ); - - -ISEStep( "vivado", - "-log Inverter_3lvl_P0N_3lvl_0_3.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_3.tcl" ); - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/runme.bat b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/runme.bat deleted file mode 100644 index 1760626..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/runme.bat +++ /dev/null @@ -1,10 +0,0 @@ -@echo off - -rem Vivado (TM) -rem runme.bat: a Vivado-generated Script -rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/runme.log b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/runme.log deleted file mode 100644 index 997023f..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/runme.log +++ /dev/null @@ -1,274 +0,0 @@ - -*** Running vivado - with args -log Inverter_3lvl_P0N_3lvl_0_3.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_3.tcl - - -****** Vivado v2019.1 (64-bit) - **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 - **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source Inverter_3lvl_P0N_3lvl_0_3.tcl -notrace -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/UPzynq20_test/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/UPzynq20_test/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1'.) -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -Command: synth_design -top Inverter_3lvl_P0N_3lvl_0_3 -part xc7z020clg484-3 -mode out_of_context -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020' -INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 3136 ---------------------------------------------------------------------------------- -Starting Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 573.750 ; gain = 180.781 ---------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_P0N_3lvl_0_3' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/synth/Inverter_3lvl_P0N_3lvl_0_3.vhd:76] -INFO: [Synth 8-3491] module 'P0N_3lvl' declared at 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:36' bound to instance 'U0' of component 'P0N_3lvl' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/synth/Inverter_3lvl_P0N_3lvl_0_3.vhd:109] -INFO: [Synth 8-638] synthesizing module 'P0N_3lvl' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:61] -WARNING: [Synth 8-6014] Unused sequential element TKin0_prev_reg was removed. [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:154] -WARNING: [Synth 8-6014] Unused sequential element TKin1_prev_reg was removed. [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:155] -INFO: [Synth 8-256] done synthesizing module 'P0N_3lvl' (1#1) [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:61] -INFO: [Synth 8-256] done synthesizing module 'Inverter_3lvl_P0N_3lvl_0_3' (2#1) [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_P0N_3lvl_0_3/synth/Inverter_3lvl_P0N_3lvl_0_3.vhd:76] ---------------------------------------------------------------------------------- -Finished Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 638.348 ; gain = 245.379 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 638.348 ; gain = 245.379 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Loading Part and Timing Information ---------------------------------------------------------------------------------- -Loading part: xc7z020clg484-3 ---------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 638.348 ; gain = 245.379 ---------------------------------------------------------------------------------- -INFO: [Device 21-403] Loading part xc7z020clg484-3 -INFO: [Synth 8-4471] merging register 'minTimeEr_sig_reg' into 'minTimeEr_reg' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/ada7/P0N_3lvl.vhd:98] -INFO: [Synth 8-802] inferred FSM for state register 'lineconfig_reg' in module 'P0N_3lvl' ---------------------------------------------------------------------------------------------------- - State | New Encoding | Previous Encoding ---------------------------------------------------------------------------------------------------- - closed | 0000001 | 000 - n | 0000010 | 110 - tech_closed | 0000100 | 001 - p | 0001000 | 101 - zero_p | 0010000 | 011 - zero | 0100000 | 010 - zero_n | 1000000 | 100 ---------------------------------------------------------------------------------------------------- -INFO: [Synth 8-3354] encoded FSM with state register 'lineconfig_reg' using encoding 'one-hot' in module 'P0N_3lvl' ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 638.348 ; gain = 245.379 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ -No constraint files found. ---------------------------------------------------------------------------------- -Start RTL Component Statistics ---------------------------------------------------------------------------------- -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 19 -+---Muxes : - 7 Input 7 Bit Muxes := 1 - 2 Input 7 Bit Muxes := 16 - 2 Input 1 Bit Muxes := 47 - 7 Input 1 Bit Muxes := 10 ---------------------------------------------------------------------------------- -Finished RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- -Hierarchical RTL Component report -Module P0N_3lvl -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 19 -+---Muxes : - 7 Input 7 Bit Muxes := 1 - 2 Input 7 Bit Muxes := 16 - 2 Input 1 Bit Muxes := 47 - 7 Input 1 Bit Muxes := 10 ---------------------------------------------------------------------------------- -Finished RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Part Resource Summary ---------------------------------------------------------------------------------- -Part Resources: -DSPs: 220 (col length:60) -BRAMs: 280 (col length: RAMB18 60 RAMB36 30) ---------------------------------------------------------------------------------- -Finished Part Resource Summary ---------------------------------------------------------------------------------- -No constraint files found. ---------------------------------------------------------------------------------- -Start Cross Boundary and Area Optimization ---------------------------------------------------------------------------------- -Warning: Parallel synthesis criteria is not met ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 802.023 ; gain = 409.055 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ -No constraint files found. ---------------------------------------------------------------------------------- -Start Timing Optimization ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 808.801 ; gain = 415.832 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Technology Mapping ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 808.977 ; gain = 416.008 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 808.977 ; gain = 416.008 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Renaming Generated Instances ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 808.977 ; gain = 416.008 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Rebuilding User Hierarchy ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 808.977 ; gain = 416.008 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Ports ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 808.977 ; gain = 416.008 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 808.977 ; gain = 416.008 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Nets ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 808.977 ; gain = 416.008 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Writing Synthesis Report ---------------------------------------------------------------------------------- - -Report BlackBoxes: -+-+--------------+----------+ -| |BlackBox name |Instances | -+-+--------------+----------+ -+-+--------------+----------+ - -Report Cell Usage: -+------+-------+------+ -| |Cell |Count | -+------+-------+------+ -|1 |CARRY4 | 36| -|2 |LUT1 | 4| -|3 |LUT2 | 7| -|4 |LUT3 | 4| -|5 |LUT4 | 108| -|6 |LUT5 | 7| -|7 |LUT6 | 23| -|8 |FDRE | 121| -|9 |FDSE | 1| -+------+-------+------+ - -Report Instance Areas: -+------+---------+---------+------+ -| |Instance |Module |Cells | -+------+---------+---------+------+ -|1 |top | | 311| -|2 | U0 |P0N_3lvl | 311| -+------+---------+---------+------+ ---------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 808.977 ; gain = 416.008 ---------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 808.977 ; gain = 416.008 -Synthesis Optimization Complete : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 808.977 ; gain = 416.008 -INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 36 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 925.750 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -INFO: [Common 17-83] Releasing license: Synthesis -20 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. -synth_design completed successfully -synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 925.750 ; gain = 537.621 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 925.750 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Common 17-1381] The checkpoint 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3.dcp' has been generated. -write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1380.430 ; gain = 454.680 -WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -WARNING: [IP_Flow 19-5475] Invalid IP Cache entry found. Please manually delete the directory 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.cache/ip/2019.1/fdc8b3b6ee8afc45' -WARNING: [Coretcl 2-1488] Problem adding IP cache entry: -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1380.586 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/Inverter_3lvl_P0N_3lvl_0_3.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file Inverter_3lvl_P0N_3lvl_0_3_utilization_synth.rpt -pb Inverter_3lvl_P0N_3lvl_0_3_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Fri Jun 11 07:49:58 2021... diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/runme.sh b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/runme.sh deleted file mode 100644 index c2e85d8..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/runme.sh +++ /dev/null @@ -1,43 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# runme.sh: a Vivado-generated Runs Script for UNIX -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# - -echo "This script was generated under a different operating system." -echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" -exit - -if [ -z "$PATH" ]; then - PATH=D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.1/bin -else - PATH=D:/Xilinx/SDK/2019.1/bin;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.1/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH= -else - LD_LIBRARY_PATH=:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1' -cd "$HD_PWD" - -HD_LOG=runme.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrap.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -EAStep vivado -log Inverter_3lvl_P0N_3lvl_0_3.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_P0N_3lvl_0_3.tcl diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/vivado.jou b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/vivado.jou deleted file mode 100644 index 3a2e73b..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1 (64-bit) -# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 -# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Fri Jun 11 07:49:17 2021 -# Process ID: 11024 -# Current directory: D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_3_synth_1 -# Command line: vivado.exe -log Inverter_3lvl_P0N_3lvl_0_3.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source 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deleted file mode 100644 index 015507c..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/.vivado.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/.vivado.end.rst b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/.vivado.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/ISEWrap.js b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/ISEWrap.js deleted file mode 100644 index 97a2ecb..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/ISEWrap.js +++ /dev/null @@ -1,270 +0,0 @@ -// -// Vivado(TM) -// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 -// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. -// - -// GLOBAL VARIABLES -var ISEShell = new ActiveXObject( "WScript.Shell" ); -var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); -var ISERunDir = ""; -var ISELogFile = "runme.log"; -var ISELogFileStr = null; -var ISELogEcho = true; -var ISEOldVersionWSH = false; - - - -// BOOTSTRAP -ISEInit(); - - - -// -// ISE FUNCTIONS -// -function ISEInit() { - - // 1. RUN DIR setup - var ISEScrFP = WScript.ScriptFullName; - var ISEScrN = WScript.ScriptName; - ISERunDir = - ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); - - // 2. LOG file setup - ISELogFileStr = ISEOpenFile( ISELogFile ); - - // 3. LOG echo? - var ISEScriptArgs = WScript.Arguments; - for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var wbemFlagReturnImmediately = 0x10; - var wbemFlagForwardOnly = 0x20; - var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); - var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); - var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); - var NOC = 0; - var NOLP = 0; - var TPM = 0; - - var cpuInfos = new Enumerator(processor); - for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { - var cpuInfo = cpuInfos.item(); - NOC += cpuInfo.NumberOfCores; - NOLP += cpuInfo.NumberOfLogicalProcessors; - } - var csInfos = new Enumerator(computerSystem); - for(;!csInfos.atEnd(); csInfos.moveNext()) { - var csInfo = csInfos.item(); - TPM += csInfo.TotalPhysicalMemory; - } - - var ISEHOSTCORE = NOLP - var ISEMEMTOTAL = TPM - - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/ISEWrap.sh b/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/ISEWrap.sh deleted file mode 100644 index f679f2e..0000000 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_P0N_3lvl_0_4_synth_1/ISEWrap.sh +++ /dev/null @@ -1,67 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -# - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! -if [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi -ISE_USER=$USER - -ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) -ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) - -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 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zickWk?9v$V2ByaJ4INey3c80ARU}Kn;voJC^hdFBg!x#Mqu^r4&3-(P4A?aFky=5L z_IrG`o4wJPK5evsV2O|g-v_iu+Q$2k_ z0zYv%5F;F(bgk6ftN9g9ckx(SrMx9>M_vLLj51h=Ed`o|zyi0D>t^==PlT6wo6Ou? z!C3AE(+J|iXKbSkD2bC8%+#s%^Bq%NlD&Qi_WDh_n^teCBcY%4_5MpkOz-Ck>f7O4 zHbr^jEi=G-jpXq7Zo!ass6hZC_A@$;;(%>18rg7_U?6fY)+yA`TmxD%4xgso8vG8> ztE!#&F(U29#o4PC@M}wH`_d~*>E<;0Kv9~2aex=K`PpL!;<8jGK0NE-kEV+(HC*gc zYga3%Q#2+a1suv#w7KO1ya?rJu#mg@{zpJHG0~DD<4~OBmxi)i1VE%^TDuJ5xS4XH z_{Oy5cS6ksRap(rGZLjTPifG4Tg(w47?DzLHh~(CE%)as=710U{a3IzHFX0JgFW%W zA$Ja!dY_nmiOhj$A%s`J>E2^5w`~k=umxIMjl2GOb>dO;i`m)A#ZlBBCY%ol1!-Uq zAfW%pN9fMeX%qP7h~so6asSKVH>WN59}ZCp66yaR zg}9k-{fp3l=`r~K_xt}HiVScdAjtpP@Sn&4`DBZHf3$CGPw#4Dtso5!@ec?4eFcI7 L0p*MRbN9ah#}1CO diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/AckChecker_AckCheckerConcept_0_3.tcl b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/AckChecker_AckCheckerConcept_0_3.tcl index 6e0e424..7d50e71 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/AckChecker_AckCheckerConcept_0_3.tcl +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/AckChecker_AckCheckerConcept_0_3.tcl @@ -24,15 +24,15 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] -set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] +set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] +set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/Projects/IP [current_project] +set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project] update_ip_catalog -set_property ip_output_repo d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] +set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3.xci +read_ip -quiet D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3.xci # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1 -new_name AckChecker_AckCheckerConcept_0_3 -ip [get_ips AckChecker_AckCheckerConcept_0_3]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1 -new_name AckChecker_AckCheckerConcept_0_3 -ip [get_ips AckChecker_AckCheckerConcept_0_3]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_AckCheckerConcept_0_3.dcp create_report "AckChecker_AckCheckerConcept_0_3_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_AckCheckerConcept_0_3_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_0_3_utilization_synth.pb" if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/AckChecker_AckCheckerConcept_0_3.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/AckChecker_AckCheckerConcept_0_3.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_stub.v + write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_stub.vhdl + write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_sim_netlist.v + write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,47 +120,47 @@ if { [catch { if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/AckChecker_AckCheckerConcept_0_3.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/AckChecker_AckCheckerConcept_0_3.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/AckChecker_AckCheckerConcept_0_3_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_stub.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/AckChecker_AckCheckerConcept_0_3_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/AckChecker_AckCheckerConcept_0_3_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_stub.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/AckChecker_AckCheckerConcept_0_3_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/AckChecker_AckCheckerConcept_0_3_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_sim_netlist.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/AckChecker_AckCheckerConcept_0_3_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/AckChecker_AckCheckerConcept_0_3_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_sim_netlist.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/AckChecker_AckCheckerConcept_0_3_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_3]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_3]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_3 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_3 } } -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_3]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_3]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_3 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_0_3/AckChecker_AckCheckerConcept_0_3_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_0_3 } } file delete __synthesis_is_running__ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/AckChecker_AckCheckerConcept_0_3.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/AckChecker_AckCheckerConcept_0_3.vds index 7a8c204..12851a3 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/AckChecker_AckCheckerConcept_0_3.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/AckChecker_AckCheckerConcept_0_3.vds @@ -2,17 +2,17 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:11 2020 -# Process ID: 17184 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1 +# Start of session at: Wed May 3 11:35:58 2023 +# Process ID: 15884 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_0_3.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_0_3.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/AckChecker_AckCheckerConcept_0_3.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/AckChecker_AckCheckerConcept_0_3.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_0_3.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_0_3, cache-ID = 75535be1b50c31fe. -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:05:18 2020... +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_0_3, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:06 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/gen_run.xml index 84406b5..3c06c78 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/gen_run.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/project.wdf deleted file mode 100644 index 1c85d85..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:95469607 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/runme.log new file mode 100644 index 0000000..fef0cb6 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_AckCheckerConcept_0_3.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_0_3.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_0_3.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_0_3, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:06 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/runme.sh index 98c5490..d3e2cb8 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/vivado.jou index bf54209..f51b01f 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:11 2020 -# Process ID: 17184 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1 +# Start of session at: Wed May 3 11:35:58 2023 +# Process ID: 15884 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_0_3.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_0_3.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/AckChecker_AckCheckerConcept_0_3.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/AckChecker_AckCheckerConcept_0_3.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_0_3.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_3_synth_1/vivado.pb index 957b538fc8a515f0a4f6386c00b7bd777549d66f..47c52de74fd83c17407a4546952d7ef78403e1ac 100644 GIT binary patch delta 183 zcmZqYSkE!RnXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@x)GbrWwo= zH(d(Aug-`)B{eOvG^fN0#xQDRf}x3(fvJ_D Og@TcRk-_9&%%%Vg^eox{ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_4_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_4_synth_1/.vivado.begin.rst index 1d002f9..f649997 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_4_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_4_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_4_synth_1/AckChecker_AckCheckerConcept_0_4.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_4_synth_1/AckChecker_AckCheckerConcept_0_4.dcp index 871b074653e36f49b176653504f3f647b3760f7e..b80c688390fdcd5856c4e9f20430231a942b717e 100644 GIT binary patch delta 16381 zcmZv@18`;A7B(8&wr$(CZQDjCJGO13V;ddYb~?7*NhdGo-249e@2j_}#vF5f`x|4< zwW?Ot9N2v+z=tWoSW2>>U}!)K!eA0Knwo}-8kzwHD#{;sd(GU9K~?^I)%q}h;9e7GcA6dOMdzIt&fbF=P&14KM__{$(&L8Np zx-Tv~R+i~z8Cz+nS7{XUoCE?eV+dL%IB&e!?r1lZgNjYgN6sXRUGP$I-{a%2?JCp- z_`MfPF$@3zWUr0%`6`QzEaUw3a?92VKWlh)ikDs$GWUndo-c1yfPYT?g=GA-%cE-7 zsa}gaeF&jf6K@R*H*d!!+~x^o`p*5s;`9(brK(BX3|Eh7@{)KnCJ#8+M??pVjW3r-6Yh<@bW&8QI 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AckChecker_AckCheckerConcept_0_4.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_0_4.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_4_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_0_4, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:06 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_4_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_4_synth_1/runme.sh index 9690e34..24794ed 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_4_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_4_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_4_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_4_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_4_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_4_synth_1/vivado.jou index dc7b3ae..1b2633b 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_4_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_4_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:11 2020 -# Process ID: 17932 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_4_synth_1 +# Start of session at: Wed May 3 11:35:58 2023 +# Process ID: 1448 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_4_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_0_4.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_0_4.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_4_synth_1/AckChecker_AckCheckerConcept_0_4.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_4_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_4_synth_1/AckChecker_AckCheckerConcept_0_4.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_4_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_0_4.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_4_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_0_4_synth_1/vivado.pb index 21fe5f8e021da1dbd6414c8eeb9825773967971b..31d47936a0ce0ab03a374ad6872d975775f2d1ef 100644 GIT binary patch delta 183 zcmZqYSkE!RnXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@x)GbrWwo= zH(d(Aug-`)B{eOvG^fN0#xQDRf}x3(fvJ_D Og@TcRk-_9&%%%Vg^eox{ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/.vivado.begin.rst index 2605fe1..195888c 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/AckChecker_AckCheckerConcept_12_0.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/AckChecker_AckCheckerConcept_12_0.dcp index fbcc48af0b61dec0b9030ed73f232e2a18ccbb25..6de44a32ddaef2336e2eedb50e9e76fa516b6b26 100644 GIT binary patch delta 16362 zcmZv@18`+c*9IEfwmGqF+qSI}CzG656WhkbHYT?1Ol*6SNp9Zn{qA4)tGavF>ec<6 zXRYpCwNF*|T5IKAEZbKk{FV1a=AI8ExMq)rfm0gfkr zUziW54lN+Inh z9V-$+GIRZNb8|CNORd}v6ua~;zrW9Rd5$1E{w_~%8O80UB1wWH# zQ(9{G$K~!kO2|s9x)7bCs6snI?H_WmYZaem004RL?!C6z=yG-Jjm*K>zHzbE&v1 zz=K-niGH&?LkO`~BVRQu4`2HQ!p1Rm+VWsH#Two`MNZCl_Qw(A z_vg4D#$DVxFG_u@2HeAAQxqC|gIQ%gm|P=cd+se=*jR5b--S#{WfGX5Bu!m};5Ns` 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z?PX<_{dDw_@$2OFkMM?K?=$1kg7f9@3M&*s@1f|N_tWziLFpfes@-CK9G|)7@n3yegizXl^<{N5BKe@ObzcQ$&83{C zlktn9Q~(3}bSCtH>|_O_>-rxF{t}A?(#qt5xMX0cfZ28}2w9WF<>8cwi@9j@rj73u zTAqT!8J>V6-Pf=ck>8cwkhj51JWH}0)88@kQ@wkiWhP)S3_o*)5N%+8dR5}A8sGhF zl>V_LB-E>{*loVH-d3T@lNTU;SeW93iL0Zq{|#fG_}Pa!QbNj?6~DYb_o8?n1EGU#MfR zvFk+k=(VC|yiIPxVV20Q;>hQ&gk&LR2@Z~lHy@zb>!9qd7YHX9B0o{xm^M6$q2N__ zTLHiw29-6^z1Ahes6bhXX+Cg6UTjh(hG~S*MQgu=QXi&v4{Sx^nQQ#aGkv4$8iQRb z=p}Nmcpc;A;qjD;lJ8L1_@j+Tg-oMtH;|&p#I1CeQ{t| z|8iXtC`A91CeDlJF1dc0W_$_FKR&+Ne-2l$|5Zel#Dx9dHH`60k{DpgIR6e@;y}gQ zOCtQ|86b%ZRzm(S-y!**=l}au^FPo3JRAKgDE?JMmO}pb74XxQGgZC@^uL7hAC0f} z-z&5Uekqd169^&2+e`h=Oj5XDIznGOHQoQaIkow=O$J|<%;5j;TAqc!47mP}PlZ_; jgE&X@>rTIk1B08bjiL-B)IZb0fBk~Ktc%6}`S-s7n);ra diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/AckChecker_AckCheckerConcept_12_0.tcl b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/AckChecker_AckCheckerConcept_12_0.tcl index ecd5670..0b4c4ae 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/AckChecker_AckCheckerConcept_12_0.tcl +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/AckChecker_AckCheckerConcept_12_0.tcl @@ -24,15 +24,15 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] -set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] +set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] +set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/Projects/IP [current_project] +set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project] update_ip_catalog -set_property ip_output_repo d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] +set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0.xci +read_ip -quiet D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0.xci # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1 -new_name AckChecker_AckCheckerConcept_12_0 -ip [get_ips AckChecker_AckCheckerConcept_12_0]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1 -new_name AckChecker_AckCheckerConcept_12_0 -ip [get_ips AckChecker_AckCheckerConcept_12_0]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_AckCheckerConcept_12_0.dcp create_report "AckChecker_AckCheckerConcept_12_0_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_AckCheckerConcept_12_0_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_12_0_utilization_synth.pb" if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/AckChecker_AckCheckerConcept_12_0.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/AckChecker_AckCheckerConcept_12_0.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_stub.v + write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_stub.vhdl + write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_sim_netlist.v + write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,47 +120,47 @@ if { [catch { if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/AckChecker_AckCheckerConcept_12_0.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/AckChecker_AckCheckerConcept_12_0.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/AckChecker_AckCheckerConcept_12_0_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_stub.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/AckChecker_AckCheckerConcept_12_0_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/AckChecker_AckCheckerConcept_12_0_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_stub.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/AckChecker_AckCheckerConcept_12_0_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/AckChecker_AckCheckerConcept_12_0_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_sim_netlist.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/AckChecker_AckCheckerConcept_12_0_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/AckChecker_AckCheckerConcept_12_0_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_sim_netlist.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/AckChecker_AckCheckerConcept_12_0_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_12_0]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_12_0]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_12_0 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_12_0 } } -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_12_0]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_12_0]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_12_0 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_0/AckChecker_AckCheckerConcept_12_0_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_12_0 } } file delete __synthesis_is_running__ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/AckChecker_AckCheckerConcept_12_0.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/AckChecker_AckCheckerConcept_12_0.vds index 67d0f7a..8e6eec5 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/AckChecker_AckCheckerConcept_12_0.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/AckChecker_AckCheckerConcept_12_0.vds @@ -2,17 +2,17 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:29 2020 -# Process ID: 8512 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1 +# Start of session at: Wed May 3 11:36:29 2023 +# Process ID: 12540 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_12_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_12_0.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/AckChecker_AckCheckerConcept_12_0.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/AckChecker_AckCheckerConcept_12_0.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_12_0.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_12_0, cache-ID = 75535be1b50c31fe. -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:05:38 2020... +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_12_0, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:37 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/gen_run.xml index 33161e0..1dd4114 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/gen_run.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/project.wdf deleted file mode 100644 index 1c85d85..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:95469607 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/runme.log new file mode 100644 index 0000000..3db7763 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_AckCheckerConcept_12_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_12_0.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_12_0.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_12_0, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:37 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/runme.sh index d318c8b..7608a52 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/vivado.jou index f5462f0..4ad6cea 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:29 2020 -# Process ID: 8512 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1 +# Start of session at: Wed May 3 11:36:29 2023 +# Process ID: 12540 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_12_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_12_0.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/AckChecker_AckCheckerConcept_12_0.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/AckChecker_AckCheckerConcept_12_0.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_12_0.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_0_synth_1/vivado.pb index 8b193db8209ca0497569424645ecf6b206c88512..d11b20cf55a66edfd1fc5257ca4cc80d397a5b78 100644 GIT binary patch delta 187 zcmeC=*vK)#nXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@nk<{@rerr zm}W9h+;k}bzgi>ql+?7u(wq`27{jQEkt+|6>6>>lwlWG>rX`yi7$lh`TO^y9S{fw+ g?JN@UO{`Qf}x3(fvJ_T Og@TcRk-_9Y%%%Vk)GX-$ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/.vivado.begin.rst index 5a100de..08d8cfa 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/AckChecker_AckCheckerConcept_12_1.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/AckChecker_AckCheckerConcept_12_1.dcp index 262baf66668c1447829530b684b1ffc2c2e6cb79..eba930f3d4561129b73a85406fb2119417449223 100644 GIT binary patch delta 16346 zcmZv@b9AIl*F7BDwmGqF+qSKalSw+(#I`Z9jfrhL6Wg9-l3(uUe%^O|?^@s0tLjwk z-uqPj(brm4=bRo$20cy&#Zi_6hrj><0f7PW)i2V-=Dv%UzybmJahlXiNu3}B0~}BM z$Tce18yKz`ANJWFs;RC9fbeae2O!5^@MMi^n8Z66m<__&kNBRwKQBqc6eo08l|tH2 zI#witWaj$k=H_OkmRh+TD0b;xet)0s@*F{S{B1AD`FCwKhly}&ZpUUFmG0#N3VtTf zrnJ=VkIUV8%G-sa)(-LJ3bs%>KQQ*_d}d+kaNkqv$D#FWlUEsGH^esJbUJ---q#I! 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z{__kF#|9}T{g>|$|IhRPeX9AN=YO7!z7=HuDk4fC{`(5JX^I(2-vheeLjRA(cl+-Z z+W5Z}iR17D5aR44{%0l$Y!EGhZ=RCo|J|F~JewxHZ%and|934fg5L%l|Hr4oD2Yax gE&P3_-^iZM)y7(03LN5}X<@&Af#24}qW}E+UjRC!Q2+n{ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/AckChecker_AckCheckerConcept_12_1.tcl b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/AckChecker_AckCheckerConcept_12_1.tcl index ee84f75..fc4fcfa 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/AckChecker_AckCheckerConcept_12_1.tcl +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/AckChecker_AckCheckerConcept_12_1.tcl @@ -24,15 +24,15 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] -set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] +set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] +set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/Projects/IP [current_project] +set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project] update_ip_catalog -set_property ip_output_repo d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] +set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1.xci +read_ip -quiet D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1.xci # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1 -new_name AckChecker_AckCheckerConcept_12_1 -ip [get_ips AckChecker_AckCheckerConcept_12_1]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1 -new_name AckChecker_AckCheckerConcept_12_1 -ip [get_ips AckChecker_AckCheckerConcept_12_1]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_AckCheckerConcept_12_1.dcp create_report "AckChecker_AckCheckerConcept_12_1_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_AckCheckerConcept_12_1_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_12_1_utilization_synth.pb" if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/AckChecker_AckCheckerConcept_12_1.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/AckChecker_AckCheckerConcept_12_1.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_stub.v + write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_stub.vhdl + write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_sim_netlist.v + write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,47 +120,47 @@ if { [catch { if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/AckChecker_AckCheckerConcept_12_1.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/AckChecker_AckCheckerConcept_12_1.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/AckChecker_AckCheckerConcept_12_1_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_stub.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/AckChecker_AckCheckerConcept_12_1_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/AckChecker_AckCheckerConcept_12_1_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_stub.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/AckChecker_AckCheckerConcept_12_1_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/AckChecker_AckCheckerConcept_12_1_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_sim_netlist.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/AckChecker_AckCheckerConcept_12_1_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/AckChecker_AckCheckerConcept_12_1_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_sim_netlist.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/AckChecker_AckCheckerConcept_12_1_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_12_1]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_12_1]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_12_1 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_12_1 } } -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_12_1]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_12_1]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_12_1 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_1/AckChecker_AckCheckerConcept_12_1_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_12_1 } } file delete __synthesis_is_running__ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/AckChecker_AckCheckerConcept_12_1.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/AckChecker_AckCheckerConcept_12_1.vds index 8228638..2b305d5 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/AckChecker_AckCheckerConcept_12_1.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/AckChecker_AckCheckerConcept_12_1.vds @@ -2,17 +2,17 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:41 2020 -# Process ID: 11824 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1 +# Start of session at: Wed May 3 11:36:48 2023 +# Process ID: 7208 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_12_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_12_1.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/AckChecker_AckCheckerConcept_12_1.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/AckChecker_AckCheckerConcept_12_1.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_12_1.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_12_1, cache-ID = 75535be1b50c31fe. -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:05:50 2020... +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_12_1, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:56 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/gen_run.xml index 8cda4e6..e0112ed 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/gen_run.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/project.wdf deleted file mode 100644 index 1c85d85..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 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AckChecker_AckCheckerConcept_12_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_12_1.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_12_1.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_12_1, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:56 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/runme.sh index 80a27ce..7eb6ae0 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/vivado.jou index 142a676..7807a7a 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:41 2020 -# Process ID: 11824 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1 +# Start of session at: Wed May 3 11:36:48 2023 +# Process ID: 7208 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_12_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_12_1.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/AckChecker_AckCheckerConcept_12_1.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/AckChecker_AckCheckerConcept_12_1.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_12_1.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_1_synth_1/vivado.pb index 2c4e8eebb9f28c73b3a85f2c93ce568af5585af6..1216e2b54e0669bdb39e42d6d284831883cbbac6 100644 GIT binary patch delta 187 zcmeC=*vK)#nXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@nk<{@rerr zm}W9h+;k}bzgi>ql+?7u(wq`27{jQEkt+|6>6>>lwlWG>rX`yi7$lh`TO^y9S{fw+ g?JN@UO{`Qf}x3(fvJ_L Ofr62Nk-_9Y%%%Vknk?f0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/.vivado.begin.rst index 48d219e..de3ebcf 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/AckChecker_AckCheckerConcept_12_2.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/AckChecker_AckCheckerConcept_12_2.dcp index 30199ea3cd4a8606cc290f61d6ddb087fded5f9f..4bf514d6c598899f0f4c0c96b30bb3f87e69aab4 100644 GIT binary patch delta 16347 zcmZv@b9AIl*FD^^ZCexDwr$&XGD*j_ZA@%qVq;<_6Wg9-l3(uUe%^O|?^@s0tLjwk z-uqPj(brm4=bRo)0Xazl!B&z514jn{0MGzmyuN&0l z+`b;G`@;M~Wtnc4v6Y5;l}0hoaUc*YhOlLV^V*y3mUdk^sMzFegLjZQS4vU=NcKGCRg7Z$}aE4;2a&_b8qd&!hC!AE@)gPoyhbgVd5+ZyE#5y z!qF?QuT?0UU_E+W#L<2SbO=(usoYZJvn2G2-=6pN5EY!eBOKuyA=sIHuK+$*5=`e2 zI&KymZu>MTQQO^(VGL-vm#bc$o!8?6^?GOYFB`Y)pLwU-(|$$rJ&R{|OjfjMjqDVu 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zc*BeEE=5CG-)zdB70pk;z;=>FnSD7>GYSRfrC{0A(1ZyV_H4?SQc{RljgzmQM7ww> zjt;OE+}87#KI{WX-iuG;-v}GVZ!XgMC{?(t4m#DF^aDj)bT#Jfau9Jf(Ne|1F=^}P zDmy)Fs6pAs4bt#nW%PM>bf!posp)0NV8V_KOu=vW#Y>ne6AwM8Uwo-|$Qh&IZ+)Xe z7upMgl0`4JTgmSXeW&<3fi%uO;|lfw{E43a@Cz?yVZOjCAMXvOTck) zyDF=LH?OK(rAiVkyG>})*ZtmNt7(aXPCLfGXP7)nF@dq)N{`6d?Zw1T0YzCGJ|7-f z`7`#4GN51}Apft+=wFA4Uk~V)H2VG15{iElXZ%m?A)^E?m@Vc%x7FiqB~Xd}DMNgo z@L){*A`5k_P+}o z;zPHC*CA#XCqM{AUWjlDJ?cF+4aAK@qbOBP4J6I8c!gE6z?GQUn5E3g6Rl->8a`d?+vTXw{0@`nmjZ3|Gk!H z;ja!{0{{K}e37ytK|rAY$7mqFIig<||4kei+-z+WWgwycvB7`+g1)?!i2w8N{{wNL Bo>Bk+ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/AckChecker_AckCheckerConcept_12_2.tcl b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/AckChecker_AckCheckerConcept_12_2.tcl index ebc8967..1190463 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/AckChecker_AckCheckerConcept_12_2.tcl +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/AckChecker_AckCheckerConcept_12_2.tcl @@ -24,15 +24,15 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] -set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] +set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] +set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/Projects/IP [current_project] +set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project] update_ip_catalog -set_property ip_output_repo d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] +set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2.xci +read_ip -quiet D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2.xci # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1 -new_name AckChecker_AckCheckerConcept_12_2 -ip [get_ips AckChecker_AckCheckerConcept_12_2]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1 -new_name AckChecker_AckCheckerConcept_12_2 -ip [get_ips AckChecker_AckCheckerConcept_12_2]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_AckCheckerConcept_12_2.dcp create_report "AckChecker_AckCheckerConcept_12_2_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_AckCheckerConcept_12_2_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_12_2_utilization_synth.pb" if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/AckChecker_AckCheckerConcept_12_2.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/AckChecker_AckCheckerConcept_12_2.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_stub.v + write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_stub.vhdl + write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_sim_netlist.v + write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,47 +120,47 @@ if { [catch { if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/AckChecker_AckCheckerConcept_12_2.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/AckChecker_AckCheckerConcept_12_2.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/AckChecker_AckCheckerConcept_12_2_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_stub.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/AckChecker_AckCheckerConcept_12_2_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/AckChecker_AckCheckerConcept_12_2_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_stub.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/AckChecker_AckCheckerConcept_12_2_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/AckChecker_AckCheckerConcept_12_2_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_sim_netlist.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/AckChecker_AckCheckerConcept_12_2_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/AckChecker_AckCheckerConcept_12_2_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_sim_netlist.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/AckChecker_AckCheckerConcept_12_2_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_12_2]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_12_2]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_12_2 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_12_2 } } -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_12_2]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_12_2]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_12_2 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_12_2/AckChecker_AckCheckerConcept_12_2_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_12_2 } } file delete __synthesis_is_running__ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/AckChecker_AckCheckerConcept_12_2.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/AckChecker_AckCheckerConcept_12_2.vds index f86a2fa..05e0667 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/AckChecker_AckCheckerConcept_12_2.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/AckChecker_AckCheckerConcept_12_2.vds @@ -2,17 +2,17 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:41 2020 -# Process ID: 7484 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1 +# Start of session at: Wed May 3 11:36:58 2023 +# Process ID: 13720 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_12_2.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_12_2.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/AckChecker_AckCheckerConcept_12_2.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/AckChecker_AckCheckerConcept_12_2.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_12_2.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_12_2, cache-ID = 75535be1b50c31fe. -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:05:48 2020... +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_12_2, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:37:05 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/gen_run.xml index 4cf5ff9..334fab5 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/gen_run.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/project.wdf deleted file mode 100644 index 1c85d85..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:95469607 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/runme.log new file mode 100644 index 0000000..513019c --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_AckCheckerConcept_12_2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_12_2.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_12_2.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_12_2, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:37:05 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/runme.sh index e00d803..ef8fe6f 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/vivado.jou index c38945b..571c461 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:41 2020 -# Process ID: 7484 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1 +# Start of session at: Wed May 3 11:36:58 2023 +# Process ID: 13720 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_12_2.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_12_2.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/AckChecker_AckCheckerConcept_12_2.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/AckChecker_AckCheckerConcept_12_2.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_12_2.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_2_synth_1/vivado.pb index bfd55391e6f36faf89c5b8179e0f1014d9ffb0e9..37325fba57cac52f993ce0cdb7a8151cfb011c7b 100644 GIT binary patch delta 187 zcmeC=*vK)#nXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@nk<{@rerr zm}W9h+;k}bzgi>ql+?7u(wq`27{jQEkt+|6>6>>lwlWG>rX`yi7$lh`TO^y9S{fw+ g?JN@UO{`Qf}x3(fvJ^= Og@TcRk-_9Y%%%Vk-z@3? diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1/.vivado.begin.rst index 2c4db42..239d8d3 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1/AckChecker_AckCheckerConcept_12_3.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1/AckChecker_AckCheckerConcept_12_3.dcp index 2cd809770a09276d7b48f24c5a6354443d3cad5a..6568681e64d0823316deb356eadb78eb2f5fff2c 100644 GIT binary patch delta 16347 zcmZv@b9AIl*F7BDwr$(CZJQk@lXR?!ZDV2^6B`pdnb`Iull*c&_w&B%d)NA|UR9@R z_ui-KkG|HbI_LCY3g}4+D2|FeI0Oa=2nY;_pFyz}HqTvxBo+wB_tWG)O6o*m7~n+G zN1k!v-rz{>#E9?yaBWQu0EB<@JPTP=Kb8E zC+GGJ*gY2JA1cfAvrKKYG^@0V`Hq8t*fB&c6WrH69JloAs=>u(XCtT5#Q=g-{I~e{ zD~AeAAwi#oQY<4N5Y>APe=Z$= z1$a>JIx%SRU<@VpZsMk z{QeyO-K3jG_eHsX)sSaoe40XYZz#LG7n6H*e9xn`8yoBG<(sf+nQS7%5S-_geJAQlK&r@7@?v7|gV1#gI_Pql5TuC^c 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:95469607 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1/runme.log new file mode 100644 index 0000000..558f780 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_AckCheckerConcept_12_3.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_12_3.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_12_3.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_12_3, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:37:15 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1/runme.sh index 4794865..3efe5dc 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1/vivado.jou index 4ac906c..ae4dc8f 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:52 2020 -# Process ID: 13632 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1 +# Start of session at: Wed May 3 11:37:08 2023 +# Process ID: 6632 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_12_3.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_12_3.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1/AckChecker_AckCheckerConcept_12_3.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1/AckChecker_AckCheckerConcept_12_3.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_12_3.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_12_3_synth_1/vivado.pb index e4c934fd063957c6f5379d9b4a564d3ba5eab76b..7be004a78e4fd7da00519cf288b1e8a323c58aa9 100644 GIT binary patch delta 187 zcmeC=*vK)#nXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@nk<{@rerr zm}W9h+;k}bzgi>ql+?7u(wq`27{jQEkt+|6>6>>lwlWG>rX`yi7$lh`TO^y9S{fw+ g?JN@UO{`Qf}x3(fvJ_L OrGk-xk-_9Y%%%Vk^epTE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1/.vivado.begin.rst index 19e5fa5..bbf6483 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1/AckChecker_AckCheckerConcept_13_0.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1/AckChecker_AckCheckerConcept_13_0.dcp index 185e3cb7c31ec0343cd27a0699124bbe1a0d9111..5e5be071d3877d2722281cbe4a0c56b8bc58e4df 100644 GIT binary patch delta 16347 zcmZv@18`+c*9IEfwmGqF+qSI}CzG656WhkbHYT?1Ol*6SNp9Zn{qA4)tGavF>ec<6 zXRYpCwNF*|T5IKAEZbKk{FV1a=AI8ExMq)rfm0gfkr zUziW54lN+Inh z9V-$+GIRZNb8|CNORd}v6ua~;zrW9Rd5$1E{w_~%8O80UB1wWH# zQ(9{G$K~!kO2|s9x)7bCs6snI?H_WmYZaem004RL?!C6z=yG-Jjm*K>zHzbE&v1 zz=K-niGH&?LkO`~BVRQu4`2HQ!p1Rm+VWsH#Two`MNZCl_Qw(A z_vg4D#$DVxFG_u@2HeAAQxqC|gIQ%gm|P=cd+se=*jR5b--S#{WfGX5Bu!m};5Ns` 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b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1/project.wdf deleted file mode 100644 index 1c85d85..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:95469607 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1/runme.log new file mode 100644 index 0000000..33ed74c --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_AckCheckerConcept_13_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_13_0.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_13_0.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_13_0, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:48 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1/runme.sh index c1997e0..703b057 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1/vivado.jou index d63e9e2..f7d339a 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:29 2020 -# Process ID: 20324 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1 +# Start of session at: Wed May 3 11:36:40 2023 +# Process ID: 1328 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_13_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_13_0.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1/AckChecker_AckCheckerConcept_13_0.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1/AckChecker_AckCheckerConcept_13_0.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_13_0.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_0_synth_1/vivado.pb index cf389300812be80e326e52e2195073bf0fceea0c..574d12196b5827aef40252b02360d307a38f4f22 100644 GIT binary patch delta 187 zcmeC=*vK)#nXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@nk<{@rerr zm}W9h+;k}bzgi>ql+?7u(wq`27{jQEkt+|6>6>>lwlWG>rX`yi7$lh`TO^y9S{fw+ g?JN@UO{`Qf}x3(fvJ_T Og@TcRk-_9Y%%%Vk)GX-$ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/.vivado.begin.rst index ca3f2ee..6639909 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/AckChecker_AckCheckerConcept_13_1.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/AckChecker_AckCheckerConcept_13_1.dcp index b736d0ed605776a06b004a8dfc78de8ba023957a..f17b07c5813ec4c6996cebddbfdf2f71e6bcd07a 100644 GIT binary patch delta 16332 zcmZv@Wl&^Ivo(slySux)ySux)HVy-g+u-glgS*2F?(WXu?mjT^@x0G_PTUi5cSluL ztzIjue)Nv0%FG@}0X<0p#Zi$5hrj><0f7PWGbq-==DACd!~y~Newy4%Nu4MR0~}BK z$TKe78yKz~ANJiJs;#L3fbegg2O=k2@Me!|nkG0Jnh(M`jQE|sKQGC^lq7aqmq9vA zI#nitWaS0q<>h6jm07zVD0S;!etVzo_8LKU`t2aZ^>=MGmzi*DZpU^VmHy=d3VtTv zwyezlkL%re>f42q_73sp3bt^D05I<8d}d+kaNkS%`=QNivv)aR55zX$bUI^j-p?I+ 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a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/AckChecker_AckCheckerConcept_13_1.tcl b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/AckChecker_AckCheckerConcept_13_1.tcl index c9275ce..8aa6c55 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/AckChecker_AckCheckerConcept_13_1.tcl +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/AckChecker_AckCheckerConcept_13_1.tcl @@ -24,15 +24,15 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] -set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] +set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] +set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/Projects/IP [current_project] +set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project] update_ip_catalog -set_property ip_output_repo d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] +set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1.xci +read_ip -quiet D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1.xci # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1 -new_name AckChecker_AckCheckerConcept_13_1 -ip [get_ips AckChecker_AckCheckerConcept_13_1]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1 -new_name AckChecker_AckCheckerConcept_13_1 -ip [get_ips AckChecker_AckCheckerConcept_13_1]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_AckCheckerConcept_13_1.dcp create_report "AckChecker_AckCheckerConcept_13_1_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_AckCheckerConcept_13_1_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_13_1_utilization_synth.pb" if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/AckChecker_AckCheckerConcept_13_1.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/AckChecker_AckCheckerConcept_13_1.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_stub.v + write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_stub.vhdl + write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_sim_netlist.v + write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,47 +120,47 @@ if { [catch { if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/AckChecker_AckCheckerConcept_13_1.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/AckChecker_AckCheckerConcept_13_1.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/AckChecker_AckCheckerConcept_13_1_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_stub.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/AckChecker_AckCheckerConcept_13_1_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/AckChecker_AckCheckerConcept_13_1_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_stub.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/AckChecker_AckCheckerConcept_13_1_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/AckChecker_AckCheckerConcept_13_1_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_sim_netlist.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/AckChecker_AckCheckerConcept_13_1_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/AckChecker_AckCheckerConcept_13_1_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_sim_netlist.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/AckChecker_AckCheckerConcept_13_1_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_13_1]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_13_1]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_13_1 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_13_1 } } -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_13_1]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_13_1]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_13_1 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_13_1/AckChecker_AckCheckerConcept_13_1_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_13_1 } } file delete __synthesis_is_running__ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/AckChecker_AckCheckerConcept_13_1.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/AckChecker_AckCheckerConcept_13_1.vds index faeae19..b74a1f3 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/AckChecker_AckCheckerConcept_13_1.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/AckChecker_AckCheckerConcept_13_1.vds @@ -2,17 +2,17 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:41 2020 -# Process ID: 17192 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1 +# Start of session at: Wed May 3 11:36:51 2023 +# Process ID: 15936 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_13_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_13_1.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/AckChecker_AckCheckerConcept_13_1.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/AckChecker_AckCheckerConcept_13_1.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_13_1.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_13_1, cache-ID = 75535be1b50c31fe. -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:05:48 2020... +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_13_1, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:58 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/gen_run.xml index 14cb00d..8da4da9 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/gen_run.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/project.wdf deleted file mode 100644 index 1c85d85..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:95469607 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/runme.log new file mode 100644 index 0000000..2f02c7d --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_AckCheckerConcept_13_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_13_1.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_13_1.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_13_1, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:58 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/runme.sh index 64eb35e..4f057e2 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/vivado.jou index c279e0d..6182aa4 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:41 2020 -# Process ID: 17192 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1 +# Start of session at: Wed May 3 11:36:51 2023 +# Process ID: 15936 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_13_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_13_1.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/AckChecker_AckCheckerConcept_13_1.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/AckChecker_AckCheckerConcept_13_1.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_13_1.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_1_synth_1/vivado.pb index e89f0d7a419d7f513bceacfb70a84ab85b9493d9..649ccb920530990d31bbf24f0debaf6f6fb99b96 100644 GIT binary patch delta 187 zcmeC=*vK)#nXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@nk<{@rerr zm}W9h+;k}bzgi>ql+?7u(wq`27{jQEkt+|6>6>>lwlWG>rX`yi7$lh`TO^y9S{fw+ g?JN@UO{`Qf}x3(fvJ^= Og@TcRk-_9Y%%%Vk-z@3? diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1/.vivado.begin.rst index ff9aaab..f9b27e2 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1/AckChecker_AckCheckerConcept_13_2.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1/AckChecker_AckCheckerConcept_13_2.dcp index 5f451f28f2689e884ce45ceac3804204fe16eafc..b9d747622b1846d42561d784675ddf4d6c9ff80c 100644 GIT binary patch delta 16340 zcmZvD18`=|)^2Ruwr$(CZ5xxkv27a@+sVYXolIpp0e0td$j+tVoG$4h*) zQ8$`a_ zqaB|nB`Ul7G4ufq_j1*%^NV^MfZnee{j0`p`xoBn_O!W3z8CTAj>(EPt&!a#mF?%- zN>;2|nb4!|^#ynbNmET(e;EA*#55g6-Yl;`-nhr-UkG)*00h&k3Ko2R{hy2Ubf!`% z%;XbVDCTx0Q|F?Oh7&QEHU7Tg79a8hG4f#UDkby`izt|9q~bvDAr2N-a{|3F+5L}K zU$BqnKG;S@lMc4w7@b3OU_>yu(`&>f3$YM`wSOn-U(Rf$vF*eZC)5&I0xEjhvw52z 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:95469607 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1/runme.log new file mode 100644 index 0000000..bd9f585 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_AckCheckerConcept_13_2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_13_2.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_13_2.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_13_2, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:37:07 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1/runme.sh index 2e8146f..714905a 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1/vivado.jou index 64e8f73..59bbb0a 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:51 2020 -# Process ID: 22364 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1 +# Start of session at: Wed May 3 11:37:00 2023 +# Process ID: 14260 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_13_2.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_13_2.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1/AckChecker_AckCheckerConcept_13_2.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1/AckChecker_AckCheckerConcept_13_2.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_13_2.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_2_synth_1/vivado.pb index 436f66fcb9379ae205bf0865d2dbf9d8072647d1..41312adc6e5b0072330170f0a76f7a0b49d98863 100644 GIT binary patch delta 187 zcmeC=*vK)#nXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@nk<{@rerr zm}W9h+;k}bzgi>ql+?7u(wq`27{jQEkt+|6>6>>lwlWG>rX`yi7$lh`TO^y9S{fw+ g?JN@UO{`Qf}x3(fvJ_L Oxq^{_k-_9Y%%%Vk;4JC@ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1/.vivado.begin.rst index 48f79ac..f43bd2f 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1/AckChecker_AckCheckerConcept_13_3.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1/AckChecker_AckCheckerConcept_13_3.dcp index a6a2cfe6198cf9b87dd00fb3204f8655e38f7c2c..1045670b20e7a5de92975848d4542ab62d6040f5 100644 GIT binary patch delta 16332 zcmZv@b9AIl*F7BDwmGqF+qSKalSw+(#I`Z9jfrhL6Wg9-l3(uUe%^O|?^@s0tLjwk z-uqPj(brm4=bRo$20cjz#Zi_6hrj><0f7PW)i2V-=Dv%UzybmJahlXiNu3}B0~}BM z$Tce18yKz`ANJWFs;RC9fbeae2O!5^@MMi^n8Z66m<__&kNBRwKQBqc6eo08l|tH2 zI#witWaj$k=H_OkmRh+TD0b;xet)0s@*F{S{B1AD`FCwKhly}&ZpUUFmG0#N3VtTf zrnJ=VkIUV8%G-sa)(-LJ3bs%>KQQ*_d}d+kaNkqv$D#FWlUEsGH^esJbUJ---q#I! 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b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1/project.wdf deleted file mode 100644 index 1c85d85..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:95469607 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1/runme.log new file mode 100644 index 0000000..aeaabb6 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_AckCheckerConcept_13_3.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_13_3.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_13_3.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_13_3, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:37:17 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1/runme.sh index 867084e..ee53473 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1/vivado.jou index 4b22385..ca90fa3 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:52 2020 -# Process ID: 1420 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1 +# Start of session at: Wed May 3 11:37:10 2023 +# Process ID: 2152 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_13_3.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_13_3.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1/AckChecker_AckCheckerConcept_13_3.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1/AckChecker_AckCheckerConcept_13_3.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_13_3.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_13_3_synth_1/vivado.pb index aef469f6570b2d3dc2f1b16f9d2c614ca38b9906..ef673337bcaa7cdc8547047cf9a9f0e26ef1f6eb 100644 GIT binary patch delta 187 zcmeC=*vK)#nXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@nk<{@rerr zm}W9h+;k}bzgi>ql+?7u(wq`27{jQEkt+|6>6>>lwlWG>rX`yi7$lh`TO^y9S{fw+ g?JN@UO{`Qf}x3(fvJ_L OrGk-xk-_9Y%%%Vk^epTE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/.vivado.begin.rst index 5e14362..a582507 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/AckChecker_AckCheckerConcept_14_0.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/AckChecker_AckCheckerConcept_14_0.dcp index 6c786ec122de03bc1dde8639731fa733084137bc..cf1cd926bff618e6da517671beffaf5d1dc74868 100644 GIT binary patch delta 16362 zcmZv@18`+c*9IEfwmGqF+qSI}CzG656WhkbHYT?1Ol*6SNp9Zn{qA4)tGavF>ec<6 zXRYpCwNF*|T5IKAEZbKk{FV1a=AI8ExMq)rfm0gfkr zUziW54lN+Inh z9V-$+GIRZNb8|CNORd}v6ua~;zrW9Rd5$1E{w_~%8O80UB1wWH# zQ(9{G$K~!kO2|s9x)7bCs6snI?H_WmYZaem004RL?!C6z=yG-Jjm*K>zHzbE&v1 zz=K-niGH&?LkO`~BVRQu4`2HQ!p1Rm+VWsH#Two`MNZCl_Qw(A z_vg4D#$DVxFG_u@2HeAAQxqC|gIQ%gm|P=cd+se=*jR5b--S#{WfGX5Bu!m};5Ns` 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b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/AckChecker_AckCheckerConcept_14_0.tcl index 85fbaed..7701c7a 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/AckChecker_AckCheckerConcept_14_0.tcl +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/AckChecker_AckCheckerConcept_14_0.tcl @@ -24,15 +24,15 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] -set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] +set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] +set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/Projects/IP [current_project] +set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project] update_ip_catalog -set_property ip_output_repo d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] +set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0.xci +read_ip -quiet D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0.xci # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1 -new_name AckChecker_AckCheckerConcept_14_0 -ip [get_ips AckChecker_AckCheckerConcept_14_0]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1 -new_name AckChecker_AckCheckerConcept_14_0 -ip [get_ips AckChecker_AckCheckerConcept_14_0]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_AckCheckerConcept_14_0.dcp create_report "AckChecker_AckCheckerConcept_14_0_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_AckCheckerConcept_14_0_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_14_0_utilization_synth.pb" if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/AckChecker_AckCheckerConcept_14_0.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/AckChecker_AckCheckerConcept_14_0.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_stub.v + write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_stub.vhdl + write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_sim_netlist.v + write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,47 +120,47 @@ if { [catch { if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/AckChecker_AckCheckerConcept_14_0.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/AckChecker_AckCheckerConcept_14_0.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/AckChecker_AckCheckerConcept_14_0_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_stub.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/AckChecker_AckCheckerConcept_14_0_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/AckChecker_AckCheckerConcept_14_0_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_stub.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/AckChecker_AckCheckerConcept_14_0_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/AckChecker_AckCheckerConcept_14_0_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_sim_netlist.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/AckChecker_AckCheckerConcept_14_0_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/AckChecker_AckCheckerConcept_14_0_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_sim_netlist.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/AckChecker_AckCheckerConcept_14_0_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_0]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_0]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_0 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_0 } } -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_0]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_0]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_0 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_0/AckChecker_AckCheckerConcept_14_0_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_0 } } file delete __synthesis_is_running__ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/AckChecker_AckCheckerConcept_14_0.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/AckChecker_AckCheckerConcept_14_0.vds index b6d4d2d..f9e74fc 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/AckChecker_AckCheckerConcept_14_0.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/AckChecker_AckCheckerConcept_14_0.vds @@ -2,17 +2,17 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:31 2020 -# Process ID: 14604 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1 +# Start of session at: Wed May 3 11:36:40 2023 +# Process ID: 8760 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_14_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_14_0.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/AckChecker_AckCheckerConcept_14_0.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/AckChecker_AckCheckerConcept_14_0.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_14_0.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_14_0, cache-ID = 75535be1b50c31fe. -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:05:38 2020... +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_14_0, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:48 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/gen_run.xml index 45e0028..27f055e 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/gen_run.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/project.wdf deleted file mode 100644 index 1c85d85..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 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AckChecker_AckCheckerConcept_14_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_14_0.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_14_0.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_14_0, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:48 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/runme.sh index bd087d0..a3bdfb0 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/vivado.jou index d9839a0..2ca883a 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:31 2020 -# Process ID: 14604 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1 +# Start of session at: Wed May 3 11:36:40 2023 +# Process ID: 8760 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_14_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_14_0.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/AckChecker_AckCheckerConcept_14_0.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/AckChecker_AckCheckerConcept_14_0.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_14_0.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_0_synth_1/vivado.pb index b8626fde56520fd72f18c7fd02d388e67e730d04..e2141fc2fd1b30a121b2306bda2c477571216c10 100644 GIT binary patch delta 187 zcmeC=*vK)#nXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@nk<{@rerr zm}W9h+;k}bzgi>ql+?7u(wq`27{jQEkt+|6>6>>lwlWG>rX`yi7$lh`TO^y9S{fw+ g?JN@UO{`Qf}x3(fvJ_T Og@TcRk-_9Y%%%Vk)GX-$ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/.vivado.begin.rst index daf644f..02a53e4 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/AckChecker_AckCheckerConcept_14_1.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/AckChecker_AckCheckerConcept_14_1.dcp index d9f2454c803cdfb4e2b29c1d902c2bc8c67be033..1795da6073e0b6c835ac5032e2a0a84daa7c24d8 100644 GIT binary patch delta 16346 zcmZv@Wl&^Ivo(slySux)ySux)HVy-g+u-glgS*2F?(WXu?mjT^@x0G_PTUi5cSluL ztzIjue)Nv0%FG@}0X<0f7PWGbq-==DACd!~y~Newy4%Nu4MR0~}BK z$TKe78yKz~ANJiJs;#L3fbegg2O=k2@Me!|nkG0Jnh(M`jQE|sKQGC^lq7aqmq9vA zI#nitWaS0q<>h6jm07zVD0S;!etVzo_8LKU`t2aZ^>=MGmzi*DZpU^VmHy=d3VtTv zwyezlkL%re>f42q_73sp3bt^D05I<8d}d+kaNkS%`=QNivv)aR55zX$bUI^j-p?I+ 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zTy&DGmbDs}JSNt^N3F^scmqb~BTESZPrB!jGsM!f)&(%Z5#~{^A~X7X5MM%kXbGvl z_*^xXjv4a(3)MAk%7wQ?YW}<}r)Q5!&KrjGe``5zP#)Tw4QR!hU(8NdE{>}HFk*i| z$V&l(00I5~T}J;tO#E)Z-_q#&PfsB3O_ct>+Cw@qY!Dmte{QSCS&Je6$N7G9AQ=C0 zU1CTC|CA=qi{>o3d|Re}3)Md^zT1EPRxtlnL>5Pf{@*o>aSY;UAW2yN4qRbD#Mz0% z{pT4Vjtx>w`Y+!h{-5Xn`&9Ek&;L9deJjZRRYa6P{Pz`b(-bq5z6W%_h5jFn@Als- zwDEr{635{QAjH{8{Lf4h*dSU0-#jJF|GPJ}c{WXY-7<`MgRHtzW_L-ov{D_ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/AckChecker_AckCheckerConcept_14_1.tcl b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/AckChecker_AckCheckerConcept_14_1.tcl index 2117a52..547666e 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/AckChecker_AckCheckerConcept_14_1.tcl +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/AckChecker_AckCheckerConcept_14_1.tcl @@ -24,15 +24,15 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] -set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] +set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] +set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/Projects/IP [current_project] +set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project] update_ip_catalog -set_property ip_output_repo d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] +set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1.xci +read_ip -quiet D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1.xci # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1 -new_name AckChecker_AckCheckerConcept_14_1 -ip [get_ips AckChecker_AckCheckerConcept_14_1]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1 -new_name AckChecker_AckCheckerConcept_14_1 -ip [get_ips AckChecker_AckCheckerConcept_14_1]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_AckCheckerConcept_14_1.dcp create_report "AckChecker_AckCheckerConcept_14_1_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_AckCheckerConcept_14_1_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_14_1_utilization_synth.pb" if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/AckChecker_AckCheckerConcept_14_1.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/AckChecker_AckCheckerConcept_14_1.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_stub.v + write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_stub.vhdl + write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_sim_netlist.v + write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,47 +120,47 @@ if { [catch { if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/AckChecker_AckCheckerConcept_14_1.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/AckChecker_AckCheckerConcept_14_1.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/AckChecker_AckCheckerConcept_14_1_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_stub.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/AckChecker_AckCheckerConcept_14_1_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/AckChecker_AckCheckerConcept_14_1_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_stub.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/AckChecker_AckCheckerConcept_14_1_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/AckChecker_AckCheckerConcept_14_1_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_sim_netlist.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/AckChecker_AckCheckerConcept_14_1_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/AckChecker_AckCheckerConcept_14_1_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_sim_netlist.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/AckChecker_AckCheckerConcept_14_1_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_1]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_1]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_1 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_1 } } -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_1]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_1]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_1 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_1/AckChecker_AckCheckerConcept_14_1_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_1 } } file delete __synthesis_is_running__ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/AckChecker_AckCheckerConcept_14_1.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/AckChecker_AckCheckerConcept_14_1.vds index 81f1c71..3a09348 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/AckChecker_AckCheckerConcept_14_1.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/AckChecker_AckCheckerConcept_14_1.vds @@ -2,17 +2,17 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:41 2020 -# Process ID: 15984 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1 +# Start of session at: Wed May 3 11:36:51 2023 +# Process ID: 14656 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_14_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_14_1.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/AckChecker_AckCheckerConcept_14_1.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/AckChecker_AckCheckerConcept_14_1.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_14_1.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_14_1, cache-ID = 75535be1b50c31fe. -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:05:48 2020... +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_14_1, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:58 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/gen_run.xml index cf0fde9..223bdda 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/gen_run.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/project.wdf deleted file mode 100644 index 1c85d85..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:95469607 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/runme.log new file mode 100644 index 0000000..34e63d6 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_AckCheckerConcept_14_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_14_1.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_14_1.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_14_1, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:58 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/runme.sh index a7246f7..b24a129 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/vivado.jou index ccab3b3..9fa1fa2 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:41 2020 -# Process ID: 15984 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1 +# Start of session at: Wed May 3 11:36:51 2023 +# Process ID: 14656 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_14_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_14_1.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/AckChecker_AckCheckerConcept_14_1.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/AckChecker_AckCheckerConcept_14_1.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_14_1.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_1_synth_1/vivado.pb index 86aa5d3fe987d0b456fd05dc89444e2a2dcf382e..8d5cda3631b56407ab103fad91f8eb72a800e036 100644 GIT binary patch delta 187 zcmeC=*vK)#nXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@nk<{@rerr zm}W9h+;k}bzgi>ql+?7u(wq`27{jQEkt+|6>6>>lwlWG>rX`yi7$lh`TO^y9S{fw+ g?JN@UO{`Qf}x3(fvJ^= Og@TcRk-_9Y%%%Vk-z@3? diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/.vivado.begin.rst index 7427996..385c583 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/AckChecker_AckCheckerConcept_14_2.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/AckChecker_AckCheckerConcept_14_2.dcp index b29e3c0d57aecba4b410a9b3ad2851242570e9b5..eb8bac3cd24684039089e7e8287979b3afdebd2c 100644 GIT binary patch delta 16347 zcmZv@Wl&^Ivo(slySux)ySux)HVy-g+u-glgS*2F?(WXu?mjT^@x0G_PTUi5cSluL ztzIjue)Nv0%FG@}0X<0p#Zi$5hrj><0f7PWGbq-==DACd!~y~Newy4%Nu4MR0~}BK z$TKe78yKz~ANJiJs;#L3fbegg2O=k2@Me!|nkG0Jnh(M`jQE|sKQGC^lq7aqmq9vA zI#nitWaS0q<>h6jm07zVD0S;!etVzo_8LKU`t2aZ^>=MGmzi*DZpU^VmHy=d3VtTv zwyezlkL%re>f42q_73sp3bt^D05I<8d}d+kaNkS%`=QNivv)aR55zX$bUI^j-p?I+ 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ztDwpm;10Ru=L3~VDbpeRx76e+Bsfrr6>PQ*twarL#$k6!9#zrXx11JN_ukM`S)zN4qYOu7P@D?KU33gg2NY#(_INkjAxQS z2T8{M*Kmam5pOR6_n#^FO5lK$ko~Lgl=zS5|9#Z?-!u50eg*lzL?lVXf2V+#u9T_# zZP)u2hW|B%Hi2&zc;Kl-=<0bd-6=6|Myy6guXj) x^8fey^G(VI2LgipAEN>J=7@Y>{5Q6zceAlpkOqhN#|HcT3HtU{BKFU({|_Bvq?G^w diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/AckChecker_AckCheckerConcept_14_2.tcl b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/AckChecker_AckCheckerConcept_14_2.tcl index fa1658b..9587545 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/AckChecker_AckCheckerConcept_14_2.tcl +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/AckChecker_AckCheckerConcept_14_2.tcl @@ -24,15 +24,15 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] -set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] +set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] +set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/Projects/IP [current_project] +set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project] update_ip_catalog -set_property ip_output_repo d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] +set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2.xci +read_ip -quiet D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2.xci # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1 -new_name AckChecker_AckCheckerConcept_14_2 -ip [get_ips AckChecker_AckCheckerConcept_14_2]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1 -new_name AckChecker_AckCheckerConcept_14_2 -ip [get_ips AckChecker_AckCheckerConcept_14_2]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_AckCheckerConcept_14_2.dcp create_report "AckChecker_AckCheckerConcept_14_2_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_AckCheckerConcept_14_2_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_14_2_utilization_synth.pb" if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/AckChecker_AckCheckerConcept_14_2.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/AckChecker_AckCheckerConcept_14_2.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_stub.v + write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_stub.vhdl + write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_sim_netlist.v + write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,47 +120,47 @@ if { [catch { if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/AckChecker_AckCheckerConcept_14_2.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/AckChecker_AckCheckerConcept_14_2.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/AckChecker_AckCheckerConcept_14_2_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_stub.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/AckChecker_AckCheckerConcept_14_2_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/AckChecker_AckCheckerConcept_14_2_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_stub.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/AckChecker_AckCheckerConcept_14_2_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/AckChecker_AckCheckerConcept_14_2_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_sim_netlist.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/AckChecker_AckCheckerConcept_14_2_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/AckChecker_AckCheckerConcept_14_2_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_sim_netlist.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/AckChecker_AckCheckerConcept_14_2_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_2]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_2]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_2 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_2 } } -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_2]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_2]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_2 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_2/AckChecker_AckCheckerConcept_14_2_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_2 } } file delete __synthesis_is_running__ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/AckChecker_AckCheckerConcept_14_2.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/AckChecker_AckCheckerConcept_14_2.vds index 85b0a45..46f5d24 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/AckChecker_AckCheckerConcept_14_2.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/AckChecker_AckCheckerConcept_14_2.vds @@ -2,17 +2,17 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:51 2020 -# Process ID: 16168 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1 +# Start of session at: Wed May 3 11:37:00 2023 +# Process ID: 13700 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_14_2.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_14_2.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/AckChecker_AckCheckerConcept_14_2.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/AckChecker_AckCheckerConcept_14_2.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_14_2.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_14_2, cache-ID = 75535be1b50c31fe. -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:05:58 2020... +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_14_2, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:37:07 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/gen_run.xml index ef037b9..eea8319 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/gen_run.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/project.wdf deleted file mode 100644 index 1c85d85..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:95469607 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/runme.log new file mode 100644 index 0000000..aac009b --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_AckCheckerConcept_14_2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_14_2.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_14_2.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_14_2, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:37:07 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/runme.sh index a053fd5..9a29a86 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/vivado.jou index c155264..ab26372 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:51 2020 -# Process ID: 16168 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1 +# Start of session at: Wed May 3 11:37:00 2023 +# Process ID: 13700 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_14_2.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_14_2.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/AckChecker_AckCheckerConcept_14_2.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/AckChecker_AckCheckerConcept_14_2.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_14_2.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_2_synth_1/vivado.pb index bf6cc352070cd82f3faf4129a419ca9c1456a8d5..d346e65dc51b18c390f8a24ca8743ace3e2c5202 100644 GIT binary patch delta 187 zcmeC=*vK)#nXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@nk<{@rerr zm}W9h+;k}bzgi>ql+?7u(wq`27{jQEkt+|6>6>>lwlWG>rX`yi7$lh`TO^y9S{fw+ g?JN@UO{`Qf}x3(fvJ_L Og@TcRk-_9Y%%%Vk>MZL3 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/.vivado.begin.rst index 54cbe4a..66f80e0 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/AckChecker_AckCheckerConcept_14_3.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/AckChecker_AckCheckerConcept_14_3.dcp index 08d00214b272d1cf16116d4bb1594a6ab03dd4ef..48db723aee7ac2f0ca44a46ef90278561be0efef 100644 GIT binary patch delta 16347 zcmZv@b8w|i*F7BDwr$(CZQI5qC$?>4Vmq1Gwv&l%Pcq3b_j5n*Ti;vtU8lNt_d09s z?mx~|)xGyVgDJqLDZp4tvY=pSKtMoHK)!m#8kk)73E~()K+$K(edLshf>3~oq|ZFV z!u`RK+KCaLgW=km8W$kmt&0G}giG%133cNHdwtU(7`sv5^N*KhDX5afPRlZIyD5jt zB%rK3|Gd1s%(OB~w?l<)-K!rTbKRb!hz`H)1UUY#ujMl0Z_n>qZy?jYUP8dm=3AGQ z+5U09zes(*RM6Zd+*-vH%-{pW9be2YE*~9uN=6@9y)}E41G*QX{c9e6!V+}0x)9;S|&JeyxHz(H4v!K4-wX=1JoyS793N~?qlh0b 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zCB%zH%&I9~1szh)a0E|tM#+!vG`Bahhh~!I)Kbx_aT;pdn#Rn*Q&@qj;cT#((O|B81ZZQ(sm`Ba#ma+x=Bw=0v~O zHx<7qN(C^mPiI0O$WB%;x~~6`07j~#OkRpcgox%BDqy)uXDn-yxICPaa4{E+-n8+Z zLd#Q7IKvZgr287S;{Cg_8}c@oiDyZ6WBLLsKlNAdaf?|XT=nNP9ik2FPp?XxRpYy# zjiYbfK}L;w?#wW^tXbBJZZtxpE3g&Vvbv42-9z$2heKUC)98aeacqj%9Jrws9V z!hCq9|9#Z?-!u4{eg(z9L=-9Hf2V+- zuAHgzW!L`_#{V^iHo-3{5Nr6aI>{hl!1i$#|HoP3HtI@BL2^>{|}va Bs5bxr diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/AckChecker_AckCheckerConcept_14_3.tcl b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/AckChecker_AckCheckerConcept_14_3.tcl index aa73932..cedff9d 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/AckChecker_AckCheckerConcept_14_3.tcl +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/AckChecker_AckCheckerConcept_14_3.tcl @@ -24,15 +24,15 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] -set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] +set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] +set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/Projects/IP [current_project] +set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project] update_ip_catalog -set_property ip_output_repo d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] +set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3.xci +read_ip -quiet D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3.xci # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1 -new_name AckChecker_AckCheckerConcept_14_3 -ip [get_ips AckChecker_AckCheckerConcept_14_3]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1 -new_name AckChecker_AckCheckerConcept_14_3 -ip [get_ips AckChecker_AckCheckerConcept_14_3]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_AckCheckerConcept_14_3.dcp create_report "AckChecker_AckCheckerConcept_14_3_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_AckCheckerConcept_14_3_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_14_3_utilization_synth.pb" if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/AckChecker_AckCheckerConcept_14_3.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/AckChecker_AckCheckerConcept_14_3.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_stub.v + write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_stub.vhdl + write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_sim_netlist.v + write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,47 +120,47 @@ if { [catch { if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/AckChecker_AckCheckerConcept_14_3.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/AckChecker_AckCheckerConcept_14_3.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/AckChecker_AckCheckerConcept_14_3_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_stub.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/AckChecker_AckCheckerConcept_14_3_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/AckChecker_AckCheckerConcept_14_3_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_stub.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/AckChecker_AckCheckerConcept_14_3_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/AckChecker_AckCheckerConcept_14_3_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_sim_netlist.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/AckChecker_AckCheckerConcept_14_3_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/AckChecker_AckCheckerConcept_14_3_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_sim_netlist.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/AckChecker_AckCheckerConcept_14_3_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_3]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_3]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_3 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_3 } } -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_3]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_3]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_3 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_14_3/AckChecker_AckCheckerConcept_14_3_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_14_3 } } file delete __synthesis_is_running__ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/AckChecker_AckCheckerConcept_14_3.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/AckChecker_AckCheckerConcept_14_3.vds index ac4d867..55c4afd 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/AckChecker_AckCheckerConcept_14_3.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/AckChecker_AckCheckerConcept_14_3.vds @@ -2,17 +2,17 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:54 2020 -# Process ID: 15372 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1 +# Start of session at: Wed May 3 11:37:10 2023 +# Process ID: 7532 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_14_3.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_14_3.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/AckChecker_AckCheckerConcept_14_3.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/AckChecker_AckCheckerConcept_14_3.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_14_3.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_14_3, cache-ID = 75535be1b50c31fe. -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:06:00 2020... +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_14_3, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:37:17 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/gen_run.xml index 0730fee..081e5b3 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/gen_run.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/project.wdf deleted file mode 100644 index 1c85d85..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 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AckChecker_AckCheckerConcept_14_3.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_14_3.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_14_3.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_14_3, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:37:17 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/runme.sh index cb2164e..04986e1 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/vivado.jou index 38a95ce..67b16f7 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:54 2020 -# Process ID: 15372 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1 +# Start of session at: Wed May 3 11:37:10 2023 +# Process ID: 7532 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_14_3.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_14_3.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/AckChecker_AckCheckerConcept_14_3.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/AckChecker_AckCheckerConcept_14_3.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_14_3.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_14_3_synth_1/vivado.pb index b2f5e09dab67d51885a5a330787eb9ad0623ac72..54591b02c901d273be05e02a5275cbb76ef2b070 100644 GIT binary patch delta 187 zcmeC=*vK)#nXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@nk<{@rerr zm}W9h+;k}bzgi>ql+?7u(wq`27{jQEkt+|6>6>>lwlWG>rX`yi7$lh`TO^y9S{fw+ g?JN@UO{`Qf}x3(fti(o Ofr62Nk-_9Y%%%Vka4g>d diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1/.vivado.begin.rst index 11325eb..3e87acd 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1/AckChecker_AckCheckerConcept_15_0.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1/AckChecker_AckCheckerConcept_15_0.dcp index cb19f0de5e8c2ae00c05b429d4e0a764f4d59dfa..73da2c818a3b4a692c30bc0b58eed147320d2077 100644 GIT binary patch delta 16362 zcmZv@1yCi+(gujTySux)ySux)9vlV^ZiBnK4DJpyxVt-pyZgYva^HRX$G(W|j;yTu z&X-x$5q%=6GPCfyfCLyxHTLrU{OQ=7Vq!BYtP^&r32eC5fHZWsnY& zPL)X@S$P3@d3l*>W!CNoO5OUG-`;1ty+)9oeme+p{astlWhUI3+p%3orGL4Af}hE^ zEi1GC<9c_V`gWnDy+gdYf-RgO0E|02pIKNs-1n0HerWUB>|IXS1F;P_oz57X_j8Ay znAi$? z_viTUCfz)`FUozZhCIV#QxuwegW2UjF}X*^_B>jz6qO_$tJQqNtw9{!)=a@ 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:95469607 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1/runme.log new file mode 100644 index 0000000..752e3b6 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_AckCheckerConcept_15_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_15_0.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_15_0.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_15_0, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:47 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1/runme.sh index 1e4799f..aeaa0a5 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1/vivado.jou index 71e8670..4b3d82d 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:41 2020 -# Process ID: 20860 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1 +# Start of session at: Wed May 3 11:36:40 2023 +# Process ID: 7524 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_15_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_15_0.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1/AckChecker_AckCheckerConcept_15_0.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1/AckChecker_AckCheckerConcept_15_0.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_15_0.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_0_synth_1/vivado.pb index 765e956259d427f0de695d4175f150b540604bf0..95055b087bce21a5329b1e648286ea84ddbb3c51 100644 GIT binary patch delta 187 zcmeC=*vK)#nXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@nk<{@rerr zm}W9h+;k}bzgi>ql+?7u(wq`27{jQEkt+|6>6>>lwlWG>rX`yi7$lh`TO^y9S{fw+ g?JN@UO{`Qf}x3(fvJ_L Ofr62Nk-_9Y%%%Vknk?f0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/.vivado.begin.rst index e28d502..38229c3 100644 --- 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zS?H?+C;xwcKVPJ5NDvU{|1lbfZ;r^<#eZXadN&(u1!+jAe{Aqyzo0K~C1U^l`~Lu` ClB3rE diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/AckChecker_AckCheckerConcept_15_1.tcl b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/AckChecker_AckCheckerConcept_15_1.tcl index 46fc325..1ca3a95 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/AckChecker_AckCheckerConcept_15_1.tcl +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/AckChecker_AckCheckerConcept_15_1.tcl @@ -24,15 +24,15 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] -set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] +set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] +set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/Projects/IP [current_project] +set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project] update_ip_catalog -set_property ip_output_repo d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] +set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1.xci +read_ip -quiet D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1.xci # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1 -new_name AckChecker_AckCheckerConcept_15_1 -ip [get_ips AckChecker_AckCheckerConcept_15_1]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1 -new_name AckChecker_AckCheckerConcept_15_1 -ip [get_ips AckChecker_AckCheckerConcept_15_1]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_AckCheckerConcept_15_1.dcp create_report "AckChecker_AckCheckerConcept_15_1_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_AckCheckerConcept_15_1_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_15_1_utilization_synth.pb" if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/AckChecker_AckCheckerConcept_15_1.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/AckChecker_AckCheckerConcept_15_1.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_stub.v + write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_stub.vhdl + write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_sim_netlist.v + write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,47 +120,47 @@ if { [catch { if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/AckChecker_AckCheckerConcept_15_1.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/AckChecker_AckCheckerConcept_15_1.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/AckChecker_AckCheckerConcept_15_1_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_stub.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/AckChecker_AckCheckerConcept_15_1_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/AckChecker_AckCheckerConcept_15_1_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_stub.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/AckChecker_AckCheckerConcept_15_1_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/AckChecker_AckCheckerConcept_15_1_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_sim_netlist.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/AckChecker_AckCheckerConcept_15_1_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/AckChecker_AckCheckerConcept_15_1_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_sim_netlist.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/AckChecker_AckCheckerConcept_15_1_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_15_1]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_15_1]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_15_1 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_15_1 } } -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_15_1]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_15_1]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_15_1 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_1/AckChecker_AckCheckerConcept_15_1_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_15_1 } } file delete __synthesis_is_running__ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/AckChecker_AckCheckerConcept_15_1.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/AckChecker_AckCheckerConcept_15_1.vds index bc6c65a..0c92627 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/AckChecker_AckCheckerConcept_15_1.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/AckChecker_AckCheckerConcept_15_1.vds @@ -2,17 +2,17 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:41 2020 -# Process ID: 21268 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1 +# Start of session at: Wed May 3 11:36:51 2023 +# Process ID: 1492 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_15_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_15_1.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/AckChecker_AckCheckerConcept_15_1.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/AckChecker_AckCheckerConcept_15_1.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_15_1.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_15_1, cache-ID = 75535be1b50c31fe. -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:05:50 2020... +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_15_1, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:58 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/gen_run.xml index c79d4ea..13f2dc9 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/gen_run.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/project.wdf deleted file mode 100644 index 1c85d85..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:95469607 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/runme.log new file mode 100644 index 0000000..805ed0c --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_AckCheckerConcept_15_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_15_1.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_15_1.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_15_1, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:58 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/runme.sh index 71151bb..335aec2 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/vivado.jou index d26e44e..37aba78 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:41 2020 -# Process ID: 21268 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1 +# Start of session at: Wed May 3 11:36:51 2023 +# Process ID: 1492 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_15_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_15_1.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/AckChecker_AckCheckerConcept_15_1.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/AckChecker_AckCheckerConcept_15_1.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_15_1.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_1_synth_1/vivado.pb index 38598d55df32346c3e3388f465c27519db0ae33f..44b877d0dea5beb2460e03f9be9e5d3090509cc8 100644 GIT binary patch delta 187 zcmeC=*vK)#nXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@nk<{@rerr zm}W9h+;k}bzgi>ql+?7u(wq`27{jQEkt+|6>6>>lwlWG>rX`yi7$lh`TO^y9S{fw+ g?JN@UO{`Qf}x3(fvJ_L Ofr62Nk-_9Y%%%Vknk?f0 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/.vivado.begin.rst index 72a3500..bbdb1a9 100644 --- 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0294600..9d08fbf 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/AckChecker_AckCheckerConcept_15_2.tcl +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/AckChecker_AckCheckerConcept_15_2.tcl @@ -24,15 +24,15 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] -set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] +set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] +set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/Projects/IP [current_project] +set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project] update_ip_catalog -set_property ip_output_repo d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] +set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2.xci +read_ip -quiet D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2.xci # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1 -new_name AckChecker_AckCheckerConcept_15_2 -ip [get_ips AckChecker_AckCheckerConcept_15_2]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1 -new_name AckChecker_AckCheckerConcept_15_2 -ip [get_ips AckChecker_AckCheckerConcept_15_2]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_AckCheckerConcept_15_2.dcp create_report "AckChecker_AckCheckerConcept_15_2_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_AckCheckerConcept_15_2_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_15_2_utilization_synth.pb" if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/AckChecker_AckCheckerConcept_15_2.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/AckChecker_AckCheckerConcept_15_2.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_stub.v + write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_stub.vhdl + write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_sim_netlist.v + write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,47 +120,47 @@ if { [catch { if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/AckChecker_AckCheckerConcept_15_2.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/AckChecker_AckCheckerConcept_15_2.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/AckChecker_AckCheckerConcept_15_2_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_stub.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/AckChecker_AckCheckerConcept_15_2_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/AckChecker_AckCheckerConcept_15_2_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_stub.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/AckChecker_AckCheckerConcept_15_2_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/AckChecker_AckCheckerConcept_15_2_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_sim_netlist.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/AckChecker_AckCheckerConcept_15_2_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/AckChecker_AckCheckerConcept_15_2_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_sim_netlist.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/AckChecker_AckCheckerConcept_15_2_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_15_2]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_15_2]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_15_2 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_15_2 } } -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_15_2]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_15_2]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_15_2 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_2/AckChecker_AckCheckerConcept_15_2_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_15_2 } } file delete __synthesis_is_running__ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/AckChecker_AckCheckerConcept_15_2.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/AckChecker_AckCheckerConcept_15_2.vds index 9d77190..6a2f525 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/AckChecker_AckCheckerConcept_15_2.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/AckChecker_AckCheckerConcept_15_2.vds @@ -2,17 +2,17 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:51 2020 -# Process ID: 2088 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1 +# Start of session at: Wed May 3 11:37:01 2023 +# Process ID: 836 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_15_2.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_15_2.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/AckChecker_AckCheckerConcept_15_2.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/AckChecker_AckCheckerConcept_15_2.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_15_2.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_15_2, cache-ID = 75535be1b50c31fe. -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:05:58 2020... +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_15_2, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:37:08 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/gen_run.xml index d01b6f4..c35bd2d 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/gen_run.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/project.wdf deleted file mode 100644 index 1c85d85..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 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AckChecker_AckCheckerConcept_15_2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_15_2.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_15_2.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_15_2, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:37:08 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/runme.sh index 94f6683..4ea4c27 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/vivado.jou index 5aac417..a69d32b 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:51 2020 -# Process ID: 2088 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1 +# Start of session at: Wed May 3 11:37:01 2023 +# Process ID: 836 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_15_2.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_15_2.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/AckChecker_AckCheckerConcept_15_2.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/AckChecker_AckCheckerConcept_15_2.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_15_2.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_2_synth_1/vivado.pb index ff8135a35d7b24f74c166b752e2c4c364d275524..72b3a706675be59e0377c012a82f1e0fe9e40d15 100644 GIT binary patch delta 187 zcmeC=*vK)#nXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@nk<{@rerr zm}W9h+;k}bzgi>ql+?7u(wq`27{jQEkt+|6>6>>lwlWG>rX`yi7$lh`TO^y9S{fw+ g?JN@UO{`Qf}x3(fvJ_L Og@TcRk-_9Y%%%Vk>MZL3 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/.vivado.begin.rst index f810980..795e79c 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/AckChecker_AckCheckerConcept_15_3.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/AckChecker_AckCheckerConcept_15_3.dcp index 08a32a37555f3102da4c0785d6eeee22926664e4..3439ca9e444a69945c28fb9f1a3e50bbb78d0286 100644 GIT binary patch delta 16347 zcmZv@Wl&^Ivo(slySux)ySux)HVy-gySuv#?hZ4!%is=!yZgYv$MZh#IdMa974#$(6h}oK90CIb1Ox`e&!9vLo98Z35(@+*<}{^`k~&Ek1~`%Y zk#AhIH#kx^G2**FTvuBQ0O8*}4@6G9;LVxPG);6gG#`R<81*}Qe_oP-DNX9KE{AlO za;i!O$<7bR&(F_FFSm9-Q0mdY{PzB<$7>YX>9>Or*Wb0(JZ8eJxgFbeRQi_-DEQd| z+wyYzKdyJ@X>S)w+B?LXE7-!B0>JpA^Vx-^!+kI5m_wV_7ViqeUWjeL=}hL(yq`Pt z+*g8SNshXPXwRRam!G`r9IMQa%4rqwu(|>izUV2L|LeoJ%KM z0Up%5PYhZ;7(Yn$t~0Vz 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zF=F*oXA_uv7&ZnK;*X~UTIzYT}k*2wc0Q!)Vl{wu_Xnwkrg z!Jc?!pE{Q-xlhcVO!h#O9MU`R_Uw_k%{CS{!~(6Y#!GL#I_jwT#q9Lu;;71%EA<^h zK^hnY2=sA*mpCt$yX5k1&iEGU|DX1sK~}K-C89`RK>v4PV?2`t zI!H41zlJMph#D|DM73^ef2!B_c^8{yPP{bfrw? zZ@b>NF#NA6vk91v~6Z#@<5|GiI(H%H|A;=i#yy_=1-f;2e9KQ`F!U(mO=60v{&{eOfNqE7$- diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/AckChecker_AckCheckerConcept_15_3.tcl b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/AckChecker_AckCheckerConcept_15_3.tcl index e1229a0..e0088b5 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/AckChecker_AckCheckerConcept_15_3.tcl +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/AckChecker_AckCheckerConcept_15_3.tcl @@ -24,15 +24,15 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] -set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] +set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] +set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/Projects/IP [current_project] +set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project] update_ip_catalog -set_property ip_output_repo d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] +set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3.xci +read_ip -quiet D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3.xci # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1 -new_name AckChecker_AckCheckerConcept_15_3 -ip [get_ips AckChecker_AckCheckerConcept_15_3]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1 -new_name AckChecker_AckCheckerConcept_15_3 -ip [get_ips AckChecker_AckCheckerConcept_15_3]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_AckCheckerConcept_15_3.dcp create_report "AckChecker_AckCheckerConcept_15_3_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_AckCheckerConcept_15_3_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_15_3_utilization_synth.pb" if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/AckChecker_AckCheckerConcept_15_3.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/AckChecker_AckCheckerConcept_15_3.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_stub.v + write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_stub.vhdl + write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_sim_netlist.v + write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,47 +120,47 @@ if { [catch { if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/AckChecker_AckCheckerConcept_15_3.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/AckChecker_AckCheckerConcept_15_3.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/AckChecker_AckCheckerConcept_15_3_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_stub.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/AckChecker_AckCheckerConcept_15_3_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/AckChecker_AckCheckerConcept_15_3_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_stub.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/AckChecker_AckCheckerConcept_15_3_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/AckChecker_AckCheckerConcept_15_3_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_sim_netlist.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/AckChecker_AckCheckerConcept_15_3_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/AckChecker_AckCheckerConcept_15_3_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_sim_netlist.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/AckChecker_AckCheckerConcept_15_3_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_15_3]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_15_3]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_15_3 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_15_3 } } -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_15_3]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_15_3]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_15_3 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_15_3/AckChecker_AckCheckerConcept_15_3_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_15_3 } } file delete __synthesis_is_running__ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/AckChecker_AckCheckerConcept_15_3.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/AckChecker_AckCheckerConcept_15_3.vds index 28d8e88..cf5a7f3 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/AckChecker_AckCheckerConcept_15_3.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/AckChecker_AckCheckerConcept_15_3.vds @@ -2,17 +2,17 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:59 2020 -# Process ID: 14588 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1 +# Start of session at: Wed May 3 11:37:11 2023 +# Process ID: 8724 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_15_3.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_15_3.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/AckChecker_AckCheckerConcept_15_3.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/AckChecker_AckCheckerConcept_15_3.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_15_3.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_15_3, cache-ID = 75535be1b50c31fe. -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:06:06 2020... +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_15_3, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:37:18 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/gen_run.xml index 7e75ca0..9dee7df 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/gen_run.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/project.wdf deleted file mode 100644 index 1c85d85..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:95469607 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/runme.log new file mode 100644 index 0000000..a8b5ac4 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_AckCheckerConcept_15_3.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_15_3.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_15_3.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_15_3, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:37:18 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/runme.sh index 2c63404..584d07d 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/vivado.jou index 5c10066..367cac2 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:59 2020 -# Process ID: 14588 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1 +# Start of session at: Wed May 3 11:37:11 2023 +# Process ID: 8724 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_15_3.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_15_3.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/AckChecker_AckCheckerConcept_15_3.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/AckChecker_AckCheckerConcept_15_3.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_15_3.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_15_3_synth_1/vivado.pb index 9ecb36d6c78281b1ddc49e7a2665a10d054b43d1..7015cbd96fd1981f699dc767153a521787f8cbee 100644 GIT binary patch delta 187 zcmeC=*vK)#nXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@nk<{@rerr zm}W9h+;k}bzgi>ql+?7u(wq`27{jQEkt+|6>6>>lwlWG>rX`yi7$lh`TO^y9S{fw+ g?JN@UO{`Qf}x3(ff*1f N7#SEDO#Z`c3IGtSEad - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_1_0_synth_1/AckChecker_AckCheckerConcept_1_0.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_1_0_synth_1/AckChecker_AckCheckerConcept_1_0.dcp index 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b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_1_0_synth_1/project.wdf deleted file mode 100644 index 1c85d85..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_1_0_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:95469607 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_1_0_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_1_0_synth_1/runme.log new file mode 100644 index 0000000..9b8ea55 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_1_0_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_AckCheckerConcept_1_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_1_0.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_1_0.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_1_0_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_1_0, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:17 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_1_0_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_1_0_synth_1/runme.sh index 007e1f1..44d9544 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_1_0_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_1_0_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_1_0_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_1_0_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_1_0_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_1_0_synth_1/vivado.jou index 4242691..9d2a929 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_1_0_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_1_0_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:11 2020 -# Process ID: 21196 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_1_0_synth_1 +# Start of session at: Wed May 3 11:36:09 2023 +# Process ID: 3612 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_1_0_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_1_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_1_0.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_1_0_synth_1/AckChecker_AckCheckerConcept_1_0.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_1_0_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_1_0_synth_1/AckChecker_AckCheckerConcept_1_0.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_1_0_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_1_0.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_1_0_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_1_0_synth_1/vivado.pb index 5504361e6e3285fe49d3e434123cb803d2c88a47..dd741f9f4b1ab02d7441b459cdfced9cd1edeab9 100644 GIT binary patch delta 183 zcmZqYSkE!RnXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@x)GbrWwo= zH(d(Aug-`)B{eOvG^fN0#xQDRf}x3(fvJ_D Og@TcRk-_9&%%%Vg^eox{ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1/.vivado.begin.rst index 69140eb..ff9c13a 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1/AckChecker_AckCheckerConcept_2_0.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1/AckChecker_AckCheckerConcept_2_0.dcp index d9baccca0158fc5bff4d5c232375956032b29c96..b6bf09f85bd1f8d344de0ef2c2a8d0e5ee87bac4 100644 GIT binary patch delta 16378 zcmZv@18`+s6E+&#wmGqF+qSI}CzG656WhkbHYT?1Ol*6SNp9Zv`|e-=ckAw|UcL5n zp6*_ISM92`y8HAcgB~S=;wa03Ltub_fWUzG>KAEZbKk{FV1a=AI8ExMq)rfm0gfkr zUziW54lN+Inh z9V-$+GIRZNb8|CNORd}v6ua~;zrW9Rd5$1E{w_~%8O80UB1wWH# zQ(9{G$K~!kO2|s9x)7bCs6snI?H_WmYZaem004RL?!C6z=yG-Jjm*K>zHzbE&v1 zz=K-niGH&?LkO`~BVRQu4`2HQ!p1Rm+VWsH#Two`MNZCl_Qw(A z_vg4D#$DVxFG_u@2HeAAQxqC|gIQ%gm|P=cd+se=*jR5b--S#{WfGX5Bu!m};5Ns` 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:95469607 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1/runme.log new file mode 100644 index 0000000..f08366b --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_AckCheckerConcept_2_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_2_0.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_2_0.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_2_0, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:17 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1/runme.sh index b1418c7..4d79867 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1/vivado.jou index 46b160f..74456c2 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:11 2020 -# Process ID: 5216 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1 +# Start of session at: Wed May 3 11:36:09 2023 +# Process ID: 16228 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_2_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_2_0.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1/AckChecker_AckCheckerConcept_2_0.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1/AckChecker_AckCheckerConcept_2_0.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_2_0.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_2_0_synth_1/vivado.pb index 51877ccce26c5ae5a344d5537b3bb66c0a0e389d..be6ab0a1819271aba656761b58441ed0f97a08aa 100644 GIT binary patch delta 183 zcmZqYSkE!RnXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@x)GbrWwo= zH(d(Aug-`)B{eOvG^fN0#xQDRf}x3(fvJ_D Og@TcRk-_9&%%%Vg^eox{ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1/.vivado.begin.rst index cc271d1..54bd28d 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1/AckChecker_AckCheckerConcept_3_0.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1/AckChecker_AckCheckerConcept_3_0.dcp index 15801589490237f05ee0d695932c86337cf01c89..a2fba236045a12445ee2ac744a444e4f5070f585 100644 GIT binary patch delta 16346 zcmZv@1yCi+(gujTySux)ySux)9vlV^ZiBnK4DJpyxVt-pyZgYva^HRX$G(W|j;yTu z&X-x$5q%=6GPCfyfCLyxHTLrU{OQ=7Vq!BYtP^&r32eC5fHZWsnY& zPL)X@S$P3@d3l*>W!CNoO5OUG-`;1ty+)9oeme+p{astlWhUI3+p%3orGL4Af}hE^ zEi1GC<9c_V`gWnDy+gdYf-RgO0E|02pIKNs-1n0HerWUB>|IXS1F;P_oz57X_j8Ay znAi$? z_viTUCfz)`FUozZhCIV#QxuwegW2UjF}X*^_B>jz6qO_$tJQqNtw9{!)=a@ zm2mx3G}I}SPp}=iF5+sx13Cq(-c)WW3s@6*$8XR3d5R0q-4P873={6myjK99D+#Ca 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:95469607 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1/runme.log new file mode 100644 index 0000000..e94ead4 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_AckCheckerConcept_3_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_3_0.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_3_0.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_3_0, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:17 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1/runme.sh index b5d317a..49f4c7f 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1/vivado.jou index 565a5ec..725c181 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:19 2020 -# Process ID: 15552 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1 +# Start of session at: Wed May 3 11:36:09 2023 +# Process ID: 14624 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_3_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_3_0.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1/AckChecker_AckCheckerConcept_3_0.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1/AckChecker_AckCheckerConcept_3_0.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_3_0.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_3_0_synth_1/vivado.pb index 8f2de106cdf339bb710f8585b958b3a2e6a65f3d..864109cf0522728574ac20bf6d4bc088fc37876b 100644 GIT binary patch delta 183 zcmZqYSkE!RnXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@x)GbrWwo= zH(d(Aug-`)B{eOvG^fN0#xQDRf}x3(fvJ^| Oxq^{_k-_9&%%%Vg^(@)| diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1/.vivado.begin.rst index 270272a..f7efe48 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1/AckChecker_AckCheckerConcept_4_1.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1/AckChecker_AckCheckerConcept_4_1.dcp index 13d112618505a4d958344ab25ee86297b81087f3..c7721d8c9b489158e9a09bfdce06475ba77c492c 100644 GIT binary patch delta 16362 zcmZv@1yCi+(gujTyEC}EySux)I~*Ja4sL_HyA19wgS)#kxVsMwEce~Ff9#9c?#Rlj z?|hk69nmMEDl@x38T2?A6h~PO90CIb1Ox`eSHDOToBJ+a0t*D>$7xb81yzC&3~)U0 zBiE>4Z(z7)eAs7ysHVCa0K&I<9)KKw!IL$vVG{3PU^WP6KjM4#{=6g&Q=HIYRSIc8 z=~$5nl9}tDo12@FT59EXpxC8%`Tc#i%X0+T@wdGo=ijx}945l8xgDEzRJxZ7DEOH? zo6=IdKQ4FYDQ_2wT06v>E7(Hm{J_|w^O=RE!+lSwABWbjOGvM+3=}U5r7~C|1B== z%D!AfP{4bk1j`TzMDGIZ2l{8%olC`C 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:95469607 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1/runme.log new file mode 100644 index 0000000..eb5c306 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_AckCheckerConcept_4_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_4_1.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_4_1.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_4_1, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:17 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1/runme.sh index 55e40f2..801f4a5 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1/vivado.jou index c08558c..d635ece 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:19 2020 -# Process ID: 15292 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1 +# Start of session at: Wed May 3 11:36:09 2023 +# Process ID: 13052 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_4_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_4_1.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1/AckChecker_AckCheckerConcept_4_1.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1/AckChecker_AckCheckerConcept_4_1.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_4_1.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_1_synth_1/vivado.pb index 1c9c98b69d831140c3c975b58bf283731a7d986f..6090a24e0541f186ab47c57fb3f989aab1b0d80f 100644 GIT binary patch delta 183 zcmZqYSkE!RnXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@x)GbrWwo= zH(d(Aug-`)B{eOvG^fN0#xQDRf}x3(fvJ^| Oxq^{_k-_9&%%%Vg^(@)| diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/.vivado.begin.rst index bd1c24b..dcb7c82 100644 --- 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zcY!L(fP#U5{Qq4>|2jrTIk1B08bjiL-B)IZb0fBk~KtV_iI`S-s7;S8Rf diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/AckChecker_AckCheckerConcept_4_2.tcl b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/AckChecker_AckCheckerConcept_4_2.tcl index 33efc50..f610f98 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/AckChecker_AckCheckerConcept_4_2.tcl +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/AckChecker_AckCheckerConcept_4_2.tcl @@ -24,15 +24,15 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] -set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] +set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] +set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/Projects/IP [current_project] +set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project] update_ip_catalog -set_property ip_output_repo d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] +set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2.xci +read_ip -quiet D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2.xci # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1 -new_name AckChecker_AckCheckerConcept_4_2 -ip [get_ips AckChecker_AckCheckerConcept_4_2]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1 -new_name AckChecker_AckCheckerConcept_4_2 -ip [get_ips AckChecker_AckCheckerConcept_4_2]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_AckCheckerConcept_4_2.dcp create_report "AckChecker_AckCheckerConcept_4_2_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_AckCheckerConcept_4_2_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_4_2_utilization_synth.pb" if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/AckChecker_AckCheckerConcept_4_2.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/AckChecker_AckCheckerConcept_4_2.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_stub.v + write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_stub.vhdl + write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_sim_netlist.v + write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,47 +120,47 @@ if { [catch { if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/AckChecker_AckCheckerConcept_4_2.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/AckChecker_AckCheckerConcept_4_2.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/AckChecker_AckCheckerConcept_4_2_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_stub.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/AckChecker_AckCheckerConcept_4_2_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/AckChecker_AckCheckerConcept_4_2_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_stub.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/AckChecker_AckCheckerConcept_4_2_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/AckChecker_AckCheckerConcept_4_2_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_sim_netlist.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/AckChecker_AckCheckerConcept_4_2_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/AckChecker_AckCheckerConcept_4_2_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_sim_netlist.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/AckChecker_AckCheckerConcept_4_2_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_4_2]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_4_2]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_4_2 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_4_2 } } -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_4_2]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_4_2]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_4_2 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_4_2/AckChecker_AckCheckerConcept_4_2_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_4_2 } } file delete __synthesis_is_running__ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/AckChecker_AckCheckerConcept_4_2.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/AckChecker_AckCheckerConcept_4_2.vds index d899cf5..ff6b751 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/AckChecker_AckCheckerConcept_4_2.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/AckChecker_AckCheckerConcept_4_2.vds @@ -2,17 +2,17 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:21 2020 -# Process ID: 19332 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1 +# Start of session at: Wed May 3 11:36:20 2023 +# Process ID: 4300 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_4_2.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_4_2.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/AckChecker_AckCheckerConcept_4_2.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/AckChecker_AckCheckerConcept_4_2.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_4_2.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_4_2, cache-ID = 75535be1b50c31fe. -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:05:28 2020... +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_4_2, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:27 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/gen_run.xml index 30b7794..1e5df5d 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/gen_run.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/project.wdf deleted file mode 100644 index 1c85d85..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 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AckChecker_AckCheckerConcept_4_2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_4_2.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_4_2.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_4_2, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:27 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/runme.sh index 5e45afc..2618d63 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/vivado.jou index c3af7f5..efea71f 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:21 2020 -# Process ID: 19332 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1 +# Start of session at: Wed May 3 11:36:20 2023 +# Process ID: 4300 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_4_2.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_4_2.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/AckChecker_AckCheckerConcept_4_2.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/AckChecker_AckCheckerConcept_4_2.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_4_2.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_4_2_synth_1/vivado.pb index 5248fa5c90cd5274d316760eba2554a8947feca3..d49042094d6da4294a489c449266f8b55b7e9b75 100644 GIT binary patch delta 183 zcmZqYSkE!RnXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@x)GbrWwo= zH(d(Aug-`)B{eOvG^fN0#xQDRf}x3(fvJ^| Og@TcRk-_9&%%%Vg|18@8 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/.vivado.begin.rst index 9546d8f..6f1ba54 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/AckChecker_AckCheckerConcept_5_1.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/AckChecker_AckCheckerConcept_5_1.dcp index 584a238bf7f0777c199b1d020ef78ffcd6fcab5d..26a07b9decb8aa77cf7b2a2f300612be48fe71ee 100644 GIT binary patch delta 16362 zcmZv@1yCi+(gujTyE8Zp?(XjH?rsN%frGodyA19wgS)#kxVsMwEce~Ff9#9c?#Rlj z?|hk69nmMEDl@x38T2?A6h}!G90CIb1Ox`eN3Tc&o9ixK918>_>NKgBf+|4}1~{Jh zk!x76H!xf?KJ2|eR8w6I0O8#{_eYMu;LaLXH;%X0Hywnt8}T`Ne_oP;DNg9HEQPe2 zbf`!K$;|c3&CSh7Ewyw#Q0UUV{P8~9Z4+D(%Y!6#Pt{ zb!n;XALqOCl(!27%^l*+6>PzDK49$8`OL!7;l77t)S=aDlV=%WH^esJbUJ---p3Vs zVs2lL)oo$^p`uhb)7VNwy;7ry=Qsd}9Zl3c&Ux*{c1ydi99U#>Hhd~s1RzMke~XK| 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ztlf*UzPTrL$aUc)9KV%%miMIflCoPJo`Nu$dqdL@Xxc#mOMQ&KplRlTCDrMQ6DQY*)aF6{a^5BVF`SZ; z^8Jz#(}uf(nhPqs7`$gBDP<4h;B|mU4S`5Bqa=$q27>k`{z7;`&mjC~us5|87bw4z z(aJtGIe2{E;H6aB=%^0D>;7ofn*54$cn9g|Zol;YU0#w)xxfX#@{}DvpnYs)pF=?! z7z7CD|L-pP_gUh11OApq-+y|7#_{iB^#9c!(u?DO*kJr~TRq-d9Qi-a_nQO3{Fmzz zMEG;v-mcgf}3G~-*S|MBtN{&Tp3^{*nb1P1i~u3?O4lt2eb#{PHU3L7HcP6F;f z&j1M=kP@b_WKw3ZCxz(&%gf#Wx}Q; diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/AckChecker_AckCheckerConcept_5_1.tcl b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/AckChecker_AckCheckerConcept_5_1.tcl index e16b5bc..dfcb755 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/AckChecker_AckCheckerConcept_5_1.tcl +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/AckChecker_AckCheckerConcept_5_1.tcl @@ -24,15 +24,15 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] -set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] +set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] +set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/Projects/IP [current_project] +set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project] update_ip_catalog -set_property ip_output_repo d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] +set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1.xci +read_ip -quiet D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1.xci # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1 -new_name AckChecker_AckCheckerConcept_5_1 -ip [get_ips AckChecker_AckCheckerConcept_5_1]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1 -new_name AckChecker_AckCheckerConcept_5_1 -ip [get_ips AckChecker_AckCheckerConcept_5_1]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_AckCheckerConcept_5_1.dcp create_report "AckChecker_AckCheckerConcept_5_1_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_AckCheckerConcept_5_1_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_5_1_utilization_synth.pb" if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/AckChecker_AckCheckerConcept_5_1.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/AckChecker_AckCheckerConcept_5_1.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_stub.v + write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_stub.vhdl + write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_sim_netlist.v + write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,47 +120,47 @@ if { [catch { if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/AckChecker_AckCheckerConcept_5_1.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/AckChecker_AckCheckerConcept_5_1.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/AckChecker_AckCheckerConcept_5_1_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_stub.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/AckChecker_AckCheckerConcept_5_1_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/AckChecker_AckCheckerConcept_5_1_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_stub.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/AckChecker_AckCheckerConcept_5_1_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/AckChecker_AckCheckerConcept_5_1_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_sim_netlist.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/AckChecker_AckCheckerConcept_5_1_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/AckChecker_AckCheckerConcept_5_1_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_sim_netlist.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/AckChecker_AckCheckerConcept_5_1_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_5_1]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_5_1]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_5_1 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_5_1 } } -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_5_1]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_5_1]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_5_1 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_5_1/AckChecker_AckCheckerConcept_5_1_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_5_1 } } file delete __synthesis_is_running__ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/AckChecker_AckCheckerConcept_5_1.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/AckChecker_AckCheckerConcept_5_1.vds index a6fb935..c1045d0 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/AckChecker_AckCheckerConcept_5_1.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/AckChecker_AckCheckerConcept_5_1.vds @@ -2,17 +2,17 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:19 2020 -# Process ID: 7912 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1 +# Start of session at: Wed May 3 11:36:20 2023 +# Process ID: 7552 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_5_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_5_1.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/AckChecker_AckCheckerConcept_5_1.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/AckChecker_AckCheckerConcept_5_1.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_5_1.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_5_1, cache-ID = 75535be1b50c31fe. -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:05:27 2020... +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_5_1, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:27 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/gen_run.xml index 8637741..950427c 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/gen_run.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/project.wdf deleted file mode 100644 index 1c85d85..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:95469607 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/runme.log new file mode 100644 index 0000000..537de70 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_AckCheckerConcept_5_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_5_1.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_5_1.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_5_1, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:27 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/runme.sh index 181a6fe..82d24b8 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/vivado.jou index 9d5da5e..8149331 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:19 2020 -# Process ID: 7912 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1 +# Start of session at: Wed May 3 11:36:20 2023 +# Process ID: 7552 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_5_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_5_1.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/AckChecker_AckCheckerConcept_5_1.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/AckChecker_AckCheckerConcept_5_1.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_5_1.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_1_synth_1/vivado.pb index 3579c70ef6cda90217a942a4ba0e273b58339abc..1e92a629101584cafba27b9937a09b89172df678 100644 GIT binary patch delta 183 zcmZqYSkE!RnXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@x)GbrWwo= zH(d(Aug-`)B{eOvG^fN0#xQDRf}x3(fvJ^| Oxq^{_k-_9&%%%Vg^(@)| diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1/.vivado.begin.rst index 332805e..360653e 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1/AckChecker_AckCheckerConcept_5_2.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1/AckChecker_AckCheckerConcept_5_2.dcp index edc69e8667f4e4235b39f24aeabad7df14884b1b..b9c6075ebde42c1c4bcef88280f333e67c64366a 100644 GIT binary patch delta 16346 zcmZv@b8w|i*F7BDwr$(CZQI5qC$?>4Vmq1Gwv&l%Pcq3b_j5n*Ti;vtU8lNt_d09s z?mx~|)xGyVgDJo#DZp4tvY=pSKtMoHK)!m#8kk)73E~()K+$K(edLshf>3~oq|ZFV z!u`RK+KCaLgW=km8W$kmt&0G}giG%133cNHdwtU(7`sv5^N*KhDX5afPRlZIyD5jt zB%rK3|Gd1s%(OB~w?l<)-K!rTbKRb!hz`H)1UUY#ujMl0Z_n>qZy?jYUP8dm=3AGQ z+5U09zes(*RM6Zd+*-vH%-{pW9be2YE*~9uN=6@9y)}E41G*QX{c9e6!V+}0x)9;S|&JeyxHz(H4v!K4-wX=1JoyS793N~?qlh0b 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:95469607 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1/runme.log new file mode 100644 index 0000000..2224068 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_AckCheckerConcept_5_2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_5_2.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_5_2.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_5_2, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:37 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1/runme.sh index 9e91d8b..837c345 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1/vivado.jou index 31983a3..dd3b153 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:29 2020 -# Process ID: 11940 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1 +# Start of session at: Wed May 3 11:36:29 2023 +# Process ID: 10912 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_5_2.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_5_2.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1/AckChecker_AckCheckerConcept_5_2.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1/AckChecker_AckCheckerConcept_5_2.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_5_2.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_5_2_synth_1/vivado.pb index 47c91b01153800f3c6d6531de1be65898e6e8111..7d169bd60c9b9146e0404be94630e6e2a87c1bb6 100644 GIT binary patch delta 183 zcmZqYSkE!RnXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@x)GbrWwo= zH(d(Aug-`)B{eOvG^fN0#xQDRf}x3(fvJ_T Og@TcRk-_9&%%%Vh3M||J diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/.vivado.begin.rst index 0cbecbe..6b8e2c5 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/AckChecker_AckCheckerConcept_6_1.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/AckChecker_AckCheckerConcept_6_1.dcp index 91321be4b75c67c1e52db6c24659ac16bcc115e4..6ebb201f8bfc2e2df75d15a842641d345a452e42 100644 GIT binary patch delta 16347 zcmZv@18{E5(gqsaJGO1xwr$(aPTttIjUC&zZSUCjPIhwho$uVg?y0(KRZq`6@6$cA zs@7XI)7@(z8Tcd_7*kOO6buyz2nY(uN4H2FgY!OK3>^q4>MW^`j3Pk*3NVrQnQKt6 zKR8k|G2(qNTvJ``48*f_;g1-9$(1#sW)yFyXEFq1JL+@(@vmAL8Qects`N)|>kuz=z&U;+kwQac? zKcClP3A#Q2fb6-EHeYGJk!h5-US`o!?rR0lM*h;HOzQSf(f#H11K^ikcOemX?fj_H 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a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/AckChecker_AckCheckerConcept_6_1.tcl +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/AckChecker_AckCheckerConcept_6_1.tcl @@ -24,15 +24,15 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] -set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] +set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] +set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/Projects/IP [current_project] +set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project] update_ip_catalog -set_property ip_output_repo d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] +set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1.xci +read_ip -quiet D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1.xci # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1 -new_name AckChecker_AckCheckerConcept_6_1 -ip [get_ips AckChecker_AckCheckerConcept_6_1]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1 -new_name AckChecker_AckCheckerConcept_6_1 -ip [get_ips AckChecker_AckCheckerConcept_6_1]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_AckCheckerConcept_6_1.dcp create_report "AckChecker_AckCheckerConcept_6_1_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_AckCheckerConcept_6_1_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_6_1_utilization_synth.pb" if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/AckChecker_AckCheckerConcept_6_1.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/AckChecker_AckCheckerConcept_6_1.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_stub.v + write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_stub.vhdl + write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_sim_netlist.v + write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,47 +120,47 @@ if { [catch { if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/AckChecker_AckCheckerConcept_6_1.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/AckChecker_AckCheckerConcept_6_1.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/AckChecker_AckCheckerConcept_6_1_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_stub.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/AckChecker_AckCheckerConcept_6_1_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/AckChecker_AckCheckerConcept_6_1_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_stub.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/AckChecker_AckCheckerConcept_6_1_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/AckChecker_AckCheckerConcept_6_1_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_sim_netlist.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/AckChecker_AckCheckerConcept_6_1_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/AckChecker_AckCheckerConcept_6_1_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_sim_netlist.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/AckChecker_AckCheckerConcept_6_1_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_6_1]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_6_1]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_6_1 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_6_1 } } -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_6_1]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_6_1]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_6_1 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_1/AckChecker_AckCheckerConcept_6_1_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_6_1 } } file delete __synthesis_is_running__ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/AckChecker_AckCheckerConcept_6_1.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/AckChecker_AckCheckerConcept_6_1.vds index 4eca648..6b76a28 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/AckChecker_AckCheckerConcept_6_1.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/AckChecker_AckCheckerConcept_6_1.vds @@ -2,17 +2,17 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:19 2020 -# Process ID: 17496 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1 +# Start of session at: Wed May 3 11:36:20 2023 +# Process ID: 10488 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_6_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_6_1.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/AckChecker_AckCheckerConcept_6_1.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/AckChecker_AckCheckerConcept_6_1.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_6_1.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_6_1, cache-ID = 75535be1b50c31fe. -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:05:27 2020... +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_6_1, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:27 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/gen_run.xml index 617dc47..1124a4e 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/gen_run.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/project.wdf deleted file mode 100644 index 1c85d85..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:95469607 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/runme.log new file mode 100644 index 0000000..d5292c8 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_AckCheckerConcept_6_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_6_1.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_6_1.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_6_1, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:27 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/runme.sh index 24ab445..b0f7d61 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/vivado.jou index 7849844..e4c0d30 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:19 2020 -# Process ID: 17496 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1 +# Start of session at: Wed May 3 11:36:20 2023 +# Process ID: 10488 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_6_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_6_1.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/AckChecker_AckCheckerConcept_6_1.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/AckChecker_AckCheckerConcept_6_1.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_6_1.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_1_synth_1/vivado.pb index ebe899f43a5e2453614e1a35dda0a39db21d555d..bcf7a4196a068a7d6a4a0f779caf689b9958eb0c 100644 GIT binary patch delta 183 zcmZqYSkE!RnXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@x)GbrWwo= zH(d(Aug-`)B{eOvG^fN0#xQDRf}x3(fvJ^| Oxq^{_k-_9&%%%Vg^(@)| diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/.vivado.begin.rst index 730f41e..8538a49 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/AckChecker_AckCheckerConcept_6_2.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/AckChecker_AckCheckerConcept_6_2.dcp index c5dfab83b8d27fb252b0baf8c0a577c1e1448d61..ce074f6c050ec44dfede3f2696be4fa2d83e90f1 100644 GIT binary patch delta 16331 zcmZv@Wl&^Ivo(slySonV?(XjHZjHl0<2Jav%i!)XxVt+H?(PEvAJ6-|=fph`cXw1} z)#|mf>PPR0s?6+xWYFVeP#k4Ba0m<#5D*v;U;QFYZ0@^w2`mthAE!yZl++1AFu?J| zk6fdIy@BDH@nN6+p_=My00`gac>r?!1y9zvhDp4Gf!QFO{fO_``}2}COmRYoRVk$X zq+>-QNM^2oZfQR!YTpx|fn zY)VV*{_cD5-dX?5Y=lvZLZRCJ<}v_t<0*W+|LG)gX;O0Duw%fMfaySI?zA6?p!MF z3hpb7?G3@`FQL%Dm!I$t7CyMfg%gf;;aDAm^bjO)_*1K-#q%*x12uog>z+^TWN_`pmB!T*SOdy? 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b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/AckChecker_AckCheckerConcept_6_2.tcl index b63d106..34e7f89 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/AckChecker_AckCheckerConcept_6_2.tcl +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/AckChecker_AckCheckerConcept_6_2.tcl @@ -24,15 +24,15 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] -set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] +set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] +set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/Projects/IP [current_project] +set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project] update_ip_catalog -set_property ip_output_repo d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] +set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2.xci +read_ip -quiet D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2.xci # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1 -new_name AckChecker_AckCheckerConcept_6_2 -ip [get_ips AckChecker_AckCheckerConcept_6_2]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1 -new_name AckChecker_AckCheckerConcept_6_2 -ip [get_ips AckChecker_AckCheckerConcept_6_2]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_AckCheckerConcept_6_2.dcp create_report "AckChecker_AckCheckerConcept_6_2_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_AckCheckerConcept_6_2_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_6_2_utilization_synth.pb" if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/AckChecker_AckCheckerConcept_6_2.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/AckChecker_AckCheckerConcept_6_2.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_stub.v + write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_stub.vhdl + write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_sim_netlist.v + write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,47 +120,47 @@ if { [catch { if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/AckChecker_AckCheckerConcept_6_2.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/AckChecker_AckCheckerConcept_6_2.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/AckChecker_AckCheckerConcept_6_2_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_stub.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/AckChecker_AckCheckerConcept_6_2_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/AckChecker_AckCheckerConcept_6_2_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_stub.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/AckChecker_AckCheckerConcept_6_2_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/AckChecker_AckCheckerConcept_6_2_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_sim_netlist.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/AckChecker_AckCheckerConcept_6_2_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/AckChecker_AckCheckerConcept_6_2_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_sim_netlist.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/AckChecker_AckCheckerConcept_6_2_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_6_2]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_6_2]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_6_2 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_6_2 } } -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_6_2]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_6_2]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_6_2 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_6_2/AckChecker_AckCheckerConcept_6_2_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_6_2 } } file delete __synthesis_is_running__ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/AckChecker_AckCheckerConcept_6_2.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/AckChecker_AckCheckerConcept_6_2.vds index 07012da..ab9e76a 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/AckChecker_AckCheckerConcept_6_2.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/AckChecker_AckCheckerConcept_6_2.vds @@ -2,17 +2,17 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:29 2020 -# Process ID: 2040 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1 +# Start of session at: Wed May 3 11:36:29 2023 +# Process ID: 14416 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_6_2.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_6_2.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/AckChecker_AckCheckerConcept_6_2.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/AckChecker_AckCheckerConcept_6_2.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_6_2.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_6_2, cache-ID = 75535be1b50c31fe. -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:05:38 2020... +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_6_2, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:37 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/gen_run.xml index c4a50db..17c0277 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/gen_run.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/project.wdf deleted file mode 100644 index 1c85d85..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:95469607 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/runme.log new file mode 100644 index 0000000..8af393f --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_AckCheckerConcept_6_2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_6_2.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_6_2.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_6_2, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:37 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/runme.sh index 18d4654..36903bc 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/vivado.jou index e506e1f..c5fad22 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:29 2020 -# Process ID: 2040 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1 +# Start of session at: Wed May 3 11:36:29 2023 +# Process ID: 14416 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_6_2.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_6_2.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/AckChecker_AckCheckerConcept_6_2.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/AckChecker_AckCheckerConcept_6_2.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_6_2.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_6_2_synth_1/vivado.pb index 7553e38304f18a68c5974feff9bf1a3cbd604da6..4fc622bdc10059a3890c23ab6d412bab8ef38be0 100644 GIT binary patch delta 183 zcmZqYSkE!RnXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@x)GbrWwo= zH(d(Aug-`)B{eOvG^fN0#xQDRf}x3(fvJ_T Og@TcRk-_9&%%%Vh3M||J diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/.vivado.begin.rst index e31b198..07ce99b 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/AckChecker_AckCheckerConcept_7_1.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/AckChecker_AckCheckerConcept_7_1.dcp index 76c30e79a676e8cb128fc2475631bca120d45c43..1de3b06ce21233b1f4087b549f90b1ce18b98884 100644 GIT binary patch delta 16362 zcmZv@18`+c*9IEf6Wg|J+qR7pCzG6D!ijBTV%xUuiEU3Z$<6z{-~H=;Rd?@Ny}F>Z&RL2;b&;0CL;~Pv*FWNt}a$*&v+#i0|3^^O7`7QGB~q38ej` zV|fBdMvi|@PELACiIv-dVyE8a_xIUO&kf7e#CnFzM#c5K#B>0U0N;Ae7e zN=oehxZIs5zg;M5?GSCQU3Y(0Q_XUx7gS# z`!Wqd0q=!kOhX_L)oVR(l!i&_Ap8Tq^bo z@SxUlqTl4s@Po*!fv<{{hp+7dVdI!8b^GpqVM@l=dA`kK*#9@9Vl{8BA}8lN`{M}m z`*ZA1<4$g!7p1;c1McCmDRPay!OYTb46c!}J@@8LEX=o;??NUeGV#n$lBO;~aGPUe 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ilH`be-RU=VWOTQ)Rg#5-`e$1BuV3(&b+N=h|Na+^8ly7+ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/AckChecker_AckCheckerConcept_7_1.tcl b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/AckChecker_AckCheckerConcept_7_1.tcl index c15f61e..b8e4b95 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/AckChecker_AckCheckerConcept_7_1.tcl +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/AckChecker_AckCheckerConcept_7_1.tcl @@ -24,15 +24,15 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] -set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] +set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] +set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/Projects/IP [current_project] +set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project] update_ip_catalog -set_property ip_output_repo d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] +set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1.xci +read_ip -quiet D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1.xci # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1 -new_name AckChecker_AckCheckerConcept_7_1 -ip [get_ips AckChecker_AckCheckerConcept_7_1]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1 -new_name AckChecker_AckCheckerConcept_7_1 -ip [get_ips AckChecker_AckCheckerConcept_7_1]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_AckCheckerConcept_7_1.dcp create_report "AckChecker_AckCheckerConcept_7_1_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_AckCheckerConcept_7_1_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_7_1_utilization_synth.pb" if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/AckChecker_AckCheckerConcept_7_1.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/AckChecker_AckCheckerConcept_7_1.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_stub.v + write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_stub.vhdl + write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_sim_netlist.v + write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,47 +120,47 @@ if { [catch { if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/AckChecker_AckCheckerConcept_7_1.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/AckChecker_AckCheckerConcept_7_1.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/AckChecker_AckCheckerConcept_7_1_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_stub.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/AckChecker_AckCheckerConcept_7_1_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/AckChecker_AckCheckerConcept_7_1_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_stub.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/AckChecker_AckCheckerConcept_7_1_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/AckChecker_AckCheckerConcept_7_1_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_sim_netlist.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/AckChecker_AckCheckerConcept_7_1_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/AckChecker_AckCheckerConcept_7_1_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_sim_netlist.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/AckChecker_AckCheckerConcept_7_1_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_7_1]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_7_1]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_7_1 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_7_1 } } -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_7_1]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_7_1]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_7_1 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_1/AckChecker_AckCheckerConcept_7_1_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_7_1 } } file delete __synthesis_is_running__ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/AckChecker_AckCheckerConcept_7_1.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/AckChecker_AckCheckerConcept_7_1.vds index b26b66c..aa0382e 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/AckChecker_AckCheckerConcept_7_1.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/AckChecker_AckCheckerConcept_7_1.vds @@ -2,17 +2,17 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:19 2020 -# Process ID: 23500 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1 +# Start of session at: Wed May 3 11:36:20 2023 +# Process ID: 9316 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_7_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_7_1.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/AckChecker_AckCheckerConcept_7_1.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/AckChecker_AckCheckerConcept_7_1.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_7_1.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_7_1, cache-ID = 75535be1b50c31fe. -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:05:27 2020... +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_7_1, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:27 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/gen_run.xml index d87a56f..2999bf5 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/gen_run.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/project.wdf deleted file mode 100644 index 1c85d85..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:95469607 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/runme.log new file mode 100644 index 0000000..56286e6 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_AckCheckerConcept_7_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_7_1.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_7_1.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_7_1, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:27 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/runme.sh index 079dc94..f3aabb1 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/vivado.jou index e49600b..7e3313f 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:19 2020 -# Process ID: 23500 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1 +# Start of session at: Wed May 3 11:36:20 2023 +# Process ID: 9316 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_7_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_7_1.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/AckChecker_AckCheckerConcept_7_1.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/AckChecker_AckCheckerConcept_7_1.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_7_1.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_1_synth_1/vivado.pb index f2e6778db95868564e079b4fa71ee0348fc3f29c..a181e4ecc8c81f3ff67679e61421613d6e34f5a2 100644 GIT binary patch delta 183 zcmZqYSkE!RnXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@x)GbrWwo= zH(d(Aug-`)B{eOvG^fN0#xQDRf}x3(fvJ^| Oxq^{_k-_9&%%%Vg^(@)| diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/.vivado.begin.rst index 67b6f9f..144c189 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/AckChecker_AckCheckerConcept_7_2.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/AckChecker_AckCheckerConcept_7_2.dcp index e7dd167bc5d3adc2d89bfb22890ef56c783d7d98..4358249a98350d6c5fffc444c639066056f946af 100644 GIT binary patch delta 16346 zcmZv@b8w|i*F7BDwr$(CZQI5qC$?>4Vmq1Gwv&l%Pcq3b_j5n*Ti;vtU8lNt_d09s z?mx~|)xGyVgDJo#DZp4tvY=pSKtMoHK)!m#8kk)73E~()K+$K(edLshf>3~oq|ZFV z!u`RK+KCaLgW=km8W$kmt&0G}giG%133cNHdwtU(7`sv5^N*KhDX5afPRlZIyD5jt zB%rK3|Gd1s%(OB~w?l<)-K!rTbKRb!hz`H)1UUY#ujMl0Z_n>qZy?jYUP8dm=3AGQ z+5U09zes(*RM6Zd+*-vH%-{pW9be2YE*~9uN=6@9y)}E41G*QX{c9e6!V+}0x)9;S|&JeyxHz(H4v!K4-wX=1JoyS793N~?qlh0b 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z&?fM$ND_xHh!AHd`9CvB;(%xie)Ckc|L@+^=Gipqe_Jwv{=aK^5&AaZ{69VwCMk5H hY?1Ff{l@n6t~S;R(%=yPObh${3;eb&7W?Pl{{mtxnP&h1 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/AckChecker_AckCheckerConcept_7_2.tcl b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/AckChecker_AckCheckerConcept_7_2.tcl index b7150f0..dabc6f1 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/AckChecker_AckCheckerConcept_7_2.tcl +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/AckChecker_AckCheckerConcept_7_2.tcl @@ -24,15 +24,15 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] -set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] +set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] +set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/Projects/IP [current_project] +set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project] update_ip_catalog -set_property ip_output_repo d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] +set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2.xci +read_ip -quiet D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2.xci # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1 -new_name AckChecker_AckCheckerConcept_7_2 -ip [get_ips AckChecker_AckCheckerConcept_7_2]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1 -new_name AckChecker_AckCheckerConcept_7_2 -ip [get_ips AckChecker_AckCheckerConcept_7_2]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_AckCheckerConcept_7_2.dcp create_report "AckChecker_AckCheckerConcept_7_2_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_AckCheckerConcept_7_2_utilization_synth.rpt -pb AckChecker_AckCheckerConcept_7_2_utilization_synth.pb" if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/AckChecker_AckCheckerConcept_7_2.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/AckChecker_AckCheckerConcept_7_2.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_stub.v + write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_stub.vhdl + write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_sim_netlist.v + write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,47 +120,47 @@ if { [catch { if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/AckChecker_AckCheckerConcept_7_2.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/AckChecker_AckCheckerConcept_7_2.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/AckChecker_AckCheckerConcept_7_2_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_stub.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/AckChecker_AckCheckerConcept_7_2_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/AckChecker_AckCheckerConcept_7_2_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_stub.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/AckChecker_AckCheckerConcept_7_2_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/AckChecker_AckCheckerConcept_7_2_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_sim_netlist.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/AckChecker_AckCheckerConcept_7_2_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/AckChecker_AckCheckerConcept_7_2_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_sim_netlist.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/AckChecker_AckCheckerConcept_7_2_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_7_2]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_7_2]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_7_2 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_7_2 } } -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_7_2]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_7_2]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_7_2 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_AckCheckerConcept_7_2/AckChecker_AckCheckerConcept_7_2_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_AckCheckerConcept_7_2 } } file delete __synthesis_is_running__ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/AckChecker_AckCheckerConcept_7_2.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/AckChecker_AckCheckerConcept_7_2.vds index 1cb29e8..6805a50 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/AckChecker_AckCheckerConcept_7_2.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/AckChecker_AckCheckerConcept_7_2.vds @@ -2,17 +2,17 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:29 2020 -# Process ID: 5524 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1 +# Start of session at: Wed May 3 11:36:29 2023 +# Process ID: 13568 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_7_2.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_7_2.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/AckChecker_AckCheckerConcept_7_2.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/AckChecker_AckCheckerConcept_7_2.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_7_2.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_7_2, cache-ID = 75535be1b50c31fe. -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:05:37 2020... +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_7_2, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:37 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/gen_run.xml index 35e8643..3e77c81 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/gen_run.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/project.wdf deleted file mode 100644 index 1c85d85..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 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AckChecker_AckCheckerConcept_7_2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_7_2.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_AckCheckerConcept_7_2.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_AckCheckerConcept_7_2, cache-ID = 9fc500b6c8c4592a. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:36:37 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/runme.sh index d02fa54..ce94967 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/vivado.jou index 7800391..3c8a6f2 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:05:29 2020 -# Process ID: 5524 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1 +# Start of session at: Wed May 3 11:36:29 2023 +# Process ID: 13568 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1 # Command line: vivado.exe -log AckChecker_AckCheckerConcept_7_2.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_AckCheckerConcept_7_2.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/AckChecker_AckCheckerConcept_7_2.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/AckChecker_AckCheckerConcept_7_2.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_AckCheckerConcept_7_2.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_AckCheckerConcept_7_2_synth_1/vivado.pb index 50652abee0addd2ee2998d5f5ef198ec9cde8627..7bdc94926029200dcaec608df26cf00c5f07cdbc 100644 GIT binary patch delta 183 zcmZqYSkE!RnXzo5i;0{*mvoAizPo3LtE0YqW{F2>lD=!OzGpyua(+>2@x)GbrWwo= zH(d(Aug-`)B{eOvG^fN0#xQDRf}x3(fvJ_T Oxq^{_k-_9&%%%Vh04&=8 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1/.vivado.begin.rst index 2cae715..6819bf6 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1/AckChecker_BusBlock16IN_0_0.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1/AckChecker_BusBlock16IN_0_0.dcp index 8f64ac9bc9391de5f218c187279e3d561cf37e05..db73a600bad5c528cc31e78372fb5938f6f21d95 100644 GIT binary patch delta 3255 zcmZ8j2{e>#8y>>g*CCB%WZyFxJ6R`tG&Dlf$d)xDyJSczMPV?;zDHC@Mxl{43XRX6 zAxrkPPqKu6=sSP^_uuEd=Y8J$x$f(}-t(MuJ@>lo139d<`3X7@003YF+`3YTluCO6wv_yKx)?21)~`1>yw&-^2=1>k9~U zVuzEW<5!2yu-$m-nK4UwH@B_P5h>BTx@X9C!B*8`{mnJP=Q?z}`#6ilUZGP1eI`e@ zYEyXGh8N3uim&&LVwOGt6a#NB<+3L z@!L}85ajc{qJ!BnO*^%ioVdbdyesyNSnBW!7)#`H^|QRgXvhkbbGEE1U#RwmbJn9S zW#{T=zh*EVd+q;?X}s@1$5!S&luvwN`@}a}J_Q9V9zwQ3)ubi@RqT@FkT!{p!o4_! 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zet+jx?}3G+9^nRukJ>{=c!B=5J;a|HKuS*%WVO*P?>t8Blw~Ile6+PM+SwGMPE|%# zT~C2)c9MrJ2euokx(ai71|b)*t!*a_=Lo+(TW2qQFPuJTx5Orbh*PsyTl-sYBK`A(Phx+;NZ7BAS`Lylg@^Qq=em50*Dp^-j<2 zF_2Pxx%0PKWyf))Iqo&H09vphZQr(dh3@X#R&_bBfQ|2ey)VrUq$0ET^mpg9`}S_^ zHpYND3X66Jq$azk>8pKhXuZplc2jmY_hMh8!@XyBGyyPh-x6iPQ1;G!<^&enX92sc zg!hk*0T$V3&AZHr?+^P47Wz}{I(}5dz+4Y$8zhc;Fx1DG?|_5d;9J0nQ=pye*0LHUuIzfMgSL+|SQI fT? - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1/project.wdf deleted file mode 100644 index f9ca837..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:31:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:996450188 diff --git a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1/runme.log similarity index 71% rename from LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/runme.log rename to LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1/runme.log index 2ffc169..c4d5b1b 100644 --- a/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/runme.log +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1/runme.log @@ -1,6 +1,6 @@ *** Running vivado - with args -log Inverter_3lvl_BUS_16IN_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Inverter_3lvl_BUS_16IN_0_0.tcl + with args -log AckChecker_BusBlock16IN_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16IN_0_0.tcl ****** Vivado v2019.1 (64-bit) @@ -8,41 +8,44 @@ **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -source Inverter_3lvl_BUS_16IN_0_0.tcl -notrace +source AckChecker_BusBlock16IN_0_0.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/UPzynq20_test/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/UPzynq20_test/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -Command: synth_design -top Inverter_3lvl_BUS_16IN_0_0 -part xc7z020clg484-3 -mode out_of_context +Command: synth_design -top AckChecker_BusBlock16IN_0_0 -part xc7z020clg484-3 -mode out_of_context Starting synth_design +WARNING: [Vivado_Tcl 4-393] The 'Synthesis' target of the following IPs are stale, please generate the output products using the generate_target or synth_ip command before running synth_design. +D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_0/AckChecker_BusBlock16IN_0_0.xci + Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020' INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 12572 +INFO: Helper process launched with PID 7484 --------------------------------------------------------------------------------- -Starting Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 573.934 ; gain = 182.871 +Starting Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 575.473 ; gain = 182.285 --------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'Inverter_3lvl_BUS_16IN_0_0' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_0_0/synth/Inverter_3lvl_BUS_16IN_0_0.vhd:78] -INFO: [Synth 8-3491] module 'BUS_16IN' declared at 'd:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/f296/BUS_16IN.vhd:36' bound to instance 'U0' of component 'BUS_16IN' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_0_0/synth/Inverter_3lvl_BUS_16IN_0_0.vhd:109] -INFO: [Synth 8-638] synthesizing module 'BUS_16IN' [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/f296/BUS_16IN.vhd:60] -INFO: [Synth 8-256] done synthesizing module 'BUS_16IN' (1#1) [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ipshared/f296/BUS_16IN.vhd:60] -INFO: [Synth 8-256] done synthesizing module 'Inverter_3lvl_BUS_16IN_0_0' (2#1) [d:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.srcs/sources_1/bd/Inverter_3lvl/ip/Inverter_3lvl_BUS_16IN_0_0/synth/Inverter_3lvl_BUS_16IN_0_0.vhd:78] +INFO: [Synth 8-638] synthesizing module 'AckChecker_BusBlock16IN_0_0' [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_0/synth/AckChecker_BusBlock16IN_0_0.vhd:78] +INFO: [Synth 8-3491] module 'BusBlock16IN' declared at 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/2edf/BusBlock16IN.vhd:36' bound to instance 'U0' of component 'BusBlock16IN' [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_0/synth/AckChecker_BusBlock16IN_0_0.vhd:109] +INFO: [Synth 8-638] synthesizing module 'BusBlock16IN' [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/2edf/BusBlock16IN.vhd:57] +INFO: [Synth 8-256] done synthesizing module 'BusBlock16IN' (1#1) [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ipshared/2edf/BusBlock16IN.vhd:57] +INFO: [Synth 8-256] done synthesizing module 'AckChecker_BusBlock16IN_0_0' (2#1) [d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_0/synth/AckChecker_BusBlock16IN_0_0.vhd:78] --------------------------------------------------------------------------------- -Finished Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 637.832 ; gain = 246.770 +Finished Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.504 ; gain = 246.316 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 637.832 ; gain = 246.770 +Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.504 ; gain = 246.316 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg484-3 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 637.832 ; gain = 246.770 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.504 ; gain = 246.316 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg484-3 --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 637.832 ; gain = 246.770 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 639.504 ; gain = 246.316 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -79,9 +82,9 @@ No constraint files found. Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met -WARNING: [Synth 8-3330] design Inverter_3lvl_BUS_16IN_0_0 has an empty top module +WARNING: [Synth 8-3330] design AckChecker_BusBlock16IN_0_0 has an empty top module --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 794.504 ; gain = 403.441 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 793.395 ; gain = 400.207 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -94,7 +97,7 @@ No constraint files found. Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 794.504 ; gain = 403.441 +Finished Timing Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 793.395 ; gain = 400.207 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -106,7 +109,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 794.504 ; gain = 403.441 +Finished Technology Mapping : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 793.395 ; gain = 400.207 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -130,7 +133,7 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 794.504 ; gain = 403.441 +Finished IO Insertion : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 793.395 ; gain = 400.207 --------------------------------------------------------------------------------- Report Check Netlist: @@ -143,7 +146,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 794.504 ; gain = 403.441 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 793.395 ; gain = 400.207 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -155,25 +158,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 794.504 ; gain = 403.441 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 793.395 ; gain = 400.207 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 794.504 ; gain = 403.441 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 793.395 ; gain = 400.207 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 794.504 ; gain = 403.441 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 793.395 ; gain = 400.207 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 794.504 ; gain = 403.441 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 793.395 ; gain = 400.207 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -198,33 +201,33 @@ Report Instance Areas: |1 |top | | 0| +------+---------+-------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 794.504 ; gain = 403.441 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 793.395 ; gain = 400.207 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 794.504 ; gain = 403.441 -Synthesis Optimization Complete : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 794.504 ; gain = 403.441 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 793.395 ; gain = 400.207 +Synthesis Optimization Complete : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 793.395 ; gain = 400.207 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 905.922 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 906.848 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis -15 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +15 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 905.922 ; gain = 520.039 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 905.922 ; gain = 0.000 +synth_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 906.848 ; gain = 519.789 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 906.848 ; gain = 0.000 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Common 17-1381] The checkpoint 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/Inverter_3lvl_BUS_16IN_0_0.dcp' has been generated. -write_checkpoint: Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1292.023 ; gain = 386.102 +INFO: [Common 17-1381] The checkpoint 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1/AckChecker_BusBlock16IN_0_0.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1294.277 ; gain = 387.430 WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP Inverter_3lvl_BUS_16IN_0_0, cache-ID = 70127aa8275ccbbd -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1293.289 ; gain = 0.000 +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP AckChecker_BusBlock16IN_0_0, cache-ID = 362e20292c8426d9 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1295.273 ; gain = 0.000 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/GITEA/UPzynq20_test/IP/LIB/Inverter_3lvl/Inverter_3lvl.runs/Inverter_3lvl_BUS_16IN_0_0_synth_1/Inverter_3lvl_BUS_16IN_0_0.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file Inverter_3lvl_BUS_16IN_0_0_utilization_synth.rpt -pb Inverter_3lvl_BUS_16IN_0_0_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Fri Jun 11 07:49:57 2021... +INFO: [Common 17-1381] The checkpoint 'D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1/AckChecker_BusBlock16IN_0_0.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file AckChecker_BusBlock16IN_0_0_utilization_synth.rpt -pb AckChecker_BusBlock16IN_0_0_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:35:54 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1/runme.sh index 0d0b741..e1e50bc 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1/vivado.jou index 5615d31..bac4b05 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:08:10 2020 -# Process ID: 5440 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1 +# Start of session at: Wed May 3 11:35:16 2023 +# Process ID: 14820 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1 # Command line: vivado.exe -log AckChecker_BusBlock16IN_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16IN_0_0.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1/AckChecker_BusBlock16IN_0_0.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1/AckChecker_BusBlock16IN_0_0.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_BusBlock16IN_0_0.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_0_synth_1/vivado.pb index 90c5a96c4ba034d70983b90eb30fd5abdfdc5269..20207a5617a0ff313e99517474cf27d08b02373d 100644 GIT binary patch delta 1822 zcmb7F+iTNM9QLHPUE_4JmfGpG$H^S5HO)QEyr4{-(}}W8$E;Xmn{}0%)+U|Tp~HuX z_xTe92*Z&cRgdzzAl7)>J6^DNDs~@ z7fbE8ebgwr^uR+;px!|pw=|nA*wV^5-NMBIY>`(3#X_NYCU4|$=Rp%|WgVNAR?y?P zRM0h3$2r~5%bKNE!NrPIs#v&GE@mqk%fuDaAv!XDVd=l>Wo(`^tig1?gw;&()G5u# z;uHD+Stl-648!5g0KR5zg6Z0LL{cP1R0O;k=d`?mw_+~I zGkj8liS{UZ19@)>zd)p}`HOW7hag?M9zF-^&?k888;;&a^o504Q8*uHgu8y-t<4j3 zgQRMOAl(!lb8VraNtg+YE`rewmuu_LFTzp)yd3oPt%d`1$Zbrgjnhab9f!zsWcR9w zEU1jcigQi#qRa@KOq!m6=gYfXf$fR*4ah!O=cio39c{a>K91a@U&R&5eiZ()jN(|5 zKIjZ1yBop+BdF3`c#&lpo>i&_Rm#og`)F|#cona=dt0x}(YS@3A_0mMW^)M(pCerNJ{WgT3-a|rDjLP$}Po#c^LT4Isf_2fe&B7%nKN= zhu&m^=BnaKx`VZm!GXS>uJc2+jS)PS>%kC{mz?041tyvLm<1v`J+1*R_7~ArumhVq zchMT=2GC~qB9y7ZKB4DaM`Ea_Tc{HxDVX_G1kvl$4NcUQ4B$*hZ@)Q}i7ZOGj^HiB z1YZD8P|S~c9sze7R=v}Jb9vj4bN0bwyx<&mUjwdx73k#}rLTxKxu+6&0Po140(k1l~%)gu@!p^22-JOI_Y~_=#@yeZi(4# zd70U)HC}2~lgwt-!15k6BSi1-ybJb3CUfoaO%qOe+ToP~*)}oluD!{7@*&R--%27C zdSE88ArofT#enIskIvNJv?W469eij@0Mkd@bfIz7mIzIU58EjOD~~_lSd`oGP)m4& zRJzde1z24qL`Cy5(%I-$z+1&${CdKJS6aQupJb7?{s3!?Q}F^u)-p(Z7iCv?+!iih zmx(A7V%^}HHV;L5XiCAw;#W}G4 z3b%4jSs_I9Yq~W_wX>`u8h&N@IhtvTVwLdW^C;>s%f)WX;L{RXwV>8ZoRr~_;VaQSd diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/.vivado.begin.rst b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/.vivado.begin.rst index 53b96b8..cde83cd 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/.vivado.begin.rst +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/AckChecker_BusBlock16IN_0_1.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/AckChecker_BusBlock16IN_0_1.dcp index dd80b4bddf6d830e99608aefa3caa427922cd2c0..1040a174a0608e530a2e9e67a8924c6009400c2b 100644 GIT binary patch delta 3138 zcmZuzc{CL49v)*E+t4tUCK>w{G8wXF&oX3fY>8Xev4^olV?H5CWH3hdtr5x=N|t07 znX)u8S_%i|)D0&7c003YH+`LkR&IP&k zDKP*5X1o9Z96+#yp2o?$xwMGO zv)YjHu}+e@(qvSVPRZ#`d$PmT)VK>oXXowEo31OVs*%AN`;6F(OowK(VMoS6u4iuw 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zpL$pG25G~%11SuMGqAUS4A9~N$P*CdeNIw(@AN%}Q;U%cw$C`&XmP(892nVx7ktp* z+E-u;RwXrnfcani;F p07(A_v5tG6sK_q>`|Ag2W)Rs~006dsBLZTvWDkBQD+aRX{3nOQb}Rq@ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/AckChecker_BusBlock16IN_0_1.tcl b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/AckChecker_BusBlock16IN_0_1.tcl index d191a18..18fc7e9 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/AckChecker_BusBlock16IN_0_1.tcl +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/AckChecker_BusBlock16IN_0_1.tcl @@ -24,15 +24,15 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] -set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] +set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] +set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/Projects/IP [current_project] +set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project] update_ip_catalog -set_property ip_output_repo d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] +set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1.xci +read_ip -quiet D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1.xci # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1 -new_name AckChecker_BusBlock16IN_0_1 -ip [get_ips AckChecker_BusBlock16IN_0_1]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1 -new_name AckChecker_BusBlock16IN_0_1 -ip [get_ips AckChecker_BusBlock16IN_0_1]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_BusBlock16IN_0_1.dcp create_report "AckChecker_BusBlock16IN_0_1_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_BusBlock16IN_0_1_utilization_synth.rpt -pb AckChecker_BusBlock16IN_0_1_utilization_synth.pb" if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/AckChecker_BusBlock16IN_0_1.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/AckChecker_BusBlock16IN_0_1.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_stub.v + write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_stub.vhdl + write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_sim_netlist.v + write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,47 +120,47 @@ if { [catch { if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/AckChecker_BusBlock16IN_0_1.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/AckChecker_BusBlock16IN_0_1.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/AckChecker_BusBlock16IN_0_1_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_stub.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/AckChecker_BusBlock16IN_0_1_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/AckChecker_BusBlock16IN_0_1_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_stub.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/AckChecker_BusBlock16IN_0_1_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/AckChecker_BusBlock16IN_0_1_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_sim_netlist.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/AckChecker_BusBlock16IN_0_1_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/AckChecker_BusBlock16IN_0_1_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_sim_netlist.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/AckChecker_BusBlock16IN_0_1_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16IN_0_1]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16IN_0_1]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16IN_0_1 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16IN_0_1 } } -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16IN_0_1]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16IN_0_1]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16IN_0_1 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_0_1/AckChecker_BusBlock16IN_0_1_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16IN_0_1 } } file delete __synthesis_is_running__ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/AckChecker_BusBlock16IN_0_1.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/AckChecker_BusBlock16IN_0_1.vds index 5fe99f1..f60d607 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/AckChecker_BusBlock16IN_0_1.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/AckChecker_BusBlock16IN_0_1.vds @@ -2,17 +2,17 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:08:40 2020 -# Process ID: 15828 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1 +# Start of session at: Wed May 3 11:37:19 2023 +# Process ID: 12568 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1 # Command line: vivado.exe -log AckChecker_BusBlock16IN_0_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16IN_0_1.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/AckChecker_BusBlock16IN_0_1.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/AckChecker_BusBlock16IN_0_1.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_BusBlock16IN_0_1.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_BusBlock16IN_0_1, cache-ID = 554578a73191d286. -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:08:46 2020... +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_BusBlock16IN_0_1, cache-ID = 362e20292c8426d9. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:37:26 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/gen_run.xml index 6c33719..fba7ed4 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/gen_run.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/project.wdf deleted file mode 100644 index f9ca837..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:31:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:996450188 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/runme.log new file mode 100644 index 0000000..d0c6655 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_BusBlock16IN_0_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16IN_0_1.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_BusBlock16IN_0_1.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_BusBlock16IN_0_1, cache-ID = 362e20292c8426d9. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:37:26 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/runme.sh index 27c345c..05ff355 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/vivado.jou index 877bea8..ba0f7e2 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:08:40 2020 -# Process ID: 15828 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1 +# Start of session at: Wed May 3 11:37:19 2023 +# Process ID: 12568 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1 # Command line: vivado.exe -log AckChecker_BusBlock16IN_0_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16IN_0_1.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/AckChecker_BusBlock16IN_0_1.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1/AckChecker_BusBlock16IN_0_1.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_1_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_BusBlock16IN_0_1.tcl -notrace diff --git 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a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_2_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_2_synth_1/runme.log new file mode 100644 index 0000000..f5b91b8 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_2_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_BusBlock16IN_0_2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16IN_0_2.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_BusBlock16IN_0_2.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_2_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_BusBlock16IN_0_2, cache-ID = 362e20292c8426d9. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:37:27 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_2_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_2_synth_1/runme.sh index 2c41da4..890edd6 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_2_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_2_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_2_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_2_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_2_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_2_synth_1/vivado.jou index 976105d..c620727 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_2_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_2_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:08:40 2020 -# Process ID: 21592 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_2_synth_1 +# Start of session at: Wed May 3 11:37:20 2023 +# Process ID: 14652 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_2_synth_1 # Command line: vivado.exe -log AckChecker_BusBlock16IN_0_2.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16IN_0_2.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_2_synth_1/AckChecker_BusBlock16IN_0_2.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_2_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_2_synth_1/AckChecker_BusBlock16IN_0_2.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_0_2_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_BusBlock16IN_0_2.tcl -notrace diff --git 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:31:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:996450188 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_1_0_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_1_0_synth_1/runme.log new file mode 100644 index 0000000..a027ee5 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_1_0_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_BusBlock16IN_1_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16IN_1_0.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_BusBlock16IN_1_0.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_1_0_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_BusBlock16IN_1_0, cache-ID = 362e20292c8426d9. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:37:35 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_1_0_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_1_0_synth_1/runme.sh index b8e18cf..d50b6ba 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_1_0_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_1_0_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_1_0_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_1_0_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_1_0_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_1_0_synth_1/vivado.jou index d987c62..c0303bc 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_1_0_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_1_0_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:08:40 2020 -# Process ID: 9568 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_1_0_synth_1 +# Start of session at: Wed May 3 11:37:29 2023 +# Process ID: 14192 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_1_0_synth_1 # Command line: vivado.exe -log AckChecker_BusBlock16IN_1_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16IN_1_0.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_1_0_synth_1/AckChecker_BusBlock16IN_1_0.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_1_0_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_1_0_synth_1/AckChecker_BusBlock16IN_1_0.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_1_0_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_BusBlock16IN_1_0.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_1_0_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_1_0_synth_1/vivado.pb index 66a8331e8754fa5db38ef6a970452a579495e697..47de6efc4fb6ad4d525bbedca6637187fce5bf19 100644 GIT binary patch delta 182 zcmey%zJz0fGh^9A7ZW*sF6k62eRt0gS4VyK%o2~%Bz@Oleb0dS - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/AckChecker_BusBlock16IN_2_0.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/AckChecker_BusBlock16IN_2_0.dcp index 55aab8b90eecf4ef5caef7d599bd246161bf96bc..692ab15f557f3b012e1764eda423c667206b6df8 100644 GIT binary patch delta 3134 zcmZvec{CJm7srP%wjqoqWUONenT!!FWXUiiYh%ljP$p{_OEM~@VpB073QzE9QV@zNG0Kf{k zdo3T64Rq~RV*&t-1pojDag7CncXe@VNVD^MiUfB|?1P^Lv0-{ygx6E6sVZ#eE?Z!W z+-~0{>D($aV19ln?ws1hy}C<{Zsduaj9vx4aPJ( z=04un@A3+5u^{bPgdJLncPp2`j@{qFg;xg!1UXFYE9b6`a+$0Q=G8giiTNMm)y+UN zCuMve-CN}$s%5usYBCuQ3g;p&c>;6>Zs}N^wM0vk zD z%6Uh~V{CcW`a}B;Bv}^khYhvNM()+8%eU*n9F=5q&ziHinRL0GNpH)^S(94SGXi^% zBcwRwRjo=*k#gtlOCot!_Je$Tro!rch-{SMq;*i|qfviu5Bb#P?K{0&!cI3QfyGT9 zBbL2~RMC+2%q{6zVkTPoiEO8~U(XFYe?s?$$L3$3JYM5j$LX6h0NQ#zJmrR-feTu=3Dig0qYiB`cMn%e-H~O49@$caUJ7`>`3^i;m_eO^dn8QF6GX z$+VW?YQ;;!2`myt>tdsenSm{TIM9?K)^W$9s7 z&7On)0I>>Mr58TG*YJ*L1xE7?6^hYcrhbIy>}IY>F7zsrlN4=bY=l!>sHeK#mq??E zlN48s%Ka6(-oKFMcs@V@2jyJDdF9TV?55>;#y1T{-OPb}YB&MQha;SobdLh>(lTigE8SDeS-e$eM zIV!(y7`GgX#v5y^A6xsU_KR|DPad*8m`voLDRa*L(_vTjq`{!|eE+YIxE1@Ho3j;*5 z*whtXj%}k0Q$(^1)fGzU+wbGTDD>|cPJof9J`nDWfu|rbp=KF(d6uc}+>@QwA5Tjz zmvxwVtxsN%N7}UJ0Mm6%)tS+@ zeNq>9ACGNGSB_bfbr}^q+e8oGQmbN=+26}+W! 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Any black boxes in the @@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1 -new_name AckChecker_BusBlock16IN_2_0 -ip [get_ips AckChecker_BusBlock16IN_2_0]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1 -new_name AckChecker_BusBlock16IN_2_0 -ip [get_ips AckChecker_BusBlock16IN_2_0]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_BusBlock16IN_2_0.dcp create_report "AckChecker_BusBlock16IN_2_0_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_BusBlock16IN_2_0_utilization_synth.rpt -pb AckChecker_BusBlock16IN_2_0_utilization_synth.pb" if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/AckChecker_BusBlock16IN_2_0.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/AckChecker_BusBlock16IN_2_0.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_stub.v + write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_stub.vhdl + write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_sim_netlist.v + write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,47 +120,47 @@ if { [catch { if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/AckChecker_BusBlock16IN_2_0.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/AckChecker_BusBlock16IN_2_0.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/AckChecker_BusBlock16IN_2_0_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_stub.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/AckChecker_BusBlock16IN_2_0_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/AckChecker_BusBlock16IN_2_0_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_stub.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/AckChecker_BusBlock16IN_2_0_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/AckChecker_BusBlock16IN_2_0_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_sim_netlist.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/AckChecker_BusBlock16IN_2_0_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/AckChecker_BusBlock16IN_2_0_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_sim_netlist.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/AckChecker_BusBlock16IN_2_0_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16IN_2_0]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16IN_2_0]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16IN_2_0 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16IN_2_0 } } -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16IN_2_0]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16IN_2_0]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16IN_2_0 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_2_0/AckChecker_BusBlock16IN_2_0_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16IN_2_0 } } file delete __synthesis_is_running__ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/AckChecker_BusBlock16IN_2_0.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/AckChecker_BusBlock16IN_2_0.vds index b82682c..d74d077 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/AckChecker_BusBlock16IN_2_0.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/AckChecker_BusBlock16IN_2_0.vds @@ -2,17 +2,17 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:08:40 2020 -# Process ID: 21708 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1 +# Start of session at: Wed May 3 11:37:26 2023 +# Process ID: 14796 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1 # Command line: vivado.exe -log AckChecker_BusBlock16IN_2_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16IN_2_0.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/AckChecker_BusBlock16IN_2_0.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/AckChecker_BusBlock16IN_2_0.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_BusBlock16IN_2_0.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_BusBlock16IN_2_0, cache-ID = 554578a73191d286. -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:08:47 2020... +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_BusBlock16IN_2_0, cache-ID = 362e20292c8426d9. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:37:33 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/gen_run.xml index 65b9ebe..6efcd48 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/gen_run.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/project.wdf deleted file mode 100644 index f9ca837..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:31:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:996450188 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/runme.log new file mode 100644 index 0000000..246d228 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_BusBlock16IN_2_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16IN_2_0.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_BusBlock16IN_2_0.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_BusBlock16IN_2_0, cache-ID = 362e20292c8426d9. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:37:33 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/runme.sh index e885a57..ad7236b 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/vivado.jou index 41ac674..ac7eadb 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:08:40 2020 -# Process ID: 21708 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1 +# Start of session at: Wed May 3 11:37:26 2023 +# Process ID: 14796 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1 # Command line: vivado.exe -log AckChecker_BusBlock16IN_2_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16IN_2_0.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/AckChecker_BusBlock16IN_2_0.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/AckChecker_BusBlock16IN_2_0.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_BusBlock16IN_2_0.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_2_0_synth_1/vivado.pb index 6b4ce9055c43308d995661c7908ac0391e4f350e..fdd25bb7988b5712f3707d0f22677f1f6fcfd0b8 100644 GIT binary patch delta 182 zcmey%zJz0fGh^9A7ZW*sF6k62eRt0gS4VyK%o2~%Bz@Oleb0dSwj- delta 137 zcmZ3&@t1vqGh^mN7ZX7xF1{2i{eYtUtkmR^Vtvnm$+}G96W0nb{a~87{}LAIgUrH$ z`CQScnl?XRtYj20H8n9cw@5TMHncQMF|sfN88x|qIa - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/AckChecker_BusBlock16IN_4_0.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/AckChecker_BusBlock16IN_4_0.dcp index 08018b907f1efc872eaaee15693438a91b943ab5..a91967868a7deeb715bf5e298211613ae18daecb 100644 GIT binary patch delta 3134 zcmZvec{CJm7sn@IY(p4J$jCC5B9k$e7P4fRk+rd9Nhp&wj3pV9?WZCP#=g@`RJQQ5 zMD``i^czHmEZNtRta(-M`<~zLJ?}l|IrpB=z0ZA~Kc4fw&x&058DV48aYirz0AK;! zzmbp00y=jqGXemH`~U!ixW){@J3F~Fq}cf6A;BFJ2jFJ`te9SAp^fBfsv_%!t7h0D zm%DdKT6fCyn4VvWxu87ppzccHsWvOJwOvBwWs<%9w*P&nWqeiLOF;l?f|WUJ6dK&j*;+nas%@M`^cz=7$JBj4$kMd7H@8} zoZ-;W9>QVjsf~e^{-`rbY)Y6y}WdeswuOJQJ2g4)VA#GHHk$X1F#!8 zOoClj$)eO4DRa@bB%EjEAi%q4Dx}Vf$VwSb*Z_4t8TI9IlTBXUx!1cb22@ToE*p{3nW}p?)rR%NfqY@O|dM?<-liIi3w*LC$_8QMJPT!j0kDePy;e6M% z`Kc>78gfg$`V>cpg_{N=oOz@uQN9FS=J^U%n!^9Ig9LLwh)&~Lv^PCvT+CUHlEEcR zrnC%KpS>a!$9%eILo~Tre2xDtTR(z2(R%R1PjMd$dY5~1BXd2BDJd-TsVuTynjT`& z>^|rV5Urq9df@YW_3w#PVAS7Gp%~p|>PL9?UdEdELho5}!dYu6E1@JO>Y1+hC6cJ( zgtIFK<-T%V?_Wr=KcAm|HM^uY82p2rwg$N_0hm8D4>b#;<5S8YdR9&&9UGtDvY7_u ziQ2DguiIz_FAo`IF^mt2EmsO~&d>N>ZavYSga)+v#Nmfi>~+sG(!i18f?q03mrsl~ zN@|I7%b^SAcyh~i(vSswQ0xqkt8=uFxJkZZd@_nAgDQBe6LeEN5mi8v!amaJZPwYJ zqw;BoaLJ%(Jki#=(Y1eSz9`pp=O){N$wYRV0y~YHpsq_8{ZliuT+^1DYy(DucYSg^ zti*ir&=2HN$2oR{+^Y|B3AUCMo=BW)@73FRF>J-SH+S;iKac5i66PCP2_Csx=qH@X zsv`GtYzJMKB%GoD=yn7ky5v}(-;rfM6>Gz24iT=nIbEw$_LJkJi@HZ>}GoF@dYaopYQD2|V)GokHx zB`@wh9ov?y95XBHGAMSmiX6ZtS4GLY{D`54`{eIe3wwQedPo^AubmL=hkfKdy95ti zV9?ICsJ-eF03B!0gGs(VFKZx;LQ#F zFj?bN{M~}t`kC!>|I`;^5aScZpF&f?#zZ^D`7^5L(Bbtt5};H7ae(tQ5d@6-RX|Ju z8i0Q0#iL`C+>a#b4si_##ou8h?OD17U|_1cT4Fy<4WabQ!<7}+&Z^Y}Q?J3R*;z^~ zFo<~X#-V6n4X5KkvWR8PBMY9(xAE+sH(yTXl;L+da3iYJYKUi-az{KUWcVv|@CMqs(ZQCQ*5~arB4o1qGH%(>S3R!HTLhOb z$idAg0vL-^qpalN7>N(4EHv9@@-g?T*hfUuHnr_k_D!pEB1T`$>7-bCVif~x`zU`A z2>(F>(`N+S(2EJ4P_Wb(3;euSa`^Oc>sHOlp{iz)4Bue=vaGtP_sJ60@b2{ZFO7HX z5Z%oWWnzQfYr>5by|m*hp@tU%=hf{apsO?(SB9UV^JxcF&j;Qb!9h^i!hn6(B_}pI zEx=E=ulB~Ec_mI#YLL1jfK)`Q>^P-OFTooz)*> zk1k2yH(^Ntk&))P^&PwIdO<1gVVrI#!T_ncs#g*tFysg9N}aU#-{Y9YUmqsF50JMN zM02v``Yp&^Do_>OdM-hghB*i5-qp}Cop1b9evfaik=ejYkdkXEf?v5PudLCIVf8V9 zxjvCgEuz|86#9cwNLKfRhuBsI?(wA3r`U>1Q2xzB@DaK8)8+DuT+=7=4k-^}1SLb$ zc&-%b{!PM;9|;l>&yo3C!^A*&$9_lcoEgVh%Z`%0IlPD#;@uN6_+F2EMR3G0@mZ;5 z?^y#v0@_T9!T^;wW#HCu#qq<6UTZCPY8uQfM1lQBt)5Jc?26#OkKLCyTK%ZadQHbX zv4Y~V7>UymMvnk6sOx6ZJTua)Z^FUS!Uo#X7}n< z^g=@2oHmDy2j+Tk(=DRhLm&rv0@*FKx_}mxL9$g>=Xo(uGpqLKq{9tI;vDK#zjvd=7SHN5(lh&G_5cdTDaycZ+7h6h4$pV=67i~#`nKi^}b8;|DiF;&VV#Bh(1xXvs}T;w_N zoBcRq3`|E1LR91B{LN6jLJXtKM@*U+%ggbbWgW3N;IF+Oc)7&>G3|~fp6Jn3{Et-; z#(xzm1bF=KrBb4p;;fG9oQ{^?fNkejO?n{yp)Na%VxU;aUEvZ{HYPL@SbV8TuSaiLn5O;n0ay7am!Zci!lEQ?q2L^BpO$}Y zOR1D;V0)BQ*Rz-8xik52ct~Yj1=FzM;;H7$?UV}(HvKG%hsT_(WaFY|((NFNn<$@> zu&{+49h4!ANX`UAUEa)qM$~fV`wYw_lo(uqBlMMGH=C&+mKqT4lV5IV3h%jY1bMc0 zJR2HC$4=Wq8^v_Fs!4(zZ611LmqI6B1gw5-wwS!LwSBTAY=Y9M*bqc4csI9v@eXQp(IaqXUk^p$Yl{T*0sVVPICpDaYd!i1av^aQID7VsvT971JT(2v zyyl>cImbqeOTR=Nijya4Dut{n%Ar0_jA#8Ywc4jRe2*7TQWeoxPStmEhe~DDC;rw4@lI0_^gr~K;K=(vuv?DU$G_t`M<4Yc{IZkmfziFk2X=*TDd>-d=-c(}!pILKyEH)lzAf+tN7$@K4-z_mZw??cA|#I*OO0%Ls{J%TobADD z#3tXj51}1lQ633a;q!%D9kh-^e+D{_Pw9f`kg zCLcz6c(!nf5+gTOthtlq<@k;mDn4FT?{g$stD>vvYbhlo(jJ_8d20 z=k$0eF|=@a9H%h3fLrm`0yFh;g<3Uox%%j48FzVH14mJvdyOaza$eC}tnC zkY`*HqNH`l$zCCi+i9aG_@SWpak`Q6{t7r}?~}pcX}6`jpZL%D#+%@-Jiy|Qu9=O5 zLh`OP_XL3m)fQ%@W?_LA6CWKk<*(m-*YOkH=)qc>dFykdFztn~+&WVKdg!{D9mr8SH;6hN;N!PW)>xmb_o8s?VK7~ze3~p!wEl%4R6me}&E7lgyWozNVCp)6= z=9+}-1WL*dzVNgvnOnH6hRY-!ihLc5#gOhJENQn*O+GC>;!ZwP*eFMylXi;u>R)+n zH2{w$DhmZSuXa+ic*aCJIVhFQv<#*%qLz`3C564`t(2T_%L=QBKP)$|x$c;f)W$C% zUB0Jggo)`HSmNuX_&_7|87TFMDy~yyU0Sjkf>y-|4bC?doukf6gou)Y3YiLeIUi&4 z;tpM!sLS2?X*#VL|Mn-Uqg%h-nL^0=kYr-D$ac_jnRf=^fk!M97^;^U*_JV+PlKaa9Py#znleeNFOuR{cL2BNyU zKH9}^qSazVY0g+NH6s#aSCrH8O@YnKXC|yGR`bLgPTbD5W1EQkR5pOS&{WM!$83pn zhhk+p+^%c44oF{$rmVc2W|MvmOjJt(2h7BTm&o!HVAk}yLf&y&l5*5D@$p^h7q~fK z-&cB?1#OgjGlv|jHa%*eMRMS zWf&x@_4~5+hNCBEe4bqyVra5b|;{Q z6{!T%^|=wEV^6>JyG|8f2T@edBTlT@fIWxnxF~;GEG>Kt+TRk1h7xvd^6(j za^a!8&ehOVf@4R}T=Tcvgda}`G%P%TeBL{cv`WV4Kn2H!2UO0P`_ddTUq%_JbwBLW zJzW{?4Ro@-r#U&$Ieqnn$wMX64RKGK z73j%%;#9Dj+-+0$%bWd(%j}%raJ!r_`c3l2+5d>ufevL|g`_(%x*{(CHIJPNJ_yxm zaTEamcoUpCK(-@{*c7VVvx6GPElaWvxT|us=VgEC10BDsHfM{>E2Zq)i%cZAzsn2` zO7zq_ToV@TT{yXm3VOey(ybRbed$+J-ZN#-$SGlXphQ7Q&Y*^^cKy!Qg{3FlEe65Q zVGp)mDR5NDe)2349FP9tz2tQnfXS*prp)YdSxkKpmZpd&5=PF)+<^ci)lD@?mq1qL zl^~SRM|K4Wr1BR(R!e0?Z)f8Lz5P&0yV}5eU|p(Y*5h(7;)0yAj!y2yNw9msa;31} z6H{L$*y5LOY3@nhAD71NjXF-T=+B*zQ~tJBEy>eM@GYH*2>9?*yf#A>D~Zfget$hY z$^uIQ`XbH7aUyX^g6Z$JY9x|L^y$m9_1QFP55eHzbO)Bdb69HDO)V1832*~he4ec z&0s%heP}@&Z4Lwh0RN{KrY1lQ#SU(+R}C+WZ5X>Eg<)b0I~YKQ(c_5VgI-yM;Exaf zJIz57C2er_E(4{-AQ%0e^5;d5`*o0{_?x+f-IzCo5x>K*<9~tvFu!4DfJCXeynLbu zY|idE@;nRx7sLL=_6JCzzT#C9``=6SFE++Rj~it=?6r<+rx6yZlin?sln)($ZqFoVn%dhqp68e)U$ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/AckChecker_BusBlock16IN_4_0.tcl b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/AckChecker_BusBlock16IN_4_0.tcl index 2f5b5f5..1de8696 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/AckChecker_BusBlock16IN_4_0.tcl +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/AckChecker_BusBlock16IN_4_0.tcl @@ -24,15 +24,15 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] -set_property parent.project_path D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] +set_property webtalk.parent_dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/wt [current_project] +set_property parent.project_path D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] -set_property ip_repo_paths d:/Projects/IP [current_project] +set_property ip_repo_paths d:/GITEA/GitHub/ES/IP_cores [current_project] update_ip_catalog -set_property ip_output_repo d:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] +set_property ip_output_repo d:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0.xci +read_ip -quiet D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0.xci # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -44,7 +44,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1 -new_name AckChecker_BusBlock16IN_4_0 -ip [get_ips AckChecker_BusBlock16IN_4_0]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1 -new_name AckChecker_BusBlock16IN_4_0 -ip [get_ips AckChecker_BusBlock16IN_4_0]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -85,32 +85,32 @@ write_checkpoint -force -noxdef AckChecker_BusBlock16IN_4_0.dcp create_report "AckChecker_BusBlock16IN_4_0_synth_1_synth_report_utilization_0" "report_utilization -file AckChecker_BusBlock16IN_4_0_utilization_synth.rpt -pb AckChecker_BusBlock16IN_4_0_utilization_synth.pb" if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/AckChecker_BusBlock16IN_4_0.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/AckChecker_BusBlock16IN_4_0.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - write_verilog -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_stub.v + write_verilog -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_stub.vhdl + write_vhdl -force -mode synth_stub D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_sim_netlist.v + write_verilog -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,47 +120,47 @@ if { [catch { if { [catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/AckChecker_BusBlock16IN_4_0.dcp D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0.dcp + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/AckChecker_BusBlock16IN_4_0.dcp D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/AckChecker_BusBlock16IN_4_0_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_stub.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/AckChecker_BusBlock16IN_4_0_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/AckChecker_BusBlock16IN_4_0_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_stub.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/AckChecker_BusBlock16IN_4_0_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/AckChecker_BusBlock16IN_4_0_sim_netlist.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_sim_netlist.v + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/AckChecker_BusBlock16IN_4_0_sim_netlist.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - file rename -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/AckChecker_BusBlock16IN_4_0_sim_netlist.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_sim_netlist.vhdl + file rename -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/AckChecker_BusBlock16IN_4_0_sim_netlist.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16IN_4_0]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16IN_4_0]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_stub.v D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16IN_4_0 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_stub.v D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16IN_4_0 } } -if {[file isdir D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16IN_4_0]} { +if {[file isdir D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16IN_4_0]} { catch { - file copy -force D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_stub.vhdl D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16IN_4_0 + file copy -force D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.srcs/sources_1/bd/AckChecker/ip/AckChecker_BusBlock16IN_4_0/AckChecker_BusBlock16IN_4_0_stub.vhdl D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.ip_user_files/ip/AckChecker_BusBlock16IN_4_0 } } file delete __synthesis_is_running__ diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/AckChecker_BusBlock16IN_4_0.vds b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/AckChecker_BusBlock16IN_4_0.vds index 1878a6b..0689316 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/AckChecker_BusBlock16IN_4_0.vds +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/AckChecker_BusBlock16IN_4_0.vds @@ -2,17 +2,17 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:08:40 2020 -# Process ID: 18852 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1 +# Start of session at: Wed May 3 11:37:29 2023 +# Process ID: 13508 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1 # Command line: vivado.exe -log AckChecker_BusBlock16IN_4_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16IN_4_0.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/AckChecker_BusBlock16IN_4_0.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/AckChecker_BusBlock16IN_4_0.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_BusBlock16IN_4_0.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Projects/IP'. -WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/Projects/IP' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1'.) +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1'.) INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. -INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_BusBlock16IN_4_0, cache-ID = 554578a73191d286. -INFO: [Common 17-206] Exiting Vivado at Wed Apr 29 14:08:46 2020... +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_BusBlock16IN_4_0, cache-ID = 362e20292c8426d9. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:37:35 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/gen_run.xml b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/gen_run.xml index 8ce7884..befc921 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/gen_run.xml +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -46,9 +46,7 @@ - - Vivado Synthesis Defaults - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/project.wdf b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/project.wdf deleted file mode 100644 index f9ca837..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:31:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:996450188 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/runme.log new file mode 100644 index 0000000..7f5d18f --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_BusBlock16IN_4_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16IN_4_0.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_BusBlock16IN_4_0.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_BusBlock16IN_4_0, cache-ID = 362e20292c8426d9. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:37:35 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/runme.sh index db1ad4d..8fa2137 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/vivado.jou index 8fe23cc..3588c1a 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:08:40 2020 -# Process ID: 18852 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1 +# Start of session at: Wed May 3 11:37:29 2023 +# Process ID: 13508 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1 # Command line: vivado.exe -log AckChecker_BusBlock16IN_4_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16IN_4_0.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/AckChecker_BusBlock16IN_4_0.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1/AckChecker_BusBlock16IN_4_0.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_0_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_BusBlock16IN_4_0.tcl -notrace diff --git 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b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_1_synth_1/project.wdf deleted file mode 100644 index f9ca837..0000000 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_1_synth_1/project.wdf +++ /dev/null @@ -1,75 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:31:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:996450188 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_1_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_1_synth_1/runme.log new file mode 100644 index 0000000..171441e --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_1_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_BusBlock16IN_4_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16IN_4_1.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_BusBlock16IN_4_1.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_1_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_BusBlock16IN_4_1, cache-ID = 362e20292c8426d9. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:37:36 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_1_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_1_synth_1/runme.sh index 3dbe860..dc7bc04 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_1_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_1_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_1_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_1_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_1_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_1_synth_1/vivado.jou index ccbe670..61617e7 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_1_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_1_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:08:40 2020 -# Process ID: 15796 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_1_synth_1 +# Start of session at: Wed May 3 11:37:30 2023 +# Process ID: 7524 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_1_synth_1 # Command line: vivado.exe -log AckChecker_BusBlock16IN_4_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16IN_4_1.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_1_synth_1/AckChecker_BusBlock16IN_4_1.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_1_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_1_synth_1/AckChecker_BusBlock16IN_4_1.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_4_1_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_BusBlock16IN_4_1.tcl -notrace diff --git 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:31:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3037393161643236363831303438333661633166663137666332616561666162:506172656e742050412070726f6a656374204944:00 -eof:996450188 diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_6_0_synth_1/runme.log b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_6_0_synth_1/runme.log new file mode 100644 index 0000000..4c9ff26 --- /dev/null +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_6_0_synth_1/runme.log @@ -0,0 +1,17 @@ + +*** Running vivado + with args -log AckChecker_BusBlock16IN_6_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16IN_6_0.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source AckChecker_BusBlock16IN_6_0.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/GITEA/GitHub/ES/IP_cores'. +WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/GITEA/GitHub/ES/IP_cores' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_6_0_synth_1'.) +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP AckChecker_BusBlock16IN_6_0, cache-ID = 362e20292c8426d9. +INFO: [Common 17-206] Exiting Vivado at Wed May 3 11:37:41 2023... diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_6_0_synth_1/runme.sh b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_6_0_synth_1/runme.sh index fa972c3..c6b90e3 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_6_0_synth_1/runme.sh +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_6_0_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_6_0_synth_1' +HD_PWD='D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_6_0_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_6_0_synth_1/vivado.jou b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_6_0_synth_1/vivado.jou index a35d3fd..f69c8f9 100644 --- a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_6_0_synth_1/vivado.jou +++ b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_6_0_synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 -# Start of session at: Wed Apr 29 14:08:49 2020 -# Process ID: 23256 -# Current directory: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_6_0_synth_1 +# Start of session at: Wed May 3 11:37:36 2023 +# Process ID: 9032 +# Current directory: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_6_0_synth_1 # Command line: vivado.exe -log AckChecker_BusBlock16IN_6_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source AckChecker_BusBlock16IN_6_0.tcl -# Log file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_6_0_synth_1/AckChecker_BusBlock16IN_6_0.vds -# Journal file: D:/Projects/IP/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_6_0_synth_1\vivado.jou +# Log file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_6_0_synth_1/AckChecker_BusBlock16IN_6_0.vds +# Journal file: D:/GITEA/GitHub/ES/IP_cores/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_6_0_synth_1\vivado.jou #----------------------------------------------------------- source AckChecker_BusBlock16IN_6_0.tcl -notrace diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_6_0_synth_1/vivado.pb b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16IN_6_0_synth_1/vivado.pb index 03f4156d78060d20012d3f7eafdbdd3c028d1cb0..e804ffd1cd0b7adf06d21634f135ad8cdcdbbe51 100644 GIT binary patch delta 182 zcmey%zJz0fGh^9A7ZW*sF6k62eRt0gS4VyK%o2~%Bz@Oleb0dS - + diff --git a/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0.dcp b/LIB/AckCheckerBlock/AckCheckerBlock.runs/AckChecker_BusBlock16OUT_0_0_synth_1/AckChecker_BusBlock16OUT_0_0.dcp index 032d644f78d92c61b65c03373687adb97968c1cf..ee36c73cc1cfee923d468a735024938a17c183d0 100644 GIT binary patch delta 6513 zcmZ9RbyQSQ*Tx4B0g0icV?au}Q@R_ZV+iT)j-gW!7#Lc*yStGRL3(He>5>qU{7}F3 zz3ctXTKnE}f6ue`y=&cn_Bp3rdR7{urikQL0{jdMw3WtLnaU9Wfa+%e0Ll|J zH*;q7cCb%L20LZ4<44q_8k@Q_fs+ww^)zV95b0QO`(9GooG`x|w+)9U1}C2^uwfci z*kpWP{kZ$nEk1x|^5j+$Q$>?k=|`JsCd{RW=*u0U!j){FH##rnI7e@W3xsMn!h%`G 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