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206
F28335.cmd
Normal file
206
F28335.cmd
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/*
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// TI File $Revision: /main/10 $
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// Checkin $Date: July 9, 2008 13:43:56 $
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//###########################################################################
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//
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// FILE: F28335.cmd
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//
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// TITLE: Linker Command File For F28335 Device
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//
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//###########################################################################
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// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
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// $Release Date: August 1, 2008 $
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//###########################################################################
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*/
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/* ======================================================
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// For Code Composer Studio V2.2 and later
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// ---------------------------------------
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// In addition to this memory linker command file,
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// add the header linker command file directly to the project.
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// The header linker command file is required to link the
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// peripheral structures to the proper locations within
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// the memory map.
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//
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// The header linker files are found in <base>\DSP2833x_Headers\cmd
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//
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// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
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// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
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========================================================= */
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/* ======================================================
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// For Code Composer Studio prior to V2.2
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// --------------------------------------
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// 1) Use one of the following -l statements to include the
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// header linker command file in the project. The header linker
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// file is required to link the peripheral structures to the proper
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// locations within the memory map */
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/* Uncomment this line to include file only for non-BIOS applications */
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/* -l DSP2833x_Headers_nonBIOS.cmd */
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/* Uncomment this line to include file only for BIOS applications */
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/* -l DSP2833x_Headers_BIOS.cmd */
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/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
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library search path under project->build options, linker tab,
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library search path (-i).
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/*========================================================= */
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/* Define the memory block start/length for the F28335
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PAGE 0 will be used to organize program sections
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PAGE 1 will be used to organize data sections
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Notes:
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Memory blocks on F28335 are uniform (ie same
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physical memory) in both PAGE 0 and PAGE 1.
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That is the same memory region should not be
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defined for both PAGE 0 and PAGE 1.
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Doing so will result in corruption of program
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and/or data.
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L0/L1/L2 and L3 memory blocks are mirrored - that is
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they can be accessed in high memory or low memory.
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For simplicity only one instance is used in this
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linker file.
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Contiguous SARAM memory blocks can be combined
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if required to create a larger memory block.
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*/
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MEMORY
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{
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PAGE 0: /* Program Memory */
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/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
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ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */
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RAML0 : origin = 0x008000, length = 0x004000 /* on-chip RAM block L0 */
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/* RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */
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/* RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */
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// RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */
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RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */
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ZONE6 : origin = 0x0100000, length = 0x100000 /* XINTF zone 6 */
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FLASHH : origin = 0x300000, length = 0x008000 /* on-chip FLASH */
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FLASHG : origin = 0x308000, length = 0x008000 /* on-chip FLASH */
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FLASHF : origin = 0x310000, length = 0x008000 /* on-chip FLASH */
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FLASHE : origin = 0x318000, length = 0x008000 /* on-chip FLASH */
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FLASHD : origin = 0x320000, length = 0x008000 /* on-chip FLASH */
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FLASHC : origin = 0x328000, length = 0x008000 /* on-chip FLASH */
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FLASHA : origin = 0x338000, length = 0x007F80 /* on-chip FLASH */
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CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
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BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
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CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
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OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */
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ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */
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IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */
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IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */
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FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */
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ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */
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RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
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VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
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PAGE 1 : /* Data Memory */
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/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
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/* Registers remain on PAGE1 */
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BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
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RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
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RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
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RAML5 : origin = 0x00D000, length = 0x003000 /* on-chip RAM block L1 */
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/* RAML6 : origin = 0x00E000, length = 0x001000 /* on-chip RAM block L1 */
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/* RAML7 : origin = 0x00F000, length = 0x001000 /* on-chip RAM block L1 */
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ZONE7A : origin = 0x0200000, length = 0x00FC00 /* XINTF zone 7 - program space */
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ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
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FLASHB : origin = 0x330000, length = 0x008000 /* on-chip FLASH */
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}
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/* Allocate sections to memory blocks.
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Note:
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codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
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execution when booting to flash
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ramfuncs user defined section to store functions that will be copied from Flash into RAM
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*/
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SECTIONS
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{
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/* Allocate program areas: */
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.cinit : > RAML0 PAGE = 0
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.pinit : > RAML0 PAGE = 0
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.text : > RAML0 PAGE = 0
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codestart : > BEGIN PAGE = 0
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ramfuncs : LOAD = RAML4,
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RUN = RAML4,
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LOAD_START(_RamfuncsLoadStart),
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LOAD_END(_RamfuncsLoadEnd),
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RUN_START(_RamfuncsRunStart),
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PAGE = 0
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csmpasswds : > CSM_PWL PAGE = 0
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csm_rsvd : > CSM_RSVD PAGE = 0
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/* Allocate uninitalized data sections: */
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.stack : > RAMM1 PAGE = 1
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.ebss : > RAML5 PAGE = 1
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.esysmem : > RAML0 PAGE = 0
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.logg : > ZONE7A PAGE = 1
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/* Initalized sections go in Flash */
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/* For SDFlash to program these, they must be allocated to page 0 */
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.econst : > RAML4 PAGE = 0
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.switch : > RAML4 PAGE = 0
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/* Allocate IQ math areas: */
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IQmath : > FLASHC PAGE = 0 /* Math Code */
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IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
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/* Uncomment the section below if calling the IQNexp() or IQexp()
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functions from the IQMath.lib library in order to utilize the
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relevant IQ Math table in Boot ROM (This saves space and Boot ROM
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is 1 wait-state). If this section is not uncommented, IQmathTables2
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will be loaded into other memory (SARAM, Flash, etc.) and will take
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up space, but 0 wait-state is possible.
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*/
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/*
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IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
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{
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IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
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}
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*/
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FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
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/* Allocate DMA-accessible RAM sections: * /
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DMARAML4 : > RAML4, PAGE = 1
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DMARAML5 : > RAML5, PAGE = 1
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/* DMARAML6 : > RAML6, PAGE = 1
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DMARAML7 : > RAML7, PAGE = 1
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*/
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/* Allocate 0x400 of XINTF Zone 7 to storing data */
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ZONE7DATA : > ZONE7B, PAGE = 1
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/* .reset is a standard section used by the compiler. It contains the */
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/* the address of the start of _c_int00 for C Code. /*
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/* When using the boot ROM this section and the CPU vector */
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/* table is not needed. Thus the default type is set here to */
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/* DSECT */
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.reset : > RESET, PAGE = 0, TYPE = DSECT
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vectors : > VECTORS PAGE = 0, TYPE = DSECT
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/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
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.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
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}
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/*
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//===========================================================================
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// End of file.
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//===========================================================================
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*/
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194
GPIO_table.h
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194
GPIO_table.h
Normal file
@@ -0,0 +1,194 @@
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#define COMM_gpio00_dir 0UL
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#define COMM_gpio01_dir 0UL
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#define COMM_gpio02_dir 0UL
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#define COMM_gpio03_dir 0UL
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#define COMM_gpio04_dir 0UL
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#define COMM_gpio05_dir 0UL
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#define COMM_gpio06_dir 0UL
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#define COMM_gpio07_dir 0UL
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#define COMM_gpio08_dir 0UL
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#define COMM_gpio09_dir 0UL
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#define COMM_gpio10_dir 0UL
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#define COMM_gpio11_dir 0UL
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#define COMM_gpio19_dir 1UL // 63 — SPI
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#define COMM_gpio20_dir 0UL // 64 2:9B mode 2
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#define COMM_gpio21_dir 0UL // 65 2:9A mode 4
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#define COMM_gpio22_dir 0UL // 66 2:12C mode 1
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#define COMM_gpio23_dir 0UL // 67 2:12B control -24V
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#define COMM_gpio24_dir 0UL
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#define COMM_gpio25_dir 0UL
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#define COMM_gpio26_dir 0UL // 72 2:11B control +24V
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#define COMM_gpio27_dir 0UL
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#define COMM_gpio32_dir 1UL // 74 2:10B SDA
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#define COMM_gpio33_dir 1UL // 75 2:10C SCL
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#define COMM_gpio34_dir 1UL // 142 — SCI
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#define COMM_gpio48_dir 1UL // 88 2:14C DIOD red
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#define COMM_gpio49_dir 1UL // 89 2:14B ts2 red
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#define COMM_gpio50_dir 0UL
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#define COMM_gpio51_dir 0UL // 91 2:13C mode !8
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#define COMM_gpio52_dir 1UL // 94 2:13B ts1 green
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#define COMM_gpio53_dir 0UL
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#define COMM_gpio58_dir 1UL // 100 1:13C led term
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#define COMM_gpio59_dir 1UL // 110 1:13B gotov
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#define COMM_gpio60_dir 1UL // 111 1:13A led job
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#define COMM_gpio61_dir 0UL
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#define COMM_gpio62_dir 1UL // 113 1:14B alarm
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#define COMM_gpio63_dir 1UL // 114 1:14A rez out
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//===========================================================================
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#define VEPP_gpio00_dir 0UL // 5 2:7A input
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#define VEPP_gpio01_dir 0UL // 6 2:4A input
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#define VEPP_gpio02_dir 0UL // 7 2:7B input
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#define VEPP_gpio03_dir 0UL // 10 2:4B input
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#define VEPP_gpio04_dir 0UL // 11 2:7C input
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#define VEPP_gpio05_dir 0UL // 12 2:4C input
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#define VEPP_gpio06_dir 0UL // 13 2:6A input
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#define VEPP_gpio07_dir 0UL // 16 2:3A input
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#define VEPP_gpio08_dir 0UL // 17 2:6B input
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#define VEPP_gpio09_dir 0UL // 18 2:3B input
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#define VEPP_gpio10_dir 0UL // 19 2:6C input
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#define VEPP_gpio11_dir 0UL // 20 2:3C input
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#define VEPP_gpio19_dir 1UL // 63 — SPI
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#define VEPP_gpio20_dir 0UL // 64 2:9B mode 2
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#define VEPP_gpio21_dir 0UL // 65 2:9A mode 4
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#define VEPP_gpio22_dir 0UL // 66 2:12C mode 1
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#define VEPP_gpio23_dir 0UL // 67 2:12B input
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#define VEPP_gpio24_dir 0UL // 68 2:12A input
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#define VEPP_gpio25_dir 0UL // 69 2:11C input
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#define VEPP_gpio26_dir 0UL // 72 2:11B input
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#define VEPP_gpio27_dir 0UL // 73 2:11A input
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#define VEPP_gpio32_dir 0UL // 74 2:10B input
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#define VEPP_gpio33_dir 0UL // 75 2:10C input
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#define VEPP_gpio34_dir 1UL // 142 — SCI
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#define VEPP_gpio48_dir 1UL // 88 2:14C DIOD red
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#define VEPP_gpio49_dir 0UL // 89 2:14B input
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#define VEPP_gpio50_dir 0UL // 90 2:14A input
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#define VEPP_gpio51_dir 0UL // 91 2:13C mode !8
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#define VEPP_gpio52_dir 0UL // 94 2:13B input
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#define VEPP_gpio53_dir 0UL // 95 2:13A input
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#define VEPP_gpio58_dir 0UL // 100 1:13C input
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#define VEPP_gpio59_dir 0UL
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#define VEPP_gpio60_dir 1UL // 111 1:13A gotov
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#define VEPP_gpio61_dir 0UL // 112 1:14C input
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#define VEPP_gpio62_dir 1UL // 113 1:14C rezout
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#define VEPP_gpio63_dir 1UL // 114 1:14A ledjob
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//===========================================================================
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#define ISOL_gpio00_dir 0UL // 5 2:7A
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#define ISOL_gpio01_dir 0UL // 6 2:4A
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#define ISOL_gpio02_dir 0UL // 7 2:7B
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#define ISOL_gpio03_dir 0UL // 10 2:4B
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#define ISOL_gpio04_dir 0UL // 11 2:7C
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#define ISOL_gpio05_dir 0UL // 12 2:4C
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#define ISOL_gpio06_dir 0UL // 13 2:6A
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#define ISOL_gpio07_dir 0UL // 16 2:3A
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#define ISOL_gpio08_dir 0UL // 17 2:6B
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#define ISOL_gpio09_dir 0UL // 18 2:3B
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#define ISOL_gpio10_dir 0UL // 19 2:6C
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#define ISOL_gpio11_dir 0UL // 20 2:3C
|
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|
||||
#define ISOL_gpio19_dir 1UL // 63 — SPI
|
||||
#define ISOL_gpio20_dir 0UL // 64 2:9B mode 2
|
||||
#define ISOL_gpio21_dir 0UL // 65 2:9A mode 4
|
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#define ISOL_gpio22_dir 0UL // 66 2:12C mode 1
|
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#define ISOL_gpio23_dir 0UL // 67 2:12B opt input 1
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#define ISOL_gpio24_dir 1UL // 68 2:12A led 2
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#define ISOL_gpio25_dir 0UL // 69 2:11C
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#define ISOL_gpio26_dir 1UL // 72 2:11B opt out 2
|
||||
#define ISOL_gpio27_dir 1UL // 73 2:11A led 1
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||||
|
||||
#define ISOL_gpio32_dir 1UL // 74 2:10B opt out 1
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||||
#define ISOL_gpio33_dir 0UL // 75 2:10C
|
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#define ISOL_gpio34_dir 1UL // 142 — SCI
|
||||
|
||||
#define ISOL_gpio48_dir 1UL // 88 2:14C DIOD red
|
||||
#define ISOL_gpio49_dir 0UL // 89 2:14B
|
||||
#define ISOL_gpio50_dir 0UL // 90 2:14A
|
||||
#define ISOL_gpio51_dir 0UL // 91 2:13C mode !8
|
||||
#define ISOL_gpio52_dir 0UL // 94 2:13B opt input 2
|
||||
#define ISOL_gpio53_dir 1UL // 95 2:13A led 3
|
||||
|
||||
#define ISOL_gpio58_dir 0UL // 100 1:13C
|
||||
#define ISOL_gpio59_dir 1UL // 110 1:13B gotov
|
||||
#define ISOL_gpio60_dir 0UL // 111 1:13A
|
||||
#define ISOL_gpio61_dir 0UL // 112 1:14C
|
||||
#define ISOL_gpio62_dir 0UL // 113 1:14C input
|
||||
#define ISOL_gpio63_dir 0UL // 114 1:14A
|
||||
|
||||
//===========================================================================
|
||||
|
||||
//===========================================================================
|
||||
|
||||
#define COMM_GPADIR (COMM_gpio00_dir ) + (COMM_gpio01_dir<<1) + (COMM_gpio02_dir<<2) + (COMM_gpio03_dir<<3) + \
|
||||
(COMM_gpio04_dir<<4) + (COMM_gpio05_dir<<5) + (COMM_gpio06_dir<<6) + (COMM_gpio07_dir<<7) + \
|
||||
(COMM_gpio08_dir<<8) + (COMM_gpio09_dir<<9) + (COMM_gpio10_dir<<10)+ (COMM_gpio11_dir<<11)+ \
|
||||
(COMM_gpio19_dir<<19)+ \
|
||||
(COMM_gpio20_dir<<20)+ (COMM_gpio21_dir<<21)+ (COMM_gpio22_dir<<22)+ (COMM_gpio23_dir<<23)+ \
|
||||
(COMM_gpio24_dir<<24)+ (COMM_gpio25_dir<<25)+ (COMM_gpio26_dir<<26)+ (COMM_gpio27_dir<<27);
|
||||
#define COMM_GPBDIR (COMM_gpio32_dir )+ (COMM_gpio33_dir<<1) + (COMM_gpio34_dir<<2 )+ \
|
||||
(COMM_gpio48_dir<<16)+ (COMM_gpio49_dir<<17)+ (COMM_gpio50_dir<<18)+ (COMM_gpio51_dir<<19)+ \
|
||||
(COMM_gpio52_dir<<20)+ (COMM_gpio53_dir<<21)+ \
|
||||
(COMM_gpio58_dir<<26)+ (COMM_gpio59_dir<<27)+ \
|
||||
(COMM_gpio60_dir<<28)+ (COMM_gpio61_dir<<29)+ (COMM_gpio62_dir<<30)+ (COMM_gpio63_dir<<31);
|
||||
|
||||
#define BKSD_GPADIR (BKSD_gpio00_dir ) + (BKSD_gpio01_dir<<1) + (BKSD_gpio02_dir<<2) + (BKSD_gpio03_dir<<3) + \
|
||||
(BKSD_gpio04_dir<<4) + (BKSD_gpio05_dir<<5) + (BKSD_gpio06_dir<<6) + (BKSD_gpio07_dir<<7) + \
|
||||
(BKSD_gpio08_dir<<8) + (BKSD_gpio09_dir<<9) + (BKSD_gpio10_dir<<10)+ (BKSD_gpio11_dir<<11)+ \
|
||||
(BKSD_gpio19_dir<<19)+ \
|
||||
(BKSD_gpio20_dir<<20)+ (BKSD_gpio21_dir<<21)+ (BKSD_gpio22_dir<<22)+ (BKSD_gpio23_dir<<23)+ \
|
||||
(BKSD_gpio24_dir<<24)+ (BKSD_gpio25_dir<<25)+ (BKSD_gpio26_dir<<26)+ (BKSD_gpio27_dir<<27);
|
||||
#define BKSD_GPBDIR (BKSD_gpio32_dir )+ (BKSD_gpio33_dir<<1) + (BKSD_gpio34_dir<<2 )+ \
|
||||
(BKSD_gpio48_dir<<16)+ (BKSD_gpio49_dir<<17)+ (BKSD_gpio50_dir<<18)+ (BKSD_gpio51_dir<<19)+ \
|
||||
(BKSD_gpio52_dir<<20)+ (BKSD_gpio53_dir<<21)+ \
|
||||
(BKSD_gpio58_dir<<26)+ (BKSD_gpio59_dir<<27)+ \
|
||||
(BKSD_gpio60_dir<<28)+ (BKSD_gpio61_dir<<29)+ (BKSD_gpio62_dir<<30)+ (BKSD_gpio63_dir<<31);
|
||||
|
||||
#define PULT_GPADIR (PULT_gpio00_dir ) + (PULT_gpio01_dir<<1) + (PULT_gpio02_dir<<2) + (PULT_gpio03_dir<<3) + \
|
||||
(PULT_gpio04_dir<<4) + (PULT_gpio05_dir<<5) + (PULT_gpio06_dir<<6) + (PULT_gpio07_dir<<7) + \
|
||||
(PULT_gpio08_dir<<8) + (PULT_gpio09_dir<<9) + (PULT_gpio10_dir<<10)+ (PULT_gpio11_dir<<11)+ \
|
||||
(PULT_gpio19_dir<<19)+ \
|
||||
(PULT_gpio20_dir<<20)+ (PULT_gpio21_dir<<21)+ (PULT_gpio22_dir<<22)+ (PULT_gpio23_dir<<23)+ \
|
||||
(PULT_gpio24_dir<<24)+ (PULT_gpio25_dir<<25)+ (PULT_gpio26_dir<<26)+ (PULT_gpio27_dir<<27);
|
||||
#define PULT_GPBDIR (PULT_gpio32_dir )+ (PULT_gpio33_dir<<1) + (PULT_gpio34_dir<<2 )+ \
|
||||
(PULT_gpio48_dir<<16)+ (PULT_gpio49_dir<<17)+ (PULT_gpio50_dir<<18)+ (PULT_gpio51_dir<<19)+ \
|
||||
(PULT_gpio52_dir<<20)+ (PULT_gpio53_dir<<21)+ \
|
||||
(PULT_gpio58_dir<<26)+ (PULT_gpio59_dir<<27)+ \
|
||||
(PULT_gpio60_dir<<28)+ (PULT_gpio61_dir<<29)+ (PULT_gpio62_dir<<30)+ (PULT_gpio63_dir<<31);
|
||||
|
||||
#define VEPP_GPADIR (VEPP_gpio00_dir ) + (VEPP_gpio01_dir<<1) + (VEPP_gpio02_dir<<2) + (VEPP_gpio03_dir<<3) + \
|
||||
(VEPP_gpio04_dir<<4) + (VEPP_gpio05_dir<<5) + (VEPP_gpio06_dir<<6) + (VEPP_gpio07_dir<<7) + \
|
||||
(VEPP_gpio08_dir<<8) + (VEPP_gpio09_dir<<9) + (VEPP_gpio10_dir<<10)+ (VEPP_gpio11_dir<<11)+ \
|
||||
(VEPP_gpio19_dir<<19)+ \
|
||||
(VEPP_gpio20_dir<<20)+ (VEPP_gpio21_dir<<21)+ (VEPP_gpio22_dir<<22)+ (VEPP_gpio23_dir<<23)+ \
|
||||
(VEPP_gpio24_dir<<24)+ (VEPP_gpio25_dir<<25)+ (VEPP_gpio26_dir<<26)+ (VEPP_gpio27_dir<<27);
|
||||
#define VEPP_GPBDIR (VEPP_gpio32_dir )+ (VEPP_gpio33_dir<<1) + (VEPP_gpio34_dir<<2 )+ \
|
||||
(VEPP_gpio48_dir<<16)+ (VEPP_gpio49_dir<<17)+ (VEPP_gpio50_dir<<18)+ (VEPP_gpio51_dir<<19)+ \
|
||||
(VEPP_gpio52_dir<<20)+ (VEPP_gpio53_dir<<21)+ \
|
||||
(VEPP_gpio58_dir<<26)+ (VEPP_gpio59_dir<<27)+ \
|
||||
(VEPP_gpio60_dir<<28)+ (VEPP_gpio61_dir<<29)+ (VEPP_gpio62_dir<<30)+ (VEPP_gpio63_dir<<31);
|
||||
|
||||
#define ISOL_GPADIR (ISOL_gpio00_dir ) + (ISOL_gpio01_dir<<1) + (ISOL_gpio02_dir<<2) + (ISOL_gpio03_dir<<3) + \
|
||||
(ISOL_gpio04_dir<<4) + (ISOL_gpio05_dir<<5) + (ISOL_gpio06_dir<<6) + (ISOL_gpio07_dir<<7) + \
|
||||
(ISOL_gpio08_dir<<8) + (ISOL_gpio09_dir<<9) + (ISOL_gpio10_dir<<10)+ (ISOL_gpio11_dir<<11)+ \
|
||||
(ISOL_gpio19_dir<<19)+ \
|
||||
(ISOL_gpio20_dir<<20)+ (ISOL_gpio21_dir<<21)+ (ISOL_gpio22_dir<<22)+ (ISOL_gpio23_dir<<23)+ \
|
||||
(ISOL_gpio24_dir<<24)+ (ISOL_gpio25_dir<<25)+ (ISOL_gpio26_dir<<26)+ (ISOL_gpio27_dir<<27);
|
||||
#define ISOL_GPBDIR (ISOL_gpio32_dir )+ (ISOL_gpio33_dir<<1) + (ISOL_gpio34_dir<<2 )+ \
|
||||
(ISOL_gpio48_dir<<16)+ (ISOL_gpio49_dir<<17)+ (ISOL_gpio50_dir<<18)+ (ISOL_gpio51_dir<<19)+ \
|
||||
(ISOL_gpio52_dir<<20)+ (ISOL_gpio53_dir<<21)+ \
|
||||
(ISOL_gpio58_dir<<26)+ (ISOL_gpio59_dir<<27)+ \
|
||||
(ISOL_gpio60_dir<<28)+ (ISOL_gpio61_dir<<29)+ (ISOL_gpio62_dir<<30)+ (ISOL_gpio63_dir<<31);
|
||||
|
||||
//===========================================================================
|
||||
// No more.
|
||||
//===========================================================================
|
||||
553
RS485.c
Normal file
553
RS485.c
Normal file
@@ -0,0 +1,553 @@
|
||||
/****************************************************************/
|
||||
/* TMS320C32 */
|
||||
/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */
|
||||
/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2000 ã. */
|
||||
/****************************************************************
|
||||
RS485.ñ
|
||||
****************************************************************
|
||||
* Ïðîöåäóðû ðàáîòû ñ UART *
|
||||
****************************************************************/
|
||||
|
||||
//#include "big_dsp_module.h"
|
||||
|
||||
|
||||
#include "DSP2833x_Device.h"
|
||||
#include "DSP2833x_SWPrioritizedIsrLevels.h"
|
||||
|
||||
#include "RS485.h"
|
||||
#include "bios_dsp.h"
|
||||
#include "cntrl_adr.h"
|
||||
|
||||
#include "tools.h"
|
||||
|
||||
//#include "flash_tools.h"
|
||||
|
||||
|
||||
RS_DATA rs_a,rs_b;
|
||||
|
||||
unsigned int RS_Len[70]={0};
|
||||
|
||||
static char size_cmd15=1;
|
||||
|
||||
void RS_RX_Handler(RS_DATA *rs_arr);
|
||||
void RS_TX_Handler(RS_DATA *rs_arr);
|
||||
|
||||
/** Îáðàáîò÷èê ïðåðûâàíèé UART - ïðèíàòî */
|
||||
interrupt void RSA_RX_Handler(void)
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG91; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
clear_timer_rs_live(&rs_a);
|
||||
RS_RX_Handler(&rs_a);
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
}
|
||||
|
||||
interrupt void RSB_RX_Handler(void)
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG93; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
clear_timer_rs_live(&rs_b);
|
||||
RS_RX_Handler(&rs_b);
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
}
|
||||
|
||||
interrupt void RSA_TX_Handler(void)
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG92; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
clear_timer_rs_live(&rs_a);
|
||||
RS_TX_Handler(&rs_a);
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
}
|
||||
|
||||
interrupt void RSB_TX_Handler(void)
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG94; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
clear_timer_rs_live(&rs_b);
|
||||
RS_TX_Handler(&rs_b);
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
}
|
||||
|
||||
/** Îáðàáîò÷èê ïðåðûâàíèé UART - ïðèíàòî */
|
||||
void RS_RX_Handler(RS_DATA *rs_arr)
|
||||
{
|
||||
char Rc;
|
||||
char RS_BytePtr;
|
||||
|
||||
// led1_on();
|
||||
|
||||
for(;;) // 'goto' ýòî íå îïåðàòîð àçûêà Ñ
|
||||
{
|
||||
if(!rs_arr->SciRegs->SCIRXST.bit.RXRDY) // Receiver ready flag
|
||||
{
|
||||
PieCtrlRegs.PIEACK.bit.ACK9 |= 1;
|
||||
rs_arr->SciRegs->SCIFFRX.bit.RXFFINTCLR=1; // Clear INT flag
|
||||
return; // êñòàòè ýòî åäèíñòâåííûé âûõîä èç ïðåðûâàíèà
|
||||
}
|
||||
|
||||
Rc = rs_arr->SciRegs->SCIRXBUF.bit.RXDT; // ×èòàåì ñèìâîë â ëþáîì ñëó÷àå
|
||||
|
||||
if(rs_arr->SciRegs->SCIRXST.bit.RXERROR) // Receiver error flag
|
||||
{
|
||||
rs_arr->SciRegs->SCICTL1.bit.SWRESET=0; // Reset SCI
|
||||
rs_arr->SciRegs->SCICTL1.bit.SWRESET=1; // Relinquish SCI from Reset
|
||||
|
||||
continue;
|
||||
}
|
||||
|
||||
if(rs_arr->RS_DataReady) continue; // Íå çàáðàëè äàííûå
|
||||
|
||||
if (rs_arr->RS_Flag9bit==1) // äëà RS485????????
|
||||
{
|
||||
// Èíèöèàëèçèðóåì ïåðåìåííûå è ôëàãè
|
||||
rs_arr->RS_FlagBegin = true; // Æäåì çàãîëîâîê
|
||||
rs_arr->RS_RecvLen = 0;
|
||||
rs_arr->RS_FlagSkiping = false;
|
||||
rs_arr->RS_HeaderCnt = 0;
|
||||
rs_arr->RS_Cmd = 0;
|
||||
}
|
||||
|
||||
if(rs_arr->RS_FlagSkiping) continue; // Íå íàì
|
||||
|
||||
if (rs_arr->RS_FlagBegin) // Çàãîëîâîê
|
||||
{
|
||||
if (rs_arr->RS_HeaderCnt==0) // Àäðåñ êîíòðîëëåðà èëè ñòàíäàðòíàà êîìàíäà
|
||||
{
|
||||
if( (Rc == CNTRL_ADDR_UNIVERSAL) || (Rc == CNTRL_ADDR && CNTRL_ADDR!=0) || ((Rc == rs_arr->addr_answer) && rs_arr->flag_LEADING)
|
||||
|| ((Rc == ADDR_FOR_ALL && ADDR_FOR_ALL!=0) && !rs_arr->flag_LEADING))
|
||||
|
||||
{
|
||||
rs_arr->addr_recive=Rc; // çàïîìíèëè àäðåñ ïî êîòîðîìó íàñ çàïðîñèëè
|
||||
rs_arr->RS_Header[rs_arr->RS_HeaderCnt++] = Rc; // Ïåðâûé áàéò
|
||||
RS_SetBitMode(rs_arr,8); // ïåðåñòðîèëèñü â 8-áèò ðåæèì
|
||||
}
|
||||
else
|
||||
{
|
||||
rs_arr->RS_FlagSkiping = true; // Íå íàøåìó êîíòðîëëåðó
|
||||
rs_arr->RS_FlagBegin = false; // îñòàëèñü â 9-áèò ðåæèìå
|
||||
// led1_off();
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
rs_arr->RS_Header[rs_arr->RS_HeaderCnt++] = Rc; // Âòîðîé áàéò è ò.ä.
|
||||
|
||||
if (rs_arr->RS_HeaderCnt == 7 && rs_arr->RS_Cmd==CMD_MODBUS_16 && !rs_arr->flag_LEADING)
|
||||
{
|
||||
RS_Len[CMD_MODBUS_16] = (10+Rc);
|
||||
}
|
||||
|
||||
// åñëè âòîðîé áàéò - ýòî êîìàíäà
|
||||
if (rs_arr->RS_HeaderCnt == 2)
|
||||
{
|
||||
rs_arr->RS_Cmd = Rc;
|
||||
// Ïðîâåðêà äëèíû ïîñûëêè
|
||||
// CMD_LOAD - ìëàäøàà íà äàííûé ìîìåíò
|
||||
// CMD_STD_ANS - ñòàðøàà íà äàííûé ìîìåíò
|
||||
if ((rs_arr->RS_Cmd < CMD_MODBUS_3) || (rs_arr->RS_Cmd > CMD_STD_ANS) || (RS_Len[rs_arr->RS_Cmd]<3)
|
||||
|| ((rs_arr->RS_Cmd == CMD_LOAD)&&(rs_arr->RS_PrevCmd != CMD_INITLOAD))
|
||||
)
|
||||
{
|
||||
RS_SetBitMode(rs_arr,9); // Ïîëó÷èëè âñå ïåðåñòðîèëèñü â 9-áèò äëà RS485?
|
||||
rs_arr->RS_HeaderCnt = 0; // Ïîòîìó ÷òî êîìàíäà íå òà
|
||||
rs_arr->RS_FlagBegin = true;
|
||||
rs_arr->RS_FlagSkiping = false;
|
||||
rs_arr->RS_Cmd=0;
|
||||
// led1_off();
|
||||
continue;
|
||||
}
|
||||
if (rs_arr->RS_Cmd == CMD_LOAD) // Äëà ýòîé êîìàíäû çàãîëîâîê î÷åíü êîðîòêèé
|
||||
rs_arr->RS_FlagBegin = false;// äàëüøå èäóò äàííûå
|
||||
}
|
||||
|
||||
if( (rs_arr->RS_HeaderCnt >= RS_Len[rs_arr->RS_Cmd]) ||
|
||||
(rs_arr->RS_HeaderCnt >= sizeof(rs_arr->RS_Header)))
|
||||
{ // Ïîëó÷èëè çàãîëîâîê
|
||||
RS_SetBitMode(rs_arr,9); // Ïîëó÷èëè âñå ïåðåñòðîèëèñü â 9-áèò äëà RS485?
|
||||
rs_arr->RS_FlagBegin = false;
|
||||
rs_arr->RS_FlagSkiping = true;
|
||||
rs_arr->RS_DataReady = true;
|
||||
rs_arr->RS_Cmd=0;
|
||||
// led1_off();
|
||||
} } }
|
||||
else // Ïîòîê äàííûõ
|
||||
{
|
||||
if(rs_arr->pRS_RecvPtr<(unsigned int *)Rec_Bloc_Begin || rs_arr->pRS_RecvPtr>(unsigned int *)Rec_Bloc_End)
|
||||
{
|
||||
rs_arr->pRS_RecvPtr = (unsigned int *)Rec_Bloc_Begin; // Íà ïðîãðàììó íàäåéñà, à ñàì íå ïëîøàé
|
||||
rs_arr->pRecvPtr = (unsigned int *)Rec_Bloc_Begin; // Íà ïðîãðàììó íàäåéñà, à ñàì íå ïëîøàé
|
||||
}
|
||||
if(rs_arr->RS_PrevCmd != CMD_INITLOAD) continue; // Ìû çäåñü îêàçàëèñü ïî êàêîé-òî ÷óäîâèùíîé îøèáêå
|
||||
|
||||
if(rs_arr->RS_DataReady) // Åñëè äàííûå â îñíîâíîì öèêëå íå çàáðàíû,
|
||||
{ // òî ïðîïóñêàåì ñëåäóþùóþ ïîñûëêó
|
||||
rs_arr->RS_FlagSkiping = true; // Èãíîðèðóåì äî ñëåäóþùåãî çàãîëîâêà
|
||||
// led1_off();
|
||||
continue;
|
||||
}
|
||||
RS_BytePtr = rs_arr->RS_RecvLen++ % 2;
|
||||
if(RS_BytePtr) *rs_arr->pRS_RecvPtr++ |= Rc; // Ïîëó÷èëè ñëîâî
|
||||
else *rs_arr->pRS_RecvPtr = Rc<<8;
|
||||
|
||||
if(rs_arr->RS_Length <= rs_arr->RS_RecvLen) // Êîíåö ïîñûëêè
|
||||
{
|
||||
rs_arr->RS_PrevCmd = rs_arr->RS_Header[1] = CMD_LOAD;
|
||||
RS_SetBitMode(rs_arr,9); // Ïîëó÷èëè âñå äàííûå ïåðåñòðîèëèñü â 9-áèò äëà RS485?
|
||||
rs_arr->RS_FlagSkiping = true; // Èãíîðèðóåì äî ñëåäóþùåãî çàãîëîâêà
|
||||
rs_arr->RS_DataReady = true; // Ôëàã â îñíîâíîé öèêë - äàííûå ïîëó÷åíû
|
||||
// led1_off();
|
||||
} } } }
|
||||
|
||||
/** Îáðàáîò÷èê ïðåðûâàíèé UART - ïîñëàíî */
|
||||
void RS_TX_Handler(RS_DATA *rs_arr)
|
||||
{
|
||||
char RS_BytePtr;
|
||||
// unsigned int i;
|
||||
|
||||
if(rs_arr->RS_SendBlockMode == BM_CHAR32)
|
||||
{
|
||||
if(++rs_arr->RS_SendLen >= rs_arr->RS_SLength)
|
||||
{
|
||||
enableUARTInt(rs_arr); /* Çàïðåùàåì ïðåðûâàíèà ïî ïåðåäà÷å */
|
||||
}
|
||||
SCI_send(rs_arr,*(rs_arr->pRS_SendPtr++));
|
||||
|
||||
if(rs_arr->RS_SendLen >= rs_arr->RS_SLength)
|
||||
{
|
||||
RS_Wait4OK(rs_arr);
|
||||
// for (i=0; i <= TIME_WAIT_RS_BYTE_OUT; i++){} /* Ïàóçà äëà PC */
|
||||
|
||||
RS_SetBitMode(rs_arr,9); /* Ïåðåäàëè âñå ïåðåñòðîèëèñü â 9-áèò äëà RS485?*/
|
||||
RS_Line_to_receive(rs_arr); /* ðåæèì ïðèåìà RS485 */
|
||||
|
||||
rs_arr->flag_TIMEOUT_to_Send=false; /* ñáðîñèëè ôëàã îæèäàíèà òàéìàóòà */
|
||||
}
|
||||
}
|
||||
else /* BM_PACKED */
|
||||
{
|
||||
|
||||
RS_BytePtr = (rs_arr->RS_SendLen++) % 2;
|
||||
if(rs_arr->RS_SendLen >= rs_arr->RS_SLength)
|
||||
{
|
||||
enableUARTInt(rs_arr); /* Çàïðåùàåì ïðåðûâàíèà ïî ïåðåäà÷å */
|
||||
}
|
||||
if(RS_BytePtr) SCI_send(rs_arr, LOBYTE( *(rs_arr->pRS_SendPtr++) ));
|
||||
else SCI_send(rs_arr, HIBYTE( *rs_arr->pRS_SendPtr ));
|
||||
|
||||
if(rs_arr->RS_SendLen >= rs_arr->RS_SLength)
|
||||
{
|
||||
RS_Wait4OK(rs_arr);
|
||||
// for (i=0; i <= TIME_WAIT_RS_BYTE_OUT; i++){} /* Ïàóçà äëà PC */
|
||||
// RS_SetBitMode(rs_arr,9); /* Ïåðåäàëè âñå ïåðåñòðîèëèñü â 9-áèò äëà RS485?*/
|
||||
// RS_Line_to_receive(); /* ðåæèì ïðèåìà RS485 */
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
PieCtrlRegs.PIEACK.bit.ACK9 |= 1;
|
||||
// rs_arr->SciRegs->SCIFFTX.bit.TXINTCLR=1; // Clear INT flag
|
||||
}
|
||||
|
||||
/** Èíèöèàëèçàöèà ìàññèâà äëèí êîìàíä */
|
||||
void setup_arr_cmd_length()
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i=0;i<70;i++) RS_Len[i]=i;
|
||||
|
||||
RS_Len[CMD_LOAD] = 12;
|
||||
RS_Len[CMD_UPLOAD] = 12;
|
||||
RS_Len[CMD_RUN] = 8;
|
||||
RS_Len[CMD_XFLASH] = 9;
|
||||
RS_Len[CMD_TFLASH] = 16;
|
||||
RS_Len[CMD_PEEK] = 8;
|
||||
RS_Len[CMD_POKE] = 12;
|
||||
RS_Len[CMD_INITLOAD] = 12;
|
||||
RS_Len[CMD_INIT] = 5;
|
||||
RS_Len[CMD_VECTOR] = size_cmd15-2; //sizeof(CMD_TO_TMS)-2;
|
||||
RS_Len[CMD_STD] = size_cmd15-1; //sizeof(CMD_TO_TMS)-1;
|
||||
RS_Len[CMD_IMPULSE] = 8;
|
||||
RS_Len[CMD_MODBUS_3] = 8;
|
||||
RS_Len[CMD_MODBUS_6] = 8;
|
||||
RS_Len[CMD_MODBUS_16] = 13;
|
||||
RS_Len[CMD_MODBUS_15] = 27;
|
||||
RS_Len[CMD_EXTEND] = 18;
|
||||
}
|
||||
|
||||
/** Íàñòðîéêà ðåæèìà ïðèåìà/ïåðåäà÷è */
|
||||
void RS_SetBitMode(RS_DATA *rs_arr,int n)
|
||||
{
|
||||
if(n == 8)
|
||||
{
|
||||
RS_SetLineMode(rs_arr,8,'N',1); /* ðåæèì ëèíèè */
|
||||
rs_arr->RS_Flag9bit=0;
|
||||
}
|
||||
if(n == 9)
|
||||
{
|
||||
RS_SetLineMode(rs_arr,8,'N',1); /* ðåæèì ëèíèè */
|
||||
rs_arr->RS_Flag9bit=1;
|
||||
} }
|
||||
|
||||
/** Ïîñûëêà áëîêà áàéòîâ.
|
||||
Ïîñûëàåò ìàññèâà 32-áèòíûõ öåëûõ ÷èñåë ñòàðøèå áèòû äîëæíû áûòü 0.
|
||||
@precondition Ðàáîòà ô-öèè çàâèñèò îò ìàêðî RS_TRANSMIT_INTR
|
||||
@param buf àäðåñ ìàññèâà
|
||||
@param len êîëè÷åñòâî áàéò
|
||||
@see RS_BSend, RS_TRANSMIT_INTR */
|
||||
int RS_Send(RS_DATA *rs_arr,unsigned int *pBuf,unsigned long len)
|
||||
{
|
||||
unsigned int i;
|
||||
for (i=0; i <= 30000; i++){} /* Ïàóçà äëà PC */
|
||||
|
||||
RS_Line_to_send(rs_arr); /* ðåæèì ïåðåäà÷è RS485 */
|
||||
|
||||
for (i=0; i <= 10000; i++){} /* Ïàóçà äëà PC */
|
||||
|
||||
rs_arr->RS_SLength = len; /* Íàñòðàèâàåì ïåðåìåííûå */
|
||||
rs_arr->pRS_SendPtr = pBuf + 1;
|
||||
|
||||
rs_arr->RS_SendBlockMode = BM_CHAR32;
|
||||
|
||||
RS_Wait4OK(rs_arr); /* Äîæèäàåìñà óõîäà */
|
||||
RS_SetBitMode(rs_arr,8); /* Îñòàëüíûå â 8-áèò ðåæèìå */
|
||||
|
||||
rs_arr->RS_SendLen = 1; /* Äâà áàéòà óæå ïåðåäàëè */
|
||||
if(len > 1)
|
||||
{
|
||||
enableUARTIntW(rs_arr); /* Ðàçðåøàåì ïðåðûâàíèà ïî ïåðåäà÷å */
|
||||
SCI_send(rs_arr, *pBuf); // Ïåðåäàåì âòîðîé áàéò ïî ïðåðûâàíèþ
|
||||
}
|
||||
else
|
||||
{
|
||||
SCI_send(rs_arr, *pBuf); // Ïåðåäàåì âòîðîé áàéò ïî ïðåðûâàíèþ
|
||||
RS_Wait4OK(rs_arr); /* Äîæèäàåìñà óõîäà áåç ïðåðûâàíèà */
|
||||
for (i=0; i <= TIME_WAIT_RS_BYTE_OUT; i++){} /* Ïàóçà äëà PC */
|
||||
RS_SetBitMode(rs_arr,9); /* Îáðàòíî â 9-áèò ðåæèì */
|
||||
RS_Line_to_receive(rs_arr); /* ðåæèì ïðèåìà RS485 */
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
// Ïîñûëêà áëîêà óïàêîâàííûõ áàéòîâ
|
||||
int RS_BSend(RS_DATA *rs_arr,unsigned int *pBuf, unsigned long len)
|
||||
{
|
||||
|
||||
RS_Line_to_send(rs_arr); // ðåæèì ïåðåäà÷è RS485
|
||||
|
||||
rs_arr->RS_SLength = len; // Íàñòðàèâàåì ïåðåìåííûå
|
||||
rs_arr->pRS_SendPtr = pBuf;
|
||||
rs_arr->RS_SendBlockMode = BM_PACKED;
|
||||
|
||||
RS_Wait4OK(rs_arr); // Îæèäàåì î÷èñòêè è óõîäà ïîñëåäíåãî áàéòà
|
||||
RS_SetBitMode(rs_arr,8); /* Îñòàëüíûå â 8-áèò ðåæèìå */
|
||||
|
||||
rs_arr->RS_SendLen = 1; // Îäèí áàéò óæå ïåðåäàëè
|
||||
|
||||
enableUARTIntW(rs_arr); /* Ðàçðåøàåì ïðåðûâàíèà ïî ïåðåäà÷å */
|
||||
|
||||
SCI_send(rs_arr,HIBYTE(*pBuf));// Ïåðåäàåì ïåðâûé áàéò
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/** Óñòàíàâëèâàåò ñêîðîñòü îáìåíà.
|
||||
@param speed ñêîðîñòü RS â áîä */
|
||||
/** Óñòàíàâëèâàåò ñêîðîñòü îáìåíà.
|
||||
@param speed ñêîðîñòü RS â áîä */
|
||||
void RS_SetLineSpeed(RS_DATA *rs_arr,unsigned long speed)
|
||||
{
|
||||
long SciBaud;
|
||||
|
||||
SciBaud = LSPCLK/(speed*8.0);
|
||||
|
||||
// if((SciBaud-(unsigned int)SciBaud)>0.5) SciBaud++;
|
||||
|
||||
rs_arr->SciRegs->SCIHBAUD = HIBYTE((int)SciBaud);
|
||||
rs_arr->SciRegs->SCILBAUD = LOBYTE((int)SciBaud);
|
||||
}
|
||||
|
||||
|
||||
/** Èíèöèàëèçàöèà ïîñëåäîâàòåëüíîãî ïîðòà */
|
||||
void create_uart_vars(char size_cmd15_set)
|
||||
{
|
||||
size_cmd15=size_cmd15_set;
|
||||
rs_a.commnumber=COM_1;
|
||||
rs_b.commnumber=COM_2;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/** Èíèöèàëèçàöèà ïîñëåäîâàòåëüíîãî ïîðòà */
|
||||
|
||||
void setup_uart(char commnumber, unsigned long speed_baud)
|
||||
{
|
||||
volatile struct SCI_REGS *SciRegs;
|
||||
RS_DATA *rs_arr;
|
||||
|
||||
if(commnumber==COM_1)
|
||||
{
|
||||
rs_a.SciRegs = &SciaRegs;
|
||||
rs_arr = &rs_a;
|
||||
|
||||
EALLOW;
|
||||
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // SCITXDA - SCI-A transmit(O)
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // SCIRXDA - SCI-A receive (I)
|
||||
|
||||
PieVectTable.SCIRXINTA = &RSA_RX_Handler;
|
||||
PieVectTable.SCITXINTA = &RSA_TX_Handler;
|
||||
PieCtrlRegs.PIEIER9.bit.INTx1=1; // PIE Group 9, INT1
|
||||
PieCtrlRegs.PIEIER9.bit.INTx2=1; // PIE Group 9, INT2
|
||||
IER |= M_INT9; // Enable CPU INT
|
||||
EDIS;
|
||||
}
|
||||
|
||||
if(commnumber==COM_2)
|
||||
{
|
||||
rs_b.SciRegs = &ScibRegs;
|
||||
rs_arr = &rs_b;
|
||||
|
||||
EALLOW;
|
||||
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 2; // SCITXDB - SCI-B transmit(O)
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 2; // SCIRXDB - SCI-B receive (I)
|
||||
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0; // GPIO 34 - general purpose I/O 34 (default)
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1; // Configures the GPIO pin as an output
|
||||
|
||||
PieVectTable.SCIRXINTB = &RSB_RX_Handler;
|
||||
PieVectTable.SCITXINTB = &RSB_TX_Handler;
|
||||
|
||||
PieCtrlRegs.PIEIER9.bit.INTx3=1; // PIE Group 9, INT3
|
||||
PieCtrlRegs.PIEIER9.bit.INTx4=1; // PIE Group 9, INT4
|
||||
IER |= M_INT9; // Enable CPU INT
|
||||
EDIS;
|
||||
}
|
||||
|
||||
rs_arr->commnumber = commnumber;
|
||||
SciRegs = rs_arr->SciRegs;
|
||||
RS_SetLineMode(rs_arr,8,'N',1);
|
||||
|
||||
// enable TX, RX, internal SCICLK,
|
||||
// Disable RX ERR, SLEEP, TXWAKE
|
||||
|
||||
SciRegs->SCIFFCT.bit.ABDCLR=1;
|
||||
SciRegs->SCIFFCT.bit.CDC=0;
|
||||
|
||||
SciRegs->SCICTL1.bit.RXERRINTENA=0;
|
||||
SciRegs->SCICTL1.bit.SWRESET=0;
|
||||
SciRegs->SCICTL1.bit.TXWAKE=0;
|
||||
SciRegs->SCICTL1.bit.SLEEP=0;
|
||||
SciRegs->SCICTL1.bit.TXENA=1;
|
||||
SciRegs->SCICTL1.bit.RXENA=1;
|
||||
|
||||
SciRegs->SCIFFTX.bit.SCIFFENA=0; // fifo off
|
||||
SciRegs->SCIFFRX.bit.RXFFIL=1; // Äëèíà íàèìåíüøåé êîìàíäû
|
||||
|
||||
setup_arr_cmd_length();
|
||||
RS_SetLineSpeed(rs_arr,speed_baud); // ñêîðîñòü ëèíèè
|
||||
RS_Line_to_receive(rs_arr); // ðåæèì ïðèåìà RS485
|
||||
enableUARTInt(rs_arr); // ðàçðåøåíèå ïðåðûâàíèé UART
|
||||
RS_SetBitMode(rs_arr,9);
|
||||
rs_arr->RS_PrevCmd = 0; // íå áûëî íèêàêèõ êîìàíä
|
||||
rs_arr->flag_TIMEOUT_to_Send = 0;
|
||||
rs_arr->flag_LEADING = 0;
|
||||
|
||||
SciRegs->SCIFFRX.bit.RXFFINTCLR=1; // Clear INT flag
|
||||
SciRegs->SCICTL1.bit.SWRESET=1; // Relinquish SCI from Reset
|
||||
}
|
||||
|
||||
/** Íàñòðîéêà ðåæèìà ëèíèè.
|
||||
@param bit êîëè÷åñòâî áèò äàííûõ
|
||||
@param parity ðåæèì ÷åòíîñòè (N,O,E,M,S)
|
||||
@param stop êîëè÷åñòâî ñòîïîâûõ áèò */
|
||||
void RS_SetLineMode(RS_DATA *rs_arr, int bit, char parity, int stop)
|
||||
{
|
||||
volatile struct SCI_REGS *SciRegs;
|
||||
/*
|
||||
SCICCR - SCI Communication Control Register
|
||||
Bit Bit Name Designation Functions
|
||||
2-0 SCI CHAR2-0 SCICHAR Select the character (data) length (one to eight bits).
|
||||
3 ADDR/IDLE MODE ADDRIDLE_MODE The idle-line mode (0) is usually used for normal communications because the address-bit mode adds an extra bit to the frame. The idle-line mode does not add this extra bit and is compatible with RS-232 type communications.
|
||||
4 LOOP BACK ENABLE LOOPBKENA This bit enables (1) the Loop Back test mode where the Tx pin is internally connected to the Rx pin.
|
||||
5 PARITY ENABLE PARITYENA Enables the parity function if set to 1, or disables the parity function if cleared to 0.
|
||||
6 EVEN/ODD PARITY PARITY If parity is enabled, selects odd parity if cleared to 0 or even parity if set to 1.
|
||||
7 STOP BITS STOPBITS Determines the number of stop bits transmitted-one stop bit if cleared to 0 or two stop bits if set to 1.
|
||||
*/
|
||||
|
||||
SciRegs = rs_arr->SciRegs;
|
||||
|
||||
if(bit>0 && bit<9) SciRegs->SCICCR.bit.SCICHAR = bit-1;
|
||||
|
||||
switch(parity)
|
||||
{
|
||||
case 'N': SciRegs->SCICCR.bit.PARITYENA = 0;
|
||||
break;
|
||||
case 'O': SciRegs->SCICCR.bit.PARITYENA = 1;
|
||||
SciRegs->SCICCR.bit.PARITY = 0;
|
||||
break;
|
||||
case 'E': SciRegs->SCICCR.bit.PARITYENA = 1;
|
||||
SciRegs->SCICCR.bit.PARITY = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
if (stop==1) SciRegs->SCICCR.bit.STOPBITS = 0;
|
||||
if (stop==2) SciRegs->SCICCR.bit.STOPBITS = 1;
|
||||
|
||||
SciRegs->SCICCR.bit.LOOPBKENA = 0; //0
|
||||
SciRegs->SCICCR.bit.ADDRIDLE_MODE = 0;
|
||||
}
|
||||
|
||||
void clear_timer_rs_live(RS_DATA *rs_arr)
|
||||
{
|
||||
rs_arr->time_wait_rs_out=0;
|
||||
}
|
||||
|
||||
/* ïðîâåðêà íà æèâó÷åñòü RS */
|
||||
void test_rs_live(RS_DATA *rs_arr)
|
||||
{
|
||||
/* if (rs_arr->time_wait_rs_out < RS_TIME_OUT)
|
||||
rs_arr->time_wait_rs_out++;
|
||||
else
|
||||
{
|
||||
rs_arr->time_wait_rs_out=0;
|
||||
RS_Line_to_receive(rs_arr); // ðåæèì ïðèåìà RS485
|
||||
RS_SetBitMode(rs_arr,9);
|
||||
}*/ }
|
||||
138
RS485.h
Normal file
138
RS485.h
Normal file
@@ -0,0 +1,138 @@
|
||||
/****************************************************************/
|
||||
/* TMS320C32 */
|
||||
/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */
|
||||
/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2000 ã. */
|
||||
/****************************************************************
|
||||
RS485.h
|
||||
****************************************************************
|
||||
* Ïðîöåäóðû ðàáîòû ñ UART *
|
||||
****************************************************************/
|
||||
#ifndef _RS485
|
||||
#define _RS485
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//#include "DSP2833x_Device.h" // DSP281x Headerfile Include File
|
||||
//#include "DSP2833x_Sci.h"
|
||||
//#include "cntrl_adr.h"
|
||||
//#include "params.h"
|
||||
|
||||
#define COM_1 1
|
||||
#define COM_2 2
|
||||
|
||||
#define MAX_RECEIVE_LENGTH 400 // 80 //150
|
||||
#define MAX_SEND_LENGTH 400 //150
|
||||
|
||||
#define TIME_WAIT_RS_BYTE_OUT 1000
|
||||
#define TIME_WAIT_RS_LOST_BYTE 100
|
||||
#define RS_TIME_OUT (SECOND*10)
|
||||
|
||||
#define Rec_Bloc_Begin 0x200000
|
||||
#define Rec_Bloc_End 0x2F0000
|
||||
#define Rec_Bloc_Length (Rec_Bloc_End-Rec_Bloc_Begin)
|
||||
|
||||
/* Message RS declaration */
|
||||
typedef struct
|
||||
{
|
||||
volatile struct SCI_REGS *SciRegs;
|
||||
|
||||
unsigned int commnumber; // Íîìåð ïîðòà
|
||||
unsigned long RS_Length; // Äëèíà ïàêåòà
|
||||
|
||||
unsigned int *pRS_RecvPtr; // Áóôåð ïðèåìà
|
||||
unsigned int *pRS_SendPtr; // Áóôåð ïîñûëêè
|
||||
unsigned int *pRecvPtr;
|
||||
|
||||
unsigned int RS_PrevCmd; // Ïðåäûäóùàà êîììàíäà
|
||||
unsigned int RS_Cmd; // Òåêóùàà êîììàíäà
|
||||
unsigned int RS_Header[MAX_RECEIVE_LENGTH]; // Çàãîëîâîê
|
||||
unsigned int flag_TIMEOUT_to_Send; // Ôëàã îæèäàíèà òàéìàóòà íà îòñûëêó
|
||||
unsigned int flag_TIMEOUT_to_Receive; // Ôëàã îæèäàíèà òàéìàóòà íà ïðèåì
|
||||
unsigned int RS_DataReady; // Ôëàã ãîòîâíîñòè RS äàííûõ
|
||||
unsigned int buffer[MAX_SEND_LENGTH]; // Áóôåð äëà îòñûëêè ïî RS
|
||||
|
||||
unsigned int addr_answer; // àäðåñ êóäà îòâå÷àòü â ðåæèìå âåäóùåãî
|
||||
unsigned int addr_recive; // àäðåñ ïî êîòîðîìó íàñ çàïðîñèëè
|
||||
unsigned int flag_LEADING; // Ôëàã ðåæèìà êîíòðîëëåðà (ïî óìîë÷àíèþ âåäîìûé)
|
||||
unsigned long RS_RecvLen;
|
||||
unsigned long RS_SLength; // Äëèíà ïàêåòà äëà ïîñûëêè
|
||||
unsigned long RS_SendLen; // Êîëè÷åñòâî áàéò óæå ïåðåäàëè
|
||||
char RS_SendBlockMode; // Ðåæèì ïåðåäà÷è
|
||||
char RS_Flag9bit; // äëà RS485????????
|
||||
int BS_LoadOK; // Ôëàã óñïåøíîñòè ïðèåìà áëîêà
|
||||
int RS_FlagBegin;
|
||||
int RS_HeaderCnt;
|
||||
int RS_FlagSkiping;
|
||||
unsigned long curr_baud;
|
||||
unsigned long time_wait_rs_out;
|
||||
|
||||
} RS_DATA;
|
||||
|
||||
extern RS_DATA rs_a,rs_b;
|
||||
|
||||
extern unsigned int
|
||||
RS_Len[70]; /* Äåéñòâèòåëüíàà äëèíà êîìàíäû (îòëàäî÷íîé) + 1 */
|
||||
|
||||
interrupt void RSA_RX_Handler(void);
|
||||
interrupt void RSA_TX_Handler(void);
|
||||
interrupt void RSB_RX_Handler(void);
|
||||
interrupt void RSB_TX_Handler(void);
|
||||
|
||||
/* èíèöèëèçàöèà ïåðåìåííûõ rs_a,rs_b*/
|
||||
void create_uart_vars(char size_cmd15);
|
||||
|
||||
/** Ïîâòîðíàà èíèöèàëèçàöèà ïîñëåäîâàòåëüíîãî ïîðòà, èñïîëüçóåòñà ïîñëå ïîäâèñà */
|
||||
/** Íàñòðîéêà ðåæèìà ïðèåìà/ïåðåäà÷è */
|
||||
void RS_SetBitMode(RS_DATA *rs_arr, int n);
|
||||
|
||||
/** Ïîñûëêà áëîêà áàéòîâ.
|
||||
Ïîñûëàåò ìàññèâà 32-áèòíûõ öåëûõ ÷èñåë ñòàðøèå áèòû äîëæíû áûòü 0.
|
||||
@precondition Ðàáîòà ô-öèè çàâèñèò îò ìàêðî RS_TRANSMIT_INTR
|
||||
@param buf àäðåñ ìàññèâà
|
||||
@param len êîëè÷åñòâî áàéò
|
||||
@see RS_BSend, RS_TRANSMIT_INTR
|
||||
*/
|
||||
int RS_Send(RS_DATA *rs_arr,unsigned int *pBuf, unsigned long len);
|
||||
|
||||
/** Ïîñûëêà áëîêà óïàêîâàííûõ áàéòîâ.
|
||||
@precondition Ðàáîòà ô-öèè çàâèñèò îò ìàêðî RS_TRANSMIT_INTR
|
||||
@param buf àäðåñ ìàññèâà
|
||||
@param len êîëè÷åñòâî 8-áèòíûõ áàéò
|
||||
@see RS_Send, RS_TRANSMIT_INTR
|
||||
*/
|
||||
int RS_BSend(RS_DATA *rs_arr,unsigned int *pBuf, unsigned long len);
|
||||
|
||||
/** Èíèöèàëèçàöèà ïîñëåäîâàòåëüíîãî ïîðòà */
|
||||
void setup_uart(char commnumber,unsigned long speed_baud); /* speed_baud - ñêîðîñòü ëèíèè â áîäàõ */
|
||||
|
||||
void RS_SetLineMode(RS_DATA *rs_arr, int bit, char parity, int stop);
|
||||
void RS_SetLineSpeed(RS_DATA *rs_arr, unsigned long speed);
|
||||
|
||||
// Transmit a character from the SCI'
|
||||
#define SCI_send(x,y) x->SciRegs->SCITXBUF=(unsigned char)(y)
|
||||
|
||||
// Îæèäàíèå çàâåðøåíèà ïåðåäà÷è UART
|
||||
// wait for TRDY =1 for empty state
|
||||
#define RS_Wait4OK(x) while(!(x->SciRegs->SCICTL2.bit.TXEMPTY))
|
||||
|
||||
/** Ïåðåêëþ÷åíèå ëèíèè íà ïðèåì */
|
||||
#define RS_Line_to_receive(x) if(x->commnumber==COM_2) GpioDataRegs.GPBDAT.bit.GPIO34 = 1;
|
||||
|
||||
/** Ïåðåêëþ÷åíèå ëèíèè íà ïåðåäà÷ó */
|
||||
#define RS_Line_to_send(x) if(x->commnumber==COM_2) GpioDataRegs.GPBDAT.bit.GPIO34 = 0;
|
||||
|
||||
/** Ðàçðåøåíèå ïðåðûâàíèé ïî ïîëó÷åíèþ ñèìâîëà è îøèáêàì îò UART */
|
||||
#define enableUARTInt(x) x->SciRegs->SCICTL2.all=2
|
||||
#define enableUARTIntW(x) x->SciRegs->SCICTL2.all=1
|
||||
|
||||
void clear_timer_rs_live(RS_DATA *rs_arr);
|
||||
void test_rs_live(RS_DATA *rs_arr);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _RS485 */
|
||||
|
||||
@@ -1,237 +0,0 @@
|
||||
/*
|
||||
/* TI File $Revision: /main/1 $ */
|
||||
/* Checkin $Date: May 7, 2008 13:07:07 $ */
|
||||
/***********************************************************************/
|
||||
/* File: DSP2833x_DualMap_EPWM.gel
|
||||
/*
|
||||
/* Description:
|
||||
/* Adds dual-mapped EPWM registers to the GEL menu in
|
||||
/* Code Composer Studio and allows user to enable dual-mapping of
|
||||
/* EPWM registers to Peripheral Frame 3 (DMA-accessible) register
|
||||
/* space
|
||||
//#####################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//#####################################################################
|
||||
*/
|
||||
|
||||
/********************************************************************/
|
||||
/* Dual-Mapped Enhanced PWM Registers */
|
||||
/********************************************************************/
|
||||
|
||||
/* Add a space line to the GEL menu */
|
||||
menuitem "___________________________________";
|
||||
hotmenu ___() {}
|
||||
|
||||
menuitem "Dual-Mapped ePWM Registers";
|
||||
hotmenu Enable_ePWM_Dual_Mapping ()
|
||||
{
|
||||
*0x702E = (*0x702E) | 0x0001; /* MAPCNF[MAPEPWM] = 1 */
|
||||
}
|
||||
hotmenu ePWM1_DualMapped_All_Regs()
|
||||
{
|
||||
GEL_WatchAdd("*0x5800,x","ePWM1 TBCTL");
|
||||
GEL_WatchAdd("*0x5801,x","ePWM1 TBSTS");
|
||||
GEL_WatchAdd("*0x5802,x","ePWM1 TBPHSHR");
|
||||
GEL_WatchAdd("*0x5803,x","ePWM1 TBPHS");
|
||||
GEL_WatchAdd("*0x5804,x","ePWM1 TBCTR");
|
||||
GEL_WatchAdd("*0x5805,x","ePWM1 TBPRD");
|
||||
GEL_WatchAdd("*0x5807,x","ePWM1 CMPCTL");
|
||||
GEL_WatchAdd("*0x5808,x","ePWM1 CMPAHR");
|
||||
GEL_WatchAdd("*0x5809,x","ePWM1 CMPA");
|
||||
GEL_WatchAdd("*0x580A,x","ePWM1 CMPB");
|
||||
GEL_WatchAdd("*0x580B,x","ePWM1 AQCTLA");
|
||||
GEL_WatchAdd("*0x580C,x","ePWM1 AQCTLB");
|
||||
GEL_WatchAdd("*0x580D,x","ePWM1 AQSFRC");
|
||||
GEL_WatchAdd("*0x580E,x","ePWM1 AQCSFRC");
|
||||
GEL_WatchAdd("*0x580F,x","ePWM1 DBCTL");
|
||||
GEL_WatchAdd("*0x5810,x","ePWM1 DBRED");
|
||||
GEL_WatchAdd("*0x5811,x","ePWM1 DBFED");
|
||||
GEL_WatchAdd("*0x5812,x","ePWM1 TZSEL");
|
||||
GEL_WatchAdd("*0x5813,x","ePWM1 TZDCSEL");
|
||||
GEL_WatchAdd("*0x5814,x","ePWM1 TZCTL");
|
||||
GEL_WatchAdd("*0x5815,x","ePWM1 TZEINT");
|
||||
GEL_WatchAdd("*0x5816,x","ePWM1 TZFLG");
|
||||
GEL_WatchAdd("*0x5817,x","ePWM1 TZCLR");
|
||||
GEL_WatchAdd("*0x5818,x","ePWM1 TZFRC");
|
||||
GEL_WatchAdd("*0x5819,x","ePWM1 ETSEL");
|
||||
GEL_WatchAdd("*0x581A,x","ePWM1 ETPS");
|
||||
GEL_WatchAdd("*0x581B,x","ePWM1 ETFLG");
|
||||
GEL_WatchAdd("*0x581C,x","ePWM1 ETCLR");
|
||||
GEL_WatchAdd("*0x581D,x","ePWM1 ETFRC");
|
||||
GEL_WatchAdd("*0x581E,x","ePWM1 PCCTL");
|
||||
GEL_WatchAdd("*0x5820,x","ePWM1 HRCNFG");
|
||||
}
|
||||
|
||||
hotmenu ePWM2_DualMapped_All_Regs()
|
||||
{
|
||||
GEL_WatchAdd("*0x5840,x","ePWM2 TBCTL");
|
||||
GEL_WatchAdd("*0x5841,x","ePWM2 TBSTS");
|
||||
GEL_WatchAdd("*0x5842,x","ePWM2 TBPHSHR");
|
||||
GEL_WatchAdd("*0x5843,x","ePWM2 TBPHS");
|
||||
GEL_WatchAdd("*0x5844,x","ePWM2 TBCTR");
|
||||
GEL_WatchAdd("*0x5845,x","ePWM2 TBPRD");
|
||||
GEL_WatchAdd("*0x5847,x","ePWM2 CMPCTL");
|
||||
GEL_WatchAdd("*0x5848,x","ePWM2 CMPAHR");
|
||||
GEL_WatchAdd("*0x5849,x","ePWM2 CMPA");
|
||||
GEL_WatchAdd("*0x584A,x","ePWM2 CMPB");
|
||||
GEL_WatchAdd("*0x584B,x","ePWM2 AQCTLA");
|
||||
GEL_WatchAdd("*0x584C,x","ePWM2 AQCTLB");
|
||||
GEL_WatchAdd("*0x584D,x","ePWM2 AQSFRC");
|
||||
GEL_WatchAdd("*0x584E,x","ePWM2 AQCSFRC");
|
||||
GEL_WatchAdd("*0x584F,x","ePWM2 DBCTL");
|
||||
GEL_WatchAdd("*0x5850,x","ePWM2 DBRED");
|
||||
GEL_WatchAdd("*0x5851,x","ePWM2 DBFED");
|
||||
GEL_WatchAdd("*0x5852,x","ePWM2 TZSEL");
|
||||
GEL_WatchAdd("*0x5853,x","ePWM2 TZDCSEL");
|
||||
GEL_WatchAdd("*0x5854,x","ePWM2 TZCTL");
|
||||
GEL_WatchAdd("*0x5855,x","ePWM2 TZEINT");
|
||||
GEL_WatchAdd("*0x5856,x","ePWM2 TZFLG");
|
||||
GEL_WatchAdd("*0x5857,x","ePWM2 TZCLR");
|
||||
GEL_WatchAdd("*0x5858,x","ePWM2 TZFRC");
|
||||
GEL_WatchAdd("*0x5859,x","ePWM2 ETSEL");
|
||||
GEL_WatchAdd("*0x585A,x","ePWM2 ETPS");
|
||||
GEL_WatchAdd("*0x585B,x","ePWM2 ETFLG");
|
||||
GEL_WatchAdd("*0x585C,x","ePWM2 ETCLR");
|
||||
GEL_WatchAdd("*0x585D,x","ePWM2 ETFRC");
|
||||
GEL_WatchAdd("*0x585E,x","ePWM2 PCCTL");
|
||||
GEL_WatchAdd("*0x5860,x","ePWM2 HRCNFG");
|
||||
}
|
||||
hotmenu ePWM3_DualMapped_All_Regs()
|
||||
{
|
||||
GEL_WatchAdd("*0x5880,x","ePWM3 TBCTL");
|
||||
GEL_WatchAdd("*0x5881,x","ePWM3 TBSTS");
|
||||
GEL_WatchAdd("*0x5882,x","ePWM3 TBPHSHR");
|
||||
GEL_WatchAdd("*0x5883,x","ePWM3 TBPHS");
|
||||
GEL_WatchAdd("*0x5884,x","ePWM3 TBCTR");
|
||||
GEL_WatchAdd("*0x5885,x","ePWM3 TBPRD");
|
||||
GEL_WatchAdd("*0x5887,x","ePWM3 CMPCTL");
|
||||
GEL_WatchAdd("*0x5888,x","ePWM3 CMPAHR");
|
||||
GEL_WatchAdd("*0x5889,x","ePWM3 CMPA");
|
||||
GEL_WatchAdd("*0x588A,x","ePWM3 CMPB");
|
||||
GEL_WatchAdd("*0x588B,x","ePWM3 AQCTLA");
|
||||
GEL_WatchAdd("*0x588C,x","ePWM3 AQCTLB");
|
||||
GEL_WatchAdd("*0x588D,x","ePWM3 AQSFRC");
|
||||
GEL_WatchAdd("*0x588E,x","ePWM3 AQCSFRC");
|
||||
GEL_WatchAdd("*0x588F,x","ePWM3 DBCTL");
|
||||
GEL_WatchAdd("*0x5890,x","ePWM3 DBRED");
|
||||
GEL_WatchAdd("*0x5891,x","ePWM3 DBFED");
|
||||
GEL_WatchAdd("*0x5892,x","ePWM3 TZSEL");
|
||||
GEL_WatchAdd("*0x5893,x","ePWM3 TZDCSEL");
|
||||
GEL_WatchAdd("*0x5894,x","ePWM3 TZCTL");
|
||||
GEL_WatchAdd("*0x5895,x","ePWM3 TZEINT");
|
||||
GEL_WatchAdd("*0x5896,x","ePWM3 TZFLG");
|
||||
GEL_WatchAdd("*0x5897,x","ePWM3 TZCLR");
|
||||
GEL_WatchAdd("*0x5898,x","ePWM3 TZFRC");
|
||||
GEL_WatchAdd("*0x5899,x","ePWM3 ETSEL");
|
||||
GEL_WatchAdd("*0x589A,x","ePWM3 ETPS");
|
||||
GEL_WatchAdd("*0x589B,x","ePWM3 ETFLG");
|
||||
GEL_WatchAdd("*0x589C,x","ePWM3 ETCLR");
|
||||
GEL_WatchAdd("*0x589D,x","ePWM3 ETFRC");
|
||||
GEL_WatchAdd("*0x589E,x","ePWM3 PCCTL");
|
||||
GEL_WatchAdd("*0x58A0,x","ePWM3 HRCNFG");
|
||||
}
|
||||
hotmenu ePWM4_DualMapped_All_Regs()
|
||||
{
|
||||
GEL_WatchAdd("*0x58C0,x","ePWM4 TBCTL");
|
||||
GEL_WatchAdd("*0x58C1,x","ePWM4 TBSTS");
|
||||
GEL_WatchAdd("*0x58C2,x","ePWM4 TBPHSHR");
|
||||
GEL_WatchAdd("*0x58C3,x","ePWM4 TBPHS");
|
||||
GEL_WatchAdd("*0x58C4,x","ePWM4 TBCTR");
|
||||
GEL_WatchAdd("*0x58C5,x","ePWM4 TBPRD");
|
||||
GEL_WatchAdd("*0x58C7,x","ePWM4 CMPCTL");
|
||||
GEL_WatchAdd("*0x58C8,x","ePWM4 CMPAHR");
|
||||
GEL_WatchAdd("*0x58C9,x","ePWM4 CMPA");
|
||||
GEL_WatchAdd("*0x58CA,x","ePWM4 CMPB");
|
||||
GEL_WatchAdd("*0x58CB,x","ePWM4 AQCTLA");
|
||||
GEL_WatchAdd("*0x58CC,x","ePWM4 AQCTLB");
|
||||
GEL_WatchAdd("*0x58CD,x","ePWM4 AQSFRC");
|
||||
GEL_WatchAdd("*0x58CE,x","ePWM4 AQCSFRC");
|
||||
GEL_WatchAdd("*0x58CF,x","ePWM4 DBCTL");
|
||||
GEL_WatchAdd("*0x58D0,x","ePWM4 DBRED");
|
||||
GEL_WatchAdd("*0x58D1,x","ePWM4 DBFED");
|
||||
GEL_WatchAdd("*0x58D2,x","ePWM4 TZSEL");
|
||||
GEL_WatchAdd("*0x58D3,x","ePWM4 TZDCSEL");
|
||||
GEL_WatchAdd("*0x58D4,x","ePWM4 TZCTL");
|
||||
GEL_WatchAdd("*0x58D5,x","ePWM4 TZEINT");
|
||||
GEL_WatchAdd("*0x58D6,x","ePWM4 TZFLG");
|
||||
GEL_WatchAdd("*0x58D7,x","ePWM4 TZCLR");
|
||||
GEL_WatchAdd("*0x58D8,x","ePWM4 TZFRC");
|
||||
GEL_WatchAdd("*0x58D9,x","ePWM4 ETSEL");
|
||||
GEL_WatchAdd("*0x58DA,x","ePWM4 ETPS");
|
||||
GEL_WatchAdd("*0x58DB,x","ePWM4 ETFLG");
|
||||
GEL_WatchAdd("*0x58DC,x","ePWM4 ETCLR");
|
||||
GEL_WatchAdd("*0x58DD,x","ePWM4 ETFRC");
|
||||
GEL_WatchAdd("*0x58DE,x","ePWM4 PCCTL");
|
||||
GEL_WatchAdd("*0x58E0,x","ePWM4 HRCNFG");
|
||||
}
|
||||
hotmenu ePWM5_DualMapped_All_Regs()
|
||||
{
|
||||
GEL_WatchAdd("*0x5900,x","ePWM5 TBCTL");
|
||||
GEL_WatchAdd("*0x5901,x","ePWM5 TBSTS");
|
||||
GEL_WatchAdd("*0x5902,x","ePWM5 TBPHSHR");
|
||||
GEL_WatchAdd("*0x5903,x","ePWM5 TBPHS");
|
||||
GEL_WatchAdd("*0x5904,x","ePWM5 TBCTR");
|
||||
GEL_WatchAdd("*0x5905,x","ePWM5 TBPRD");
|
||||
GEL_WatchAdd("*0x5907,x","ePWM5 CMPCTL");
|
||||
GEL_WatchAdd("*0x5908,x","ePWM5 CMPAHR");
|
||||
GEL_WatchAdd("*0x5909,x","ePWM5 CMPA");
|
||||
GEL_WatchAdd("*0x590A,x","ePWM5 CMPB");
|
||||
GEL_WatchAdd("*0x590B,x","ePWM5 AQCTLA");
|
||||
GEL_WatchAdd("*0x590C,x","ePWM5 AQCTLB");
|
||||
GEL_WatchAdd("*0x590D,x","ePWM5 AQSFRC");
|
||||
GEL_WatchAdd("*0x590E,x","ePWM5 AQCSFRC");
|
||||
GEL_WatchAdd("*0x590F,x","ePWM5 DBCTL");
|
||||
GEL_WatchAdd("*0x5910,x","ePWM5 DBRED");
|
||||
GEL_WatchAdd("*0x5911,x","ePWM5 DBFED");
|
||||
GEL_WatchAdd("*0x5912,x","ePWM5 TZSEL");
|
||||
GEL_WatchAdd("*0x5913,x","ePWM5 TZDCSEL");
|
||||
GEL_WatchAdd("*0x5914,x","ePWM5 TZCTL");
|
||||
GEL_WatchAdd("*0x5915,x","ePWM5 TZEINT");
|
||||
GEL_WatchAdd("*0x5916,x","ePWM5 TZFLG");
|
||||
GEL_WatchAdd("*0x5917,x","ePWM5 TZCLR");
|
||||
GEL_WatchAdd("*0x5918,x","ePWM5 TZFRC");
|
||||
GEL_WatchAdd("*0x5919,x","ePWM5 ETSEL");
|
||||
GEL_WatchAdd("*0x591A,x","ePWM5 ETPS");
|
||||
GEL_WatchAdd("*0x591B,x","ePWM5 ETFLG");
|
||||
GEL_WatchAdd("*0x591C,x","ePWM5 ETCLR");
|
||||
GEL_WatchAdd("*0x591D,x","ePWM5 ETFRC");
|
||||
GEL_WatchAdd("*0x591E,x","ePWM5 PCCTL");
|
||||
GEL_WatchAdd("*0x5920,x","ePWM5 HRCNFG");
|
||||
}
|
||||
hotmenu ePWM6_DualMapped_All_Regs()
|
||||
{
|
||||
GEL_WatchAdd("*0x5940,x","ePWM6 TBCTL");
|
||||
GEL_WatchAdd("*0x5941,x","ePWM6 TBSTS");
|
||||
GEL_WatchAdd("*0x5942,x","ePWM6 TBPHSHR");
|
||||
GEL_WatchAdd("*0x5943,x","ePWM6 TBPHS");
|
||||
GEL_WatchAdd("*0x5944,x","ePWM6 TBCTR");
|
||||
GEL_WatchAdd("*0x5945,x","ePWM6 TBPRD");
|
||||
GEL_WatchAdd("*0x5947,x","ePWM6 CMPCTL");
|
||||
GEL_WatchAdd("*0x5948,x","ePWM6 CMPAHR");
|
||||
GEL_WatchAdd("*0x5949,x","ePWM6 CMPA");
|
||||
GEL_WatchAdd("*0x594A,x","ePWM6 CMPB");
|
||||
GEL_WatchAdd("*0x594B,x","ePWM6 AQCTLA");
|
||||
GEL_WatchAdd("*0x594C,x","ePWM6 AQCTLB");
|
||||
GEL_WatchAdd("*0x594D,x","ePWM6 AQSFRC");
|
||||
GEL_WatchAdd("*0x594E,x","ePWM6 AQCSFRC");
|
||||
GEL_WatchAdd("*0x594F,x","ePWM6 DBCTL");
|
||||
GEL_WatchAdd("*0x5950,x","ePWM6 DBRED");
|
||||
GEL_WatchAdd("*0x5951,x","ePWM6 DBFED");
|
||||
GEL_WatchAdd("*0x5952,x","ePWM6 TZSEL");
|
||||
GEL_WatchAdd("*0x5953,x","ePWM6 TZDCSEL");
|
||||
GEL_WatchAdd("*0x5954,x","ePWM6 TZCTL");
|
||||
GEL_WatchAdd("*0x5955,x","ePWM6 TZEINT");
|
||||
GEL_WatchAdd("*0x5956,x","ePWM6 TZFLG");
|
||||
GEL_WatchAdd("*0x5957,x","ePWM6 TZCLR");
|
||||
GEL_WatchAdd("*0x5958,x","ePWM6 TZFRC");
|
||||
GEL_WatchAdd("*0x5959,x","ePWM6 ETSEL");
|
||||
GEL_WatchAdd("*0x595A,x","ePWM6 ETPS");
|
||||
GEL_WatchAdd("*0x595B,x","ePWM6 ETFLG");
|
||||
GEL_WatchAdd("*0x595C,x","ePWM6 ETCLR");
|
||||
GEL_WatchAdd("*0x595D,x","ePWM6 ETFRC");
|
||||
GEL_WatchAdd("*0x595E,x","ePWM6 PCCTL");
|
||||
GEL_WatchAdd("*0x5960,x","ePWM6 HRCNFG");
|
||||
|
||||
}
|
||||
|
||||
BIN
bin/HEX2BIN.EXE
Normal file
BIN
bin/HEX2BIN.EXE
Normal file
Binary file not shown.
BIN
bin/hex2000.exe
Normal file
BIN
bin/hex2000.exe
Normal file
Binary file not shown.
BIN
bin/ice.bin
Normal file
BIN
bin/ice.bin
Normal file
Binary file not shown.
979
bin/ice.hex
Normal file
979
bin/ice.hex
Normal file
@@ -0,0 +1,979 @@
|
||||
:20000000AA0800000000000000000000000000000000000041B8E1010000BDB900FF40DFBF
|
||||
:2000200000000000C1C081C1400101C3C003800241C201C6C006800741C70005C1C581C4C4
|
||||
:20004000400401CCC00C800D41CD000FC1CF81CE400E000AC1CA81CB400B01C9C0098008A5
|
||||
:2000600041C801D8C018801941D9001BC1DB81DA401A001EC1DE81DF401F01DDC01D801CD4
|
||||
:2000800041DC0014C1D481D5401501D7C017801641D601D2C012801341D30011C1D181D053
|
||||
:2000A000401001F0C030803141F10033C1F381F240320036C1F681F7403701F5C0358034E5
|
||||
:2000C00041F4003CC1FC81FD403D01FFC03F803E41FE01FAC03A803B41FB0039C1F981F8A3
|
||||
:2000E00040380028C1E881E9402901EBC02B802A41EA01EEC02E802F41EF002DC1ED81EC34
|
||||
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:206A9E001C001F762C00201A03001F762C00201A00301F762C00201A000E1F762C00201A8F
|
||||
:206ABE0080011F762C00211A40001F762C00201A00401F762C00201A00801F762C00211A49
|
||||
:206ADE0003001F762C002C1A60001F762C002C1A1C001F762C002C1A03001F762C002C1AFA
|
||||
:206AFE0000301F762C002C1A000E1F762C002C1A80011F762C002D1A40001F762C002C1A5C
|
||||
:206B1E0000401F762C002C1A00801F762C002D1A03001F762C002E1A60001F762C002E1A13
|
||||
:206B3E001C001F762C002E1A03001F762C002E1A00301F762C002E1A000E1F762C002E1AB6
|
||||
:206B5E0080011F762C002F1A40001F762C002E1A00401F762C002E1A00801F762C002F1A70
|
||||
:206B7E0003001F762C00381A07001F762C00381A38001A7669FF407663B407F6007769FFEE
|
||||
:206B9E00060022761F76BE01181A03001F76BE01181A0C001F76BE01181A30001F76BE0114
|
||||
:206BBE00181AC0001F76BE01181A00031F76BE01181A000C1F76BE01181A00301F76BE01A0
|
||||
:206BDE00181A00C01F76BE01191A03001F76BE01191A0C001F76BE01191A30001F76BE017D
|
||||
:206BFE00191AC0001F76BE01191A00031F76BE01191A000C1F76BE01191A00301F76BE015C
|
||||
:206C1E00191A00C01F76BE01141A03001F76BE01141A0C001F76BE01141A30001F76BE014A
|
||||
:206C3E00141AC0001F76BE01141A00031F76BE01141A000C1F76BE01141A00301F76BE012F
|
||||
:206C5E00141A00C01F76BE01151A03001F76BE01151A0C001F76BE01151A30001F76BE010C
|
||||
:206C7E00151AC0001F76BE01151A00031F76BE01151A000C1F76BE01151A00301F76BE01EB
|
||||
:206C9E00151A00C069FF407663B4060022761F76BE01261A03001F76BE01261A0C001F7648
|
||||
:206CBE00BE01261A30001F76BE01261AC0001F76BE01261A00031F76BE01261A000C1F7667
|
||||
:206CDE00BE01261A00301F76BE01261A00C01F76BE01271A03001F76BE01271A0C001F7645
|
||||
:206CFE00BE01271A30001F76BE01271AC0001F76BE01271A00031F76BE01271A000C1F7623
|
||||
:206D1E00BE01271A00301F76BE01271A00C01F76BE01171A03001F76BE01171A0C001F7622
|
||||
:206D3E00BE01171A30001F76BE01171AC0001F76BE01171A00031F76BE01171A000C1F7622
|
||||
:206D5E00BE01171A00301F76BE01171A00C01F76BE01281A03001F76BE01281A0C001F76E0
|
||||
:206D7E00BE01281A30001F76BE01281AC0001F76BE01281A00031F76BE01281A000C1F769E
|
||||
:206D9E00BE01281A00301F76BE01281A00C01F76BE01161A00C01F76BE01161AC0001F7631
|
||||
:206DBE00BE01161A00301F76BE01161A000C1A7669FF060022761F76BE011C18FEFF1F7656
|
||||
:206DDE00BE011C18FDFF1F76BE01121A03001F76BE01121A0C001F76BE0116CCFCFF015015
|
||||
:206DFE001F76BE0116961F76BE0116CCF3FF1F76BE01045016961A7669FF06004076F7B49A
|
||||
:206E1E001F76E401BF5607501F76E4010918DFFF1F76E401BF560C0E1F76E401BF56030AB0
|
||||
:206E3E001F76E401BF5604051F76E401092B1F76E401091A00041F76E401091A200006008A
|
||||
:206E5E00A8881F76E401094B04EFA92855553C6F1F76E401024C04EFA9280010356F1F7628
|
||||
:206E7E00E401BF5605041F76E4010928206EA993D6FF1F76E401FF9108971F76E40102443E
|
||||
:206E9E00FDEF0356A9011F76E40108961F76E4010244FDEFA6921F76E401A7FF08961F7696
|
||||
:206EBE00E4010244FDEF1F76E401087E1F76E4010244FDEF1F76E401094BFDEE1F76E401BE
|
||||
:206EDE00024CFDEE009A06001F76E401094B04EFA92855553E6F1F76E401024C04EFA92846
|
||||
:206EFE000010376F1F76E401BF5605021F76E4010928206EA993D6FF1F76E401FF91089735
|
||||
:206F1E001F76E4010244FDEF0356A9011F76E40108961F76E401094BFDEE1F76E401BF5644
|
||||
:206F3E0005021F76E4010928206C1F76E4010243FDEF1F76E4010693A8381F76E401024398
|
||||
:206F5E00FDEFA9CD00FF1F76E4010692FF90A8CA0600A71EA70610EC8458A592A0F2807690
|
||||
:206F7E0040DFA092FF90A958A592C7FF9670A95D81DFA706F2EDA59206005AFF00B6A9A97F
|
||||
:206F9E00A70F2569A7920190A9580129A4C4A70640FF0156A600C693A09204EDA892C7FFCD
|
||||
:206FBE00A92DA092015204EDA8CCFF00A92DA593AC58A0F3807640DFA092D7FFFF90A958A2
|
||||
:206FDE009671A85D01DFA9A9A70FDD66A5920600A988A928FFFF00D0A693A0552B69949366
|
||||
:206FFE00FF91A87000D5A59308530D67A9CD010003EDC0FF046FC0FFA91C01A001DDA5931B
|
||||
:20701E000853F5689493D7FFA87000D5A59308530D67A9CD010003EDC0FF046FC0FFA91C8C
|
||||
:20703E0001A001DDA5930853F568A69301D8A055D766060006FEC406461E0129460647FF8B
|
||||
:20705E00A81A00FF421E00BEA69220521563420608560080441E440605ECAA280031AB2B75
|
||||
:20707E0044A9420630FF44704371421EA692019C2052A988ED644206AC28180046A3AB181D
|
||||
:20709E0000FF2256ABCAAACB421E00D44606420FB156A401A49286FE0600BD3ABDB2BDAA67
|
||||
:2070BE00BDA202FE0129A9BF120F58FF5B61A85C7F91A8088000421EA493D6FFA85CA9BF71
|
||||
:2070DE00160F6761A85D7F91A8088000A859A958A593D6FFA85DA493A571A8180001A69701
|
||||
:2070FE00A418FF00A518FF007FDCA492A59EA7964D64A90801FF3E62A193A09236FFA8594C
|
||||
:20711E00A958420635FF0EF6A11FA95BA3010AF6A11F2D56A204A32DA03640FF0BF6A11FD9
|
||||
:20713E0033FF009B30FF54FFA20CA39540FFA70801001FF677FF200940FFA70801001FF655
|
||||
:20715E0077FF5AFFA7922265A90801FF1363A9A946FF7F91A85BA95AA625A79596FFA20C64
|
||||
:20717E00A395A9BD120F82FEBE82BE86BE8BBE8E0600009B57FFA8087FFF5AFFA693F26090
|
||||
:20719E00A8280080AA71AB92ED6F20FF0000EA6F5AFFA493A818000196FFA85CA9A9A80869
|
||||
:2071BE007FFFA81C0080A4CBDD6F1F76C001201A0010407663B422761F762C003518F8FF2A
|
||||
:2071DE001F762C00341A03001F762C003418F7FF1F762C003418FBFF1F762C002ECC9FFF1C
|
||||
:2071FE001F762C0020502E961F762C002ECCE3FF1F762C0008502E961F762C002ECCFCFF4C
|
||||
:20721E001F762C0001502E961F762C002ECCFFCF1F762C00A91A00102E961F762C002ECCDE
|
||||
:20723E00FFF11F762C00A91A00062E961F762C002E187FFE1F762C002F18BFFF1F762C00E7
|
||||
:20725E002E18FFBF1F762C002E18FF7F1F762C002F1A03001A7607F6007769FF0600227670
|
||||
:20727E001F76BE011618FCFF1F76BE011818FCFF1F76BE011A1A01001F76BE011B1A0100E1
|
||||
:20729E001A7669FF0600BDB2BDAAA986012900D1A9AA40FFA986A10F086910024076B9B9B6
|
||||
:2072BE0001D9A9AAA10FFA66BE86BE8B0600008F000C1F767C031EA8AA28FFFFAB28FFFFCA
|
||||
:2072DE001F76300002A91F763000062B1F763000072B1F763000041A10001F763000041A5D
|
||||
:2072FE00200000021F767C03201E1F767C03008F080C26A81F767C03008F100C2EA81F764D
|
||||
:20731E0030000AA91F76300012A91F7630000E2B1F7630000F2B1F763000162B1F76300024
|
||||
:20733E00172B1F7630000C1A10001F763000141A10001F7630000C1A20001F763000141AF1
|
||||
:20735E0020001F767C03281E1F767C03301E060003E2E40003E2F40100E70800007788E6B6
|
||||
:20737E000000C48303E2D500C483F52BC483FD2BC483E51A1000C483E51A2000C483E51818
|
||||
:20739E00FFFBC483E518FFF7C483E51A00400002D41E0600103B1F7633002018FEFF1F763E
|
||||
:2073BE003300222B1F763300242B1F763300262B1F763300282B1F7633002A2B1F763300FF
|
||||
:2073DE002C2B1F7633002E2B1F763300302B1F763300322B1F763300342B1F763300362B7F
|
||||
:2073FE001F763300382B1F763300232B1F763300252B1F763300272B1F763300292B1F764B
|
||||
:20741E0033002B2B1F7633002D2B1F7633002F2B1F763300312B1F763300332B1F76330071
|
||||
:20743E00352B1F763300372B1F763300392B69FF06001F763300201A01001F7633002128F6
|
||||
:20745E00FFFF102969FF0600AD28000469FF1F5616561A5610E6000240291F7600000229B6
|
||||
:20747E001B762276A928BDB9A828000001091B61C076BDB904290F6F009BA92401DF046C19
|
||||
:20749E000429A82401DFA61EA1F78624A706A1810109A71EA92403635CFF043BA95901DFA2
|
||||
:2074BE000900ECFF1A76A928FFFFA828FFFF01090E61FF76FFFF066F01DFBDC3A71E673E62
|
||||
:2074DE00BEC5A92401DFA82458FFF760407665B9407682B9BDB203E2BD0403E2BD0503E27E
|
||||
:2074FE00BD06CFE6010008D0AFE2F402AFE2F40510E7AA000ED112E39493AFE2C40014E324
|
||||
:20751E00D4D40CD000E3948509E3E45EAFE29C0240E79231007710E7100094069C1E03E2CF
|
||||
:20753E00940008D0F406941E03E2F401AFE2BE06AFE2BE05AFE2BE04BE8B06000229042998
|
||||
:20755E005F565AFF42065F56421E00021FF617564200AB06325602292076022904295F56D5
|
||||
:20757E005AFF420656FF421E00021FF6175642003256022920765AFF00021FF61756420069
|
||||
:20759E00A9A920765AFF00021FF6175642002076A85CA971A697013BA98556FFA95DA485E7
|
||||
:2075BE0056FFA95CA5920FF6A41FA64F026C5CFF2076A696A85C013BA98556FFA95DA485D2
|
||||
:2075DE0056FFA95CA5920FF6A41FA64F026C5DFFA89220765AFFAB92A4C5A48E07ECFF9CE6
|
||||
:2075FE00A988859287960E00FEFFAB92A988A9A9A60F10ECAA930EECA9A9FF9DA85CBF762E
|
||||
:20761E00FEFF859287960E00FEFF859287960C00F8FFA08A0600A0E514AD0962A0E51F76DE
|
||||
:20763E00760314AD90E5B4563701156F4FE803C092E601008CB5050000E7CA00007700E7EF
|
||||
:20765E008A000077CFE812F0007700E75100007700E74000060022761F76C0011C1A0800D3
|
||||
:20767E0069FF787680001A761F76C4011CCCFF3F1F76C401A91A00401C961F76C401BF5688
|
||||
:20769E0018E0028FE64969FFA9A84076B9B90600A928FFFFAA28FFFFAB28FFFFA828FFFFEF
|
||||
:2076BE00AB0F04ED00D400BE0B6FA927A928FFFFA92FA4A9C488A928FFFF0209A98AA692A0
|
||||
:2076DE0040765AAD06000077006F1F767603BDB230C5A959673E1F76760334C5A70603EC27
|
||||
:2076FE00A192673E1F767603320603ECA71E673E407680B9BE8B0600408F00C0008F000D8C
|
||||
:20771E002276009A8052066385C484C2019C8052FC641A7669FF06001F7676032EA8060098
|
||||
:20773E001F76760330A8060006001F766F0339961F766F03389706000119C356FFFF060050
|
||||
:20775E002B0000002EC122761F762A00001A01001F762A0006CCFFF0A91A00051F762A0078
|
||||
:20777E0006961F762A0006CCF0FF05501F762A0006961F762A0007CCE0FF08501F762A0097
|
||||
:1C779E0007961F762A00041AFF011F762A00051AFF011A7607F6007769FF060005
|
||||
:2077BA000301000000C067920000679200006792000067920000679200006792000067921C
|
||||
:2077DA000000679200006792000067920000679200006792000067920000F6890000038AAD
|
||||
:2077FA000000108A00001D8A00007B920000358A0000408A00004B8A0000568A0000618AF8
|
||||
:20781A0000006C8A0000778A0000828A00008D8A0000988A0000A38A0000AE8A0000B98A6A
|
||||
:20783A000000C48A0000CF8A0000F08A00007B920000118B0000328B0000518B0000728BCE
|
||||
:20785A000000958B0000B68B0000D78B0000F88B0000198C00003C8C00005D8C00007B9265
|
||||
:20787A0000007B9200007E8C00009F8C0000C28C0000E58C0000068D0000278D00007B9299
|
||||
:20789A0000007B9200004A8D00006B8D00008E8D0000AF8D0000D08D0000F18D00007B92B3
|
||||
:2078BA0000007B920000128E0000338E00007B9200007B9200007B9200007B9200007B92FF
|
||||
:2078DA0000007B920000568E0000778E00009A8E0000BB8E0000DC8E0000FD8E00007B9225
|
||||
:2078FA0000007B920000208F0000418F0000628F0000838F0000A48F0000C58F00007B924B
|
||||
:20791A0000007B920000E88F00000B9000007B9200007B9200002C9000004D9000007B926E
|
||||
:20793A0000007B9200006E90000091900000B2900000D3900000F4900000179100003A9165
|
||||
:20795A0000005B9100007B9200007B9200007B9200007B9200007B9200007B9200007B92C6
|
||||
:20797A0000007B9200007B9200007B9200007B9200007B9200007B9200007B9200007B9285
|
||||
:20799A0000007B9200007C9100009D910000BE910000DF910000009200007B920000239272
|
||||
:0C79BA0000004492000033000B000A00A3
|
||||
:2079C600280000005AC119AA0000C6AA000005AA0000B2AA0000F4A90000A0AA0000E3A9AD
|
||||
:2079E600000087AA0000C4A9000073AA0000B3A9000067AA000095A9000056AA000084A9EE
|
||||
:187A0600000043AA000073A9000032AA00005CA9000042A90000000093
|
||||
:00000001FF
|
||||
34
bin/ice.map
Normal file
34
bin/ice.map
Normal file
@@ -0,0 +1,34 @@
|
||||
********************************************************************************
|
||||
TMS320C2000 Hex Converter v5.2.1
|
||||
********************************************************************************
|
||||
|
||||
INPUT FILE NAME: <D:\project2833\GIT\ICE_22220_1\bin\ice.out>
|
||||
OUTPUT FORMAT: Binary
|
||||
|
||||
PHYSICAL MEMORY PARAMETERS
|
||||
Default data width : 16
|
||||
Default memory width : 8 (LS-->MS)
|
||||
Default output width : 8
|
||||
|
||||
BOOT LOADER PARAMETERS
|
||||
Table Type: SERIAL PORT (SCI 8 bit Mode)
|
||||
Entry Point: 0x0000b841
|
||||
|
||||
|
||||
OUTPUT TRANSLATION MAP
|
||||
--------------------------------------------------------------------------------
|
||||
00000000..003fffff Page=0 Memory Width=8 ROM Width=8
|
||||
--------------------------------------------------------------------------------
|
||||
OUTPUT FILES: D:\project2833\GIT\ICE_22220_1\bin\ice.bin [b0..b7]
|
||||
|
||||
CONTENTS: 00000000..00007a1d BOOT TABLE
|
||||
.cinit : dest=0000b9bd size=000001e1 width=00000002
|
||||
.text : dest=00008000 size=000039bd width=00000002
|
||||
ramfuncs : dest=0000c12e size=0000002b width=00000002
|
||||
.econst : dest=0000c000 size=00000103 width=00000002
|
||||
.switch : dest=0000c15a size=00000028 width=00000002
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
00000000..003fffff Page=1 Memory Width=8 ROM Width=8 "*DEFAULT PAGE 1*"
|
||||
--------------------------------------------------------------------------------
|
||||
NO CONTENTS
|
||||
BIN
bin/ice.out
Normal file
BIN
bin/ice.out
Normal file
Binary file not shown.
BIN
doc/ICE data stru.xls
Normal file
BIN
doc/ICE data stru.xls
Normal file
Binary file not shown.
BIN
doc/Инструкция по калибровке УКСИ.docx
Normal file
BIN
doc/Инструкция по калибровке УКСИ.docx
Normal file
Binary file not shown.
354
ecan.c
Normal file
354
ecan.c
Normal file
@@ -0,0 +1,354 @@
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_SWPrioritizedIsrLevels.h"
|
||||
|
||||
#include "filter_bat2.h"
|
||||
#include "measure.h"
|
||||
#include "package.h" // DSP281x Headerfile Include File
|
||||
#include "peripher.h" // DSP281x Headerfile Include File
|
||||
|
||||
#include "ecan.h" // DSP281x Headerfile Include File
|
||||
#include "tools.h" // DSP281x Headerfile Include File
|
||||
|
||||
#include "RS485.h"
|
||||
#include "message.h"
|
||||
|
||||
|
||||
// Prototype statements for functions found within this file.
|
||||
interrupt void CANa_handler(void);
|
||||
interrupt void CANa_reset_err(void);
|
||||
interrupt void CANb_handler(void);
|
||||
interrupt void CANb_reset_err(void);
|
||||
|
||||
// Global variable for this example
|
||||
Uint32 ErrorCount;
|
||||
Uint32 MessageReceivedCount;
|
||||
Uint32 MessageTransivedCount=0;
|
||||
|
||||
Uint32 TestMbox1 = 0;
|
||||
Uint32 TestMbox2 = 0;
|
||||
Uint32 TestMbox3 = 0;
|
||||
|
||||
int CanTimeOutErrorTR = 0;
|
||||
|
||||
int wait=0;
|
||||
|
||||
void Init_Can(int Port, int DevNum)
|
||||
{
|
||||
struct ECAN_REGS ECanShadow;
|
||||
|
||||
volatile struct ECAN_REGS * ECanRegs;
|
||||
volatile struct ECAN_MBOXES * ECanMboxes;
|
||||
volatile struct MOTO_REGS * ECanMOTORegs;
|
||||
|
||||
long id = 0x801CE000;
|
||||
|
||||
if(DevNum<0)DevNum=0;
|
||||
if(DevNum>15)DevNum=15;
|
||||
|
||||
// Configure CAN pins using GPIO regs here
|
||||
EALLOW;
|
||||
|
||||
if(!Port)
|
||||
{
|
||||
ECanRegs = &ECanaRegs;
|
||||
ECanMboxes = &ECanaMboxes;
|
||||
ECanMOTORegs = &ECanaMOTORegs;
|
||||
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1;
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
ECanRegs = &ECanbRegs;
|
||||
ECanMboxes = &ECanbMboxes;
|
||||
ECanMOTORegs = &ECanbMOTORegs;
|
||||
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 2;
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 2;
|
||||
}
|
||||
|
||||
// Configure the eCAN RX and TX pins for eCAN transmissions
|
||||
ECanRegs->CANTIOC.all = 8; // only 3rd bit, TXFUNC, is significant
|
||||
ECanRegs->CANRIOC.all = 8; // only 3rd bit, RXFUNC, is significant
|
||||
|
||||
// Specify that 8 bits will be sent/received
|
||||
ECanMboxes->MBOX0.MSGCTRL.all = 0x00000008;
|
||||
ECanMboxes->MBOX1.MSGCTRL.all = 0x00000008;
|
||||
ECanMboxes->MBOX2.MSGCTRL.all = 0x00000008;
|
||||
|
||||
// Disable all Mailboxes
|
||||
// Required before writing the MSGIDs
|
||||
ECanRegs->CANME.all = 0;
|
||||
|
||||
// çàäàåì àäðåñ 0 àùèêa íà ïåðåäà÷ó
|
||||
ECanMboxes->MBOX0.MSGID.all = id + DevNum;
|
||||
|
||||
// çàäàåì àäðåñ 1 àùèêa íà ïðèåì
|
||||
ECanMboxes->MBOX1.MSGID.all = id + 0x20 + DevNum;
|
||||
|
||||
// çàäàåì àäðåñ 2 àùèêa íà ïðèåì
|
||||
ECanMboxes->MBOX2.MSGID.all = id + 0x30 + (DevNum&1);
|
||||
|
||||
// çàäàåì ðåæèìû ðàáîòû àùèêa 0 íà ïåðåäà÷ó, îñòàëüíûå íà ïðèåì
|
||||
ECanRegs->CANMD.all = 0xFFFFFFFE;
|
||||
|
||||
// âûáèðàåì òîëüêî 3 àùèêa äëà ðàáîòû, îñòàëüíûå çàïðåùàåì
|
||||
ECanRegs->CANME.all = 0x00000007;
|
||||
|
||||
// Clear all TAn bits
|
||||
ECanRegs->CANTA.all = 0xFFFFFFFF;
|
||||
// Clear all RMPn bits
|
||||
ECanRegs->CANRMP.all = 0xFFFFFFFF;
|
||||
// Clear all interrupt flag bits
|
||||
ECanRegs->CANGIF0.all = 0xFFFFFFFF;
|
||||
ECanRegs->CANGIF1.all = 0xFFFFFFFF;
|
||||
// Clear all error and status bits
|
||||
ECanRegs->CANES.all=0xffffffff;
|
||||
|
||||
// Request permission to change the configuration registers
|
||||
ECanShadow.CANMC.all = 0;
|
||||
ECanShadow.CANMC.bit.MBCC = 1; // Mailbox timestamp counter clear bit
|
||||
ECanShadow.CANMC.bit.TCC = 1; // Time stamp counter MSB clear bit
|
||||
ECanShadow.CANMC.bit.SCB = 1; // eCAN mode (reqd to access 32 mailboxes)
|
||||
ECanShadow.CANMC.bit.WUBA = 1; // Wake up on bus activity
|
||||
ECanShadow.CANMC.bit.ABO = 1; // Auto bus on
|
||||
ECanShadow.CANMC.bit.CCR = 1;
|
||||
// ECanShadow.CANMC.bit.STM = 1; // self-test loop-back
|
||||
ECanRegs->CANMC.all = ECanShadow.CANMC.all;
|
||||
while(!ECanRegs->CANES.bit.CCE); // Wait for CCE bit to be set..
|
||||
|
||||
// íàñòðèâàåì ñêîðîñòü CAN
|
||||
ECanShadow.CANBTC.all = ECanRegs->CANBTC.all;
|
||||
ECanShadow.CANBTC.bit.SJWREG=1;
|
||||
ECanShadow.CANBTC.bit.BRPREG = (CLKMULT * 3) - 1;
|
||||
ECanShadow.CANBTC.bit.TSEG1REG = 15;
|
||||
ECanShadow.CANBTC.bit.TSEG2REG = 2;
|
||||
|
||||
ECanRegs->CANBTC.all = ECanShadow.CANBTC.all;
|
||||
ECanShadow.CANMC.bit.CCR = 0; // Set CCR = 0
|
||||
ECanRegs->CANMC.all = ECanShadow.CANMC.all;
|
||||
while(ECanRegs->CANES.bit.CCE); // Wait for CCE bit to be cleared..
|
||||
|
||||
// çàäàåì òàéìàóòû äëà îæèäàíèà îòïðàâêè ïîëó÷åíèà ïîñûëêè
|
||||
ECanMOTORegs->MOTO0 = 550000;
|
||||
ECanMOTORegs->MOTO1 = 550000;
|
||||
|
||||
ECanRegs->CANTOC.all = 1;
|
||||
ECanRegs->CANTOS.all = 0; // clear all time-out flags
|
||||
ECanRegs->CANTSC = 0; // clear time-out counter
|
||||
|
||||
ECanShadow.CANGIM.all = 0;
|
||||
|
||||
ECanRegs->CANMIM.all = 2+4; // Enable interrupts of box 1
|
||||
ECanRegs->CANMIL.all = 0x00000000; // All mailbox interrupts are generated on interrupt line 0.
|
||||
ECanShadow.CANGIM.bit.I0EN = 1;
|
||||
|
||||
ECanShadow.CANGIM.bit.MTOM = 1;
|
||||
ECanShadow.CANGIM.bit.I1EN = 1;
|
||||
ECanShadow.CANGIM.bit.GIL = 1;
|
||||
ECanRegs->CANGIM.all = ECanShadow.CANGIM.all;
|
||||
|
||||
if(!Port)
|
||||
{
|
||||
PieVectTable.ECAN0INTA = &CANa_handler;
|
||||
PieCtrlRegs.PIEIER9.bit.INTx5=1; // PIE Group 9, INT6
|
||||
PieVectTable.ECAN1INTA = &CANa_reset_err;
|
||||
PieCtrlRegs.PIEIER9.bit.INTx6=1; // PIE Group 9, INT6
|
||||
}
|
||||
else
|
||||
{
|
||||
PieVectTable.ECAN0INTB = &CANb_handler;
|
||||
PieCtrlRegs.PIEIER9.bit.INTx7=1; // PIE Group 9, INT6
|
||||
PieVectTable.ECAN1INTB = &CANb_reset_err;
|
||||
PieCtrlRegs.PIEIER9.bit.INTx8=1; // PIE Group 9, INT6
|
||||
}
|
||||
IER |= M_INT9; // Enable CPU INT
|
||||
|
||||
EDIS;
|
||||
|
||||
// çàâåðøèëè íàñòðîéêó CAN àùèêîâ
|
||||
|
||||
MessageReceivedCount = 0;
|
||||
ErrorCount = 0;
|
||||
CanTimeOutErrorTR=0;
|
||||
MessageTransivedCount=0;
|
||||
}
|
||||
|
||||
void CAN_send(int Port, int data[], int Addr)
|
||||
{
|
||||
unsigned long hiword,loword;
|
||||
volatile struct ECAN_REGS * ECanRegs;
|
||||
volatile struct ECAN_MBOXES * ECanMboxes;
|
||||
|
||||
if(!Port)
|
||||
{
|
||||
ECanRegs = &ECanaRegs;
|
||||
ECanMboxes = &ECanaMboxes;
|
||||
}
|
||||
else
|
||||
{
|
||||
#ifdef TUBER
|
||||
ECanRegs = &ECanbRegs;
|
||||
ECanMboxes = &ECanbMboxes;
|
||||
#endif
|
||||
}
|
||||
|
||||
if(wait)
|
||||
if(!(ECanRegs->CANTA.all & 1))
|
||||
if(!(ECanRegs->CANAA.all & 1))
|
||||
return;
|
||||
|
||||
ECanRegs->CANTA.all = 1;
|
||||
ECanRegs->CANAA.all = 1;
|
||||
|
||||
hiword= ((((Uint32) Addr ) & 0xffff)<<16)| 0xE0000000 |
|
||||
((((Uint32)data[Addr ]) & 0xffff) );
|
||||
loword= ((((Uint32)data[Addr+1]) & 0xffff)<<16)|
|
||||
((((Uint32)data[Addr+2]) & 0xffff) );
|
||||
|
||||
ECanMboxes->MBOX0.MDH.all = hiword;
|
||||
ECanMboxes->MBOX0.MDL.all = loword;
|
||||
|
||||
EALLOW;
|
||||
ECanRegs->CANTSC = 0; // clear time-out counter
|
||||
EDIS;
|
||||
|
||||
ECanRegs->CANTRS.all = 1; // çàïóñòèòü ïåðåäà÷ó
|
||||
|
||||
wait=1;
|
||||
|
||||
if(Desk==dsk_COMM) GpioDataRegs.GPBTOGGLE.bit.GPIO52=1;
|
||||
if(Desk==dsk_ISOL) GpioDataRegs.GPATOGGLE.bit.GPIO27=1;
|
||||
if(Desk==dsk_SHKF) GpioDataRegs.GPBTOGGLE.bit.GPIO63=1;
|
||||
// led1_toggle();
|
||||
}
|
||||
|
||||
|
||||
void Handlai(volatile struct MBOX * ECanMbox)
|
||||
{
|
||||
unsigned int adr;
|
||||
unsigned int bit[3];
|
||||
unsigned long hiword,loword;
|
||||
int Data[3];
|
||||
|
||||
hiword = ECanMbox->MDH.all;
|
||||
loword = ECanMbox->MDL.all;
|
||||
|
||||
adr = (hiword >> 16);
|
||||
|
||||
bit[0] = adr & 0x8000;
|
||||
bit[1] = adr & 0x4000;
|
||||
bit[2] = adr & 0x2000;
|
||||
|
||||
adr &= 0x1fff;
|
||||
|
||||
Data[0] = (hiword ) & 0xffff;
|
||||
Data[1] = (loword>>16) & 0xffff;
|
||||
Data[2] = (loword ) & 0xffff;
|
||||
|
||||
if(bit[0]) if(adr < ANSWER_LEN) Modbus[adr].all = Data[0]; adr++;
|
||||
if(bit[1]) if(adr < ANSWER_LEN) Modbus[adr].all = Data[1]; adr++;
|
||||
if(bit[2]) if(adr < ANSWER_LEN) Modbus[adr].all = Data[2];
|
||||
|
||||
if(Desk==dsk_COMM) GpioDataRegs.GPBTOGGLE.bit.GPIO49=1;
|
||||
else
|
||||
led2_toggle();
|
||||
}
|
||||
|
||||
interrupt void CANa_handler(void)
|
||||
{
|
||||
unsigned long mask=1;
|
||||
int box;
|
||||
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG95; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
box = ECanaRegs.CANGIF0.bit.MIV0;
|
||||
mask <<= box;
|
||||
ECanaRegs.CANRMP.all = mask;
|
||||
|
||||
Handlai(&ECanaMboxes.MBOX0 + box);
|
||||
|
||||
PieCtrlRegs.PIEACK.bit.ACK9 |= 1;
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
}
|
||||
|
||||
interrupt void CANa_reset_err(void)
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG96; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
ECanaRegs.CANTRR.all = 1;
|
||||
CanTimeOutErrorTR++;
|
||||
|
||||
PieCtrlRegs.PIEACK.bit.ACK9 |= 1;
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
}
|
||||
|
||||
interrupt void CANb_handler(void)
|
||||
{
|
||||
#ifdef TUBER
|
||||
unsigned long mask=1;
|
||||
int box;
|
||||
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG97; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
box = ECanbRegs.CANGIF0.bit.MIV0;
|
||||
mask <<= box;
|
||||
ECanbRegs.CANRMP.all = mask;
|
||||
|
||||
Handlai(&ECanbMboxes.MBOX0 + box);
|
||||
|
||||
PieCtrlRegs.PIEACK.bit.ACK9 |= 1;
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
#endif
|
||||
}
|
||||
|
||||
interrupt void CANb_reset_err(void)
|
||||
{
|
||||
#ifdef TUBER
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG98; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
ECanbRegs.CANTRR.all = 1;
|
||||
CanTimeOutErrorTR++;
|
||||
|
||||
PieCtrlRegs.PIEACK.bit.ACK9 |= 1;
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
#endif
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
// No more.
|
||||
//===========================================================================
|
||||
3
ecan.h
Normal file
3
ecan.h
Normal file
@@ -0,0 +1,3 @@
|
||||
void Init_Can(int Port, int DevNum);
|
||||
void CAN_send(int Port, int data[], int Addr);
|
||||
extern int CAN_input_data[];
|
||||
19
filter_bat2.c
Normal file
19
filter_bat2.c
Normal file
@@ -0,0 +1,19 @@
|
||||
#include "filter_bat2.h"
|
||||
|
||||
float filterbat(FILTERBAT *b, float InpVarCurr)
|
||||
{
|
||||
float y;
|
||||
|
||||
y = (b->k_0 * (InpVarCurr + (b->i_0*2) + b->i_1)) +
|
||||
(b->k_1 * b->u_0) + (b->k_2 * b->u_1);
|
||||
|
||||
b->u_1=b->u_0;
|
||||
b->u_0=y;
|
||||
b->i_1=b->i_0;
|
||||
b->i_0=InpVarCurr;
|
||||
|
||||
return y;
|
||||
}
|
||||
|
||||
|
||||
|
||||
49
filter_bat2.h
Normal file
49
filter_bat2.h
Normal file
@@ -0,0 +1,49 @@
|
||||
#ifndef _FILTER_BAT2
|
||||
#define _FILTER_BAT2
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define K1_FILTER_BATTER2_1HZ 0.0000096
|
||||
#define K2_FILTER_BATTER2_1HZ 1.94468056
|
||||
#define K3_FILTER_BATTER2_1HZ -0.94471895
|
||||
|
||||
#define K1_FILTER_BATTER2_3HZ 0.00008766
|
||||
#define K2_FILTER_BATTER2_3HZ 1.97347532
|
||||
#define K3_FILTER_BATTER2_3HZ -0.97382594
|
||||
|
||||
#define K1_FILTER_BATTER2_5HZ 0.00024135
|
||||
#define K2_FILTER_BATTER2_5HZ 1.95581276
|
||||
#define K3_FILTER_BATTER2_5HZ -0.95677816
|
||||
|
||||
#define K1_FILTER_BATTER2_10HZ 0.00094411
|
||||
#define K2_FILTER_BATTER2_10HZ 1.91126422
|
||||
#define K3_FILTER_BATTER2_10HZ -0.91504065
|
||||
|
||||
typedef struct { float k_0;
|
||||
float k_1;
|
||||
float k_2;
|
||||
float i_0;
|
||||
float i_1;
|
||||
float i_2;
|
||||
float u_0;
|
||||
float u_1;
|
||||
float u_2;
|
||||
} FILTERBAT;
|
||||
|
||||
|
||||
#define DEF_FILTERBAT { K1_FILTER_BATTER2_5HZ, \
|
||||
K2_FILTER_BATTER2_5HZ, \
|
||||
K3_FILTER_BATTER2_5HZ, \
|
||||
0,0,0,0,0,0}
|
||||
|
||||
float filterbat(FILTERBAT *b, float InpVarCurr);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _FILTER_BAT2 */
|
||||
|
||||
142
i2c.c
Normal file
142
i2c.c
Normal file
@@ -0,0 +1,142 @@
|
||||
#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
|
||||
#include "i2c.h" // Device Headerfile and Examples Include File
|
||||
|
||||
void InitI2CGpio()
|
||||
{
|
||||
|
||||
EALLOW;
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up for GPIO32 (SDAA)
|
||||
GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up for GPIO33 (SCLA)
|
||||
|
||||
/* Set qualification for selected pins to asynch only */
|
||||
// This will select asynch (no qualification) for the selected pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // Asynch input GPIO32 (SDAA)
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input GPIO33 (SCLA)
|
||||
|
||||
/* Configure SCI pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be I2C functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; // Configure GPIO32 for SDAA operation
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1; // Configure GPIO33 for SCLA operation
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
|
||||
void I2CA_Init(void)
|
||||
{
|
||||
InitI2CGpio();
|
||||
|
||||
// Initialize I2C
|
||||
I2caRegs.I2CSAR = 0x0050; // Slave address - EEPROM control code
|
||||
|
||||
I2caRegs.I2CMDR.bit.IRS = 0; // IPSC must be initialized while the I2C module is in reset (IRS = 0 in I2CMDR).
|
||||
#if (CPU_FRQ_150MHZ) // Default - For 150MHz SYSCLKOUT
|
||||
I2caRegs.I2CPSC.all = 14; // Prescaler - need 7-12 Mhz on module clk (150/15 = 10MHz)
|
||||
#endif
|
||||
#if (CPU_FRQ_100MHZ) // For 100 MHz SYSCLKOUT
|
||||
I2caRegs.I2CPSC.all = 9; // Prescaler - need 7-12 Mhz on module clk (100/10 = 10MHz)
|
||||
#endif
|
||||
|
||||
I2caRegs.I2CCLKL = 10; // NOTE: must be non zero
|
||||
I2caRegs.I2CCLKH = 5; // NOTE: must be non zero
|
||||
|
||||
I2caRegs.I2CMDR.all = 0x0000;
|
||||
|
||||
I2caRegs.I2CMDR.bit.MST = 1;
|
||||
|
||||
I2caRegs.I2CMDR.bit.IRS = 1; // Take I2C out of reset
|
||||
// Stop I2C when suspended
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
Uint16 I2CA_WriteData(unsigned int Addr, int Data)
|
||||
{
|
||||
|
||||
// Wait until the STP bit is cleared from any previous master communication.
|
||||
// Clearing of this bit by the module is delayed until after the SCD bit is
|
||||
// set. If this bit is not checked prior to initiating a new message, the
|
||||
// I2C could get confused.
|
||||
if (I2caRegs.I2CMDR.bit.STP == 1)
|
||||
{
|
||||
return I2C_STP_NOT_READY_ERROR;
|
||||
}
|
||||
|
||||
// Check if bus busy
|
||||
if (I2caRegs.I2CSTR.bit.BB == 1)
|
||||
{
|
||||
return I2C_BUS_BUSY_ERROR;
|
||||
}
|
||||
|
||||
// Setup number of bytes to send
|
||||
// MsgBuffer + Address
|
||||
I2caRegs.I2CCNT = 4;
|
||||
|
||||
// Send start as master transmitter
|
||||
I2caRegs.I2CMDR.all = 0x6E20;
|
||||
|
||||
// Setup data to send
|
||||
I2caRegs.I2CDXR = (Addr*2)>>8;
|
||||
while(!I2caRegs.I2CSTR.bit.XRDY);
|
||||
I2caRegs.I2CDXR = (Addr*2);
|
||||
while(!I2caRegs.I2CSTR.bit.XRDY);
|
||||
I2caRegs.I2CDXR = Data>>8;
|
||||
while(!I2caRegs.I2CSTR.bit.XRDY);
|
||||
I2caRegs.I2CDXR = Data;
|
||||
while(!I2caRegs.I2CSTR.bit.XRDY);
|
||||
while(I2caRegs.I2CMDR.bit.STP == 1);
|
||||
while(I2caRegs.I2CSTR.bit.BB == 1);
|
||||
|
||||
return I2C_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
int I2CA_ReadData(unsigned int Addr)
|
||||
{
|
||||
WORDE data;
|
||||
|
||||
// Wait until the STP bit is cleared from any previous master communication.
|
||||
// Clearing of this bit by the module is delayed until after the SCD bit is
|
||||
// set. If this bit is not checked prior to initiating a new message, the
|
||||
// I2C could get confused.
|
||||
if (I2caRegs.I2CMDR.bit.STP == 1)
|
||||
{
|
||||
return I2C_STP_NOT_READY_ERROR;
|
||||
}
|
||||
|
||||
// Check if bus busy
|
||||
if (I2caRegs.I2CSTR.bit.BB == 1)
|
||||
{
|
||||
return I2C_BUS_BUSY_ERROR;
|
||||
}
|
||||
|
||||
I2caRegs.I2CCNT = 2;
|
||||
I2caRegs.I2CMDR.all = 0x6E20; // Send data to setup EEPROM address 0x6620
|
||||
I2caRegs.I2CDXR = (Addr*2)>>8;
|
||||
while(!I2caRegs.I2CSTR.bit.XRDY);
|
||||
I2caRegs.I2CDXR = (Addr*2);
|
||||
while(I2caRegs.I2CMDR.bit.STP == 1);
|
||||
|
||||
I2caRegs.I2CCNT = 2;
|
||||
I2caRegs.I2CMDR.all = 0x6C20; // Send restart as master receiver
|
||||
|
||||
while(!I2caRegs.I2CSTR.bit.RRDY);
|
||||
data.byt.byte_1 = I2caRegs.I2CDRR;
|
||||
while(!I2caRegs.I2CSTR.bit.RRDY);
|
||||
data.byt.byte_0 = I2caRegs.I2CDRR;
|
||||
|
||||
return data.all;
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
// No more.
|
||||
//===========================================================================
|
||||
4
i2c.h
Normal file
4
i2c.h
Normal file
@@ -0,0 +1,4 @@
|
||||
void I2CA_Init(void);
|
||||
Uint16 I2CA_WriteData(unsigned int Addr, int Data);
|
||||
int I2CA_ReadData(unsigned int Addr);
|
||||
|
||||
70
ice.pjt
Normal file
70
ice.pjt
Normal file
@@ -0,0 +1,70 @@
|
||||
; Code Composer Project File, Version 2.0 (do not modify or remove this line)
|
||||
|
||||
[Project Settings]
|
||||
ProjectDir="D:\projects\Dimas\ICE_19_03_2018\"
|
||||
ProjectType=Executable
|
||||
CPUFamily=TMS320C28XX
|
||||
Tool="Compiler"
|
||||
Tool="CustomBuilder"
|
||||
Tool="DspBiosBuilder"
|
||||
Tool="Linker"
|
||||
Config="Debug"
|
||||
Config="Release"
|
||||
|
||||
[Source Files]
|
||||
Source="ADC.c"
|
||||
Source="bios.c"
|
||||
Source="cntrl_adr.c"
|
||||
Source="crc16.c"
|
||||
Source="ecan.c"
|
||||
Source="filter_bat2.c"
|
||||
Source="i2c.c"
|
||||
Source="isolatio.c"
|
||||
Source="main.c"
|
||||
Source="measure.c"
|
||||
Source="message.c"
|
||||
Source="peripher.c"
|
||||
Source="RS485.c"
|
||||
Source="spise2p.c"
|
||||
Source="tools.c"
|
||||
Source="v120\DSP2833x_common\source\DSP2833x_Adc.c"
|
||||
Source="v120\DSP2833x_common\source\DSP2833x_ADC_cal.asm"
|
||||
Source="v120\DSP2833x_common\source\DSP2833x_CpuTimers.c"
|
||||
Source="v120\DSP2833x_common\source\DSP2833x_PieCtrl.c"
|
||||
Source="v120\DSP2833x_common\source\DSP2833x_SWPrioritizedDefaultIsr.c"
|
||||
Source="v120\DSP2833x_common\source\DSP2833x_SWPrioritizedPieVect.c"
|
||||
Source="v120\DSP2833x_common\source\DSP2833x_SysCtrl.c"
|
||||
Source="v120\DSP2833x_common\source\DSP2833x_usDelay.asm"
|
||||
Source="v120\DSP2833x_common\source\DSP2833x_Xintf.c"
|
||||
Source="v120\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c"
|
||||
Source="F28335.cmd"
|
||||
Source="v120\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd"
|
||||
|
||||
["Debug" Settings]
|
||||
FinalBuildCmd=$(Proj_dir)\bin\hex2000.exe $(Proj_dir)\bin\ice.out -boot -sci8 -map $(Proj_dir)\bin\ice.map -o $(Proj_dir)\bin\ice.hex -i
|
||||
FinalBuildCmd=$(Proj_dir)\bin\hex2000.exe $(Proj_dir)\bin\ice.out -boot -sci8 -map $(Proj_dir)\bin\ice.map -o $(Proj_dir)\bin\ice.bin -b
|
||||
|
||||
["Compiler" Settings: "Debug"]
|
||||
Options=-g -pdsw225 -o0 -fr"$(Proj_dir)\Debug" -fs"$(Proj_dir)\Asm" -i"$(Proj_dir)\v120\DSP2833x_headers\include" -i"$(Proj_dir)\v120\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32
|
||||
|
||||
["Compiler" Settings: "Release"]
|
||||
Options=-pdsw225 -o3 -fr"$(Proj_dir)\Release" -d"LARGE_MODEL" -ml -v28
|
||||
|
||||
["Linker" Settings: "Debug"]
|
||||
Options=-c -e_c_int00 -m".\Debug\ice.map" -o".\bin\ice.out" -stack0x3f0 -w -x -l"rts2800_fpu32.lib"
|
||||
|
||||
["Linker" Settings: "Release"]
|
||||
Options=-c -m".\Release\UKSS745.1TMS320F28335.map" -o".\Release\UKSS745.1TMS320F28335.out" -w -x
|
||||
|
||||
["F28335.cmd" Settings: "Debug"]
|
||||
LinkOrder=1
|
||||
|
||||
["F28335.cmd" Settings: "Release"]
|
||||
LinkOrder=1
|
||||
|
||||
["v120\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" Settings: "Debug"]
|
||||
LinkOrder=2
|
||||
|
||||
["v120\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" Settings: "Release"]
|
||||
LinkOrder=1
|
||||
|
||||
268
isolatio.c
Normal file
268
isolatio.c
Normal file
@@ -0,0 +1,268 @@
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_SWPrioritizedIsrLevels.h"
|
||||
|
||||
#include "RS485.h"
|
||||
#include "filter_bat2.h"
|
||||
#include "measure.h"
|
||||
#include "message.h"
|
||||
#include "package.h"
|
||||
#include "peripher.h"
|
||||
#include "crc16.h"
|
||||
#include "isolatio.h"
|
||||
#include <math.h> // Ýòî ÷òîáû ìåðèòü àìïëèòóäó! sqrt áåç ýòîãî áóäåò êðèâ!!!
|
||||
|
||||
OPTOCANAL opt[2];
|
||||
|
||||
ISOLATION iso[2];
|
||||
|
||||
float iso_KOEF[2] = {-0.5, -0.5};
|
||||
|
||||
void init_isolation_struct(void);
|
||||
|
||||
void DCLK(int i, int x)
|
||||
{
|
||||
x=!x;
|
||||
|
||||
if(i)
|
||||
{
|
||||
if(x) GpioDataRegs.GPASET.bit.GPIO26=1;
|
||||
else GpioDataRegs.GPACLEAR.bit.GPIO26=1;
|
||||
}
|
||||
else
|
||||
{
|
||||
if(x) GpioDataRegs.GPBSET.bit.GPIO32=1;
|
||||
else GpioDataRegs.GPBCLEAR.bit.GPIO32=1;
|
||||
} }
|
||||
|
||||
int DIN(int i)
|
||||
{
|
||||
if(i) return !GpioDataRegs.GPBDAT.bit.GPIO52;
|
||||
else return !GpioDataRegs.GPADAT.bit.GPIO23;
|
||||
}
|
||||
|
||||
void BLIN(int i)
|
||||
{
|
||||
if(i) GpioDataRegs.GPBTOGGLE.bit.GPIO53=1;
|
||||
else GpioDataRegs.GPATOGGLE.bit.GPIO24=1;
|
||||
}
|
||||
|
||||
interrupt void cpu_timer1_isr_ISOL(void)
|
||||
{
|
||||
ERROR error;
|
||||
float Riso=0;
|
||||
long numb=0;
|
||||
int i;
|
||||
static unsigned int count_ready=0;
|
||||
|
||||
EALLOW;
|
||||
CpuTimer1.InterruptCount++;
|
||||
IER |= MINT13; // Set "global" priority
|
||||
EINT;
|
||||
EDIS; // This is needed to disable write to EALLOW protected registers
|
||||
|
||||
if(!cReset) ServiceDog();
|
||||
|
||||
if(++CanPowse >= CANPOWSE*2)
|
||||
{
|
||||
CanPowse = 0;
|
||||
CanGO = 1;
|
||||
}
|
||||
|
||||
if(++count_ready >= period_ready)
|
||||
{
|
||||
count_ready=0;
|
||||
|
||||
if((!sig.bit.Error)|(cTestLamp)) toggle_READY();
|
||||
else set_READY();
|
||||
}
|
||||
|
||||
for(i=0;i<2;i++)
|
||||
{
|
||||
iso[i].pause_counter++;
|
||||
|
||||
if(sens_error[i].bit.Bypas)
|
||||
{
|
||||
sens_error[i].all = 0;
|
||||
sens_error[i].bit.Bypas = 1;
|
||||
Modbus[i+DATASTART].all = 0;
|
||||
continue;
|
||||
}
|
||||
|
||||
if(opt[i].Wait)
|
||||
{
|
||||
opt[i].Wait--;
|
||||
opt[i].bit = 0;
|
||||
opt[i].clk = 0;
|
||||
DCLK(i,0);
|
||||
continue;
|
||||
}
|
||||
|
||||
opt[i].clk=!opt[i].clk;
|
||||
DCLK(i,opt[i].clk);
|
||||
if(!opt[i].clk)
|
||||
{
|
||||
opt[i].Numb = (opt[i].Numb<<1) | DIN(i);
|
||||
if(++opt[i].bit>=32)
|
||||
{
|
||||
error.all = 0;
|
||||
|
||||
opt[i].Wait = (TELE_FREQ/1000)*optopowse;
|
||||
opt[!i].Wait =(TELE_FREQ/2000)*optopowse;
|
||||
if(get_crc32(&(opt[i].Numb)))
|
||||
{
|
||||
numb = opt[i].Numb;
|
||||
numb = numb / 256; // óäàëàåì êîíòðîëüíóþ ñóììó
|
||||
|
||||
Riso=numb;
|
||||
/*
|
||||
if(ist[i]) { kff=1; ist[i]=0; }
|
||||
else kff = optofiltr;
|
||||
fRiso[i] += (Riso-fRiso[i])/kff;
|
||||
numb = (long)fRiso[i];
|
||||
*/
|
||||
Modbus[i*2+0x10].all = (int)(numb & 0xFFFF);
|
||||
Modbus[i*2+0x11].all = (int)(numb>>16);
|
||||
|
||||
Riso=numb;
|
||||
Riso = Riso/1024;//256; // ïðåäïîëîæèì
|
||||
|
||||
iso[i].adc_value = Riso; // íà Ëåøèí àëãîðèòì
|
||||
|
||||
Modbus[i+DATASTART].all = Riso; // êàêáå
|
||||
opt[i].ers = 0; BLIN(i);
|
||||
}
|
||||
else
|
||||
{
|
||||
if(++opt[i].ers > 20)
|
||||
{
|
||||
opt[i].ers = 20;
|
||||
error.bit.Tear = 1;
|
||||
} }
|
||||
|
||||
reset_errs(i,error);
|
||||
|
||||
} } }
|
||||
|
||||
sig.all = chk.all;
|
||||
chk.all = 0;
|
||||
|
||||
}
|
||||
void timer_Init()
|
||||
{
|
||||
EALLOW; // This is needed to write to EALLOW protected registers
|
||||
PieVectTable.XINT13 = &cpu_timer1_isr_ISOL;
|
||||
EDIS; // This is needed to disable write to EALLOW protected registers
|
||||
|
||||
ConfigCpuTimer(&CpuTimer1, SYSCLKOUT/1000000, 1000000/TELE_FREQ);
|
||||
CpuTimer1Regs.TCR.all = 0x4020; // Use write-only instruction to set TSS bit = 0
|
||||
IER |= M_INT13;
|
||||
|
||||
period_ready = TELE_FREQ / (READY_FREQ * 2);
|
||||
|
||||
init_isolation_struct();
|
||||
Calcul_Iso_Koef();
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
void Calcul_Iso_Koef()
|
||||
{
|
||||
iso_KOEF[0] = (isoMOM[1]-isoMOM[0]);
|
||||
iso_KOEF[0]/= (isoADC[1]-isoADC[0]);
|
||||
|
||||
iso_KOEF[1] = (isoMOM[3]-isoMOM[2]);
|
||||
iso_KOEF[1]/= (isoADC[3]-isoADC[2]);
|
||||
}
|
||||
|
||||
void init_isolation_struct(void)
|
||||
{
|
||||
int i;
|
||||
int* pint = (int*)iso;
|
||||
int size = sizeof(ISOLATION)/sizeof(int);
|
||||
|
||||
for(i=0; i < size*2; i++) pint[i] = 0;
|
||||
|
||||
iso[1].pause_counter = ISO_PAUSE / 2;
|
||||
}
|
||||
|
||||
#define iso_time_pause 6200
|
||||
|
||||
void isolation_calc(void)
|
||||
{
|
||||
float our_delta;
|
||||
static int i;
|
||||
int k, l, m;
|
||||
int buff[BUFF_LEN];
|
||||
|
||||
for(i=0; i<2; i++)
|
||||
|
||||
if(iso[i].pause_counter > ISO_PAUSE) //Ïîñêîëüêó âñ¸ ìåäëåííî, ñîõðàíàþ çíà÷åíèà ðàç 3 ñåêóíäû
|
||||
{ //÷òîáû íåìüøå îòñ÷¸òîâ ïîïàäàëî, íàâûáðîñû
|
||||
iso[i].pause_counter = 0;
|
||||
|
||||
iso[i].buff[iso[i].buff_position] = iso[i].adc_value;
|
||||
|
||||
// Ýòî èäåò ñîðòèðîâêà âñåãî ìàññèâà äàííûõ ---------------------------
|
||||
|
||||
for (k = 0; k < BUFF_LEN; k++) buff[k] = 0x8000; //minimal int
|
||||
for (k = 0; k <=iso[i].prim_position; k++)
|
||||
{
|
||||
for (l = 0; (l < BUFF_LEN) && (iso[i].buff[k] < buff[l]); l++);
|
||||
if (l < BUFF_LEN)
|
||||
{
|
||||
for (m = BUFF_LEN - 1; (m > l) && (m > 0); m--) buff[m] = buff[m-1];
|
||||
buff[l] = iso[i].buff[k];
|
||||
} }
|
||||
|
||||
// -----------------------------------------------------------------------
|
||||
|
||||
m = (buff[0]+buff[iso[i].prim_position])/2;
|
||||
|
||||
for(k=0; k < iso[i].prim_position; k++) if( buff[k] <= m) break;
|
||||
|
||||
iso[i].max_val = buff[k - 1 - iso[i].cycles];
|
||||
|
||||
iso[i].min_val = buff[k + iso[i].cycles];
|
||||
|
||||
/* Òàê áûëî
|
||||
iso[i].max_val = buff[iso[i].cycles];
|
||||
iso[i].min_val = buff[iso[i].prim_position - iso[i].cycles];
|
||||
*/
|
||||
our_delta = iso[i].max_val - iso[i].min_val;
|
||||
|
||||
|
||||
// Íîâûé àëãîðèòì ñ÷åòà ÌÎìîâ -------------------------------------------
|
||||
|
||||
if(!iso[i].cycles)
|
||||
iso[i].MOms_x_10 = isoMOM[i*2+1];
|
||||
else
|
||||
iso[i].MOms_x_10 = (our_delta-isoADC[i*2]) * iso_KOEF[i] + isoMOM[i*2];
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
Modbus[26+i].all = iso[i].MOms_x_10;
|
||||
Modbus[32+i].all = iso[i].adc_value;
|
||||
Modbus[40+i].all = iso[i].max_val;
|
||||
Modbus[48+i].all = iso[i].min_val;
|
||||
Modbus[56+i].all = our_delta;
|
||||
Modbus[64+i].all = iso[i].prim_position;
|
||||
Modbus[72+i].all = iso[i].buff_position;
|
||||
Modbus[80+i].all = iso[i].cycles;
|
||||
|
||||
//for(j=0;j<35;j++) Modbus[0x20+j].all = iso[i].buff[j];
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
iso[i].buff_position++;
|
||||
|
||||
if(iso[i].cycles < BUFF_CYCLES)
|
||||
{
|
||||
iso[i].prim_position = iso[i].buff_position;
|
||||
iso[i].cycles = iso[i].prim_position / CYCLE_LEN;
|
||||
}
|
||||
else
|
||||
iso[i].prim_position = BUFF_LEN-1;
|
||||
|
||||
if (iso[i].buff_position >= BUFF_LEN) iso[i].buff_position = 0;
|
||||
} }
|
||||
|
||||
54
isolatio.h
Normal file
54
isolatio.h
Normal file
@@ -0,0 +1,54 @@
|
||||
void timer_Init(void);
|
||||
int get_isolatio(void);
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int clk;
|
||||
unsigned int bit;
|
||||
unsigned int ers;
|
||||
unsigned Wait;
|
||||
unsigned long Numb;
|
||||
|
||||
} OPTOCANAL;
|
||||
|
||||
|
||||
// ïðèìåðíî 105 ñåêóíä - ïîëíûé öèêë èçìåðåíèà ñîïðîòèâëåíèà èçîëàöèè, çàðàä êîíäåíñàòîðà òóäà ñþäà
|
||||
#define CYCLE_TIME 105L
|
||||
|
||||
// 3 ñåêóíäû - ïàóçà ìåæäó èçìåðåíèàìè èçîëàöèè
|
||||
#define ISO_TIME 3
|
||||
|
||||
// ñêîëüêî ìåñòà çàíèìàåò â áóôåðå îäèí ïîëíûé öèêë
|
||||
#define CYCLE_LEN (CYCLE_TIME / ISO_TIME)
|
||||
|
||||
// Êîëè÷åñòâî ïîëíûõ öèêëîâ â íàøåì áóôåðå
|
||||
#define BUFF_CYCLES 5
|
||||
|
||||
// âåëè÷èíà áóôåðà äëà õðàíåíèà èçìåðåíèé, ïóñòü â íåãî âëàçèò íåñêîëüêî ïîëíûõ öèêëîâ
|
||||
#define BUFF_LEN (CYCLE_LEN * BUFF_CYCLES)
|
||||
|
||||
#define TELE_FREQ 2000 // Ãö - ÷àñòîòà ïðåðûâàíèà
|
||||
|
||||
#define ISO_PAUSE (ISO_TIME * TELE_FREQ)
|
||||
|
||||
|
||||
typedef struct {
|
||||
int buff[BUFF_LEN];
|
||||
int min_val;
|
||||
int max_val;
|
||||
unsigned int buff_position;
|
||||
unsigned int prim_position;
|
||||
unsigned int cycles;
|
||||
int MOms_x_10;
|
||||
unsigned int pause_counter;
|
||||
int adc_value;
|
||||
|
||||
}ISOLATION;
|
||||
|
||||
extern ISOLATION iso[];
|
||||
|
||||
void isolation_calc(void);
|
||||
void Calcul_Iso_Koef(void);
|
||||
|
||||
|
||||
|
||||
164
kanal.c
Normal file
164
kanal.c
Normal file
@@ -0,0 +1,164 @@
|
||||
#include "DSP2833x_Device.h" // DSP281x Headerfile Include File
|
||||
#include "DSP2833x_SWPrioritizedIsrLevels.h"
|
||||
#include "filter_bat2.h"
|
||||
#include "measure.h"
|
||||
|
||||
#include "RS485.h"
|
||||
#include "message.h"
|
||||
#include "kanal.h"
|
||||
#include "test.h"
|
||||
#include "package.h"
|
||||
#include "tools.h"
|
||||
|
||||
#include "peripher.h"
|
||||
|
||||
int digits[16] = {63,6,91,79,102,109,125,7,127,111,64,0,0,0,121,0};
|
||||
|
||||
void DCLK(int x)
|
||||
{
|
||||
if(x) GpioDataRegs.GPASET.bit.GPIO6=1;
|
||||
else GpioDataRegs.GPACLEAR.bit.GPIO6=1;
|
||||
DSP28x_usDelay(1L);
|
||||
}
|
||||
|
||||
void DOUT(int x)
|
||||
{
|
||||
if(x) GpioDataRegs.GPASET.bit.GPIO8=1;
|
||||
else GpioDataRegs.GPACLEAR.bit.GPIO8=1;
|
||||
DSP28x_usDelay(1L);
|
||||
}
|
||||
|
||||
void RESET()
|
||||
{
|
||||
DCLK(0); DOUT(1);
|
||||
DCLK(0); DOUT(0);
|
||||
}
|
||||
|
||||
void SENDBIT(int x)
|
||||
{
|
||||
DOUT(x); DCLK(1);
|
||||
DOUT(0); DCLK(0);
|
||||
}
|
||||
|
||||
void kanal_Send(int adr, long dat, int dot)
|
||||
{
|
||||
long Word,data,aliq_part,dg[4];
|
||||
int i,j,bit,byt,addr,sgn=0,punkt=0,aliq_len=0,full_len;
|
||||
|
||||
if(adr>1) // Ëàìïî÷êè
|
||||
{
|
||||
Word =dat;
|
||||
}
|
||||
|
||||
else
|
||||
|
||||
{
|
||||
if(dot<0 || dot>13) // Îøèáêà: -Å...
|
||||
{
|
||||
dg[3] = 0xA; dg[2] = 0xE;
|
||||
dg[1] = 0xF; dg[0] = 0xF;
|
||||
punkt = 0x7;
|
||||
}
|
||||
|
||||
else
|
||||
|
||||
{
|
||||
if(dat<0) sgn=1;
|
||||
data = labs(dat);
|
||||
|
||||
aliq_part = data;
|
||||
for(i=0;i<dot;i++) aliq_part/=10;
|
||||
|
||||
dat = aliq_part;
|
||||
while(dat>0)
|
||||
{
|
||||
aliq_len++; dat/=10;
|
||||
}
|
||||
|
||||
if(aliq_len+sgn>4)
|
||||
{
|
||||
if(sgn) dg[3] = 0xA;
|
||||
else dg[3] = 0xF;
|
||||
|
||||
dat = aliq_part;
|
||||
for(i=1;i<aliq_len;i++) dat/=10;
|
||||
|
||||
dg[2] = dat;
|
||||
dg[1] = 0xE;
|
||||
dg[0] = aliq_len-1;
|
||||
punkt=0;
|
||||
}
|
||||
else
|
||||
{
|
||||
dat = data;
|
||||
|
||||
full_len = aliq_len+sgn;
|
||||
if(full_len==0) full_len=1;
|
||||
full_len += dot;
|
||||
|
||||
for(i=0; i<(full_len-4);i++)
|
||||
{
|
||||
dot--; dat/=10;
|
||||
}
|
||||
if(dot<0) dot=0;
|
||||
punkt = 1<<dot;
|
||||
if(punkt==1) punkt=0;
|
||||
|
||||
dg[3] = (dat)/1000;
|
||||
dg[2] = (dat%1000)/100;
|
||||
dg[1] = (dat%100)/10;
|
||||
dg[0] = (dat%10);
|
||||
|
||||
if(dg[0]+dg[1]+dg[2]+dg[3]==0)
|
||||
{
|
||||
punkt=0; dot=0; sgn=0;
|
||||
}
|
||||
|
||||
for(i=3;i>0;i--)
|
||||
{
|
||||
if((dg[i]==0)&&(i!=dot))
|
||||
dg[i]=0xF; // Ýòî çíà÷èò ïóñòî
|
||||
else break;
|
||||
}
|
||||
|
||||
if(sgn)
|
||||
for(i=1;i<4;i++)
|
||||
{
|
||||
if( (dg[i]==0xF)||(i==3))
|
||||
{
|
||||
dg[i]=0xA; // Ýòî çíà÷èò ìèíóñ
|
||||
break;
|
||||
} } } }
|
||||
|
||||
for(i=0;i<4;i++)
|
||||
{
|
||||
dg[i] = digits[dg[i]];
|
||||
if((punkt>>i)&1) dg[i]+= 128;
|
||||
|
||||
}
|
||||
|
||||
Word = ((dg[0] ) & 0x000000FF) | ((dg[1]<<8 ) & 0x0000FF00) |
|
||||
((dg[2]<<16) & 0x00FF0000) | ((dg[3]<<24) & 0xFF000000);
|
||||
}
|
||||
|
||||
for (i=0;i<4;i++)
|
||||
{
|
||||
if(addr>0x10) break;
|
||||
|
||||
for (j=0;j<8;j++)
|
||||
{
|
||||
bit = Word & 1; Word >>= 1;
|
||||
SENDBIT(bit);
|
||||
}
|
||||
|
||||
byt = addr;
|
||||
for (j=0;j<6;j++)
|
||||
{
|
||||
bit = byt & 1; byt >>= 1;
|
||||
SENDBIT(bit);
|
||||
}
|
||||
addr++;
|
||||
|
||||
RESET();
|
||||
}
|
||||
}
|
||||
7
kanal.h
Normal file
7
kanal.h
Normal file
@@ -0,0 +1,7 @@
|
||||
void kanal_Send(int adr, long dat, int dot);
|
||||
|
||||
#define adr_diod1 0x00 // Ïåðâûå 4 äèîäíûõ ïëàòû
|
||||
#define adr_diod2 0x04 // Âòîðûå 4 äèîäíûõ ïëàòû
|
||||
#define adr_digg1 0x08 // Ïåðâûå 4 öèôðû
|
||||
#define adr_digg2 0x0C // Âòîðûå 4 öèôðû
|
||||
#define adr_lamps 0x10 // Ëàìïû
|
||||
34
log_to_mem.c
Normal file
34
log_to_mem.c
Normal file
@@ -0,0 +1,34 @@
|
||||
/****************************************************************/
|
||||
/* TMS320C32 */
|
||||
/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */
|
||||
/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2001ã. */
|
||||
/****************************************************************/
|
||||
/* log_to_mem.c
|
||||
****************************************************************
|
||||
* Çàïèñü ëîãîâ â ïàìyòü *
|
||||
****************************************************************/
|
||||
|
||||
#include "log_to_mem.h"
|
||||
|
||||
int no_write = 1,
|
||||
never_write = 0; // Ôëàãè, ÷òîáû íå ïèñàòü (åñëè ÷òî)
|
||||
|
||||
#pragma DATA_SECTION(logs_block,".logg");
|
||||
unsigned int logs_block[0xF000];
|
||||
|
||||
LOG Log;
|
||||
unsigned int flog=0;
|
||||
|
||||
// Î÷èùåíèå ïàìàòè, ãäå ëîãè ëåæàò
|
||||
void clear_mem()
|
||||
{
|
||||
unsigned long i;
|
||||
|
||||
Log.Start = LOG_PAGE_START;
|
||||
Log.Finis = LOG_PAGE_START + LOG_PAGE_LEN;
|
||||
Log.Adres = Log.Start;
|
||||
Log.Circl = 0;
|
||||
|
||||
for (i=Log.Start; i<Log.Finis; i++)
|
||||
*(volatile int *)i = 0;
|
||||
}
|
||||
48
log_to_mem.h
Normal file
48
log_to_mem.h
Normal file
@@ -0,0 +1,48 @@
|
||||
/****************************************************************/
|
||||
/* TMS320C32 */
|
||||
/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */
|
||||
/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2001ã. */
|
||||
/****************************************************************/
|
||||
/* log_to_mem.h
|
||||
****************************************************************
|
||||
* Çàïèñü ëîãîâ â ïàìyòü *
|
||||
****************************************************************/
|
||||
|
||||
#ifndef _LOG_TO_MEM
|
||||
#define _LOG_TO_MEM
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Îïðåäåëåíèa äëa ðàáîòû ëîããåðà */
|
||||
#define LOG_PAGE_START 0x0200000
|
||||
#define LOG_PAGE_LEN 0xF000
|
||||
|
||||
extern int no_write, never_write; // Ôëàãè, ÷òîáû íå ïèñàòü (åñëè ÷òî)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned long Start;
|
||||
unsigned long Finis;
|
||||
unsigned long Adres;
|
||||
unsigned int Circl;
|
||||
|
||||
} LOG;
|
||||
|
||||
extern LOG Log;
|
||||
|
||||
/* Çàïèñü ñëîâa â ïàìàòü, ãäå ëîãè ëåæàò */
|
||||
#define Log_to_mem(x) *(int *)(Log.Adres++) = x
|
||||
|
||||
/* Ïðîâåðêà ãðàíèöû ïàìàòè äëà ëîãîâ */
|
||||
#define Test_mem_limit(x) if(Log.Adres > (Log.Finis - x)) Log.Adres = Log.Start
|
||||
|
||||
/* Î÷èñòêà ïàìàòè (îáíóëåíèå) */
|
||||
void clear_mem();
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _LOG_TO_MEM */
|
||||
220
main.c
Normal file
220
main.c
Normal file
@@ -0,0 +1,220 @@
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
|
||||
#include "cntrl_adr.h"
|
||||
#include "RS485.h"
|
||||
#include "BIOS_DSP.h"
|
||||
#include "filter_bat2.h"
|
||||
#include "measure.h"
|
||||
#include "Message.h"
|
||||
#include "package.h"
|
||||
|
||||
#include "spise2p.h"
|
||||
#include "i2c.h"
|
||||
|
||||
#include "tools.h"
|
||||
#include "peripher.h"
|
||||
#include "ADC.h"
|
||||
|
||||
#include "ecan.h"
|
||||
#include "log_to_mem.h"
|
||||
|
||||
#include "measure.h"
|
||||
#include "isolatio.h"
|
||||
|
||||
extern void DSP28x_usDelay(Uint32 Count);
|
||||
|
||||
void main()
|
||||
{
|
||||
int i,j,mask;
|
||||
static int cancount[2],cancell[2];
|
||||
RS_DATA * rs;
|
||||
|
||||
InitSysCtrl();
|
||||
|
||||
// Disable CPU interrupts and clear all CPU interrupt flags:
|
||||
DINT;
|
||||
|
||||
InitPieCtrl();
|
||||
|
||||
IER = 0x0000;
|
||||
IFR = 0x0000;
|
||||
|
||||
InitPieVectTable();
|
||||
|
||||
init_zone7();
|
||||
|
||||
setup_leds_line();
|
||||
led1_on();
|
||||
led2_off();
|
||||
for (i=0;i<10;i++)
|
||||
{
|
||||
pause_us(50000);
|
||||
led2_toggle();
|
||||
led1_toggle();
|
||||
}
|
||||
led1_off();
|
||||
led2_off();
|
||||
|
||||
get_Mode();
|
||||
set_cntrl_addr(Mode,16);
|
||||
create_uart_vars(sizeof(CMD_TO_TMS));
|
||||
setup_uart(COM_1,115200);
|
||||
setup_uart(COM_2,115200);
|
||||
Init_Can(0,Addrr);
|
||||
Init_Seeprom();
|
||||
// clear_mem();
|
||||
|
||||
EnableInterrupts();
|
||||
|
||||
if(Desk!=dsk_ISOL)
|
||||
{
|
||||
setup_adc();
|
||||
Init_sensors();
|
||||
I2CA_Init(); pause_us(500000);
|
||||
Load_caliber();
|
||||
}
|
||||
else
|
||||
{
|
||||
// timer_Init();
|
||||
Init_optic();
|
||||
}
|
||||
|
||||
Load_params();
|
||||
Init_packMask();
|
||||
|
||||
if(Desk==dsk_ISOL)
|
||||
{
|
||||
timer_Init();
|
||||
// Init_optic();
|
||||
}
|
||||
|
||||
|
||||
LastMode = Addrr;
|
||||
|
||||
for(i=0;i<3;i++)
|
||||
{
|
||||
cancount[i]= 0;
|
||||
cancell[i] = CAN_send_start;
|
||||
}
|
||||
|
||||
EALLOW;
|
||||
SysCtrlRegs.WDCR= 0x2F;
|
||||
EDIS;
|
||||
|
||||
MAY=1;
|
||||
|
||||
while(1)
|
||||
{
|
||||
if(CanGO)
|
||||
{
|
||||
CanGO=0;
|
||||
for(i=0;i<2;i++)
|
||||
if(Cancount[i])
|
||||
if(++cancount[i] >= Cancount[i])
|
||||
if(cancount[0])
|
||||
{
|
||||
cancount[i] = 0;
|
||||
while(1)
|
||||
{
|
||||
if(cancell[i] >= 0x80) cancell[i]=0;
|
||||
mask = Maska[i][cancell[i]/16] >> (cancell[i]%16);
|
||||
if(!mask) cancell[i] = (cancell[i] + 0x10) & 0xFFF0;
|
||||
else
|
||||
{
|
||||
while(!(mask & 1))
|
||||
{
|
||||
cancell[i]++; mask >>= 1;
|
||||
}
|
||||
break;
|
||||
} }
|
||||
CAN_send(0,(int *)Modbus,cancell[i]);
|
||||
cancell[i]+=3;
|
||||
} }
|
||||
/*
|
||||
CanGO=0;
|
||||
for(i=0;i<3;i++)
|
||||
{
|
||||
if(cancount[i]) cancount[i]--;
|
||||
else
|
||||
{
|
||||
cancount[i] = Cancount[i]; circ[i] = 0;
|
||||
|
||||
while( !((Maska[i][cancell[i]/16]>>(cancell[i]%16))&1) && circ[i] < 2 )
|
||||
if(cancell[i]>CAN_send_finis)
|
||||
{
|
||||
cancell[i] = CAN_send_start; circ[i]++;
|
||||
}
|
||||
else cancell[i]++;
|
||||
|
||||
if(cancell[i]<=CAN_send_finis && circ[i] < 2)
|
||||
{
|
||||
CAN_send(0,(int *)Modbus,cancell[i]);
|
||||
cancell[i]+=3;
|
||||
} } } }
|
||||
*/
|
||||
if(cSaveParam)
|
||||
{
|
||||
cSaveParam=0;
|
||||
Save_params();
|
||||
}
|
||||
|
||||
if(cReadCal)
|
||||
{
|
||||
cReadCal=0;
|
||||
Load_caliber();
|
||||
}
|
||||
|
||||
if(cDefParam)
|
||||
{
|
||||
cDefParam=0;
|
||||
Default_params();
|
||||
}
|
||||
|
||||
if(cKoefCalc)
|
||||
{
|
||||
cKoefCalc=0;
|
||||
Calcul_Iso_Koef();
|
||||
}
|
||||
|
||||
get_Inputs();
|
||||
|
||||
if(Desk!=dsk_SHKF)
|
||||
{
|
||||
Modbus[23].all = Inputs.wrd.word_0;
|
||||
}
|
||||
|
||||
if(Desk==dsk_ISOL)
|
||||
{
|
||||
IsShimON = cShimON;
|
||||
if(!cShimON)
|
||||
isolation_calc();
|
||||
}
|
||||
|
||||
for(i=0;i<2;i++)
|
||||
{
|
||||
if(i) rs = &rs_a;
|
||||
else rs = &rs_b;
|
||||
|
||||
j = get_command(rs);
|
||||
|
||||
if(j!=-1)
|
||||
switch(j)
|
||||
{
|
||||
case CMD_INIT: init(rs); led2_toggle();break; // íà÷àëüíûå óñòàíîâêè
|
||||
case CMD_INITLOAD: initload(rs); led2_toggle();break; // íàñòðîéêà çàãðóçêè
|
||||
case CMD_RUN: run(rs); led2_toggle();break; // çàãðóçèòü áëîê
|
||||
case CMD_LOAD: load(rs); led2_toggle();break; // çàãðóçèòü áëîê
|
||||
case CMD_PEEK: peek(rs); led2_toggle();break; // ïðî÷èòàòü à÷åéêó ïàìàòè
|
||||
case CMD_POKE: poke(rs); led2_toggle();break; // çàïèñàòü â à÷åéêó ïàìàòè
|
||||
case CMD_UPLOAD: upload(rs); led2_toggle();break; // ïåðåäàòü áëîê ïàìàòè
|
||||
case CMD_EXTEND: extendbios(rs); led2_toggle();break; // ðàñøèðåííûå êîìàíäû äëà áèîñà
|
||||
|
||||
case CMD_TFLASH: tflash(rs); led2_toggle();break; // ïðîøèòü TMS
|
||||
|
||||
// case CMD_STD: ReceiveCommand(rs); led2_toggle();break;
|
||||
case CMD_MODBUS_3: ReceiveCommandModbus3(rs); led2_toggle();break;
|
||||
case CMD_MODBUS_6: ReceiveCommandModbus6(rs); led2_toggle();break;
|
||||
|
||||
default: break;
|
||||
} } } }
|
||||
|
||||
673
measure.c
Normal file
673
measure.c
Normal file
@@ -0,0 +1,673 @@
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_SWPrioritizedIsrLevels.h"
|
||||
#include "filter_bat2.h"
|
||||
#include "package.h"
|
||||
|
||||
#include "measure.h"
|
||||
#include "package.h"
|
||||
|
||||
#include "peripher.h"
|
||||
#include "ADC.h"
|
||||
|
||||
#include "RS485.h"
|
||||
#include "message.h"
|
||||
#include "log_to_mem.h"
|
||||
|
||||
#include <math.h> // Ýòî ÷òîáû ìåðèòü àìïëèòóäó! sqrt áåç ýòîãî áóäåò êðèâ!!!
|
||||
|
||||
unsigned int CanPowse,CanGO;
|
||||
|
||||
int MAX_TPL_CANAL=0; // Êîëè÷åñòâî òåìïåðàòóðíûõ êàíàëîâ
|
||||
int period_ready, period_blink, period_dac, time_dac;
|
||||
|
||||
FLAG chk,sig;
|
||||
long time_1_5sec, time_5msec, time_5sec;
|
||||
|
||||
long err_count[6];
|
||||
float lev_count[6];
|
||||
|
||||
int sens_type[24];
|
||||
int sens_pair[24];
|
||||
long din_count[32];
|
||||
|
||||
int adc0[24];
|
||||
int tmp0[24];
|
||||
float tmpK[24];
|
||||
|
||||
FILTERBAT def_FILTERBAT = DEF_FILTERBAT;
|
||||
FILTERBAT filter[40];
|
||||
|
||||
long sens_count[28];
|
||||
|
||||
interrupt void cpu_timer1_isr_SENS(void);
|
||||
|
||||
/********************************************************************/
|
||||
/* Ðàñ÷åò ìîäóëà òîêà èç ïîêàçàíèé äâóõ ôàç */
|
||||
/********************************************************************/
|
||||
float im_calc(float ia,float ib)
|
||||
{
|
||||
float isa,isb;
|
||||
|
||||
isa = - 1.5 * (ia + ib);
|
||||
isb = COSPi6 * (ia - ib);
|
||||
return (2*sqrt(isa*isa+isb*isb)/3);
|
||||
}
|
||||
|
||||
|
||||
interrupt void cpu_timer1_isr_SENS(void)
|
||||
{
|
||||
static unsigned int
|
||||
count_ready=0, count_blink=0, count_bright=0, count_mode,
|
||||
blink_over, blink_alarm, work_lamp, heat_lamp, errr_lamp;
|
||||
|
||||
EALLOW;
|
||||
CpuTimer1.InterruptCount++;
|
||||
IER |= MINT13; // Set "global" priority
|
||||
EINT;
|
||||
EDIS; // This is needed to disable write to EALLOW protected registers
|
||||
|
||||
if(!cReset) ServiceDog();
|
||||
|
||||
if(++count_ready >= period_ready)
|
||||
{
|
||||
count_ready=0;
|
||||
|
||||
if((!sig.bit.Error)|(cTestLamp)) toggle_READY();
|
||||
else set_READY();
|
||||
}
|
||||
|
||||
if(++CanPowse >= CANPOWSE)
|
||||
{
|
||||
CanPowse = 0;
|
||||
CanGO = 1;
|
||||
}
|
||||
|
||||
if(++count_bright == maximum_bright)
|
||||
{
|
||||
count_bright = 0 ;
|
||||
|
||||
if(Desk==dsk_COMM)
|
||||
{
|
||||
if(work_lamp) GpioDataRegs.GPBCLEAR.bit.GPIO60=1;
|
||||
else GpioDataRegs.GPBSET.bit.GPIO60=1;
|
||||
if(heat_lamp) GpioDataRegs.GPBCLEAR.bit.GPIO58=1;
|
||||
else GpioDataRegs.GPBSET.bit.GPIO58=1;
|
||||
if(errr_lamp) GpioDataRegs.GPBCLEAR.bit.GPIO62=1;
|
||||
else GpioDataRegs.GPBSET.bit.GPIO62=1;
|
||||
}
|
||||
|
||||
if(Mode==adr_SHKF)
|
||||
{
|
||||
if(work_lamp) GpioDataRegs.GPBCLEAR.bit.GPIO62=1;
|
||||
else GpioDataRegs.GPBSET.bit.GPIO62=1;
|
||||
} }
|
||||
|
||||
if(count_bright == Brightness)
|
||||
{
|
||||
if(Desk==dsk_COMM)
|
||||
{
|
||||
GpioDataRegs.GPBSET.bit.GPIO60=1;
|
||||
GpioDataRegs.GPBSET.bit.GPIO58=1;
|
||||
GpioDataRegs.GPBSET.bit.GPIO62=1;
|
||||
}
|
||||
|
||||
if(Desk==dsk_SHKF)
|
||||
{
|
||||
GpioDataRegs.GPBSET.bit.GPIO62=1;
|
||||
} }
|
||||
|
||||
if(++count_blink >= period_blink)
|
||||
{
|
||||
count_blink=0;
|
||||
count_mode++;
|
||||
blink_over = (count_mode & 1)?1:0;
|
||||
blink_alarm = (count_mode & 7)?1:0;
|
||||
|
||||
if(cExtLamp)
|
||||
{
|
||||
work_lamp = cExtLite;
|
||||
heat_lamp = cExtLite;
|
||||
errr_lamp = cExtLite;
|
||||
}
|
||||
else
|
||||
{
|
||||
if(cTestLamp)
|
||||
{
|
||||
work_lamp = blink_over;
|
||||
heat_lamp = blink_over;
|
||||
errr_lamp = blink_over;
|
||||
}
|
||||
else
|
||||
{
|
||||
if(Mode==adr_SHKF)
|
||||
{
|
||||
if(sig.bit.Error) work_lamp = blink_over;
|
||||
else work_lamp = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
if(sig.bit.Error) work_lamp = 0;//blink_over;
|
||||
// else if(sig.bit.Alarm) work_lamp = blink_alarm;
|
||||
else work_lamp = 1;
|
||||
|
||||
if(sig.bit.OverHeat) heat_lamp = 1;
|
||||
else if(sig.bit.SubHeat) heat_lamp = blink_over;
|
||||
else if(sig.bit.OutHeat) heat_lamp = !blink_alarm;
|
||||
else heat_lamp = 0;
|
||||
} } } } }
|
||||
|
||||
void Init_optic()
|
||||
{
|
||||
int i;
|
||||
|
||||
for(i=0;i<24;i++)
|
||||
{
|
||||
sens_type[i]=0;
|
||||
sens_pair[i]=i;
|
||||
}
|
||||
|
||||
// sens_type[2] = OPTIC;
|
||||
// sens_type[3] = OPTIC;
|
||||
}
|
||||
|
||||
void Init_sensors()
|
||||
{
|
||||
int i;
|
||||
|
||||
EALLOW; // This is needed to write to EALLOW protected registers
|
||||
PieVectTable.XINT13 = &cpu_timer1_isr_SENS;
|
||||
EDIS; // This is needed to disable write to EALLOW protected registers
|
||||
|
||||
ConfigCpuTimer(&CpuTimer1, (SYSCLKOUT/1000000), 1000000/SIG_FREQ);
|
||||
CpuTimer1Regs.TCR.all = 0x4020; // Use write-only instruction to set TSS bit = 0
|
||||
IER |= M_INT13;
|
||||
|
||||
period_ready = SIG_FREQ / (READY_FREQ * 2);
|
||||
period_blink = SIG_FREQ / (BLINK_FREQ * 2);
|
||||
|
||||
period_dac = SIG_FREQ / (DAC_FREQ);
|
||||
time_dac = LOAD_TIME * DAC_FREQ;
|
||||
|
||||
time_1_5sec = (3 * ADC_FREQ) / 2;
|
||||
time_5msec = (5 * ADC_FREQ) / 1000;
|
||||
time_5sec = (5 * ADC_FREQ);
|
||||
|
||||
for(i=0;i<24;i++)
|
||||
{
|
||||
sens_type[i]=0;
|
||||
sens_pair[i]=i;
|
||||
}
|
||||
|
||||
if((Mode==adr_REC1)||(Mode==adr_REC2))
|
||||
{
|
||||
sens_type[0]=TERMO_AD;
|
||||
sens_type[1]=TERMO_AD;
|
||||
sens_type[2]=TERMO_AD;
|
||||
sens_type[3]=TERMO_AD;
|
||||
|
||||
sens_type[4]=TERMO_AD;
|
||||
sens_type[5]=TERMO_AD;
|
||||
|
||||
//sens_type[6]=TERMO_AD;
|
||||
//sens_type[7]=TERMO_AD;
|
||||
|
||||
|
||||
sens_type[8]=TERMO_RS;
|
||||
sens_type[9]=TERMO_RS;
|
||||
sens_type[10]=TERMO_RS;
|
||||
sens_type[11]=TERMO_RS;
|
||||
|
||||
sens_type[12]=VOLTAGE; sens_pair[12]=13;
|
||||
sens_type[13]=VOLTAGE; sens_pair[13]=12;
|
||||
sens_type[14]=VOLTAGE; sens_pair[14]=15;
|
||||
sens_type[15]=VOLTAGE; sens_pair[15]=14;
|
||||
|
||||
Modbus[12].bit.bitE = 1; // Ignore
|
||||
Modbus[13].bit.bitE = 1; // Ignore
|
||||
Modbus[14].bit.bitE = 1; // Ignore
|
||||
Modbus[15].bit.bitE = 1; // Ignore
|
||||
}
|
||||
|
||||
if((Mode==adr_INV1)||(Mode==adr_INV2))
|
||||
{
|
||||
sens_type[0]=TERMO_AD;
|
||||
sens_type[1]=TERMO_AD;
|
||||
sens_type[2]=TERMO_AD;
|
||||
sens_type[3]=TERMO_AD;
|
||||
|
||||
sens_type[4]=TERMO_AD;
|
||||
sens_type[5]=TERMO_AD;
|
||||
//sens_type[6]=TERMO_AD;
|
||||
|
||||
sens_type[7]=TERMO_RS;
|
||||
sens_type[8]=TERMO_RS;
|
||||
sens_type[9]=TERMO_RS;
|
||||
sens_type[10]=TERMO_RS;
|
||||
sens_type[11]=TERMO_RS;
|
||||
}
|
||||
|
||||
if(Mode==adr_SHKF)
|
||||
{
|
||||
sens_type[0 ] = POWER_380; sens_pair[0]=1;
|
||||
sens_type[1 ] = POWER_380; sens_pair[1]=0;
|
||||
sens_type[2 ] = POWER_220; sens_pair[2]=3;
|
||||
sens_type[3 ] = POWER_220; sens_pair[3]=2;
|
||||
sens_type[4 ] = POWER_31;
|
||||
sens_type[5 ] = POWER_31;
|
||||
sens_type[6 ] = POWER_24;
|
||||
sens_type[7 ] = POWER_24;
|
||||
sens_type[8 ] = POWER_24;
|
||||
sens_type[9 ] = POWER_24;
|
||||
sens_type[10] = POWER_24;
|
||||
sens_type[11] = POWER_24;
|
||||
sens_type[12] = POWER_15;
|
||||
sens_type[13] = TERMO_AD;
|
||||
sens_type[14] = TERMO_AD;
|
||||
sens_type[15] = VIRT_24;
|
||||
sens_type[16] = VIRT_24;
|
||||
}
|
||||
|
||||
for(i=0;i<4; i++) err_count[i] = 0;
|
||||
for(i=0;i<6; i++) lev_count[i] = 0;
|
||||
for(i=0;i<28;i++) sens_count[i] = 0;
|
||||
for(i=0;i<32;i++) din_count[i] = 0;
|
||||
for(i=0;i<40;i++) filter[i] = def_FILTERBAT;
|
||||
|
||||
for(i=0;i<DATASTART;i++) Modbus[i].all &= NOER;
|
||||
|
||||
MAX_TPL_CANAL = 12;
|
||||
}
|
||||
|
||||
void Init_packMask()
|
||||
{
|
||||
int i,j;
|
||||
|
||||
for(i=0;i<2; i++)
|
||||
for(j=0;j<8;j++) { Maska[i][j]=0; }
|
||||
|
||||
for(i=0;i<24;i++)
|
||||
if(sens_type[i])
|
||||
{
|
||||
Maska[0][ i /16]|=(1<<( i %16));
|
||||
Maska[0][(i+24)/16]|=(1<<((i+24)%16));
|
||||
}
|
||||
|
||||
for(i=0;i<3; i++)
|
||||
Maska[1][i+3] = Maska[0][i];
|
||||
|
||||
if(Desk==dsk_COMM) Maska[0][1]|=0x80; // OilSensor, ButtsPressed
|
||||
|
||||
if(Desk==dsk_ISOL)
|
||||
{
|
||||
Maska[0][0]|=0x0007; // optic answers and shim is on
|
||||
Maska[0][1]|=0x0F8F; // raw data and result MOhm
|
||||
Maska[0][2]|=0x0300; // max values
|
||||
Maska[0][3]|=0x0003; // min values
|
||||
Maska[0][5]|=0x0003; // cycles (ready)
|
||||
Maska[1][7]|=0x0F0F; // caliber
|
||||
}
|
||||
|
||||
Maska[1][6] |= 0x0073;
|
||||
Maska[1][7] |= 0xE000;
|
||||
}
|
||||
|
||||
int er_anal(int term, long * count, int edge, int pre)
|
||||
{
|
||||
if (term)
|
||||
{
|
||||
if((*count)>=edge) return 1;
|
||||
(*count)++; return pre;
|
||||
}
|
||||
if( (*count) == 0 ) return 0;
|
||||
(*count)--; return pre;
|
||||
}
|
||||
|
||||
void reset_errs(int sens, ERROR er)
|
||||
{
|
||||
// unsigned long report;
|
||||
unsigned int set;
|
||||
ERROR err;
|
||||
|
||||
err=er;
|
||||
|
||||
if(!sens_error[sens].bit.Latch)
|
||||
{
|
||||
set = sens_error[sens].all & NOER;
|
||||
sens_error[sens].all = err.all | set;
|
||||
}
|
||||
else
|
||||
{
|
||||
sens_error[sens].all |= err.all;
|
||||
}
|
||||
sens_error[sens].bit.Ready = !(err.bit.Stop && (!sens_error[sens].bit.Ignor));
|
||||
chk.bit.Error|= !(sens_error[sens].bit.Ready);
|
||||
}
|
||||
|
||||
|
||||
ERROR control_ADC(int sens, int number, int zero)
|
||||
{
|
||||
ERROR err;
|
||||
int erwait;
|
||||
|
||||
err.all = 0;
|
||||
|
||||
if(TermoSW) erwait = SENS_ERR_WAIT;
|
||||
else erwait = ADC_FREQ;
|
||||
|
||||
// Êàíàë îáîðâàí
|
||||
if(er_anal(((number <= zero)||(number >= (0x0FFF-(zero/100)))),
|
||||
&sens_count[sens],erwait,
|
||||
sens_error[sens].bit.Tear))
|
||||
{
|
||||
err.bit.Tear = 1;
|
||||
}
|
||||
/*
|
||||
// ÀÖÏ çàëèï
|
||||
if(er_anal( (sens_prev[sens] == number),
|
||||
&sens_count[sens][1],ADC_FREQ,
|
||||
sens_error[sens].bit.Stick))
|
||||
{
|
||||
err.bit.Stick = 1;
|
||||
}
|
||||
sens_prev[sens] = number;
|
||||
*/
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
int input_freq(int chan, int Volt)
|
||||
{
|
||||
static int prevolt[4],tics[4],tacs[4],tic[4],tac[4];
|
||||
static long Freq = 0;
|
||||
int i,sum=0,bum=0;
|
||||
|
||||
if(Volt >= Zero_lev[chan])
|
||||
if(prevolt[chan]< Zero_lev[chan])
|
||||
{
|
||||
tics[chan] = tic[chan]; tic[chan] = 0; bum = 1;
|
||||
}
|
||||
|
||||
if(Volt < Zero_lev[chan])
|
||||
if(prevolt[chan]>= Zero_lev[chan])
|
||||
{
|
||||
tacs[chan] = tac[chan]; tac[chan] = 0; bum = 1;
|
||||
}
|
||||
|
||||
if(bum)
|
||||
{
|
||||
for(i=0;i<4;i++) sum += tics[i] + tacs[i];
|
||||
Freq = (80L * ADC_FREQ) / sum;
|
||||
}
|
||||
|
||||
prevolt[chan] = Volt;
|
||||
tic[chan]++;
|
||||
tac[chan]++;
|
||||
|
||||
return Freq;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
void Current_count(int sens)
|
||||
{
|
||||
float Numb,Current,fAmpl;
|
||||
static float aCurrent,Amplitude;
|
||||
static int prezer0=0;
|
||||
int chan, pair, ist, thrd, i, ignor;
|
||||
int freq=0;
|
||||
|
||||
ERROR error;
|
||||
|
||||
error.all = 0;
|
||||
|
||||
chan = sens - MAX_TPL_CANAL;
|
||||
pair = sens_pair[sens] - MAX_TPL_CANAL;
|
||||
ist = !(chan & 1);
|
||||
thrd= (chan >>1) + 4;
|
||||
|
||||
if(sens_error[sens].bit.Bypas)
|
||||
{
|
||||
sens_error[sens].all = 0;
|
||||
sens_error[sens].bit.Bypas = 1;
|
||||
Modbus[sens+DATASTART].all = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
Numb = ADC_table[sens];
|
||||
|
||||
if(cTermoCal||cSetZero)
|
||||
{
|
||||
if(!prezer0)
|
||||
for(i=0;i<4;i++) lev_count[i] = Numb;
|
||||
lev_count[chan] += (Numb-lev_count[chan])/1000.0;
|
||||
adc0[sens] = (int)(filterbat(&filter[sens],lev_count[chan]));
|
||||
Zero_lev[chan] = adc0[sens];
|
||||
Modbus[sens+DATASTART].all = adc0[sens];
|
||||
}
|
||||
prezer0 = (cTermoCal||cSetZero);
|
||||
|
||||
Current = (Numb - adc0[sens]) * tmpK[sens];
|
||||
|
||||
if(!(cTermoCal||cSetZero))
|
||||
{
|
||||
freq = input_freq(chan,Numb);
|
||||
|
||||
|
||||
lev_count[chan] += (fabs(Current)-lev_count[chan])/1000.0;
|
||||
|
||||
// Çàïîìíèì
|
||||
if(ist)
|
||||
{
|
||||
aCurrent = -Current; // Çàïîìíèëè ìãíîâåííîå çíà÷åíèå - äëà àìïëèòóäû
|
||||
}
|
||||
else
|
||||
{
|
||||
// Âû÷èñëåíèå àìïëèòóäû
|
||||
Amplitude = im_calc(Current,aCurrent);
|
||||
fAmpl = filterbat(&filter[sens],Amplitude);
|
||||
|
||||
if(fAmpl<100)
|
||||
{
|
||||
fAmpl=0; freq=0;
|
||||
}
|
||||
|
||||
|
||||
// Modbus[sens+DATASTART-1].all = (int)fAmpl;//(int)Amplitude;
|
||||
Modbus[sens+DATASTART-1].all = (int)(fAmpl/RADIX2);
|
||||
|
||||
// Òðåòüà ôàçà äëà ïðîâåðîê
|
||||
lev_count[thrd] += (fabs(-Current-aCurrent)-lev_count[thrd])/1000.0;
|
||||
|
||||
i=(8-((sens+DATASTART-1)%8));
|
||||
Modbus[sens+DATASTART+i-1+(thrd-4)*3].all = lev_count[chan];
|
||||
Modbus[sens+DATASTART+i +(thrd-4)*3].all = lev_count[pair];
|
||||
Modbus[sens+DATASTART+i+1+(thrd-4)*3].all = lev_count[thrd];
|
||||
|
||||
}
|
||||
|
||||
Modbus[sens+DATASTART].all = freq;
|
||||
|
||||
// Çàøèòû!
|
||||
if(Current > 1.1 * sens_hi_edge[sens])
|
||||
{
|
||||
error.bit.Hyper = 1;
|
||||
error.bit.Stop = 1;
|
||||
}
|
||||
|
||||
Numb = lev_count[chan];
|
||||
if(Numb<lev_count[pair]) Numb = lev_count[pair];
|
||||
if(Numb<lev_count[thrd]) Numb = lev_count[thrd];
|
||||
|
||||
ignor = sens_error[sens].bit.Ignor;
|
||||
|
||||
|
||||
if(er_anal( ((Numb-lev_count[chan])/Numb > 0.2) && (Numb>100),
|
||||
&err_count[chan],time_1_5sec,0))
|
||||
{
|
||||
error.bit.Wry = 1;
|
||||
error.bit.Stop = 1;
|
||||
}
|
||||
|
||||
if(er_anal( ((Numb-lev_count[thrd])/Numb > 0.2) && (Numb>100),
|
||||
&err_count[thrd],time_1_5sec,0))
|
||||
{
|
||||
error.bit.Wry = 1;
|
||||
if(!ignor)
|
||||
error.bit.Stop = 1;
|
||||
}
|
||||
|
||||
if(!ist)
|
||||
{
|
||||
if(Amplitude > sens_hi_edge[sens])
|
||||
{
|
||||
error.bit.Hyper = 1;
|
||||
if(!ignor)
|
||||
error.bit.Stop = 1;
|
||||
}
|
||||
|
||||
if(Amplitude < sens_lo_edge[sens])
|
||||
{
|
||||
error.bit.Out = 1;
|
||||
if(!ignor)
|
||||
error.bit.Stop = 1;
|
||||
} } }
|
||||
|
||||
reset_errs(sens,error);
|
||||
|
||||
}
|
||||
|
||||
void Temper_count(int chan)
|
||||
{
|
||||
float Numb;
|
||||
int Temper;
|
||||
int ignor;
|
||||
ERROR error;
|
||||
int zer0;
|
||||
|
||||
if(!chan)
|
||||
{
|
||||
sig.all = chk.all;
|
||||
chk.all = 0;
|
||||
}
|
||||
|
||||
if(chan<MAX_TPL_CANAL*2)
|
||||
if(sens_error[chan].bit.Bypas)
|
||||
{
|
||||
sens_error[chan].all = 0;
|
||||
sens_error[chan].bit.Bypas = 1;
|
||||
Modbus[chan+DATASTART].all = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
Numb = ADC_table[chan];
|
||||
|
||||
if(cTermoCal)
|
||||
{
|
||||
Modbus[chan+DATASTART].all = (int)(Numb);
|
||||
return; // øòîáû ñòðóêòóðà îøèáîê íå âëåçàëà â äàííûå
|
||||
}
|
||||
|
||||
Numb = (Numb-adc0[chan])*tmpK[chan]+tmp0[chan]-273;
|
||||
Modbus[chan+DATASTART].all = (int)(Numb*10);
|
||||
|
||||
Temper = (int)Numb;
|
||||
|
||||
error.all = 0;
|
||||
if(sens_type[chan]==TERMO_AD) zer0=500;
|
||||
if(sens_type[chan]==TERMO_RS) zer0=10;
|
||||
error = control_ADC(chan, ADC_table[chan], zer0);
|
||||
|
||||
if(!error.all)
|
||||
{
|
||||
ignor = sens_error[chan].bit.Ignor;
|
||||
if(((Temper>sens_hi_edge[chan]-Cooling) && (sens_error[chan].bit.Hyper)) ||
|
||||
(Temper>sens_hi_edge[chan]) )
|
||||
{
|
||||
error.bit.Hyper = 1;
|
||||
if(!ignor)
|
||||
{
|
||||
error.bit.Stop = 1;
|
||||
chk.bit.OverHeat= 1;
|
||||
} }
|
||||
|
||||
else
|
||||
|
||||
// Ïðåäóïðåæäåíèå ïî òåìïåðàòóðå
|
||||
|
||||
if(Temper>sens_lo_edge[chan])
|
||||
{
|
||||
error.bit.Over = 1;
|
||||
if(!ignor)
|
||||
chk.bit.SubHeat = 1;
|
||||
} }
|
||||
|
||||
if(error.all) chk.bit.OutHeat = 1;
|
||||
|
||||
reset_errs(chan,error);
|
||||
|
||||
}
|
||||
|
||||
void Power_count(int chan)
|
||||
{
|
||||
float Numb;
|
||||
int Power,ignor,bitt;
|
||||
ERROR error;
|
||||
|
||||
if(sens_error[chan].bit.Bypas)
|
||||
{
|
||||
sens_error[chan].all = 0;
|
||||
sens_error[chan].bit.Bypas = 1;
|
||||
Modbus[chan+DATASTART].all = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
Numb = ADC_table[chan];
|
||||
|
||||
if(cTermoCal)
|
||||
{
|
||||
Modbus[chan+DATASTART].all = (int)(Numb);
|
||||
return; // øòîáû ñòðóêòóðà îøèáîê íå âëåçàëà â äàííûå
|
||||
}
|
||||
|
||||
Power = (Numb * tmpK[chan]+5)/10.0; // powK[sens_type[chan]];
|
||||
|
||||
Modbus[chan+DATASTART].all = Power;
|
||||
|
||||
error.all = 0;
|
||||
ignor = sens_error[chan].bit.Ignor;
|
||||
|
||||
if(Power <sens_lo_edge[chan])
|
||||
{
|
||||
error.bit.Out = 1;
|
||||
|
||||
if(sens_error[sens_pair[chan]].bit.Out)
|
||||
{
|
||||
if(!ignor)
|
||||
error.bit.Stop = 1;
|
||||
} }
|
||||
|
||||
// Ïîâûøåííîå íàïðàæåíèå
|
||||
if(Power > sens_hi_edge[chan])
|
||||
{
|
||||
error.bit.Hyper = 1;
|
||||
if(!ignor)
|
||||
error.bit.Stop = 1;
|
||||
}
|
||||
|
||||
if(chan>3)
|
||||
{
|
||||
bitt = (chan-4)*2;
|
||||
error.bit.Contr1 = er_anal(((Inputs.all>>bitt)&1), &din_count[bitt], 1000, 0); bitt++;
|
||||
error.bit.Contr2 = er_anal(((Inputs.all>>bitt)&1), &din_count[bitt], 1000, 0);
|
||||
}
|
||||
|
||||
if(error.all)
|
||||
if(!ignor)
|
||||
chk.bit.Alarm = 1;
|
||||
reset_errs(chan,error);
|
||||
}
|
||||
140
measure.h
Normal file
140
measure.h
Normal file
@@ -0,0 +1,140 @@
|
||||
// âãâ
|
||||
#ifndef _MEASURE
|
||||
#define _MEASURE
|
||||
|
||||
void Init_sensors(void);
|
||||
void Init_optic(void);
|
||||
void Init_packMask(void);
|
||||
void Temper_count(int chan);
|
||||
void Current_count(int chan);
|
||||
void Power_count(int chan);
|
||||
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int Tear :1;
|
||||
unsigned int Stick :1;
|
||||
unsigned int Wry :1;
|
||||
unsigned int Out :1;
|
||||
unsigned int Over :1;
|
||||
unsigned int Hyper :1;
|
||||
unsigned int Contr1 :1;
|
||||
unsigned int Contr2 :1;
|
||||
|
||||
unsigned int Stop :1;
|
||||
unsigned int Ready :1;
|
||||
unsigned int res :3;
|
||||
unsigned int Latch :1;
|
||||
unsigned int Ignor :1;
|
||||
unsigned int Bypas :1;
|
||||
|
||||
} bit;
|
||||
unsigned int all;
|
||||
|
||||
} ERROR;
|
||||
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int Error :1;
|
||||
unsigned int Alarm :1;
|
||||
unsigned int OverHeat :1;
|
||||
unsigned int SubHeat :1;
|
||||
unsigned int OutHeat :1;
|
||||
unsigned int Test_lamp :1;
|
||||
|
||||
} bit;
|
||||
unsigned int all;
|
||||
|
||||
} FLAG;
|
||||
|
||||
#define NOER 0xE000
|
||||
#define EROR 0x01FF
|
||||
|
||||
#define SIG_FREQ 4000 // Ãö
|
||||
#define READY_FREQ 1000 // Ãö
|
||||
#define BLINK_FREQ 2 // Ãö
|
||||
#define ADC_FREQ 5000//3885//777//2000//20000 //777 //3885 // Ãö (777*5)
|
||||
#define DAC_FREQ 50 // Ãö
|
||||
|
||||
#define CANPOWSE (SIG_FREQ / 100) // 10 ms
|
||||
|
||||
#define LOAD_TIME 10 // sec
|
||||
|
||||
|
||||
#define SENS_ERR_WAIT 10
|
||||
|
||||
#define maximum_bright 10
|
||||
|
||||
/*
|
||||
#define SNOW 1720.0 //1920.0
|
||||
#define BOIL 2360.0 //2561.0
|
||||
|
||||
#define tmp_T_0 0.0
|
||||
#define tmp_T_1 200.00
|
||||
#define tmp_A1_0 978.0
|
||||
#define tmp_A1_1 1686.0
|
||||
#define tmp_A2_0 1017.0
|
||||
#define tmp_A2_1 1736.0
|
||||
#define eta_A1 1002.0
|
||||
#define eta_A2 1542.0
|
||||
*/
|
||||
|
||||
#define tmp_T_0 84.31 // 68Om
|
||||
#define tmp_T_1 234.19 // 100Om
|
||||
#define tmp_A1_0 540.0 // êàíàë 1 68Îì
|
||||
#define tmp_A2_0 500.0 // êàíàë 1 100Îì
|
||||
#define tmp_A1_1 1055.0 // êàíàë 2 68Îì
|
||||
#define tmp_A2_1 1060.0 // êàíàë 2 100Îì
|
||||
|
||||
|
||||
#define ZERO 27
|
||||
|
||||
#define mka300 2040
|
||||
#define mka400 2700
|
||||
|
||||
#define C100 650
|
||||
#define C150 2370
|
||||
|
||||
#define Cooling 5 // (°Ñ) Ãèñòåðåçèñ ïî ñíàòèþ ïåðåãðåâà
|
||||
|
||||
#define COSPi6 0.86602540378443864676372317075294
|
||||
|
||||
#define RADIX2 1.4142135623730950488016887242097
|
||||
|
||||
#define CURRENT 1 // òîê
|
||||
#define VOLTAGE 2 // íàïðàæåíèå
|
||||
|
||||
#define POWER_380 3 // ïèòàíèå 380Â
|
||||
#define POWER_220 4 // ïèòàíèå 220Â
|
||||
#define POWER_31 5 // ïèòàíèå 31Â
|
||||
#define POWER_24 6 // ïèòàíèå 24Â
|
||||
#define VIRT_24 7 // ïèòàíèå 24Â
|
||||
#define POWER_15 8 // ïèòàíèå 15Â
|
||||
#define TERMO_AD 9 // òåðìîäàò÷èê ìåëêîñõåìà
|
||||
#define TERMO_RS 10 // òåðìîäàò÷èê ðåçèñòîð
|
||||
#define OPTIC 11 // îïòîêàíàë ìåãîììåòðà
|
||||
|
||||
extern int MAX_TPL_CANAL;
|
||||
|
||||
extern FILTERBAT filter[];
|
||||
|
||||
extern ERROR * sens_error;
|
||||
extern int * sens_hi_edge;
|
||||
extern int * sens_lo_edge;
|
||||
|
||||
extern int adc0[],tmp0[];
|
||||
|
||||
#define Zero_lev (adc0+12) //((int *)&Modbus[0x74])
|
||||
|
||||
extern float tmpK[];
|
||||
extern FLAG chk,sig;
|
||||
extern int sens_type[];
|
||||
|
||||
extern int period_ready;
|
||||
|
||||
extern unsigned int CanPowse,CanGO;
|
||||
|
||||
#endif //_MEASURE
|
||||
367
message.c
Normal file
367
message.c
Normal file
@@ -0,0 +1,367 @@
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "package.h"
|
||||
#include "RS485.h"
|
||||
#include "crc16.h"
|
||||
#include "cntrl_adr.h"
|
||||
#include "bios_dsp.h"
|
||||
#include "filter_bat2.h"
|
||||
#include "measure.h"
|
||||
#include "message.h"
|
||||
|
||||
|
||||
#include "ADC.h"
|
||||
#include "peripher.h"
|
||||
|
||||
#include "ecan.h"
|
||||
#include "spise2p.h"
|
||||
#include "i2c.h"
|
||||
|
||||
WORDE Modbus[ANSWER_LEN+1];
|
||||
WORDE reply[REPLY_LEN];
|
||||
|
||||
unsigned int param[ANSWER_LEN+1];
|
||||
|
||||
LONGE* outputs;
|
||||
|
||||
int DataAnalog1,DataAnalog2;
|
||||
|
||||
ERROR * sens_error;
|
||||
int * sens_hi_edge;
|
||||
int * sens_lo_edge;
|
||||
|
||||
unsigned int Maska[2][8];
|
||||
|
||||
void Default_params()
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for(i=0;i<ANSWER_LEN;i++)
|
||||
{
|
||||
Modbus[i].all = 0;
|
||||
}
|
||||
|
||||
Brightness = 8;
|
||||
|
||||
LastMode = Addrr;
|
||||
|
||||
Cancount[0] = 20; // ïàóçà ìåæäó ïîñûëêàìè CAN
|
||||
Cancount[1] = 200; // ïàóçà ìåæäó ïîñûëêàìè CAN
|
||||
|
||||
if(Desk==dsk_COMM)
|
||||
{
|
||||
sens_hi_edge[0 ] = 55;
|
||||
sens_hi_edge[1 ] = 55;
|
||||
sens_hi_edge[2 ] = 55;
|
||||
sens_hi_edge[3 ] = 55;
|
||||
|
||||
sens_hi_edge[4 ] = 65;
|
||||
sens_hi_edge[5 ] = 65;
|
||||
|
||||
sens_hi_edge[7 ] = 50;
|
||||
sens_hi_edge[8 ] = 50;
|
||||
sens_hi_edge[9 ] = 50;
|
||||
sens_hi_edge[10] = 50;
|
||||
sens_hi_edge[11] = 50;
|
||||
|
||||
sens_lo_edge[0 ] = 50;
|
||||
sens_lo_edge[1 ] = 50;
|
||||
sens_lo_edge[2 ] = 50;
|
||||
sens_lo_edge[3 ] = 50;
|
||||
|
||||
sens_lo_edge[4 ] = 60;
|
||||
sens_lo_edge[5 ] = 60;
|
||||
|
||||
sens_lo_edge[7 ] = 45;
|
||||
sens_lo_edge[8 ] = 45;
|
||||
sens_lo_edge[9 ] = 45;
|
||||
sens_lo_edge[10] = 45;
|
||||
sens_lo_edge[11] = 45;
|
||||
}
|
||||
|
||||
if(Currentoz)
|
||||
{
|
||||
for(i=12;i<16;i++)
|
||||
{
|
||||
sens_hi_edge[i] = 2428;
|
||||
sens_lo_edge[i] = 1462;
|
||||
}
|
||||
|
||||
Modbus[12].bit.bitE = 1; // Ignore
|
||||
Modbus[13].bit.bitE = 1; // Ignore
|
||||
Modbus[14].bit.bitE = 1; // Ignore
|
||||
Modbus[15].bit.bitE = 1; // Ignore
|
||||
}
|
||||
|
||||
if(Mode==adr_ISOL)
|
||||
{
|
||||
optopowse = 200;
|
||||
optofiltr = 20; //200;
|
||||
|
||||
Brightness = 0;
|
||||
|
||||
isoMOM[0] = 100;
|
||||
isoMOM[1] = 500;
|
||||
isoMOM[2] = 100;
|
||||
isoMOM[3] = 500;
|
||||
|
||||
isoADC[0] = 4800;
|
||||
isoADC[1] = 4000;
|
||||
isoADC[2] = 4800;
|
||||
isoADC[3] = 4000;
|
||||
}
|
||||
|
||||
if(Mode==adr_SHKF)
|
||||
{
|
||||
Modbus[0x02].bit.bitE = 1; // Ignore êëèìàò êîíòðîëü
|
||||
Modbus[0x03].bit.bitE = 1; // Ignore êëèìàò êîíòðîëü
|
||||
|
||||
for(i=0;i<17;i++)
|
||||
{
|
||||
if(sens_type[i]==POWER_380)
|
||||
{ sens_lo_edge[i] = 300;
|
||||
sens_hi_edge[i] = 430; }
|
||||
if(sens_type[i]==POWER_220)
|
||||
{ sens_lo_edge[i] = 170;
|
||||
sens_hi_edge[i] = 250; }
|
||||
if(sens_type[i]==POWER_31)
|
||||
{ sens_lo_edge[i] = 20;
|
||||
sens_hi_edge[i] = 40; }
|
||||
if(sens_type[i]==POWER_24 || sens_type[i]==VIRT_24)
|
||||
{ sens_lo_edge[i] = 15;
|
||||
sens_hi_edge[i] = 30; }
|
||||
if(sens_type[i]==POWER_15)
|
||||
{ sens_lo_edge[i] = 10;
|
||||
sens_hi_edge[i] = 20; }
|
||||
if(sens_type[i]==TERMO_AD)
|
||||
{ sens_lo_edge[i] = 60;
|
||||
sens_hi_edge[i] = 65;
|
||||
} } } }
|
||||
|
||||
void Load_params()
|
||||
{
|
||||
unsigned int i,crc;
|
||||
|
||||
sens_error = ((ERROR *)&Modbus[start_sens_error]);
|
||||
sens_hi_edge = ((int *)&Modbus[start_sens_hi_edge]);
|
||||
sens_lo_edge = ((int *)&Modbus[start_sens_lo_edge]);
|
||||
|
||||
Seeprom_read(0x3FFF-(ANSWER_LEN+1), param, (ANSWER_LEN+1)*2);
|
||||
crc = get_crc16(param,ANSWER_LEN);
|
||||
if( (crc==param[ANSWER_LEN]) &&
|
||||
(crc !=0xFFFF) &&
|
||||
(Addrr == param[126]) )
|
||||
{
|
||||
for(i=0;i<ANSWER_LEN;i++) Modbus[i].all = param[i];
|
||||
Commands=0;
|
||||
|
||||
if(Desk==dsk_ISOL)
|
||||
{
|
||||
if(optopowse==0) optopowse=200;
|
||||
if(optofiltr==0) optofiltr=20; //200
|
||||
} }
|
||||
else
|
||||
{
|
||||
Default_params();
|
||||
Commands=0;
|
||||
Save_params();
|
||||
}
|
||||
|
||||
if(Desk==dsk_COMM)
|
||||
for(i=0;i<4;i++) Zeroes[i] = adc0[12+i];
|
||||
}
|
||||
|
||||
void Save_params()
|
||||
{
|
||||
unsigned int i,dif=0;
|
||||
|
||||
for(i=0;i<ANSWER_LEN;i++)
|
||||
if(param[i] != (unsigned int)Modbus[i].all)
|
||||
{
|
||||
param[i] = Modbus[i].all;
|
||||
dif=1;
|
||||
}
|
||||
if(dif)
|
||||
{
|
||||
param[ANSWER_LEN] = get_crc16(param,ANSWER_LEN);
|
||||
Seeprom_write(0x3FFF-(ANSWER_LEN+1),param,(ANSWER_LEN+1)*2);
|
||||
}
|
||||
}
|
||||
|
||||
void Load_caliber()
|
||||
{
|
||||
unsigned int buf[2],crc;
|
||||
int i,line;
|
||||
int adcLOW,adcHI;
|
||||
float tmpLOW,tmpHI;
|
||||
|
||||
if(Desk==dsk_COMM)
|
||||
{
|
||||
for(i=0;i<12;i++)
|
||||
{
|
||||
line = i*4;
|
||||
//-------------------------------------------------------------------
|
||||
buf[0]= I2CA_ReadData(line); DSP28x_usDelay(500);
|
||||
buf[1]= I2CA_ReadData(line+1); DSP28x_usDelay(500);
|
||||
crc = I2CA_ReadData(line+70); DSP28x_usDelay(500);
|
||||
if(crc!=get_crc16(buf,2))
|
||||
{
|
||||
if(sens_type[i]==TERMO_AD) { buf[0] = 330; buf[1] = 30; }
|
||||
else { buf[0] = 0; buf[1] = 273; }
|
||||
}
|
||||
adcLOW = buf[0];
|
||||
tmpLOW = buf[1];
|
||||
//-------------------------------------------------------------------
|
||||
buf[0]= I2CA_ReadData(line+2); DSP28x_usDelay(500);
|
||||
buf[1]= I2CA_ReadData(line+3); DSP28x_usDelay(500);
|
||||
crc = I2CA_ReadData(line+72); DSP28x_usDelay(500);
|
||||
if(crc!=get_crc16(buf,2))
|
||||
{
|
||||
if(sens_type[i]==TERMO_AD) { buf[0] = 4000; buf[1] = 360; }
|
||||
else { buf[0] = 3790; buf[1] = 473; }
|
||||
}
|
||||
adcHI = buf[0];
|
||||
tmpHI = buf[1];
|
||||
//-------------------------------------------------------------------
|
||||
adc0[i] = adcLOW;
|
||||
tmp0[i] = tmpLOW;
|
||||
tmpK[i] = (tmpHI - tmpLOW)/(adcHI - adcLOW);
|
||||
}
|
||||
|
||||
for(i=12;i<16;i++)
|
||||
{
|
||||
line = i*4;
|
||||
//-------------------------------------------------------------------
|
||||
buf[0]= I2CA_ReadData(line); DSP28x_usDelay(500);
|
||||
buf[1]= I2CA_ReadData(line+1); DSP28x_usDelay(500);
|
||||
crc = I2CA_ReadData(line+70); DSP28x_usDelay(500);
|
||||
if(crc!=get_crc16(buf,2))
|
||||
{
|
||||
buf[0] = 2047; buf[1] = 0;
|
||||
}
|
||||
adcLOW = buf[0];
|
||||
tmpLOW = buf[1];
|
||||
//-------------------------------------------------------------------
|
||||
buf[0]= I2CA_ReadData(line+2); DSP28x_usDelay(500);
|
||||
buf[1]= I2CA_ReadData(line+3); DSP28x_usDelay(500);
|
||||
crc = I2CA_ReadData(line+72); DSP28x_usDelay(500);
|
||||
if(crc!=get_crc16(buf,2))
|
||||
{
|
||||
buf[0] = 2310; buf[1] = 0; // #define cur_K 2.31//2.352
|
||||
}
|
||||
adcHI = buf[0];
|
||||
tmpHI = buf[1];
|
||||
//-------------------------------------------------------------------
|
||||
adc0[i] = adcLOW;
|
||||
tmp0[i] = tmpLOW;
|
||||
tmpK[i] = adcHI/1000.0;
|
||||
}
|
||||
for(i=0;i<4;i++) Zeroes[i] = adc0[12+i];
|
||||
}
|
||||
if(Desk==dsk_SHKF)
|
||||
for(i=0;i<17;i++)
|
||||
{
|
||||
line = i*4;
|
||||
//-------------------------------------------------------------------
|
||||
buf[0]= I2CA_ReadData(line); DSP28x_usDelay(500);
|
||||
buf[1]= I2CA_ReadData(line+1); DSP28x_usDelay(500);
|
||||
crc = I2CA_ReadData(line+70); DSP28x_usDelay(500);
|
||||
if(crc!=get_crc16(buf,2))
|
||||
{
|
||||
if(sens_type[i]==TERMO_AD) { buf[0] = 1635; buf[1] = 240; }
|
||||
else { buf[0] = 0; buf[1] = 0; }
|
||||
}
|
||||
adcLOW = buf[0];
|
||||
tmpLOW = buf[1];
|
||||
//-------------------------------------------------------------------
|
||||
buf[0]= I2CA_ReadData(line+2); DSP28x_usDelay(500);
|
||||
buf[1]= I2CA_ReadData(line+3); DSP28x_usDelay(500);
|
||||
crc = I2CA_ReadData(line+72); DSP28x_usDelay(500);
|
||||
if(crc!=get_crc16(buf,2))
|
||||
{
|
||||
if(sens_type[i]==TERMO_AD) { buf[0] = 4019; buf[1] = 590; } else
|
||||
if(sens_type[i]==POWER_380) { buf[0] = 2450; buf[1] = 3800; } else
|
||||
if(sens_type[i]==POWER_220) { buf[0] = 2450; buf[1] = 2200; } else
|
||||
if(sens_type[i]==VIRT_24) { buf[0] = 1; buf[1] = 240; } else
|
||||
{ buf[0] = 2450; buf[1] = 240; }
|
||||
|
||||
}
|
||||
|
||||
//if(sens_type[i]==VIRT_24) { buf[0] = 1; buf[1] = 240; }
|
||||
|
||||
adcHI = buf[0];
|
||||
tmpHI = buf[1];
|
||||
//-------------------------------------------------------------------
|
||||
adc0[i] = adcLOW;
|
||||
tmp0[i] = tmpLOW;
|
||||
tmpK[i] = (tmpHI - tmpLOW)/(adcHI - adcLOW);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/***************************************************************/
|
||||
/* Ïåðåäà÷à äàííûõ ïî ïðîòîêîëó ModBus - êîìàíäà 3
|
||||
×òåíèå à÷ååê äàííûõ */
|
||||
/***************************************************************/
|
||||
void ReceiveCommandModbus3(RS_DATA *rs_arr)
|
||||
{
|
||||
unsigned int crc, Address_MB, Length_MB, i;
|
||||
|
||||
// ïîëó÷èëè íà÷àëüíûé àäðåñ ÷òåíèà
|
||||
Address_MB =/*(rs_arr->RS_Header[2] << 8) |*/ rs_arr->RS_Header[3];
|
||||
|
||||
// ïîëó÷èëè êîëè÷åñòâî ñëîâ äàííûõ
|
||||
Length_MB = (rs_arr->RS_Header[4] << 8) | rs_arr->RS_Header[5];
|
||||
|
||||
/////////////////////////////////////////////////
|
||||
// Îòñûëêà
|
||||
/* Ïîñ÷èòàëè êîíòðîëüíóþ ñóììó ïåðåä ñàìîé ïîñûëêîé */
|
||||
|
||||
rs_arr->buffer[0] = CNTRL_ADDR;
|
||||
rs_arr->buffer[1] = CMD_MODBUS_3;
|
||||
rs_arr->buffer[2] = Length_MB*2;
|
||||
|
||||
for (i=0;i<Length_MB;i++)
|
||||
{
|
||||
rs_arr->buffer[3+i*2 ]=(Modbus[Address_MB+i].byt.byte_hi);
|
||||
rs_arr->buffer[3+i*2+1]=(Modbus[Address_MB+i].byt.byte_lo);
|
||||
}
|
||||
|
||||
crc = 0xffff;
|
||||
crc = get_crc_16(crc, rs_arr->buffer, Length_MB*2+3);
|
||||
|
||||
rs_arr->buffer[Length_MB*2+3] = LOBYTE(crc);
|
||||
rs_arr->buffer[Length_MB*2+4] = HIBYTE(crc);
|
||||
|
||||
rs_arr->buffer[Length_MB*2+5] = 0;
|
||||
rs_arr->buffer[Length_MB*2+6] = 0;
|
||||
rs_arr->buffer[Length_MB*2+7] = 0;
|
||||
rs_arr->buffer[Length_MB*2+8] = 0;
|
||||
|
||||
rs_arr->flag_TIMEOUT_to_Send=true;
|
||||
RS_Send(rs_arr, rs_arr->buffer, Length_MB*2+8);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void ReceiveCommandModbus6(RS_DATA *rs_arr)
|
||||
{
|
||||
unsigned int Address_MB, Data_MB, i;
|
||||
|
||||
/////////////////////////////////////////////////
|
||||
// Îòñûëêà
|
||||
/* Îòïðàâëàåì íàçàä òî æå ñàìîå */
|
||||
|
||||
for (i=0;i<8;i++)
|
||||
rs_arr->buffer[i] = rs_arr->RS_Header[i];
|
||||
|
||||
// ïîëó÷èëè íà÷àëüíûé àäðåñ çàïèñè
|
||||
Address_MB = (/*(rs_arr->RS_Header[2] << 8) | */rs_arr->RS_Header[3]);
|
||||
|
||||
// ïîëó÷èëè ñëîâî äàííûõ
|
||||
Data_MB = (rs_arr->RS_Header[4] << 8) | rs_arr->RS_Header[5];
|
||||
|
||||
Modbus[Address_MB].all = Data_MB;
|
||||
|
||||
rs_arr->flag_TIMEOUT_to_Send=true;
|
||||
RS_Send(rs_arr, rs_arr->buffer, 10);
|
||||
}
|
||||
51
message.h
Normal file
51
message.h
Normal file
@@ -0,0 +1,51 @@
|
||||
#ifndef MESSAGE_H
|
||||
#define MESSAGE_H
|
||||
|
||||
typedef unsigned char CHAR;
|
||||
|
||||
#define ANSWER_LEN 0x80 //70 // 16+16+16+16+6
|
||||
#define REPLY_LEN 0x19
|
||||
|
||||
#define byte_hi byte_1
|
||||
#define byte_lo byte_0
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned char Address; // Àäðåñ êîíòðîëëåðà
|
||||
unsigned char Number; // Íîìåð êîìàíäû
|
||||
|
||||
BAITE byte0;
|
||||
BAITE byte1;
|
||||
BAITE byte2;
|
||||
BAITE byte3;
|
||||
BAITE byte4;
|
||||
BAITE byte5;
|
||||
BAITE byte6;
|
||||
BAITE byte7;
|
||||
|
||||
unsigned char crc_lo;
|
||||
unsigned char crc_hi;
|
||||
unsigned char add_byte;
|
||||
} CMD_TO_TMS;
|
||||
|
||||
extern WORDE Modbus[];
|
||||
extern WORDE reply[];
|
||||
|
||||
extern LONGE* outputs;
|
||||
|
||||
extern int DataAnalog1,DataAnalog2;
|
||||
|
||||
extern unsigned int Maska[][8];
|
||||
|
||||
//void ReceiveCommand(RS_DATA *rs_arr);
|
||||
void ReceiveCommandModbus3(RS_DATA *rs_arr);
|
||||
void ReceiveCommandModbus6(RS_DATA *rs_arr);
|
||||
|
||||
void reset_errs(int sens, ERROR er);
|
||||
|
||||
void Save_params(void);
|
||||
void Load_params(void);
|
||||
void Load_caliber(void);
|
||||
void Default_params(void);
|
||||
|
||||
#endif //MESSAGE_H
|
||||
70
package.h
Normal file
70
package.h
Normal file
@@ -0,0 +1,70 @@
|
||||
#ifndef PACKAGE
|
||||
#define PACKAGE
|
||||
|
||||
#define TERMOPAIR 14
|
||||
#define CURRENTOS (TERMOPAIR*2)
|
||||
#define DATASTART 24
|
||||
|
||||
//-----------------------------------------------
|
||||
#define adr_REC1 1
|
||||
#define adr_REC2 2
|
||||
#define adr_INV1 3
|
||||
#define adr_INV2 4
|
||||
#define adr_SHKF 5
|
||||
#define adr_ISOL 6
|
||||
//-----------------------------------------------
|
||||
|
||||
//-----------------------------------------------
|
||||
#define dsk_COMM 1
|
||||
#define dsk_SHKF 2
|
||||
#define dsk_ISOL 3
|
||||
//-----------------------------------------------
|
||||
|
||||
|
||||
#define CAN_send_start 0 // Àäðåñ ïåðâîãî ïåðåäàâàåìîãî
|
||||
#define CAN_send_finis 0x6F // Àäðåñ ïîñëåäíåãî ïåðåäàâàåìîãî
|
||||
|
||||
#define start_sens_error 0
|
||||
#define start_sens_hi_edge 48
|
||||
#define start_sens_lo_edge 72
|
||||
|
||||
#define IsShimON Modbus[2].bit.bit0
|
||||
|
||||
#define Input Modbus[0x17]
|
||||
|
||||
#define optopowse Modbus[0x60].all // ïàóçà ìåæäó çàïðîñàìè, ms
|
||||
#define optofiltr Modbus[0x61].all // êîýôôèöèåíò ôèëüòðàöèè
|
||||
|
||||
#define Brightness Modbus[0x64].all // àðêîñòü ñèãíàëüíûõ ëàìïî÷åê
|
||||
|
||||
#define Cancount ((int *)&Modbus[0x65])
|
||||
|
||||
#define Zeroes ((int *)&Modbus[0x70])
|
||||
|
||||
#define isoMOM ((int *)&Modbus[0x70])
|
||||
#define isoADC ((int *)&Modbus[0x78])
|
||||
|
||||
#define LastMode Modbus[126].all
|
||||
|
||||
#define Commands Modbus[127].all
|
||||
#define cTestLamp Modbus[127].bit.bit0
|
||||
#define cSetZero Modbus[127].bit.bit1
|
||||
#define cSaveParam Modbus[127].bit.bit2
|
||||
#define cDefParam Modbus[127].bit.bit3
|
||||
|
||||
#define cTermoCal Modbus[127].bit.bit4
|
||||
#define cReadCal Modbus[127].bit.bit5
|
||||
|
||||
#define cExtLamp Modbus[127].bit.bit6
|
||||
#define cExtLite Modbus[127].bit.bit7
|
||||
|
||||
#define cKoefCalc Modbus[127].bit.bit8
|
||||
|
||||
#define cShimON Modbus[127].bit.bit9
|
||||
|
||||
|
||||
#define cReset Modbus[127].bit.bitF
|
||||
|
||||
|
||||
#endif //PACKAGE
|
||||
|
||||
145
peripher.c
Normal file
145
peripher.c
Normal file
@@ -0,0 +1,145 @@
|
||||
#include "DSP2833x_Device.h" // DSP281x Headerfile Include File
|
||||
#include "filter_bat2.h"
|
||||
#include "measure.h"
|
||||
#include "RS485.h"
|
||||
#include "message.h"
|
||||
|
||||
#include "package.h"
|
||||
|
||||
#include "peripher.h"
|
||||
#include "GPIO_table.h"
|
||||
|
||||
|
||||
int Mode,Desk,Addrr,TermoAD=0,TermoRS=0,TermoSW=0,Currentoz=0;
|
||||
LONGE Inputs;
|
||||
|
||||
int ExtraCanal[24];
|
||||
|
||||
void get_Mode()
|
||||
{
|
||||
int i,qua;
|
||||
|
||||
EALLOW;
|
||||
|
||||
GpioCtrlRegs.GPAMUX1.all &= 0xFF000000; // 00—11
|
||||
GpioCtrlRegs.GPAMUX2.all &= 0xFF00003F; // 19—27
|
||||
GpioCtrlRegs.GPBMUX1.all &= 0xFFFFFCC0; // 32—34, 36
|
||||
GpioCtrlRegs.GPBMUX2.all &= 0x000FF000; // 48—53, 58—63
|
||||
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO20 = 0;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO21 = 0;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO22 = 0;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO51 = 0;
|
||||
|
||||
EDIS;
|
||||
|
||||
Mode=0;
|
||||
|
||||
qua=0;
|
||||
for(i=0;i<100;i++)
|
||||
qua += !GpioDataRegs.GPADAT.bit.GPIO22;
|
||||
if(qua>50) Mode += 1;
|
||||
|
||||
qua=0;
|
||||
for(i=0;i<100;i++)
|
||||
qua += !GpioDataRegs.GPADAT.bit.GPIO20;
|
||||
if(qua>50) Mode += 2;
|
||||
|
||||
qua=0;
|
||||
for(i=0;i<100;i++)
|
||||
qua += !GpioDataRegs.GPADAT.bit.GPIO21;
|
||||
if(qua>50) Mode += 4;
|
||||
|
||||
Addrr = Mode*2;
|
||||
|
||||
Mode+= 1;
|
||||
|
||||
qua=0;
|
||||
for(i=0;i<100;i++)
|
||||
qua += !GpioDataRegs.GPBDAT.bit.GPIO51;
|
||||
if(qua>50) Addrr += 1;
|
||||
|
||||
if( (Mode==adr_REC1)||(Mode==adr_REC2)) Currentoz = 1;
|
||||
if( (Mode==adr_REC1)||(Mode==adr_REC2)||
|
||||
(Mode==adr_INV1)||(Mode==adr_INV2)) Desk = dsk_COMM;
|
||||
if (Mode==adr_SHKF) Desk = dsk_SHKF;
|
||||
if (Mode==adr_ISOL) Desk = dsk_ISOL;
|
||||
|
||||
EALLOW;
|
||||
switch(Desk)
|
||||
{
|
||||
case dsk_COMM: GpioCtrlRegs.GPADIR.all = COMM_GPADIR;
|
||||
GpioCtrlRegs.GPBDIR.all = COMM_GPBDIR; break;
|
||||
|
||||
case dsk_SHKF: GpioCtrlRegs.GPADIR.all = VEPP_GPADIR;
|
||||
GpioCtrlRegs.GPBDIR.all = VEPP_GPBDIR; break;
|
||||
|
||||
case dsk_ISOL: GpioCtrlRegs.GPADIR.all = ISOL_GPADIR;
|
||||
GpioCtrlRegs.GPBDIR.all = ISOL_GPBDIR; break;
|
||||
}
|
||||
EDIS;
|
||||
}
|
||||
|
||||
void get_Inputs()
|
||||
{
|
||||
static long butthurt[2] ={0,0};
|
||||
unsigned long butt=0;
|
||||
|
||||
if(Desk==dsk_COMM)
|
||||
{
|
||||
if(!GpioDataRegs.GPADAT.bit.GPIO7) butthurt[0]=0;
|
||||
else if(butthurt[0]<MAX_BUTTHURT) butthurt[0]++;
|
||||
if(butthurt[0]<MAX_BUTTHURT) butt =1;
|
||||
|
||||
if(!GpioDataRegs.GPADAT.bit.GPIO6) butthurt[1]=0;
|
||||
else if(butthurt[1]<MAX_BUTTHURT) butthurt[1]++;
|
||||
if(butthurt[1]<MAX_BUTTHURT) butt +=2;
|
||||
|
||||
if(Mode<adr_INV1)
|
||||
{
|
||||
if(!GpioDataRegs.GPADAT.bit.GPIO26) butt += 4;
|
||||
if(!GpioDataRegs.GPADAT.bit.GPIO23) butt += 8;
|
||||
} }
|
||||
|
||||
if(Desk==dsk_SHKF)
|
||||
{
|
||||
if(GpioDataRegs.GPBDAT.bit.GPIO58) butt += 0x0000001;
|
||||
if(GpioDataRegs.GPBDAT.bit.GPIO61) butt += 0x0000002;
|
||||
|
||||
if(GpioDataRegs.GPBDAT.bit.GPIO53) butt += 0x00000010;
|
||||
if(GpioDataRegs.GPBDAT.bit.GPIO52) butt += 0x00000020;
|
||||
if(GpioDataRegs.GPADAT.bit.GPIO24) butt += 0x00000040;
|
||||
if(GpioDataRegs.GPADAT.bit.GPIO23) butt += 0x00000080;
|
||||
if(GpioDataRegs.GPADAT.bit.GPIO27) butt += 0x00000100;
|
||||
if(GpioDataRegs.GPADAT.bit.GPIO26) butt += 0x00000200;
|
||||
if(GpioDataRegs.GPBDAT.bit.GPIO36) butt += 0x00000400;
|
||||
if(GpioDataRegs.GPADAT.bit.GPIO25) butt += 0x00000800;
|
||||
if(GpioDataRegs.GPADAT.bit.GPIO0) butt += 0x00001000;
|
||||
if(GpioDataRegs.GPADAT.bit.GPIO2) butt += 0x00002000;
|
||||
if(GpioDataRegs.GPADAT.bit.GPIO4) butt += 0x00004000;
|
||||
if(GpioDataRegs.GPADAT.bit.GPIO6) butt += 0x00008000;
|
||||
if(GpioDataRegs.GPADAT.bit.GPIO8) butt += 0x00010000;
|
||||
if(GpioDataRegs.GPADAT.bit.GPIO10) butt += 0x00020000;
|
||||
|
||||
if(GpioDataRegs.GPADAT.bit.GPIO1) butt += 0x00400000;
|
||||
if(GpioDataRegs.GPADAT.bit.GPIO3) butt += 0x00800000;
|
||||
if(GpioDataRegs.GPADAT.bit.GPIO7) butt += 0x01000000;
|
||||
if(GpioDataRegs.GPADAT.bit.GPIO9) butt += 0x02000000;
|
||||
|
||||
// ExtraCanal1 = !GpioDataRegs.GPADAT.bit.GPIO5;
|
||||
// ExtraCanal2 = !GpioDataRegs.GPADAT.bit.GPIO11;
|
||||
|
||||
ExtraCanal[15] = (!GpioDataRegs.GPADAT.bit.GPIO1) | (!GpioDataRegs.GPADAT.bit.GPIO3);
|
||||
ExtraCanal[16] = (!GpioDataRegs.GPADAT.bit.GPIO7) | (!GpioDataRegs.GPADAT.bit.GPIO9);
|
||||
}
|
||||
|
||||
if(Desk==dsk_ISOL)
|
||||
{
|
||||
if(!GpioDataRegs.GPBDAT.bit.GPIO62) butt += 0x0000001;
|
||||
|
||||
Input.all = butt;
|
||||
}
|
||||
|
||||
Inputs.all = butt;
|
||||
}
|
||||
|
||||
28
peripher.h
Normal file
28
peripher.h
Normal file
@@ -0,0 +1,28 @@
|
||||
#include "DSP2833x_Device.h" // DSP281x Headerfile Include File
|
||||
|
||||
extern int Mode,Desk,Addrr,TermoAD,TermoRS,TermoSW,Currentoz;
|
||||
extern int ExtraCanal[];
|
||||
|
||||
// READY ---------------------------------------------------------
|
||||
static inline void dat_READY(int x)
|
||||
{ if(Desk==dsk_SHKF) GpioDataRegs.GPBDAT.bit.GPIO60=!x; else
|
||||
GpioDataRegs.GPBDAT.bit.GPIO59=!x; }
|
||||
static inline void set_READY(void)
|
||||
{ if(Desk==dsk_SHKF) GpioDataRegs.GPBCLEAR.bit.GPIO60=1; else
|
||||
GpioDataRegs.GPBCLEAR.bit.GPIO59=1; }
|
||||
static inline void clear_READY(void)
|
||||
{ if(Desk==dsk_SHKF) GpioDataRegs.GPBSET.bit.GPIO60=1; else
|
||||
GpioDataRegs.GPBSET.bit.GPIO59=1; }
|
||||
static inline void toggle_READY(void)
|
||||
{ if(Desk==dsk_SHKF) GpioDataRegs.GPBTOGGLE.bit.GPIO60=1;else
|
||||
GpioDataRegs.GPBTOGGLE.bit.GPIO59=1;}
|
||||
|
||||
|
||||
extern LONGE Inputs;
|
||||
|
||||
void select_tpl_canal(int n_tpl);
|
||||
|
||||
void get_Mode(void);
|
||||
void get_Inputs(void);
|
||||
|
||||
#define MAX_BUTTHURT 250000
|
||||
471
spise2p.c
Normal file
471
spise2p.c
Normal file
@@ -0,0 +1,471 @@
|
||||
/*=================================================================
|
||||
File name : SPISE2PD.C
|
||||
|
||||
Originator : Settu Duraisamy
|
||||
C2000 Applications Team
|
||||
Texas Instruments
|
||||
|
||||
Description : This file contains the SPI bus Serial EEPROM driver
|
||||
implemented using Virtual SPI driver
|
||||
|
||||
Date : 6/30/2003 (DD/MM/YYYY)
|
||||
====================================================================*/
|
||||
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
|
||||
#include "spise2p.h"
|
||||
//#include "pins.h"
|
||||
|
||||
/* Instance the SPI bus serial EEPROM driver */
|
||||
static SPISE2P_DRV se2p=SPISE2P_DRV_DEFAULTS;
|
||||
|
||||
/* Instance serial EEPROm data transfer structure */
|
||||
static SE2P_DATA writeData, readData;
|
||||
|
||||
// Prototype statements for functions found within this file.
|
||||
interrupt void PRD_TICK(void);
|
||||
interrupt void cpu_timer2_isr(void);
|
||||
|
||||
int ccc=0;
|
||||
|
||||
/********************************************************************/
|
||||
/******* SPI bus Serial EEPROM driver Initialization routine ********/
|
||||
/********************************************************************/
|
||||
|
||||
void Seeprom_write( unsigned int adres,
|
||||
unsigned int buf[],
|
||||
unsigned int size)
|
||||
{
|
||||
unsigned int len;
|
||||
|
||||
// diod2_on();
|
||||
|
||||
CpuTimer2.InterruptCount=0;
|
||||
CpuTimer2Regs.TCR.all = 0x4020; // Use write-only instruction to set TSS bit = 0
|
||||
|
||||
while(!spiSe2pFree(&se2p));
|
||||
|
||||
size = (size / WORD_LEN) + (size % WORD_LEN);
|
||||
while(size)
|
||||
{
|
||||
len = PAGE_LEN - (adres % PAGE_LEN);
|
||||
if(len > size) len=size;
|
||||
|
||||
writeData.dataPtr = buf;
|
||||
writeData.nrData = len;
|
||||
writeData.se2pAddr = adres * WORD_LEN;
|
||||
|
||||
spiSe2pWrite(&se2p, &writeData);
|
||||
while(!spiSe2pFree(&se2p));
|
||||
|
||||
buf += len;
|
||||
adres += len;
|
||||
size -= len;
|
||||
}
|
||||
CpuTimer2Regs.TCR.all = 0x4010; // Use write-only instruction to set TSS bit = 1
|
||||
// diod2_off();
|
||||
|
||||
}
|
||||
|
||||
void Seeprom_read( unsigned int adres,
|
||||
unsigned int buf[],
|
||||
unsigned int size)
|
||||
{
|
||||
unsigned int len;
|
||||
|
||||
// diod2_on();
|
||||
CpuTimer2.InterruptCount=0;
|
||||
CpuTimer2Regs.TCR.all = 0x4020; // Use write-only instruction to set TSS bit = 0
|
||||
|
||||
while(!spiSe2pFree(&se2p));
|
||||
|
||||
size = (size / WORD_LEN) + (size % WORD_LEN);
|
||||
while(size)
|
||||
{
|
||||
len = PAGE_LEN - (adres % PAGE_LEN);
|
||||
if(len > size) len=size;
|
||||
|
||||
readData.dataPtr = buf;
|
||||
readData.nrData = len;
|
||||
readData.se2pAddr = adres * WORD_LEN;
|
||||
|
||||
spiSe2pRead(&se2p, &readData);
|
||||
while(!spiSe2pFree(&se2p));
|
||||
|
||||
buf += len;
|
||||
adres += len;
|
||||
size -= len;
|
||||
}
|
||||
CpuTimer2Regs.TCR.all = 0x4010; // Use write-only instruction to set TSS bit = 1
|
||||
// diod2_off();
|
||||
}
|
||||
|
||||
void Init_Seeprom()
|
||||
{
|
||||
se2p.init(&se2p);
|
||||
|
||||
EALLOW; // This is needed to write to EALLOW protected registers
|
||||
PieVectTable.TINT2 = &cpu_timer2_isr;
|
||||
EDIS; // This is needed to disable write to EALLOW protected registers
|
||||
|
||||
InitCpuTimers(); // For this example, only initialize the Cpu Timers
|
||||
// ConfigCpuTimer(&CpuTimer2, (SYSCLKOUT/1000000), 100);
|
||||
// ConfigCpuTimer(&CpuTimer2, (SYSCLKOUT/1000000), 10);
|
||||
ConfigCpuTimer(&CpuTimer2, (SYSCLKOUT/1000000), 100);
|
||||
|
||||
IER |= M_INT14;
|
||||
}
|
||||
|
||||
void SPISE2P_DRV_init(SPISE2P_DRV *eeprom)
|
||||
{
|
||||
/* Configure SPI-A pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be SPI functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
EALLOW;
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0; // General purpose I/O 19 (default) (I/O)
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO19 = 1; // Configures the GPIO pin as an output
|
||||
GpioDataRegs.GPADAT.bit.GPIO19 = 0;
|
||||
EDIS;
|
||||
|
||||
/* Configure the SPI: 8-bit, Rising edge with delay */
|
||||
SpiaRegs.SPICCR.all=0x0007;
|
||||
SpiaRegs.SPICTL.all=0x001F;
|
||||
SpiaRegs.SPISTS.all=0x00;
|
||||
|
||||
SpiaRegs.SPIBRR = CLKMULT * 6;
|
||||
|
||||
SpiaRegs.SPIFFTX.all=0x8000;
|
||||
SpiaRegs.SPIFFRX.all=0x0000;
|
||||
SpiaRegs.SPIFFCT.all=0x00;
|
||||
SpiaRegs.SPIPRI.all=0x0010;
|
||||
|
||||
/* Disable Chip Select of Serial EEPROM */
|
||||
eeprom->csr=0;
|
||||
eeprom->msgPtr=0;
|
||||
|
||||
SpiaRegs.SPICCR.bit.SPISWRESET=1; // Enable SCI
|
||||
}
|
||||
|
||||
void SPISE2P_DRV_csset()
|
||||
{
|
||||
GpioDataRegs.GPADAT.bit.GPIO19 = 1;
|
||||
}
|
||||
|
||||
void SPISE2P_DRV_csclr()
|
||||
{
|
||||
GpioDataRegs.GPADAT.bit.GPIO19 = 0;
|
||||
}
|
||||
|
||||
unsigned int spiSe2pFree(SPISE2P_DRV *se2p)
|
||||
{
|
||||
if(se2p->csr&0x3) return(0);
|
||||
else return(1);
|
||||
}
|
||||
|
||||
void spiSe2pWrite(SPISE2P_DRV *se2p, SE2P_DATA *msgPtr)
|
||||
{
|
||||
se2p->msgPtr=msgPtr;
|
||||
se2p->csr|=0x1;
|
||||
}
|
||||
|
||||
void spiSe2pRead(SPISE2P_DRV *se2p, SE2P_DATA *msgPtr)
|
||||
{
|
||||
se2p->msgPtr=msgPtr;
|
||||
se2p->csr|=0x2;
|
||||
}
|
||||
|
||||
/********************************************************************/
|
||||
/******* SPI bus Serial EEPROM driver Tick function *****************/
|
||||
/********************************************************************/
|
||||
|
||||
interrupt void cpu_timer2_isr(void)
|
||||
{ EALLOW;
|
||||
CpuTimer2.InterruptCount++;
|
||||
|
||||
se2p.tick(&se2p);
|
||||
|
||||
// The CPU acknowledges the interrupt.
|
||||
EDIS;
|
||||
}
|
||||
|
||||
void SPISE2P_DRV_tick(SPISE2P_DRV *eeprom)
|
||||
{
|
||||
static unsigned int step=0;
|
||||
static unsigned int dataCount=0;
|
||||
static volatile unsigned int dummy=0;
|
||||
|
||||
switch(step)
|
||||
{
|
||||
case 0:
|
||||
/* If write request is SET, then trigger the Write operation
|
||||
If read request is SET, then trigger the Read operation
|
||||
If Read request is also not SET, then continue to poll */
|
||||
|
||||
if(eeprom->csr&SPISE2P_WRRQ)
|
||||
{ step=1;
|
||||
eeprom->csr|=SPISE2P_WRIP; /* Set Write in progress*/
|
||||
eeprom->csclr();
|
||||
}
|
||||
|
||||
if(eeprom->csr&SPISE2P_RDRQ)
|
||||
{ step=13;
|
||||
eeprom->csr|=SPISE2P_RDIP; /* Set Read in progress */
|
||||
eeprom->csclr();
|
||||
}
|
||||
break;
|
||||
|
||||
case 1:
|
||||
/************************************************************
|
||||
*********** SPI bus EEPROM Write Starts from here ***********
|
||||
*************************************************************
|
||||
Prier to any attempt to write data to SPI serial EEPROM
|
||||
Write Enable Latch must be set by issuing the WREN command */
|
||||
SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT;
|
||||
SpiaRegs.SPITXBUF=SPISE2P_WREN_CMD;
|
||||
SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1;
|
||||
step=2;
|
||||
break;
|
||||
|
||||
case 2:
|
||||
/* Wait for VSPI State machine to send the WREN command and
|
||||
serial EEPROM Chip Select must be brought to HIGH to set
|
||||
the WREN latch */
|
||||
|
||||
if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
|
||||
{
|
||||
dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */
|
||||
eeprom->csset();
|
||||
|
||||
step=3;
|
||||
}
|
||||
break;
|
||||
|
||||
case 3:
|
||||
/* Assert CS of Serial EEPROM and send WRITE command */
|
||||
|
||||
eeprom->csclr();
|
||||
SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT;
|
||||
SpiaRegs.SPITXBUF=SPISE2P_WRITE_CMD;
|
||||
SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1;
|
||||
step=4;
|
||||
break;
|
||||
|
||||
case 4:
|
||||
/* Wait for VSPI State machine to send the WRITE command */
|
||||
|
||||
if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
|
||||
{ dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */
|
||||
step=5;
|
||||
}
|
||||
break;
|
||||
|
||||
case 5:
|
||||
/* Send Address */
|
||||
|
||||
#if(SPISE2P_ADDR_WIDTH==SIXTEEN_BIT)
|
||||
SpiaRegs.SPICCR.all= SPISE2P_TFR16BIT;
|
||||
SpiaRegs.SPITXBUF=eeprom->msgPtr->se2pAddr;
|
||||
#endif
|
||||
#if(SPISE2P_ADDR_WIDTH==EIGHT_BIT)
|
||||
SpiaRegs.SPICCR.all= SPISE2P_TFR8BIT;
|
||||
SpiaRegs.SPITXBUF=eeprom->msgPtr->se2pAddr<<8;
|
||||
#endif
|
||||
|
||||
SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */
|
||||
step=6;
|
||||
break;
|
||||
|
||||
case 6:
|
||||
/* Wait for VSPI State machine to send the Address */
|
||||
|
||||
if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
|
||||
{ dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */
|
||||
step=7;
|
||||
}
|
||||
break;
|
||||
|
||||
case 7:
|
||||
/* Send Data */
|
||||
|
||||
#if(SPISE2P_DATA_WIDTH==SIXTEEN_BIT)
|
||||
SpiaRegs.SPICCR.all=SPISE2P_TFR16BIT;
|
||||
SpiaRegs.SPITXBUF=*(eeprom->msgPtr->dataPtr+dataCount);
|
||||
#endif
|
||||
|
||||
#if(SPISE2P_DATA_WIDTH==EIGHT_BIT)
|
||||
SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT;
|
||||
SpiaRegs.SPITXBUF=*(eeprom->msgPtr->dataPtr+dataCount)<<8;
|
||||
#endif
|
||||
|
||||
dataCount++;
|
||||
SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */
|
||||
step=8;
|
||||
break;
|
||||
|
||||
case 8:
|
||||
/* Wait for VSPI State machine to send the Data.
|
||||
If all the data are sent, then set the CS pin to HIGH
|
||||
to program or write the data in EEPROM array */
|
||||
|
||||
if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
|
||||
{ dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */
|
||||
|
||||
if (dataCount==eeprom->msgPtr->nrData)
|
||||
{ eeprom->csset();
|
||||
step=9;}
|
||||
else
|
||||
step=7; /* Write next data */
|
||||
}
|
||||
break;
|
||||
|
||||
|
||||
case 9:
|
||||
/* Read the EEPROM status register to check whether the
|
||||
data sent are indeed programmed to the EEPROM array.
|
||||
Hence, send RDSR command to EEPROM to read status reg. */
|
||||
|
||||
eeprom->csclr();
|
||||
SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT;
|
||||
SpiaRegs.SPITXBUF=SPISE2P_RDSR_CMD;
|
||||
SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */
|
||||
step=10;
|
||||
break;
|
||||
|
||||
case 10:
|
||||
/* Wait for VSPI State machine to send RDSR command */
|
||||
|
||||
if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
|
||||
{ dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */
|
||||
step=11;
|
||||
}
|
||||
break;
|
||||
|
||||
case 11:
|
||||
/* Send dummy Data to read Status reg. */
|
||||
|
||||
SpiaRegs.SPITXBUF=SPISE2P_DUMMY_DATA;
|
||||
SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */
|
||||
step=12;
|
||||
break;
|
||||
|
||||
case 12:
|
||||
/* Wait for VSPI State machine to clock out status reg.
|
||||
Check, whether the data are written to the EEPROM array,
|
||||
If written, then reset the WRIP(write in progress) and
|
||||
WRRQ(Write request bit) and go back to STATE0 */
|
||||
|
||||
if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
|
||||
{ eeprom->csset();
|
||||
|
||||
if (SpiaRegs.SPIRXBUF & SPISE2P_BUSY_MASK )
|
||||
step=9;
|
||||
else
|
||||
{ eeprom->csr&=(~SPISE2P_WRIP);
|
||||
eeprom->csr&=(~SPISE2P_WRRQ);
|
||||
step=0;
|
||||
dataCount=0;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case 13:
|
||||
/************************************************************
|
||||
*********** SPI bus EEPROM Read Starts from here ***********
|
||||
*************************************************************
|
||||
Send READ Command to SPI bus serail EEPROM */
|
||||
|
||||
SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT;
|
||||
SpiaRegs.SPITXBUF=SPISE2P_READ_CMD;
|
||||
SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */
|
||||
step=14;
|
||||
break;
|
||||
|
||||
case 14:
|
||||
/* Wait for VSPI State machine to send READ command */
|
||||
|
||||
if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
|
||||
{ dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */
|
||||
step=15;
|
||||
}
|
||||
break;
|
||||
|
||||
case 15:
|
||||
/* Send Address */
|
||||
|
||||
#if(SPISE2P_ADDR_WIDTH==SIXTEEN_BIT)
|
||||
SpiaRegs.SPICCR.all= SPISE2P_TFR16BIT;
|
||||
SpiaRegs.SPITXBUF=eeprom->msgPtr->se2pAddr;
|
||||
#endif
|
||||
#if(SPISE2P_ADDR_WIDTH==EIGHT_BIT)
|
||||
SpiaRegs.SPICCR.all= SPISE2P_TFR8BIT;
|
||||
SpiaRegs.SPITXBUF=eeprom->msgPtr->se2pAddr<<8;
|
||||
#endif
|
||||
|
||||
SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */
|
||||
step=16;
|
||||
break;
|
||||
|
||||
case 16:
|
||||
/* Wait for VSPI State machine to send Address */
|
||||
|
||||
if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
|
||||
{ dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */
|
||||
step=17;
|
||||
}
|
||||
break;
|
||||
|
||||
case 17:
|
||||
/* Send Dummy value to clock out data from serial EEPROM */
|
||||
|
||||
#if(SPISE2P_DATA_WIDTH==SIXTEEN_BIT)
|
||||
SpiaRegs.SPICCR.all= SPISE2P_TFR16BIT;
|
||||
SpiaRegs.SPITXBUF=SPISE2P_DUMMY_DATA;
|
||||
#endif
|
||||
|
||||
#if(SPISE2P_DATA_WIDTH==EIGHT_BIT)
|
||||
SpiaRegs.SPICCR.all= SPISE2P_TFR8BIT;
|
||||
SpiaRegs.SPITXBUF=SPISE2P_DUMMY_DATA<<8;
|
||||
#endif
|
||||
|
||||
SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */
|
||||
step=18;
|
||||
break;
|
||||
|
||||
case 18:
|
||||
/* Wait for VSPI State machine to clk out data from EEPROM */
|
||||
|
||||
if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
|
||||
{
|
||||
#if(SPISE2P_DATA_WIDTH==SIXTEEN_BIT)
|
||||
*(eeprom->msgPtr->dataPtr+dataCount)=SpiaRegs.SPIRXBUF;
|
||||
#endif
|
||||
|
||||
#if(SPISE2P_DATA_WIDTH==EIGHT_BIT)
|
||||
*(eeprom->msgPtr->dataPtr+dataCount)=SpiaRegs.SPIRXBUF&0xFF;
|
||||
#endif
|
||||
dataCount++;
|
||||
step=19;
|
||||
}
|
||||
break;
|
||||
|
||||
case 19:
|
||||
/* If all the data are read, terminate the read operation by
|
||||
rising the CS. Then reset the RDIP (Read in progress) bit
|
||||
and reset the RDRQ(Read request) bit and go back to STATE0 */
|
||||
|
||||
if (dataCount==eeprom->msgPtr->nrData)
|
||||
{ eeprom->csset();
|
||||
step=0;
|
||||
dataCount=0;
|
||||
eeprom->csr&=(~SPISE2P_RDIP);
|
||||
eeprom->csr&=(~SPISE2P_RDRQ);
|
||||
}
|
||||
else
|
||||
step=17;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
134
spise2p.h
Normal file
134
spise2p.h
Normal file
@@ -0,0 +1,134 @@
|
||||
/*=====================================================================
|
||||
File name : SPISE2P.H
|
||||
|
||||
Originator : Settu Duraisamy
|
||||
C2000 Applications Team
|
||||
Texas Instruments
|
||||
|
||||
Description :
|
||||
Header file containing object definitions, proto type
|
||||
declaration and default object initializers for
|
||||
SPI Serial EEPROM driver using VSPI
|
||||
|
||||
Date : 30/6/2003 (DD/MM/YYYY)
|
||||
=======================================================================*/
|
||||
|
||||
#ifndef __SPISE2P_H__
|
||||
|
||||
#define __SPISE2P_H__
|
||||
|
||||
// ¨ìêîñòü ïàìàòè â áàéòàõ
|
||||
#define SEEPROM_LEN 0x10000
|
||||
|
||||
#define NULL 0
|
||||
|
||||
#define SIXTEEN_BIT 15
|
||||
#define EIGHT_BIT 07
|
||||
|
||||
/***************************************************************/
|
||||
/* Configurable Parameter for SPI bus Serial EEPROM */
|
||||
/***************************************************************/
|
||||
#define SPISE2P_DATA_WIDTH SIXTEEN_BIT//EIGHT_BIT
|
||||
#define SPISE2P_ADDR_WIDTH SIXTEEN_BIT
|
||||
#define SPIBAUD_REG_VAL 1//12
|
||||
#define SPICLK_PHASE 1
|
||||
#define SPICLK_POLARITY 0
|
||||
|
||||
#define SPIBAUD_RATE 100000
|
||||
//10000000
|
||||
|
||||
/**************************************************************/
|
||||
/**************************************************************/
|
||||
|
||||
/* Serial EEPROM Command words, left justified */
|
||||
#define SPISE2P_READ_CMD 0x0300
|
||||
#define SPISE2P_WRITE_CMD 0x0200
|
||||
#define SPISE2P_WRDI_CMD 0x0400
|
||||
#define SPISE2P_WREN_CMD 0x0600
|
||||
#define SPISE2P_RDSR_CMD 0x0500
|
||||
#define SPISE2P_WRSR_CMD 0x0100
|
||||
|
||||
#define SPISE2P_RDID_CMD 0x0A00
|
||||
|
||||
#define SPISE2P_DUMMY_DATA 0x0000
|
||||
#define SPISE2P_BUSY_MASK 0x01
|
||||
|
||||
/* Symbolic constant for SPICCR to transfer 8bit or 16 bit value*/
|
||||
#define SPISE2P_TFR16BIT 0x80|(SPICLK_POLARITY<<6)|SIXTEEN_BIT
|
||||
#define SPISE2P_TFR8BIT 0x80|(SPICLK_POLARITY<<6)|EIGHT_BIT
|
||||
|
||||
/* Status valus */
|
||||
#define SPISE2P_WRRQ 1 /* Write Requset */
|
||||
#define SPISE2P_RDRQ 2 /* Read request */
|
||||
#define SPISE2P_WRIP 4 /* Write in progress */
|
||||
#define SPISE2P_RDIP 8 /* Read in progress */
|
||||
|
||||
/* Message declaration */
|
||||
typedef struct {
|
||||
unsigned int *dataPtr; /* Data pointer */
|
||||
unsigned long nrData; /* number of data */
|
||||
unsigned long se2pAddr; /* se2pAddr */
|
||||
}SE2P_DATA;
|
||||
|
||||
|
||||
/* Object declaration */
|
||||
typedef struct {
|
||||
SE2P_DATA *msgPtr;
|
||||
unsigned int csr; /* control/status register */
|
||||
void (*init)(void *);
|
||||
void (*tick)(void *);
|
||||
void (*csset)(void);
|
||||
void (*csclr)(void);
|
||||
}SPISE2P_DRV;
|
||||
|
||||
#define SPISE2P_DRV_DEFAULTS { NULL,\
|
||||
0,\
|
||||
(void (*)(void *))SPISE2P_DRV_init,\
|
||||
(void (*)(void *))SPISE2P_DRV_tick,\
|
||||
(void (*)(void))SPISE2P_DRV_csset,\
|
||||
(void (*)(void))SPISE2P_DRV_csclr}
|
||||
|
||||
typedef SPISE2P_DRV *SPISE2P_DRV_handle;
|
||||
|
||||
void SPISE2P_DRV_init(SPISE2P_DRV * );
|
||||
void SPISE2P_DRV_tick(SPISE2P_DRV *);
|
||||
void SPISE2P_DRV_csset(void);
|
||||
void SPISE2P_DRV_csclr(void);
|
||||
|
||||
unsigned int spiSe2pFree(SPISE2P_DRV *se2p);
|
||||
void spiSe2pWrite(SPISE2P_DRV *se2p, SE2P_DATA *data);
|
||||
void spiSe2pRead(SPISE2P_DRV *se2p, SE2P_DATA *data);
|
||||
|
||||
#if(SPISE2P_DATA_WIDTH==SIXTEEN_BIT)
|
||||
#define PROM_LEN 0x8000
|
||||
#define PAGE_LEN 0x20
|
||||
#define WORD_LEN 2
|
||||
#else
|
||||
#define PROM_LEN 0x4000
|
||||
#define PAGE_LEN 0x40
|
||||
#define WORD_LEN 1
|
||||
#endif
|
||||
|
||||
/* Óñòàíîâêà äðàéâåðà ñåðèàëüíîé EEPROM. **
|
||||
** Èíèöèàëèçàöèà SPI è ïðî÷. Òàêæå íàñòðîéêà òàéìåðà. **
|
||||
** Äðàéâåð ðàáîòàåò íà ïðåðûâàíèàõ îò òàéìåðà 2! */
|
||||
void Init_Seeprom(void);
|
||||
|
||||
/* Çàïèñü áëîêà â SEEPROM. Ïàðàìåòðû òàêîâû: **
|
||||
** adres - àäðåñ â åïðîìêå, êóäà ïèñàòü. **
|
||||
** adres = 0..0x8000, åñëè äëèíà ñëîâà 8 áèò **
|
||||
** adres = 0..0x4000, åñëè äëèíà ñëîâà 16 áèò **
|
||||
** buf - óêàçàòåëü íà ïàìàòü, îòêóäà ïèñàòü. **
|
||||
** size - äëèíà áëîêà â áàéòàõ. Ïî-ëþáîìó â áàéòàõ! */
|
||||
void Seeprom_write(unsigned int adres, unsigned int buf[], unsigned int size);
|
||||
|
||||
/* ×òåíèå áëîêà èç SEEPROM. Ïàðàìåòðû òàêîâû: **
|
||||
** adres - àäðåñ â åïðîìêå, îòêóäà ÷èòàòü. **
|
||||
** adres = 0..0x8000, åñëè äëèíà ñëîâà 8 áèò **
|
||||
** adres = 0..0x4000, åñëè äëèíà ñëîâà 16 áèò **
|
||||
** buf - óêàçàòåëü íà ïàìàòü, êóäà ÷èòàòü. **
|
||||
** size - äëèíà áëîêà â áàéòàõ. Ïî-ëþáîìó â áàéòàõ! */
|
||||
void Seeprom_read(unsigned int adres, unsigned int buf[], unsigned int size);
|
||||
|
||||
#endif
|
||||
|
||||
183
test.c
Normal file
183
test.c
Normal file
@@ -0,0 +1,183 @@
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_SWPrioritizedIsrLevels.h"
|
||||
|
||||
#include "RS485.h"
|
||||
#include "message.h"
|
||||
#include "filter_bat2.h"
|
||||
#include "measure.h"
|
||||
#include "package.h"
|
||||
#include "test.h"
|
||||
#include "kanal.h"
|
||||
#include "peripher.h"
|
||||
|
||||
WORDE PRES;
|
||||
|
||||
int isMask = 1;
|
||||
int isLamp = 0;
|
||||
int isBrit = 0;
|
||||
int isNumb = 1111;
|
||||
|
||||
long cownt=0;
|
||||
|
||||
unsigned int Light = 0xFFFF;
|
||||
|
||||
int quaLamp = 6;
|
||||
|
||||
void what_is()
|
||||
{
|
||||
static int numb=0;
|
||||
|
||||
if(keyTest)
|
||||
{
|
||||
if(keyNext & !preNext)
|
||||
{
|
||||
if(!isBrit)
|
||||
{
|
||||
isBrit=1;
|
||||
isMask=1;
|
||||
isLamp=0;
|
||||
}
|
||||
else
|
||||
{
|
||||
isMask<<=1;
|
||||
|
||||
if(++isLamp >= quaLamp)
|
||||
{
|
||||
isMask=1;
|
||||
isLamp=0;
|
||||
} } }
|
||||
|
||||
if(isBrit)
|
||||
{
|
||||
if(keyUp && !preUp)
|
||||
if(Bright[isLamp]<10) Bright[isLamp]++;
|
||||
|
||||
if(keyDown & !preDown)
|
||||
if(Bright[isLamp]>0) Bright[isLamp]--;
|
||||
}
|
||||
else
|
||||
{
|
||||
if(cownt) cownt--;
|
||||
else
|
||||
{
|
||||
cownt = BLN_FREQ/4;
|
||||
|
||||
numb++; if(numb==10) numb=1;
|
||||
isNumb = numb*1111;
|
||||
|
||||
if(!isMask) isMask = 0xFFFF;
|
||||
else isMask = 0;
|
||||
} } }
|
||||
|
||||
else
|
||||
{
|
||||
if(isBrit)
|
||||
{
|
||||
isBrit=0;
|
||||
Save_params();
|
||||
} }
|
||||
|
||||
PRES = KEYS;
|
||||
}
|
||||
|
||||
|
||||
interrupt void cpu_timer1_isr_PULT(void)
|
||||
{
|
||||
static int count_bright=0;
|
||||
unsigned int light=0, i;
|
||||
static LONGE Diod1,Diod2;
|
||||
static unsigned int Cownt,cownt;
|
||||
int dig1,dig2;
|
||||
|
||||
EALLOW;
|
||||
CpuTimer1.InterruptCount++;
|
||||
IER |= MINT13; // Set "global" priority
|
||||
EINT;
|
||||
EDIS; // This is needed to disable write to EALLOW protected registers
|
||||
|
||||
GpioDataRegs.GPATOGGLE.bit.GPIO0=1; // Ready
|
||||
|
||||
if(count_bright) count_bright --;
|
||||
else count_bright = 9;
|
||||
for(i=0; i<quaLamp; i++)
|
||||
{
|
||||
if(count_bright < Bright[i]) light+=(1<<i);
|
||||
}
|
||||
Light = light;
|
||||
|
||||
Modbus[16].all = Inputs.all | cTestLamp;
|
||||
|
||||
if(Modbus[16].bit.bit4) GpioDataRegs.GPASET.bit.GPIO2=1; //
|
||||
else GpioDataRegs.GPACLEAR.bit.GPIO2=1; //
|
||||
|
||||
Cownt++; cownt = Cownt&3;
|
||||
|
||||
what_is();
|
||||
|
||||
if(isBrit)
|
||||
{
|
||||
if(cownt==0) kanal_Send(adr_digg1,isLamp,0);
|
||||
if(cownt==1) kanal_Send(adr_digg2,Bright[isLamp],0);
|
||||
}
|
||||
else
|
||||
{
|
||||
if(keyTest)
|
||||
{
|
||||
dig1 = isNumb;
|
||||
dig2 = isNumb;
|
||||
}
|
||||
else
|
||||
{
|
||||
dig1 = Modbus[0].all;
|
||||
dig2 = Modbus[1].all;
|
||||
}
|
||||
|
||||
if(cownt==0) kanal_Send(adr_digg1,dig1,0);
|
||||
if(cownt==1) kanal_Send(adr_digg2,dig2,0);
|
||||
}
|
||||
|
||||
if(keyTest) kanal_Send(adr_lamps, isMask & Light,0);
|
||||
else kanal_Send(adr_lamps, Modbus[2].all & Light,0);
|
||||
|
||||
if(Mode==adr_PLT1)
|
||||
{
|
||||
if(keyTest)
|
||||
{
|
||||
Diod1.wrd.word_0 = isMask;
|
||||
Diod1.wrd.word_1 = isMask;
|
||||
Diod2.wrd.word_0 = isMask;
|
||||
Diod2.wrd.word_1 = isMask;
|
||||
}
|
||||
else
|
||||
{
|
||||
Diod1.wrd.word_0 = Modbus[3].all;
|
||||
Diod1.wrd.word_1 = Modbus[4].all;
|
||||
Diod2.wrd.word_0 = Modbus[5].all;
|
||||
Diod2.wrd.word_1 = Modbus[6].all;
|
||||
}
|
||||
if(cownt==2) kanal_Send(adr_diod1,Diod1.all,0);
|
||||
if(cownt==3) kanal_Send(adr_diod2,Diod2.all,0);
|
||||
}
|
||||
|
||||
ServiceDog();
|
||||
}
|
||||
|
||||
void timer_Init()
|
||||
{
|
||||
|
||||
#ifdef TUBER
|
||||
if(Mode==adr_PLT2) quaLamp = 4;
|
||||
#endif
|
||||
#ifdef P20183
|
||||
if(Mode==adr_PLT2) quaLamp = 4;
|
||||
if(Mode==adr_PLT3) quaLamp = 4;
|
||||
#endif
|
||||
|
||||
EALLOW; // This is needed to write to EALLOW protected registers
|
||||
PieVectTable.XINT13 = &cpu_timer1_isr_PULT;
|
||||
EDIS; // This is needed to disable write to EALLOW protected registers
|
||||
|
||||
ConfigCpuTimer(&CpuTimer1, SYSCLKOUT/1000000, 1000000/BLN_FREQ);
|
||||
CpuTimer1Regs.TCR.all = 0x4020; // Use write-only instruction to set TSS bit = 0
|
||||
IER |= M_INT13;
|
||||
}
|
||||
17
test.h
Normal file
17
test.h
Normal file
@@ -0,0 +1,17 @@
|
||||
#define KEYS Modbus[16]
|
||||
#define keyTest KEYS.bit.bit0
|
||||
#define keyUp KEYS.bit.bit1
|
||||
#define keyDown KEYS.bit.bit2
|
||||
#define keyNext KEYS.bit.bit3
|
||||
|
||||
#define preTest PRES.bit.bit0
|
||||
#define preUp PRES.bit.bit1
|
||||
#define preDown PRES.bit.bit2
|
||||
#define preNext PRES.bit.bit3
|
||||
|
||||
#define BLN_FREQ 2000//500 // 2000
|
||||
|
||||
void what_is(void);
|
||||
void timer_Init(void);
|
||||
|
||||
//extern int isMask, isLamp, isBrit;
|
||||
80
tools.c
Normal file
80
tools.c
Normal file
@@ -0,0 +1,80 @@
|
||||
#include "DSP2833x_Device.h" // DSP281x Headerfile Include File
|
||||
|
||||
// Configure the timing paramaters for Zone 7.
|
||||
// Notes:
|
||||
// This function should not be executed from XINTF
|
||||
// Adjust the timing based on the data manual and
|
||||
// external device requirements.
|
||||
void init_zone7(void)
|
||||
{
|
||||
|
||||
// Make sure the XINTF clock is enabled
|
||||
SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1;
|
||||
|
||||
// Configure the GPIO for XINTF with a 16-bit data bus
|
||||
// This function is in DSP2833x_Xintf.c
|
||||
InitXintf16Gpio();
|
||||
EALLOW;
|
||||
// All Zones---------------------------------
|
||||
// Timing for all zones based on XTIMCLK = SYSCLKOUT
|
||||
XintfRegs.XINTCNF2.bit.XTIMCLK = 0;
|
||||
// Buffer up to 3 writes
|
||||
XintfRegs.XINTCNF2.bit.WRBUFF = 3;
|
||||
// XCLKOUT is enabled
|
||||
XintfRegs.XINTCNF2.bit.CLKOFF = 0;
|
||||
// XCLKOUT = XTIMCLK
|
||||
XintfRegs.XINTCNF2.bit.CLKMODE = 0;
|
||||
|
||||
// Zone 7------------------------------------
|
||||
// When using ready, ACTIVE must be 1 or greater
|
||||
// Lead must always be 1 or greater
|
||||
// Zone write timing
|
||||
XintfRegs.XTIMING7.bit.XWRLEAD = 1;
|
||||
XintfRegs.XTIMING7.bit.XWRACTIVE = 2;
|
||||
XintfRegs.XTIMING7.bit.XWRTRAIL = 1;
|
||||
// Zone read timing
|
||||
XintfRegs.XTIMING7.bit.XRDLEAD = 1;
|
||||
XintfRegs.XTIMING7.bit.XRDACTIVE = 3;
|
||||
XintfRegs.XTIMING7.bit.XRDTRAIL = 0;
|
||||
|
||||
// don't double all Zone read/write lead/active/trail timing
|
||||
XintfRegs.XTIMING7.bit.X2TIMING = 0;
|
||||
|
||||
// Zone will not sample XREADY signal
|
||||
XintfRegs.XTIMING7.bit.USEREADY = 0;
|
||||
XintfRegs.XTIMING7.bit.READYMODE = 0;
|
||||
|
||||
// 1,1 = x16 data bus
|
||||
// 0,1 = x32 data bus
|
||||
// other values are reserved
|
||||
XintfRegs.XTIMING7.bit.XSIZE = 3;
|
||||
EDIS;
|
||||
|
||||
//Force a pipeline flush to ensure that the write to
|
||||
//the last register configured occurs before returning.
|
||||
asm(" RPT #7 || NOP");
|
||||
}
|
||||
|
||||
void setup_leds_line()
|
||||
{
|
||||
EALLOW;
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0;
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 0;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO32 = 1;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO48 = 1;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
void pause_us(unsigned long t)
|
||||
{
|
||||
unsigned long i;
|
||||
|
||||
t = t >> 1;
|
||||
|
||||
for (i = 0; i < t; i++)
|
||||
DSP28x_usDelay(CLKMULT*8L);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
26
tools.h
Normal file
26
tools.h
Normal file
@@ -0,0 +1,26 @@
|
||||
#ifndef TOOLS_H
|
||||
#define TOOLS_H
|
||||
|
||||
void init_zone7(void);
|
||||
|
||||
void setup_leds_line(void);
|
||||
|
||||
void pause_us(unsigned long t);
|
||||
|
||||
#ifndef TUBER
|
||||
#define led1_toggle() GpioDataRegs.GPBTOGGLE.bit.GPIO32=1
|
||||
#define led2_toggle() GpioDataRegs.GPBTOGGLE.bit.GPIO48=1
|
||||
#define led1_off() GpioDataRegs.GPBSET.bit.GPIO32=1
|
||||
#define led2_off() GpioDataRegs.GPBSET.bit.GPIO48=1
|
||||
#define led1_on() GpioDataRegs.GPBCLEAR.bit.GPIO32=1
|
||||
#define led2_on() GpioDataRegs.GPBCLEAR.bit.GPIO48=1
|
||||
#else
|
||||
#define led1_toggle() GpioDataRegs.GPBTOGGLE.bit.GPIO32=1
|
||||
#define led2_toggle() GpioDataRegs.GPBTOGGLE.bit.GPIO32=1
|
||||
#define led1_off() GpioDataRegs.GPBSET.bit.GPIO32=1
|
||||
#define led2_off() GpioDataRegs.GPBSET.bit.GPIO32=1
|
||||
#define led1_on() GpioDataRegs.GPBCLEAR.bit.GPIO32=1
|
||||
#define led2_on() GpioDataRegs.GPBCLEAR.bit.GPIO32=1
|
||||
#endif
|
||||
|
||||
#endif //TOOLS_H
|
||||
164
v120/DSP2833x_common/include/DSP2833x_EPwm_defines.h
Normal file
164
v120/DSP2833x_common/include/DSP2833x_EPwm_defines.h
Normal file
@@ -0,0 +1,164 @@
|
||||
// TI File $Revision: /main/1 $
|
||||
// Checkin $Date: August 18, 2006 13:45:39 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_EPwm_defines.h
|
||||
//
|
||||
// TITLE: #defines used in ePWM examples examples
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_EPWM_DEFINES_H
|
||||
#define DSP2833x_EPWM_DEFINES_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// TBCTL (Time-Base Control)
|
||||
//==========================
|
||||
// CTRMODE bits
|
||||
#define TB_COUNT_UP 0x0
|
||||
#define TB_COUNT_DOWN 0x1
|
||||
#define TB_COUNT_UPDOWN 0x2
|
||||
#define TB_FREEZE 0x3
|
||||
// PHSEN bit
|
||||
#define TB_DISABLE 0x0
|
||||
#define TB_ENABLE 0x1
|
||||
// PRDLD bit
|
||||
#define TB_SHADOW 0x0
|
||||
#define TB_IMMEDIATE 0x1
|
||||
// SYNCOSEL bits
|
||||
#define TB_SYNC_IN 0x0
|
||||
#define TB_CTR_ZERO 0x1
|
||||
#define TB_CTR_CMPB 0x2
|
||||
#define TB_SYNC_DISABLE 0x3
|
||||
// HSPCLKDIV and CLKDIV bits
|
||||
#define TB_DIV1 0x0
|
||||
#define TB_DIV2 0x1
|
||||
#define TB_DIV4 0x2
|
||||
// PHSDIR bit
|
||||
#define TB_DOWN 0x0
|
||||
#define TB_UP 0x1
|
||||
|
||||
// CMPCTL (Compare Control)
|
||||
//==========================
|
||||
// LOADAMODE and LOADBMODE bits
|
||||
#define CC_CTR_ZERO 0x0
|
||||
#define CC_CTR_PRD 0x1
|
||||
#define CC_CTR_ZERO_PRD 0x2
|
||||
#define CC_LD_DISABLE 0x3
|
||||
// SHDWAMODE and SHDWBMODE bits
|
||||
#define CC_SHADOW 0x0
|
||||
#define CC_IMMEDIATE 0x1
|
||||
|
||||
// AQCTLA and AQCTLB (Action Qualifier Control)
|
||||
//=============================================
|
||||
// ZRO, PRD, CAU, CAD, CBU, CBD bits
|
||||
#define AQ_NO_ACTION 0x0
|
||||
#define AQ_CLEAR 0x1
|
||||
#define AQ_SET 0x2
|
||||
#define AQ_TOGGLE 0x3
|
||||
|
||||
// DBCTL (Dead-Band Control)
|
||||
//==========================
|
||||
// OUT MODE bits
|
||||
#define DB_DISABLE 0x0
|
||||
#define DBA_ENABLE 0x1
|
||||
#define DBB_ENABLE 0x2
|
||||
#define DB_FULL_ENABLE 0x3
|
||||
// POLSEL bits
|
||||
#define DB_ACTV_HI 0x0
|
||||
#define DB_ACTV_LOC 0x1
|
||||
#define DB_ACTV_HIC 0x2
|
||||
#define DB_ACTV_LO 0x3
|
||||
// IN MODE
|
||||
#define DBA_ALL 0x0
|
||||
#define DBB_RED_DBA_FED 0x1
|
||||
#define DBA_RED_DBB_FED 0x2
|
||||
#define DBB_ALL 0x3
|
||||
|
||||
// CHPCTL (chopper control)
|
||||
//==========================
|
||||
// CHPEN bit
|
||||
#define CHP_DISABLE 0x0
|
||||
#define CHP_ENABLE 0x1
|
||||
// CHPFREQ bits
|
||||
#define CHP_DIV1 0x0
|
||||
#define CHP_DIV2 0x1
|
||||
#define CHP_DIV3 0x2
|
||||
#define CHP_DIV4 0x3
|
||||
#define CHP_DIV5 0x4
|
||||
#define CHP_DIV6 0x5
|
||||
#define CHP_DIV7 0x6
|
||||
#define CHP_DIV8 0x7
|
||||
// CHPDUTY bits
|
||||
#define CHP1_8TH 0x0
|
||||
#define CHP2_8TH 0x1
|
||||
#define CHP3_8TH 0x2
|
||||
#define CHP4_8TH 0x3
|
||||
#define CHP5_8TH 0x4
|
||||
#define CHP6_8TH 0x5
|
||||
#define CHP7_8TH 0x6
|
||||
|
||||
// TZSEL (Trip Zone Select)
|
||||
//==========================
|
||||
// CBCn and OSHTn bits
|
||||
#define TZ_DISABLE 0x0
|
||||
#define TZ_ENABLE 0x1
|
||||
|
||||
// TZCTL (Trip Zone Control)
|
||||
//==========================
|
||||
// TZA and TZB bits
|
||||
#define TZ_HIZ 0x0
|
||||
#define TZ_FORCE_HI 0x1
|
||||
#define TZ_FORCE_LO 0x2
|
||||
#define TZ_NO_CHANGE 0x3
|
||||
|
||||
// ETSEL (Event Trigger Select)
|
||||
//=============================
|
||||
#define ET_CTR_ZERO 0x1
|
||||
#define ET_CTR_PRD 0x2
|
||||
#define ET_CTRU_CMPA 0x4
|
||||
#define ET_CTRD_CMPA 0x5
|
||||
#define ET_CTRU_CMPB 0x6
|
||||
#define ET_CTRD_CMPB 0x7
|
||||
|
||||
// ETPS (Event Trigger Pre-scale)
|
||||
//===============================
|
||||
// INTPRD, SOCAPRD, SOCBPRD bits
|
||||
#define ET_DISABLE 0x0
|
||||
#define ET_1ST 0x1
|
||||
#define ET_2ND 0x2
|
||||
#define ET_3RD 0x3
|
||||
|
||||
|
||||
//--------------------------------
|
||||
// HRPWM (High Resolution PWM)
|
||||
//================================
|
||||
// HRCNFG
|
||||
#define HR_Disable 0x0
|
||||
#define HR_REP 0x1
|
||||
#define HR_FEP 0x2
|
||||
#define HR_BEP 0x3
|
||||
|
||||
#define HR_CMP 0x0
|
||||
#define HR_PHS 0x1
|
||||
|
||||
#define HR_CTR_ZERO 0x0
|
||||
#define HR_CTR_PRD 0x1
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // - end of DSP2833x_EPWM_DEFINES_H
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
143
v120/DSP2833x_common/include/DSP2833x_Examples.h
Normal file
143
v120/DSP2833x_common/include/DSP2833x_Examples.h
Normal file
@@ -0,0 +1,143 @@
|
||||
// TI File $Revision: /main/9 $
|
||||
// Checkin $Date: July 2, 2008 14:31:12 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Examples.h
|
||||
//
|
||||
// TITLE: DSP2833x Device Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_EXAMPLES_H
|
||||
#define DSP2833x_EXAMPLES_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
Specify the PLL control register (PLLCR) and divide select (DIVSEL) value.
|
||||
-----------------------------------------------------------------------------*/
|
||||
//#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT
|
||||
//#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT
|
||||
#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT
|
||||
//#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT
|
||||
|
||||
#define DSP28_PLLCR CLKMULT*2
|
||||
|
||||
//#define DSP28_PLLCR 10
|
||||
//#define DSP28_PLLCR 9
|
||||
//#define DSP28_PLLCR 8
|
||||
//#define DSP28_PLLCR 7
|
||||
//#define DSP28_PLLCR 6
|
||||
//#define DSP28_PLLCR 5
|
||||
//#define DSP28_PLLCR 4
|
||||
//#define DSP28_PLLCR 3
|
||||
//#define DSP28_PLLCR 2
|
||||
//#define DSP28_PLLCR 1
|
||||
//#define DSP28_PLLCR 0 // PLL is bypassed in this mode
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
Specify the clock rate of the CPU (SYSCLKOUT) in nS.
|
||||
|
||||
Take into account the input clock frequency and the PLL multiplier
|
||||
selected in step 1.
|
||||
|
||||
Use one of the values provided, or define your own.
|
||||
The trailing L is required tells the compiler to treat
|
||||
the number as a 64-bit value.
|
||||
|
||||
Only one statement should be uncommented.
|
||||
|
||||
Example 1:150 MHz devices:
|
||||
CLKIN is a 30MHz crystal.
|
||||
|
||||
In step 1 the user specified PLLCR = 0xA for a
|
||||
150Mhz CPU clock (SYSCLKOUT = 150MHz).
|
||||
|
||||
In this case, the CPU_RATE will be 6.667L
|
||||
Uncomment the line: #define CPU_RATE 6.667L
|
||||
|
||||
Example 2: 100 MHz devices:
|
||||
CLKIN is a 20MHz crystal.
|
||||
|
||||
In step 1 the user specified PLLCR = 0xA for a
|
||||
100Mhz CPU clock (SYSCLKOUT = 100MHz).
|
||||
|
||||
In this case, the CPU_RATE will be 10.000L
|
||||
Uncomment the line: #define CPU_RATE 10.000L
|
||||
-----------------------------------------------------------------------------*/
|
||||
#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT)
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
Target device (in DSP2833x_Device.h) determines CPU frequency
|
||||
(for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz
|
||||
(for 28332). User does not have to change anything here.
|
||||
-----------------------------------------------------------------------------*/
|
||||
#if DSP28_28332 // DSP28_28332 device only
|
||||
#define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq)
|
||||
#define CPU_FRQ_150MHZ 0
|
||||
#else
|
||||
#define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334
|
||||
#define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Include Example Header Files:
|
||||
//
|
||||
|
||||
#include "DSP2833x_GlobalPrototypes.h" // Prototypes for global functions within the
|
||||
// .c files.
|
||||
|
||||
#include "DSP2833x_ePwm_defines.h" // Macros used for PWM examples.
|
||||
#include "DSP2833x_Dma_defines.h" // Macros used for DMA examples.
|
||||
#include "DSP2833x_I2C_defines.h" // Macros used for I2C examples.
|
||||
|
||||
#define PARTNO_28335 0xEF
|
||||
#define PARTNO_28334 0xEE
|
||||
#define PARTNO_28332 0xED
|
||||
#define PARTNO_28235 0xE8
|
||||
#define PARTNO_28234 0xE7
|
||||
#define PARTNO_28232 0xE6
|
||||
|
||||
|
||||
// Include files not used with DSP/BIOS
|
||||
#ifndef DSP28_BIOS
|
||||
#include "DSP2833x_DefaultISR.h"
|
||||
#endif
|
||||
|
||||
|
||||
// DO NOT MODIFY THIS LINE.
|
||||
#define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / (long double)CPU_RATE) - 9.0L) / 5.0L)
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_EXAMPLES_H definition
|
||||
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
207
v120/DSP2833x_common/include/DSP2833x_GlobalPrototypes.h
Normal file
207
v120/DSP2833x_common/include/DSP2833x_GlobalPrototypes.h
Normal file
@@ -0,0 +1,207 @@
|
||||
// TI File $Revision: /main/11 $
|
||||
// Checkin $Date: May 12, 2008 14:30:08 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_GlobalPrototypes.h
|
||||
//
|
||||
// TITLE: Global prototypes for DSP2833x Examples
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_GLOBALPROTOTYPES_H
|
||||
#define DSP2833x_GLOBALPROTOTYPES_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*---- shared global function prototypes -----------------------------------*/
|
||||
extern void InitAdc(void);
|
||||
|
||||
extern void DMAInitialize(void);
|
||||
// DMA Channel 1
|
||||
extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
|
||||
extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
|
||||
extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||
extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
|
||||
extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
|
||||
extern void StartDMACH1(void);
|
||||
// DMA Channel 2
|
||||
extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
|
||||
extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
|
||||
extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||
extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
|
||||
extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
|
||||
extern void StartDMACH2(void);
|
||||
// DMA Channel 3
|
||||
extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
|
||||
extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
|
||||
extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||
extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
|
||||
extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
|
||||
extern void StartDMACH3(void);
|
||||
// DMA Channel 4
|
||||
extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
|
||||
extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
|
||||
extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||
extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
|
||||
extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
|
||||
extern void StartDMACH4(void);
|
||||
// DMA Channel 5
|
||||
extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
|
||||
extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
|
||||
extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||
extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
|
||||
extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
|
||||
extern void StartDMACH5(void);
|
||||
// DMA Channel 6
|
||||
extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
|
||||
extern void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep);
|
||||
extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||
extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
|
||||
extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
|
||||
extern void StartDMACH6(void);
|
||||
|
||||
extern void InitPeripherals(void);
|
||||
#if DSP28_ECANA
|
||||
extern void InitECan(void);
|
||||
extern void InitECana(void);
|
||||
extern void InitECanGpio(void);
|
||||
extern void InitECanaGpio(void);
|
||||
#endif // endif DSP28_ECANA
|
||||
#if DSP28_ECANB
|
||||
extern void InitECanb(void);
|
||||
extern void InitECanbGpio(void);
|
||||
#endif // endif DSP28_ECANB
|
||||
extern void InitECap(void);
|
||||
extern void InitECapGpio(void);
|
||||
extern void InitECap1Gpio(void);
|
||||
extern void InitECap2Gpio(void);
|
||||
#if DSP28_ECAP3
|
||||
extern void InitECap3Gpio(void);
|
||||
#endif // endif DSP28_ECAP3
|
||||
#if DSP28_ECAP4
|
||||
extern void InitECap4Gpio(void);
|
||||
#endif // endif DSP28_ECAP4
|
||||
#if DSP28_ECAP5
|
||||
extern void InitECap5Gpio(void);
|
||||
#endif // endif DSP28_ECAP5
|
||||
#if DSP28_ECAP6
|
||||
extern void InitECap6Gpio(void);
|
||||
#endif // endif DSP28_ECAP6
|
||||
extern void InitEPwm(void);
|
||||
extern void InitEPwmGpio(void);
|
||||
extern void InitEPwm1Gpio(void);
|
||||
extern void InitEPwm2Gpio(void);
|
||||
extern void InitEPwm3Gpio(void);
|
||||
#if DSP28_EPWM4
|
||||
extern void InitEPwm4Gpio(void);
|
||||
#endif // endif DSP28_EPWM4
|
||||
#if DSP28_EPWM5
|
||||
extern void InitEPwm5Gpio(void);
|
||||
#endif // endif DSP28_EPWM5
|
||||
#if DSP28_EPWM6
|
||||
extern void InitEPwm6Gpio(void);
|
||||
#endif // endif DSP28_EPWM6
|
||||
#if DSP28_EQEP1
|
||||
extern void InitEQep(void);
|
||||
extern void InitEQepGpio(void);
|
||||
extern void InitEQep1Gpio(void);
|
||||
#endif // if DSP28_EQEP1
|
||||
#if DSP28_EQEP2
|
||||
extern void InitEQep2Gpio(void);
|
||||
#endif // endif DSP28_EQEP2
|
||||
extern void InitGpio(void);
|
||||
extern void InitI2CGpio(void);
|
||||
|
||||
extern void InitMcbsp(void);
|
||||
extern void InitMcbspa(void);
|
||||
extern void delay_loop(void);
|
||||
extern void InitMcbspaGpio(void);
|
||||
extern void InitMcbspa8bit(void);
|
||||
extern void InitMcbspa12bit(void);
|
||||
extern void InitMcbspa16bit(void);
|
||||
extern void InitMcbspa20bit(void);
|
||||
extern void InitMcbspa24bit(void);
|
||||
extern void InitMcbspa32bit(void);
|
||||
#if DSP28_MCBSPB
|
||||
extern void InitMcbspb(void);
|
||||
extern void InitMcbspbGpio(void);
|
||||
extern void InitMcbspb8bit(void);
|
||||
extern void InitMcbspb12bit(void);
|
||||
extern void InitMcbspb16bit(void);
|
||||
extern void InitMcbspb20bit(void);
|
||||
extern void InitMcbspb24bit(void);
|
||||
extern void InitMcbspb32bit(void);
|
||||
#endif // endif DSP28_MCBSPB
|
||||
|
||||
extern void InitPieCtrl(void);
|
||||
extern void InitPieVectTable(void);
|
||||
|
||||
extern void InitSci(void);
|
||||
extern void InitSciGpio(void);
|
||||
extern void InitSciaGpio(void);
|
||||
#if DSP28_SCIB
|
||||
extern void InitScibGpio(void);
|
||||
#endif // endif DSP28_SCIB
|
||||
#if DSP28_SCIC
|
||||
extern void InitScicGpio(void);
|
||||
#endif
|
||||
extern void InitSpi(void);
|
||||
extern void InitSpiGpio(void);
|
||||
extern void InitSpiaGpio(void);
|
||||
extern void InitSysCtrl(void);
|
||||
extern void InitTzGpio(void);
|
||||
extern void InitXIntrupt(void);
|
||||
extern void XintfInit(void);
|
||||
extern void InitXintf16Gpio();
|
||||
extern void InitXintf32Gpio();
|
||||
extern void InitPll(Uint16 pllcr, Uint16 clkindiv);
|
||||
extern void InitPeripheralClocks(void);
|
||||
extern void EnableInterrupts(void);
|
||||
extern void DSP28x_usDelay(Uint32 Count);
|
||||
extern void ADC_cal (void);
|
||||
#define KickDog ServiceDog // For compatiblity with previous versions
|
||||
extern void ServiceDog(void);
|
||||
extern void DisableDog(void);
|
||||
extern Uint16 CsmUnlock(void);
|
||||
|
||||
// DSP28_DBGIER.asm
|
||||
extern void SetDBGIER(Uint16 dbgier);
|
||||
|
||||
// CAUTION
|
||||
// This function MUST be executed out of RAM. Executing it
|
||||
// out of OTP/Flash will yield unpredictable results
|
||||
extern void InitFlash(void);
|
||||
|
||||
|
||||
void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr);
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// External symbols created by the linker cmd file
|
||||
// DSP28 examples will use these to relocate code from one LOAD location
|
||||
// in either Flash or XINTF to a different RUN location in internal
|
||||
// RAM
|
||||
extern Uint16 RamfuncsLoadStart;
|
||||
extern Uint16 RamfuncsLoadEnd;
|
||||
extern Uint16 RamfuncsRunStart;
|
||||
|
||||
extern Uint16 XintffuncsLoadStart;
|
||||
extern Uint16 XintffuncsLoadEnd;
|
||||
extern Uint16 XintffuncsRunStart;
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // - end of DSP2833x_GLOBALPROTOTYPES_H
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
117
v120/DSP2833x_common/include/DSP2833x_I2c_defines.h
Normal file
117
v120/DSP2833x_common/include/DSP2833x_I2c_defines.h
Normal file
@@ -0,0 +1,117 @@
|
||||
// TI File $Revision: /main/2 $
|
||||
// Checkin $Date: April 16, 2008 17:16:47 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_I2cExample.h
|
||||
//
|
||||
// TITLE: 2833x I2C Example Code Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_I2C_DEFINES_H
|
||||
#define DSP2833x_I2C_DEFINES_H
|
||||
|
||||
//--------------------------------------------
|
||||
// Defines
|
||||
//--------------------------------------------
|
||||
|
||||
// Error Messages
|
||||
#define I2C_ERROR 0xFFFF
|
||||
#define I2C_ARB_LOST_ERROR 0x0001
|
||||
#define I2C_NACK_ERROR 0x0002
|
||||
#define I2C_BUS_BUSY_ERROR 0x1000
|
||||
#define I2C_STP_NOT_READY_ERROR 0x5555
|
||||
#define I2C_NO_FLAGS 0xAAAA
|
||||
#define I2C_SUCCESS 0x0000
|
||||
|
||||
// Clear Status Flags
|
||||
#define I2C_CLR_AL_BIT 0x0001
|
||||
#define I2C_CLR_NACK_BIT 0x0002
|
||||
#define I2C_CLR_ARDY_BIT 0x0004
|
||||
#define I2C_CLR_RRDY_BIT 0x0008
|
||||
#define I2C_CLR_SCD_BIT 0x0020
|
||||
|
||||
// Interrupt Source Messages
|
||||
#define I2C_NO_ISRC 0x0000
|
||||
#define I2C_ARB_ISRC 0x0001
|
||||
#define I2C_NACK_ISRC 0x0002
|
||||
#define I2C_ARDY_ISRC 0x0003
|
||||
#define I2C_RX_ISRC 0x0004
|
||||
#define I2C_TX_ISRC 0x0005
|
||||
#define I2C_SCD_ISRC 0x0006
|
||||
#define I2C_AAS_ISRC 0x0007
|
||||
|
||||
// I2CMSG structure defines
|
||||
#define I2C_NO_STOP 0
|
||||
#define I2C_YES_STOP 1
|
||||
#define I2C_RECEIVE 0
|
||||
#define I2C_TRANSMIT 1
|
||||
#define I2C_MAX_BUFFER_SIZE 16
|
||||
|
||||
// I2C Slave State defines
|
||||
#define I2C_NOTSLAVE 0
|
||||
#define I2C_ADDR_AS_SLAVE 1
|
||||
#define I2C_ST_MSG_READY 2
|
||||
|
||||
// I2C Slave Receiver messages defines
|
||||
#define I2C_SND_MSG1 1
|
||||
#define I2C_SND_MSG2 2
|
||||
|
||||
// I2C State defines
|
||||
#define I2C_IDLE 0
|
||||
#define I2C_SLAVE_RECEIVER 1
|
||||
#define I2C_SLAVE_TRANSMITTER 2
|
||||
#define I2C_MASTER_RECEIVER 3
|
||||
#define I2C_MASTER_TRANSMITTER 4
|
||||
|
||||
// I2C Message Commands for I2CMSG struct
|
||||
#define I2C_MSGSTAT_INACTIVE 0x0000
|
||||
#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010
|
||||
#define I2C_MSGSTAT_WRITE_BUSY 0x0011
|
||||
#define I2C_MSGSTAT_SEND_NOSTOP 0x0020
|
||||
#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021
|
||||
#define I2C_MSGSTAT_RESTART 0x0022
|
||||
#define I2C_MSGSTAT_READ_BUSY 0x0023
|
||||
|
||||
// Generic defines
|
||||
#define I2C_TRUE 1
|
||||
#define I2C_FALSE 0
|
||||
#define I2C_YES 1
|
||||
#define I2C_NO 0
|
||||
#define I2C_DUMMY_BYTE 0
|
||||
|
||||
|
||||
//--------------------------------------------
|
||||
// Structures
|
||||
//--------------------------------------------
|
||||
|
||||
// I2C Message Structure
|
||||
struct I2CMSG {
|
||||
Uint16 MsgStatus; // Word stating what state msg is in:
|
||||
// I2C_MSGCMD_INACTIVE = do not send msg
|
||||
// I2C_MSGCMD_BUSY = msg start has been sent,
|
||||
// awaiting stop
|
||||
// I2C_MSGCMD_SEND_WITHSTOP = command to send
|
||||
// master trans msg complete with a stop bit
|
||||
// I2C_MSGCMD_SEND_NOSTOP = command to send
|
||||
// master trans msg without the stop bit
|
||||
// I2C_MSGCMD_RESTART = command to send a restart
|
||||
// as a master receiver with a stop bit
|
||||
Uint16 SlaveAddress; // I2C address of slave msg is intended for
|
||||
Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer)
|
||||
Uint16 MemoryHighAddr; // EEPROM address of data associated with msg (high byte)
|
||||
Uint16 MemoryLowAddr; // EEPROM address of data associated with msg (low byte)
|
||||
Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; // Array holding msg data - max that
|
||||
// MAX_BUFFER_SIZE can be is 16 due to
|
||||
// the FIFO's
|
||||
};
|
||||
|
||||
|
||||
#endif // end of DSP2833x_I2C_DEFINES_H definition
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
5850
v120/DSP2833x_common/include/DSP2833x_SWPrioritizedIsrLevels.h
Normal file
5850
v120/DSP2833x_common/include/DSP2833x_SWPrioritizedIsrLevels.h
Normal file
File diff suppressed because it is too large
Load Diff
83
v120/DSP2833x_common/source/DSP2833x_PieCtrl.c
Normal file
83
v120/DSP2833x_common/source/DSP2833x_PieCtrl.c
Normal file
@@ -0,0 +1,83 @@
|
||||
// TI File $Revision: /main/1 $
|
||||
// Checkin $Date: August 18, 2006 13:46:35 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_PieCtrl.c
|
||||
//
|
||||
// TITLE: DSP2833x Device PIE Control Register Initialization Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// InitPieCtrl:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes the PIE control registers to a known state.
|
||||
//
|
||||
void InitPieCtrl(void)
|
||||
{
|
||||
// Disable Interrupts at the CPU level:
|
||||
DINT;
|
||||
|
||||
// Disable the PIE
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 0;
|
||||
|
||||
// Clear all PIEIER registers:
|
||||
PieCtrlRegs.PIEIER1.all = 0;
|
||||
PieCtrlRegs.PIEIER2.all = 0;
|
||||
PieCtrlRegs.PIEIER3.all = 0;
|
||||
PieCtrlRegs.PIEIER4.all = 0;
|
||||
PieCtrlRegs.PIEIER5.all = 0;
|
||||
PieCtrlRegs.PIEIER6.all = 0;
|
||||
PieCtrlRegs.PIEIER7.all = 0;
|
||||
PieCtrlRegs.PIEIER8.all = 0;
|
||||
PieCtrlRegs.PIEIER9.all = 0;
|
||||
PieCtrlRegs.PIEIER10.all = 0;
|
||||
PieCtrlRegs.PIEIER11.all = 0;
|
||||
PieCtrlRegs.PIEIER12.all = 0;
|
||||
|
||||
// Clear all PIEIFR registers:
|
||||
PieCtrlRegs.PIEIFR1.all = 0;
|
||||
PieCtrlRegs.PIEIFR2.all = 0;
|
||||
PieCtrlRegs.PIEIFR3.all = 0;
|
||||
PieCtrlRegs.PIEIFR4.all = 0;
|
||||
PieCtrlRegs.PIEIFR5.all = 0;
|
||||
PieCtrlRegs.PIEIFR6.all = 0;
|
||||
PieCtrlRegs.PIEIFR7.all = 0;
|
||||
PieCtrlRegs.PIEIFR8.all = 0;
|
||||
PieCtrlRegs.PIEIFR9.all = 0;
|
||||
PieCtrlRegs.PIEIFR10.all = 0;
|
||||
PieCtrlRegs.PIEIFR11.all = 0;
|
||||
PieCtrlRegs.PIEIFR12.all = 0;
|
||||
|
||||
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// EnableInterrupts:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function enables the PIE module and CPU interrupts
|
||||
//
|
||||
void EnableInterrupts()
|
||||
{
|
||||
|
||||
// Enable the PIE
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
|
||||
|
||||
// Enables PIE to drive a pulse into the CPU
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF;
|
||||
|
||||
// Enable Interrupts at the CPU level
|
||||
EINT;
|
||||
|
||||
}
|
||||
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
204
v120/DSP2833x_common/source/DSP2833x_PieVect.c
Normal file
204
v120/DSP2833x_common/source/DSP2833x_PieVect.c
Normal file
@@ -0,0 +1,204 @@
|
||||
// TI File $Revision: /main/1 $
|
||||
// Checkin $Date: August 18, 2006 13:46:38 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_PieVect.c
|
||||
//
|
||||
// TITLE: DSP2833x Devices PIE Vector Table Initialization Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
|
||||
const struct PIE_VECT_TABLE PieVectTableInit = {
|
||||
|
||||
PIE_RESERVED, // 0 Reserved space
|
||||
PIE_RESERVED, // 1 Reserved space
|
||||
PIE_RESERVED, // 2 Reserved space
|
||||
PIE_RESERVED, // 3 Reserved space
|
||||
PIE_RESERVED, // 4 Reserved space
|
||||
PIE_RESERVED, // 5 Reserved space
|
||||
PIE_RESERVED, // 6 Reserved space
|
||||
PIE_RESERVED, // 7 Reserved space
|
||||
PIE_RESERVED, // 8 Reserved space
|
||||
PIE_RESERVED, // 9 Reserved space
|
||||
PIE_RESERVED, // 10 Reserved space
|
||||
PIE_RESERVED, // 11 Reserved space
|
||||
PIE_RESERVED, // 12 Reserved space
|
||||
|
||||
|
||||
// Non-Peripheral Interrupts
|
||||
INT13_ISR, // XINT13 or CPU-Timer 1
|
||||
INT14_ISR, // CPU-Timer2
|
||||
DATALOG_ISR, // Datalogging interrupt
|
||||
RTOSINT_ISR, // RTOS interrupt
|
||||
EMUINT_ISR, // Emulation interrupt
|
||||
NMI_ISR, // Non-maskable interrupt
|
||||
ILLEGAL_ISR, // Illegal operation TRAP
|
||||
USER1_ISR, // User Defined trap 1
|
||||
USER2_ISR, // User Defined trap 2
|
||||
USER3_ISR, // User Defined trap 3
|
||||
USER4_ISR, // User Defined trap 4
|
||||
USER5_ISR, // User Defined trap 5
|
||||
USER6_ISR, // User Defined trap 6
|
||||
USER7_ISR, // User Defined trap 7
|
||||
USER8_ISR, // User Defined trap 8
|
||||
USER9_ISR, // User Defined trap 9
|
||||
USER10_ISR, // User Defined trap 10
|
||||
USER11_ISR, // User Defined trap 11
|
||||
USER12_ISR, // User Defined trap 12
|
||||
|
||||
// Group 1 PIE Vectors
|
||||
SEQ1INT_ISR, // 1.1 ADC
|
||||
SEQ2INT_ISR, // 1.2 ADC
|
||||
rsvd_ISR, // 1.3
|
||||
XINT1_ISR, // 1.4
|
||||
XINT2_ISR, // 1.5
|
||||
ADCINT_ISR, // 1.6 ADC
|
||||
TINT0_ISR, // 1.7 Timer 0
|
||||
WAKEINT_ISR, // 1.8 WD, Low Power
|
||||
|
||||
// Group 2 PIE Vectors
|
||||
EPWM1_TZINT_ISR, // 2.1 EPWM-1 Trip Zone
|
||||
EPWM2_TZINT_ISR, // 2.2 EPWM-2 Trip Zone
|
||||
EPWM3_TZINT_ISR, // 2.3 EPWM-3 Trip Zone
|
||||
EPWM4_TZINT_ISR, // 2.4 EPWM-4 Trip Zone
|
||||
EPWM5_TZINT_ISR, // 2.5 EPWM-5 Trip Zone
|
||||
EPWM6_TZINT_ISR, // 2.6 EPWM-6 Trip Zone
|
||||
rsvd_ISR, // 2.7
|
||||
rsvd_ISR, // 2.8
|
||||
|
||||
// Group 3 PIE Vectors
|
||||
EPWM1_INT_ISR, // 3.1 EPWM-1 Interrupt
|
||||
EPWM2_INT_ISR, // 3.2 EPWM-2 Interrupt
|
||||
EPWM3_INT_ISR, // 3.3 EPWM-3 Interrupt
|
||||
EPWM4_INT_ISR, // 3.4 EPWM-4 Interrupt
|
||||
EPWM5_INT_ISR, // 3.5 EPWM-5 Interrupt
|
||||
EPWM6_INT_ISR, // 3.6 EPWM-6 Interrupt
|
||||
rsvd_ISR, // 3.7
|
||||
rsvd_ISR, // 3.8
|
||||
|
||||
// Group 4 PIE Vectors
|
||||
ECAP1_INT_ISR, // 4.1 ECAP-1
|
||||
ECAP2_INT_ISR, // 4.2 ECAP-2
|
||||
ECAP3_INT_ISR, // 4.3 ECAP-3
|
||||
ECAP4_INT_ISR, // 4.4 ECAP-4
|
||||
ECAP5_INT_ISR, // 4.5 ECAP-5
|
||||
ECAP6_INT_ISR, // 4.6 ECAP-6
|
||||
rsvd_ISR, // 4.7
|
||||
rsvd_ISR, // 4.8
|
||||
|
||||
// Group 5 PIE Vectors
|
||||
EQEP1_INT_ISR, // 5.1 EQEP-1
|
||||
EQEP2_INT_ISR, // 5.2 EQEP-2
|
||||
rsvd_ISR, // 5.3
|
||||
rsvd_ISR, // 5.4
|
||||
rsvd_ISR, // 5.5
|
||||
rsvd_ISR, // 5.6
|
||||
rsvd_ISR, // 5.7
|
||||
rsvd_ISR, // 5.8
|
||||
|
||||
|
||||
// Group 6 PIE Vectors
|
||||
SPIRXINTA_ISR, // 6.1 SPI-A
|
||||
SPITXINTA_ISR, // 6.2 SPI-A
|
||||
MRINTA_ISR, // 6.3 McBSP-A
|
||||
MXINTA_ISR, // 6.4 McBSP-A
|
||||
MRINTB_ISR, // 6.5 McBSP-B
|
||||
MXINTB_ISR, // 6.6 McBSP-B
|
||||
rsvd_ISR, // 6.7
|
||||
rsvd_ISR, // 6.8
|
||||
|
||||
|
||||
// Group 7 PIE Vectors
|
||||
DINTCH1_ISR, // 7.1 DMA channel 1
|
||||
DINTCH2_ISR, // 7.2 DMA channel 2
|
||||
DINTCH3_ISR, // 7.3 DMA channel 3
|
||||
DINTCH4_ISR, // 7.4 DMA channel 4
|
||||
DINTCH5_ISR, // 7.5 DMA channel 5
|
||||
DINTCH6_ISR, // 7.6 DMA channel 6
|
||||
rsvd_ISR, // 7.7
|
||||
rsvd_ISR, // 7.8
|
||||
|
||||
// Group 8 PIE Vectors
|
||||
I2CINT1A_ISR, // 8.1 I2C
|
||||
I2CINT2A_ISR, // 8.2 I2C
|
||||
rsvd_ISR, // 8.3
|
||||
rsvd_ISR, // 8.4
|
||||
SCIRXINTC_ISR, // 8.5 SCI-C
|
||||
SCITXINTC_ISR, // 8.6 SCI-C
|
||||
rsvd_ISR, // 8.7
|
||||
rsvd_ISR, // 8.8
|
||||
|
||||
// Group 9 PIE Vectors
|
||||
SCIRXINTA_ISR, // 9.1 SCI-A
|
||||
SCITXINTA_ISR, // 9.2 SCI-A
|
||||
SCIRXINTB_ISR, // 9.3 SCI-B
|
||||
SCITXINTB_ISR, // 9.4 SCI-B
|
||||
ECAN0INTA_ISR, // 9.5 eCAN-A
|
||||
ECAN1INTA_ISR, // 9.6 eCAN-A
|
||||
ECAN0INTB_ISR, // 9.7 eCAN-B
|
||||
ECAN1INTB_ISR, // 9.8 eCAN-B
|
||||
|
||||
// Group 10 PIE Vectors
|
||||
rsvd_ISR, // 10.1
|
||||
rsvd_ISR, // 10.2
|
||||
rsvd_ISR, // 10.3
|
||||
rsvd_ISR, // 10.4
|
||||
rsvd_ISR, // 10.5
|
||||
rsvd_ISR, // 10.6
|
||||
rsvd_ISR, // 10.7
|
||||
rsvd_ISR, // 10.8
|
||||
|
||||
// Group 11 PIE Vectors
|
||||
rsvd_ISR, // 11.1
|
||||
rsvd_ISR, // 11.2
|
||||
rsvd_ISR, // 11.3
|
||||
rsvd_ISR, // 11.4
|
||||
rsvd_ISR, // 11.5
|
||||
rsvd_ISR, // 11.6
|
||||
rsvd_ISR, // 11.7
|
||||
rsvd_ISR, // 11.8
|
||||
|
||||
// Group 12 PIE Vectors
|
||||
XINT3_ISR, // 12.1
|
||||
XINT4_ISR, // 12.2
|
||||
XINT5_ISR, // 12.3
|
||||
XINT6_ISR, // 12.4
|
||||
XINT7_ISR, // 12.5
|
||||
rsvd_ISR, // 12.6
|
||||
LVF_ISR, // 12.7
|
||||
LUF_ISR, // 12.8
|
||||
};
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// InitPieVectTable:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes the PIE vector table to a known state.
|
||||
// This function must be executed after boot time.
|
||||
//
|
||||
|
||||
void InitPieVectTable(void)
|
||||
{
|
||||
int16 i;
|
||||
Uint32 *Source = (void *) &PieVectTableInit;
|
||||
Uint32 *Dest = (void *) &PieVectTable;
|
||||
|
||||
EALLOW;
|
||||
for(i=0; i < 128; i++)
|
||||
*Dest++ = *Source++;
|
||||
EDIS;
|
||||
|
||||
// Enable the PIE Vector Table
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
|
||||
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
1863
v120/DSP2833x_common/source/DSP2833x_SWPrioritizedDefaultIsr.c
Normal file
1863
v120/DSP2833x_common/source/DSP2833x_SWPrioritizedDefaultIsr.c
Normal file
@@ -0,0 +1,1863 @@
|
||||
// TI File $Revision: /main/5 $
|
||||
// Checkin $Date: January 14, 2008 11:28:12 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_SWPrioritizedDefaultIsr.c
|
||||
//
|
||||
// TITLE: DSP2833x Device Default Software Prioritized Interrupt Service Routines.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
#include "DSP2833x_SWPrioritizedIsrLevels.h"
|
||||
|
||||
|
||||
// Connected to INT13 of CPU (use MINT13 mask):
|
||||
// Note CPU-Timer1 is reserved for TI use, however XINT13
|
||||
// ISR can be used by the user.
|
||||
#if (INT13PL != 0)
|
||||
interrupt void INT13_ISR(void) // INT13 or CPU-Timer1
|
||||
{
|
||||
IER |= MINT13; // Set "global" priority
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to INT14 of CPU (use MINT14 mask):
|
||||
#if (INT14PL != 0)
|
||||
interrupt void INT14_ISR(void) // CPU-Timer2
|
||||
{
|
||||
IER |= MINT14; // Set "global" priority
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to INT15 of CPU (use MINT15 mask):
|
||||
#if (INT15PL != 0)
|
||||
interrupt void DATALOG_ISR(void) // Datalogging interrupt
|
||||
{
|
||||
IER |= MINT15; // Set "global" priority
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to INT16 of CPU (use MINT16 mask):
|
||||
#if (INT16PL != 0)
|
||||
interrupt void RTOSINT_ISR(void) // RTOS interrupt
|
||||
{
|
||||
IER |= MINT16; // Set "global" priority
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to EMUINT of CPU (non-maskable):
|
||||
interrupt void EMUINT_ISR(void) // Emulation interrupt
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
|
||||
// Connected to NMI of CPU (non-maskable):
|
||||
interrupt void NMI_ISR(void) // Non-maskable interrupt
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void ILLEGAL_ISR(void) // Illegal operation TRAP
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
|
||||
interrupt void USER1_ISR(void) // User Defined trap 1
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER2_ISR(void) // User Defined trap 2
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER3_ISR(void) // User Defined trap 3
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER4_ISR(void) // User Defined trap 4
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER5_ISR(void) // User Defined trap 5
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER6_ISR(void) // User Defined trap 6
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER7_ISR(void) // User Defined trap 7
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER8_ISR(void) // User Defined trap 8
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER9_ISR(void) // User Defined trap 9
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER10_ISR(void) // User Defined trap 10
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER11_ISR(void) // User Defined trap 11
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER12_ISR(void) // User Defined trap 12
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 1 - MUXed into CPU INT1
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// Connected to PIEIER1_1 (use MINT1 and MG11 masks):
|
||||
#if (G11PL != 0)
|
||||
interrupt void SEQ1INT_ISR( void ) // ADC
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
|
||||
IER |= M_INT1;
|
||||
IER &= MINT1; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER1.all &= MG11; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER1.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER1_2 (use MINT1 and MG12 masks):
|
||||
#if (G12PL != 0)
|
||||
interrupt void SEQ2INT_ISR( void ) // ADC
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
|
||||
IER |= M_INT1;
|
||||
IER &= MINT1; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER1.all &= MG12; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
|
||||
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER1.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
// Connected to PIEIER1_4 (use MINT1 and MG14 masks):
|
||||
#if (G14PL != 0)
|
||||
interrupt void XINT1_ISR(void)
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
|
||||
IER |= MINT1; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER1.all &= MG14; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER1.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER1_5 (use MINT1 and MG15 masks):
|
||||
#if (G15PL != 0)
|
||||
interrupt void XINT2_ISR(void)
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
|
||||
IER |= MINT1; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER1.all &= MG15; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER1.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
// Connected to PIEIER1_6 (use MINT1 and MG16 masks):
|
||||
#if (G16PL != 0)
|
||||
interrupt void ADCINT_ISR(void) // ADC
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
|
||||
IER |= M_INT1;
|
||||
IER &= MINT1; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER1.all &= MG16; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER1.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER1_7 (use MINT1 and MG17 masks):
|
||||
#if (G17PL != 0)
|
||||
interrupt void TINT0_ISR(void) // CPU-Timer 0
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
|
||||
IER |= M_INT1;
|
||||
IER &= MINT1; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER1.all &= MG17; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER1.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER1_8 (use MINT1 and MG18 masks):
|
||||
#if (G18PL != 0)
|
||||
interrupt void WAKEINT_ISR(void) // WD/LPM
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
|
||||
IER |= M_INT1;
|
||||
IER &= MINT1; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER1.all &= MG18; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER1.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 2 - MUXed into CPU INT2
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// Connected to PIEIER2_1 (use MINT2 and MG21 masks):
|
||||
#if (G21PL != 0)
|
||||
interrupt void EPWM1_TZINT_ISR(void) // ePWM1 Trip Zone
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
|
||||
IER |= M_INT2;
|
||||
IER &= MINT2; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER2.all &= MG21; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER2.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER2_2 (use MINT2 and MG22 masks):
|
||||
#if (G22PL != 0)
|
||||
interrupt void EPWM2_TZINT_ISR(void) // ePWM2 Trip Zone
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
|
||||
IER |= M_INT2;
|
||||
IER &= MINT2; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER2.all &= MG22; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER2.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER2_3 (use MINT2 and MG23 masks):
|
||||
#if (G23PL != 0)
|
||||
interrupt void EPWM3_TZINT_ISR(void) // ePWM3 Trip Zone
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
|
||||
IER |= M_INT2;
|
||||
IER &= MINT2; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER2.all &= MG23; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER2.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER2_4 (use MINT2 and MG24 masks):
|
||||
#if (G24PL != 0)
|
||||
interrupt void EPWM4_TZINT_ISR(void) // ePWM4 Trip Zone
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
|
||||
IER |= M_INT2;
|
||||
IER &= MINT2; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER2.all &= MG24; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER2.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER2_5 (use MINT2 and MG25 masks):
|
||||
#if (G25PL != 0)
|
||||
interrupt void EPWM5_TZINT_ISR(void) // ePWM5 Trip Zone
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
|
||||
IER |= M_INT2;
|
||||
IER &= MINT2; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER2.all &= MG25; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER2.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER2_6 (use MINT2 and MG26 masks):
|
||||
#if (G26PL != 0)
|
||||
interrupt void EPWM6_TZINT_ISR(void) // ePWM6 Trip Zone
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
|
||||
IER |= M_INT2;
|
||||
IER &= MINT2; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER2.all &= MG26; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER2.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 3 - MUXed into CPU INT3
|
||||
// -----------------------------------------------------------
|
||||
|
||||
|
||||
// Connected to PIEIER3_1 (use MINT3 and MG31 masks):
|
||||
#if (G31PL != 0)
|
||||
interrupt void EPWM1_INT_ISR(void) // ePWM1 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
|
||||
IER |= M_INT3;
|
||||
IER &= MINT3; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER3.all &= MG31; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER3.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER3_2 (use MINT3 and MG32 masks):
|
||||
#if (G32PL != 0)
|
||||
interrupt void EPWM2_INT_ISR(void) // ePWM2 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
|
||||
IER |= M_INT3;
|
||||
IER &= MINT3; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER3.all &= MG32; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER3.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER3_3 (use MINT3 and MG33 masks):
|
||||
#if (G33PL != 0)
|
||||
interrupt void EPWM3_INT_ISR(void) // ePWM3 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
|
||||
IER |= M_INT3;
|
||||
IER &= MINT3; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER3.all &= MG33; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER3.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER3_4 (use MINT3 and MG34 masks):
|
||||
#if (G34PL != 0)
|
||||
interrupt void EPWM4_INT_ISR(void) // ePWM4 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
|
||||
IER |= M_INT3;
|
||||
IER &= MINT3; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER3.all &= MG34; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER3.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER3_5 (use MINT3 and MG35 masks):
|
||||
#if (G35PL != 0)
|
||||
interrupt void EPWM5_INT_ISR(void) // ePWM5 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
|
||||
IER |= M_INT3;
|
||||
IER &= MINT3; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER3.all &= MG35; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER3.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER3_6 (use MINT3 and MG36 masks):
|
||||
#if (G36PL != 0)
|
||||
interrupt void EPWM6_INT_ISR(void) // ePWM6 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
|
||||
IER |= M_INT3;
|
||||
IER &= MINT3; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER3.all &= MG36; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER3.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 4 - MUXed into CPU INT4
|
||||
// -----------------------------------------------------------
|
||||
|
||||
|
||||
// Connected to PIEIER4_1 (use MINT4 and MG41 masks):
|
||||
#if (G41PL != 0)
|
||||
interrupt void ECAP1_INT_ISR(void) // eCAP1 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
|
||||
IER |= M_INT4;
|
||||
IER &= MINT4; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER4.all &= MG41; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER4.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER4_2 (use MINT4 and MG42 masks):
|
||||
#if (G42PL != 0)
|
||||
interrupt void ECAP2_INT_ISR(void) // eCAP2 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all;
|
||||
IER |= M_INT4;
|
||||
IER &= MINT4; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER4.all &= MG42; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER4.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER4_3 (use MINT4 and MG43 masks):
|
||||
#if (G43PL != 0)
|
||||
interrupt void ECAP3_INT_ISR(void) // eCAP3 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
|
||||
IER |= M_INT4;
|
||||
IER &= MINT4; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER4.all &= MG43; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER4.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER4_4 (use MINT4 and MG44 masks):
|
||||
#if (G44PL != 0)
|
||||
interrupt void ECAP4_INT_ISR(void) // eCAP4 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
|
||||
IER |= M_INT4;
|
||||
IER &= MINT4; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER4.all &= MG44; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER4.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER4_5 (use MINT4 and MG45 masks):
|
||||
#if (G45PL != 0)
|
||||
interrupt void ECAP5_INT_ISR(void) // eCAP5 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
|
||||
IER |= M_INT4;
|
||||
IER &= MINT4; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER4.all &= MG45; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER4.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER4_6 (use MINT4 and MG46 masks):
|
||||
#if (G46PL != 0)
|
||||
interrupt void ECAP6_INT_ISR(void) // eCAP6 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
|
||||
IER |= M_INT4;
|
||||
IER &= MINT4; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER4.all &= MG46; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER4.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 5 - MUXed into CPU INT5
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// Connected to PIEIER5_1 (use MINT5 and MG51 masks):
|
||||
#if (G51PL != 0)
|
||||
interrupt void EQEP1_INT_ISR(void) // eQEP1 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all;
|
||||
IER |= M_INT5;
|
||||
IER &= MINT5; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER5.all &= MG51; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER5.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER5_2 (use MINT5 and MG52 masks):
|
||||
#if (G52PL != 0)
|
||||
interrupt void EQEP2_INT_ISR(void) // eQEP2 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all;
|
||||
IER |= M_INT5;
|
||||
IER &= MINT5; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER5.all &= MG52; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER5.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 6 - MUXed into CPU INT6
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// Connected to PIEIER6_1 (use MINT6 and MG61 masks):
|
||||
#if (G61PL != 0)
|
||||
interrupt void SPIRXINTA_ISR(void) // SPI-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
|
||||
IER |= M_INT6;
|
||||
IER &= MINT6; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER6.all &= MG61; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER6.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER6_2 (use MINT6 and MG62 masks):
|
||||
#if (G62PL != 0)
|
||||
interrupt void SPITXINTA_ISR(void) // SPI-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
|
||||
IER |= M_INT6;
|
||||
IER &= MINT6; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER6.all &= MG62; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER6.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER6_3 (use MINT6 and MG63 masks):
|
||||
#if (G63PL != 0)
|
||||
interrupt void MRINTB_ISR(void) // McBSP-B
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
|
||||
IER |= M_INT6;
|
||||
IER &= MINT6; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER6.all &= MG63; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER6.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER6_4 (use MINT6 and MG64 masks):
|
||||
#if (G64PL != 0)
|
||||
interrupt void MXINTB_ISR(void) // McBSP-B
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
|
||||
IER |= M_INT6;
|
||||
IER &= MINT6; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER6.all &= MG64; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER6.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
// Connected to PIEIER6_5 (use MINT6 and MG65 masks):
|
||||
#if (G65PL != 0)
|
||||
interrupt void MRINTA_ISR(void) // McBSP-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
|
||||
IER |= M_INT6;
|
||||
IER &= MINT6; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER6.all &= MG65; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER6.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER6_6 (use MINT6 and MG66 masks):
|
||||
#if (G66PL != 0)
|
||||
interrupt void MXINTA_ISR(void) // McBSP-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
|
||||
IER |= M_INT6;
|
||||
IER &= MINT6; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER6.all &= MG66; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER6.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 7 - MUXed into CPU INT7
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// Connected to PIEIER7_1 (use MINT7 and MG71 masks):
|
||||
#if (G71PL != 0)
|
||||
interrupt void DINTCH1_ISR(void) // DMA
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
|
||||
IER |= M_INT7;
|
||||
IER &= MINT7; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER7.all &= MG71; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER7.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER7_2 (use MINT7 and MG72 masks):
|
||||
#if (G72PL != 0)
|
||||
interrupt void DINTCH2_ISR(void) // DMA
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
|
||||
IER |= M_INT7;
|
||||
IER &= MINT7; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER7.all &= MG72; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER7.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER7_3 (use MINT7 and MG73 masks):
|
||||
#if (G73PL != 0)
|
||||
interrupt void DINTCH3_ISR(void) // DMA
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
|
||||
IER |= M_INT7;
|
||||
IER &= MINT7; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER7.all &= MG73; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER7.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER7_4 (use MINT7 and MG74 masks):
|
||||
#if (G74PL != 0)
|
||||
interrupt void DINTCH4_ISR(void) // DMA
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
|
||||
IER |= M_INT7;
|
||||
IER &= MINT7; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER7.all &= MG74; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER7.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
// Connected to PIEIER7_5 (use MINT7 and MG75 masks):
|
||||
#if (G75PL != 0)
|
||||
interrupt void DINTCH5_ISR(void) // DMA
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
|
||||
IER |= M_INT7;
|
||||
IER &= MINT7; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER7.all &= MG75; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER7.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER7_6 (use MINT7 and MG76 masks):
|
||||
#if (G76PL != 0)
|
||||
interrupt void DINTCH6_ISR(void) // DMA
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
|
||||
IER |= M_INT7;
|
||||
IER &= MINT7; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER7.all &= MG76; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER7.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 8 - MUXed into CPU INT8
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// Connected to PIEIER8_1 (use MINT8 and MG81 masks):
|
||||
#if (G81PL != 0)
|
||||
interrupt void I2CINT1A_ISR(void) // I2C-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all;
|
||||
IER |= M_INT8;
|
||||
IER &= MINT8; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER6.all &= MG81; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER8.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER8_2 (use MINT8 and MG82 masks):
|
||||
#if (G82PL != 0)
|
||||
interrupt void I2CINT2A_ISR(void) // I2C-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all;
|
||||
IER |= M_INT8;
|
||||
IER &= MINT8; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER8.all &= MG82; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER8.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER8_5 (use MINT8 and MG85 masks):
|
||||
#if (G85PL != 0)
|
||||
interrupt void SCIRXINTC_ISR(void) // SCI-C
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all;
|
||||
IER |= M_INT8;
|
||||
IER &= MINT8; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER6.all &= MG85; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER8.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER8_6 (use MINT8 and MG86 masks):
|
||||
#if (G82PL != 0)
|
||||
interrupt void SCITXINTC_ISR(void) // SCI-C
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all;
|
||||
IER |= M_INT8;
|
||||
IER &= MINT8; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER8.all &= MG86; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER8.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 9 - MUXed into CPU INT9
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// Connected to PIEIER9_1 (use MINT9 and MG91 masks):
|
||||
#if (G91PL != 0)
|
||||
interrupt void SCIRXINTA_ISR(void) // SCI-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG91; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER9_2 (use MINT9 and MG92 masks):
|
||||
#if (G92PL != 0)
|
||||
interrupt void SCITXINTA_ISR(void) // SCI-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG92; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
// Connected to PIEIER9_3 (use MINT9 and MG93 masks):
|
||||
#if (G93PL != 0)
|
||||
interrupt void SCIRXINTB_ISR(void) // SCI-B
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG93; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER9_4 (use MINT9 and MG94 masks):
|
||||
#if (G94PL != 0)
|
||||
interrupt void SCITXINTB_ISR(void) // SCI-B
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG94; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER9_5 (use MINT9 and MG95 masks):
|
||||
#if (G95PL != 0)
|
||||
interrupt void ECAN0INTA_ISR(void) // eCAN-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG95; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER9_6 (use MINT9 and MG96 masks):
|
||||
#if (G96PL != 0)
|
||||
interrupt void ECAN1INTA_ISR(void) // eCAN-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG96; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER9_7 (use MINT9 and MG97 masks):
|
||||
#if (G97PL != 0)
|
||||
interrupt void ECAN0INTB_ISR(void) // eCAN-B
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG97; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER9_8 (use MINT9 and MG98 masks):
|
||||
#if (G98PL != 0)
|
||||
interrupt void ECAN1INTB_ISR(void) // eCAN-B
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG98; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 10 - MUXed into CPU INT10
|
||||
// -----------------------------------------------------------
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 11 - MUXed into CPU INT11
|
||||
// -----------------------------------------------------------
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 12 - MUXed into CPU INT12
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// Connected to PIEIER9_1 (use MINT12 and MG121 masks):
|
||||
#if (G121PL != 0)
|
||||
interrupt void XINT3_ISR(void)
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
|
||||
IER |= M_INT12;
|
||||
IER &= MINT12; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER12.all &= MG121; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER12.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER12_2 (use MINT12 and MG122 masks):
|
||||
#if (G122PL != 0)
|
||||
interrupt void XINT4_ISR(void)
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
|
||||
IER |= M_INT12;
|
||||
IER &= MINT12; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER12.all &= MG122; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER12.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
// Connected to PIEIER12_3 (use MINT12 and MG123 masks):
|
||||
#if (G123PL != 0)
|
||||
interrupt void XINT5_ISR(void) // SCI-B
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
|
||||
IER |= M_INT12;
|
||||
IER &= MINT12; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER12.all &= MG123; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER12.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER12_4 (use MINT12 and MG124 masks):
|
||||
#if (G124PL != 0)
|
||||
interrupt void XINT6_ISR(void) // SCI-B
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
|
||||
IER |= M_INT12;
|
||||
IER &= MINT12; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER12.all &= MG124; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER12.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER12_5 (use MINT12 and MG125 masks):
|
||||
#if (G125PL != 0)
|
||||
interrupt void XINT7_ISR(void) // eCAN-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
|
||||
IER |= M_INT12;
|
||||
IER &= MINT12; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER12.all &= MG125; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER12.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER12_7 (use MINT12 and MG127 masks):
|
||||
#if (G127PL != 0)
|
||||
interrupt void LVF_ISR(void) // FPU
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
|
||||
IER |= M_INT12;
|
||||
IER &= MINT12; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER12.all &= MG127; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER12.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER12_8 (use MINT12 and MG128 masks):
|
||||
#if (G128PL != 0)
|
||||
interrupt void LUF_ISR(void) // FPU
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
|
||||
IER |= M_INT12;
|
||||
IER &= MINT12; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER12.all &= MG128; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER12.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Catch All Default ISRs:
|
||||
//
|
||||
|
||||
interrupt void PIE_RESERVED(void) // Reserved space. For test.
|
||||
{
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void INT_NOTUSED_ISR(void) // Reserved space. For test.
|
||||
{
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void rsvd_ISR(void) // For test
|
||||
{
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
// No more.
|
||||
//===========================================================================
|
||||
511
v120/DSP2833x_common/source/DSP2833x_SWPrioritizedPieVect.c
Normal file
511
v120/DSP2833x_common/source/DSP2833x_SWPrioritizedPieVect.c
Normal file
@@ -0,0 +1,511 @@
|
||||
// TI File $Revision: /main/2 $
|
||||
// Checkin $Date: April 4, 2007 14:25:31 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_SWPiroritizedPieVect.c
|
||||
//
|
||||
// TITLE: DSP2833x Devices SW Prioritized PIE Vector Table Initialization.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// Original Source by A.T.
|
||||
//
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
#include "DSP2833x_SWPrioritizedIsrLevels.h"
|
||||
|
||||
const struct PIE_VECT_TABLE PieVectTableInit = {
|
||||
|
||||
PIE_RESERVED, // Reserved space
|
||||
PIE_RESERVED, // reserved
|
||||
PIE_RESERVED, // reserved
|
||||
PIE_RESERVED, // reserved
|
||||
PIE_RESERVED, // reserved
|
||||
PIE_RESERVED, // reserved
|
||||
PIE_RESERVED, // reserved
|
||||
PIE_RESERVED, // reserved
|
||||
PIE_RESERVED, // reserved
|
||||
PIE_RESERVED, // reserved
|
||||
PIE_RESERVED, // reserved
|
||||
PIE_RESERVED, // reserved
|
||||
PIE_RESERVED, // reserved
|
||||
|
||||
// Non-Peripheral Interrupts:
|
||||
#if (INT13PL != 0)
|
||||
INT13_ISR, // XINT13
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (INT14PL != 0)
|
||||
INT14_ISR, // CPU-Timer2
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (INT15PL != 0)
|
||||
DATALOG_ISR, // Datalogging interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (INT16PL != 0)
|
||||
RTOSINT_ISR, // RTOS interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
rsvd_ISR, // reserved interrupt
|
||||
NMI_ISR, // Non-maskable interrupt
|
||||
ILLEGAL_ISR, // Illegal operation TRAP
|
||||
USER1_ISR, // User Defined trap 1
|
||||
USER2_ISR, // User Defined trap 2
|
||||
USER3_ISR, // User Defined trap 3
|
||||
USER4_ISR, // User Defined trap 4
|
||||
USER5_ISR, // User Defined trap 5
|
||||
USER6_ISR, // User Defined trap 6
|
||||
USER7_ISR, // User Defined trap 7
|
||||
USER8_ISR, // User Defined trap 8
|
||||
USER9_ISR, // User Defined trap 9
|
||||
USER10_ISR, // User Defined trap 10
|
||||
USER11_ISR, // User Defined trap 11
|
||||
USER12_ISR, // User Defined trap 12
|
||||
|
||||
// Group 1 PIE Vectors:
|
||||
#if (G11PL != 0)
|
||||
SEQ1INT_ISR, // ADC
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G12PL != 0)
|
||||
SEQ2INT_ISR, // ADC
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
rsvd_ISR,
|
||||
|
||||
#if (G14PL != 0)
|
||||
XINT1_ISR, // External
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G15PL != 0)
|
||||
XINT2_ISR, // External
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G16PL != 0)
|
||||
ADCINT_ISR, // ADC
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G17PL != 0)
|
||||
TINT0_ISR, // Timer 0
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G18PL != 0)
|
||||
WAKEINT_ISR, // WD & Low Power
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
// Group 2 PIE Vectors:
|
||||
#if (G21PL != 0)
|
||||
EPWM1_TZINT_ISR, // ePWM1 Trip Zone
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G22PL != 0)
|
||||
EPWM2_TZINT_ISR, // ePWM2 Trip Zone
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G23PL != 0)
|
||||
EPWM3_TZINT_ISR, // ePWM3 Trip Zone
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G24PL != 0)
|
||||
EPWM4_TZINT_ISR, // ePWM4 Trip Zone
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G25PL != 0)
|
||||
EPWM5_TZINT_ISR, // ePWM5 Trip Zone
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G26PL != 0)
|
||||
EPWM6_TZINT_ISR, // ePWM6 Trip Zone
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
|
||||
// Group 3 PIE Vectors:
|
||||
#if (G31PL != 0)
|
||||
EPWM1_INT_ISR, // ePWM1 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G32PL != 0)
|
||||
EPWM2_INT_ISR, // ePWM2 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G33PL != 0)
|
||||
EPWM3_INT_ISR, // ePWM3 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G34PL != 0)
|
||||
EPWM4_INT_ISR, // ePWM4 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G35PL != 0)
|
||||
EPWM5_INT_ISR, // ePWM5 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G36PL != 0)
|
||||
EPWM6_INT_ISR, // ePWM6 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
|
||||
// Group 4 PIE Vectors:
|
||||
#if (G41PL != 0)
|
||||
ECAP1_INT_ISR, // eCAP1 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G42PL != 0)
|
||||
ECAP2_INT_ISR, // eCAP2 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G43PL != 0)
|
||||
ECAP3_INT_ISR, // eCAP3 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G44PL != 0)
|
||||
ECAP4_INT_ISR, // eCAP4 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G45PL != 0)
|
||||
ECAP5_INT_ISR, // eCAP5 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G46PL != 0)
|
||||
ECAP6_INT_ISR, // eCAP6 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
|
||||
// Group 5 PIE Vectors:
|
||||
#if (G51PL != 0)
|
||||
EQEP1_INT_ISR, // eQEP1 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G52PL != 0)
|
||||
EQEP2_INT_ISR, // eQEP2 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
|
||||
// Group 6 PIE Vectors:
|
||||
#if (G61PL != 0)
|
||||
SPIRXINTA_ISR, // SPI-A
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G62PL != 0)
|
||||
SPITXINTA_ISR, // SPI-A
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G63PL != 0)
|
||||
MRINTB_ISR, // McBSP-B
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G64PL != 0)
|
||||
MXINTB_ISR, // McBSP-B
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G65PL != 0)
|
||||
MRINTA_ISR, // McBSP-A
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G66PL != 0)
|
||||
MXINTA_ISR, // McBSP-A
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
|
||||
// Group 7 PIE Vectors:
|
||||
#if (G71PL != 0)
|
||||
DINTCH1_ISR, // DMA-Channel 1 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G72PL != 0)
|
||||
DINTCH2_ISR, // DMA-Channel 2 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G73PL != 0)
|
||||
DINTCH3_ISR, // DMA-Channel 3 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G74PL != 0)
|
||||
DINTCH4_ISR, // DMA-Channel 4 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G75PL != 0)
|
||||
DINTCH5_ISR, // DMA-Channel 5 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G76PL != 0)
|
||||
DINTCH6_ISR, // DMA-Channel 6 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
|
||||
// Group 8 PIE Vectors:
|
||||
#if (G81PL != 0)
|
||||
I2CINT1A_ISR, // I2C-A
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G82PL != 0)
|
||||
I2CINT2A_ISR, // I2C-A
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
|
||||
#if (G85PL != 0)
|
||||
SCIRXINTC_ISR, // SCI-C
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G86PL != 0)
|
||||
SCITXINTC_ISR, // SCI-C
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
|
||||
// Group 9 PIE Vectors:
|
||||
#if (G91PL != 0)
|
||||
SCIRXINTA_ISR, // SCI-A
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G92PL != 0)
|
||||
SCITXINTA_ISR, // SCI-A
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G93PL != 0)
|
||||
SCIRXINTB_ISR, // SCI-B
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G94PL != 0)
|
||||
SCITXINTB_ISR, // SCI-B
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G95PL != 0)
|
||||
ECAN0INTA_ISR, // eCAN-A
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G96PL != 0)
|
||||
ECAN1INTA_ISR, // eCAN-A
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G97PL != 0)
|
||||
ECAN0INTB_ISR, // eCAN-B
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G98PL != 0)
|
||||
ECAN1INTB_ISR, // eCAN-B
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
// Group 10 PIE Vectors
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
|
||||
// Group 11 PIE Vectors
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
|
||||
// Group 12 PIE Vectors
|
||||
#if (G121PL != 0)
|
||||
XINT3_ISR, // External interrupt 3
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G122PL != 0)
|
||||
XINT4_ISR, // External interrupt 4
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G123PL != 0)
|
||||
XINT5_ISR, // External interrupt 5
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G124PL != 0)
|
||||
XINT6_ISR, // External interrupt 6
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G125PL != 0)
|
||||
XINT7_ISR, // External interrupt 7
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
rsvd_ISR,
|
||||
|
||||
#if (G127PL != 0)
|
||||
LVF_ISR, // Latched overflow flag
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G128PL != 0)
|
||||
LUF_ISR, // Latched underflow flag
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// InitPieVectTable:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes the PIE vector table to a known state.
|
||||
// This function must be executed after boot time.
|
||||
//
|
||||
|
||||
void InitPieVectTable(void)
|
||||
{
|
||||
int16 i;
|
||||
Uint32 *Source = (void *) &PieVectTableInit;
|
||||
Uint32 *Dest = (void *) &PieVectTable;
|
||||
|
||||
EALLOW;
|
||||
for(i=0; i < 128; i++) {
|
||||
*Dest++ = *Source++;
|
||||
}
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
// No more.
|
||||
//===========================================================================
|
||||
415
v120/DSP2833x_common/source/DSP2833x_SysCtrl.c
Normal file
415
v120/DSP2833x_common/source/DSP2833x_SysCtrl.c
Normal file
@@ -0,0 +1,415 @@
|
||||
// TI File $Revision: /main/7 $
|
||||
// Checkin $Date: September 20, 2007 13:30:31 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_SysCtrl.c
|
||||
//
|
||||
// TITLE: DSP2833x Device System Control Initialization & Support Functions.
|
||||
//
|
||||
// DESCRIPTION:
|
||||
//
|
||||
// Example initialization of system resources.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
|
||||
#include "DSP2833x_Device.h" // Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // Examples Include File
|
||||
|
||||
//#include "RS485.h"
|
||||
//#include "message.h"
|
||||
|
||||
// Functions that will be run from RAM need to be assigned to
|
||||
// a different section. This section will then be mapped to a load and
|
||||
// run address using the linker cmd file.
|
||||
|
||||
#pragma CODE_SECTION(InitFlash, "ramfuncs");
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// InitSysCtrl:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes the System Control registers to a known state.
|
||||
// - Disables the watchdog
|
||||
// - Set the PLLCR for proper SYSCLKOUT frequency
|
||||
// - Set the pre-scaler for the high and low frequency peripheral clocks
|
||||
// - Enable the clocks to the peripherals
|
||||
|
||||
long SYSCLKOUT, LSPCLK, HSPCLK;
|
||||
|
||||
void InitSysCtrl(void)
|
||||
{
|
||||
|
||||
// Disable the watchdog
|
||||
DisableDog();
|
||||
|
||||
// Initialize the PLL control: PLLCR and DIVSEL
|
||||
// DSP28_PLLCR and DSP28_DIVSEL are defined in DSP2833x_Examples.h
|
||||
InitPll(DSP28_PLLCR,DSP28_DIVSEL);
|
||||
|
||||
// Initialize the peripheral clocks
|
||||
InitPeripheralClocks();
|
||||
}
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Example: InitFlash:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes the Flash Control registers
|
||||
|
||||
// CAUTION
|
||||
// This function MUST be executed out of RAM. Executing it
|
||||
// out of OTP/Flash will yield unpredictable results
|
||||
|
||||
void InitFlash(void)
|
||||
{
|
||||
EALLOW;
|
||||
//Enable Flash Pipeline mode to improve performance
|
||||
//of code executed from Flash.
|
||||
FlashRegs.FOPT.bit.ENPIPE = 1;
|
||||
|
||||
// CAUTION
|
||||
//Minimum waitstates required for the flash operating
|
||||
//at a given CPU rate must be characterized by TI.
|
||||
//Refer to the datasheet for the latest information.
|
||||
#if CPU_FRQ_150MHZ
|
||||
//Set the Paged Waitstate for the Flash
|
||||
FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5;
|
||||
|
||||
//Set the Random Waitstate for the Flash
|
||||
FlashRegs.FBANKWAIT.bit.RANDWAIT = 5;
|
||||
|
||||
//Set the Waitstate for the OTP
|
||||
FlashRegs.FOTPWAIT.bit.OTPWAIT = 8;
|
||||
#endif
|
||||
|
||||
#if CPU_FRQ_100MHZ
|
||||
//Set the Paged Waitstate for the Flash
|
||||
FlashRegs.FBANKWAIT.bit.PAGEWAIT = 3;
|
||||
|
||||
//Set the Random Waitstate for the Flash
|
||||
FlashRegs.FBANKWAIT.bit.RANDWAIT = 3;
|
||||
|
||||
//Set the Waitstate for the OTP
|
||||
FlashRegs.FOTPWAIT.bit.OTPWAIT = 5;
|
||||
#endif
|
||||
// CAUTION
|
||||
//ONLY THE DEFAULT VALUE FOR THESE 2 REGISTERS SHOULD BE USED
|
||||
FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF;
|
||||
FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF;
|
||||
EDIS;
|
||||
|
||||
//Force a pipeline flush to ensure that the write to
|
||||
//the last register configured occurs before returning.
|
||||
|
||||
asm(" RPT #7 || NOP");
|
||||
}
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Example: ServiceDog:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function resets the watchdog timer.
|
||||
// Enable this function for using ServiceDog in the application
|
||||
|
||||
void ServiceDog(void)
|
||||
{
|
||||
if(SysCtrlRegs.PLLCR.bit.DIV == DSP28_PLLCR)
|
||||
if(SysCtrlRegs.PLLSTS.bit.DIVSEL == DSP28_DIVSEL)
|
||||
{
|
||||
EALLOW;
|
||||
SysCtrlRegs.WDKEY = 0x0055;
|
||||
SysCtrlRegs.WDKEY = 0x00AA;
|
||||
EDIS;
|
||||
return;
|
||||
} }
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Example: DisableDog:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function disables the watchdog timer.
|
||||
|
||||
void DisableDog(void)
|
||||
{
|
||||
EALLOW;
|
||||
SysCtrlRegs.WDCR= 0x0068;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Example: InitPll:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes the PLLCR register.
|
||||
|
||||
void InitPll(Uint16 divval, Uint16 divsel)
|
||||
{
|
||||
long clkVal;
|
||||
|
||||
// Make sure the PLL is not running in limp mode
|
||||
if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0)
|
||||
{
|
||||
// Missing external clock has been detected
|
||||
// Replace this line with a call to an appropriate
|
||||
// SystemShutdown(); function.
|
||||
asm(" ESTOP0");
|
||||
}
|
||||
|
||||
// DIVSEL MUST be 0 before PLLCR can be changed from
|
||||
// 0x0000. It is set to 0 by an external reset XRSn
|
||||
// This puts us in 1/4
|
||||
if (SysCtrlRegs.PLLSTS.bit.DIVSEL != 0)
|
||||
{
|
||||
EALLOW;
|
||||
SysCtrlRegs.PLLSTS.bit.DIVSEL = 0;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
// Change the PLLCR
|
||||
// if (SysCtrlRegs.PLLCR.bit.DIV != val)
|
||||
{
|
||||
|
||||
EALLOW;
|
||||
// Before setting PLLCR turn off missing clock detect logic
|
||||
SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1;
|
||||
SysCtrlRegs.PLLCR.bit.DIV = divval;
|
||||
EDIS;
|
||||
|
||||
clkVal = (divval)?divval:1;
|
||||
clkVal = XCLKIN * clkVal;
|
||||
|
||||
// Optional: Wait for PLL to lock.
|
||||
// During this time the CPU will switch to OSCCLK/2 until
|
||||
// the PLL is stable. Once the PLL is stable the CPU will
|
||||
// switch to the new PLL value.
|
||||
//
|
||||
// This time-to-lock is monitored by a PLL lock counter.
|
||||
//
|
||||
// Code is not required to sit and wait for the PLL to lock.
|
||||
// However, if the code does anything that is timing critical,
|
||||
// and requires the correct clock be locked, then it is best to
|
||||
// wait until this switching has completed.
|
||||
|
||||
// Wait for the PLL lock bit to be set.
|
||||
|
||||
// The watchdog should be disabled before this loop, or fed within
|
||||
// the loop via ServiceDog().
|
||||
|
||||
// Uncomment to disable the watchdog
|
||||
DisableDog();
|
||||
|
||||
while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1)
|
||||
{
|
||||
// Uncomment to service the watchdog
|
||||
// ServiceDog();
|
||||
}
|
||||
|
||||
EALLOW;
|
||||
SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
// If switching to 1/2
|
||||
if((divsel == 1)||(divsel == 2))
|
||||
{
|
||||
EALLOW;
|
||||
SysCtrlRegs.PLLSTS.bit.DIVSEL = divsel;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
if(divsel == 0) clkVal /= 4;
|
||||
if(divsel == 1) clkVal /= 4;
|
||||
if(divsel == 2) clkVal /= 2;
|
||||
|
||||
// If switching to 1/1
|
||||
// * First go to 1/2 and let the power settle
|
||||
// The time required will depend on the system, this is only an example
|
||||
// * Then switch to 1/1
|
||||
|
||||
if((divval == 0) && (divsel == 3))
|
||||
{
|
||||
EALLOW;
|
||||
SysCtrlRegs.PLLSTS.bit.DIVSEL = 2;
|
||||
DELAY_US(50L);
|
||||
// pause_us(50L);
|
||||
SysCtrlRegs.PLLSTS.bit.DIVSEL = 3;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
SYSCLKOUT = clkVal;
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------------
|
||||
// Example: InitPeripheralClocks:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes the clocks to the peripheral modules.
|
||||
// First the high and low clock prescalers are set
|
||||
// Second the clocks are enabled to each peripheral.
|
||||
// To reduce power, leave clocks to unused peripherals disabled
|
||||
//
|
||||
// Note: If a peripherals clock is not enabled then you cannot
|
||||
// read or write to the registers for that peripheral
|
||||
|
||||
void InitPeripheralClocks(void)
|
||||
{
|
||||
long Val;
|
||||
|
||||
EALLOW;
|
||||
|
||||
// HISPCP/LOSPCP prescale register settings, normally it will be set to default values
|
||||
|
||||
#if CLKMULT == 0
|
||||
SysCtrlRegs.HISPCP.all = 0x0000;
|
||||
#endif
|
||||
#if CLKMULT == 1
|
||||
SysCtrlRegs.HISPCP.all = 0x0000;
|
||||
#endif
|
||||
#if CLKMULT == 2
|
||||
SysCtrlRegs.HISPCP.all = 0x0001;
|
||||
#endif
|
||||
#if CLKMULT == 3
|
||||
SysCtrlRegs.HISPCP.all = 0x0002;
|
||||
#endif
|
||||
#if CLKMULT == 4
|
||||
SysCtrlRegs.HISPCP.all = 0x0002;
|
||||
#endif
|
||||
#if CLKMULT == 5
|
||||
SysCtrlRegs.HISPCP.all = 0x0003;
|
||||
#endif
|
||||
|
||||
SysCtrlRegs.LOSPCP.all = 0x0000;
|
||||
|
||||
Val = (SysCtrlRegs.HISPCP.all)?
|
||||
SysCtrlRegs.HISPCP.all*2 : 1;
|
||||
Val = SYSCLKOUT / Val;
|
||||
|
||||
HSPCLK = Val;
|
||||
|
||||
Val = (SysCtrlRegs.LOSPCP.all)?
|
||||
SysCtrlRegs.LOSPCP.all*2 : 1;
|
||||
Val = SYSCLKOUT / Val;
|
||||
LSPCLK = Val;
|
||||
|
||||
// XCLKOUT to SYSCLKOUT ratio. By default XCLKOUT = 1/4 SYSCLKOUT
|
||||
// XTIMCLK = SYSCLKOUT/2
|
||||
XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
|
||||
// XCLKOUT = XTIMCLK/2
|
||||
XintfRegs.XINTCNF2.bit.CLKMODE = 1;
|
||||
// Enable XCLKOUT
|
||||
XintfRegs.XINTCNF2.bit.CLKOFF = 0;
|
||||
|
||||
// Peripheral clock enables set for the selected peripherals.
|
||||
// If you are not using a peripheral leave the clock off
|
||||
// to save on power.
|
||||
//
|
||||
// Note: not all peripherals are available on all 2833x derivates.
|
||||
// Refer to the datasheet for your particular device.
|
||||
//
|
||||
// This function is not written to be an example of efficient code.
|
||||
|
||||
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // ADC
|
||||
|
||||
// *IMPORTANT*
|
||||
// The ADC_cal function, which copies the ADC calibration values from TI reserved
|
||||
// OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs automatically in the
|
||||
// Boot ROM. If the boot ROM code is bypassed during the debug process, the
|
||||
// following function MUST be called for the ADC to function according
|
||||
// to specification. The clocks to the ADC MUST be enabled before calling this
|
||||
// function.
|
||||
// See the device data manual and/or the ADC Reference
|
||||
// Manual for more information.
|
||||
|
||||
ADC_cal();
|
||||
|
||||
|
||||
SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 1; // I2C
|
||||
SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 1; // SCI-A
|
||||
SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 1; // SCI-B
|
||||
SysCtrlRegs.PCLKCR0.bit.SCICENCLK = 1; // SCI-C
|
||||
SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 1; // SPI-A
|
||||
SysCtrlRegs.PCLKCR0.bit.MCBSPAENCLK = 1; // McBSP-A
|
||||
SysCtrlRegs.PCLKCR0.bit.MCBSPBENCLK = 1; // McBSP-B
|
||||
SysCtrlRegs.PCLKCR0.bit.ECANAENCLK=1; // eCAN-A
|
||||
SysCtrlRegs.PCLKCR0.bit.ECANBENCLK=1; // eCAN-B
|
||||
|
||||
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the ePWM
|
||||
SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1; // ePWM1
|
||||
SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1; // ePWM2
|
||||
SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1; // ePWM3
|
||||
SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1; // ePWM4
|
||||
SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1; // ePWM5
|
||||
SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 1; // ePWM6
|
||||
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the ePWM
|
||||
|
||||
SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 1; // eCAP3
|
||||
SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 1; // eCAP4
|
||||
SysCtrlRegs.PCLKCR1.bit.ECAP5ENCLK = 1; // eCAP5
|
||||
SysCtrlRegs.PCLKCR1.bit.ECAP6ENCLK = 1; // eCAP6
|
||||
SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 1; // eCAP1
|
||||
SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 1; // eCAP2
|
||||
SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 1; // eQEP1
|
||||
SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 1; // eQEP2
|
||||
|
||||
SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 1; // CPU Timer 0
|
||||
SysCtrlRegs.PCLKCR3.bit.CPUTIMER1ENCLK = 1; // CPU Timer 1
|
||||
SysCtrlRegs.PCLKCR3.bit.CPUTIMER2ENCLK = 1; // CPU Timer 2
|
||||
|
||||
SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1; // DMA Clock
|
||||
SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; // XTIMCLK
|
||||
SysCtrlRegs.PCLKCR3.bit.GPIOINENCLK = 1; // GPIO input clock
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Example: CsmUnlock:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function unlocks the CSM. User must replace 0xFFFF's with current
|
||||
// password for the DSP. Returns 1 if unlock is successful.
|
||||
|
||||
#define STATUS_FAIL 0
|
||||
#define STATUS_SUCCESS 1
|
||||
|
||||
Uint16 CsmUnlock()
|
||||
{
|
||||
volatile Uint16 temp;
|
||||
|
||||
// Load the key registers with the current password. The 0xFFFF's are dummy
|
||||
// passwords. User should replace them with the correct password for the DSP.
|
||||
|
||||
EALLOW;
|
||||
CsmRegs.KEY0 = 0xFFFF;
|
||||
CsmRegs.KEY1 = 0xFFFF;
|
||||
CsmRegs.KEY2 = 0xFFFF;
|
||||
CsmRegs.KEY3 = 0xFFFF;
|
||||
CsmRegs.KEY4 = 0xFFFF;
|
||||
CsmRegs.KEY5 = 0xFFFF;
|
||||
CsmRegs.KEY6 = 0xFFFF;
|
||||
CsmRegs.KEY7 = 0xFFFF;
|
||||
EDIS;
|
||||
|
||||
// Perform a dummy read of the password locations
|
||||
// if they match the key values, the CSM will unlock
|
||||
|
||||
temp = CsmPwl.PSWD0;
|
||||
temp = CsmPwl.PSWD1;
|
||||
temp = CsmPwl.PSWD2;
|
||||
temp = CsmPwl.PSWD3;
|
||||
temp = CsmPwl.PSWD4;
|
||||
temp = CsmPwl.PSWD5;
|
||||
temp = CsmPwl.PSWD6;
|
||||
temp = CsmPwl.PSWD7;
|
||||
|
||||
// If the CSM unlocked, return succes, otherwise return
|
||||
// failure.
|
||||
if (CsmRegs.CSMSCR.bit.SECURE == 0) return STATUS_SUCCESS;
|
||||
else return STATUS_FAIL;
|
||||
|
||||
}
|
||||
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user