diff --git a/F28335.cmd b/F28335.cmd
new file mode 100644
index 0000000..fffa02b
--- /dev/null
+++ b/F28335.cmd
@@ -0,0 +1,206 @@
+/*
+// TI File $Revision: /main/10 $
+// Checkin $Date: July 9, 2008 13:43:56 $
+//###########################################################################
+//
+// FILE: F28335.cmd
+//
+// TITLE: Linker Command File For F28335 Device
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+*/
+
+/* ======================================================
+// For Code Composer Studio V2.2 and later
+// ---------------------------------------
+// In addition to this memory linker command file,
+// add the header linker command file directly to the project.
+// The header linker command file is required to link the
+// peripheral structures to the proper locations within
+// the memory map.
+//
+// The header linker files are found in \DSP2833x_Headers\cmd
+//
+// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
+// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
+========================================================= */
+
+/* ======================================================
+// For Code Composer Studio prior to V2.2
+// --------------------------------------
+// 1) Use one of the following -l statements to include the
+// header linker command file in the project. The header linker
+// file is required to link the peripheral structures to the proper
+// locations within the memory map */
+
+/* Uncomment this line to include file only for non-BIOS applications */
+/* -l DSP2833x_Headers_nonBIOS.cmd */
+
+/* Uncomment this line to include file only for BIOS applications */
+/* -l DSP2833x_Headers_BIOS.cmd */
+
+/* 2) In your project add the path to \DSP2833x_headers\cmd to the
+ library search path under project->build options, linker tab,
+ library search path (-i).
+/*========================================================= */
+
+/* Define the memory block start/length for the F28335
+ PAGE 0 will be used to organize program sections
+ PAGE 1 will be used to organize data sections
+
+ Notes:
+ Memory blocks on F28335 are uniform (ie same
+ physical memory) in both PAGE 0 and PAGE 1.
+ That is the same memory region should not be
+ defined for both PAGE 0 and PAGE 1.
+ Doing so will result in corruption of program
+ and/or data.
+
+ L0/L1/L2 and L3 memory blocks are mirrored - that is
+ they can be accessed in high memory or low memory.
+ For simplicity only one instance is used in this
+ linker file.
+
+ Contiguous SARAM memory blocks can be combined
+ if required to create a larger memory block.
+ */
+
+
+MEMORY
+{
+PAGE 0: /* Program Memory */
+ /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
+
+ ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */
+ RAML0 : origin = 0x008000, length = 0x004000 /* on-chip RAM block L0 */
+/* RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */
+/* RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */
+// RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */
+ RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */
+
+ ZONE6 : origin = 0x0100000, length = 0x100000 /* XINTF zone 6 */
+ FLASHH : origin = 0x300000, length = 0x008000 /* on-chip FLASH */
+ FLASHG : origin = 0x308000, length = 0x008000 /* on-chip FLASH */
+ FLASHF : origin = 0x310000, length = 0x008000 /* on-chip FLASH */
+ FLASHE : origin = 0x318000, length = 0x008000 /* on-chip FLASH */
+ FLASHD : origin = 0x320000, length = 0x008000 /* on-chip FLASH */
+ FLASHC : origin = 0x328000, length = 0x008000 /* on-chip FLASH */
+ FLASHA : origin = 0x338000, length = 0x007F80 /* on-chip FLASH */
+ CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
+ BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
+ CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
+ OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */
+ ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */
+
+ IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */
+ IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */
+ FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */
+ ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */
+ RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
+ VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
+
+PAGE 1 : /* Data Memory */
+ /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
+ /* Registers remain on PAGE1 */
+
+ BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
+ RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
+ RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
+ RAML5 : origin = 0x00D000, length = 0x003000 /* on-chip RAM block L1 */
+/* RAML6 : origin = 0x00E000, length = 0x001000 /* on-chip RAM block L1 */
+/* RAML7 : origin = 0x00F000, length = 0x001000 /* on-chip RAM block L1 */
+ ZONE7A : origin = 0x0200000, length = 0x00FC00 /* XINTF zone 7 - program space */
+ ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
+ FLASHB : origin = 0x330000, length = 0x008000 /* on-chip FLASH */
+}
+
+/* Allocate sections to memory blocks.
+ Note:
+ codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
+ execution when booting to flash
+ ramfuncs user defined section to store functions that will be copied from Flash into RAM
+*/
+
+SECTIONS
+{
+
+ /* Allocate program areas: */
+ .cinit : > RAML0 PAGE = 0
+ .pinit : > RAML0 PAGE = 0
+ .text : > RAML0 PAGE = 0
+ codestart : > BEGIN PAGE = 0
+ ramfuncs : LOAD = RAML4,
+ RUN = RAML4,
+ LOAD_START(_RamfuncsLoadStart),
+ LOAD_END(_RamfuncsLoadEnd),
+ RUN_START(_RamfuncsRunStart),
+ PAGE = 0
+
+ csmpasswds : > CSM_PWL PAGE = 0
+ csm_rsvd : > CSM_RSVD PAGE = 0
+
+ /* Allocate uninitalized data sections: */
+ .stack : > RAMM1 PAGE = 1
+ .ebss : > RAML5 PAGE = 1
+ .esysmem : > RAML0 PAGE = 0
+
+ .logg : > ZONE7A PAGE = 1
+
+ /* Initalized sections go in Flash */
+ /* For SDFlash to program these, they must be allocated to page 0 */
+ .econst : > RAML4 PAGE = 0
+ .switch : > RAML4 PAGE = 0
+
+ /* Allocate IQ math areas: */
+ IQmath : > FLASHC PAGE = 0 /* Math Code */
+ IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
+
+ /* Uncomment the section below if calling the IQNexp() or IQexp()
+ functions from the IQMath.lib library in order to utilize the
+ relevant IQ Math table in Boot ROM (This saves space and Boot ROM
+ is 1 wait-state). If this section is not uncommented, IQmathTables2
+ will be loaded into other memory (SARAM, Flash, etc.) and will take
+ up space, but 0 wait-state is possible.
+ */
+ /*
+ IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
+ {
+
+ IQmath.lib (IQmathTablesRam)
+
+ }
+ */
+
+ FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
+
+ /* Allocate DMA-accessible RAM sections: * /
+ DMARAML4 : > RAML4, PAGE = 1
+ DMARAML5 : > RAML5, PAGE = 1
+/* DMARAML6 : > RAML6, PAGE = 1
+ DMARAML7 : > RAML7, PAGE = 1
+*/
+ /* Allocate 0x400 of XINTF Zone 7 to storing data */
+ ZONE7DATA : > ZONE7B, PAGE = 1
+
+ /* .reset is a standard section used by the compiler. It contains the */
+ /* the address of the start of _c_int00 for C Code. /*
+ /* When using the boot ROM this section and the CPU vector */
+ /* table is not needed. Thus the default type is set here to */
+ /* DSECT */
+ .reset : > RESET, PAGE = 0, TYPE = DSECT
+ vectors : > VECTORS PAGE = 0, TYPE = DSECT
+
+ /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
+ .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
+
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
+
diff --git a/GPIO_table.h b/GPIO_table.h
new file mode 100644
index 0000000..c6cfa83
--- /dev/null
+++ b/GPIO_table.h
@@ -0,0 +1,194 @@
+#define COMM_gpio00_dir 0UL
+#define COMM_gpio01_dir 0UL
+#define COMM_gpio02_dir 0UL
+#define COMM_gpio03_dir 0UL
+#define COMM_gpio04_dir 0UL
+#define COMM_gpio05_dir 0UL
+#define COMM_gpio06_dir 0UL
+#define COMM_gpio07_dir 0UL
+#define COMM_gpio08_dir 0UL
+#define COMM_gpio09_dir 0UL
+#define COMM_gpio10_dir 0UL
+#define COMM_gpio11_dir 0UL
+
+#define COMM_gpio19_dir 1UL // 63 — SPI
+#define COMM_gpio20_dir 0UL // 64 2:9B mode 2
+#define COMM_gpio21_dir 0UL // 65 2:9A mode 4
+#define COMM_gpio22_dir 0UL // 66 2:12C mode 1
+#define COMM_gpio23_dir 0UL // 67 2:12B control -24V
+#define COMM_gpio24_dir 0UL
+#define COMM_gpio25_dir 0UL
+#define COMM_gpio26_dir 0UL // 72 2:11B control +24V
+#define COMM_gpio27_dir 0UL
+
+#define COMM_gpio32_dir 1UL // 74 2:10B SDA
+#define COMM_gpio33_dir 1UL // 75 2:10C SCL
+#define COMM_gpio34_dir 1UL // 142 — SCI
+
+#define COMM_gpio48_dir 1UL // 88 2:14C DIOD red
+#define COMM_gpio49_dir 1UL // 89 2:14B ts2 red
+#define COMM_gpio50_dir 0UL
+#define COMM_gpio51_dir 0UL // 91 2:13C mode !8
+#define COMM_gpio52_dir 1UL // 94 2:13B ts1 green
+#define COMM_gpio53_dir 0UL
+
+#define COMM_gpio58_dir 1UL // 100 1:13C led term
+#define COMM_gpio59_dir 1UL // 110 1:13B gotov
+#define COMM_gpio60_dir 1UL // 111 1:13A led job
+#define COMM_gpio61_dir 0UL
+#define COMM_gpio62_dir 1UL // 113 1:14B alarm
+#define COMM_gpio63_dir 1UL // 114 1:14A rez out
+
+//===========================================================================
+
+#define VEPP_gpio00_dir 0UL // 5 2:7A input
+#define VEPP_gpio01_dir 0UL // 6 2:4A input
+#define VEPP_gpio02_dir 0UL // 7 2:7B input
+#define VEPP_gpio03_dir 0UL // 10 2:4B input
+#define VEPP_gpio04_dir 0UL // 11 2:7C input
+#define VEPP_gpio05_dir 0UL // 12 2:4C input
+#define VEPP_gpio06_dir 0UL // 13 2:6A input
+#define VEPP_gpio07_dir 0UL // 16 2:3A input
+#define VEPP_gpio08_dir 0UL // 17 2:6B input
+#define VEPP_gpio09_dir 0UL // 18 2:3B input
+#define VEPP_gpio10_dir 0UL // 19 2:6C input
+#define VEPP_gpio11_dir 0UL // 20 2:3C input
+
+#define VEPP_gpio19_dir 1UL // 63 — SPI
+#define VEPP_gpio20_dir 0UL // 64 2:9B mode 2
+#define VEPP_gpio21_dir 0UL // 65 2:9A mode 4
+#define VEPP_gpio22_dir 0UL // 66 2:12C mode 1
+#define VEPP_gpio23_dir 0UL // 67 2:12B input
+#define VEPP_gpio24_dir 0UL // 68 2:12A input
+#define VEPP_gpio25_dir 0UL // 69 2:11C input
+#define VEPP_gpio26_dir 0UL // 72 2:11B input
+#define VEPP_gpio27_dir 0UL // 73 2:11A input
+
+#define VEPP_gpio32_dir 0UL // 74 2:10B input
+#define VEPP_gpio33_dir 0UL // 75 2:10C input
+#define VEPP_gpio34_dir 1UL // 142 — SCI
+
+#define VEPP_gpio48_dir 1UL // 88 2:14C DIOD red
+#define VEPP_gpio49_dir 0UL // 89 2:14B input
+#define VEPP_gpio50_dir 0UL // 90 2:14A input
+#define VEPP_gpio51_dir 0UL // 91 2:13C mode !8
+#define VEPP_gpio52_dir 0UL // 94 2:13B input
+#define VEPP_gpio53_dir 0UL // 95 2:13A input
+
+#define VEPP_gpio58_dir 0UL // 100 1:13C input
+#define VEPP_gpio59_dir 0UL
+#define VEPP_gpio60_dir 1UL // 111 1:13A gotov
+#define VEPP_gpio61_dir 0UL // 112 1:14C input
+#define VEPP_gpio62_dir 1UL // 113 1:14C rezout
+#define VEPP_gpio63_dir 1UL // 114 1:14A ledjob
+
+//===========================================================================
+
+#define ISOL_gpio00_dir 0UL // 5 2:7A
+#define ISOL_gpio01_dir 0UL // 6 2:4A
+#define ISOL_gpio02_dir 0UL // 7 2:7B
+#define ISOL_gpio03_dir 0UL // 10 2:4B
+#define ISOL_gpio04_dir 0UL // 11 2:7C
+#define ISOL_gpio05_dir 0UL // 12 2:4C
+#define ISOL_gpio06_dir 0UL // 13 2:6A
+#define ISOL_gpio07_dir 0UL // 16 2:3A
+#define ISOL_gpio08_dir 0UL // 17 2:6B
+#define ISOL_gpio09_dir 0UL // 18 2:3B
+#define ISOL_gpio10_dir 0UL // 19 2:6C
+#define ISOL_gpio11_dir 0UL // 20 2:3C
+
+#define ISOL_gpio19_dir 1UL // 63 — SPI
+#define ISOL_gpio20_dir 0UL // 64 2:9B mode 2
+#define ISOL_gpio21_dir 0UL // 65 2:9A mode 4
+#define ISOL_gpio22_dir 0UL // 66 2:12C mode 1
+#define ISOL_gpio23_dir 0UL // 67 2:12B opt input 1
+#define ISOL_gpio24_dir 1UL // 68 2:12A led 2
+#define ISOL_gpio25_dir 0UL // 69 2:11C
+#define ISOL_gpio26_dir 1UL // 72 2:11B opt out 2
+#define ISOL_gpio27_dir 1UL // 73 2:11A led 1
+
+#define ISOL_gpio32_dir 1UL // 74 2:10B opt out 1
+#define ISOL_gpio33_dir 0UL // 75 2:10C
+#define ISOL_gpio34_dir 1UL // 142 — SCI
+
+#define ISOL_gpio48_dir 1UL // 88 2:14C DIOD red
+#define ISOL_gpio49_dir 0UL // 89 2:14B
+#define ISOL_gpio50_dir 0UL // 90 2:14A
+#define ISOL_gpio51_dir 0UL // 91 2:13C mode !8
+#define ISOL_gpio52_dir 0UL // 94 2:13B opt input 2
+#define ISOL_gpio53_dir 1UL // 95 2:13A led 3
+
+#define ISOL_gpio58_dir 0UL // 100 1:13C
+#define ISOL_gpio59_dir 1UL // 110 1:13B gotov
+#define ISOL_gpio60_dir 0UL // 111 1:13A
+#define ISOL_gpio61_dir 0UL // 112 1:14C
+#define ISOL_gpio62_dir 0UL // 113 1:14C input
+#define ISOL_gpio63_dir 0UL // 114 1:14A
+
+//===========================================================================
+
+//===========================================================================
+
+#define COMM_GPADIR (COMM_gpio00_dir ) + (COMM_gpio01_dir<<1) + (COMM_gpio02_dir<<2) + (COMM_gpio03_dir<<3) + \
+ (COMM_gpio04_dir<<4) + (COMM_gpio05_dir<<5) + (COMM_gpio06_dir<<6) + (COMM_gpio07_dir<<7) + \
+ (COMM_gpio08_dir<<8) + (COMM_gpio09_dir<<9) + (COMM_gpio10_dir<<10)+ (COMM_gpio11_dir<<11)+ \
+ (COMM_gpio19_dir<<19)+ \
+ (COMM_gpio20_dir<<20)+ (COMM_gpio21_dir<<21)+ (COMM_gpio22_dir<<22)+ (COMM_gpio23_dir<<23)+ \
+ (COMM_gpio24_dir<<24)+ (COMM_gpio25_dir<<25)+ (COMM_gpio26_dir<<26)+ (COMM_gpio27_dir<<27);
+#define COMM_GPBDIR (COMM_gpio32_dir )+ (COMM_gpio33_dir<<1) + (COMM_gpio34_dir<<2 )+ \
+ (COMM_gpio48_dir<<16)+ (COMM_gpio49_dir<<17)+ (COMM_gpio50_dir<<18)+ (COMM_gpio51_dir<<19)+ \
+ (COMM_gpio52_dir<<20)+ (COMM_gpio53_dir<<21)+ \
+ (COMM_gpio58_dir<<26)+ (COMM_gpio59_dir<<27)+ \
+ (COMM_gpio60_dir<<28)+ (COMM_gpio61_dir<<29)+ (COMM_gpio62_dir<<30)+ (COMM_gpio63_dir<<31);
+
+#define BKSD_GPADIR (BKSD_gpio00_dir ) + (BKSD_gpio01_dir<<1) + (BKSD_gpio02_dir<<2) + (BKSD_gpio03_dir<<3) + \
+ (BKSD_gpio04_dir<<4) + (BKSD_gpio05_dir<<5) + (BKSD_gpio06_dir<<6) + (BKSD_gpio07_dir<<7) + \
+ (BKSD_gpio08_dir<<8) + (BKSD_gpio09_dir<<9) + (BKSD_gpio10_dir<<10)+ (BKSD_gpio11_dir<<11)+ \
+ (BKSD_gpio19_dir<<19)+ \
+ (BKSD_gpio20_dir<<20)+ (BKSD_gpio21_dir<<21)+ (BKSD_gpio22_dir<<22)+ (BKSD_gpio23_dir<<23)+ \
+ (BKSD_gpio24_dir<<24)+ (BKSD_gpio25_dir<<25)+ (BKSD_gpio26_dir<<26)+ (BKSD_gpio27_dir<<27);
+#define BKSD_GPBDIR (BKSD_gpio32_dir )+ (BKSD_gpio33_dir<<1) + (BKSD_gpio34_dir<<2 )+ \
+ (BKSD_gpio48_dir<<16)+ (BKSD_gpio49_dir<<17)+ (BKSD_gpio50_dir<<18)+ (BKSD_gpio51_dir<<19)+ \
+ (BKSD_gpio52_dir<<20)+ (BKSD_gpio53_dir<<21)+ \
+ (BKSD_gpio58_dir<<26)+ (BKSD_gpio59_dir<<27)+ \
+ (BKSD_gpio60_dir<<28)+ (BKSD_gpio61_dir<<29)+ (BKSD_gpio62_dir<<30)+ (BKSD_gpio63_dir<<31);
+
+#define PULT_GPADIR (PULT_gpio00_dir ) + (PULT_gpio01_dir<<1) + (PULT_gpio02_dir<<2) + (PULT_gpio03_dir<<3) + \
+ (PULT_gpio04_dir<<4) + (PULT_gpio05_dir<<5) + (PULT_gpio06_dir<<6) + (PULT_gpio07_dir<<7) + \
+ (PULT_gpio08_dir<<8) + (PULT_gpio09_dir<<9) + (PULT_gpio10_dir<<10)+ (PULT_gpio11_dir<<11)+ \
+ (PULT_gpio19_dir<<19)+ \
+ (PULT_gpio20_dir<<20)+ (PULT_gpio21_dir<<21)+ (PULT_gpio22_dir<<22)+ (PULT_gpio23_dir<<23)+ \
+ (PULT_gpio24_dir<<24)+ (PULT_gpio25_dir<<25)+ (PULT_gpio26_dir<<26)+ (PULT_gpio27_dir<<27);
+#define PULT_GPBDIR (PULT_gpio32_dir )+ (PULT_gpio33_dir<<1) + (PULT_gpio34_dir<<2 )+ \
+ (PULT_gpio48_dir<<16)+ (PULT_gpio49_dir<<17)+ (PULT_gpio50_dir<<18)+ (PULT_gpio51_dir<<19)+ \
+ (PULT_gpio52_dir<<20)+ (PULT_gpio53_dir<<21)+ \
+ (PULT_gpio58_dir<<26)+ (PULT_gpio59_dir<<27)+ \
+ (PULT_gpio60_dir<<28)+ (PULT_gpio61_dir<<29)+ (PULT_gpio62_dir<<30)+ (PULT_gpio63_dir<<31);
+
+#define VEPP_GPADIR (VEPP_gpio00_dir ) + (VEPP_gpio01_dir<<1) + (VEPP_gpio02_dir<<2) + (VEPP_gpio03_dir<<3) + \
+ (VEPP_gpio04_dir<<4) + (VEPP_gpio05_dir<<5) + (VEPP_gpio06_dir<<6) + (VEPP_gpio07_dir<<7) + \
+ (VEPP_gpio08_dir<<8) + (VEPP_gpio09_dir<<9) + (VEPP_gpio10_dir<<10)+ (VEPP_gpio11_dir<<11)+ \
+ (VEPP_gpio19_dir<<19)+ \
+ (VEPP_gpio20_dir<<20)+ (VEPP_gpio21_dir<<21)+ (VEPP_gpio22_dir<<22)+ (VEPP_gpio23_dir<<23)+ \
+ (VEPP_gpio24_dir<<24)+ (VEPP_gpio25_dir<<25)+ (VEPP_gpio26_dir<<26)+ (VEPP_gpio27_dir<<27);
+#define VEPP_GPBDIR (VEPP_gpio32_dir )+ (VEPP_gpio33_dir<<1) + (VEPP_gpio34_dir<<2 )+ \
+ (VEPP_gpio48_dir<<16)+ (VEPP_gpio49_dir<<17)+ (VEPP_gpio50_dir<<18)+ (VEPP_gpio51_dir<<19)+ \
+ (VEPP_gpio52_dir<<20)+ (VEPP_gpio53_dir<<21)+ \
+ (VEPP_gpio58_dir<<26)+ (VEPP_gpio59_dir<<27)+ \
+ (VEPP_gpio60_dir<<28)+ (VEPP_gpio61_dir<<29)+ (VEPP_gpio62_dir<<30)+ (VEPP_gpio63_dir<<31);
+
+#define ISOL_GPADIR (ISOL_gpio00_dir ) + (ISOL_gpio01_dir<<1) + (ISOL_gpio02_dir<<2) + (ISOL_gpio03_dir<<3) + \
+ (ISOL_gpio04_dir<<4) + (ISOL_gpio05_dir<<5) + (ISOL_gpio06_dir<<6) + (ISOL_gpio07_dir<<7) + \
+ (ISOL_gpio08_dir<<8) + (ISOL_gpio09_dir<<9) + (ISOL_gpio10_dir<<10)+ (ISOL_gpio11_dir<<11)+ \
+ (ISOL_gpio19_dir<<19)+ \
+ (ISOL_gpio20_dir<<20)+ (ISOL_gpio21_dir<<21)+ (ISOL_gpio22_dir<<22)+ (ISOL_gpio23_dir<<23)+ \
+ (ISOL_gpio24_dir<<24)+ (ISOL_gpio25_dir<<25)+ (ISOL_gpio26_dir<<26)+ (ISOL_gpio27_dir<<27);
+#define ISOL_GPBDIR (ISOL_gpio32_dir )+ (ISOL_gpio33_dir<<1) + (ISOL_gpio34_dir<<2 )+ \
+ (ISOL_gpio48_dir<<16)+ (ISOL_gpio49_dir<<17)+ (ISOL_gpio50_dir<<18)+ (ISOL_gpio51_dir<<19)+ \
+ (ISOL_gpio52_dir<<20)+ (ISOL_gpio53_dir<<21)+ \
+ (ISOL_gpio58_dir<<26)+ (ISOL_gpio59_dir<<27)+ \
+ (ISOL_gpio60_dir<<28)+ (ISOL_gpio61_dir<<29)+ (ISOL_gpio62_dir<<30)+ (ISOL_gpio63_dir<<31);
+
+//===========================================================================
+// No more.
+//===========================================================================
diff --git a/RS485.c b/RS485.c
new file mode 100644
index 0000000..4e57f4a
--- /dev/null
+++ b/RS485.c
@@ -0,0 +1,553 @@
+/****************************************************************/
+/* TMS320C32 */
+/* ====== BIOS, КЛАИН, КЛВСП ====== */
+/* ЦНИИ СЭТ (с) 1998-2000 г. */
+/****************************************************************
+ RS485.с
+ ****************************************************************
+ * Процедуры работы с UART *
+ ****************************************************************/
+
+//#include "big_dsp_module.h"
+
+
+#include "DSP2833x_Device.h"
+#include "DSP2833x_SWPrioritizedIsrLevels.h"
+
+#include "RS485.h"
+#include "bios_dsp.h"
+#include "cntrl_adr.h"
+
+#include "tools.h"
+
+//#include "flash_tools.h"
+
+
+RS_DATA rs_a,rs_b;
+
+unsigned int RS_Len[70]={0};
+
+static char size_cmd15=1;
+
+void RS_RX_Handler(RS_DATA *rs_arr);
+void RS_TX_Handler(RS_DATA *rs_arr);
+
+/** Обработчик прерываний UART - принато */
+interrupt void RSA_RX_Handler(void)
+{
+// Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
+ IER |= M_INT9;
+ IER &= MINT9; // Set "global" priority
+ PieCtrlRegs.PIEIER9.all &= MG91; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ clear_timer_rs_live(&rs_a);
+ RS_RX_Handler(&rs_a);
+
+// Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER9.all = TempPIEIER;
+}
+
+interrupt void RSB_RX_Handler(void)
+{
+// Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
+ IER |= M_INT9;
+ IER &= MINT9; // Set "global" priority
+ PieCtrlRegs.PIEIER9.all &= MG93; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ clear_timer_rs_live(&rs_b);
+ RS_RX_Handler(&rs_b);
+
+// Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER9.all = TempPIEIER;
+}
+
+interrupt void RSA_TX_Handler(void)
+{
+// Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
+ IER |= M_INT9;
+ IER &= MINT9; // Set "global" priority
+ PieCtrlRegs.PIEIER9.all &= MG92; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ clear_timer_rs_live(&rs_a);
+ RS_TX_Handler(&rs_a);
+
+// Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER9.all = TempPIEIER;
+}
+
+interrupt void RSB_TX_Handler(void)
+{
+// Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
+ IER |= M_INT9;
+ IER &= MINT9; // Set "global" priority
+ PieCtrlRegs.PIEIER9.all &= MG94; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ clear_timer_rs_live(&rs_b);
+ RS_TX_Handler(&rs_b);
+
+// Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER9.all = TempPIEIER;
+}
+
+/** Обработчик прерываний UART - принато */
+void RS_RX_Handler(RS_DATA *rs_arr)
+{
+ char Rc;
+ char RS_BytePtr;
+
+// led1_on();
+
+ for(;;) // 'goto' это не оператор азыка С
+ {
+ if(!rs_arr->SciRegs->SCIRXST.bit.RXRDY) // Receiver ready flag
+ {
+ PieCtrlRegs.PIEACK.bit.ACK9 |= 1;
+ rs_arr->SciRegs->SCIFFRX.bit.RXFFINTCLR=1; // Clear INT flag
+ return; // кстати это единственный выход из прерываниа
+ }
+
+ Rc = rs_arr->SciRegs->SCIRXBUF.bit.RXDT; // Читаем символ в любом случае
+
+ if(rs_arr->SciRegs->SCIRXST.bit.RXERROR) // Receiver error flag
+ {
+ rs_arr->SciRegs->SCICTL1.bit.SWRESET=0; // Reset SCI
+ rs_arr->SciRegs->SCICTL1.bit.SWRESET=1; // Relinquish SCI from Reset
+
+ continue;
+ }
+
+ if(rs_arr->RS_DataReady) continue; // Не забрали данные
+
+ if (rs_arr->RS_Flag9bit==1) // дла RS485????????
+ {
+ // Инициализируем переменные и флаги
+ rs_arr->RS_FlagBegin = true; // Ждем заголовок
+ rs_arr->RS_RecvLen = 0;
+ rs_arr->RS_FlagSkiping = false;
+ rs_arr->RS_HeaderCnt = 0;
+ rs_arr->RS_Cmd = 0;
+ }
+
+ if(rs_arr->RS_FlagSkiping) continue; // Не нам
+
+ if (rs_arr->RS_FlagBegin) // Заголовок
+ {
+ if (rs_arr->RS_HeaderCnt==0) // Адрес контроллера или стандартнаа команда
+ {
+ if( (Rc == CNTRL_ADDR_UNIVERSAL) || (Rc == CNTRL_ADDR && CNTRL_ADDR!=0) || ((Rc == rs_arr->addr_answer) && rs_arr->flag_LEADING)
+ || ((Rc == ADDR_FOR_ALL && ADDR_FOR_ALL!=0) && !rs_arr->flag_LEADING))
+
+ {
+ rs_arr->addr_recive=Rc; // запомнили адрес по которому нас запросили
+ rs_arr->RS_Header[rs_arr->RS_HeaderCnt++] = Rc; // Первый байт
+ RS_SetBitMode(rs_arr,8); // перестроились в 8-бит режим
+ }
+ else
+ {
+ rs_arr->RS_FlagSkiping = true; // Не нашему контроллеру
+ rs_arr->RS_FlagBegin = false; // остались в 9-бит режиме
+// led1_off();
+ }
+ }
+ else
+ {
+ rs_arr->RS_Header[rs_arr->RS_HeaderCnt++] = Rc; // Второй байт и т.д.
+
+ if (rs_arr->RS_HeaderCnt == 7 && rs_arr->RS_Cmd==CMD_MODBUS_16 && !rs_arr->flag_LEADING)
+ {
+ RS_Len[CMD_MODBUS_16] = (10+Rc);
+ }
+
+ // если второй байт - это команда
+ if (rs_arr->RS_HeaderCnt == 2)
+ {
+ rs_arr->RS_Cmd = Rc;
+ // Проверка длины посылки
+ // CMD_LOAD - младшаа на данный момент
+ // CMD_STD_ANS - старшаа на данный момент
+ if ((rs_arr->RS_Cmd < CMD_MODBUS_3) || (rs_arr->RS_Cmd > CMD_STD_ANS) || (RS_Len[rs_arr->RS_Cmd]<3)
+ || ((rs_arr->RS_Cmd == CMD_LOAD)&&(rs_arr->RS_PrevCmd != CMD_INITLOAD))
+ )
+ {
+ RS_SetBitMode(rs_arr,9); // Получили все перестроились в 9-бит дла RS485?
+ rs_arr->RS_HeaderCnt = 0; // Потому что команда не та
+ rs_arr->RS_FlagBegin = true;
+ rs_arr->RS_FlagSkiping = false;
+ rs_arr->RS_Cmd=0;
+// led1_off();
+ continue;
+ }
+ if (rs_arr->RS_Cmd == CMD_LOAD) // Дла этой команды заголовок очень короткий
+ rs_arr->RS_FlagBegin = false;// дальше идут данные
+ }
+
+ if( (rs_arr->RS_HeaderCnt >= RS_Len[rs_arr->RS_Cmd]) ||
+ (rs_arr->RS_HeaderCnt >= sizeof(rs_arr->RS_Header)))
+ { // Получили заголовок
+ RS_SetBitMode(rs_arr,9); // Получили все перестроились в 9-бит дла RS485?
+ rs_arr->RS_FlagBegin = false;
+ rs_arr->RS_FlagSkiping = true;
+ rs_arr->RS_DataReady = true;
+ rs_arr->RS_Cmd=0;
+// led1_off();
+ } } }
+ else // Поток данных
+ {
+ if(rs_arr->pRS_RecvPtr<(unsigned int *)Rec_Bloc_Begin || rs_arr->pRS_RecvPtr>(unsigned int *)Rec_Bloc_End)
+ {
+ rs_arr->pRS_RecvPtr = (unsigned int *)Rec_Bloc_Begin; // На программу надейса, а сам не плошай
+ rs_arr->pRecvPtr = (unsigned int *)Rec_Bloc_Begin; // На программу надейса, а сам не плошай
+ }
+ if(rs_arr->RS_PrevCmd != CMD_INITLOAD) continue; // Мы здесь оказались по какой-то чудовищной ошибке
+
+ if(rs_arr->RS_DataReady) // Если данные в основном цикле не забраны,
+ { // то пропускаем следующую посылку
+ rs_arr->RS_FlagSkiping = true; // Игнорируем до следующего заголовка
+// led1_off();
+ continue;
+ }
+ RS_BytePtr = rs_arr->RS_RecvLen++ % 2;
+ if(RS_BytePtr) *rs_arr->pRS_RecvPtr++ |= Rc; // Получили слово
+ else *rs_arr->pRS_RecvPtr = Rc<<8;
+
+ if(rs_arr->RS_Length <= rs_arr->RS_RecvLen) // Конец посылки
+ {
+ rs_arr->RS_PrevCmd = rs_arr->RS_Header[1] = CMD_LOAD;
+ RS_SetBitMode(rs_arr,9); // Получили все данные перестроились в 9-бит дла RS485?
+ rs_arr->RS_FlagSkiping = true; // Игнорируем до следующего заголовка
+ rs_arr->RS_DataReady = true; // Флаг в основной цикл - данные получены
+// led1_off();
+} } } }
+
+/** Обработчик прерываний UART - послано */
+void RS_TX_Handler(RS_DATA *rs_arr)
+{
+ char RS_BytePtr;
+// unsigned int i;
+
+ if(rs_arr->RS_SendBlockMode == BM_CHAR32)
+ {
+ if(++rs_arr->RS_SendLen >= rs_arr->RS_SLength)
+ {
+ enableUARTInt(rs_arr); /* Запрещаем прерываниа по передаче */
+ }
+ SCI_send(rs_arr,*(rs_arr->pRS_SendPtr++));
+
+ if(rs_arr->RS_SendLen >= rs_arr->RS_SLength)
+ {
+ RS_Wait4OK(rs_arr);
+// for (i=0; i <= TIME_WAIT_RS_BYTE_OUT; i++){} /* Пауза дла PC */
+
+ RS_SetBitMode(rs_arr,9); /* Передали все перестроились в 9-бит дла RS485?*/
+ RS_Line_to_receive(rs_arr); /* режим приема RS485 */
+
+ rs_arr->flag_TIMEOUT_to_Send=false; /* сбросили флаг ожиданиа таймаута */
+ }
+ }
+ else /* BM_PACKED */
+ {
+
+ RS_BytePtr = (rs_arr->RS_SendLen++) % 2;
+ if(rs_arr->RS_SendLen >= rs_arr->RS_SLength)
+ {
+ enableUARTInt(rs_arr); /* Запрещаем прерываниа по передаче */
+ }
+ if(RS_BytePtr) SCI_send(rs_arr, LOBYTE( *(rs_arr->pRS_SendPtr++) ));
+ else SCI_send(rs_arr, HIBYTE( *rs_arr->pRS_SendPtr ));
+
+ if(rs_arr->RS_SendLen >= rs_arr->RS_SLength)
+ {
+ RS_Wait4OK(rs_arr);
+// for (i=0; i <= TIME_WAIT_RS_BYTE_OUT; i++){} /* Пауза дла PC */
+// RS_SetBitMode(rs_arr,9); /* Передали все перестроились в 9-бит дла RS485?*/
+// RS_Line_to_receive(); /* режим приема RS485 */
+
+ }
+ }
+
+ PieCtrlRegs.PIEACK.bit.ACK9 |= 1;
+// rs_arr->SciRegs->SCIFFTX.bit.TXINTCLR=1; // Clear INT flag
+}
+
+/** Инициализациа массива длин команд */
+void setup_arr_cmd_length()
+{
+ int i;
+
+ for (i=0;i<70;i++) RS_Len[i]=i;
+
+ RS_Len[CMD_LOAD] = 12;
+ RS_Len[CMD_UPLOAD] = 12;
+ RS_Len[CMD_RUN] = 8;
+ RS_Len[CMD_XFLASH] = 9;
+ RS_Len[CMD_TFLASH] = 16;
+ RS_Len[CMD_PEEK] = 8;
+ RS_Len[CMD_POKE] = 12;
+ RS_Len[CMD_INITLOAD] = 12;
+ RS_Len[CMD_INIT] = 5;
+ RS_Len[CMD_VECTOR] = size_cmd15-2; //sizeof(CMD_TO_TMS)-2;
+ RS_Len[CMD_STD] = size_cmd15-1; //sizeof(CMD_TO_TMS)-1;
+ RS_Len[CMD_IMPULSE] = 8;
+ RS_Len[CMD_MODBUS_3] = 8;
+ RS_Len[CMD_MODBUS_6] = 8;
+ RS_Len[CMD_MODBUS_16] = 13;
+ RS_Len[CMD_MODBUS_15] = 27;
+ RS_Len[CMD_EXTEND] = 18;
+}
+
+/** Настройка режима приема/передачи */
+void RS_SetBitMode(RS_DATA *rs_arr,int n)
+{
+ if(n == 8)
+ {
+ RS_SetLineMode(rs_arr,8,'N',1); /* режим линии */
+ rs_arr->RS_Flag9bit=0;
+ }
+ if(n == 9)
+ {
+ RS_SetLineMode(rs_arr,8,'N',1); /* режим линии */
+ rs_arr->RS_Flag9bit=1;
+} }
+
+/** Посылка блока байтов.
+ Посылает массива 32-битных целых чисел старшие биты должны быть 0.
+ @precondition Работа ф-ции зависит от макро RS_TRANSMIT_INTR
+ @param buf адрес массива
+ @param len количество байт
+ @see RS_BSend, RS_TRANSMIT_INTR */
+int RS_Send(RS_DATA *rs_arr,unsigned int *pBuf,unsigned long len)
+{
+ unsigned int i;
+ for (i=0; i <= 30000; i++){} /* Пауза дла PC */
+
+ RS_Line_to_send(rs_arr); /* режим передачи RS485 */
+
+ for (i=0; i <= 10000; i++){} /* Пауза дла PC */
+
+ rs_arr->RS_SLength = len; /* Настраиваем переменные */
+ rs_arr->pRS_SendPtr = pBuf + 1;
+
+ rs_arr->RS_SendBlockMode = BM_CHAR32;
+
+ RS_Wait4OK(rs_arr); /* Дожидаемса ухода */
+ RS_SetBitMode(rs_arr,8); /* Остальные в 8-бит режиме */
+
+ rs_arr->RS_SendLen = 1; /* Два байта уже передали */
+ if(len > 1)
+ {
+ enableUARTIntW(rs_arr); /* Разрешаем прерываниа по передаче */
+ SCI_send(rs_arr, *pBuf); // Передаем второй байт по прерыванию
+ }
+ else
+ {
+ SCI_send(rs_arr, *pBuf); // Передаем второй байт по прерыванию
+ RS_Wait4OK(rs_arr); /* Дожидаемса ухода без прерываниа */
+ for (i=0; i <= TIME_WAIT_RS_BYTE_OUT; i++){} /* Пауза дла PC */
+ RS_SetBitMode(rs_arr,9); /* Обратно в 9-бит режим */
+ RS_Line_to_receive(rs_arr); /* режим приема RS485 */
+ }
+ return 0;
+}
+
+// Посылка блока упакованных байтов
+int RS_BSend(RS_DATA *rs_arr,unsigned int *pBuf, unsigned long len)
+{
+
+ RS_Line_to_send(rs_arr); // режим передачи RS485
+
+ rs_arr->RS_SLength = len; // Настраиваем переменные
+ rs_arr->pRS_SendPtr = pBuf;
+ rs_arr->RS_SendBlockMode = BM_PACKED;
+
+ RS_Wait4OK(rs_arr); // Ожидаем очистки и ухода последнего байта
+ RS_SetBitMode(rs_arr,8); /* Остальные в 8-бит режиме */
+
+ rs_arr->RS_SendLen = 1; // Один байт уже передали
+
+ enableUARTIntW(rs_arr); /* Разрешаем прерываниа по передаче */
+
+ SCI_send(rs_arr,HIBYTE(*pBuf));// Передаем первый байт
+
+ return 0;
+}
+
+/** Устанавливает скорость обмена.
+ @param speed скорость RS в бод */
+/** Устанавливает скорость обмена.
+ @param speed скорость RS в бод */
+void RS_SetLineSpeed(RS_DATA *rs_arr,unsigned long speed)
+{
+ long SciBaud;
+
+ SciBaud = LSPCLK/(speed*8.0);
+
+// if((SciBaud-(unsigned int)SciBaud)>0.5) SciBaud++;
+
+ rs_arr->SciRegs->SCIHBAUD = HIBYTE((int)SciBaud);
+ rs_arr->SciRegs->SCILBAUD = LOBYTE((int)SciBaud);
+}
+
+
+/** Инициализациа последовательного порта */
+void create_uart_vars(char size_cmd15_set)
+{
+ size_cmd15=size_cmd15_set;
+ rs_a.commnumber=COM_1;
+ rs_b.commnumber=COM_2;
+}
+
+
+
+/** Инициализациа последовательного порта */
+
+void setup_uart(char commnumber, unsigned long speed_baud)
+{
+ volatile struct SCI_REGS *SciRegs;
+ RS_DATA *rs_arr;
+
+ if(commnumber==COM_1)
+ {
+ rs_a.SciRegs = &SciaRegs;
+ rs_arr = &rs_a;
+
+ EALLOW;
+
+ GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // SCITXDA - SCI-A transmit(O)
+ GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // SCIRXDA - SCI-A receive (I)
+
+ PieVectTable.SCIRXINTA = &RSA_RX_Handler;
+ PieVectTable.SCITXINTA = &RSA_TX_Handler;
+ PieCtrlRegs.PIEIER9.bit.INTx1=1; // PIE Group 9, INT1
+ PieCtrlRegs.PIEIER9.bit.INTx2=1; // PIE Group 9, INT2
+ IER |= M_INT9; // Enable CPU INT
+ EDIS;
+ }
+
+ if(commnumber==COM_2)
+ {
+ rs_b.SciRegs = &ScibRegs;
+ rs_arr = &rs_b;
+
+ EALLOW;
+
+ GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 2; // SCITXDB - SCI-B transmit(O)
+ GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 2; // SCIRXDB - SCI-B receive (I)
+
+ GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0; // GPIO 34 - general purpose I/O 34 (default)
+ GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1; // Configures the GPIO pin as an output
+
+ PieVectTable.SCIRXINTB = &RSB_RX_Handler;
+ PieVectTable.SCITXINTB = &RSB_TX_Handler;
+
+ PieCtrlRegs.PIEIER9.bit.INTx3=1; // PIE Group 9, INT3
+ PieCtrlRegs.PIEIER9.bit.INTx4=1; // PIE Group 9, INT4
+ IER |= M_INT9; // Enable CPU INT
+ EDIS;
+ }
+
+ rs_arr->commnumber = commnumber;
+ SciRegs = rs_arr->SciRegs;
+ RS_SetLineMode(rs_arr,8,'N',1);
+
+// enable TX, RX, internal SCICLK,
+// Disable RX ERR, SLEEP, TXWAKE
+
+ SciRegs->SCIFFCT.bit.ABDCLR=1;
+ SciRegs->SCIFFCT.bit.CDC=0;
+
+ SciRegs->SCICTL1.bit.RXERRINTENA=0;
+ SciRegs->SCICTL1.bit.SWRESET=0;
+ SciRegs->SCICTL1.bit.TXWAKE=0;
+ SciRegs->SCICTL1.bit.SLEEP=0;
+ SciRegs->SCICTL1.bit.TXENA=1;
+ SciRegs->SCICTL1.bit.RXENA=1;
+
+ SciRegs->SCIFFTX.bit.SCIFFENA=0; // fifo off
+ SciRegs->SCIFFRX.bit.RXFFIL=1; // Длина наименьшей команды
+
+ setup_arr_cmd_length();
+ RS_SetLineSpeed(rs_arr,speed_baud); // скорость линии
+ RS_Line_to_receive(rs_arr); // режим приема RS485
+ enableUARTInt(rs_arr); // разрешение прерываний UART
+ RS_SetBitMode(rs_arr,9);
+ rs_arr->RS_PrevCmd = 0; // не было никаких команд
+ rs_arr->flag_TIMEOUT_to_Send = 0;
+ rs_arr->flag_LEADING = 0;
+
+ SciRegs->SCIFFRX.bit.RXFFINTCLR=1; // Clear INT flag
+ SciRegs->SCICTL1.bit.SWRESET=1; // Relinquish SCI from Reset
+}
+
+/** Настройка режима линии.
+ @param bit количество бит данных
+ @param parity режим четности (N,O,E,M,S)
+ @param stop количество стоповых бит */
+void RS_SetLineMode(RS_DATA *rs_arr, int bit, char parity, int stop)
+{
+ volatile struct SCI_REGS *SciRegs;
+/*
+SCICCR - SCI Communication Control Register
+Bit Bit Name Designation Functions
+2-0 SCI CHAR2-0 SCICHAR Select the character (data) length (one to eight bits).
+3 ADDR/IDLE MODE ADDRIDLE_MODE The idle-line mode (0) is usually used for normal communications because the address-bit mode adds an extra bit to the frame. The idle-line mode does not add this extra bit and is compatible with RS-232 type communications.
+4 LOOP BACK ENABLE LOOPBKENA This bit enables (1) the Loop Back test mode where the Tx pin is internally connected to the Rx pin.
+5 PARITY ENABLE PARITYENA Enables the parity function if set to 1, or disables the parity function if cleared to 0.
+6 EVEN/ODD PARITY PARITY If parity is enabled, selects odd parity if cleared to 0 or even parity if set to 1.
+7 STOP BITS STOPBITS Determines the number of stop bits transmitted-one stop bit if cleared to 0 or two stop bits if set to 1.
+*/
+
+ SciRegs = rs_arr->SciRegs;
+
+ if(bit>0 && bit<9) SciRegs->SCICCR.bit.SCICHAR = bit-1;
+
+ switch(parity)
+ {
+ case 'N': SciRegs->SCICCR.bit.PARITYENA = 0;
+ break;
+ case 'O': SciRegs->SCICCR.bit.PARITYENA = 1;
+ SciRegs->SCICCR.bit.PARITY = 0;
+ break;
+ case 'E': SciRegs->SCICCR.bit.PARITYENA = 1;
+ SciRegs->SCICCR.bit.PARITY = 1;
+ break;
+ }
+
+ if (stop==1) SciRegs->SCICCR.bit.STOPBITS = 0;
+ if (stop==2) SciRegs->SCICCR.bit.STOPBITS = 1;
+
+ SciRegs->SCICCR.bit.LOOPBKENA = 0; //0
+ SciRegs->SCICCR.bit.ADDRIDLE_MODE = 0;
+}
+
+void clear_timer_rs_live(RS_DATA *rs_arr)
+{
+ rs_arr->time_wait_rs_out=0;
+}
+
+/* проверка на живучесть RS */
+void test_rs_live(RS_DATA *rs_arr)
+{
+/* if (rs_arr->time_wait_rs_out < RS_TIME_OUT)
+ rs_arr->time_wait_rs_out++;
+ else
+ {
+ rs_arr->time_wait_rs_out=0;
+ RS_Line_to_receive(rs_arr); // режим приема RS485
+ RS_SetBitMode(rs_arr,9);
+}*/ }
diff --git a/RS485.h b/RS485.h
new file mode 100644
index 0000000..3e4ca38
--- /dev/null
+++ b/RS485.h
@@ -0,0 +1,138 @@
+/****************************************************************/
+/* TMS320C32 */
+/* ====== BIOS, КЛАИН, КЛВСП ====== */
+/* ЦНИИ СЭТ (с) 1998-2000 г. */
+/****************************************************************
+ RS485.h
+ ****************************************************************
+ * Процедуры работы с UART *
+ ****************************************************************/
+#ifndef _RS485
+#define _RS485
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//#include "DSP2833x_Device.h" // DSP281x Headerfile Include File
+//#include "DSP2833x_Sci.h"
+//#include "cntrl_adr.h"
+//#include "params.h"
+
+#define COM_1 1
+#define COM_2 2
+
+#define MAX_RECEIVE_LENGTH 400 // 80 //150
+#define MAX_SEND_LENGTH 400 //150
+
+#define TIME_WAIT_RS_BYTE_OUT 1000
+#define TIME_WAIT_RS_LOST_BYTE 100
+#define RS_TIME_OUT (SECOND*10)
+
+#define Rec_Bloc_Begin 0x200000
+#define Rec_Bloc_End 0x2F0000
+#define Rec_Bloc_Length (Rec_Bloc_End-Rec_Bloc_Begin)
+
+/* Message RS declaration */
+typedef struct
+{
+ volatile struct SCI_REGS *SciRegs;
+
+ unsigned int commnumber; // Номер порта
+ unsigned long RS_Length; // Длина пакета
+
+ unsigned int *pRS_RecvPtr; // Буфер приема
+ unsigned int *pRS_SendPtr; // Буфер посылки
+ unsigned int *pRecvPtr;
+
+ unsigned int RS_PrevCmd; // Предыдущаа комманда
+ unsigned int RS_Cmd; // Текущаа комманда
+ unsigned int RS_Header[MAX_RECEIVE_LENGTH]; // Заголовок
+ unsigned int flag_TIMEOUT_to_Send; // Флаг ожиданиа таймаута на отсылку
+ unsigned int flag_TIMEOUT_to_Receive; // Флаг ожиданиа таймаута на прием
+ unsigned int RS_DataReady; // Флаг готовности RS данных
+ unsigned int buffer[MAX_SEND_LENGTH]; // Буфер дла отсылки по RS
+
+ unsigned int addr_answer; // адрес куда отвечать в режиме ведущего
+ unsigned int addr_recive; // адрес по которому нас запросили
+ unsigned int flag_LEADING; // Флаг режима контроллера (по умолчанию ведомый)
+ unsigned long RS_RecvLen;
+ unsigned long RS_SLength; // Длина пакета дла посылки
+ unsigned long RS_SendLen; // Количество байт уже передали
+ char RS_SendBlockMode; // Режим передачи
+ char RS_Flag9bit; // дла RS485????????
+ int BS_LoadOK; // Флаг успешности приема блока
+ int RS_FlagBegin;
+ int RS_HeaderCnt;
+ int RS_FlagSkiping;
+ unsigned long curr_baud;
+ unsigned long time_wait_rs_out;
+
+} RS_DATA;
+
+extern RS_DATA rs_a,rs_b;
+
+extern unsigned int
+ RS_Len[70]; /* Действительнаа длина команды (отладочной) + 1 */
+
+interrupt void RSA_RX_Handler(void);
+interrupt void RSA_TX_Handler(void);
+interrupt void RSB_RX_Handler(void);
+interrupt void RSB_TX_Handler(void);
+
+/* иницилизациа переменных rs_a,rs_b*/
+void create_uart_vars(char size_cmd15);
+
+/** Повторнаа инициализациа последовательного порта, используетса после подвиса */
+/** Настройка режима приема/передачи */
+void RS_SetBitMode(RS_DATA *rs_arr, int n);
+
+/** Посылка блока байтов.
+ Посылает массива 32-битных целых чисел старшие биты должны быть 0.
+ @precondition Работа ф-ции зависит от макро RS_TRANSMIT_INTR
+ @param buf адрес массива
+ @param len количество байт
+ @see RS_BSend, RS_TRANSMIT_INTR
+*/
+int RS_Send(RS_DATA *rs_arr,unsigned int *pBuf, unsigned long len);
+
+/** Посылка блока упакованных байтов.
+ @precondition Работа ф-ции зависит от макро RS_TRANSMIT_INTR
+ @param buf адрес массива
+ @param len количество 8-битных байт
+ @see RS_Send, RS_TRANSMIT_INTR
+ */
+int RS_BSend(RS_DATA *rs_arr,unsigned int *pBuf, unsigned long len);
+
+/** Инициализациа последовательного порта */
+void setup_uart(char commnumber,unsigned long speed_baud); /* speed_baud - скорость линии в бодах */
+
+void RS_SetLineMode(RS_DATA *rs_arr, int bit, char parity, int stop);
+void RS_SetLineSpeed(RS_DATA *rs_arr, unsigned long speed);
+
+// Transmit a character from the SCI'
+#define SCI_send(x,y) x->SciRegs->SCITXBUF=(unsigned char)(y)
+
+// Ожидание завершениа передачи UART
+// wait for TRDY =1 for empty state
+#define RS_Wait4OK(x) while(!(x->SciRegs->SCICTL2.bit.TXEMPTY))
+
+/** Переключение линии на прием */
+#define RS_Line_to_receive(x) if(x->commnumber==COM_2) GpioDataRegs.GPBDAT.bit.GPIO34 = 1;
+
+/** Переключение линии на передачу */
+#define RS_Line_to_send(x) if(x->commnumber==COM_2) GpioDataRegs.GPBDAT.bit.GPIO34 = 0;
+
+/** Разрешение прерываний по получению символа и ошибкам от UART */
+#define enableUARTInt(x) x->SciRegs->SCICTL2.all=2
+#define enableUARTIntW(x) x->SciRegs->SCICTL2.all=1
+
+void clear_timer_rs_live(RS_DATA *rs_arr);
+void test_rs_live(RS_DATA *rs_arr);
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _RS485 */
+
diff --git a/aaa/gel/DSP2833x_DualMap_EPWM.gel b/aaa/gel/DSP2833x_DualMap_EPWM.gel
deleted file mode 100644
index e08455b..0000000
--- a/aaa/gel/DSP2833x_DualMap_EPWM.gel
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
-/* TI File $Revision: /main/1 $ */
-/* Checkin $Date: May 7, 2008 13:07:07 $ */
-/***********************************************************************/
-/* File: DSP2833x_DualMap_EPWM.gel
-/*
-/* Description:
-/* Adds dual-mapped EPWM registers to the GEL menu in
-/* Code Composer Studio and allows user to enable dual-mapping of
-/* EPWM registers to Peripheral Frame 3 (DMA-accessible) register
-/* space
-//#####################################################################
-// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
-// $Release Date: August 1, 2008 $
-//#####################################################################
-*/
-
-/********************************************************************/
-/* Dual-Mapped Enhanced PWM Registers */
-/********************************************************************/
-
-/* Add a space line to the GEL menu */
-menuitem "___________________________________";
-hotmenu ___() {}
-
-menuitem "Dual-Mapped ePWM Registers";
-hotmenu Enable_ePWM_Dual_Mapping ()
-{
- *0x702E = (*0x702E) | 0x0001; /* MAPCNF[MAPEPWM] = 1 */
-}
-hotmenu ePWM1_DualMapped_All_Regs()
-{
- GEL_WatchAdd("*0x5800,x","ePWM1 TBCTL");
- GEL_WatchAdd("*0x5801,x","ePWM1 TBSTS");
- GEL_WatchAdd("*0x5802,x","ePWM1 TBPHSHR");
- GEL_WatchAdd("*0x5803,x","ePWM1 TBPHS");
- GEL_WatchAdd("*0x5804,x","ePWM1 TBCTR");
- GEL_WatchAdd("*0x5805,x","ePWM1 TBPRD");
- GEL_WatchAdd("*0x5807,x","ePWM1 CMPCTL");
- GEL_WatchAdd("*0x5808,x","ePWM1 CMPAHR");
- GEL_WatchAdd("*0x5809,x","ePWM1 CMPA");
- GEL_WatchAdd("*0x580A,x","ePWM1 CMPB");
- GEL_WatchAdd("*0x580B,x","ePWM1 AQCTLA");
- GEL_WatchAdd("*0x580C,x","ePWM1 AQCTLB");
- GEL_WatchAdd("*0x580D,x","ePWM1 AQSFRC");
- GEL_WatchAdd("*0x580E,x","ePWM1 AQCSFRC");
- GEL_WatchAdd("*0x580F,x","ePWM1 DBCTL");
- GEL_WatchAdd("*0x5810,x","ePWM1 DBRED");
- GEL_WatchAdd("*0x5811,x","ePWM1 DBFED");
- GEL_WatchAdd("*0x5812,x","ePWM1 TZSEL");
- GEL_WatchAdd("*0x5813,x","ePWM1 TZDCSEL");
- GEL_WatchAdd("*0x5814,x","ePWM1 TZCTL");
- GEL_WatchAdd("*0x5815,x","ePWM1 TZEINT");
- GEL_WatchAdd("*0x5816,x","ePWM1 TZFLG");
- GEL_WatchAdd("*0x5817,x","ePWM1 TZCLR");
- GEL_WatchAdd("*0x5818,x","ePWM1 TZFRC");
- GEL_WatchAdd("*0x5819,x","ePWM1 ETSEL");
- GEL_WatchAdd("*0x581A,x","ePWM1 ETPS");
- GEL_WatchAdd("*0x581B,x","ePWM1 ETFLG");
- GEL_WatchAdd("*0x581C,x","ePWM1 ETCLR");
- GEL_WatchAdd("*0x581D,x","ePWM1 ETFRC");
- GEL_WatchAdd("*0x581E,x","ePWM1 PCCTL");
- GEL_WatchAdd("*0x5820,x","ePWM1 HRCNFG");
-}
-
-hotmenu ePWM2_DualMapped_All_Regs()
-{
- GEL_WatchAdd("*0x5840,x","ePWM2 TBCTL");
- GEL_WatchAdd("*0x5841,x","ePWM2 TBSTS");
- GEL_WatchAdd("*0x5842,x","ePWM2 TBPHSHR");
- GEL_WatchAdd("*0x5843,x","ePWM2 TBPHS");
- GEL_WatchAdd("*0x5844,x","ePWM2 TBCTR");
- GEL_WatchAdd("*0x5845,x","ePWM2 TBPRD");
- GEL_WatchAdd("*0x5847,x","ePWM2 CMPCTL");
- GEL_WatchAdd("*0x5848,x","ePWM2 CMPAHR");
- GEL_WatchAdd("*0x5849,x","ePWM2 CMPA");
- GEL_WatchAdd("*0x584A,x","ePWM2 CMPB");
- GEL_WatchAdd("*0x584B,x","ePWM2 AQCTLA");
- GEL_WatchAdd("*0x584C,x","ePWM2 AQCTLB");
- GEL_WatchAdd("*0x584D,x","ePWM2 AQSFRC");
- GEL_WatchAdd("*0x584E,x","ePWM2 AQCSFRC");
- GEL_WatchAdd("*0x584F,x","ePWM2 DBCTL");
- GEL_WatchAdd("*0x5850,x","ePWM2 DBRED");
- GEL_WatchAdd("*0x5851,x","ePWM2 DBFED");
- GEL_WatchAdd("*0x5852,x","ePWM2 TZSEL");
- GEL_WatchAdd("*0x5853,x","ePWM2 TZDCSEL");
- GEL_WatchAdd("*0x5854,x","ePWM2 TZCTL");
- GEL_WatchAdd("*0x5855,x","ePWM2 TZEINT");
- GEL_WatchAdd("*0x5856,x","ePWM2 TZFLG");
- GEL_WatchAdd("*0x5857,x","ePWM2 TZCLR");
- GEL_WatchAdd("*0x5858,x","ePWM2 TZFRC");
- GEL_WatchAdd("*0x5859,x","ePWM2 ETSEL");
- GEL_WatchAdd("*0x585A,x","ePWM2 ETPS");
- GEL_WatchAdd("*0x585B,x","ePWM2 ETFLG");
- GEL_WatchAdd("*0x585C,x","ePWM2 ETCLR");
- GEL_WatchAdd("*0x585D,x","ePWM2 ETFRC");
- GEL_WatchAdd("*0x585E,x","ePWM2 PCCTL");
- GEL_WatchAdd("*0x5860,x","ePWM2 HRCNFG");
-}
-hotmenu ePWM3_DualMapped_All_Regs()
-{
- GEL_WatchAdd("*0x5880,x","ePWM3 TBCTL");
- GEL_WatchAdd("*0x5881,x","ePWM3 TBSTS");
- GEL_WatchAdd("*0x5882,x","ePWM3 TBPHSHR");
- GEL_WatchAdd("*0x5883,x","ePWM3 TBPHS");
- GEL_WatchAdd("*0x5884,x","ePWM3 TBCTR");
- GEL_WatchAdd("*0x5885,x","ePWM3 TBPRD");
- GEL_WatchAdd("*0x5887,x","ePWM3 CMPCTL");
- GEL_WatchAdd("*0x5888,x","ePWM3 CMPAHR");
- GEL_WatchAdd("*0x5889,x","ePWM3 CMPA");
- GEL_WatchAdd("*0x588A,x","ePWM3 CMPB");
- GEL_WatchAdd("*0x588B,x","ePWM3 AQCTLA");
- GEL_WatchAdd("*0x588C,x","ePWM3 AQCTLB");
- GEL_WatchAdd("*0x588D,x","ePWM3 AQSFRC");
- GEL_WatchAdd("*0x588E,x","ePWM3 AQCSFRC");
- GEL_WatchAdd("*0x588F,x","ePWM3 DBCTL");
- GEL_WatchAdd("*0x5890,x","ePWM3 DBRED");
- GEL_WatchAdd("*0x5891,x","ePWM3 DBFED");
- GEL_WatchAdd("*0x5892,x","ePWM3 TZSEL");
- GEL_WatchAdd("*0x5893,x","ePWM3 TZDCSEL");
- GEL_WatchAdd("*0x5894,x","ePWM3 TZCTL");
- GEL_WatchAdd("*0x5895,x","ePWM3 TZEINT");
- GEL_WatchAdd("*0x5896,x","ePWM3 TZFLG");
- GEL_WatchAdd("*0x5897,x","ePWM3 TZCLR");
- GEL_WatchAdd("*0x5898,x","ePWM3 TZFRC");
- GEL_WatchAdd("*0x5899,x","ePWM3 ETSEL");
- GEL_WatchAdd("*0x589A,x","ePWM3 ETPS");
- GEL_WatchAdd("*0x589B,x","ePWM3 ETFLG");
- GEL_WatchAdd("*0x589C,x","ePWM3 ETCLR");
- GEL_WatchAdd("*0x589D,x","ePWM3 ETFRC");
- GEL_WatchAdd("*0x589E,x","ePWM3 PCCTL");
- GEL_WatchAdd("*0x58A0,x","ePWM3 HRCNFG");
-}
-hotmenu ePWM4_DualMapped_All_Regs()
-{
- GEL_WatchAdd("*0x58C0,x","ePWM4 TBCTL");
- GEL_WatchAdd("*0x58C1,x","ePWM4 TBSTS");
- GEL_WatchAdd("*0x58C2,x","ePWM4 TBPHSHR");
- GEL_WatchAdd("*0x58C3,x","ePWM4 TBPHS");
- GEL_WatchAdd("*0x58C4,x","ePWM4 TBCTR");
- GEL_WatchAdd("*0x58C5,x","ePWM4 TBPRD");
- GEL_WatchAdd("*0x58C7,x","ePWM4 CMPCTL");
- GEL_WatchAdd("*0x58C8,x","ePWM4 CMPAHR");
- GEL_WatchAdd("*0x58C9,x","ePWM4 CMPA");
- GEL_WatchAdd("*0x58CA,x","ePWM4 CMPB");
- GEL_WatchAdd("*0x58CB,x","ePWM4 AQCTLA");
- GEL_WatchAdd("*0x58CC,x","ePWM4 AQCTLB");
- GEL_WatchAdd("*0x58CD,x","ePWM4 AQSFRC");
- GEL_WatchAdd("*0x58CE,x","ePWM4 AQCSFRC");
- GEL_WatchAdd("*0x58CF,x","ePWM4 DBCTL");
- GEL_WatchAdd("*0x58D0,x","ePWM4 DBRED");
- GEL_WatchAdd("*0x58D1,x","ePWM4 DBFED");
- GEL_WatchAdd("*0x58D2,x","ePWM4 TZSEL");
- GEL_WatchAdd("*0x58D3,x","ePWM4 TZDCSEL");
- GEL_WatchAdd("*0x58D4,x","ePWM4 TZCTL");
- GEL_WatchAdd("*0x58D5,x","ePWM4 TZEINT");
- GEL_WatchAdd("*0x58D6,x","ePWM4 TZFLG");
- GEL_WatchAdd("*0x58D7,x","ePWM4 TZCLR");
- GEL_WatchAdd("*0x58D8,x","ePWM4 TZFRC");
- GEL_WatchAdd("*0x58D9,x","ePWM4 ETSEL");
- GEL_WatchAdd("*0x58DA,x","ePWM4 ETPS");
- GEL_WatchAdd("*0x58DB,x","ePWM4 ETFLG");
- GEL_WatchAdd("*0x58DC,x","ePWM4 ETCLR");
- GEL_WatchAdd("*0x58DD,x","ePWM4 ETFRC");
- GEL_WatchAdd("*0x58DE,x","ePWM4 PCCTL");
- GEL_WatchAdd("*0x58E0,x","ePWM4 HRCNFG");
-}
-hotmenu ePWM5_DualMapped_All_Regs()
-{
- GEL_WatchAdd("*0x5900,x","ePWM5 TBCTL");
- GEL_WatchAdd("*0x5901,x","ePWM5 TBSTS");
- GEL_WatchAdd("*0x5902,x","ePWM5 TBPHSHR");
- GEL_WatchAdd("*0x5903,x","ePWM5 TBPHS");
- GEL_WatchAdd("*0x5904,x","ePWM5 TBCTR");
- GEL_WatchAdd("*0x5905,x","ePWM5 TBPRD");
- GEL_WatchAdd("*0x5907,x","ePWM5 CMPCTL");
- GEL_WatchAdd("*0x5908,x","ePWM5 CMPAHR");
- GEL_WatchAdd("*0x5909,x","ePWM5 CMPA");
- GEL_WatchAdd("*0x590A,x","ePWM5 CMPB");
- GEL_WatchAdd("*0x590B,x","ePWM5 AQCTLA");
- GEL_WatchAdd("*0x590C,x","ePWM5 AQCTLB");
- GEL_WatchAdd("*0x590D,x","ePWM5 AQSFRC");
- GEL_WatchAdd("*0x590E,x","ePWM5 AQCSFRC");
- GEL_WatchAdd("*0x590F,x","ePWM5 DBCTL");
- GEL_WatchAdd("*0x5910,x","ePWM5 DBRED");
- GEL_WatchAdd("*0x5911,x","ePWM5 DBFED");
- GEL_WatchAdd("*0x5912,x","ePWM5 TZSEL");
- GEL_WatchAdd("*0x5913,x","ePWM5 TZDCSEL");
- GEL_WatchAdd("*0x5914,x","ePWM5 TZCTL");
- GEL_WatchAdd("*0x5915,x","ePWM5 TZEINT");
- GEL_WatchAdd("*0x5916,x","ePWM5 TZFLG");
- GEL_WatchAdd("*0x5917,x","ePWM5 TZCLR");
- GEL_WatchAdd("*0x5918,x","ePWM5 TZFRC");
- GEL_WatchAdd("*0x5919,x","ePWM5 ETSEL");
- GEL_WatchAdd("*0x591A,x","ePWM5 ETPS");
- GEL_WatchAdd("*0x591B,x","ePWM5 ETFLG");
- GEL_WatchAdd("*0x591C,x","ePWM5 ETCLR");
- GEL_WatchAdd("*0x591D,x","ePWM5 ETFRC");
- GEL_WatchAdd("*0x591E,x","ePWM5 PCCTL");
- GEL_WatchAdd("*0x5920,x","ePWM5 HRCNFG");
-}
-hotmenu ePWM6_DualMapped_All_Regs()
-{
- GEL_WatchAdd("*0x5940,x","ePWM6 TBCTL");
- GEL_WatchAdd("*0x5941,x","ePWM6 TBSTS");
- GEL_WatchAdd("*0x5942,x","ePWM6 TBPHSHR");
- GEL_WatchAdd("*0x5943,x","ePWM6 TBPHS");
- GEL_WatchAdd("*0x5944,x","ePWM6 TBCTR");
- GEL_WatchAdd("*0x5945,x","ePWM6 TBPRD");
- GEL_WatchAdd("*0x5947,x","ePWM6 CMPCTL");
- GEL_WatchAdd("*0x5948,x","ePWM6 CMPAHR");
- GEL_WatchAdd("*0x5949,x","ePWM6 CMPA");
- GEL_WatchAdd("*0x594A,x","ePWM6 CMPB");
- GEL_WatchAdd("*0x594B,x","ePWM6 AQCTLA");
- GEL_WatchAdd("*0x594C,x","ePWM6 AQCTLB");
- GEL_WatchAdd("*0x594D,x","ePWM6 AQSFRC");
- GEL_WatchAdd("*0x594E,x","ePWM6 AQCSFRC");
- GEL_WatchAdd("*0x594F,x","ePWM6 DBCTL");
- GEL_WatchAdd("*0x5950,x","ePWM6 DBRED");
- GEL_WatchAdd("*0x5951,x","ePWM6 DBFED");
- GEL_WatchAdd("*0x5952,x","ePWM6 TZSEL");
- GEL_WatchAdd("*0x5953,x","ePWM6 TZDCSEL");
- GEL_WatchAdd("*0x5954,x","ePWM6 TZCTL");
- GEL_WatchAdd("*0x5955,x","ePWM6 TZEINT");
- GEL_WatchAdd("*0x5956,x","ePWM6 TZFLG");
- GEL_WatchAdd("*0x5957,x","ePWM6 TZCLR");
- GEL_WatchAdd("*0x5958,x","ePWM6 TZFRC");
- GEL_WatchAdd("*0x5959,x","ePWM6 ETSEL");
- GEL_WatchAdd("*0x595A,x","ePWM6 ETPS");
- GEL_WatchAdd("*0x595B,x","ePWM6 ETFLG");
- GEL_WatchAdd("*0x595C,x","ePWM6 ETCLR");
- GEL_WatchAdd("*0x595D,x","ePWM6 ETFRC");
- GEL_WatchAdd("*0x595E,x","ePWM6 PCCTL");
- GEL_WatchAdd("*0x5960,x","ePWM6 HRCNFG");
-
-}
-
diff --git a/bin/HEX2BIN.EXE b/bin/HEX2BIN.EXE
new file mode 100644
index 0000000..0a3799a
Binary files /dev/null and b/bin/HEX2BIN.EXE differ
diff --git a/bin/hex2000.exe b/bin/hex2000.exe
new file mode 100644
index 0000000..7072690
Binary files /dev/null and b/bin/hex2000.exe differ
diff --git a/bin/ice.bin b/bin/ice.bin
new file mode 100644
index 0000000..0d11572
Binary files /dev/null and b/bin/ice.bin differ
diff --git a/bin/ice.hex b/bin/ice.hex
new file mode 100644
index 0000000..758214e
--- /dev/null
+++ b/bin/ice.hex
@@ -0,0 +1,979 @@
+:20000000AA0800000000000000000000000000000000000041B8E1010000BDB900FF40DFBF
+:2000200000000000C1C081C1400101C3C003800241C201C6C006800741C70005C1C581C4C4
+:20004000400401CCC00C800D41CD000FC1CF81CE400E000AC1CA81CB400B01C9C0098008A5
+:2000600041C801D8C018801941D9001BC1DB81DA401A001EC1DE81DF401F01DDC01D801CD4
+:2000800041DC0014C1D481D5401501D7C017801641D601D2C012801341D30011C1D181D053
+:2000A000401001F0C030803141F10033C1F381F240320036C1F681F7403701F5C0358034E5
+:2000C00041F4003CC1FC81FD403D01FFC03F803E41FE01FAC03A803B41FB0039C1F981F8A3
+:2000E00040380028C1E881E9402901EBC02B802A41EA01EEC02E802F41EF002DC1ED81EC34
+:20010000402C01E4C024802541E50027C1E781E640260022C1E281E3402301E1C021802054
+:2001200041E001A0C060806141A10063C1A381A240620066C1A681A7406701A5C065806443
+:2001400041A4006CC1AC81AD406D01AFC06F806E41AE01AAC06A806B41AB0069C1A981A8A2
+:2001600040680078C1B881B9407901BBC07B807A41BA01BEC07E807F41BF007DC1BD81BCD3
+:20018000407C01B4C074807541B50077C1B781B640760072C1B281B3407301B1C071807054
+:2001A00041B00050C190819140510193C053805241920196C056805741970055C1958194A2
+:2001C0004054019CC05C805D419D005FC19F819E405E005AC19A819B405B0199C0598058A4
+:2001E00041980188C04880494189004BC18B818A404A004EC18E818F404F018DC04D804C33
+:20020000418C0044C184818540450187C047804641860182C042804341830041C181818051
+:200220004040FFFF82D700000000EEFF58D80000E6127D391358FA3F6AEF74BF00000000EC
+:200240000000000000000000000000000000000000000000FFFFF0D700000000FFFFF1D713
+:2002600000000000FFFFF2D700000000FEFFFED7000000000000FFFFFDD700000000FFFF15
+:2002800071E000000000F8FF72E0000000000000000000000000000000000000F8FF80E06D
+:2002A000000000000000000000000000000000000000F8FF88E000000000000000000000DF
+:2002C0000000000000000000F4FF02DF0000000000000000000091A800002DA90000DDA8B6
+:2002E0000000E2A80000FFFF1ADF00000000FFFF1BDF00000000FFFF1CDF00000000FFFF8E
+:200300001DDF00000000FEFF70D7000000000000FEFF72D7000000000000FEFF74D700000F
+:2003200000000000FEFF76D7000000000000FFFF78D700000000FFFF79D700000000FFFFDA
+:2003400049D700000000FFFF4AD700000000FFFF4BD700000000FFFF4CD700000000FCFF22
+:2003600068D700000000000000000000FCFF0CDC0000000000BF000000BFFFFF10DC0000F3
+:200380000000FEFFAEDD0000B1B90000FEFFB0DD0000B1B90000FEFFB2DD000000000000EB
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diff --git a/bin/ice.map b/bin/ice.map
new file mode 100644
index 0000000..1aa415e
--- /dev/null
+++ b/bin/ice.map
@@ -0,0 +1,34 @@
+********************************************************************************
+TMS320C2000 Hex Converter v5.2.1
+********************************************************************************
+
+INPUT FILE NAME:
+OUTPUT FORMAT: Binary
+
+PHYSICAL MEMORY PARAMETERS
+ Default data width : 16
+ Default memory width : 8 (LS-->MS)
+ Default output width : 8
+
+BOOT LOADER PARAMETERS
+ Table Type: SERIAL PORT (SCI 8 bit Mode)
+ Entry Point: 0x0000b841
+
+
+OUTPUT TRANSLATION MAP
+--------------------------------------------------------------------------------
+00000000..003fffff Page=0 Memory Width=8 ROM Width=8
+--------------------------------------------------------------------------------
+ OUTPUT FILES: D:\project2833\GIT\ICE_22220_1\bin\ice.bin [b0..b7]
+
+ CONTENTS: 00000000..00007a1d BOOT TABLE
+ .cinit : dest=0000b9bd size=000001e1 width=00000002
+ .text : dest=00008000 size=000039bd width=00000002
+ ramfuncs : dest=0000c12e size=0000002b width=00000002
+ .econst : dest=0000c000 size=00000103 width=00000002
+ .switch : dest=0000c15a size=00000028 width=00000002
+
+--------------------------------------------------------------------------------
+00000000..003fffff Page=1 Memory Width=8 ROM Width=8 "*DEFAULT PAGE 1*"
+--------------------------------------------------------------------------------
+ NO CONTENTS
diff --git a/bin/ice.out b/bin/ice.out
new file mode 100644
index 0000000..91a7613
Binary files /dev/null and b/bin/ice.out differ
diff --git a/doc/ICE data stru.xls b/doc/ICE data stru.xls
new file mode 100644
index 0000000..e2bd8a0
Binary files /dev/null and b/doc/ICE data stru.xls differ
diff --git a/doc/Рнструкция РїРѕ калибровке РЈРљРЎР.docx b/doc/Рнструкция РїРѕ калибровке РЈРљРЎР.docx
new file mode 100644
index 0000000..3ab354c
Binary files /dev/null and b/doc/Рнструкция РїРѕ калибровке РЈРљРЎР.docx differ
diff --git a/ecan.c b/ecan.c
new file mode 100644
index 0000000..19fd0d0
--- /dev/null
+++ b/ecan.c
@@ -0,0 +1,354 @@
+#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
+#include "DSP2833x_SWPrioritizedIsrLevels.h"
+
+#include "filter_bat2.h"
+#include "measure.h"
+#include "package.h" // DSP281x Headerfile Include File
+#include "peripher.h" // DSP281x Headerfile Include File
+
+#include "ecan.h" // DSP281x Headerfile Include File
+#include "tools.h" // DSP281x Headerfile Include File
+
+#include "RS485.h"
+#include "message.h"
+
+
+// Prototype statements for functions found within this file.
+interrupt void CANa_handler(void);
+interrupt void CANa_reset_err(void);
+interrupt void CANb_handler(void);
+interrupt void CANb_reset_err(void);
+
+// Global variable for this example
+Uint32 ErrorCount;
+Uint32 MessageReceivedCount;
+Uint32 MessageTransivedCount=0;
+
+Uint32 TestMbox1 = 0;
+Uint32 TestMbox2 = 0;
+Uint32 TestMbox3 = 0;
+
+int CanTimeOutErrorTR = 0;
+
+int wait=0;
+
+void Init_Can(int Port, int DevNum)
+{
+ struct ECAN_REGS ECanShadow;
+
+ volatile struct ECAN_REGS * ECanRegs;
+ volatile struct ECAN_MBOXES * ECanMboxes;
+ volatile struct MOTO_REGS * ECanMOTORegs;
+
+ long id = 0x801CE000;
+
+ if(DevNum<0)DevNum=0;
+ if(DevNum>15)DevNum=15;
+
+// Configure CAN pins using GPIO regs here
+ EALLOW;
+
+ if(!Port)
+ {
+ ECanRegs = &ECanaRegs;
+ ECanMboxes = &ECanaMboxes;
+ ECanMOTORegs = &ECanaMOTORegs;
+
+ GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1;
+ GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1;
+ }
+ else
+ {
+ ECanRegs = &ECanbRegs;
+ ECanMboxes = &ECanbMboxes;
+ ECanMOTORegs = &ECanbMOTORegs;
+
+ GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 2;
+ GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 2;
+ }
+
+// Configure the eCAN RX and TX pins for eCAN transmissions
+ ECanRegs->CANTIOC.all = 8; // only 3rd bit, TXFUNC, is significant
+ ECanRegs->CANRIOC.all = 8; // only 3rd bit, RXFUNC, is significant
+
+// Specify that 8 bits will be sent/received
+ ECanMboxes->MBOX0.MSGCTRL.all = 0x00000008;
+ ECanMboxes->MBOX1.MSGCTRL.all = 0x00000008;
+ ECanMboxes->MBOX2.MSGCTRL.all = 0x00000008;
+
+// Disable all Mailboxes
+// Required before writing the MSGIDs
+ ECanRegs->CANME.all = 0;
+
+// задаем адрес 0 ащикa на передачу
+ ECanMboxes->MBOX0.MSGID.all = id + DevNum;
+
+// задаем адрес 1 ащикa на прием
+ ECanMboxes->MBOX1.MSGID.all = id + 0x20 + DevNum;
+
+// задаем адрес 2 ащикa на прием
+ ECanMboxes->MBOX2.MSGID.all = id + 0x30 + (DevNum&1);
+
+// задаем режимы работы ащикa 0 на передачу, остальные на прием
+ ECanRegs->CANMD.all = 0xFFFFFFFE;
+
+// выбираем только 3 ащикa дла работы, остальные запрещаем
+ ECanRegs->CANME.all = 0x00000007;
+
+// Clear all TAn bits
+ ECanRegs->CANTA.all = 0xFFFFFFFF;
+// Clear all RMPn bits
+ ECanRegs->CANRMP.all = 0xFFFFFFFF;
+// Clear all interrupt flag bits
+ ECanRegs->CANGIF0.all = 0xFFFFFFFF;
+ ECanRegs->CANGIF1.all = 0xFFFFFFFF;
+// Clear all error and status bits
+ ECanRegs->CANES.all=0xffffffff;
+
+// Request permission to change the configuration registers
+ ECanShadow.CANMC.all = 0;
+ ECanShadow.CANMC.bit.MBCC = 1; // Mailbox timestamp counter clear bit
+ ECanShadow.CANMC.bit.TCC = 1; // Time stamp counter MSB clear bit
+ ECanShadow.CANMC.bit.SCB = 1; // eCAN mode (reqd to access 32 mailboxes)
+ ECanShadow.CANMC.bit.WUBA = 1; // Wake up on bus activity
+ ECanShadow.CANMC.bit.ABO = 1; // Auto bus on
+ ECanShadow.CANMC.bit.CCR = 1;
+// ECanShadow.CANMC.bit.STM = 1; // self-test loop-back
+ ECanRegs->CANMC.all = ECanShadow.CANMC.all;
+ while(!ECanRegs->CANES.bit.CCE); // Wait for CCE bit to be set..
+
+// настриваем скорость CAN
+ ECanShadow.CANBTC.all = ECanRegs->CANBTC.all;
+ ECanShadow.CANBTC.bit.SJWREG=1;
+ ECanShadow.CANBTC.bit.BRPREG = (CLKMULT * 3) - 1;
+ ECanShadow.CANBTC.bit.TSEG1REG = 15;
+ ECanShadow.CANBTC.bit.TSEG2REG = 2;
+
+ ECanRegs->CANBTC.all = ECanShadow.CANBTC.all;
+ ECanShadow.CANMC.bit.CCR = 0; // Set CCR = 0
+ ECanRegs->CANMC.all = ECanShadow.CANMC.all;
+ while(ECanRegs->CANES.bit.CCE); // Wait for CCE bit to be cleared..
+
+// задаем таймауты дла ожиданиа отправки получениа посылки
+ ECanMOTORegs->MOTO0 = 550000;
+ ECanMOTORegs->MOTO1 = 550000;
+
+ ECanRegs->CANTOC.all = 1;
+ ECanRegs->CANTOS.all = 0; // clear all time-out flags
+ ECanRegs->CANTSC = 0; // clear time-out counter
+
+ ECanShadow.CANGIM.all = 0;
+
+ ECanRegs->CANMIM.all = 2+4; // Enable interrupts of box 1
+ ECanRegs->CANMIL.all = 0x00000000; // All mailbox interrupts are generated on interrupt line 0.
+ ECanShadow.CANGIM.bit.I0EN = 1;
+
+ ECanShadow.CANGIM.bit.MTOM = 1;
+ ECanShadow.CANGIM.bit.I1EN = 1;
+ ECanShadow.CANGIM.bit.GIL = 1;
+ ECanRegs->CANGIM.all = ECanShadow.CANGIM.all;
+
+ if(!Port)
+ {
+ PieVectTable.ECAN0INTA = &CANa_handler;
+ PieCtrlRegs.PIEIER9.bit.INTx5=1; // PIE Group 9, INT6
+ PieVectTable.ECAN1INTA = &CANa_reset_err;
+ PieCtrlRegs.PIEIER9.bit.INTx6=1; // PIE Group 9, INT6
+ }
+ else
+ {
+ PieVectTable.ECAN0INTB = &CANb_handler;
+ PieCtrlRegs.PIEIER9.bit.INTx7=1; // PIE Group 9, INT6
+ PieVectTable.ECAN1INTB = &CANb_reset_err;
+ PieCtrlRegs.PIEIER9.bit.INTx8=1; // PIE Group 9, INT6
+ }
+ IER |= M_INT9; // Enable CPU INT
+
+ EDIS;
+
+// завершили настройку CAN ащиков
+
+ MessageReceivedCount = 0;
+ ErrorCount = 0;
+ CanTimeOutErrorTR=0;
+ MessageTransivedCount=0;
+}
+
+void CAN_send(int Port, int data[], int Addr)
+{
+ unsigned long hiword,loword;
+ volatile struct ECAN_REGS * ECanRegs;
+ volatile struct ECAN_MBOXES * ECanMboxes;
+
+ if(!Port)
+ {
+ ECanRegs = &ECanaRegs;
+ ECanMboxes = &ECanaMboxes;
+ }
+ else
+ {
+#ifdef TUBER
+ ECanRegs = &ECanbRegs;
+ ECanMboxes = &ECanbMboxes;
+#endif
+ }
+
+ if(wait)
+ if(!(ECanRegs->CANTA.all & 1))
+ if(!(ECanRegs->CANAA.all & 1))
+ return;
+
+ ECanRegs->CANTA.all = 1;
+ ECanRegs->CANAA.all = 1;
+
+ hiword= ((((Uint32) Addr ) & 0xffff)<<16)| 0xE0000000 |
+ ((((Uint32)data[Addr ]) & 0xffff) );
+ loword= ((((Uint32)data[Addr+1]) & 0xffff)<<16)|
+ ((((Uint32)data[Addr+2]) & 0xffff) );
+
+ ECanMboxes->MBOX0.MDH.all = hiword;
+ ECanMboxes->MBOX0.MDL.all = loword;
+
+ EALLOW;
+ ECanRegs->CANTSC = 0; // clear time-out counter
+ EDIS;
+
+ ECanRegs->CANTRS.all = 1; // запустить передачу
+
+ wait=1;
+
+ if(Desk==dsk_COMM) GpioDataRegs.GPBTOGGLE.bit.GPIO52=1;
+ if(Desk==dsk_ISOL) GpioDataRegs.GPATOGGLE.bit.GPIO27=1;
+ if(Desk==dsk_SHKF) GpioDataRegs.GPBTOGGLE.bit.GPIO63=1;
+// led1_toggle();
+}
+
+
+void Handlai(volatile struct MBOX * ECanMbox)
+{
+ unsigned int adr;
+ unsigned int bit[3];
+ unsigned long hiword,loword;
+ int Data[3];
+
+ hiword = ECanMbox->MDH.all;
+ loword = ECanMbox->MDL.all;
+
+ adr = (hiword >> 16);
+
+ bit[0] = adr & 0x8000;
+ bit[1] = adr & 0x4000;
+ bit[2] = adr & 0x2000;
+
+ adr &= 0x1fff;
+
+ Data[0] = (hiword ) & 0xffff;
+ Data[1] = (loword>>16) & 0xffff;
+ Data[2] = (loword ) & 0xffff;
+
+ if(bit[0]) if(adr < ANSWER_LEN) Modbus[adr].all = Data[0]; adr++;
+ if(bit[1]) if(adr < ANSWER_LEN) Modbus[adr].all = Data[1]; adr++;
+ if(bit[2]) if(adr < ANSWER_LEN) Modbus[adr].all = Data[2];
+
+ if(Desk==dsk_COMM) GpioDataRegs.GPBTOGGLE.bit.GPIO49=1;
+ else
+ led2_toggle();
+}
+
+interrupt void CANa_handler(void)
+{
+ unsigned long mask=1;
+ int box;
+
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
+ IER |= M_INT9;
+ IER &= MINT9; // Set "global" priority
+ PieCtrlRegs.PIEIER9.all &= MG95; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ box = ECanaRegs.CANGIF0.bit.MIV0;
+ mask <<= box;
+ ECanaRegs.CANRMP.all = mask;
+
+ Handlai(&ECanaMboxes.MBOX0 + box);
+
+ PieCtrlRegs.PIEACK.bit.ACK9 |= 1;
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER9.all = TempPIEIER;
+}
+
+interrupt void CANa_reset_err(void)
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
+ IER |= M_INT9;
+ IER &= MINT9; // Set "global" priority
+ PieCtrlRegs.PIEIER9.all &= MG96; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ ECanaRegs.CANTRR.all = 1;
+ CanTimeOutErrorTR++;
+
+ PieCtrlRegs.PIEACK.bit.ACK9 |= 1;
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER9.all = TempPIEIER;
+}
+
+interrupt void CANb_handler(void)
+{
+#ifdef TUBER
+ unsigned long mask=1;
+ int box;
+
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
+ IER |= M_INT9;
+ IER &= MINT9; // Set "global" priority
+ PieCtrlRegs.PIEIER9.all &= MG97; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ box = ECanbRegs.CANGIF0.bit.MIV0;
+ mask <<= box;
+ ECanbRegs.CANRMP.all = mask;
+
+ Handlai(&ECanbMboxes.MBOX0 + box);
+
+ PieCtrlRegs.PIEACK.bit.ACK9 |= 1;
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER9.all = TempPIEIER;
+#endif
+}
+
+interrupt void CANb_reset_err(void)
+{
+#ifdef TUBER
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
+ IER |= M_INT9;
+ IER &= MINT9; // Set "global" priority
+ PieCtrlRegs.PIEIER9.all &= MG98; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ ECanbRegs.CANTRR.all = 1;
+ CanTimeOutErrorTR++;
+
+ PieCtrlRegs.PIEACK.bit.ACK9 |= 1;
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER9.all = TempPIEIER;
+#endif
+}
+
+//===========================================================================
+// No more.
+//===========================================================================
diff --git a/ecan.h b/ecan.h
new file mode 100644
index 0000000..b9bd676
--- /dev/null
+++ b/ecan.h
@@ -0,0 +1,3 @@
+void Init_Can(int Port, int DevNum);
+void CAN_send(int Port, int data[], int Addr);
+extern int CAN_input_data[];
diff --git a/filter_bat2.c b/filter_bat2.c
new file mode 100644
index 0000000..a577836
--- /dev/null
+++ b/filter_bat2.c
@@ -0,0 +1,19 @@
+#include "filter_bat2.h"
+
+float filterbat(FILTERBAT *b, float InpVarCurr)
+{
+ float y;
+
+ y = (b->k_0 * (InpVarCurr + (b->i_0*2) + b->i_1)) +
+ (b->k_1 * b->u_0) + (b->k_2 * b->u_1);
+
+ b->u_1=b->u_0;
+ b->u_0=y;
+ b->i_1=b->i_0;
+ b->i_0=InpVarCurr;
+
+ return y;
+}
+
+
+
diff --git a/filter_bat2.h b/filter_bat2.h
new file mode 100644
index 0000000..a9ed52d
--- /dev/null
+++ b/filter_bat2.h
@@ -0,0 +1,49 @@
+#ifndef _FILTER_BAT2
+#define _FILTER_BAT2
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define K1_FILTER_BATTER2_1HZ 0.0000096
+#define K2_FILTER_BATTER2_1HZ 1.94468056
+#define K3_FILTER_BATTER2_1HZ -0.94471895
+
+#define K1_FILTER_BATTER2_3HZ 0.00008766
+#define K2_FILTER_BATTER2_3HZ 1.97347532
+#define K3_FILTER_BATTER2_3HZ -0.97382594
+
+#define K1_FILTER_BATTER2_5HZ 0.00024135
+#define K2_FILTER_BATTER2_5HZ 1.95581276
+#define K3_FILTER_BATTER2_5HZ -0.95677816
+
+#define K1_FILTER_BATTER2_10HZ 0.00094411
+#define K2_FILTER_BATTER2_10HZ 1.91126422
+#define K3_FILTER_BATTER2_10HZ -0.91504065
+
+typedef struct { float k_0;
+ float k_1;
+ float k_2;
+ float i_0;
+ float i_1;
+ float i_2;
+ float u_0;
+ float u_1;
+ float u_2;
+ } FILTERBAT;
+
+
+#define DEF_FILTERBAT { K1_FILTER_BATTER2_5HZ, \
+ K2_FILTER_BATTER2_5HZ, \
+ K3_FILTER_BATTER2_5HZ, \
+ 0,0,0,0,0,0}
+
+float filterbat(FILTERBAT *b, float InpVarCurr);
+
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _FILTER_BAT2 */
+
diff --git a/i2c.c b/i2c.c
new file mode 100644
index 0000000..c39b484
--- /dev/null
+++ b/i2c.c
@@ -0,0 +1,142 @@
+#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
+#include "i2c.h" // Device Headerfile and Examples Include File
+
+void InitI2CGpio()
+{
+
+ EALLOW;
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled disabled by the user.
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+
+ GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up for GPIO32 (SDAA)
+ GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up for GPIO33 (SCLA)
+
+/* Set qualification for selected pins to asynch only */
+// This will select asynch (no qualification) for the selected pins.
+// Comment out other unwanted lines.
+
+ GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // Asynch input GPIO32 (SDAA)
+ GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input GPIO33 (SCLA)
+
+/* Configure SCI pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be I2C functional pins.
+// Comment out other unwanted lines.
+
+ GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; // Configure GPIO32 for SDAA operation
+ GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1; // Configure GPIO33 for SCLA operation
+
+ EDIS;
+}
+
+
+void I2CA_Init(void)
+{
+ InitI2CGpio();
+
+// Initialize I2C
+ I2caRegs.I2CSAR = 0x0050; // Slave address - EEPROM control code
+
+ I2caRegs.I2CMDR.bit.IRS = 0; // IPSC must be initialized while the I2C module is in reset (IRS = 0 in I2CMDR).
+ #if (CPU_FRQ_150MHZ) // Default - For 150MHz SYSCLKOUT
+ I2caRegs.I2CPSC.all = 14; // Prescaler - need 7-12 Mhz on module clk (150/15 = 10MHz)
+ #endif
+ #if (CPU_FRQ_100MHZ) // For 100 MHz SYSCLKOUT
+ I2caRegs.I2CPSC.all = 9; // Prescaler - need 7-12 Mhz on module clk (100/10 = 10MHz)
+ #endif
+
+ I2caRegs.I2CCLKL = 10; // NOTE: must be non zero
+ I2caRegs.I2CCLKH = 5; // NOTE: must be non zero
+
+ I2caRegs.I2CMDR.all = 0x0000;
+
+ I2caRegs.I2CMDR.bit.MST = 1;
+
+ I2caRegs.I2CMDR.bit.IRS = 1; // Take I2C out of reset
+ // Stop I2C when suspended
+ return;
+}
+
+
+Uint16 I2CA_WriteData(unsigned int Addr, int Data)
+{
+
+// Wait until the STP bit is cleared from any previous master communication.
+// Clearing of this bit by the module is delayed until after the SCD bit is
+// set. If this bit is not checked prior to initiating a new message, the
+// I2C could get confused.
+ if (I2caRegs.I2CMDR.bit.STP == 1)
+ {
+ return I2C_STP_NOT_READY_ERROR;
+ }
+
+// Check if bus busy
+ if (I2caRegs.I2CSTR.bit.BB == 1)
+ {
+ return I2C_BUS_BUSY_ERROR;
+ }
+
+// Setup number of bytes to send
+// MsgBuffer + Address
+ I2caRegs.I2CCNT = 4;
+
+// Send start as master transmitter
+ I2caRegs.I2CMDR.all = 0x6E20;
+
+// Setup data to send
+ I2caRegs.I2CDXR = (Addr*2)>>8;
+ while(!I2caRegs.I2CSTR.bit.XRDY);
+ I2caRegs.I2CDXR = (Addr*2);
+ while(!I2caRegs.I2CSTR.bit.XRDY);
+ I2caRegs.I2CDXR = Data>>8;
+ while(!I2caRegs.I2CSTR.bit.XRDY);
+ I2caRegs.I2CDXR = Data;
+ while(!I2caRegs.I2CSTR.bit.XRDY);
+ while(I2caRegs.I2CMDR.bit.STP == 1);
+ while(I2caRegs.I2CSTR.bit.BB == 1);
+
+ return I2C_SUCCESS;
+}
+
+
+int I2CA_ReadData(unsigned int Addr)
+{
+ WORDE data;
+
+// Wait until the STP bit is cleared from any previous master communication.
+// Clearing of this bit by the module is delayed until after the SCD bit is
+// set. If this bit is not checked prior to initiating a new message, the
+// I2C could get confused.
+ if (I2caRegs.I2CMDR.bit.STP == 1)
+ {
+ return I2C_STP_NOT_READY_ERROR;
+ }
+
+// Check if bus busy
+ if (I2caRegs.I2CSTR.bit.BB == 1)
+ {
+ return I2C_BUS_BUSY_ERROR;
+ }
+
+ I2caRegs.I2CCNT = 2;
+ I2caRegs.I2CMDR.all = 0x6E20; // Send data to setup EEPROM address 0x6620
+ I2caRegs.I2CDXR = (Addr*2)>>8;
+ while(!I2caRegs.I2CSTR.bit.XRDY);
+ I2caRegs.I2CDXR = (Addr*2);
+ while(I2caRegs.I2CMDR.bit.STP == 1);
+
+ I2caRegs.I2CCNT = 2;
+ I2caRegs.I2CMDR.all = 0x6C20; // Send restart as master receiver
+
+ while(!I2caRegs.I2CSTR.bit.RRDY);
+ data.byt.byte_1 = I2caRegs.I2CDRR;
+ while(!I2caRegs.I2CSTR.bit.RRDY);
+ data.byt.byte_0 = I2caRegs.I2CDRR;
+
+ return data.all;
+}
+
+//===========================================================================
+// No more.
+//===========================================================================
diff --git a/i2c.h b/i2c.h
new file mode 100644
index 0000000..d358a9e
--- /dev/null
+++ b/i2c.h
@@ -0,0 +1,4 @@
+void I2CA_Init(void);
+Uint16 I2CA_WriteData(unsigned int Addr, int Data);
+int I2CA_ReadData(unsigned int Addr);
+
diff --git a/ice.pjt b/ice.pjt
new file mode 100644
index 0000000..7dcd130
--- /dev/null
+++ b/ice.pjt
@@ -0,0 +1,70 @@
+; Code Composer Project File, Version 2.0 (do not modify or remove this line)
+
+[Project Settings]
+ProjectDir="D:\projects\Dimas\ICE_19_03_2018\"
+ProjectType=Executable
+CPUFamily=TMS320C28XX
+Tool="Compiler"
+Tool="CustomBuilder"
+Tool="DspBiosBuilder"
+Tool="Linker"
+Config="Debug"
+Config="Release"
+
+[Source Files]
+Source="ADC.c"
+Source="bios.c"
+Source="cntrl_adr.c"
+Source="crc16.c"
+Source="ecan.c"
+Source="filter_bat2.c"
+Source="i2c.c"
+Source="isolatio.c"
+Source="main.c"
+Source="measure.c"
+Source="message.c"
+Source="peripher.c"
+Source="RS485.c"
+Source="spise2p.c"
+Source="tools.c"
+Source="v120\DSP2833x_common\source\DSP2833x_Adc.c"
+Source="v120\DSP2833x_common\source\DSP2833x_ADC_cal.asm"
+Source="v120\DSP2833x_common\source\DSP2833x_CpuTimers.c"
+Source="v120\DSP2833x_common\source\DSP2833x_PieCtrl.c"
+Source="v120\DSP2833x_common\source\DSP2833x_SWPrioritizedDefaultIsr.c"
+Source="v120\DSP2833x_common\source\DSP2833x_SWPrioritizedPieVect.c"
+Source="v120\DSP2833x_common\source\DSP2833x_SysCtrl.c"
+Source="v120\DSP2833x_common\source\DSP2833x_usDelay.asm"
+Source="v120\DSP2833x_common\source\DSP2833x_Xintf.c"
+Source="v120\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c"
+Source="F28335.cmd"
+Source="v120\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd"
+
+["Debug" Settings]
+FinalBuildCmd=$(Proj_dir)\bin\hex2000.exe $(Proj_dir)\bin\ice.out -boot -sci8 -map $(Proj_dir)\bin\ice.map -o $(Proj_dir)\bin\ice.hex -i
+FinalBuildCmd=$(Proj_dir)\bin\hex2000.exe $(Proj_dir)\bin\ice.out -boot -sci8 -map $(Proj_dir)\bin\ice.map -o $(Proj_dir)\bin\ice.bin -b
+
+["Compiler" Settings: "Debug"]
+Options=-g -pdsw225 -o0 -fr"$(Proj_dir)\Debug" -fs"$(Proj_dir)\Asm" -i"$(Proj_dir)\v120\DSP2833x_headers\include" -i"$(Proj_dir)\v120\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32
+
+["Compiler" Settings: "Release"]
+Options=-pdsw225 -o3 -fr"$(Proj_dir)\Release" -d"LARGE_MODEL" -ml -v28
+
+["Linker" Settings: "Debug"]
+Options=-c -e_c_int00 -m".\Debug\ice.map" -o".\bin\ice.out" -stack0x3f0 -w -x -l"rts2800_fpu32.lib"
+
+["Linker" Settings: "Release"]
+Options=-c -m".\Release\UKSS745.1TMS320F28335.map" -o".\Release\UKSS745.1TMS320F28335.out" -w -x
+
+["F28335.cmd" Settings: "Debug"]
+LinkOrder=1
+
+["F28335.cmd" Settings: "Release"]
+LinkOrder=1
+
+["v120\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" Settings: "Debug"]
+LinkOrder=2
+
+["v120\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" Settings: "Release"]
+LinkOrder=1
+
diff --git a/isolatio.c b/isolatio.c
new file mode 100644
index 0000000..62fbb22
--- /dev/null
+++ b/isolatio.c
@@ -0,0 +1,268 @@
+#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
+#include "DSP2833x_SWPrioritizedIsrLevels.h"
+
+#include "RS485.h"
+#include "filter_bat2.h"
+#include "measure.h"
+#include "message.h"
+#include "package.h"
+#include "peripher.h"
+#include "crc16.h"
+#include "isolatio.h"
+#include // Это чтобы мерить амплитуду! sqrt без этого будет крив!!!
+
+OPTOCANAL opt[2];
+
+ISOLATION iso[2];
+
+float iso_KOEF[2] = {-0.5, -0.5};
+
+void init_isolation_struct(void);
+
+void DCLK(int i, int x)
+{
+ x=!x;
+
+ if(i)
+ {
+ if(x) GpioDataRegs.GPASET.bit.GPIO26=1;
+ else GpioDataRegs.GPACLEAR.bit.GPIO26=1;
+ }
+ else
+ {
+ if(x) GpioDataRegs.GPBSET.bit.GPIO32=1;
+ else GpioDataRegs.GPBCLEAR.bit.GPIO32=1;
+} }
+
+int DIN(int i)
+{
+ if(i) return !GpioDataRegs.GPBDAT.bit.GPIO52;
+ else return !GpioDataRegs.GPADAT.bit.GPIO23;
+}
+
+void BLIN(int i)
+{
+ if(i) GpioDataRegs.GPBTOGGLE.bit.GPIO53=1;
+ else GpioDataRegs.GPATOGGLE.bit.GPIO24=1;
+}
+
+interrupt void cpu_timer1_isr_ISOL(void)
+{
+ ERROR error;
+ float Riso=0;
+ long numb=0;
+ int i;
+ static unsigned int count_ready=0;
+
+ EALLOW;
+ CpuTimer1.InterruptCount++;
+ IER |= MINT13; // Set "global" priority
+ EINT;
+ EDIS; // This is needed to disable write to EALLOW protected registers
+
+ if(!cReset) ServiceDog();
+
+ if(++CanPowse >= CANPOWSE*2)
+ {
+ CanPowse = 0;
+ CanGO = 1;
+ }
+
+ if(++count_ready >= period_ready)
+ {
+ count_ready=0;
+
+ if((!sig.bit.Error)|(cTestLamp)) toggle_READY();
+ else set_READY();
+ }
+
+ for(i=0;i<2;i++)
+ {
+ iso[i].pause_counter++;
+
+ if(sens_error[i].bit.Bypas)
+ {
+ sens_error[i].all = 0;
+ sens_error[i].bit.Bypas = 1;
+ Modbus[i+DATASTART].all = 0;
+ continue;
+ }
+
+ if(opt[i].Wait)
+ {
+ opt[i].Wait--;
+ opt[i].bit = 0;
+ opt[i].clk = 0;
+ DCLK(i,0);
+ continue;
+ }
+
+ opt[i].clk=!opt[i].clk;
+ DCLK(i,opt[i].clk);
+ if(!opt[i].clk)
+ {
+ opt[i].Numb = (opt[i].Numb<<1) | DIN(i);
+ if(++opt[i].bit>=32)
+ {
+ error.all = 0;
+
+ opt[i].Wait = (TELE_FREQ/1000)*optopowse;
+ opt[!i].Wait =(TELE_FREQ/2000)*optopowse;
+ if(get_crc32(&(opt[i].Numb)))
+ {
+ numb = opt[i].Numb;
+ numb = numb / 256; // удалаем контрольную сумму
+
+ Riso=numb;
+/*
+ if(ist[i]) { kff=1; ist[i]=0; }
+ else kff = optofiltr;
+ fRiso[i] += (Riso-fRiso[i])/kff;
+ numb = (long)fRiso[i];
+*/
+ Modbus[i*2+0x10].all = (int)(numb & 0xFFFF);
+ Modbus[i*2+0x11].all = (int)(numb>>16);
+
+ Riso=numb;
+ Riso = Riso/1024;//256; // предположим
+
+ iso[i].adc_value = Riso; // на Лешин алгоритм
+
+ Modbus[i+DATASTART].all = Riso; // какбе
+ opt[i].ers = 0; BLIN(i);
+ }
+ else
+ {
+ if(++opt[i].ers > 20)
+ {
+ opt[i].ers = 20;
+ error.bit.Tear = 1;
+ } }
+
+ reset_errs(i,error);
+
+ } } }
+
+ sig.all = chk.all;
+ chk.all = 0;
+
+}
+void timer_Init()
+{
+ EALLOW; // This is needed to write to EALLOW protected registers
+ PieVectTable.XINT13 = &cpu_timer1_isr_ISOL;
+ EDIS; // This is needed to disable write to EALLOW protected registers
+
+ ConfigCpuTimer(&CpuTimer1, SYSCLKOUT/1000000, 1000000/TELE_FREQ);
+ CpuTimer1Regs.TCR.all = 0x4020; // Use write-only instruction to set TSS bit = 0
+ IER |= M_INT13;
+
+ period_ready = TELE_FREQ / (READY_FREQ * 2);
+
+ init_isolation_struct();
+ Calcul_Iso_Koef();
+}
+
+////////////////////////////////////////////////////////////////////////////////////////////
+
+void Calcul_Iso_Koef()
+{
+ iso_KOEF[0] = (isoMOM[1]-isoMOM[0]);
+ iso_KOEF[0]/= (isoADC[1]-isoADC[0]);
+
+ iso_KOEF[1] = (isoMOM[3]-isoMOM[2]);
+ iso_KOEF[1]/= (isoADC[3]-isoADC[2]);
+}
+
+void init_isolation_struct(void)
+{
+ int i;
+ int* pint = (int*)iso;
+ int size = sizeof(ISOLATION)/sizeof(int);
+
+ for(i=0; i < size*2; i++) pint[i] = 0;
+
+ iso[1].pause_counter = ISO_PAUSE / 2;
+}
+
+#define iso_time_pause 6200
+
+void isolation_calc(void)
+{
+ float our_delta;
+ static int i;
+ int k, l, m;
+ int buff[BUFF_LEN];
+
+ for(i=0; i<2; i++)
+
+ if(iso[i].pause_counter > ISO_PAUSE) //Поскольку всё медленно, сохранаю значениа раз 3 секунды
+ { //чтобы немьше отсчётов попадало, навыбросы
+ iso[i].pause_counter = 0;
+
+ iso[i].buff[iso[i].buff_position] = iso[i].adc_value;
+
+// Это идет сортировка всего массива данных ---------------------------
+
+ for (k = 0; k < BUFF_LEN; k++) buff[k] = 0x8000; //minimal int
+ for (k = 0; k <=iso[i].prim_position; k++)
+ {
+ for (l = 0; (l < BUFF_LEN) && (iso[i].buff[k] < buff[l]); l++);
+ if (l < BUFF_LEN)
+ {
+ for (m = BUFF_LEN - 1; (m > l) && (m > 0); m--) buff[m] = buff[m-1];
+ buff[l] = iso[i].buff[k];
+ } }
+
+// -----------------------------------------------------------------------
+
+ m = (buff[0]+buff[iso[i].prim_position])/2;
+
+ for(k=0; k < iso[i].prim_position; k++) if( buff[k] <= m) break;
+
+ iso[i].max_val = buff[k - 1 - iso[i].cycles];
+
+ iso[i].min_val = buff[k + iso[i].cycles];
+
+/* Так было
+ iso[i].max_val = buff[iso[i].cycles];
+ iso[i].min_val = buff[iso[i].prim_position - iso[i].cycles];
+*/
+ our_delta = iso[i].max_val - iso[i].min_val;
+
+
+// Новый алгоритм счета МОмов -------------------------------------------
+
+ if(!iso[i].cycles)
+ iso[i].MOms_x_10 = isoMOM[i*2+1];
+ else
+ iso[i].MOms_x_10 = (our_delta-isoADC[i*2]) * iso_KOEF[i] + isoMOM[i*2];
+
+// ---------------------------------------------------------------------------
+
+Modbus[26+i].all = iso[i].MOms_x_10;
+Modbus[32+i].all = iso[i].adc_value;
+Modbus[40+i].all = iso[i].max_val;
+Modbus[48+i].all = iso[i].min_val;
+Modbus[56+i].all = our_delta;
+Modbus[64+i].all = iso[i].prim_position;
+Modbus[72+i].all = iso[i].buff_position;
+Modbus[80+i].all = iso[i].cycles;
+
+//for(j=0;j<35;j++) Modbus[0x20+j].all = iso[i].buff[j];
+
+// ---------------------------------------------------------------------------
+
+ iso[i].buff_position++;
+
+ if(iso[i].cycles < BUFF_CYCLES)
+ {
+ iso[i].prim_position = iso[i].buff_position;
+ iso[i].cycles = iso[i].prim_position / CYCLE_LEN;
+ }
+ else
+ iso[i].prim_position = BUFF_LEN-1;
+
+ if (iso[i].buff_position >= BUFF_LEN) iso[i].buff_position = 0;
+} }
+
diff --git a/isolatio.h b/isolatio.h
new file mode 100644
index 0000000..10d41a1
--- /dev/null
+++ b/isolatio.h
@@ -0,0 +1,54 @@
+void timer_Init(void);
+int get_isolatio(void);
+
+typedef struct
+{
+ unsigned int clk;
+ unsigned int bit;
+ unsigned int ers;
+ unsigned Wait;
+ unsigned long Numb;
+
+} OPTOCANAL;
+
+
+// примерно 105 секунд - полный цикл измерениа сопротивлениа изолации, зарад конденсатора туда сюда
+#define CYCLE_TIME 105L
+
+// 3 секунды - пауза между измерениами изолации
+#define ISO_TIME 3
+
+// сколько места занимает в буфере один полный цикл
+#define CYCLE_LEN (CYCLE_TIME / ISO_TIME)
+
+// Количество полных циклов в нашем буфере
+#define BUFF_CYCLES 5
+
+// величина буфера дла хранениа измерений, пусть в него влазит несколько полных циклов
+#define BUFF_LEN (CYCLE_LEN * BUFF_CYCLES)
+
+#define TELE_FREQ 2000 // Гц - частота прерываниа
+
+#define ISO_PAUSE (ISO_TIME * TELE_FREQ)
+
+
+typedef struct {
+ int buff[BUFF_LEN];
+ int min_val;
+ int max_val;
+ unsigned int buff_position;
+ unsigned int prim_position;
+ unsigned int cycles;
+ int MOms_x_10;
+ unsigned int pause_counter;
+ int adc_value;
+
+}ISOLATION;
+
+extern ISOLATION iso[];
+
+void isolation_calc(void);
+void Calcul_Iso_Koef(void);
+
+
+
diff --git a/kanal.c b/kanal.c
new file mode 100644
index 0000000..704f829
--- /dev/null
+++ b/kanal.c
@@ -0,0 +1,164 @@
+#include "DSP2833x_Device.h" // DSP281x Headerfile Include File
+#include "DSP2833x_SWPrioritizedIsrLevels.h"
+#include "filter_bat2.h"
+#include "measure.h"
+
+#include "RS485.h"
+#include "message.h"
+#include "kanal.h"
+#include "test.h"
+#include "package.h"
+#include "tools.h"
+
+#include "peripher.h"
+
+int digits[16] = {63,6,91,79,102,109,125,7,127,111,64,0,0,0,121,0};
+
+void DCLK(int x)
+{
+ if(x) GpioDataRegs.GPASET.bit.GPIO6=1;
+ else GpioDataRegs.GPACLEAR.bit.GPIO6=1;
+ DSP28x_usDelay(1L);
+}
+
+void DOUT(int x)
+{
+ if(x) GpioDataRegs.GPASET.bit.GPIO8=1;
+ else GpioDataRegs.GPACLEAR.bit.GPIO8=1;
+ DSP28x_usDelay(1L);
+}
+
+void RESET()
+{
+ DCLK(0); DOUT(1);
+ DCLK(0); DOUT(0);
+}
+
+void SENDBIT(int x)
+{
+ DOUT(x); DCLK(1);
+ DOUT(0); DCLK(0);
+}
+
+void kanal_Send(int adr, long dat, int dot)
+{
+ long Word,data,aliq_part,dg[4];
+ int i,j,bit,byt,addr,sgn=0,punkt=0,aliq_len=0,full_len;
+
+ if(adr>1) // Лампочки
+ {
+ Word =dat;
+ }
+
+ else
+
+ {
+ if(dot<0 || dot>13) // Ошибка: -Е...
+ {
+ dg[3] = 0xA; dg[2] = 0xE;
+ dg[1] = 0xF; dg[0] = 0xF;
+ punkt = 0x7;
+ }
+
+ else
+
+ {
+ if(dat<0) sgn=1;
+ data = labs(dat);
+
+ aliq_part = data;
+ for(i=0;i0)
+ {
+ aliq_len++; dat/=10;
+ }
+
+ if(aliq_len+sgn>4)
+ {
+ if(sgn) dg[3] = 0xA;
+ else dg[3] = 0xF;
+
+ dat = aliq_part;
+ for(i=1;i0;i--)
+ {
+ if((dg[i]==0)&&(i!=dot))
+ dg[i]=0xF; // Это значит пусто
+ else break;
+ }
+
+ if(sgn)
+ for(i=1;i<4;i++)
+ {
+ if( (dg[i]==0xF)||(i==3))
+ {
+ dg[i]=0xA; // Это значит минус
+ break;
+ } } } }
+
+ for(i=0;i<4;i++)
+ {
+ dg[i] = digits[dg[i]];
+ if((punkt>>i)&1) dg[i]+= 128;
+
+ }
+
+ Word = ((dg[0] ) & 0x000000FF) | ((dg[1]<<8 ) & 0x0000FF00) |
+ ((dg[2]<<16) & 0x00FF0000) | ((dg[3]<<24) & 0xFF000000);
+ }
+
+ for (i=0;i<4;i++)
+ {
+ if(addr>0x10) break;
+
+ for (j=0;j<8;j++)
+ {
+ bit = Word & 1; Word >>= 1;
+ SENDBIT(bit);
+ }
+
+ byt = addr;
+ for (j=0;j<6;j++)
+ {
+ bit = byt & 1; byt >>= 1;
+ SENDBIT(bit);
+ }
+ addr++;
+
+ RESET();
+ }
+}
diff --git a/kanal.h b/kanal.h
new file mode 100644
index 0000000..44cb4e7
--- /dev/null
+++ b/kanal.h
@@ -0,0 +1,7 @@
+void kanal_Send(int adr, long dat, int dot);
+
+#define adr_diod1 0x00 // Первые 4 диодных платы
+#define adr_diod2 0x04 // Вторые 4 диодных платы
+#define adr_digg1 0x08 // Первые 4 цифры
+#define adr_digg2 0x0C // Вторые 4 цифры
+#define adr_lamps 0x10 // Лампы
diff --git a/log_to_mem.c b/log_to_mem.c
new file mode 100644
index 0000000..c26404b
--- /dev/null
+++ b/log_to_mem.c
@@ -0,0 +1,34 @@
+/****************************************************************/
+/* TMS320C32 */
+/* ====== BIOS, КЛАИН, КЛВСП ====== */
+/* ЦНИИ СЭТ (с) 1998-2001г. */
+/****************************************************************/
+/* log_to_mem.c
+ ****************************************************************
+ * Запись логов в памyть *
+ ****************************************************************/
+
+#include "log_to_mem.h"
+
+int no_write = 1,
+ never_write = 0; // Флаги, чтобы не писать (если что)
+
+#pragma DATA_SECTION(logs_block,".logg");
+unsigned int logs_block[0xF000];
+
+LOG Log;
+unsigned int flog=0;
+
+// Очищение памати, где логи лежат
+void clear_mem()
+{
+ unsigned long i;
+
+ Log.Start = LOG_PAGE_START;
+ Log.Finis = LOG_PAGE_START + LOG_PAGE_LEN;
+ Log.Adres = Log.Start;
+ Log.Circl = 0;
+
+ for (i=Log.Start; i (Log.Finis - x)) Log.Adres = Log.Start
+
+/* Очистка памати (обнуление) */
+void clear_mem();
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _LOG_TO_MEM */
diff --git a/main.c b/main.c
new file mode 100644
index 0000000..aa8ad0e
--- /dev/null
+++ b/main.c
@@ -0,0 +1,220 @@
+#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
+
+#include "cntrl_adr.h"
+#include "RS485.h"
+#include "BIOS_DSP.h"
+#include "filter_bat2.h"
+#include "measure.h"
+#include "Message.h"
+#include "package.h"
+
+#include "spise2p.h"
+#include "i2c.h"
+
+#include "tools.h"
+#include "peripher.h"
+#include "ADC.h"
+
+#include "ecan.h"
+#include "log_to_mem.h"
+
+#include "measure.h"
+#include "isolatio.h"
+
+extern void DSP28x_usDelay(Uint32 Count);
+
+void main()
+{
+ int i,j,mask;
+ static int cancount[2],cancell[2];
+ RS_DATA * rs;
+
+ InitSysCtrl();
+
+// Disable CPU interrupts and clear all CPU interrupt flags:
+ DINT;
+
+ InitPieCtrl();
+
+ IER = 0x0000;
+ IFR = 0x0000;
+
+ InitPieVectTable();
+
+ init_zone7();
+
+ setup_leds_line();
+ led1_on();
+ led2_off();
+ for (i=0;i<10;i++)
+ {
+ pause_us(50000);
+ led2_toggle();
+ led1_toggle();
+ }
+ led1_off();
+ led2_off();
+
+ get_Mode();
+ set_cntrl_addr(Mode,16);
+ create_uart_vars(sizeof(CMD_TO_TMS));
+ setup_uart(COM_1,115200);
+ setup_uart(COM_2,115200);
+ Init_Can(0,Addrr);
+ Init_Seeprom();
+// clear_mem();
+
+ EnableInterrupts();
+
+ if(Desk!=dsk_ISOL)
+ {
+ setup_adc();
+ Init_sensors();
+ I2CA_Init(); pause_us(500000);
+ Load_caliber();
+ }
+ else
+ {
+// timer_Init();
+ Init_optic();
+ }
+
+ Load_params();
+ Init_packMask();
+
+ if(Desk==dsk_ISOL)
+ {
+ timer_Init();
+// Init_optic();
+ }
+
+
+ LastMode = Addrr;
+
+ for(i=0;i<3;i++)
+ {
+ cancount[i]= 0;
+ cancell[i] = CAN_send_start;
+ }
+
+ EALLOW;
+ SysCtrlRegs.WDCR= 0x2F;
+ EDIS;
+
+ MAY=1;
+
+ while(1)
+ {
+ if(CanGO)
+ {
+ CanGO=0;
+ for(i=0;i<2;i++)
+ if(Cancount[i])
+ if(++cancount[i] >= Cancount[i])
+ if(cancount[0])
+ {
+ cancount[i] = 0;
+ while(1)
+ {
+ if(cancell[i] >= 0x80) cancell[i]=0;
+ mask = Maska[i][cancell[i]/16] >> (cancell[i]%16);
+ if(!mask) cancell[i] = (cancell[i] + 0x10) & 0xFFF0;
+ else
+ {
+ while(!(mask & 1))
+ {
+ cancell[i]++; mask >>= 1;
+ }
+ break;
+ } }
+ CAN_send(0,(int *)Modbus,cancell[i]);
+ cancell[i]+=3;
+ } }
+/*
+ CanGO=0;
+ for(i=0;i<3;i++)
+ {
+ if(cancount[i]) cancount[i]--;
+ else
+ {
+ cancount[i] = Cancount[i]; circ[i] = 0;
+
+ while( !((Maska[i][cancell[i]/16]>>(cancell[i]%16))&1) && circ[i] < 2 )
+ if(cancell[i]>CAN_send_finis)
+ {
+ cancell[i] = CAN_send_start; circ[i]++;
+ }
+ else cancell[i]++;
+
+ if(cancell[i]<=CAN_send_finis && circ[i] < 2)
+ {
+ CAN_send(0,(int *)Modbus,cancell[i]);
+ cancell[i]+=3;
+ } } } }
+*/
+ if(cSaveParam)
+ {
+ cSaveParam=0;
+ Save_params();
+ }
+
+ if(cReadCal)
+ {
+ cReadCal=0;
+ Load_caliber();
+ }
+
+ if(cDefParam)
+ {
+ cDefParam=0;
+ Default_params();
+ }
+
+ if(cKoefCalc)
+ {
+ cKoefCalc=0;
+ Calcul_Iso_Koef();
+ }
+
+ get_Inputs();
+
+ if(Desk!=dsk_SHKF)
+ {
+ Modbus[23].all = Inputs.wrd.word_0;
+ }
+
+ if(Desk==dsk_ISOL)
+ {
+ IsShimON = cShimON;
+ if(!cShimON)
+ isolation_calc();
+ }
+
+ for(i=0;i<2;i++)
+ {
+ if(i) rs = &rs_a;
+ else rs = &rs_b;
+
+ j = get_command(rs);
+
+ if(j!=-1)
+ switch(j)
+ {
+ case CMD_INIT: init(rs); led2_toggle();break; // начальные установки
+ case CMD_INITLOAD: initload(rs); led2_toggle();break; // настройка загрузки
+ case CMD_RUN: run(rs); led2_toggle();break; // загрузить блок
+ case CMD_LOAD: load(rs); led2_toggle();break; // загрузить блок
+ case CMD_PEEK: peek(rs); led2_toggle();break; // прочитать ачейку памати
+ case CMD_POKE: poke(rs); led2_toggle();break; // записать в ачейку памати
+ case CMD_UPLOAD: upload(rs); led2_toggle();break; // передать блок памати
+ case CMD_EXTEND: extendbios(rs); led2_toggle();break; // расширенные команды дла биоса
+
+ case CMD_TFLASH: tflash(rs); led2_toggle();break; // прошить TMS
+
+// case CMD_STD: ReceiveCommand(rs); led2_toggle();break;
+ case CMD_MODBUS_3: ReceiveCommandModbus3(rs); led2_toggle();break;
+ case CMD_MODBUS_6: ReceiveCommandModbus6(rs); led2_toggle();break;
+
+ default: break;
+} } } }
+
diff --git a/measure.c b/measure.c
new file mode 100644
index 0000000..7c846a1
--- /dev/null
+++ b/measure.c
@@ -0,0 +1,673 @@
+#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
+#include "DSP2833x_SWPrioritizedIsrLevels.h"
+#include "filter_bat2.h"
+#include "package.h"
+
+#include "measure.h"
+#include "package.h"
+
+#include "peripher.h"
+#include "ADC.h"
+
+#include "RS485.h"
+#include "message.h"
+#include "log_to_mem.h"
+
+#include // Это чтобы мерить амплитуду! sqrt без этого будет крив!!!
+
+unsigned int CanPowse,CanGO;
+
+int MAX_TPL_CANAL=0; // Количество температурных каналов
+int period_ready, period_blink, period_dac, time_dac;
+
+FLAG chk,sig;
+long time_1_5sec, time_5msec, time_5sec;
+
+long err_count[6];
+float lev_count[6];
+
+int sens_type[24];
+int sens_pair[24];
+long din_count[32];
+
+int adc0[24];
+int tmp0[24];
+float tmpK[24];
+
+FILTERBAT def_FILTERBAT = DEF_FILTERBAT;
+FILTERBAT filter[40];
+
+long sens_count[28];
+
+interrupt void cpu_timer1_isr_SENS(void);
+
+/********************************************************************/
+/* Расчет модула тока из показаний двух фаз */
+/********************************************************************/
+float im_calc(float ia,float ib)
+{
+ float isa,isb;
+
+ isa = - 1.5 * (ia + ib);
+ isb = COSPi6 * (ia - ib);
+ return (2*sqrt(isa*isa+isb*isb)/3);
+}
+
+
+interrupt void cpu_timer1_isr_SENS(void)
+{
+ static unsigned int
+ count_ready=0, count_blink=0, count_bright=0, count_mode,
+ blink_over, blink_alarm, work_lamp, heat_lamp, errr_lamp;
+
+ EALLOW;
+ CpuTimer1.InterruptCount++;
+ IER |= MINT13; // Set "global" priority
+ EINT;
+ EDIS; // This is needed to disable write to EALLOW protected registers
+
+ if(!cReset) ServiceDog();
+
+ if(++count_ready >= period_ready)
+ {
+ count_ready=0;
+
+ if((!sig.bit.Error)|(cTestLamp)) toggle_READY();
+ else set_READY();
+ }
+
+ if(++CanPowse >= CANPOWSE)
+ {
+ CanPowse = 0;
+ CanGO = 1;
+ }
+
+ if(++count_bright == maximum_bright)
+ {
+ count_bright = 0 ;
+
+ if(Desk==dsk_COMM)
+ {
+ if(work_lamp) GpioDataRegs.GPBCLEAR.bit.GPIO60=1;
+ else GpioDataRegs.GPBSET.bit.GPIO60=1;
+ if(heat_lamp) GpioDataRegs.GPBCLEAR.bit.GPIO58=1;
+ else GpioDataRegs.GPBSET.bit.GPIO58=1;
+ if(errr_lamp) GpioDataRegs.GPBCLEAR.bit.GPIO62=1;
+ else GpioDataRegs.GPBSET.bit.GPIO62=1;
+ }
+
+ if(Mode==adr_SHKF)
+ {
+ if(work_lamp) GpioDataRegs.GPBCLEAR.bit.GPIO62=1;
+ else GpioDataRegs.GPBSET.bit.GPIO62=1;
+ } }
+
+ if(count_bright == Brightness)
+ {
+ if(Desk==dsk_COMM)
+ {
+ GpioDataRegs.GPBSET.bit.GPIO60=1;
+ GpioDataRegs.GPBSET.bit.GPIO58=1;
+ GpioDataRegs.GPBSET.bit.GPIO62=1;
+ }
+
+ if(Desk==dsk_SHKF)
+ {
+ GpioDataRegs.GPBSET.bit.GPIO62=1;
+ } }
+
+ if(++count_blink >= period_blink)
+ {
+ count_blink=0;
+ count_mode++;
+ blink_over = (count_mode & 1)?1:0;
+ blink_alarm = (count_mode & 7)?1:0;
+
+ if(cExtLamp)
+ {
+ work_lamp = cExtLite;
+ heat_lamp = cExtLite;
+ errr_lamp = cExtLite;
+ }
+ else
+ {
+ if(cTestLamp)
+ {
+ work_lamp = blink_over;
+ heat_lamp = blink_over;
+ errr_lamp = blink_over;
+ }
+ else
+ {
+ if(Mode==adr_SHKF)
+ {
+ if(sig.bit.Error) work_lamp = blink_over;
+ else work_lamp = 1;
+ }
+ else
+ {
+ if(sig.bit.Error) work_lamp = 0;//blink_over;
+// else if(sig.bit.Alarm) work_lamp = blink_alarm;
+ else work_lamp = 1;
+
+ if(sig.bit.OverHeat) heat_lamp = 1;
+ else if(sig.bit.SubHeat) heat_lamp = blink_over;
+ else if(sig.bit.OutHeat) heat_lamp = !blink_alarm;
+ else heat_lamp = 0;
+} } } } }
+
+void Init_optic()
+{
+ int i;
+
+ for(i=0;i<24;i++)
+ {
+ sens_type[i]=0;
+ sens_pair[i]=i;
+ }
+
+// sens_type[2] = OPTIC;
+// sens_type[3] = OPTIC;
+}
+
+void Init_sensors()
+{
+ int i;
+
+ EALLOW; // This is needed to write to EALLOW protected registers
+ PieVectTable.XINT13 = &cpu_timer1_isr_SENS;
+ EDIS; // This is needed to disable write to EALLOW protected registers
+
+ ConfigCpuTimer(&CpuTimer1, (SYSCLKOUT/1000000), 1000000/SIG_FREQ);
+ CpuTimer1Regs.TCR.all = 0x4020; // Use write-only instruction to set TSS bit = 0
+ IER |= M_INT13;
+
+ period_ready = SIG_FREQ / (READY_FREQ * 2);
+ period_blink = SIG_FREQ / (BLINK_FREQ * 2);
+
+ period_dac = SIG_FREQ / (DAC_FREQ);
+ time_dac = LOAD_TIME * DAC_FREQ;
+
+ time_1_5sec = (3 * ADC_FREQ) / 2;
+ time_5msec = (5 * ADC_FREQ) / 1000;
+ time_5sec = (5 * ADC_FREQ);
+
+ for(i=0;i<24;i++)
+ {
+ sens_type[i]=0;
+ sens_pair[i]=i;
+ }
+
+ if((Mode==adr_REC1)||(Mode==adr_REC2))
+ {
+ sens_type[0]=TERMO_AD;
+ sens_type[1]=TERMO_AD;
+ sens_type[2]=TERMO_AD;
+ sens_type[3]=TERMO_AD;
+
+ sens_type[4]=TERMO_AD;
+ sens_type[5]=TERMO_AD;
+
+//sens_type[6]=TERMO_AD;
+//sens_type[7]=TERMO_AD;
+
+
+ sens_type[8]=TERMO_RS;
+ sens_type[9]=TERMO_RS;
+ sens_type[10]=TERMO_RS;
+ sens_type[11]=TERMO_RS;
+
+ sens_type[12]=VOLTAGE; sens_pair[12]=13;
+ sens_type[13]=VOLTAGE; sens_pair[13]=12;
+ sens_type[14]=VOLTAGE; sens_pair[14]=15;
+ sens_type[15]=VOLTAGE; sens_pair[15]=14;
+
+ Modbus[12].bit.bitE = 1; // Ignore
+ Modbus[13].bit.bitE = 1; // Ignore
+ Modbus[14].bit.bitE = 1; // Ignore
+ Modbus[15].bit.bitE = 1; // Ignore
+ }
+
+ if((Mode==adr_INV1)||(Mode==adr_INV2))
+ {
+ sens_type[0]=TERMO_AD;
+ sens_type[1]=TERMO_AD;
+ sens_type[2]=TERMO_AD;
+ sens_type[3]=TERMO_AD;
+
+ sens_type[4]=TERMO_AD;
+ sens_type[5]=TERMO_AD;
+//sens_type[6]=TERMO_AD;
+
+ sens_type[7]=TERMO_RS;
+ sens_type[8]=TERMO_RS;
+ sens_type[9]=TERMO_RS;
+ sens_type[10]=TERMO_RS;
+ sens_type[11]=TERMO_RS;
+ }
+
+ if(Mode==adr_SHKF)
+ {
+ sens_type[0 ] = POWER_380; sens_pair[0]=1;
+ sens_type[1 ] = POWER_380; sens_pair[1]=0;
+ sens_type[2 ] = POWER_220; sens_pair[2]=3;
+ sens_type[3 ] = POWER_220; sens_pair[3]=2;
+ sens_type[4 ] = POWER_31;
+ sens_type[5 ] = POWER_31;
+ sens_type[6 ] = POWER_24;
+ sens_type[7 ] = POWER_24;
+ sens_type[8 ] = POWER_24;
+ sens_type[9 ] = POWER_24;
+ sens_type[10] = POWER_24;
+ sens_type[11] = POWER_24;
+ sens_type[12] = POWER_15;
+ sens_type[13] = TERMO_AD;
+ sens_type[14] = TERMO_AD;
+ sens_type[15] = VIRT_24;
+ sens_type[16] = VIRT_24;
+ }
+
+ for(i=0;i<4; i++) err_count[i] = 0;
+ for(i=0;i<6; i++) lev_count[i] = 0;
+ for(i=0;i<28;i++) sens_count[i] = 0;
+ for(i=0;i<32;i++) din_count[i] = 0;
+ for(i=0;i<40;i++) filter[i] = def_FILTERBAT;
+
+ for(i=0;i=edge) return 1;
+ (*count)++; return pre;
+ }
+ if( (*count) == 0 ) return 0;
+ (*count)--; return pre;
+}
+
+void reset_errs(int sens, ERROR er)
+{
+// unsigned long report;
+ unsigned int set;
+ ERROR err;
+
+ err=er;
+
+ if(!sens_error[sens].bit.Latch)
+ {
+ set = sens_error[sens].all & NOER;
+ sens_error[sens].all = err.all | set;
+ }
+ else
+ {
+ sens_error[sens].all |= err.all;
+ }
+ sens_error[sens].bit.Ready = !(err.bit.Stop && (!sens_error[sens].bit.Ignor));
+ chk.bit.Error|= !(sens_error[sens].bit.Ready);
+}
+
+
+ERROR control_ADC(int sens, int number, int zero)
+{
+ ERROR err;
+ int erwait;
+
+ err.all = 0;
+
+ if(TermoSW) erwait = SENS_ERR_WAIT;
+ else erwait = ADC_FREQ;
+
+// Канал оборван
+ if(er_anal(((number <= zero)||(number >= (0x0FFF-(zero/100)))),
+ &sens_count[sens],erwait,
+ sens_error[sens].bit.Tear))
+ {
+ err.bit.Tear = 1;
+ }
+/*
+// АЦП залип
+ if(er_anal( (sens_prev[sens] == number),
+ &sens_count[sens][1],ADC_FREQ,
+ sens_error[sens].bit.Stick))
+ {
+ err.bit.Stick = 1;
+ }
+ sens_prev[sens] = number;
+*/
+ return err;
+}
+
+
+
+
+
+
+int input_freq(int chan, int Volt)
+{
+ static int prevolt[4],tics[4],tacs[4],tic[4],tac[4];
+ static long Freq = 0;
+ int i,sum=0,bum=0;
+
+ if(Volt >= Zero_lev[chan])
+ if(prevolt[chan]< Zero_lev[chan])
+ {
+ tics[chan] = tic[chan]; tic[chan] = 0; bum = 1;
+ }
+
+ if(Volt < Zero_lev[chan])
+ if(prevolt[chan]>= Zero_lev[chan])
+ {
+ tacs[chan] = tac[chan]; tac[chan] = 0; bum = 1;
+ }
+
+ if(bum)
+ {
+ for(i=0;i<4;i++) sum += tics[i] + tacs[i];
+ Freq = (80L * ADC_FREQ) / sum;
+ }
+
+ prevolt[chan] = Volt;
+ tic[chan]++;
+ tac[chan]++;
+
+ return Freq;
+}
+
+
+
+
+void Current_count(int sens)
+{
+ float Numb,Current,fAmpl;
+ static float aCurrent,Amplitude;
+ static int prezer0=0;
+ int chan, pair, ist, thrd, i, ignor;
+ int freq=0;
+
+ ERROR error;
+
+ error.all = 0;
+
+ chan = sens - MAX_TPL_CANAL;
+ pair = sens_pair[sens] - MAX_TPL_CANAL;
+ ist = !(chan & 1);
+ thrd= (chan >>1) + 4;
+
+ if(sens_error[sens].bit.Bypas)
+ {
+ sens_error[sens].all = 0;
+ sens_error[sens].bit.Bypas = 1;
+ Modbus[sens+DATASTART].all = 0;
+ return;
+ }
+
+ Numb = ADC_table[sens];
+
+ if(cTermoCal||cSetZero)
+ {
+ if(!prezer0)
+ for(i=0;i<4;i++) lev_count[i] = Numb;
+ lev_count[chan] += (Numb-lev_count[chan])/1000.0;
+ adc0[sens] = (int)(filterbat(&filter[sens],lev_count[chan]));
+ Zero_lev[chan] = adc0[sens];
+ Modbus[sens+DATASTART].all = adc0[sens];
+ }
+ prezer0 = (cTermoCal||cSetZero);
+
+ Current = (Numb - adc0[sens]) * tmpK[sens];
+
+ if(!(cTermoCal||cSetZero))
+ {
+ freq = input_freq(chan,Numb);
+
+
+ lev_count[chan] += (fabs(Current)-lev_count[chan])/1000.0;
+
+// Запомним
+ if(ist)
+ {
+ aCurrent = -Current; // Запомнили мгновенное значение - дла амплитуды
+ }
+ else
+ {
+// Вычисление амплитуды
+ Amplitude = im_calc(Current,aCurrent);
+ fAmpl = filterbat(&filter[sens],Amplitude);
+
+ if(fAmpl<100)
+ {
+ fAmpl=0; freq=0;
+ }
+
+
+// Modbus[sens+DATASTART-1].all = (int)fAmpl;//(int)Amplitude;
+ Modbus[sens+DATASTART-1].all = (int)(fAmpl/RADIX2);
+
+// Третьа фаза дла проверок
+ lev_count[thrd] += (fabs(-Current-aCurrent)-lev_count[thrd])/1000.0;
+
+i=(8-((sens+DATASTART-1)%8));
+Modbus[sens+DATASTART+i-1+(thrd-4)*3].all = lev_count[chan];
+Modbus[sens+DATASTART+i +(thrd-4)*3].all = lev_count[pair];
+Modbus[sens+DATASTART+i+1+(thrd-4)*3].all = lev_count[thrd];
+
+ }
+
+ Modbus[sens+DATASTART].all = freq;
+
+// Зашиты!
+ if(Current > 1.1 * sens_hi_edge[sens])
+ {
+ error.bit.Hyper = 1;
+ error.bit.Stop = 1;
+ }
+
+ Numb = lev_count[chan];
+ if(Numb 0.2) && (Numb>100),
+ &err_count[chan],time_1_5sec,0))
+ {
+ error.bit.Wry = 1;
+ error.bit.Stop = 1;
+ }
+
+ if(er_anal( ((Numb-lev_count[thrd])/Numb > 0.2) && (Numb>100),
+ &err_count[thrd],time_1_5sec,0))
+ {
+ error.bit.Wry = 1;
+ if(!ignor)
+ error.bit.Stop = 1;
+ }
+
+ if(!ist)
+ {
+ if(Amplitude > sens_hi_edge[sens])
+ {
+ error.bit.Hyper = 1;
+ if(!ignor)
+ error.bit.Stop = 1;
+ }
+
+ if(Amplitude < sens_lo_edge[sens])
+ {
+ error.bit.Out = 1;
+ if(!ignor)
+ error.bit.Stop = 1;
+ } } }
+
+ reset_errs(sens,error);
+
+}
+
+void Temper_count(int chan)
+{
+ float Numb;
+ int Temper;
+ int ignor;
+ ERROR error;
+ int zer0;
+
+ if(!chan)
+ {
+ sig.all = chk.all;
+ chk.all = 0;
+ }
+
+ if(chansens_hi_edge[chan]-Cooling) && (sens_error[chan].bit.Hyper)) ||
+ (Temper>sens_hi_edge[chan]) )
+ {
+ error.bit.Hyper = 1;
+ if(!ignor)
+ {
+ error.bit.Stop = 1;
+ chk.bit.OverHeat= 1;
+ } }
+
+ else
+
+// Предупреждение по температуре
+
+ if(Temper>sens_lo_edge[chan])
+ {
+ error.bit.Over = 1;
+ if(!ignor)
+ chk.bit.SubHeat = 1;
+ } }
+
+ if(error.all) chk.bit.OutHeat = 1;
+
+ reset_errs(chan,error);
+
+}
+
+void Power_count(int chan)
+{
+ float Numb;
+ int Power,ignor,bitt;
+ ERROR error;
+
+ if(sens_error[chan].bit.Bypas)
+ {
+ sens_error[chan].all = 0;
+ sens_error[chan].bit.Bypas = 1;
+ Modbus[chan+DATASTART].all = 0;
+ return;
+ }
+
+ Numb = ADC_table[chan];
+
+ if(cTermoCal)
+ {
+ Modbus[chan+DATASTART].all = (int)(Numb);
+ return; // штобы структура ошибок не влезала в данные
+ }
+
+ Power = (Numb * tmpK[chan]+5)/10.0; // powK[sens_type[chan]];
+
+ Modbus[chan+DATASTART].all = Power;
+
+ error.all = 0;
+ ignor = sens_error[chan].bit.Ignor;
+
+ if(Power sens_hi_edge[chan])
+ {
+ error.bit.Hyper = 1;
+ if(!ignor)
+ error.bit.Stop = 1;
+ }
+
+ if(chan>3)
+ {
+ bitt = (chan-4)*2;
+ error.bit.Contr1 = er_anal(((Inputs.all>>bitt)&1), &din_count[bitt], 1000, 0); bitt++;
+ error.bit.Contr2 = er_anal(((Inputs.all>>bitt)&1), &din_count[bitt], 1000, 0);
+ }
+
+ if(error.all)
+ if(!ignor)
+ chk.bit.Alarm = 1;
+ reset_errs(chan,error);
+}
diff --git a/measure.h b/measure.h
new file mode 100644
index 0000000..5a1665e
--- /dev/null
+++ b/measure.h
@@ -0,0 +1,140 @@
+// вгв
+#ifndef _MEASURE
+#define _MEASURE
+
+void Init_sensors(void);
+void Init_optic(void);
+void Init_packMask(void);
+void Temper_count(int chan);
+void Current_count(int chan);
+void Power_count(int chan);
+
+typedef union
+{
+ struct
+ {
+ unsigned int Tear :1;
+ unsigned int Stick :1;
+ unsigned int Wry :1;
+ unsigned int Out :1;
+ unsigned int Over :1;
+ unsigned int Hyper :1;
+ unsigned int Contr1 :1;
+ unsigned int Contr2 :1;
+
+ unsigned int Stop :1;
+ unsigned int Ready :1;
+ unsigned int res :3;
+ unsigned int Latch :1;
+ unsigned int Ignor :1;
+ unsigned int Bypas :1;
+
+ } bit;
+ unsigned int all;
+
+} ERROR;
+
+typedef union
+{
+ struct
+ {
+ unsigned int Error :1;
+ unsigned int Alarm :1;
+ unsigned int OverHeat :1;
+ unsigned int SubHeat :1;
+ unsigned int OutHeat :1;
+ unsigned int Test_lamp :1;
+
+ } bit;
+ unsigned int all;
+
+} FLAG;
+
+#define NOER 0xE000
+#define EROR 0x01FF
+
+#define SIG_FREQ 4000 // Гц
+#define READY_FREQ 1000 // Гц
+#define BLINK_FREQ 2 // Гц
+#define ADC_FREQ 5000//3885//777//2000//20000 //777 //3885 // Гц (777*5)
+#define DAC_FREQ 50 // Гц
+
+#define CANPOWSE (SIG_FREQ / 100) // 10 ms
+
+#define LOAD_TIME 10 // sec
+
+
+#define SENS_ERR_WAIT 10
+
+#define maximum_bright 10
+
+/*
+#define SNOW 1720.0 //1920.0
+#define BOIL 2360.0 //2561.0
+
+#define tmp_T_0 0.0
+#define tmp_T_1 200.00
+#define tmp_A1_0 978.0
+#define tmp_A1_1 1686.0
+#define tmp_A2_0 1017.0
+#define tmp_A2_1 1736.0
+#define eta_A1 1002.0
+#define eta_A2 1542.0
+*/
+
+#define tmp_T_0 84.31 // 68Om
+#define tmp_T_1 234.19 // 100Om
+#define tmp_A1_0 540.0 // канал 1 68Ом
+#define tmp_A2_0 500.0 // канал 1 100Ом
+#define tmp_A1_1 1055.0 // канал 2 68Ом
+#define tmp_A2_1 1060.0 // канал 2 100Ом
+
+
+#define ZERO 27
+
+#define mka300 2040
+#define mka400 2700
+
+#define C100 650
+#define C150 2370
+
+#define Cooling 5 // (°С) Гистерезис по снатию перегрева
+
+#define COSPi6 0.86602540378443864676372317075294
+
+#define RADIX2 1.4142135623730950488016887242097
+
+#define CURRENT 1 // ток
+#define VOLTAGE 2 // напражение
+
+#define POWER_380 3 // питание 380В
+#define POWER_220 4 // питание 220В
+#define POWER_31 5 // питание 31В
+#define POWER_24 6 // питание 24В
+#define VIRT_24 7 // питание 24В
+#define POWER_15 8 // питание 15В
+#define TERMO_AD 9 // термодатчик мелкосхема
+#define TERMO_RS 10 // термодатчик резистор
+#define OPTIC 11 // оптоканал мегомметра
+
+extern int MAX_TPL_CANAL;
+
+extern FILTERBAT filter[];
+
+extern ERROR * sens_error;
+extern int * sens_hi_edge;
+extern int * sens_lo_edge;
+
+extern int adc0[],tmp0[];
+
+#define Zero_lev (adc0+12) //((int *)&Modbus[0x74])
+
+extern float tmpK[];
+extern FLAG chk,sig;
+extern int sens_type[];
+
+extern int period_ready;
+
+extern unsigned int CanPowse,CanGO;
+
+#endif //_MEASURE
diff --git a/message.c b/message.c
new file mode 100644
index 0000000..ac88305
--- /dev/null
+++ b/message.c
@@ -0,0 +1,367 @@
+#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
+#include "package.h"
+#include "RS485.h"
+#include "crc16.h"
+#include "cntrl_adr.h"
+#include "bios_dsp.h"
+#include "filter_bat2.h"
+#include "measure.h"
+#include "message.h"
+
+
+#include "ADC.h"
+#include "peripher.h"
+
+#include "ecan.h"
+#include "spise2p.h"
+#include "i2c.h"
+
+WORDE Modbus[ANSWER_LEN+1];
+WORDE reply[REPLY_LEN];
+
+unsigned int param[ANSWER_LEN+1];
+
+LONGE* outputs;
+
+int DataAnalog1,DataAnalog2;
+
+ERROR * sens_error;
+int * sens_hi_edge;
+int * sens_lo_edge;
+
+unsigned int Maska[2][8];
+
+void Default_params()
+{
+ unsigned int i;
+
+ for(i=0;iRS_Header[2] << 8) |*/ rs_arr->RS_Header[3];
+
+// получили количество слов данных
+ Length_MB = (rs_arr->RS_Header[4] << 8) | rs_arr->RS_Header[5];
+
+ /////////////////////////////////////////////////
+ // Отсылка
+ /* Посчитали контрольную сумму перед самой посылкой */
+
+ rs_arr->buffer[0] = CNTRL_ADDR;
+ rs_arr->buffer[1] = CMD_MODBUS_3;
+ rs_arr->buffer[2] = Length_MB*2;
+
+ for (i=0;ibuffer[3+i*2 ]=(Modbus[Address_MB+i].byt.byte_hi);
+ rs_arr->buffer[3+i*2+1]=(Modbus[Address_MB+i].byt.byte_lo);
+ }
+
+ crc = 0xffff;
+ crc = get_crc_16(crc, rs_arr->buffer, Length_MB*2+3);
+
+ rs_arr->buffer[Length_MB*2+3] = LOBYTE(crc);
+ rs_arr->buffer[Length_MB*2+4] = HIBYTE(crc);
+
+ rs_arr->buffer[Length_MB*2+5] = 0;
+ rs_arr->buffer[Length_MB*2+6] = 0;
+ rs_arr->buffer[Length_MB*2+7] = 0;
+ rs_arr->buffer[Length_MB*2+8] = 0;
+
+ rs_arr->flag_TIMEOUT_to_Send=true;
+ RS_Send(rs_arr, rs_arr->buffer, Length_MB*2+8);
+
+ return;
+}
+
+void ReceiveCommandModbus6(RS_DATA *rs_arr)
+{
+ unsigned int Address_MB, Data_MB, i;
+
+ /////////////////////////////////////////////////
+ // Отсылка
+ /* Отправлаем назад то же самое */
+
+ for (i=0;i<8;i++)
+ rs_arr->buffer[i] = rs_arr->RS_Header[i];
+
+// получили начальный адрес записи
+ Address_MB = (/*(rs_arr->RS_Header[2] << 8) | */rs_arr->RS_Header[3]);
+
+// получили слово данных
+ Data_MB = (rs_arr->RS_Header[4] << 8) | rs_arr->RS_Header[5];
+
+ Modbus[Address_MB].all = Data_MB;
+
+ rs_arr->flag_TIMEOUT_to_Send=true;
+ RS_Send(rs_arr, rs_arr->buffer, 10);
+}
diff --git a/message.h b/message.h
new file mode 100644
index 0000000..9ae50ae
--- /dev/null
+++ b/message.h
@@ -0,0 +1,51 @@
+#ifndef MESSAGE_H
+#define MESSAGE_H
+
+typedef unsigned char CHAR;
+
+#define ANSWER_LEN 0x80 //70 // 16+16+16+16+6
+#define REPLY_LEN 0x19
+
+#define byte_hi byte_1
+#define byte_lo byte_0
+
+typedef struct
+{
+ unsigned char Address; // Адрес контроллера
+ unsigned char Number; // Номер команды
+
+ BAITE byte0;
+ BAITE byte1;
+ BAITE byte2;
+ BAITE byte3;
+ BAITE byte4;
+ BAITE byte5;
+ BAITE byte6;
+ BAITE byte7;
+
+ unsigned char crc_lo;
+ unsigned char crc_hi;
+ unsigned char add_byte;
+} CMD_TO_TMS;
+
+extern WORDE Modbus[];
+extern WORDE reply[];
+
+extern LONGE* outputs;
+
+extern int DataAnalog1,DataAnalog2;
+
+extern unsigned int Maska[][8];
+
+//void ReceiveCommand(RS_DATA *rs_arr);
+void ReceiveCommandModbus3(RS_DATA *rs_arr);
+void ReceiveCommandModbus6(RS_DATA *rs_arr);
+
+void reset_errs(int sens, ERROR er);
+
+void Save_params(void);
+void Load_params(void);
+void Load_caliber(void);
+void Default_params(void);
+
+#endif //MESSAGE_H
diff --git a/package.h b/package.h
new file mode 100644
index 0000000..c0a9fde
--- /dev/null
+++ b/package.h
@@ -0,0 +1,70 @@
+#ifndef PACKAGE
+#define PACKAGE
+
+#define TERMOPAIR 14
+#define CURRENTOS (TERMOPAIR*2)
+#define DATASTART 24
+
+//-----------------------------------------------
+#define adr_REC1 1
+#define adr_REC2 2
+#define adr_INV1 3
+#define adr_INV2 4
+#define adr_SHKF 5
+#define adr_ISOL 6
+//-----------------------------------------------
+
+//-----------------------------------------------
+#define dsk_COMM 1
+#define dsk_SHKF 2
+#define dsk_ISOL 3
+//-----------------------------------------------
+
+
+#define CAN_send_start 0 // Адрес первого передаваемого
+#define CAN_send_finis 0x6F // Адрес последнего передаваемого
+
+#define start_sens_error 0
+#define start_sens_hi_edge 48
+#define start_sens_lo_edge 72
+
+#define IsShimON Modbus[2].bit.bit0
+
+#define Input Modbus[0x17]
+
+#define optopowse Modbus[0x60].all // пауза между запросами, ms
+#define optofiltr Modbus[0x61].all // коэффициент фильтрации
+
+#define Brightness Modbus[0x64].all // аркость сигнальных лампочек
+
+#define Cancount ((int *)&Modbus[0x65])
+
+#define Zeroes ((int *)&Modbus[0x70])
+
+#define isoMOM ((int *)&Modbus[0x70])
+#define isoADC ((int *)&Modbus[0x78])
+
+#define LastMode Modbus[126].all
+
+#define Commands Modbus[127].all
+#define cTestLamp Modbus[127].bit.bit0
+#define cSetZero Modbus[127].bit.bit1
+#define cSaveParam Modbus[127].bit.bit2
+#define cDefParam Modbus[127].bit.bit3
+
+#define cTermoCal Modbus[127].bit.bit4
+#define cReadCal Modbus[127].bit.bit5
+
+#define cExtLamp Modbus[127].bit.bit6
+#define cExtLite Modbus[127].bit.bit7
+
+#define cKoefCalc Modbus[127].bit.bit8
+
+#define cShimON Modbus[127].bit.bit9
+
+
+#define cReset Modbus[127].bit.bitF
+
+
+#endif //PACKAGE
+
diff --git a/peripher.c b/peripher.c
new file mode 100644
index 0000000..1658091
--- /dev/null
+++ b/peripher.c
@@ -0,0 +1,145 @@
+#include "DSP2833x_Device.h" // DSP281x Headerfile Include File
+#include "filter_bat2.h"
+#include "measure.h"
+#include "RS485.h"
+#include "message.h"
+
+#include "package.h"
+
+#include "peripher.h"
+#include "GPIO_table.h"
+
+
+int Mode,Desk,Addrr,TermoAD=0,TermoRS=0,TermoSW=0,Currentoz=0;
+LONGE Inputs;
+
+int ExtraCanal[24];
+
+void get_Mode()
+{
+ int i,qua;
+
+ EALLOW;
+
+ GpioCtrlRegs.GPAMUX1.all &= 0xFF000000; // 00—11
+ GpioCtrlRegs.GPAMUX2.all &= 0xFF00003F; // 19—27
+ GpioCtrlRegs.GPBMUX1.all &= 0xFFFFFCC0; // 32—34, 36
+ GpioCtrlRegs.GPBMUX2.all &= 0x000FF000; // 48—53, 58—63
+
+ GpioCtrlRegs.GPADIR.bit.GPIO20 = 0;
+ GpioCtrlRegs.GPADIR.bit.GPIO21 = 0;
+ GpioCtrlRegs.GPADIR.bit.GPIO22 = 0;
+ GpioCtrlRegs.GPBDIR.bit.GPIO51 = 0;
+
+ EDIS;
+
+ Mode=0;
+
+ qua=0;
+ for(i=0;i<100;i++)
+ qua += !GpioDataRegs.GPADAT.bit.GPIO22;
+ if(qua>50) Mode += 1;
+
+ qua=0;
+ for(i=0;i<100;i++)
+ qua += !GpioDataRegs.GPADAT.bit.GPIO20;
+ if(qua>50) Mode += 2;
+
+ qua=0;
+ for(i=0;i<100;i++)
+ qua += !GpioDataRegs.GPADAT.bit.GPIO21;
+ if(qua>50) Mode += 4;
+
+ Addrr = Mode*2;
+
+ Mode+= 1;
+
+ qua=0;
+ for(i=0;i<100;i++)
+ qua += !GpioDataRegs.GPBDAT.bit.GPIO51;
+ if(qua>50) Addrr += 1;
+
+ if( (Mode==adr_REC1)||(Mode==adr_REC2)) Currentoz = 1;
+ if( (Mode==adr_REC1)||(Mode==adr_REC2)||
+ (Mode==adr_INV1)||(Mode==adr_INV2)) Desk = dsk_COMM;
+ if (Mode==adr_SHKF) Desk = dsk_SHKF;
+ if (Mode==adr_ISOL) Desk = dsk_ISOL;
+
+ EALLOW;
+ switch(Desk)
+ {
+ case dsk_COMM: GpioCtrlRegs.GPADIR.all = COMM_GPADIR;
+ GpioCtrlRegs.GPBDIR.all = COMM_GPBDIR; break;
+
+ case dsk_SHKF: GpioCtrlRegs.GPADIR.all = VEPP_GPADIR;
+ GpioCtrlRegs.GPBDIR.all = VEPP_GPBDIR; break;
+
+ case dsk_ISOL: GpioCtrlRegs.GPADIR.all = ISOL_GPADIR;
+ GpioCtrlRegs.GPBDIR.all = ISOL_GPBDIR; break;
+ }
+ EDIS;
+}
+
+void get_Inputs()
+{
+ static long butthurt[2] ={0,0};
+ unsigned long butt=0;
+
+ if(Desk==dsk_COMM)
+ {
+ if(!GpioDataRegs.GPADAT.bit.GPIO7) butthurt[0]=0;
+ else if(butthurt[0] size) len=size;
+
+ writeData.dataPtr = buf;
+ writeData.nrData = len;
+ writeData.se2pAddr = adres * WORD_LEN;
+
+ spiSe2pWrite(&se2p, &writeData);
+ while(!spiSe2pFree(&se2p));
+
+ buf += len;
+ adres += len;
+ size -= len;
+ }
+ CpuTimer2Regs.TCR.all = 0x4010; // Use write-only instruction to set TSS bit = 1
+// diod2_off();
+
+}
+
+void Seeprom_read( unsigned int adres,
+ unsigned int buf[],
+ unsigned int size)
+{
+ unsigned int len;
+
+// diod2_on();
+ CpuTimer2.InterruptCount=0;
+ CpuTimer2Regs.TCR.all = 0x4020; // Use write-only instruction to set TSS bit = 0
+
+ while(!spiSe2pFree(&se2p));
+
+ size = (size / WORD_LEN) + (size % WORD_LEN);
+ while(size)
+ {
+ len = PAGE_LEN - (adres % PAGE_LEN);
+ if(len > size) len=size;
+
+ readData.dataPtr = buf;
+ readData.nrData = len;
+ readData.se2pAddr = adres * WORD_LEN;
+
+ spiSe2pRead(&se2p, &readData);
+ while(!spiSe2pFree(&se2p));
+
+ buf += len;
+ adres += len;
+ size -= len;
+ }
+ CpuTimer2Regs.TCR.all = 0x4010; // Use write-only instruction to set TSS bit = 1
+// diod2_off();
+}
+
+void Init_Seeprom()
+{
+ se2p.init(&se2p);
+
+ EALLOW; // This is needed to write to EALLOW protected registers
+ PieVectTable.TINT2 = &cpu_timer2_isr;
+ EDIS; // This is needed to disable write to EALLOW protected registers
+
+ InitCpuTimers(); // For this example, only initialize the Cpu Timers
+// ConfigCpuTimer(&CpuTimer2, (SYSCLKOUT/1000000), 100);
+// ConfigCpuTimer(&CpuTimer2, (SYSCLKOUT/1000000), 10);
+ ConfigCpuTimer(&CpuTimer2, (SYSCLKOUT/1000000), 100);
+
+ IER |= M_INT14;
+}
+
+void SPISE2P_DRV_init(SPISE2P_DRV *eeprom)
+{
+/* Configure SPI-A pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be SPI functional pins.
+// Comment out other unwanted lines.
+ EALLOW;
+ GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA
+ GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA
+ GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA
+ GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0; // General purpose I/O 19 (default) (I/O)
+ GpioCtrlRegs.GPADIR.bit.GPIO19 = 1; // Configures the GPIO pin as an output
+ GpioDataRegs.GPADAT.bit.GPIO19 = 0;
+ EDIS;
+
+ /* Configure the SPI: 8-bit, Rising edge with delay */
+ SpiaRegs.SPICCR.all=0x0007;
+ SpiaRegs.SPICTL.all=0x001F;
+ SpiaRegs.SPISTS.all=0x00;
+
+ SpiaRegs.SPIBRR = CLKMULT * 6;
+
+ SpiaRegs.SPIFFTX.all=0x8000;
+ SpiaRegs.SPIFFRX.all=0x0000;
+ SpiaRegs.SPIFFCT.all=0x00;
+ SpiaRegs.SPIPRI.all=0x0010;
+
+ /* Disable Chip Select of Serial EEPROM */
+ eeprom->csr=0;
+ eeprom->msgPtr=0;
+
+ SpiaRegs.SPICCR.bit.SPISWRESET=1; // Enable SCI
+}
+
+void SPISE2P_DRV_csset()
+{
+ GpioDataRegs.GPADAT.bit.GPIO19 = 1;
+}
+
+void SPISE2P_DRV_csclr()
+{
+ GpioDataRegs.GPADAT.bit.GPIO19 = 0;
+}
+
+unsigned int spiSe2pFree(SPISE2P_DRV *se2p)
+{
+ if(se2p->csr&0x3) return(0);
+ else return(1);
+}
+
+void spiSe2pWrite(SPISE2P_DRV *se2p, SE2P_DATA *msgPtr)
+{
+ se2p->msgPtr=msgPtr;
+ se2p->csr|=0x1;
+}
+
+void spiSe2pRead(SPISE2P_DRV *se2p, SE2P_DATA *msgPtr)
+{
+ se2p->msgPtr=msgPtr;
+ se2p->csr|=0x2;
+}
+
+/********************************************************************/
+/******* SPI bus Serial EEPROM driver Tick function *****************/
+/********************************************************************/
+
+interrupt void cpu_timer2_isr(void)
+{ EALLOW;
+ CpuTimer2.InterruptCount++;
+
+ se2p.tick(&se2p);
+
+ // The CPU acknowledges the interrupt.
+ EDIS;
+}
+
+void SPISE2P_DRV_tick(SPISE2P_DRV *eeprom)
+{
+ static unsigned int step=0;
+ static unsigned int dataCount=0;
+ static volatile unsigned int dummy=0;
+
+ switch(step)
+ {
+ case 0:
+ /* If write request is SET, then trigger the Write operation
+ If read request is SET, then trigger the Read operation
+ If Read request is also not SET, then continue to poll */
+
+ if(eeprom->csr&SPISE2P_WRRQ)
+ { step=1;
+ eeprom->csr|=SPISE2P_WRIP; /* Set Write in progress*/
+ eeprom->csclr();
+ }
+
+ if(eeprom->csr&SPISE2P_RDRQ)
+ { step=13;
+ eeprom->csr|=SPISE2P_RDIP; /* Set Read in progress */
+ eeprom->csclr();
+ }
+ break;
+
+ case 1:
+ /************************************************************
+ *********** SPI bus EEPROM Write Starts from here ***********
+ *************************************************************
+ Prier to any attempt to write data to SPI serial EEPROM
+ Write Enable Latch must be set by issuing the WREN command */
+ SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT;
+ SpiaRegs.SPITXBUF=SPISE2P_WREN_CMD;
+ SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1;
+ step=2;
+ break;
+
+ case 2:
+ /* Wait for VSPI State machine to send the WREN command and
+ serial EEPROM Chip Select must be brought to HIGH to set
+ the WREN latch */
+
+ if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
+ {
+ dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */
+ eeprom->csset();
+
+ step=3;
+ }
+ break;
+
+ case 3:
+ /* Assert CS of Serial EEPROM and send WRITE command */
+
+ eeprom->csclr();
+ SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT;
+ SpiaRegs.SPITXBUF=SPISE2P_WRITE_CMD;
+ SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1;
+ step=4;
+ break;
+
+ case 4:
+ /* Wait for VSPI State machine to send the WRITE command */
+
+ if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
+ { dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */
+ step=5;
+ }
+ break;
+
+ case 5:
+ /* Send Address */
+
+ #if(SPISE2P_ADDR_WIDTH==SIXTEEN_BIT)
+ SpiaRegs.SPICCR.all= SPISE2P_TFR16BIT;
+ SpiaRegs.SPITXBUF=eeprom->msgPtr->se2pAddr;
+ #endif
+ #if(SPISE2P_ADDR_WIDTH==EIGHT_BIT)
+ SpiaRegs.SPICCR.all= SPISE2P_TFR8BIT;
+ SpiaRegs.SPITXBUF=eeprom->msgPtr->se2pAddr<<8;
+ #endif
+
+ SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */
+ step=6;
+ break;
+
+ case 6:
+ /* Wait for VSPI State machine to send the Address */
+
+ if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
+ { dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */
+ step=7;
+ }
+ break;
+
+ case 7:
+ /* Send Data */
+
+ #if(SPISE2P_DATA_WIDTH==SIXTEEN_BIT)
+ SpiaRegs.SPICCR.all=SPISE2P_TFR16BIT;
+ SpiaRegs.SPITXBUF=*(eeprom->msgPtr->dataPtr+dataCount);
+ #endif
+
+ #if(SPISE2P_DATA_WIDTH==EIGHT_BIT)
+ SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT;
+ SpiaRegs.SPITXBUF=*(eeprom->msgPtr->dataPtr+dataCount)<<8;
+ #endif
+
+ dataCount++;
+ SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */
+ step=8;
+ break;
+
+ case 8:
+ /* Wait for VSPI State machine to send the Data.
+ If all the data are sent, then set the CS pin to HIGH
+ to program or write the data in EEPROM array */
+
+ if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
+ { dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */
+
+ if (dataCount==eeprom->msgPtr->nrData)
+ { eeprom->csset();
+ step=9;}
+ else
+ step=7; /* Write next data */
+ }
+ break;
+
+
+ case 9:
+ /* Read the EEPROM status register to check whether the
+ data sent are indeed programmed to the EEPROM array.
+ Hence, send RDSR command to EEPROM to read status reg. */
+
+ eeprom->csclr();
+ SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT;
+ SpiaRegs.SPITXBUF=SPISE2P_RDSR_CMD;
+ SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */
+ step=10;
+ break;
+
+ case 10:
+ /* Wait for VSPI State machine to send RDSR command */
+
+ if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
+ { dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */
+ step=11;
+ }
+ break;
+
+ case 11:
+ /* Send dummy Data to read Status reg. */
+
+ SpiaRegs.SPITXBUF=SPISE2P_DUMMY_DATA;
+ SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */
+ step=12;
+ break;
+
+ case 12:
+ /* Wait for VSPI State machine to clock out status reg.
+ Check, whether the data are written to the EEPROM array,
+ If written, then reset the WRIP(write in progress) and
+ WRRQ(Write request bit) and go back to STATE0 */
+
+ if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
+ { eeprom->csset();
+
+ if (SpiaRegs.SPIRXBUF & SPISE2P_BUSY_MASK )
+ step=9;
+ else
+ { eeprom->csr&=(~SPISE2P_WRIP);
+ eeprom->csr&=(~SPISE2P_WRRQ);
+ step=0;
+ dataCount=0;
+ }
+ }
+ break;
+
+ case 13:
+ /************************************************************
+ *********** SPI bus EEPROM Read Starts from here ***********
+ *************************************************************
+ Send READ Command to SPI bus serail EEPROM */
+
+ SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT;
+ SpiaRegs.SPITXBUF=SPISE2P_READ_CMD;
+ SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */
+ step=14;
+ break;
+
+ case 14:
+ /* Wait for VSPI State machine to send READ command */
+
+ if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
+ { dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */
+ step=15;
+ }
+ break;
+
+ case 15:
+ /* Send Address */
+
+ #if(SPISE2P_ADDR_WIDTH==SIXTEEN_BIT)
+ SpiaRegs.SPICCR.all= SPISE2P_TFR16BIT;
+ SpiaRegs.SPITXBUF=eeprom->msgPtr->se2pAddr;
+ #endif
+ #if(SPISE2P_ADDR_WIDTH==EIGHT_BIT)
+ SpiaRegs.SPICCR.all= SPISE2P_TFR8BIT;
+ SpiaRegs.SPITXBUF=eeprom->msgPtr->se2pAddr<<8;
+ #endif
+
+ SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */
+ step=16;
+ break;
+
+ case 16:
+ /* Wait for VSPI State machine to send Address */
+
+ if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
+ { dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */
+ step=17;
+ }
+ break;
+
+ case 17:
+ /* Send Dummy value to clock out data from serial EEPROM */
+
+ #if(SPISE2P_DATA_WIDTH==SIXTEEN_BIT)
+ SpiaRegs.SPICCR.all= SPISE2P_TFR16BIT;
+ SpiaRegs.SPITXBUF=SPISE2P_DUMMY_DATA;
+ #endif
+
+ #if(SPISE2P_DATA_WIDTH==EIGHT_BIT)
+ SpiaRegs.SPICCR.all= SPISE2P_TFR8BIT;
+ SpiaRegs.SPITXBUF=SPISE2P_DUMMY_DATA<<8;
+ #endif
+
+ SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */
+ step=18;
+ break;
+
+ case 18:
+ /* Wait for VSPI State machine to clk out data from EEPROM */
+
+ if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
+ {
+ #if(SPISE2P_DATA_WIDTH==SIXTEEN_BIT)
+ *(eeprom->msgPtr->dataPtr+dataCount)=SpiaRegs.SPIRXBUF;
+ #endif
+
+ #if(SPISE2P_DATA_WIDTH==EIGHT_BIT)
+ *(eeprom->msgPtr->dataPtr+dataCount)=SpiaRegs.SPIRXBUF&0xFF;
+ #endif
+ dataCount++;
+ step=19;
+ }
+ break;
+
+ case 19:
+ /* If all the data are read, terminate the read operation by
+ rising the CS. Then reset the RDIP (Read in progress) bit
+ and reset the RDRQ(Read request) bit and go back to STATE0 */
+
+ if (dataCount==eeprom->msgPtr->nrData)
+ { eeprom->csset();
+ step=0;
+ dataCount=0;
+ eeprom->csr&=(~SPISE2P_RDIP);
+ eeprom->csr&=(~SPISE2P_RDRQ);
+ }
+ else
+ step=17;
+ break;
+ }
+}
+
diff --git a/spise2p.h b/spise2p.h
new file mode 100644
index 0000000..6cf27e4
--- /dev/null
+++ b/spise2p.h
@@ -0,0 +1,134 @@
+/*=====================================================================
+File name : SPISE2P.H
+
+Originator : Settu Duraisamy
+ C2000 Applications Team
+ Texas Instruments
+
+Description :
+ Header file containing object definitions, proto type
+ declaration and default object initializers for
+ SPI Serial EEPROM driver using VSPI
+
+Date : 30/6/2003 (DD/MM/YYYY)
+=======================================================================*/
+
+#ifndef __SPISE2P_H__
+
+#define __SPISE2P_H__
+
+// Ёмкость памати в байтах
+#define SEEPROM_LEN 0x10000
+
+#define NULL 0
+
+#define SIXTEEN_BIT 15
+#define EIGHT_BIT 07
+
+/***************************************************************/
+/* Configurable Parameter for SPI bus Serial EEPROM */
+/***************************************************************/
+#define SPISE2P_DATA_WIDTH SIXTEEN_BIT//EIGHT_BIT
+#define SPISE2P_ADDR_WIDTH SIXTEEN_BIT
+#define SPIBAUD_REG_VAL 1//12
+#define SPICLK_PHASE 1
+#define SPICLK_POLARITY 0
+
+#define SPIBAUD_RATE 100000
+//10000000
+
+/**************************************************************/
+/**************************************************************/
+
+/* Serial EEPROM Command words, left justified */
+#define SPISE2P_READ_CMD 0x0300
+#define SPISE2P_WRITE_CMD 0x0200
+#define SPISE2P_WRDI_CMD 0x0400
+#define SPISE2P_WREN_CMD 0x0600
+#define SPISE2P_RDSR_CMD 0x0500
+#define SPISE2P_WRSR_CMD 0x0100
+
+#define SPISE2P_RDID_CMD 0x0A00
+
+#define SPISE2P_DUMMY_DATA 0x0000
+#define SPISE2P_BUSY_MASK 0x01
+
+/* Symbolic constant for SPICCR to transfer 8bit or 16 bit value*/
+#define SPISE2P_TFR16BIT 0x80|(SPICLK_POLARITY<<6)|SIXTEEN_BIT
+#define SPISE2P_TFR8BIT 0x80|(SPICLK_POLARITY<<6)|EIGHT_BIT
+
+/* Status valus */
+#define SPISE2P_WRRQ 1 /* Write Requset */
+#define SPISE2P_RDRQ 2 /* Read request */
+#define SPISE2P_WRIP 4 /* Write in progress */
+#define SPISE2P_RDIP 8 /* Read in progress */
+
+/* Message declaration */
+typedef struct {
+ unsigned int *dataPtr; /* Data pointer */
+ unsigned long nrData; /* number of data */
+ unsigned long se2pAddr; /* se2pAddr */
+ }SE2P_DATA;
+
+
+/* Object declaration */
+typedef struct {
+ SE2P_DATA *msgPtr;
+ unsigned int csr; /* control/status register */
+ void (*init)(void *);
+ void (*tick)(void *);
+ void (*csset)(void);
+ void (*csclr)(void);
+ }SPISE2P_DRV;
+
+#define SPISE2P_DRV_DEFAULTS { NULL,\
+ 0,\
+ (void (*)(void *))SPISE2P_DRV_init,\
+ (void (*)(void *))SPISE2P_DRV_tick,\
+ (void (*)(void))SPISE2P_DRV_csset,\
+ (void (*)(void))SPISE2P_DRV_csclr}
+
+typedef SPISE2P_DRV *SPISE2P_DRV_handle;
+
+void SPISE2P_DRV_init(SPISE2P_DRV * );
+void SPISE2P_DRV_tick(SPISE2P_DRV *);
+void SPISE2P_DRV_csset(void);
+void SPISE2P_DRV_csclr(void);
+
+unsigned int spiSe2pFree(SPISE2P_DRV *se2p);
+void spiSe2pWrite(SPISE2P_DRV *se2p, SE2P_DATA *data);
+void spiSe2pRead(SPISE2P_DRV *se2p, SE2P_DATA *data);
+
+#if(SPISE2P_DATA_WIDTH==SIXTEEN_BIT)
+ #define PROM_LEN 0x8000
+ #define PAGE_LEN 0x20
+ #define WORD_LEN 2
+#else
+ #define PROM_LEN 0x4000
+ #define PAGE_LEN 0x40
+ #define WORD_LEN 1
+#endif
+
+/* Установка драйвера сериальной EEPROM. **
+** Инициализациа SPI и проч. Также настройка таймера. **
+** Драйвер работает на прерываниах от таймера 2! */
+void Init_Seeprom(void);
+
+/* Запись блока в SEEPROM. Параметры таковы: **
+** adres - адрес в епромке, куда писать. **
+** adres = 0..0x8000, если длина слова 8 бит **
+** adres = 0..0x4000, если длина слова 16 бит **
+** buf - указатель на памать, откуда писать. **
+** size - длина блока в байтах. По-любому в байтах! */
+void Seeprom_write(unsigned int adres, unsigned int buf[], unsigned int size);
+
+/* Чтение блока из SEEPROM. Параметры таковы: **
+** adres - адрес в епромке, откуда читать. **
+** adres = 0..0x8000, если длина слова 8 бит **
+** adres = 0..0x4000, если длина слова 16 бит **
+** buf - указатель на памать, куда читать. **
+** size - длина блока в байтах. По-любому в байтах! */
+void Seeprom_read(unsigned int adres, unsigned int buf[], unsigned int size);
+
+#endif
+
diff --git a/test.c b/test.c
new file mode 100644
index 0000000..5427b15
--- /dev/null
+++ b/test.c
@@ -0,0 +1,183 @@
+#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
+#include "DSP2833x_SWPrioritizedIsrLevels.h"
+
+#include "RS485.h"
+#include "message.h"
+#include "filter_bat2.h"
+#include "measure.h"
+#include "package.h"
+#include "test.h"
+#include "kanal.h"
+#include "peripher.h"
+
+WORDE PRES;
+
+int isMask = 1;
+int isLamp = 0;
+int isBrit = 0;
+int isNumb = 1111;
+
+long cownt=0;
+
+unsigned int Light = 0xFFFF;
+
+int quaLamp = 6;
+
+void what_is()
+{
+ static int numb=0;
+
+ if(keyTest)
+ {
+ if(keyNext & !preNext)
+ {
+ if(!isBrit)
+ {
+ isBrit=1;
+ isMask=1;
+ isLamp=0;
+ }
+ else
+ {
+ isMask<<=1;
+
+ if(++isLamp >= quaLamp)
+ {
+ isMask=1;
+ isLamp=0;
+ } } }
+
+ if(isBrit)
+ {
+ if(keyUp && !preUp)
+ if(Bright[isLamp]<10) Bright[isLamp]++;
+
+ if(keyDown & !preDown)
+ if(Bright[isLamp]>0) Bright[isLamp]--;
+ }
+ else
+ {
+ if(cownt) cownt--;
+ else
+ {
+ cownt = BLN_FREQ/4;
+
+ numb++; if(numb==10) numb=1;
+ isNumb = numb*1111;
+
+ if(!isMask) isMask = 0xFFFF;
+ else isMask = 0;
+ } } }
+
+ else
+ {
+ if(isBrit)
+ {
+ isBrit=0;
+ Save_params();
+ } }
+
+ PRES = KEYS;
+}
+
+
+interrupt void cpu_timer1_isr_PULT(void)
+{
+ static int count_bright=0;
+ unsigned int light=0, i;
+ static LONGE Diod1,Diod2;
+ static unsigned int Cownt,cownt;
+ int dig1,dig2;
+
+ EALLOW;
+ CpuTimer1.InterruptCount++;
+ IER |= MINT13; // Set "global" priority
+ EINT;
+ EDIS; // This is needed to disable write to EALLOW protected registers
+
+ GpioDataRegs.GPATOGGLE.bit.GPIO0=1; // Ready
+
+ if(count_bright) count_bright --;
+ else count_bright = 9;
+ for(i=0; i> 1;
+
+ for (i = 0; i < t; i++)
+ DSP28x_usDelay(CLKMULT*8L);
+}
+
+
+
+
diff --git a/tools.h b/tools.h
new file mode 100644
index 0000000..2107dc4
--- /dev/null
+++ b/tools.h
@@ -0,0 +1,26 @@
+#ifndef TOOLS_H
+#define TOOLS_H
+
+void init_zone7(void);
+
+void setup_leds_line(void);
+
+void pause_us(unsigned long t);
+
+#ifndef TUBER
+#define led1_toggle() GpioDataRegs.GPBTOGGLE.bit.GPIO32=1
+#define led2_toggle() GpioDataRegs.GPBTOGGLE.bit.GPIO48=1
+#define led1_off() GpioDataRegs.GPBSET.bit.GPIO32=1
+#define led2_off() GpioDataRegs.GPBSET.bit.GPIO48=1
+#define led1_on() GpioDataRegs.GPBCLEAR.bit.GPIO32=1
+#define led2_on() GpioDataRegs.GPBCLEAR.bit.GPIO48=1
+#else
+#define led1_toggle() GpioDataRegs.GPBTOGGLE.bit.GPIO32=1
+#define led2_toggle() GpioDataRegs.GPBTOGGLE.bit.GPIO32=1
+#define led1_off() GpioDataRegs.GPBSET.bit.GPIO32=1
+#define led2_off() GpioDataRegs.GPBSET.bit.GPIO32=1
+#define led1_on() GpioDataRegs.GPBCLEAR.bit.GPIO32=1
+#define led2_on() GpioDataRegs.GPBCLEAR.bit.GPIO32=1
+#endif
+
+#endif //TOOLS_H
diff --git a/v120/DSP2833x_common/include/DSP2833x_EPwm_defines.h b/v120/DSP2833x_common/include/DSP2833x_EPwm_defines.h
new file mode 100644
index 0000000..061842f
--- /dev/null
+++ b/v120/DSP2833x_common/include/DSP2833x_EPwm_defines.h
@@ -0,0 +1,164 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006 13:45:39 $
+//###########################################################################
+//
+// FILE: DSP2833x_EPwm_defines.h
+//
+// TITLE: #defines used in ePWM examples examples
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#ifndef DSP2833x_EPWM_DEFINES_H
+#define DSP2833x_EPWM_DEFINES_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// TBCTL (Time-Base Control)
+//==========================
+// CTRMODE bits
+#define TB_COUNT_UP 0x0
+#define TB_COUNT_DOWN 0x1
+#define TB_COUNT_UPDOWN 0x2
+#define TB_FREEZE 0x3
+// PHSEN bit
+#define TB_DISABLE 0x0
+#define TB_ENABLE 0x1
+// PRDLD bit
+#define TB_SHADOW 0x0
+#define TB_IMMEDIATE 0x1
+// SYNCOSEL bits
+#define TB_SYNC_IN 0x0
+#define TB_CTR_ZERO 0x1
+#define TB_CTR_CMPB 0x2
+#define TB_SYNC_DISABLE 0x3
+// HSPCLKDIV and CLKDIV bits
+#define TB_DIV1 0x0
+#define TB_DIV2 0x1
+#define TB_DIV4 0x2
+// PHSDIR bit
+#define TB_DOWN 0x0
+#define TB_UP 0x1
+
+// CMPCTL (Compare Control)
+//==========================
+// LOADAMODE and LOADBMODE bits
+#define CC_CTR_ZERO 0x0
+#define CC_CTR_PRD 0x1
+#define CC_CTR_ZERO_PRD 0x2
+#define CC_LD_DISABLE 0x3
+// SHDWAMODE and SHDWBMODE bits
+#define CC_SHADOW 0x0
+#define CC_IMMEDIATE 0x1
+
+// AQCTLA and AQCTLB (Action Qualifier Control)
+//=============================================
+// ZRO, PRD, CAU, CAD, CBU, CBD bits
+#define AQ_NO_ACTION 0x0
+#define AQ_CLEAR 0x1
+#define AQ_SET 0x2
+#define AQ_TOGGLE 0x3
+
+// DBCTL (Dead-Band Control)
+//==========================
+// OUT MODE bits
+#define DB_DISABLE 0x0
+#define DBA_ENABLE 0x1
+#define DBB_ENABLE 0x2
+#define DB_FULL_ENABLE 0x3
+// POLSEL bits
+#define DB_ACTV_HI 0x0
+#define DB_ACTV_LOC 0x1
+#define DB_ACTV_HIC 0x2
+#define DB_ACTV_LO 0x3
+// IN MODE
+#define DBA_ALL 0x0
+#define DBB_RED_DBA_FED 0x1
+#define DBA_RED_DBB_FED 0x2
+#define DBB_ALL 0x3
+
+// CHPCTL (chopper control)
+//==========================
+// CHPEN bit
+#define CHP_DISABLE 0x0
+#define CHP_ENABLE 0x1
+// CHPFREQ bits
+#define CHP_DIV1 0x0
+#define CHP_DIV2 0x1
+#define CHP_DIV3 0x2
+#define CHP_DIV4 0x3
+#define CHP_DIV5 0x4
+#define CHP_DIV6 0x5
+#define CHP_DIV7 0x6
+#define CHP_DIV8 0x7
+// CHPDUTY bits
+#define CHP1_8TH 0x0
+#define CHP2_8TH 0x1
+#define CHP3_8TH 0x2
+#define CHP4_8TH 0x3
+#define CHP5_8TH 0x4
+#define CHP6_8TH 0x5
+#define CHP7_8TH 0x6
+
+// TZSEL (Trip Zone Select)
+//==========================
+// CBCn and OSHTn bits
+#define TZ_DISABLE 0x0
+#define TZ_ENABLE 0x1
+
+// TZCTL (Trip Zone Control)
+//==========================
+// TZA and TZB bits
+#define TZ_HIZ 0x0
+#define TZ_FORCE_HI 0x1
+#define TZ_FORCE_LO 0x2
+#define TZ_NO_CHANGE 0x3
+
+// ETSEL (Event Trigger Select)
+//=============================
+#define ET_CTR_ZERO 0x1
+#define ET_CTR_PRD 0x2
+#define ET_CTRU_CMPA 0x4
+#define ET_CTRD_CMPA 0x5
+#define ET_CTRU_CMPB 0x6
+#define ET_CTRD_CMPB 0x7
+
+// ETPS (Event Trigger Pre-scale)
+//===============================
+// INTPRD, SOCAPRD, SOCBPRD bits
+#define ET_DISABLE 0x0
+#define ET_1ST 0x1
+#define ET_2ND 0x2
+#define ET_3RD 0x3
+
+
+//--------------------------------
+// HRPWM (High Resolution PWM)
+//================================
+// HRCNFG
+#define HR_Disable 0x0
+#define HR_REP 0x1
+#define HR_FEP 0x2
+#define HR_BEP 0x3
+
+#define HR_CMP 0x0
+#define HR_PHS 0x1
+
+#define HR_CTR_ZERO 0x0
+#define HR_CTR_PRD 0x1
+
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // - end of DSP2833x_EPWM_DEFINES_H
+
+//===========================================================================
+// End of file.
+//===========================================================================
diff --git a/v120/DSP2833x_common/include/DSP2833x_Examples.h b/v120/DSP2833x_common/include/DSP2833x_Examples.h
new file mode 100644
index 0000000..7ababcb
--- /dev/null
+++ b/v120/DSP2833x_common/include/DSP2833x_Examples.h
@@ -0,0 +1,143 @@
+// TI File $Revision: /main/9 $
+// Checkin $Date: July 2, 2008 14:31:12 $
+//###########################################################################
+//
+// FILE: DSP2833x_Examples.h
+//
+// TITLE: DSP2833x Device Definitions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#ifndef DSP2833x_EXAMPLES_H
+#define DSP2833x_EXAMPLES_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*-----------------------------------------------------------------------------
+ Specify the PLL control register (PLLCR) and divide select (DIVSEL) value.
+-----------------------------------------------------------------------------*/
+//#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT
+//#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT
+#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT
+//#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT
+
+#define DSP28_PLLCR CLKMULT*2
+
+//#define DSP28_PLLCR 10
+//#define DSP28_PLLCR 9
+//#define DSP28_PLLCR 8
+//#define DSP28_PLLCR 7
+//#define DSP28_PLLCR 6
+//#define DSP28_PLLCR 5
+//#define DSP28_PLLCR 4
+//#define DSP28_PLLCR 3
+//#define DSP28_PLLCR 2
+//#define DSP28_PLLCR 1
+//#define DSP28_PLLCR 0 // PLL is bypassed in this mode
+//----------------------------------------------------------------------------
+
+
+/*-----------------------------------------------------------------------------
+ Specify the clock rate of the CPU (SYSCLKOUT) in nS.
+
+ Take into account the input clock frequency and the PLL multiplier
+ selected in step 1.
+
+ Use one of the values provided, or define your own.
+ The trailing L is required tells the compiler to treat
+ the number as a 64-bit value.
+
+ Only one statement should be uncommented.
+
+ Example 1:150 MHz devices:
+ CLKIN is a 30MHz crystal.
+
+ In step 1 the user specified PLLCR = 0xA for a
+ 150Mhz CPU clock (SYSCLKOUT = 150MHz).
+
+ In this case, the CPU_RATE will be 6.667L
+ Uncomment the line: #define CPU_RATE 6.667L
+
+ Example 2: 100 MHz devices:
+ CLKIN is a 20MHz crystal.
+
+ In step 1 the user specified PLLCR = 0xA for a
+ 100Mhz CPU clock (SYSCLKOUT = 100MHz).
+
+ In this case, the CPU_RATE will be 10.000L
+ Uncomment the line: #define CPU_RATE 10.000L
+-----------------------------------------------------------------------------*/
+#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT)
+//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT)
+//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT)
+//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT)
+//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT)
+//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT)
+//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT)
+//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT)
+//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT)
+//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT)
+//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT)
+
+//----------------------------------------------------------------------------
+
+/*-----------------------------------------------------------------------------
+ Target device (in DSP2833x_Device.h) determines CPU frequency
+ (for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz
+ (for 28332). User does not have to change anything here.
+-----------------------------------------------------------------------------*/
+#if DSP28_28332 // DSP28_28332 device only
+ #define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq)
+ #define CPU_FRQ_150MHZ 0
+#else
+ #define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334
+ #define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT
+#endif
+
+
+//---------------------------------------------------------------------------
+// Include Example Header Files:
+//
+
+#include "DSP2833x_GlobalPrototypes.h" // Prototypes for global functions within the
+ // .c files.
+
+#include "DSP2833x_ePwm_defines.h" // Macros used for PWM examples.
+#include "DSP2833x_Dma_defines.h" // Macros used for DMA examples.
+#include "DSP2833x_I2C_defines.h" // Macros used for I2C examples.
+
+#define PARTNO_28335 0xEF
+#define PARTNO_28334 0xEE
+#define PARTNO_28332 0xED
+#define PARTNO_28235 0xE8
+#define PARTNO_28234 0xE7
+#define PARTNO_28232 0xE6
+
+
+// Include files not used with DSP/BIOS
+#ifndef DSP28_BIOS
+#include "DSP2833x_DefaultISR.h"
+#endif
+
+
+// DO NOT MODIFY THIS LINE.
+#define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / (long double)CPU_RATE) - 9.0L) / 5.0L)
+
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_EXAMPLES_H definition
+
+
+//===========================================================================
+// End of file.
+//===========================================================================
diff --git a/v120/DSP2833x_common/include/DSP2833x_GlobalPrototypes.h b/v120/DSP2833x_common/include/DSP2833x_GlobalPrototypes.h
new file mode 100644
index 0000000..9c90607
--- /dev/null
+++ b/v120/DSP2833x_common/include/DSP2833x_GlobalPrototypes.h
@@ -0,0 +1,207 @@
+// TI File $Revision: /main/11 $
+// Checkin $Date: May 12, 2008 14:30:08 $
+//###########################################################################
+//
+// FILE: DSP2833x_GlobalPrototypes.h
+//
+// TITLE: Global prototypes for DSP2833x Examples
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#ifndef DSP2833x_GLOBALPROTOTYPES_H
+#define DSP2833x_GLOBALPROTOTYPES_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*---- shared global function prototypes -----------------------------------*/
+extern void InitAdc(void);
+
+extern void DMAInitialize(void);
+// DMA Channel 1
+extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
+extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
+extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
+extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
+extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
+extern void StartDMACH1(void);
+// DMA Channel 2
+extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
+extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
+extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
+extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
+extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
+extern void StartDMACH2(void);
+// DMA Channel 3
+extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
+extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
+extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
+extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
+extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
+extern void StartDMACH3(void);
+// DMA Channel 4
+extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
+extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
+extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
+extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
+extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
+extern void StartDMACH4(void);
+// DMA Channel 5
+extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
+extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
+extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
+extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
+extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
+extern void StartDMACH5(void);
+// DMA Channel 6
+extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
+extern void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep);
+extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
+extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
+extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
+extern void StartDMACH6(void);
+
+extern void InitPeripherals(void);
+#if DSP28_ECANA
+extern void InitECan(void);
+extern void InitECana(void);
+extern void InitECanGpio(void);
+extern void InitECanaGpio(void);
+#endif // endif DSP28_ECANA
+#if DSP28_ECANB
+extern void InitECanb(void);
+extern void InitECanbGpio(void);
+#endif // endif DSP28_ECANB
+extern void InitECap(void);
+extern void InitECapGpio(void);
+extern void InitECap1Gpio(void);
+extern void InitECap2Gpio(void);
+#if DSP28_ECAP3
+extern void InitECap3Gpio(void);
+#endif // endif DSP28_ECAP3
+#if DSP28_ECAP4
+extern void InitECap4Gpio(void);
+#endif // endif DSP28_ECAP4
+#if DSP28_ECAP5
+extern void InitECap5Gpio(void);
+#endif // endif DSP28_ECAP5
+#if DSP28_ECAP6
+extern void InitECap6Gpio(void);
+#endif // endif DSP28_ECAP6
+extern void InitEPwm(void);
+extern void InitEPwmGpio(void);
+extern void InitEPwm1Gpio(void);
+extern void InitEPwm2Gpio(void);
+extern void InitEPwm3Gpio(void);
+#if DSP28_EPWM4
+extern void InitEPwm4Gpio(void);
+#endif // endif DSP28_EPWM4
+#if DSP28_EPWM5
+extern void InitEPwm5Gpio(void);
+#endif // endif DSP28_EPWM5
+#if DSP28_EPWM6
+extern void InitEPwm6Gpio(void);
+#endif // endif DSP28_EPWM6
+#if DSP28_EQEP1
+extern void InitEQep(void);
+extern void InitEQepGpio(void);
+extern void InitEQep1Gpio(void);
+#endif // if DSP28_EQEP1
+#if DSP28_EQEP2
+extern void InitEQep2Gpio(void);
+#endif // endif DSP28_EQEP2
+extern void InitGpio(void);
+extern void InitI2CGpio(void);
+
+extern void InitMcbsp(void);
+extern void InitMcbspa(void);
+extern void delay_loop(void);
+extern void InitMcbspaGpio(void);
+extern void InitMcbspa8bit(void);
+extern void InitMcbspa12bit(void);
+extern void InitMcbspa16bit(void);
+extern void InitMcbspa20bit(void);
+extern void InitMcbspa24bit(void);
+extern void InitMcbspa32bit(void);
+#if DSP28_MCBSPB
+extern void InitMcbspb(void);
+extern void InitMcbspbGpio(void);
+extern void InitMcbspb8bit(void);
+extern void InitMcbspb12bit(void);
+extern void InitMcbspb16bit(void);
+extern void InitMcbspb20bit(void);
+extern void InitMcbspb24bit(void);
+extern void InitMcbspb32bit(void);
+#endif // endif DSP28_MCBSPB
+
+extern void InitPieCtrl(void);
+extern void InitPieVectTable(void);
+
+extern void InitSci(void);
+extern void InitSciGpio(void);
+extern void InitSciaGpio(void);
+#if DSP28_SCIB
+extern void InitScibGpio(void);
+#endif // endif DSP28_SCIB
+#if DSP28_SCIC
+extern void InitScicGpio(void);
+#endif
+extern void InitSpi(void);
+extern void InitSpiGpio(void);
+extern void InitSpiaGpio(void);
+extern void InitSysCtrl(void);
+extern void InitTzGpio(void);
+extern void InitXIntrupt(void);
+extern void XintfInit(void);
+extern void InitXintf16Gpio();
+extern void InitXintf32Gpio();
+extern void InitPll(Uint16 pllcr, Uint16 clkindiv);
+extern void InitPeripheralClocks(void);
+extern void EnableInterrupts(void);
+extern void DSP28x_usDelay(Uint32 Count);
+extern void ADC_cal (void);
+#define KickDog ServiceDog // For compatiblity with previous versions
+extern void ServiceDog(void);
+extern void DisableDog(void);
+extern Uint16 CsmUnlock(void);
+
+// DSP28_DBGIER.asm
+extern void SetDBGIER(Uint16 dbgier);
+
+// CAUTION
+// This function MUST be executed out of RAM. Executing it
+// out of OTP/Flash will yield unpredictable results
+extern void InitFlash(void);
+
+
+void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr);
+
+
+//---------------------------------------------------------------------------
+// External symbols created by the linker cmd file
+// DSP28 examples will use these to relocate code from one LOAD location
+// in either Flash or XINTF to a different RUN location in internal
+// RAM
+extern Uint16 RamfuncsLoadStart;
+extern Uint16 RamfuncsLoadEnd;
+extern Uint16 RamfuncsRunStart;
+
+extern Uint16 XintffuncsLoadStart;
+extern Uint16 XintffuncsLoadEnd;
+extern Uint16 XintffuncsRunStart;
+
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // - end of DSP2833x_GLOBALPROTOTYPES_H
+
+//===========================================================================
+// End of file.
+//===========================================================================
diff --git a/v120/DSP2833x_common/include/DSP2833x_I2c_defines.h b/v120/DSP2833x_common/include/DSP2833x_I2c_defines.h
new file mode 100644
index 0000000..ce3f1f7
--- /dev/null
+++ b/v120/DSP2833x_common/include/DSP2833x_I2c_defines.h
@@ -0,0 +1,117 @@
+// TI File $Revision: /main/2 $
+// Checkin $Date: April 16, 2008 17:16:47 $
+//###########################################################################
+//
+// FILE: DSP2833x_I2cExample.h
+//
+// TITLE: 2833x I2C Example Code Definitions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#ifndef DSP2833x_I2C_DEFINES_H
+#define DSP2833x_I2C_DEFINES_H
+
+//--------------------------------------------
+// Defines
+//--------------------------------------------
+
+// Error Messages
+#define I2C_ERROR 0xFFFF
+#define I2C_ARB_LOST_ERROR 0x0001
+#define I2C_NACK_ERROR 0x0002
+#define I2C_BUS_BUSY_ERROR 0x1000
+#define I2C_STP_NOT_READY_ERROR 0x5555
+#define I2C_NO_FLAGS 0xAAAA
+#define I2C_SUCCESS 0x0000
+
+// Clear Status Flags
+#define I2C_CLR_AL_BIT 0x0001
+#define I2C_CLR_NACK_BIT 0x0002
+#define I2C_CLR_ARDY_BIT 0x0004
+#define I2C_CLR_RRDY_BIT 0x0008
+#define I2C_CLR_SCD_BIT 0x0020
+
+// Interrupt Source Messages
+#define I2C_NO_ISRC 0x0000
+#define I2C_ARB_ISRC 0x0001
+#define I2C_NACK_ISRC 0x0002
+#define I2C_ARDY_ISRC 0x0003
+#define I2C_RX_ISRC 0x0004
+#define I2C_TX_ISRC 0x0005
+#define I2C_SCD_ISRC 0x0006
+#define I2C_AAS_ISRC 0x0007
+
+// I2CMSG structure defines
+#define I2C_NO_STOP 0
+#define I2C_YES_STOP 1
+#define I2C_RECEIVE 0
+#define I2C_TRANSMIT 1
+#define I2C_MAX_BUFFER_SIZE 16
+
+// I2C Slave State defines
+#define I2C_NOTSLAVE 0
+#define I2C_ADDR_AS_SLAVE 1
+#define I2C_ST_MSG_READY 2
+
+// I2C Slave Receiver messages defines
+#define I2C_SND_MSG1 1
+#define I2C_SND_MSG2 2
+
+// I2C State defines
+#define I2C_IDLE 0
+#define I2C_SLAVE_RECEIVER 1
+#define I2C_SLAVE_TRANSMITTER 2
+#define I2C_MASTER_RECEIVER 3
+#define I2C_MASTER_TRANSMITTER 4
+
+// I2C Message Commands for I2CMSG struct
+#define I2C_MSGSTAT_INACTIVE 0x0000
+#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010
+#define I2C_MSGSTAT_WRITE_BUSY 0x0011
+#define I2C_MSGSTAT_SEND_NOSTOP 0x0020
+#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021
+#define I2C_MSGSTAT_RESTART 0x0022
+#define I2C_MSGSTAT_READ_BUSY 0x0023
+
+// Generic defines
+#define I2C_TRUE 1
+#define I2C_FALSE 0
+#define I2C_YES 1
+#define I2C_NO 0
+#define I2C_DUMMY_BYTE 0
+
+
+//--------------------------------------------
+// Structures
+//--------------------------------------------
+
+// I2C Message Structure
+struct I2CMSG {
+ Uint16 MsgStatus; // Word stating what state msg is in:
+ // I2C_MSGCMD_INACTIVE = do not send msg
+ // I2C_MSGCMD_BUSY = msg start has been sent,
+ // awaiting stop
+ // I2C_MSGCMD_SEND_WITHSTOP = command to send
+ // master trans msg complete with a stop bit
+ // I2C_MSGCMD_SEND_NOSTOP = command to send
+ // master trans msg without the stop bit
+ // I2C_MSGCMD_RESTART = command to send a restart
+ // as a master receiver with a stop bit
+ Uint16 SlaveAddress; // I2C address of slave msg is intended for
+ Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer)
+ Uint16 MemoryHighAddr; // EEPROM address of data associated with msg (high byte)
+ Uint16 MemoryLowAddr; // EEPROM address of data associated with msg (low byte)
+ Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; // Array holding msg data - max that
+ // MAX_BUFFER_SIZE can be is 16 due to
+ // the FIFO's
+};
+
+
+#endif // end of DSP2833x_I2C_DEFINES_H definition
+
+//===========================================================================
+// End of file.
+//===========================================================================
diff --git a/v120/DSP2833x_common/include/DSP2833x_SWPrioritizedIsrLevels.h b/v120/DSP2833x_common/include/DSP2833x_SWPrioritizedIsrLevels.h
new file mode 100644
index 0000000..c3f3ea1
--- /dev/null
+++ b/v120/DSP2833x_common/include/DSP2833x_SWPrioritizedIsrLevels.h
@@ -0,0 +1,5850 @@
+// TI File $Revision: /main/2 $
+// Checkin $Date: April 4, 2007 14:25:21 $
+//###########################################################################
+//
+// FILE: DSP2833x_SWPrioritizedIsrLevels.h
+//
+// TITLE: DSP28 Devices Software Prioritized Interrupt Service Routine
+// Level definitions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#ifndef DSP2833x_SW_PRIORITZIED_ISR_H
+#define DSP2833x_SW_PRIORITZIED_ISR_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//-------------------------------------------------------------------------------
+// Interrupt Enable Register Allocation For 2833x Devices:
+//-------------------------------------------------------------------------------
+// Interrupts can be enabled/disabled using the CPU interrupt enable register
+// (IER) and the PIE interrupt enable registers (PIEIER1 to PIEIER12).
+//-------------------------------------------------------------------------------
+//-------------------------------------------------------------------------------
+// Set "Global" Interrupt Priority Level (IER register):
+//-------------------------------------------------------------------------------
+// The user must set the appropriate priority level for each of the CPU
+// interrupts. This is termed as the "global" priority. The priority level
+// must be a number between 1 (highest) to 16 (lowest). A value of 0 must
+// be entered for reserved interrupts or interrupts that are not used. This
+// will also reduce code size by not including ISR's that are not used.
+//
+// Note: The priority levels below are used to calculate the IER register
+// interrupt masks MINT1 to MINT16.
+//
+//
+// Note: The priority levels shown here may not make sense in a
+// real application. This is for demonstration purposes only!!!
+//
+// The user should change these to values that make sense for
+// their application.
+//
+// 0 = not used
+// 1 = highest priority
+// ...
+// 16 = lowest priority
+#define INT1PL 2 // Group1 Interrupts (PIEIER1)
+#define INT2PL 0 // Group2 Interrupts (PIEIER2)
+#define INT3PL 4 // Group3 Interrupts (PIEIER3)
+#define INT4PL 2 // Group4 Interrupts (PIEIER4)
+#define INT5PL 2 // Group5 Interrupts (PIEIER5)
+#define INT6PL 3 // Group6 Interrupts (PIEIER6)
+#define INT7PL 0 // reserved
+#define INT8PL 0 // reserved
+#define INT9PL 1 // Group9 Interrupts (PIEIER9)
+#define INT10PL 0 // reserved
+#define INT11PL 0 // reserved
+#define INT12PL 0 // reserved
+#define INT13PL 4 // XINT13
+#define INT14PL 4 // INT14 (TINT2)
+#define INT15PL 4 // DATALOG
+#define INT16PL 4 // RTOSINT
+
+//-------------------------------------------------------------------------------
+// Set "Group" Interrupt Priority Level (PIEIER1 to PIEIER12 registers):
+//-------------------------------------------------------------------------------
+// The user must set the appropriate priority level for each of the PIE
+// interrupts. This is termed as the "group" priority. The priority level
+// must be a number between 1 (highest) to 8 (lowest). A value of 0 must
+// be entered for reserved interrupts or interrupts that are not used. This
+// will also reduce code size by not including ISR's that are not used:
+//
+// Note: The priority levels below are used to calculate the following
+// PIEIER register interrupt masks:
+// MG11 to MG18
+// MG21 to MG28
+// MG31 to MG38
+// MG41 to MG48
+// MG51 to MG58
+// MG61 to MG68
+// MG71 to MG78
+// MG81 to MG88
+// MG91 to MG98
+// MG101 to MG108
+// MG111 to MG118
+// MG121 to MG128
+//
+// Note: The priority levels shown here may not make sense in a
+// real application. This is for demonstration purposes only!!!
+//
+// The user should change these to values that make sense for
+// their application.
+//
+// 0 = not used
+// 1 = highest priority
+// ...
+// 8 = lowest priority
+//
+#define G11PL 7 // SEQ1INT (ADC)
+#define G12PL 6 // SEQ2INT (ADC)
+#define G13PL 0 // reserved
+#define G14PL 1 // XINT1 (External)
+#define G15PL 3 // XINT2 (External)
+#define G16PL 2 // ADCINT (ADC)
+#define G17PL 1 // TINT0 (CPU Timer 0)
+#define G18PL 5 // WAKEINT (WD/LPM)
+
+#define G21PL 4 // EPWM1_TZINT (ePWM1 Trip)
+#define G22PL 3 // EPWM2_TZINT (ePWM2 Trip)
+#define G23PL 2 // EPWM3_TZINT (ePWM3 Trip)
+#define G24PL 1 // EPWM4_TZINT (ePWM4 Trip)
+#define G25PL 5 // EPWM5_TZINT (ePWM5 Trip)
+#define G26PL 6 // EPWM6_TZINT (ePWM6 Trip)
+#define G27PL 0 // reserved
+#define G28PL 0 // reserved
+
+#define G31PL 4 // EPWM1_INT (ePWM1 Int)
+#define G32PL 1 // EPWM2_INT (ePWM2 Int)
+#define G33PL 1 // EPWM3_INT (ePWM3 Int)
+#define G34PL 2 // EPWM4_INT (ePWM4 Int)
+#define G35PL 2 // EPWM5_INT (ePWM5 Int)
+#define G36PL 1 // EPWM6_INT (ePWM6 Int)
+#define G37PL 0 // reserved
+#define G38PL 0 // reserved
+
+#define G41PL 2 // ECAP1_INT (eCAP1 Int)
+#define G42PL 1 // ECAP2_INT (eCAP2 Int)
+#define G43PL 3 // ECAP3_INT (eCAP3 Int)
+#define G44PL 3 // ECAP4_INT (eCAP4 Int)
+#define G45PL 5 // ECAP5_INT (eCAP5 Int)
+#define G46PL 5 // ECAP6_INT (eCAP6 Int)
+#define G47PL 0 // reserved
+#define G48PL 0 // reserved
+
+#define G51PL 2 // EQEP1_INT (eQEP1 Int)
+#define G52PL 1 // EQEP2_INT (eQEP2 Int)
+#define G53PL 0 // reserved
+#define G54PL 0 // reserved
+#define G55PL 0 // reserved
+#define G56PL 0 // reserved
+#define G57PL 0 // reserved
+#define G58PL 0 // reserved
+
+#define G61PL 3 // SPIRXINTA (SPI-A)
+#define G62PL 1 // SPITXINTA (SPI-A)
+#define G63PL 4 // MRINTB (McBSP-B)
+#define G64PL 6 // MXINTB (McBSP-B)
+#define G65PL 2 // MRINTA (McBSP-A)
+#define G66PL 1 // MXINTA (McBSP-A)
+#define G67PL 0 // reserved
+#define G68PL 0 // reserved
+
+#define G71PL 5 // DINTCH1 (DMA)
+#define G72PL 4 // DINTCH2 (DMA)
+#define G73PL 4 // DINTCH3 (DMA)
+#define G74PL 2 // DINTCH4 (DMA)
+#define G75PL 3 // DINTCH5 (DMA)
+#define G76PL 1 // DINTCH6 (DMA)
+#define G77PL 0 // reserved
+#define G78PL 0 // reserved
+
+#define G81PL 1 // I2CINT1A (I2C-A)
+#define G82PL 2 // I2CINT2A (I2C-A)
+#define G83PL 0 // reserved
+#define G84PL 0 // reserved
+#define G85PL 4 // SCIRXINTC (SCI-C)
+#define G86PL 3 // SCITXINTC (SCI-C)
+#define G87PL 0 // reserved
+#define G88PL 0 // reserved
+
+#define G91PL 1 // SCIRXINTA (SCI-A)
+#define G92PL 5 // SCITXINTA (SCI-A)
+#define G93PL 3 // SCIRXINTB (SCI-B)
+#define G94PL 4 // SCITXINTB (SCI-B)
+#define G95PL 1 // ECAN0INTA (ECAN-A)
+#define G96PL 1 // ECAN1INTA (ECAN-A)
+#define G97PL 2 // ECAN0INTB (ECAN-B)
+#define G98PL 4 // ECAN1INTB (ECAN-B)
+
+#define G101PL 0 // reserved
+#define G102PL 0 // reserved
+#define G103PL 0 // reserved
+#define G104PL 0 // reserved
+#define G105PL 0 // reserved
+#define G106PL 0 // reserved
+#define G107PL 0 // reserved
+#define G108PL 0 // reserved
+
+#define G111PL 0 // reserved
+#define G112PL 0 // reserved
+#define G113PL 0 // reserved
+#define G114PL 0 // reserved
+#define G115PL 0 // reserved
+#define G116PL 0 // reserved
+#define G117PL 0 // reserved
+#define G118PL 0 // reserved
+
+#define G121PL 5 // XINT3 (External)
+#define G122PL 3 // XINT4 (External)
+#define G123PL 2 // XINT5 (External)
+#define G124PL 2 // XINT6 (External)
+#define G125PL 1 // XINT7 (External)
+#define G126PL 0 // reserved
+#define G127PL 6 // LVF (FPA32)
+#define G128PL 1 // LUF (FPA32)
+
+
+// There should be no need to modify code below this line
+//-------------------------------------------------------------------------------
+// Automatically generate IER interrupt masks MINT1 to MINT16:
+//
+
+// Beginning of MINT1:
+#if (INT1PL == 0)
+#define MINT1_1PL ~(1 << 0)
+#else
+#define MINT1_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT1PL) || (INT2PL == 0)
+#define MINT1_2PL ~(1 << 1)
+#else
+#define MINT1_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT1PL) || (INT3PL == 0)
+#define MINT1_3PL ~(1 << 2)
+#else
+#define MINT1_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT1PL) || (INT4PL == 0)
+#define MINT1_4PL ~(1 << 3)
+#else
+#define MINT1_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT1PL) || (INT5PL == 0)
+#define MINT1_5PL ~(1 << 4)
+#else
+#define MINT1_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT1PL) || (INT6PL == 0)
+#define MINT1_6PL ~(1 << 5)
+#else
+#define MINT1_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT1PL) || (INT7PL == 0)
+#define MINT1_7PL ~(1 << 6)
+#else
+#define MINT1_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT1PL) || (INT8PL == 0)
+#define MINT1_8PL ~(1 << 7)
+#else
+#define MINT1_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT1PL) || (INT9PL == 0)
+#define MINT1_9PL ~(1 << 8)
+#else
+#define MINT1_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT1PL) || (INT10PL == 0)
+#define MINT1_10PL ~(1 << 9)
+#else
+#define MINT1_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT1PL) || (INT11PL == 0)
+#define MINT1_11PL ~(1 << 10)
+#else
+#define MINT1_11PL 0xFFFF
+#endif
+
+#if (INT12PL >= INT1PL) || (INT12PL == 0)
+#define MINT1_12PL ~(1 << 11)
+#else
+#define MINT1_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT1PL) || (INT13PL == 0)
+#define MINT1_13PL ~(1 << 12)
+#else
+#define MINT1_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT1PL) || (INT14PL == 0)
+#define MINT1_14PL ~(1 << 13)
+#else
+#define MINT1_14PL 0xFFFF
+#endif
+
+#if (INT15PL >= INT1PL) || (INT15PL == 0)
+#define MINT1_15PL ~(1 << 14)
+#else
+#define MINT1_15PL 0xFFFF
+#endif
+
+#if (INT16PL >= INT1PL) || (INT16PL == 0)
+#define MINT1_16PL ~(1 << 15)
+#else
+#define MINT1_16PL 0xFFFF
+#endif
+
+#define MINT1 (MINT1_1PL & MINT1_2PL & MINT1_3PL & MINT1_4PL & \
+ MINT1_5PL & MINT1_6PL & MINT1_7PL & MINT1_8PL & \
+ MINT1_9PL & MINT1_10PL & MINT1_11PL & MINT1_12PL & \
+ MINT1_13PL & MINT1_14PL & MINT1_15PL & MINT1_16PL)
+// End Of MINT1.
+
+// Beginning of MINT2:
+#if (INT1PL >= INT2PL) || (INT1PL == 0)
+#define MINT2_1PL ~(1 << 0)
+#else
+#define MINT2_1PL 0xFFFF
+#endif
+
+#if (INT2PL == 0)
+#define MINT2_2PL ~(1 << 1)
+#else
+#define MINT2_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT2PL) || (INT3PL == 0)
+#define MINT2_3PL ~(1 << 2)
+#else
+#define MINT2_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT2PL) || (INT4PL == 0)
+#define MINT2_4PL ~(1 << 3)
+#else
+#define MINT2_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT2PL) || (INT5PL == 0)
+#define MINT2_5PL ~(1 << 4)
+#else
+#define MINT2_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT2PL) || (INT6PL == 0)
+#define MINT2_6PL ~(1 << 5)
+#else
+#define MINT2_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT2PL) || (INT7PL == 0)
+#define MINT2_7PL ~(1 << 6)
+#else
+#define MINT2_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT2PL) || (INT8PL == 0)
+#define MINT2_8PL ~(1 << 7)
+#else
+#define MINT2_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT2PL) || (INT9PL == 0)
+#define MINT2_9PL ~(1 << 8)
+#else
+#define MINT2_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT2PL) || (INT10PL == 0)
+#define MINT2_10PL ~(1 << 9)
+#else
+#define MINT2_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT2PL) || (INT11PL == 0)
+#define MINT2_11PL ~(1 << 10)
+#else
+#define MINT2_11PL 0xFFFF
+#endif
+
+#if (INT12PL >= INT2PL) || (INT12PL == 0)
+#define MINT2_12PL ~(1 << 11)
+#else
+#define MINT2_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT2PL) || (INT13PL == 0)
+#define MINT2_13PL ~(1 << 12)
+#else
+#define MINT2_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT2PL) || (INT14PL == 0)
+#define MINT2_14PL ~(1 << 13)
+#else
+#define MINT2_14PL 0xFFFF
+#endif
+
+#if (INT15PL >= INT2PL) || (INT15PL == 0)
+#define MINT2_15PL ~(1 << 14)
+#else
+#define MINT2_15PL 0xFFFF
+#endif
+
+#if (INT16PL >= INT2PL) || (INT16PL == 0)
+#define MINT2_16PL ~(1 << 15)
+#else
+#define MINT2_16PL 0xFFFF
+#endif
+
+#define MINT2 (MINT2_1PL & MINT2_2PL & MINT2_3PL & MINT2_4PL & \
+ MINT2_5PL & MINT2_6PL & MINT2_7PL & MINT2_8PL & \
+ MINT2_9PL & MINT2_10PL & MINT2_11PL & MINT2_12PL & \
+ MINT2_13PL & MINT2_14PL & MINT2_15PL & MINT2_16PL)
+// End Of MINT2.
+
+// Beginning of MINT3:
+#if (INT1PL >= INT3PL) || (INT1PL == 0)
+#define MINT3_1PL ~(1 << 0)
+#else
+#define MINT3_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT3PL) || (INT2PL == 0)
+#define MINT3_2PL ~(1 << 1)
+#else
+#define MINT3_2PL 0xFFFF
+#endif
+
+#if (INT3PL == 0)
+#define MINT3_3PL ~(1 << 2)
+#else
+#define MINT3_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT3PL) || (INT4PL == 0)
+#define MINT3_4PL ~(1 << 3)
+#else
+#define MINT3_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT3PL) || (INT5PL == 0)
+#define MINT3_5PL ~(1 << 4)
+#else
+#define MINT3_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT3PL) || (INT6PL == 0)
+#define MINT3_6PL ~(1 << 5)
+#else
+#define MINT3_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT3PL) || (INT7PL == 0)
+#define MINT3_7PL ~(1 << 6)
+#else
+#define MINT3_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT3PL) || (INT8PL == 0)
+#define MINT3_8PL ~(1 << 7)
+#else
+#define MINT3_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT3PL) || (INT9PL == 0)
+#define MINT3_9PL ~(1 << 8)
+#else
+#define MINT3_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT3PL) || (INT10PL == 0)
+#define MINT3_10PL ~(1 << 9)
+#else
+#define MINT3_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT3PL) || (INT11PL == 0)
+#define MINT3_11PL ~(1 << 10)
+#else
+#define MINT3_11PL 0xFFFF
+#endif
+
+#if (INT12PL >= INT3PL) || (INT12PL == 0)
+#define MINT3_12PL ~(1 << 11)
+#else
+#define MINT3_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT3PL) || (INT13PL == 0)
+#define MINT3_13PL ~(1 << 12)
+#else
+#define MINT3_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT3PL) || (INT14PL == 0)
+#define MINT3_14PL ~(1 << 13)
+#else
+#define MINT3_14PL 0xFFFF
+#endif
+
+#if (INT15PL >= INT3PL) || (INT15PL == 0)
+#define MINT3_15PL ~(1 << 14)
+#else
+#define MINT3_15PL 0xFFFF
+#endif
+
+#if (INT16PL >= INT3PL) || (INT16PL == 0)
+#define MINT3_16PL ~(1 << 15)
+#else
+#define MINT3_16PL 0xFFFF
+#endif
+
+#define MINT3 (MINT3_1PL & MINT3_2PL & MINT3_3PL & MINT3_4PL & \
+ MINT3_5PL & MINT3_6PL & MINT3_7PL & MINT3_8PL & \
+ MINT3_9PL & MINT3_10PL & MINT3_11PL & MINT3_12PL & \
+ MINT3_13PL & MINT3_14PL & MINT3_15PL & MINT3_16PL)
+// End Of MINT3.
+
+// Beginning of MINT4:
+#if (INT1PL >= INT4PL) || (INT1PL == 0)
+#define MINT4_1PL ~(1 << 0)
+#else
+#define MINT4_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT4PL) || (INT2PL == 0)
+#define MINT4_2PL ~(1 << 1)
+#else
+#define MINT4_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT4PL) || (INT3PL == 0)
+#define MINT4_3PL ~(1 << 2)
+#else
+#define MINT4_3PL 0xFFFF
+#endif
+
+#if (INT4PL == 0)
+#define MINT4_4PL ~(1 << 3)
+#else
+#define MINT4_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT4PL) || (INT5PL == 0)
+#define MINT4_5PL ~(1 << 4)
+#else
+#define MINT4_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT4PL) || (INT6PL == 0)
+#define MINT4_6PL ~(1 << 5)
+#else
+#define MINT4_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT4PL) || (INT7PL == 0)
+#define MINT4_7PL ~(1 << 6)
+#else
+#define MINT4_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT4PL) || (INT8PL == 0)
+#define MINT4_8PL ~(1 << 7)
+#else
+#define MINT4_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT4PL) || (INT9PL == 0)
+#define MINT4_9PL ~(1 << 8)
+#else
+#define MINT4_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT4PL) || (INT10PL == 0)
+#define MINT4_10PL ~(1 << 9)
+#else
+#define MINT4_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT4PL) || (INT11PL == 0)
+#define MINT4_11PL ~(1 << 10)
+#else
+#define MINT4_11PL 0xFFFF
+#endif
+
+#if (INT12PL >= INT4PL) || (INT12PL == 0)
+#define MINT4_12PL ~(1 << 11)
+#else
+#define MINT4_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT4PL) || (INT13PL == 0)
+#define MINT4_13PL ~(1 << 12)
+#else
+#define MINT4_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT4PL) || (INT14PL == 0)
+#define MINT4_14PL ~(1 << 13)
+#else
+#define MINT4_14PL 0xFFFF
+#endif
+
+#if (INT15PL >= INT4PL) || (INT15PL == 0)
+#define MINT4_15PL ~(1 << 14)
+#else
+#define MINT4_15PL 0xFFFF
+#endif
+
+#if (INT16PL >= INT4PL) || (INT16PL == 0)
+#define MINT4_16PL ~(1 << 15)
+#else
+#define MINT4_16PL 0xFFFF
+#endif
+
+#define MINT4 (MINT4_1PL & MINT4_2PL & MINT4_3PL & MINT4_4PL & \
+ MINT4_5PL & MINT4_6PL & MINT4_7PL & MINT4_8PL & \
+ MINT4_9PL & MINT4_10PL & MINT4_11PL & MINT4_12PL & \
+ MINT4_13PL & MINT4_14PL & MINT4_15PL & MINT4_16PL)
+// End Of MINT4.
+
+// Beginning of MINT5:
+#if (INT1PL >= INT5PL) || (INT1PL == 0)
+#define MINT5_1PL ~(1 << 0)
+#else
+#define MINT5_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT5PL) || (INT2PL == 0)
+#define MINT5_2PL ~(1 << 1)
+#else
+#define MINT5_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT5PL) || (INT3PL == 0)
+#define MINT5_3PL ~(1 << 2)
+#else
+#define MINT5_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT5PL) || (INT4PL == 0)
+#define MINT5_4PL ~(1 << 3)
+#else
+#define MINT5_4PL 0xFFFF
+#endif
+
+#if (INT5PL == 0)
+#define MINT5_5PL ~(1 << 4)
+#else
+#define MINT5_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT5PL) || (INT6PL == 0)
+#define MINT5_6PL ~(1 << 5)
+#else
+#define MINT5_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT5PL) || (INT7PL == 0)
+#define MINT5_7PL ~(1 << 6)
+#else
+#define MINT5_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT5PL) || (INT8PL == 0)
+#define MINT5_8PL ~(1 << 7)
+#else
+#define MINT5_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT5PL) || (INT9PL == 0)
+#define MINT5_9PL ~(1 << 8)
+#else
+#define MINT5_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT5PL) || (INT10PL == 0)
+#define MINT5_10PL ~(1 << 9)
+#else
+#define MINT5_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT5PL) || (INT11PL == 0)
+#define MINT5_11PL ~(1 << 10)
+#else
+#define MINT5_11PL 0xFFFF
+#endif
+
+#if (INT12PL >= INT5PL) || (INT12PL == 0)
+#define MINT5_12PL ~(1 << 11)
+#else
+#define MINT5_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT5PL) || (INT13PL == 0)
+#define MINT5_13PL ~(1 << 12)
+#else
+#define MINT5_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT5PL) || (INT14PL == 0)
+#define MINT5_14PL ~(1 << 13)
+#else
+#define MINT5_14PL 0xFFFF
+#endif
+
+#if (INT15PL >= INT5PL) || (INT15PL == 0)
+#define MINT5_15PL ~(1 << 14)
+#else
+#define MINT5_15PL 0xFFFF
+#endif
+
+#if (INT16PL >= INT5PL) || (INT16PL == 0)
+#define MINT5_16PL ~(1 << 15)
+#else
+#define MINT5_16PL 0xFFFF
+#endif
+
+#define MINT5 (MINT5_1PL & MINT5_2PL & MINT5_3PL & MINT5_4PL & \
+ MINT5_5PL & MINT5_6PL & MINT5_7PL & MINT5_8PL & \
+ MINT5_9PL & MINT5_10PL & MINT5_11PL & MINT5_12PL & \
+ MINT5_13PL & MINT5_14PL & MINT5_15PL & MINT5_16PL)
+// End Of MINT5.
+
+// Beginning of MINT6:
+#if (INT1PL >= INT6PL) || (INT1PL == 0)
+#define MINT6_1PL ~(1 << 0)
+#else
+#define MINT6_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT6PL) || (INT2PL == 0)
+#define MINT6_2PL ~(1 << 1)
+#else
+#define MINT6_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT6PL) || (INT3PL == 0)
+#define MINT6_3PL ~(1 << 2)
+#else
+#define MINT6_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT6PL) || (INT4PL == 0)
+#define MINT6_4PL ~(1 << 3)
+#else
+#define MINT6_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT6PL) || (INT5PL == 0)
+#define MINT6_5PL ~(1 << 4)
+#else
+#define MINT6_5PL 0xFFFF
+#endif
+
+#if (INT6PL == 0)
+#define MINT6_6PL ~(1 << 5)
+#else
+#define MINT6_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT6PL) || (INT7PL == 0)
+#define MINT6_7PL ~(1 << 6)
+#else
+#define MINT6_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT6PL) || (INT8PL == 0)
+#define MINT6_8PL ~(1 << 7)
+#else
+#define MINT6_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT6PL) || (INT9PL == 0)
+#define MINT6_9PL ~(1 << 8)
+#else
+#define MINT6_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT6PL) || (INT10PL == 0)
+#define MINT6_10PL ~(1 << 9)
+#else
+#define MINT6_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT6PL) || (INT11PL == 0)
+#define MINT6_11PL ~(1 << 10)
+#else
+#define MINT6_11PL 0xFFFF
+#endif
+
+#if (INT12PL >= INT6PL) || (INT12PL == 0)
+#define MINT6_12PL ~(1 << 11)
+#else
+#define MINT6_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT6PL) || (INT13PL == 0)
+#define MINT6_13PL ~(1 << 12)
+#else
+#define MINT6_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT6PL) || (INT14PL == 0)
+#define MINT6_14PL ~(1 << 13)
+#else
+#define MINT6_14PL 0xFFFF
+#endif
+
+#if (INT15PL >= INT6PL) || (INT15PL == 0)
+#define MINT6_15PL ~(1 << 14)
+#else
+#define MINT6_15PL 0xFFFF
+#endif
+
+#if (INT16PL >= INT6PL) || (INT16PL == 0)
+#define MINT6_16PL ~(1 << 15)
+#else
+#define MINT6_16PL 0xFFFF
+#endif
+
+#define MINT6 (MINT6_1PL & MINT6_2PL & MINT6_3PL & MINT6_4PL & \
+ MINT6_5PL & MINT6_6PL & MINT6_7PL & MINT6_8PL & \
+ MINT6_9PL & MINT6_10PL & MINT6_11PL & MINT6_12PL & \
+ MINT6_13PL & MINT6_14PL & MINT6_15PL & MINT6_16PL)
+// End Of MINT6.
+
+// Beginning of MINT7:
+#if (INT1PL >= INT7PL) || (INT1PL == 0)
+#define MINT7_1PL ~(1 << 0)
+#else
+#define MINT7_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT7PL) || (INT2PL == 0)
+#define MINT7_2PL ~(1 << 1)
+#else
+#define MINT7_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT7PL) || (INT3PL == 0)
+#define MINT7_3PL ~(1 << 2)
+#else
+#define MINT7_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT7PL) || (INT4PL == 0)
+#define MINT7_4PL ~(1 << 3)
+#else
+#define MINT7_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT7PL) || (INT5PL == 0)
+#define MINT7_5PL ~(1 << 4)
+#else
+#define MINT7_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT7PL) || (INT6PL == 0)
+#define MINT7_6PL ~(1 << 5)
+#else
+#define MINT7_6PL 0xFFFF
+#endif
+
+#if (INT7PL == 0)
+#define MINT7_7PL ~(1 << 6)
+#else
+#define MINT7_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT7PL) || (INT8PL == 0)
+#define MINT7_8PL ~(1 << 7)
+#else
+#define MINT7_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT7PL) || (INT9PL == 0)
+#define MINT7_9PL ~(1 << 8)
+#else
+#define MINT7_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT7PL) || (INT10PL == 0)
+#define MINT7_10PL ~(1 << 9)
+#else
+#define MINT7_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT7PL) || (INT11PL == 0)
+#define MINT7_11PL ~(1 << 10)
+#else
+#define MINT7_11PL 0xFFFF
+#endif
+
+#if (INT12PL >= INT7PL) || (INT12PL == 0)
+#define MINT7_12PL ~(1 << 11)
+#else
+#define MINT7_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT7PL) || (INT13PL == 0)
+#define MINT7_13PL ~(1 << 12)
+#else
+#define MINT7_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT7PL) || (INT14PL == 0)
+#define MINT7_14PL ~(1 << 13)
+#else
+#define MINT7_14PL 0xFFFF
+#endif
+
+#if (INT15PL >= INT7PL) || (INT15PL == 0)
+#define MINT7_15PL ~(1 << 14)
+#else
+#define MINT7_15PL 0xFFFF
+#endif
+
+#if (INT16PL >= INT7PL) || (INT16PL == 0)
+#define MINT7_16PL ~(1 << 15)
+#else
+#define MINT7_16PL 0xFFFF
+#endif
+
+#define MINT7 (MINT7_1PL & MINT7_2PL & MINT7_3PL & MINT7_4PL & \
+ MINT7_5PL & MINT7_6PL & MINT7_7PL & MINT7_8PL & \
+ MINT7_9PL & MINT7_10PL & MINT7_11PL & MINT7_12PL & \
+ MINT7_13PL & MINT7_14PL & MINT7_15PL & MINT7_16PL)
+// End Of MINT7.
+
+// Beginning of MINT8:
+#if (INT1PL >= INT8PL) || (INT1PL == 0)
+#define MINT8_1PL ~(1 << 0)
+#else
+#define MINT8_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT8PL) || (INT2PL == 0)
+#define MINT8_2PL ~(1 << 1)
+#else
+#define MINT8_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT8PL) || (INT3PL == 0)
+#define MINT8_3PL ~(1 << 2)
+#else
+#define MINT8_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT8PL) || (INT4PL == 0)
+#define MINT8_4PL ~(1 << 3)
+#else
+#define MINT8_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT8PL) || (INT5PL == 0)
+#define MINT8_5PL ~(1 << 4)
+#else
+#define MINT8_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT8PL) || (INT6PL == 0)
+#define MINT8_6PL ~(1 << 5)
+#else
+#define MINT8_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT8PL) || (INT7PL == 0)
+#define MINT8_7PL ~(1 << 6)
+#else
+#define MINT8_7PL 0xFFFF
+#endif
+
+#if (INT8PL == 0)
+#define MINT8_8PL ~(1 << 7)
+#else
+#define MINT8_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT8PL) || (INT9PL == 0)
+#define MINT8_9PL ~(1 << 8)
+#else
+#define MINT8_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT8PL) || (INT10PL == 0)
+#define MINT8_10PL ~(1 << 9)
+#else
+#define MINT8_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT8PL) || (INT11PL == 0)
+#define MINT8_11PL ~(1 << 10)
+#else
+#define MINT8_11PL 0xFFFF
+#endif
+
+#if (INT12PL >= INT8PL) || (INT12PL == 0)
+#define MINT8_12PL ~(1 << 11)
+#else
+#define MINT8_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT8PL) || (INT13PL == 0)
+#define MINT8_13PL ~(1 << 12)
+#else
+#define MINT8_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT8PL) || (INT14PL == 0)
+#define MINT8_14PL ~(1 << 13)
+#else
+#define MINT8_14PL 0xFFFF
+#endif
+
+#if (INT15PL >= INT8PL) || (INT15PL == 0)
+#define MINT8_15PL ~(1 << 14)
+#else
+#define MINT8_15PL 0xFFFF
+#endif
+
+#if (INT16PL >= INT8PL) || (INT16PL == 0)
+#define MINT8_16PL ~(1 << 15)
+#else
+#define MINT8_16PL 0xFFFF
+#endif
+
+#define MINT8 (MINT8_1PL & MINT8_2PL & MINT8_3PL & MINT8_4PL & \
+ MINT8_5PL & MINT8_6PL & MINT8_7PL & MINT8_8PL & \
+ MINT8_9PL & MINT8_10PL & MINT8_11PL & MINT8_12PL & \
+ MINT8_13PL & MINT8_14PL & MINT8_15PL & MINT8_16PL)
+// End Of MINT8.
+
+// Beginning of MINT9:
+#if (INT1PL >= INT9PL) || (INT1PL == 0)
+#define MINT9_1PL ~(1 << 0)
+#else
+#define MINT9_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT9PL) || (INT2PL == 0)
+#define MINT9_2PL ~(1 << 1)
+#else
+#define MINT9_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT9PL) || (INT3PL == 0)
+#define MINT9_3PL ~(1 << 2)
+#else
+#define MINT9_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT9PL) || (INT4PL == 0)
+#define MINT9_4PL ~(1 << 3)
+#else
+#define MINT9_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT9PL) || (INT5PL == 0)
+#define MINT9_5PL ~(1 << 4)
+#else
+#define MINT9_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT9PL) || (INT6PL == 0)
+#define MINT9_6PL ~(1 << 5)
+#else
+#define MINT9_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT9PL) || (INT7PL == 0)
+#define MINT9_7PL ~(1 << 6)
+#else
+#define MINT9_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT9PL) || (INT8PL == 0)
+#define MINT9_8PL ~(1 << 7)
+#else
+#define MINT9_8PL 0xFFFF
+#endif
+
+#if (INT9PL == 0)
+#define MINT9_9PL ~(1 << 8)
+#else
+#define MINT9_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT9PL) || (INT10PL == 0)
+#define MINT9_10PL ~(1 << 9)
+#else
+#define MINT9_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT9PL) || (INT11PL == 0)
+#define MINT9_11PL ~(1 << 10)
+#else
+#define MINT9_11PL 0xFFFF
+#endif
+
+#if (INT12PL >= INT9PL) || (INT12PL == 0)
+#define MINT9_12PL ~(1 << 11)
+#else
+#define MINT9_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT9PL) || (INT13PL == 0)
+#define MINT9_13PL ~(1 << 12)
+#else
+#define MINT9_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT9PL) || (INT14PL == 0)
+#define MINT9_14PL ~(1 << 13)
+#else
+#define MINT9_14PL 0xFFFF
+#endif
+
+#if (INT15PL >= INT9PL) || (INT15PL == 0)
+#define MINT9_15PL ~(1 << 14)
+#else
+#define MINT9_15PL 0xFFFF
+#endif
+
+#if (INT16PL >= INT9PL) || (INT16PL == 0)
+#define MINT9_16PL ~(1 << 15)
+#else
+#define MINT9_16PL 0xFFFF
+#endif
+
+#define MINT9 (MINT9_1PL & MINT9_2PL & MINT9_3PL & MINT9_4PL & \
+ MINT9_5PL & MINT9_6PL & MINT9_7PL & MINT9_8PL & \
+ MINT9_9PL & MINT9_10PL & MINT9_11PL & MINT9_12PL & \
+ MINT9_13PL & MINT9_14PL & MINT9_15PL & MINT9_16PL)
+// End Of MINT9.
+
+// Beginning of MINT10:
+#if (INT1PL >= INT10PL) || (INT1PL == 0)
+#define MINT10_1PL ~(1 << 0)
+#else
+#define MINT10_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT10PL) || (INT2PL == 0)
+#define MINT10_2PL ~(1 << 1)
+#else
+#define MINT10_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT10PL) || (INT3PL == 0)
+#define MINT10_3PL ~(1 << 2)
+#else
+#define MINT10_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT10PL) || (INT4PL == 0)
+#define MINT10_4PL ~(1 << 3)
+#else
+#define MINT10_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT10PL) || (INT5PL == 0)
+#define MINT10_5PL ~(1 << 4)
+#else
+#define MINT10_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT10PL) || (INT6PL == 0)
+#define MINT10_6PL ~(1 << 5)
+#else
+#define MINT10_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT10PL) || (INT7PL == 0)
+#define MINT10_7PL ~(1 << 6)
+#else
+#define MINT10_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT10PL) || (INT8PL == 0)
+#define MINT10_8PL ~(1 << 7)
+#else
+#define MINT10_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT10PL) || (INT9PL == 0)
+#define MINT10_9PL ~(1 << 8)
+#else
+#define MINT10_9PL 0xFFFF
+#endif
+
+#if (INT10PL == 0)
+#define MINT10_10PL ~(1 << 9)
+#else
+#define MINT10_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT10PL) || (INT11PL == 0)
+#define MINT10_11PL ~(1 << 10)
+#else
+#define MINT10_11PL 0xFFFF
+#endif
+
+#if (INT12PL >= INT10PL) || (INT12PL == 0)
+#define MINT10_12PL ~(1 << 11)
+#else
+#define MINT10_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT10PL) || (INT13PL == 0)
+#define MINT10_13PL ~(1 << 12)
+#else
+#define MINT10_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT10PL) || (INT14PL == 0)
+#define MINT10_14PL ~(1 << 13)
+#else
+#define MINT10_14PL 0xFFFF
+#endif
+
+#if (INT15PL >= INT10PL) || (INT15PL == 0)
+#define MINT10_15PL ~(1 << 14)
+#else
+#define MINT10_15PL 0xFFFF
+#endif
+
+#if (INT16PL >= INT10PL) || (INT16PL == 0)
+#define MINT10_16PL ~(1 << 15)
+#else
+#define MINT10_16PL 0xFFFF
+#endif
+
+#define MINT10 (MINT10_1PL & MINT10_2PL & MINT10_3PL & MINT10_4PL & \
+ MINT10_5PL & MINT10_6PL & MINT10_7PL & MINT10_8PL & \
+ MINT10_9PL & MINT10_10PL & MINT10_11PL & MINT10_12PL & \
+ MINT10_13PL & MINT10_14PL & MINT10_15PL & MINT10_16PL)
+// End Of MINT10.
+
+// Beginning of MINT11:
+#if (INT1PL >= INT11PL) || (INT1PL == 0)
+#define MINT11_1PL ~(1 << 0)
+#else
+#define MINT11_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT11PL) || (INT2PL == 0)
+#define MINT11_2PL ~(1 << 1)
+#else
+#define MINT11_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT11PL) || (INT3PL == 0)
+#define MINT11_3PL ~(1 << 2)
+#else
+#define MINT11_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT11PL) || (INT4PL == 0)
+#define MINT11_4PL ~(1 << 3)
+#else
+#define MINT11_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT11PL) || (INT5PL == 0)
+#define MINT11_5PL ~(1 << 4)
+#else
+#define MINT11_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT11PL) || (INT6PL == 0)
+#define MINT11_6PL ~(1 << 5)
+#else
+#define MINT11_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT11PL) || (INT7PL == 0)
+#define MINT11_7PL ~(1 << 6)
+#else
+#define MINT11_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT11PL) || (INT8PL == 0)
+#define MINT11_8PL ~(1 << 7)
+#else
+#define MINT11_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT11PL) || (INT9PL == 0)
+#define MINT11_9PL ~(1 << 8)
+#else
+#define MINT11_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT11PL) || (INT10PL == 0)
+#define MINT11_10PL ~(1 << 9)
+#else
+#define MINT11_10PL 0xFFFF
+#endif
+
+#if (INT11PL == 0)
+#define MINT11_11PL ~(1 << 10)
+#else
+#define MINT11_11PL 0xFFFF
+#endif
+
+#if (INT12PL >= INT11PL) || (INT12PL == 0)
+#define MINT11_12PL ~(1 << 11)
+#else
+#define MINT11_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT11PL) || (INT13PL == 0)
+#define MINT11_13PL ~(1 << 12)
+#else
+#define MINT11_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT11PL) || (INT14PL == 0)
+#define MINT11_14PL ~(1 << 13)
+#else
+#define MINT11_14PL 0xFFFF
+#endif
+
+#if (INT15PL >= INT11PL) || (INT15PL == 0)
+#define MINT11_15PL ~(1 << 14)
+#else
+#define MINT11_15PL 0xFFFF
+#endif
+
+#if (INT16PL >= INT11PL) || (INT16PL == 0)
+#define MINT11_16PL ~(1 << 15)
+#else
+#define MINT11_16PL 0xFFFF
+#endif
+
+#define MINT11 (MINT11_1PL & MINT11_2PL & MINT11_3PL & MINT11_4PL & \
+ MINT11_5PL & MINT11_6PL & MINT11_7PL & MINT11_8PL & \
+ MINT11_9PL & MINT11_10PL & MINT11_11PL & MINT11_12PL & \
+ MINT11_13PL & MINT11_14PL & MINT11_15PL & MINT11_16PL)
+// End Of MINT11.
+
+// Beginning of MINT12:
+#if (INT1PL >= INT12PL) || (INT1PL == 0)
+#define MINT12_1PL ~(1 << 0)
+#else
+#define MINT12_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT12PL) || (INT2PL == 0)
+#define MINT12_2PL ~(1 << 1)
+#else
+#define MINT12_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT12PL) || (INT3PL == 0)
+#define MINT12_3PL ~(1 << 2)
+#else
+#define MINT12_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT12PL) || (INT4PL == 0)
+#define MINT12_4PL ~(1 << 3)
+#else
+#define MINT12_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT12PL) || (INT5PL == 0)
+#define MINT12_5PL ~(1 << 4)
+#else
+#define MINT12_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT12PL) || (INT6PL == 0)
+#define MINT12_6PL ~(1 << 5)
+#else
+#define MINT12_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT12PL) || (INT7PL == 0)
+#define MINT12_7PL ~(1 << 6)
+#else
+#define MINT12_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT12PL) || (INT8PL == 0)
+#define MINT12_8PL ~(1 << 7)
+#else
+#define MINT12_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT12PL) || (INT9PL == 0)
+#define MINT12_9PL ~(1 << 8)
+#else
+#define MINT12_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT12PL) || (INT10PL == 0)
+#define MINT12_10PL ~(1 << 9)
+#else
+#define MINT12_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT12PL) || (INT11PL == 0)
+#define MINT12_11PL ~(1 << 10)
+#else
+#define MINT12_11PL 0xFFFF
+#endif
+
+#if (INT12PL == 0)
+#define MINT12_12PL ~(1 << 11)
+#else
+#define MINT12_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT12PL) || (INT13PL == 0)
+#define MINT12_13PL ~(1 << 12)
+#else
+#define MINT12_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT12PL) || (INT14PL == 0)
+#define MINT12_14PL ~(1 << 13)
+#else
+#define MINT12_14PL 0xFFFF
+#endif
+
+#if (INT15PL >= INT12PL) || (INT15PL == 0)
+#define MINT12_15PL ~(1 << 14)
+#else
+#define MINT12_15PL 0xFFFF
+#endif
+
+#if (INT16PL >= INT12PL) || (INT16PL == 0)
+#define MINT12_16PL ~(1 << 15)
+#else
+#define MINT12_16PL 0xFFFF
+#endif
+
+#define MINT12 (MINT12_1PL & MINT12_2PL & MINT12_3PL & MINT12_4PL & \
+ MINT12_5PL & MINT12_6PL & MINT12_7PL & MINT12_8PL & \
+ MINT12_9PL & MINT12_10PL & MINT12_11PL & MINT12_12PL & \
+ MINT12_13PL & MINT12_14PL & MINT12_15PL & MINT12_16PL)
+// End Of MINT12.
+
+// Beginning of MINT13:
+#if (INT1PL >= INT13PL) || (INT1PL == 0)
+#define MINT13_1PL ~(1 << 0)
+#else
+#define MINT13_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT13PL) || (INT2PL == 0)
+#define MINT13_2PL ~(1 << 1)
+#else
+#define MINT13_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT13PL) || (INT3PL == 0)
+#define MINT13_3PL ~(1 << 2)
+#else
+#define MINT13_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT13PL) || (INT4PL == 0)
+#define MINT13_4PL ~(1 << 3)
+#else
+#define MINT13_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT13PL) || (INT5PL == 0)
+#define MINT13_5PL ~(1 << 4)
+#else
+#define MINT13_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT13PL) || (INT6PL == 0)
+#define MINT13_6PL ~(1 << 5)
+#else
+#define MINT13_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT13PL) || (INT7PL == 0)
+#define MINT13_7PL ~(1 << 6)
+#else
+#define MINT13_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT13PL) || (INT8PL == 0)
+#define MINT13_8PL ~(1 << 7)
+#else
+#define MINT13_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT13PL) || (INT9PL == 0)
+#define MINT13_9PL ~(1 << 8)
+#else
+#define MINT13_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT13PL) || (INT10PL == 0)
+#define MINT13_10PL ~(1 << 9)
+#else
+#define MINT13_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT13PL) || (INT11PL == 0)
+#define MINT13_11PL ~(1 << 10)
+#else
+#define MINT13_11PL 0xFFFF
+#endif
+
+#define MINT13_12PL ~(1 << 11)
+
+#if (INT13PL == 0)
+#define MINT13_13PL ~(1 << 12)
+#else
+#define MINT13_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT13PL) || (INT14PL == 0)
+#define MINT13_14PL ~(1 << 13)
+#else
+#define MINT13_14PL 0xFFFF
+#endif
+
+#if (INT15PL >= INT13PL) || (INT15PL == 0)
+#define MINT13_15PL ~(1 << 14)
+#else
+#define MINT13_15PL 0xFFFF
+#endif
+
+#if (INT16PL >= INT13PL) || (INT16PL == 0)
+#define MINT13_16PL ~(1 << 15)
+#else
+#define MINT13_16PL 0xFFFF
+#endif
+
+#define MINT13 (MINT13_1PL & MINT13_2PL & MINT13_3PL & MINT13_4PL & \
+ MINT13_5PL & MINT13_6PL & MINT13_7PL & MINT13_8PL & \
+ MINT13_9PL & MINT13_10PL & MINT13_11PL & MINT13_12PL & \
+ MINT13_13PL & MINT13_14PL & MINT13_15PL & MINT13_16PL)
+// End Of MINT13.
+
+// Beginning of MINT14:
+#if (INT1PL >= INT14PL) || (INT1PL == 0)
+#define MINT14_1PL ~(1 << 0)
+#else
+#define MINT14_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT14PL) || (INT2PL == 0)
+#define MINT14_2PL ~(1 << 1)
+#else
+#define MINT14_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT14PL) || (INT3PL == 0)
+#define MINT14_3PL ~(1 << 2)
+#else
+#define MINT14_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT14PL) || (INT4PL == 0)
+#define MINT14_4PL ~(1 << 3)
+#else
+#define MINT14_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT14PL) || (INT5PL == 0)
+#define MINT14_5PL ~(1 << 4)
+#else
+#define MINT14_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT14PL) || (INT6PL == 0)
+#define MINT14_6PL ~(1 << 5)
+#else
+#define MINT14_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT14PL) || (INT7PL == 0)
+#define MINT14_7PL ~(1 << 6)
+#else
+#define MINT14_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT14PL) || (INT8PL == 0)
+#define MINT14_8PL ~(1 << 7)
+#else
+#define MINT14_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT14PL) || (INT9PL == 0)
+#define MINT14_9PL ~(1 << 8)
+#else
+#define MINT14_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT14PL) || (INT10PL == 0)
+#define MINT14_10PL ~(1 << 9)
+#else
+#define MINT14_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT14PL) || (INT11PL == 0)
+#define MINT14_11PL ~(1 << 10)
+#else
+#define MINT14_11PL 0xFFFF
+#endif
+
+#if (INT12PL >= INT14PL) || (INT12PL == 0)
+#define MINT14_12PL ~(1 << 11)
+#else
+#define MINT14_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT14PL) || (INT13PL == 0)
+#define MINT14_13PL ~(1 << 12)
+#else
+#define MINT14_13PL 0xFFFF
+#endif
+
+#define MINT14_14PL ~(1 << 13)
+
+#if (INT15PL >= INT14PL) || (INT15PL == 0)
+#define MINT14_15PL ~(1 << 14)
+#else
+#define MINT14_15PL 0xFFFF
+#endif
+
+#if (INT16PL >= INT14PL) || (INT16PL == 0)
+#define MINT14_16PL ~(1 << 15)
+#else
+#define MINT14_16PL 0xFFFF
+#endif
+
+#define MINT14 (MINT14_1PL & MINT14_2PL & MINT14_3PL & MINT14_4PL & \
+ MINT14_5PL & MINT14_6PL & MINT14_7PL & MINT14_8PL & \
+ MINT14_9PL & MINT14_10PL & MINT14_11PL & MINT14_12PL & \
+ MINT14_13PL & MINT14_14PL & MINT14_15PL & MINT14_16PL)
+// End Of MINT14.
+
+// Beginning of MINT15:
+#if (INT1PL >= INT15PL) || (INT1PL == 0)
+#define MINT15_1PL ~(1 << 0)
+#else
+#define MINT15_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT15PL) || (INT2PL == 0)
+#define MINT15_2PL ~(1 << 1)
+#else
+#define MINT15_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT15PL) || (INT3PL == 0)
+#define MINT15_3PL ~(1 << 2)
+#else
+#define MINT15_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT15PL) || (INT4PL == 0)
+#define MINT15_4PL ~(1 << 3)
+#else
+#define MINT15_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT15PL) || (INT5PL == 0)
+#define MINT15_5PL ~(1 << 4)
+#else
+#define MINT15_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT15PL) || (INT6PL == 0)
+#define MINT15_6PL ~(1 << 5)
+#else
+#define MINT15_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT15PL) || (INT7PL == 0)
+#define MINT15_7PL ~(1 << 6)
+#else
+#define MINT15_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT15PL) || (INT8PL == 0)
+#define MINT15_8PL ~(1 << 7)
+#else
+#define MINT15_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT15PL) || (INT9PL == 0)
+#define MINT15_9PL ~(1 << 8)
+#else
+#define MINT15_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT15PL) || (INT10PL == 0)
+#define MINT15_10PL ~(1 << 9)
+#else
+#define MINT15_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT15PL) || (INT11PL == 0)
+#define MINT15_11PL ~(1 << 10)
+#else
+#define MINT15_11PL 0xFFFF
+#endif
+
+#if (INT12PL >= INT15PL) || (INT12PL == 0)
+#define MINT15_12PL ~(1 << 11)
+#else
+#define MINT15_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT15PL) || (INT13PL == 0)
+#define MINT15_13PL ~(1 << 12)
+#else
+#define MINT15_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT15PL) || (INT14PL == 0)
+#define MINT15_14PL ~(1 << 13)
+#else
+#define MINT15_14PL 0xFFFF
+#endif
+
+#define MINT15_15PL ~(1 << 14)
+
+#if (INT16PL >= INT15PL) || (INT16PL == 0)
+#define MINT15_16PL ~(1 << 15)
+#else
+#define MINT15_16PL 0xFFFF
+#endif
+
+#define MINT15 (MINT15_1PL & MINT15_2PL & MINT15_3PL & MINT15_4PL & \
+ MINT15_5PL & MINT15_6PL & MINT15_7PL & MINT15_8PL & \
+ MINT15_9PL & MINT15_10PL & MINT15_11PL & MINT15_12PL & \
+ MINT15_13PL & MINT15_14PL & MINT15_15PL & MINT15_16PL)
+// End Of MINT15.
+
+// Beginning of MINT16:
+#if (INT1PL >= INT16PL) || (INT1PL == 0)
+#define MINT16_1PL ~(1 << 0)
+#else
+#define MINT16_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT16PL) || (INT2PL == 0)
+#define MINT16_2PL ~(1 << 1)
+#else
+#define MINT16_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT16PL) || (INT3PL == 0)
+#define MINT16_3PL ~(1 << 2)
+#else
+#define MINT16_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT16PL) || (INT4PL == 0)
+#define MINT16_4PL ~(1 << 3)
+#else
+#define MINT16_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT16PL) || (INT5PL == 0)
+#define MINT16_5PL ~(1 << 4)
+#else
+#define MINT16_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT16PL) || (INT6PL == 0)
+#define MINT16_6PL ~(1 << 5)
+#else
+#define MINT16_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT16PL) || (INT7PL == 0)
+#define MINT16_7PL ~(1 << 6)
+#else
+#define MINT16_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT16PL) || (INT8PL == 0)
+#define MINT16_8PL ~(1 << 7)
+#else
+#define MINT16_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT16PL) || (INT9PL == 0)
+#define MINT16_9PL ~(1 << 8)
+#else
+#define MINT16_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT16PL) || (INT10PL == 0)
+#define MINT16_10PL ~(1 << 9)
+#else
+#define MINT16_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT16PL) || (INT11PL == 0)
+#define MINT16_11PL ~(1 << 10)
+#else
+#define MINT16_11PL 0xFFFF
+#endif
+
+#if (INT12PL >= INT16PL) || (INT12PL == 0)
+#define MINT16_12PL ~(1 << 11)
+#else
+#define MINT16_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT16PL) || (INT13PL == 0)
+#define MINT16_13PL ~(1 << 12)
+#else
+#define MINT16_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT16PL) || (INT14PL == 0)
+#define MINT16_14PL ~(1 << 13)
+#else
+#define MINT16_14PL 0xFFFF
+#endif
+
+#if (INT15PL >= INT16PL) || (INT15PL == 0)
+#define MINT16_15PL ~(1 << 14)
+#else
+#define MINT16_15PL 0xFFFF
+#endif
+
+#define MINT16_16PL ~(1 << 15)
+
+#define MINT16 (MINT16_1PL & MINT16_2PL & MINT16_3PL & MINT16_4PL & \
+ MINT16_5PL & MINT16_6PL & MINT16_7PL & MINT16_8PL & \
+ MINT16_9PL & MINT16_10PL & MINT16_11PL & MINT16_12PL & \
+ MINT16_13PL & MINT16_14PL & MINT16_15PL & MINT16_16PL)
+// End Of MINT16.
+
+//-------------------------------------------------------------------------------
+// Automatically generate PIEIER1 interrupt masks MG11 to MG18:
+
+// Beginning of MG11:
+#if (G12PL >= G11PL) || (G12PL == 0)
+#define MG11_12PL ~(1 << 1)
+#else
+#define MG11_12PL 0xFFFF
+#endif
+
+#if (G13PL >= G11PL) || (G13PL == 0)
+#define MG11_13PL ~(1 << 2)
+#else
+#define MG11_13PL 0xFFFF
+#endif
+
+#if (G14PL >= G11PL) || (G14PL == 0)
+#define MG11_14PL ~(1 << 3)
+#else
+#define MG11_14PL 0xFFFF
+#endif
+
+#if (G15PL >= G11PL) || (G15PL == 0)
+#define MG11_15PL ~(1 << 4)
+#else
+#define MG11_15PL 0xFFFF
+#endif
+
+#if (G16PL >= G11PL) || (G16PL == 0)
+#define MG11_16PL ~(1 << 5)
+#else
+#define MG11_16PL 0xFFFF
+#endif
+
+#if (G17PL >= G11PL) || (G17PL == 0)
+#define MG11_17PL ~(1 << 6)
+#else
+#define MG11_17PL 0xFFFF
+#endif
+
+#if (G18PL >= G11PL) || (G18PL == 0)
+#define MG11_18PL ~(1 << 7)
+#else
+#define MG11_18PL 0xFFFF
+#endif
+
+#define MG11_11PL 0x00FE
+#define MG11 (MG11_11PL & MG11_12PL & MG11_13PL & MG11_14PL & \
+ MG11_15PL & MG11_16PL & MG11_17PL & MG11_18PL)
+// End of MG11:
+
+// Beginning of MG12:
+#if (G11PL >= G12PL) || (G11PL == 0)
+#define MG12_11PL ~(1)
+#else
+#define MG12_11PL 0xFFFF
+#endif
+#if (G13PL >= G12PL) || (G13PL == 0)
+#define MG12_13PL ~(1 << 2)
+#else
+#define MG12_13PL 0xFFFF
+#endif
+#if (G14PL >= G12PL) || (G14PL == 0)
+#define MG12_14PL ~(1 << 3)
+#else
+#define MG12_14PL 0xFFFF
+#endif
+#if (G15PL >= G12PL) || (G15PL == 0)
+#define MG12_15PL ~(1 << 4)
+#else
+#define MG12_15PL 0xFFFF
+#endif
+#if (G16PL >= G12PL) || (G16PL == 0)
+#define MG12_16PL ~(1 << 5)
+#else
+#define MG12_16PL 0xFFFF
+#endif
+#if (G17PL >= G12PL) || (G17PL == 0)
+#define MG12_17PL ~(1 << 6)
+#else
+#define MG12_17PL 0xFFFF
+#endif
+#if (G18PL >= G12PL) || (G18PL == 0)
+#define MG12_18PL ~(1 << 7)
+#else
+#define MG12_18PL 0xFFFF
+#endif
+#define MG12_12PL 0x00FD
+#define MG12 (MG12_11PL & MG12_12PL & MG12_13PL & MG12_14PL & \
+ MG12_15PL & MG12_16PL & MG12_17PL & MG12_18PL)
+// End of MG12:
+
+// Beginning of MG13:
+#if (G11PL >= G13PL) || (G11PL == 0)
+#define MG13_11PL ~(1)
+#else
+#define MG13_11PL 0xFFFF
+#endif
+#if (G12PL >= G13PL) || (G12PL == 0)
+#define MG13_12PL ~(1 << 1)
+#else
+#define MG13_12PL 0xFFFF
+#endif
+#if (G14PL >= G13PL) || (G14PL == 0)
+#define MG13_14PL ~(1 << 3)
+#else
+#define MG13_14PL 0xFFFF
+#endif
+#if (G15PL >= G13PL) || (G15PL == 0)
+#define MG13_15PL ~(1 << 4)
+#else
+#define MG13_15PL 0xFFFF
+#endif
+#if (G16PL >= G13PL) || (G16PL == 0)
+#define MG13_16PL ~(1 << 5)
+#else
+#define MG13_16PL 0xFFFF
+#endif
+#if (G17PL >= G13PL) || (G17PL == 0)
+#define MG13_17PL ~(1 << 6)
+#else
+#define MG13_17PL 0xFFFF
+#endif
+#if (G18PL >= G13PL) || (G18PL == 0)
+#define MG13_18PL ~(1 << 7)
+#else
+#define MG13_18PL 0xFFFF
+#endif
+#define MG13_13PL 0x00FB
+#define MG13 (MG13_11PL & MG13_12PL & MG13_13PL & MG13_14PL & \
+ MG13_15PL & MG13_16PL & MG13_17PL & MG13_18PL)
+// End of MG13:
+
+// Beginning of MG14:
+#if (G11PL >= G14PL) || (G11PL == 0)
+#define MG14_11PL ~(1)
+#else
+#define MG14_11PL 0xFFFF
+#endif
+#if (G12PL >= G14PL) || (G12PL == 0)
+#define MG14_12PL ~(1 << 1)
+#else
+#define MG14_12PL 0xFFFF
+#endif
+#if (G13PL >= G14PL) || (G13PL == 0)
+#define MG14_13PL ~(1 << 2)
+#else
+#define MG14_13PL 0xFFFF
+#endif
+#if (G15PL >= G14PL) || (G15PL == 0)
+#define MG14_15PL ~(1 << 4)
+#else
+#define MG14_15PL 0xFFFF
+#endif
+#if (G16PL >= G14PL) || (G16PL == 0)
+#define MG14_16PL ~(1 << 5)
+#else
+#define MG14_16PL 0xFFFF
+#endif
+#if (G17PL >= G14PL) || (G17PL == 0)
+#define MG14_17PL ~(1 << 6)
+#else
+#define MG14_17PL 0xFFFF
+#endif
+#if (G18PL >= G14PL) || (G18PL == 0)
+#define MG14_18PL ~(1 << 7)
+#else
+#define MG14_18PL 0xFFFF
+#endif
+#define MG14_14PL 0x00F7
+#define MG14 (MG14_11PL & MG14_12PL & MG14_13PL & MG14_14PL & \
+ MG14_15PL & MG14_16PL & MG14_17PL & MG14_18PL)
+// End of MG14:
+
+// Beginning of MG15:
+#if (G11PL >= G15PL) || (G11PL == 0)
+#define MG15_11PL ~(1)
+#else
+#define MG15_11PL 0xFFFF
+#endif
+#if (G12PL >= G15PL) || (G12PL == 0)
+#define MG15_12PL ~(1 << 1)
+#else
+#define MG15_12PL 0xFFFF
+#endif
+#if (G13PL >= G15PL) || (G13PL == 0)
+#define MG15_13PL ~(1 << 2)
+#else
+#define MG15_13PL 0xFFFF
+#endif
+#if (G14PL >= G15PL) || (G14PL == 0)
+#define MG15_14PL ~(1 << 3)
+#else
+#define MG15_14PL 0xFFFF
+#endif
+#if (G16PL >= G15PL) || (G16PL == 0)
+#define MG15_16PL ~(1 << 5)
+#else
+#define MG15_16PL 0xFFFF
+#endif
+#if (G17PL >= G15PL) || (G17PL == 0)
+#define MG15_17PL ~(1 << 6)
+#else
+#define MG15_17PL 0xFFFF
+#endif
+#if (G18PL >= G15PL) || (G18PL == 0)
+#define MG15_18PL ~(1 << 7)
+#else
+#define MG15_18PL 0xFFFF
+#endif
+#define MG15_15PL 0x00EF
+#define MG15 (MG15_11PL & MG15_12PL & MG15_13PL & MG15_14PL & \
+ MG15_15PL & MG15_16PL & MG15_17PL & MG15_18PL)
+// End of MG15:
+
+// Beginning of MG16:
+#if (G11PL >= G16PL) || (G11PL == 0)
+#define MG16_11PL ~(1)
+#else
+#define MG16_11PL 0xFFFF
+#endif
+#if (G12PL >= G16PL) || (G12PL == 0)
+#define MG16_12PL ~(1 << 1)
+#else
+#define MG16_12PL 0xFFFF
+#endif
+#if (G13PL >= G16PL) || (G13PL == 0)
+#define MG16_13PL ~(1 << 2)
+#else
+#define MG16_13PL 0xFFFF
+#endif
+#if (G14PL >= G16PL) || (G14PL == 0)
+#define MG16_14PL ~(1 << 3)
+#else
+#define MG16_14PL 0xFFFF
+#endif
+#if (G15PL >= G16PL) || (G15PL == 0)
+#define MG16_15PL ~(1 << 4)
+#else
+#define MG16_15PL 0xFFFF
+#endif
+#if (G17PL >= G16PL) || (G17PL == 0)
+#define MG16_17PL ~(1 << 6)
+#else
+#define MG16_17PL 0xFFFF
+#endif
+#if (G18PL >= G16PL) || (G18PL == 0)
+#define MG16_18PL ~(1 << 7)
+#else
+#define MG16_18PL 0xFFFF
+#endif
+#define MG16_16PL 0x00DF
+#define MG16 (MG16_11PL & MG16_12PL & MG16_13PL & MG16_14PL & \
+ MG16_15PL & MG16_16PL & MG16_17PL & MG16_18PL)
+// End of MG16:
+
+// Beginning of MG17:
+#if (G11PL >= G17PL) || (G11PL == 0)
+#define MG17_11PL ~(1)
+#else
+#define MG17_11PL 0xFFFF
+#endif
+#if (G12PL >= G17PL) || (G12PL == 0)
+#define MG17_12PL ~(1 << 1)
+#else
+#define MG17_12PL 0xFFFF
+#endif
+#if (G13PL >= G17PL) || (G13PL == 0)
+#define MG17_13PL ~(1 << 2)
+#else
+#define MG17_13PL 0xFFFF
+#endif
+#if (G14PL >= G17PL) || (G14PL == 0)
+#define MG17_14PL ~(1 << 3)
+#else
+#define MG17_14PL 0xFFFF
+#endif
+#if (G15PL >= G17PL) || (G15PL == 0)
+#define MG17_15PL ~(1 << 4)
+#else
+#define MG17_15PL 0xFFFF
+#endif
+#if (G16PL >= G17PL) || (G16PL == 0)
+#define MG17_16PL ~(1 << 5)
+#else
+#define MG17_16PL 0xFFFF
+#endif
+#if (G18PL >= G17PL) || (G18PL == 0)
+#define MG17_18PL ~(1 << 7)
+#else
+#define MG17_18PL 0xFFFF
+#endif
+#define MG17_17PL 0x00BF
+#define MG17 (MG17_11PL & MG17_12PL & MG17_13PL & MG17_14PL & \
+ MG17_15PL & MG17_16PL & MG17_17PL & MG17_18PL)
+// End of MG17:
+
+// Beginning of MG18:
+#if (G11PL >= G18PL) || (G11PL == 0)
+#define MG18_11PL ~(1)
+#else
+#define MG18_11PL 0xFFFF
+#endif
+#if (G12PL >= G18PL) || (G12PL == 0)
+#define MG18_12PL ~(1 << 1)
+#else
+#define MG18_12PL 0xFFFF
+#endif
+#if (G13PL >= G18PL) || (G13PL == 0)
+#define MG18_13PL ~(1 << 2)
+#else
+#define MG18_13PL 0xFFFF
+#endif
+#if (G14PL >= G18PL) || (G14PL == 0)
+#define MG18_14PL ~(1 << 3)
+#else
+#define MG18_14PL 0xFFFF
+#endif
+#if (G15PL >= G18PL) || (G15PL == 0)
+#define MG18_15PL ~(1 << 4)
+#else
+#define MG18_15PL 0xFFFF
+#endif
+#if (G16PL >= G18PL) || (G16PL == 0)
+#define MG18_16PL ~(1 << 5)
+#else
+#define MG18_16PL 0xFFFF
+#endif
+#if (G17PL >= G18PL) || (G17PL == 0)
+#define MG18_17PL ~(1 << 6)
+#else
+#define MG18_17PL 0xFFFF
+#endif
+#define MG18_18PL 0x007F
+#define MG18 (MG18_11PL & MG18_12PL & MG18_13PL & MG18_14PL & \
+ MG18_15PL & MG18_16PL & MG18_17PL & MG18_18PL)
+// End of MG18:
+
+//-------------------------------------------------------------------------------
+// Automatically generate PIEIER1 interrupt masks MG21 to MG28:
+//
+
+// Beginning of MG21:
+#if (G22PL >= G21PL) || (G22PL == 0)
+#define MG21_12PL ~(1 << 1)
+#else
+#define MG21_12PL 0xFFFF
+#endif
+#if (G23PL >= G21PL) || (G23PL == 0)
+#define MG21_13PL ~(1 << 2)
+#else
+#define MG21_13PL 0xFFFF
+#endif
+#if (G24PL >= G21PL) || (G24PL == 0)
+#define MG21_14PL ~(1 << 3)
+#else
+#define MG21_14PL 0xFFFF
+#endif
+#if (G25PL >= G21PL) || (G25PL == 0)
+#define MG21_15PL ~(1 << 4)
+#else
+#define MG21_15PL 0xFFFF
+#endif
+#if (G26PL >= G21PL) || (G26PL == 0)
+#define MG21_16PL ~(1 << 5)
+#else
+#define MG21_16PL 0xFFFF
+#endif
+#if (G27PL >= G21PL) || (G27PL == 0)
+#define MG21_17PL ~(1 << 6)
+#else
+#define MG21_17PL 0xFFFF
+#endif
+#if (G28PL >= G21PL) || (G28PL == 0)
+#define MG21_18PL ~(1 << 7)
+#else
+#define MG21_18PL 0xFFFF
+#endif
+#define MG21_11PL 0x00FE
+#define MG21 (MG21_11PL & MG21_12PL & MG21_13PL & MG21_14PL & \
+ MG21_15PL & MG21_16PL & MG21_17PL & MG21_18PL)
+// End of MG21:
+
+// Beginning of MG22:
+#if (G21PL >= G22PL) || (G21PL == 0)
+#define MG22_11PL ~(1)
+#else
+#define MG22_11PL 0xFFFF
+#endif
+#if (G23PL >= G22PL) || (G23PL == 0)
+#define MG22_13PL ~(1 << 2)
+#else
+#define MG22_13PL 0xFFFF
+#endif
+#if (G24PL >= G22PL) || (G24PL == 0)
+#define MG22_14PL ~(1 << 3)
+#else
+#define MG22_14PL 0xFFFF
+#endif
+#if (G25PL >= G22PL) || (G25PL == 0)
+#define MG22_15PL ~(1 << 4)
+#else
+#define MG22_15PL 0xFFFF
+#endif
+#if (G26PL >= G22PL) || (G26PL == 0)
+#define MG22_16PL ~(1 << 5)
+#else
+#define MG22_16PL 0xFFFF
+#endif
+#if (G27PL >= G22PL) || (G27PL == 0)
+#define MG22_17PL ~(1 << 6)
+#else
+#define MG22_17PL 0xFFFF
+#endif
+#if (G28PL >= G22PL) || (G28PL == 0)
+#define MG22_18PL ~(1 << 7)
+#else
+#define MG22_18PL 0xFFFF
+#endif
+#define MG22_12PL 0x00FD
+#define MG22 (MG22_11PL & MG22_12PL & MG22_13PL & MG22_14PL & \
+ MG22_15PL & MG22_16PL & MG22_17PL & MG22_18PL)
+// End of MG22:
+
+// Beginning of MG23:
+#if (G21PL >= G23PL) || (G21PL == 0)
+#define MG23_11PL ~(1)
+#else
+#define MG23_11PL 0xFFFF
+#endif
+#if (G22PL >= G23PL) || (G22PL == 0)
+#define MG23_12PL ~(1 << 1)
+#else
+#define MG23_12PL 0xFFFF
+#endif
+#if (G24PL >= G23PL) || (G24PL == 0)
+#define MG23_14PL ~(1 << 3)
+#else
+#define MG23_14PL 0xFFFF
+#endif
+#if (G25PL >= G23PL) || (G25PL == 0)
+#define MG23_15PL ~(1 << 4)
+#else
+#define MG23_15PL 0xFFFF
+#endif
+#if (G26PL >= G23PL) || (G26PL == 0)
+#define MG23_16PL ~(1 << 5)
+#else
+#define MG23_16PL 0xFFFF
+#endif
+#if (G27PL >= G23PL) || (G27PL == 0)
+#define MG23_17PL ~(1 << 6)
+#else
+#define MG23_17PL 0xFFFF
+#endif
+#if (G28PL >= G23PL) || (G28PL == 0)
+#define MG23_18PL ~(1 << 7)
+#else
+#define MG23_18PL 0xFFFF
+#endif
+#define MG23_13PL 0x00FB
+#define MG23 (MG23_11PL & MG23_12PL & MG23_13PL & MG23_14PL & \
+ MG23_15PL & MG23_16PL & MG23_17PL & MG23_18PL)
+// End of MG23:
+
+// Beginning of MG24:
+#if (G21PL >= G24PL) || (G21PL == 0)
+#define MG24_11PL ~(1)
+#else
+#define MG24_11PL 0xFFFF
+#endif
+#if (G22PL >= G24PL) || (G22PL == 0)
+#define MG24_12PL ~(1 << 1)
+#else
+#define MG24_12PL 0xFFFF
+#endif
+#if (G23PL >= G24PL) || (G23PL == 0)
+#define MG24_13PL ~(1 << 2)
+#else
+#define MG24_13PL 0xFFFF
+#endif
+#if (G25PL >= G24PL) || (G25PL == 0)
+#define MG24_15PL ~(1 << 4)
+#else
+#define MG24_15PL 0xFFFF
+#endif
+#if (G26PL >= G24PL) || (G26PL == 0)
+#define MG24_16PL ~(1 << 5)
+#else
+#define MG24_16PL 0xFFFF
+#endif
+#if (G27PL >= G24PL) || (G27PL == 0)
+#define MG24_17PL ~(1 << 6)
+#else
+#define MG24_17PL 0xFFFF
+#endif
+#if (G28PL >= G24PL) || (G28PL == 0)
+#define MG24_18PL ~(1 << 7)
+#else
+#define MG24_18PL 0xFFFF
+#endif
+#define MG24_14PL 0x00F7
+#define MG24 (MG24_11PL & MG24_12PL & MG24_13PL & MG24_14PL & \
+ MG24_15PL & MG24_16PL & MG24_17PL & MG24_18PL)
+// End of MG24:
+
+// Beginning of MG25:
+#if (G21PL >= G25PL) || (G21PL == 0)
+#define MG25_11PL ~(1)
+#else
+#define MG25_11PL 0xFFFF
+#endif
+#if (G22PL >= G25PL) || (G22PL == 0)
+#define MG25_12PL ~(1 << 1)
+#else
+#define MG25_12PL 0xFFFF
+#endif
+#if (G23PL >= G25PL) || (G23PL == 0)
+#define MG25_13PL ~(1 << 2)
+#else
+#define MG25_13PL 0xFFFF
+#endif
+#if (G24PL >= G25PL) || (G24PL == 0)
+#define MG25_14PL ~(1 << 3)
+#else
+#define MG25_14PL 0xFFFF
+#endif
+#if (G26PL >= G25PL) || (G26PL == 0)
+#define MG25_16PL ~(1 << 5)
+#else
+#define MG25_16PL 0xFFFF
+#endif
+#if (G27PL >= G25PL) || (G27PL == 0)
+#define MG25_17PL ~(1 << 6)
+#else
+#define MG25_17PL 0xFFFF
+#endif
+#if (G28PL >= G25PL) || (G28PL == 0)
+#define MG25_18PL ~(1 << 7)
+#else
+#define MG25_18PL 0xFFFF
+#endif
+#define MG25_15PL 0x00EF
+#define MG25 (MG25_11PL & MG25_12PL & MG25_13PL & MG25_14PL & \
+ MG25_15PL & MG25_16PL & MG25_17PL & MG25_18PL)
+// End of MG25:
+
+// Beginning of MG26:
+#if (G21PL >= G26PL) || (G21PL == 0)
+#define MG26_11PL ~(1)
+#else
+#define MG26_11PL 0xFFFF
+#endif
+#if (G22PL >= G26PL) || (G22PL == 0)
+#define MG26_12PL ~(1 << 1)
+#else
+#define MG26_12PL 0xFFFF
+#endif
+#if (G23PL >= G26PL) || (G23PL == 0)
+#define MG26_13PL ~(1 << 2)
+#else
+#define MG26_13PL 0xFFFF
+#endif
+#if (G24PL >= G26PL) || (G24PL == 0)
+#define MG26_14PL ~(1 << 3)
+#else
+#define MG26_14PL 0xFFFF
+#endif
+#if (G25PL >= G26PL) || (G25PL == 0)
+#define MG26_15PL ~(1 << 4)
+#else
+#define MG26_15PL 0xFFFF
+#endif
+#if (G27PL >= G26PL) || (G27PL == 0)
+#define MG26_17PL ~(1 << 6)
+#else
+#define MG26_17PL 0xFFFF
+#endif
+#if (G28PL >= G26PL) || (G28PL == 0)
+#define MG26_18PL ~(1 << 7)
+#else
+#define MG26_18PL 0xFFFF
+#endif
+#define MG26_16PL 0x00DF
+#define MG26 (MG26_11PL & MG26_12PL & MG26_13PL & MG26_14PL & \
+ MG26_15PL & MG26_16PL & MG26_17PL & MG26_18PL)
+// End of MG26:
+
+// Beginning of MG27:
+#if (G21PL >= G27PL) || (G21PL == 0)
+#define MG27_11PL ~(1)
+#else
+#define MG27_11PL 0xFFFF
+#endif
+#if (G22PL >= G27PL) || (G22PL == 0)
+#define MG27_12PL ~(1 << 1)
+#else
+#define MG27_12PL 0xFFFF
+#endif
+#if (G23PL >= G27PL) || (G23PL == 0)
+#define MG27_13PL ~(1 << 2)
+#else
+#define MG27_13PL 0xFFFF
+#endif
+#if (G24PL >= G27PL) || (G24PL == 0)
+#define MG27_14PL ~(1 << 3)
+#else
+#define MG27_14PL 0xFFFF
+#endif
+#if (G25PL >= G27PL) || (G25PL == 0)
+#define MG27_15PL ~(1 << 4)
+#else
+#define MG27_15PL 0xFFFF
+#endif
+#if (G26PL >= G27PL) || (G26PL == 0)
+#define MG27_16PL ~(1 << 5)
+#else
+#define MG27_16PL 0xFFFF
+#endif
+#if (G28PL >= G27PL) || (G28PL == 0)
+#define MG27_18PL ~(1 << 7)
+#else
+#define MG27_18PL 0xFFFF
+#endif
+#define MG27_17PL 0x00BF
+#define MG27 (MG27_11PL & MG27_12PL & MG27_13PL & MG27_14PL & \
+ MG27_15PL & MG27_16PL & MG27_17PL & MG27_18PL)
+// End of MG27:
+
+// Beginning of MG28:
+#if (G21PL >= G28PL) || (G21PL == 0)
+#define MG28_11PL ~(1)
+#else
+#define MG28_11PL 0xFFFF
+#endif
+#if (G22PL >= G28PL) || (G22PL == 0)
+#define MG28_12PL ~(1 << 1)
+#else
+#define MG28_12PL 0xFFFF
+#endif
+#if (G23PL >= G28PL) || (G23PL == 0)
+#define MG28_13PL ~(1 << 2)
+#else
+#define MG28_13PL 0xFFFF
+#endif
+#if (G24PL >= G28PL) || (G24PL == 0)
+#define MG28_14PL ~(1 << 3)
+#else
+#define MG28_14PL 0xFFFF
+#endif
+#if (G25PL >= G28PL) || (G25PL == 0)
+#define MG28_15PL ~(1 << 4)
+#else
+#define MG28_15PL 0xFFFF
+#endif
+#if (G26PL >= G28PL) || (G26PL == 0)
+#define MG28_16PL ~(1 << 5)
+#else
+#define MG28_16PL 0xFFFF
+#endif
+#if (G27PL >= G28PL) || (G27PL == 0)
+#define MG28_17PL ~(1 << 6)
+#else
+#define MG28_17PL 0xFFFF
+#endif
+#define MG28_18PL 0x007F
+#define MG28 (MG28_11PL & MG28_12PL & MG28_13PL & MG28_14PL & \
+ MG28_15PL & MG28_16PL & MG28_17PL & MG28_18PL)
+// End of MG28:
+
+//-------------------------------------------------------------------------------
+// Automatically generate PIEIER1 interrupt masks MG31 to MG38:
+//
+
+// Beginning of MG31:
+#if (G32PL >= G31PL) || (G32PL == 0)
+#define MG31_12PL ~(1 << 1)
+#else
+#define MG31_12PL 0xFFFF
+#endif
+#if (G33PL >= G31PL) || (G33PL == 0)
+#define MG31_13PL ~(1 << 2)
+#else
+#define MG31_13PL 0xFFFF
+#endif
+#if (G34PL >= G31PL) || (G34PL == 0)
+#define MG31_14PL ~(1 << 3)
+#else
+#define MG31_14PL 0xFFFF
+#endif
+#if (G35PL >= G31PL) || (G35PL == 0)
+#define MG31_15PL ~(1 << 4)
+#else
+#define MG31_15PL 0xFFFF
+#endif
+#if (G36PL >= G31PL) || (G36PL == 0)
+#define MG31_16PL ~(1 << 5)
+#else
+#define MG31_16PL 0xFFFF
+#endif
+#if (G37PL >= G31PL) || (G37PL == 0)
+#define MG31_17PL ~(1 << 6)
+#else
+#define MG31_17PL 0xFFFF
+#endif
+#if (G38PL >= G31PL) || (G38PL == 0)
+#define MG31_18PL ~(1 << 7)
+#else
+#define MG31_18PL 0xFFFF
+#endif
+#define MG31_11PL 0x00FE
+#define MG31 (MG31_11PL & MG31_12PL & MG31_13PL & MG31_14PL & \
+ MG31_15PL & MG31_16PL & MG31_17PL & MG31_18PL)
+// End of MG31:
+
+// Beginning of MG32:
+#if (G31PL >= G32PL) || (G31PL == 0)
+#define MG32_11PL ~(1)
+#else
+#define MG32_11PL 0xFFFF
+#endif
+#if (G33PL >= G32PL) || (G33PL == 0)
+#define MG32_13PL ~(1 << 2)
+#else
+#define MG32_13PL 0xFFFF
+#endif
+#if (G34PL >= G32PL) || (G34PL == 0)
+#define MG32_14PL ~(1 << 3)
+#else
+#define MG32_14PL 0xFFFF
+#endif
+#if (G35PL >= G32PL) || (G35PL == 0)
+#define MG32_15PL ~(1 << 4)
+#else
+#define MG32_15PL 0xFFFF
+#endif
+#if (G36PL >= G32PL) || (G36PL == 0)
+#define MG32_16PL ~(1 << 5)
+#else
+#define MG32_16PL 0xFFFF
+#endif
+#if (G37PL >= G32PL) || (G37PL == 0)
+#define MG32_17PL ~(1 << 6)
+#else
+#define MG32_17PL 0xFFFF
+#endif
+#if (G38PL >= G32PL) || (G38PL == 0)
+#define MG32_18PL ~(1 << 7)
+#else
+#define MG32_18PL 0xFFFF
+#endif
+#define MG32_12PL 0x00FD
+#define MG32 (MG32_11PL & MG32_12PL & MG32_13PL & MG32_14PL & \
+ MG32_15PL & MG32_16PL & MG32_17PL & MG32_18PL)
+// End of MG32:
+
+// Beginning of MG33:
+#if (G31PL >= G33PL) || (G31PL == 0)
+#define MG33_11PL ~(1)
+#else
+#define MG33_11PL 0xFFFF
+#endif
+#if (G32PL >= G33PL) || (G32PL == 0)
+#define MG33_12PL ~(1 << 1)
+#else
+#define MG33_12PL 0xFFFF
+#endif
+#if (G34PL >= G33PL) || (G34PL == 0)
+#define MG33_14PL ~(1 << 3)
+#else
+#define MG33_14PL 0xFFFF
+#endif
+#if (G35PL >= G33PL) || (G35PL == 0)
+#define MG33_15PL ~(1 << 4)
+#else
+#define MG33_15PL 0xFFFF
+#endif
+#if (G36PL >= G33PL) || (G36PL == 0)
+#define MG33_16PL ~(1 << 5)
+#else
+#define MG33_16PL 0xFFFF
+#endif
+#if (G37PL >= G33PL) || (G37PL == 0)
+#define MG33_17PL ~(1 << 6)
+#else
+#define MG33_17PL 0xFFFF
+#endif
+#if (G38PL >= G33PL) || (G38PL == 0)
+#define MG33_18PL ~(1 << 7)
+#else
+#define MG33_18PL 0xFFFF
+#endif
+#define MG33_13PL 0x00FB
+#define MG33 (MG33_11PL & MG33_12PL & MG33_13PL & MG33_14PL & \
+ MG33_15PL & MG33_16PL & MG33_17PL & MG33_18PL)
+// End of MG33:
+
+// Beginning of MG34:
+#if (G31PL >= G34PL) || (G31PL == 0)
+#define MG34_11PL ~(1)
+#else
+#define MG34_11PL 0xFFFF
+#endif
+#if (G32PL >= G34PL) || (G32PL == 0)
+#define MG34_12PL ~(1 << 1)
+#else
+#define MG34_12PL 0xFFFF
+#endif
+#if (G33PL >= G34PL) || (G33PL == 0)
+#define MG34_13PL ~(1 << 2)
+#else
+#define MG34_13PL 0xFFFF
+#endif
+#if (G35PL >= G34PL) || (G35PL == 0)
+#define MG34_15PL ~(1 << 4)
+#else
+#define MG34_15PL 0xFFFF
+#endif
+#if (G36PL >= G34PL) || (G36PL == 0)
+#define MG34_16PL ~(1 << 5)
+#else
+#define MG34_16PL 0xFFFF
+#endif
+#if (G37PL >= G34PL) || (G37PL == 0)
+#define MG34_17PL ~(1 << 6)
+#else
+#define MG34_17PL 0xFFFF
+#endif
+#if (G38PL >= G34PL) || (G38PL == 0)
+#define MG34_18PL ~(1 << 7)
+#else
+#define MG34_18PL 0xFFFF
+#endif
+#define MG34_14PL 0x00F7
+#define MG34 (MG34_11PL & MG34_12PL & MG34_13PL & MG34_14PL & \
+ MG34_15PL & MG34_16PL & MG34_17PL & MG34_18PL)
+// End of MG34:
+
+// Beginning of MG35:
+#if (G31PL >= G35PL) || (G31PL == 0)
+#define MG35_11PL ~(1)
+#else
+#define MG35_11PL 0xFFFF
+#endif
+#if (G32PL >= G35PL) || (G32PL == 0)
+#define MG35_12PL ~(1 << 1)
+#else
+#define MG35_12PL 0xFFFF
+#endif
+#if (G33PL >= G35PL) || (G33PL == 0)
+#define MG35_13PL ~(1 << 2)
+#else
+#define MG35_13PL 0xFFFF
+#endif
+#if (G34PL >= G35PL) || (G34PL == 0)
+#define MG35_14PL ~(1 << 3)
+#else
+#define MG35_14PL 0xFFFF
+#endif
+#if (G36PL >= G35PL) || (G36PL == 0)
+#define MG35_16PL ~(1 << 5)
+#else
+#define MG35_16PL 0xFFFF
+#endif
+#if (G37PL >= G35PL) || (G37PL == 0)
+#define MG35_17PL ~(1 << 6)
+#else
+#define MG35_17PL 0xFFFF
+#endif
+#if (G38PL >= G35PL) || (G38PL == 0)
+#define MG35_18PL ~(1 << 7)
+#else
+#define MG35_18PL 0xFFFF
+#endif
+#define MG35_15PL 0x00EF
+#define MG35 (MG35_11PL & MG35_12PL & MG35_13PL & MG35_14PL & \
+ MG35_15PL & MG35_16PL & MG35_17PL & MG35_18PL)
+// End of MG35:
+
+// Beginning of MG36:
+#if (G31PL >= G36PL) || (G31PL == 0)
+#define MG36_11PL ~(1)
+#else
+#define MG36_11PL 0xFFFF
+#endif
+#if (G32PL >= G36PL) || (G32PL == 0)
+#define MG36_12PL ~(1 << 1)
+#else
+#define MG36_12PL 0xFFFF
+#endif
+#if (G33PL >= G36PL) || (G33PL == 0)
+#define MG36_13PL ~(1 << 2)
+#else
+#define MG36_13PL 0xFFFF
+#endif
+#if (G34PL >= G36PL) || (G34PL == 0)
+#define MG36_14PL ~(1 << 3)
+#else
+#define MG36_14PL 0xFFFF
+#endif
+#if (G35PL >= G36PL) || (G35PL == 0)
+#define MG36_15PL ~(1 << 4)
+#else
+#define MG36_15PL 0xFFFF
+#endif
+#if (G37PL >= G36PL) || (G37PL == 0)
+#define MG36_17PL ~(1 << 6)
+#else
+#define MG36_17PL 0xFFFF
+#endif
+#if (G38PL >= G36PL) || (G38PL == 0)
+#define MG36_18PL ~(1 << 7)
+#else
+#define MG36_18PL 0xFFFF
+#endif
+#define MG36_16PL 0x00DF
+#define MG36 (MG36_11PL & MG36_12PL & MG36_13PL & MG36_14PL & \
+ MG36_15PL & MG36_16PL & MG36_17PL & MG36_18PL)
+// End of MG36:
+
+// Beginning of MG37:
+#if (G31PL >= G37PL) || (G31PL == 0)
+#define MG37_11PL ~(1)
+#else
+#define MG37_11PL 0xFFFF
+#endif
+#if (G32PL >= G37PL) || (G32PL == 0)
+#define MG37_12PL ~(1 << 1)
+#else
+#define MG37_12PL 0xFFFF
+#endif
+#if (G33PL >= G37PL) || (G33PL == 0)
+#define MG37_13PL ~(1 << 2)
+#else
+#define MG37_13PL 0xFFFF
+#endif
+#if (G34PL >= G37PL) || (G34PL == 0)
+#define MG37_14PL ~(1 << 3)
+#else
+#define MG37_14PL 0xFFFF
+#endif
+#if (G35PL >= G37PL) || (G35PL == 0)
+#define MG37_15PL ~(1 << 4)
+#else
+#define MG37_15PL 0xFFFF
+#endif
+#if (G36PL >= G37PL) || (G36PL == 0)
+#define MG37_16PL ~(1 << 5)
+#else
+#define MG37_16PL 0xFFFF
+#endif
+#if (G38PL >= G37PL) || (G38PL == 0)
+#define MG37_18PL ~(1 << 7)
+#else
+#define MG37_18PL 0xFFFF
+#endif
+#define MG37_17PL 0x00BF
+#define MG37 (MG37_11PL & MG37_12PL & MG37_13PL & MG37_14PL & \
+ MG37_15PL & MG37_16PL & MG37_17PL & MG37_18PL)
+// End of MG37:
+
+// Beginning of MG38:
+#if (G31PL >= G38PL) || (G31PL == 0)
+#define MG38_11PL ~(1)
+#else
+#define MG38_11PL 0xFFFF
+#endif
+#if (G32PL >= G38PL) || (G32PL == 0)
+#define MG38_12PL ~(1 << 1)
+#else
+#define MG38_12PL 0xFFFF
+#endif
+#if (G33PL >= G38PL) || (G33PL == 0)
+#define MG38_13PL ~(1 << 2)
+#else
+#define MG38_13PL 0xFFFF
+#endif
+#if (G34PL >= G38PL) || (G34PL == 0)
+#define MG38_14PL ~(1 << 3)
+#else
+#define MG38_14PL 0xFFFF
+#endif
+#if (G35PL >= G38PL) || (G35PL == 0)
+#define MG38_15PL ~(1 << 4)
+#else
+#define MG38_15PL 0xFFFF
+#endif
+#if (G36PL >= G38PL) || (G36PL == 0)
+#define MG38_16PL ~(1 << 5)
+#else
+#define MG38_16PL 0xFFFF
+#endif
+#if (G37PL >= G38PL) || (G37PL == 0)
+#define MG38_17PL ~(1 << 6)
+#else
+#define MG38_17PL 0xFFFF
+#endif
+#define MG38_18PL 0x007F
+#define MG38 (MG38_11PL & MG38_12PL & MG38_13PL & MG38_14PL & \
+ MG38_15PL & MG38_16PL & MG38_17PL & MG38_18PL)
+// End of MG38:
+
+//-------------------------------------------------------------------------------
+// Automatically generate PIEIER1 interrupt masks MG41 to MG48:
+//
+
+// Beginning of MG41:
+#if (G42PL >= G41PL) || (G42PL == 0)
+#define MG41_12PL ~(1 << 1)
+#else
+#define MG41_12PL 0xFFFF
+#endif
+#if (G43PL >= G41PL) || (G43PL == 0)
+#define MG41_13PL ~(1 << 2)
+#else
+#define MG41_13PL 0xFFFF
+#endif
+#if (G44PL >= G41PL) || (G44PL == 0)
+#define MG41_14PL ~(1 << 3)
+#else
+#define MG41_14PL 0xFFFF
+#endif
+#if (G45PL >= G41PL) || (G45PL == 0)
+#define MG41_15PL ~(1 << 4)
+#else
+#define MG41_15PL 0xFFFF
+#endif
+#if (G46PL >= G41PL) || (G46PL == 0)
+#define MG41_16PL ~(1 << 5)
+#else
+#define MG41_16PL 0xFFFF
+#endif
+#if (G47PL >= G41PL) || (G47PL == 0)
+#define MG41_17PL ~(1 << 6)
+#else
+#define MG41_17PL 0xFFFF
+#endif
+#if (G48PL >= G41PL) || (G48PL == 0)
+#define MG41_18PL ~(1 << 7)
+#else
+#define MG41_18PL 0xFFFF
+#endif
+#define MG41_11PL 0x00FE
+#define MG41 (MG41_11PL & MG41_12PL & MG41_13PL & MG41_14PL & \
+ MG41_15PL & MG41_16PL & MG41_17PL & MG41_18PL)
+// End of MG41:
+
+// Beginning of MG42:
+#if (G41PL >= G42PL) || (G41PL == 0)
+#define MG42_11PL ~(1)
+#else
+#define MG42_11PL 0xFFFF
+#endif
+#if (G43PL >= G42PL) || (G43PL == 0)
+#define MG42_13PL ~(1 << 2)
+#else
+#define MG42_13PL 0xFFFF
+#endif
+#if (G44PL >= G42PL) || (G44PL == 0)
+#define MG42_14PL ~(1 << 3)
+#else
+#define MG42_14PL 0xFFFF
+#endif
+#if (G45PL >= G42PL) || (G45PL == 0)
+#define MG42_15PL ~(1 << 4)
+#else
+#define MG42_15PL 0xFFFF
+#endif
+#if (G46PL >= G42PL) || (G46PL == 0)
+#define MG42_16PL ~(1 << 5)
+#else
+#define MG42_16PL 0xFFFF
+#endif
+#if (G47PL >= G42PL) || (G47PL == 0)
+#define MG42_17PL ~(1 << 6)
+#else
+#define MG42_17PL 0xFFFF
+#endif
+#if (G48PL >= G42PL) || (G48PL == 0)
+#define MG42_18PL ~(1 << 7)
+#else
+#define MG42_18PL 0xFFFF
+#endif
+#define MG42_12PL 0x00FD
+#define MG42 (MG42_11PL & MG42_12PL & MG42_13PL & MG42_14PL & \
+ MG42_15PL & MG42_16PL & MG42_17PL & MG42_18PL)
+// End of MG42:
+
+// Beginning of MG43:
+#if (G41PL >= G43PL) || (G41PL == 0)
+#define MG43_11PL ~(1)
+#else
+#define MG43_11PL 0xFFFF
+#endif
+#if (G42PL >= G43PL) || (G42PL == 0)
+#define MG43_12PL ~(1 << 1)
+#else
+#define MG43_12PL 0xFFFF
+#endif
+#if (G44PL >= G43PL) || (G44PL == 0)
+#define MG43_14PL ~(1 << 3)
+#else
+#define MG43_14PL 0xFFFF
+#endif
+#if (G45PL >= G43PL) || (G45PL == 0)
+#define MG43_15PL ~(1 << 4)
+#else
+#define MG43_15PL 0xFFFF
+#endif
+#if (G46PL >= G43PL) || (G46PL == 0)
+#define MG43_16PL ~(1 << 5)
+#else
+#define MG43_16PL 0xFFFF
+#endif
+#if (G47PL >= G43PL) || (G47PL == 0)
+#define MG43_17PL ~(1 << 6)
+#else
+#define MG43_17PL 0xFFFF
+#endif
+#if (G48PL >= G43PL) || (G48PL == 0)
+#define MG43_18PL ~(1 << 7)
+#else
+#define MG43_18PL 0xFFFF
+#endif
+#define MG43_13PL 0x00FB
+#define MG43 (MG43_11PL & MG43_12PL & MG43_13PL & MG43_14PL & \
+ MG43_15PL & MG43_16PL & MG43_17PL & MG43_18PL)
+// End of MG43:
+
+// Beginning of MG44:
+#if (G41PL >= G44PL) || (G41PL == 0)
+#define MG44_11PL ~(1)
+#else
+#define MG44_11PL 0xFFFF
+#endif
+#if (G42PL >= G44PL) || (G42PL == 0)
+#define MG44_12PL ~(1 << 1)
+#else
+#define MG44_12PL 0xFFFF
+#endif
+#if (G43PL >= G44PL) || (G43PL == 0)
+#define MG44_13PL ~(1 << 2)
+#else
+#define MG44_13PL 0xFFFF
+#endif
+#if (G45PL >= G44PL) || (G45PL == 0)
+#define MG44_15PL ~(1 << 4)
+#else
+#define MG44_15PL 0xFFFF
+#endif
+#if (G46PL >= G44PL) || (G46PL == 0)
+#define MG44_16PL ~(1 << 5)
+#else
+#define MG44_16PL 0xFFFF
+#endif
+#if (G47PL >= G44PL) || (G47PL == 0)
+#define MG44_17PL ~(1 << 6)
+#else
+#define MG44_17PL 0xFFFF
+#endif
+#if (G48PL >= G44PL) || (G48PL == 0)
+#define MG44_18PL ~(1 << 7)
+#else
+#define MG44_18PL 0xFFFF
+#endif
+#define MG44_14PL 0x00F7
+#define MG44 (MG44_11PL & MG44_12PL & MG44_13PL & MG44_14PL & \
+ MG44_15PL & MG44_16PL & MG44_17PL & MG44_18PL)
+// End of MG44:
+
+// Beginning of MG45:
+#if (G41PL >= G45PL) || (G41PL == 0)
+#define MG45_11PL ~(1)
+#else
+#define MG45_11PL 0xFFFF
+#endif
+#if (G42PL >= G45PL) || (G42PL == 0)
+#define MG45_12PL ~(1 << 1)
+#else
+#define MG45_12PL 0xFFFF
+#endif
+#if (G43PL >= G45PL) || (G43PL == 0)
+#define MG45_13PL ~(1 << 2)
+#else
+#define MG45_13PL 0xFFFF
+#endif
+#if (G44PL >= G45PL) || (G44PL == 0)
+#define MG45_14PL ~(1 << 3)
+#else
+#define MG45_14PL 0xFFFF
+#endif
+#if (G46PL >= G45PL) || (G46PL == 0)
+#define MG45_16PL ~(1 << 5)
+#else
+#define MG45_16PL 0xFFFF
+#endif
+#if (G47PL >= G45PL) || (G47PL == 0)
+#define MG45_17PL ~(1 << 6)
+#else
+#define MG45_17PL 0xFFFF
+#endif
+#if (G48PL >= G45PL) || (G48PL == 0)
+#define MG45_18PL ~(1 << 7)
+#else
+#define MG45_18PL 0xFFFF
+#endif
+#define MG45_15PL 0x00EF
+#define MG45 (MG45_11PL & MG45_12PL & MG45_13PL & MG45_14PL & \
+ MG45_15PL & MG45_16PL & MG45_17PL & MG45_18PL)
+// End of MG45:
+
+// Beginning of MG46:
+#if (G41PL >= G46PL) || (G41PL == 0)
+#define MG46_11PL ~(1)
+#else
+#define MG46_11PL 0xFFFF
+#endif
+#if (G42PL >= G46PL) || (G42PL == 0)
+#define MG46_12PL ~(1 << 1)
+#else
+#define MG46_12PL 0xFFFF
+#endif
+#if (G43PL >= G46PL) || (G43PL == 0)
+#define MG46_13PL ~(1 << 2)
+#else
+#define MG46_13PL 0xFFFF
+#endif
+#if (G44PL >= G46PL) || (G44PL == 0)
+#define MG46_14PL ~(1 << 3)
+#else
+#define MG46_14PL 0xFFFF
+#endif
+#if (G45PL >= G46PL) || (G45PL == 0)
+#define MG46_15PL ~(1 << 4)
+#else
+#define MG46_15PL 0xFFFF
+#endif
+#if (G47PL >= G46PL) || (G47PL == 0)
+#define MG46_17PL ~(1 << 6)
+#else
+#define MG46_17PL 0xFFFF
+#endif
+#if (G48PL >= G46PL) || (G48PL == 0)
+#define MG46_18PL ~(1 << 7)
+#else
+#define MG46_18PL 0xFFFF
+#endif
+#define MG46_16PL 0x00DF
+#define MG46 (MG46_11PL & MG46_12PL & MG46_13PL & MG46_14PL & \
+ MG46_15PL & MG46_16PL & MG46_17PL & MG46_18PL)
+// End of MG46:
+
+// Beginning of MG47:
+#if (G41PL >= G47PL) || (G41PL == 0)
+#define MG47_11PL ~(1)
+#else
+#define MG47_11PL 0xFFFF
+#endif
+#if (G42PL >= G47PL) || (G42PL == 0)
+#define MG47_12PL ~(1 << 1)
+#else
+#define MG47_12PL 0xFFFF
+#endif
+#if (G43PL >= G47PL) || (G43PL == 0)
+#define MG47_13PL ~(1 << 2)
+#else
+#define MG47_13PL 0xFFFF
+#endif
+#if (G44PL >= G47PL) || (G44PL == 0)
+#define MG47_14PL ~(1 << 3)
+#else
+#define MG47_14PL 0xFFFF
+#endif
+#if (G45PL >= G47PL) || (G45PL == 0)
+#define MG47_15PL ~(1 << 4)
+#else
+#define MG47_15PL 0xFFFF
+#endif
+#if (G46PL >= G47PL) || (G46PL == 0)
+#define MG47_16PL ~(1 << 5)
+#else
+#define MG47_16PL 0xFFFF
+#endif
+#if (G48PL >= G47PL) || (G48PL == 0)
+#define MG47_18PL ~(1 << 7)
+#else
+#define MG47_18PL 0xFFFF
+#endif
+#define MG47_17PL 0x00BF
+#define MG47 (MG47_11PL & MG47_12PL & MG47_13PL & MG47_14PL & \
+ MG47_15PL & MG47_16PL & MG47_17PL & MG47_18PL)
+// End of MG47:
+
+// Beginning of MG48:
+#if (G41PL >= G48PL) || (G41PL == 0)
+#define MG48_11PL ~(1)
+#else
+#define MG48_11PL 0xFFFF
+#endif
+#if (G42PL >= G48PL) || (G42PL == 0)
+#define MG48_12PL ~(1 << 1)
+#else
+#define MG48_12PL 0xFFFF
+#endif
+#if (G43PL >= G48PL) || (G43PL == 0)
+#define MG48_13PL ~(1 << 2)
+#else
+#define MG48_13PL 0xFFFF
+#endif
+#if (G44PL >= G48PL) || (G44PL == 0)
+#define MG48_14PL ~(1 << 3)
+#else
+#define MG48_14PL 0xFFFF
+#endif
+#if (G45PL >= G48PL) || (G45PL == 0)
+#define MG48_15PL ~(1 << 4)
+#else
+#define MG48_15PL 0xFFFF
+#endif
+#if (G46PL >= G48PL) || (G46PL == 0)
+#define MG48_16PL ~(1 << 5)
+#else
+#define MG48_16PL 0xFFFF
+#endif
+#if (G47PL >= G48PL) || (G47PL == 0)
+#define MG48_17PL ~(1 << 6)
+#else
+#define MG48_17PL 0xFFFF
+#endif
+#define MG48_18PL 0x007F
+#define MG48 (MG48_11PL & MG48_12PL & MG48_13PL & MG48_14PL & \
+ MG48_15PL & MG48_16PL & MG48_17PL & MG48_18PL)
+// End of MG48:
+
+//-------------------------------------------------------------------------------
+// Automatically generate PIEIER1 interrupt masks MG51 to MG58:
+//
+
+// Beginning of MG51:
+#if (G52PL >= G51PL) || (G52PL == 0)
+#define MG51_12PL ~(1 << 1)
+#else
+#define MG51_12PL 0xFFFF
+#endif
+#if (G53PL >= G51PL) || (G53PL == 0)
+#define MG51_13PL ~(1 << 2)
+#else
+#define MG51_13PL 0xFFFF
+#endif
+#if (G54PL >= G51PL) || (G54PL == 0)
+#define MG51_14PL ~(1 << 3)
+#else
+#define MG51_14PL 0xFFFF
+#endif
+#if (G55PL >= G51PL) || (G55PL == 0)
+#define MG51_15PL ~(1 << 4)
+#else
+#define MG51_15PL 0xFFFF
+#endif
+#if (G56PL >= G51PL) || (G56PL == 0)
+#define MG51_16PL ~(1 << 5)
+#else
+#define MG51_16PL 0xFFFF
+#endif
+#if (G57PL >= G51PL) || (G57PL == 0)
+#define MG51_17PL ~(1 << 6)
+#else
+#define MG51_17PL 0xFFFF
+#endif
+#if (G58PL >= G51PL) || (G58PL == 0)
+#define MG51_18PL ~(1 << 7)
+#else
+#define MG51_18PL 0xFFFF
+#endif
+#define MG51_11PL 0x00FE
+#define MG51 (MG51_11PL & MG51_12PL & MG51_13PL & MG51_14PL & \
+ MG51_15PL & MG51_16PL & MG51_17PL & MG51_18PL)
+// End of MG51:
+
+// Beginning of MG52:
+#if (G51PL >= G52PL) || (G51PL == 0)
+#define MG52_11PL ~(1)
+#else
+#define MG52_11PL 0xFFFF
+#endif
+#if (G53PL >= G52PL) || (G53PL == 0)
+#define MG52_13PL ~(1 << 2)
+#else
+#define MG52_13PL 0xFFFF
+#endif
+#if (G54PL >= G52PL) || (G54PL == 0)
+#define MG52_14PL ~(1 << 3)
+#else
+#define MG52_14PL 0xFFFF
+#endif
+#if (G55PL >= G52PL) || (G55PL == 0)
+#define MG52_15PL ~(1 << 4)
+#else
+#define MG52_15PL 0xFFFF
+#endif
+#if (G56PL >= G52PL) || (G56PL == 0)
+#define MG52_16PL ~(1 << 5)
+#else
+#define MG52_16PL 0xFFFF
+#endif
+#if (G57PL >= G52PL) || (G57PL == 0)
+#define MG52_17PL ~(1 << 6)
+#else
+#define MG52_17PL 0xFFFF
+#endif
+#if (G58PL >= G52PL) || (G58PL == 0)
+#define MG52_18PL ~(1 << 7)
+#else
+#define MG52_18PL 0xFFFF
+#endif
+#define MG52_12PL 0x00FD
+#define MG52 (MG52_11PL & MG52_12PL & MG52_13PL & MG52_14PL & \
+ MG52_15PL & MG52_16PL & MG52_17PL & MG52_18PL)
+// End of MG52:
+
+// Beginning of MG53:
+#if (G51PL >= G53PL) || (G51PL == 0)
+#define MG53_11PL ~(1)
+#else
+#define MG53_11PL 0xFFFF
+#endif
+#if (G52PL >= G53PL) || (G52PL == 0)
+#define MG53_12PL ~(1 << 1)
+#else
+#define MG53_12PL 0xFFFF
+#endif
+#if (G54PL >= G53PL) || (G54PL == 0)
+#define MG53_14PL ~(1 << 3)
+#else
+#define MG53_14PL 0xFFFF
+#endif
+#if (G55PL >= G53PL) || (G55PL == 0)
+#define MG53_15PL ~(1 << 4)
+#else
+#define MG53_15PL 0xFFFF
+#endif
+#if (G56PL >= G53PL) || (G56PL == 0)
+#define MG53_16PL ~(1 << 5)
+#else
+#define MG53_16PL 0xFFFF
+#endif
+#if (G57PL >= G53PL) || (G57PL == 0)
+#define MG53_17PL ~(1 << 6)
+#else
+#define MG53_17PL 0xFFFF
+#endif
+#if (G58PL >= G53PL) || (G58PL == 0)
+#define MG53_18PL ~(1 << 7)
+#else
+#define MG53_18PL 0xFFFF
+#endif
+#define MG53_13PL 0x00FB
+#define MG53 (MG53_11PL & MG53_12PL & MG53_13PL & MG53_14PL & \
+ MG53_15PL & MG53_16PL & MG53_17PL & MG53_18PL)
+// End of MG53:
+
+// Beginning of MG54:
+#if (G51PL >= G54PL) || (G51PL == 0)
+#define MG54_11PL ~(1)
+#else
+#define MG54_11PL 0xFFFF
+#endif
+#if (G52PL >= G54PL) || (G52PL == 0)
+#define MG54_12PL ~(1 << 1)
+#else
+#define MG54_12PL 0xFFFF
+#endif
+#if (G53PL >= G54PL) || (G53PL == 0)
+#define MG54_13PL ~(1 << 2)
+#else
+#define MG54_13PL 0xFFFF
+#endif
+#if (G55PL >= G54PL) || (G55PL == 0)
+#define MG54_15PL ~(1 << 4)
+#else
+#define MG54_15PL 0xFFFF
+#endif
+#if (G56PL >= G54PL) || (G56PL == 0)
+#define MG54_16PL ~(1 << 5)
+#else
+#define MG54_16PL 0xFFFF
+#endif
+#if (G57PL >= G54PL) || (G57PL == 0)
+#define MG54_17PL ~(1 << 6)
+#else
+#define MG54_17PL 0xFFFF
+#endif
+#if (G58PL >= G54PL) || (G58PL == 0)
+#define MG54_18PL ~(1 << 7)
+#else
+#define MG54_18PL 0xFFFF
+#endif
+#define MG54_14PL 0x00F7
+#define MG54 (MG54_11PL & MG54_12PL & MG54_13PL & MG54_14PL & \
+ MG54_15PL & MG54_16PL & MG54_17PL & MG54_18PL)
+// End of MG54:
+
+// Beginning of MG55:
+#if (G51PL >= G55PL) || (G51PL == 0)
+#define MG55_11PL ~(1)
+#else
+#define MG55_11PL 0xFFFF
+#endif
+#if (G52PL >= G55PL) || (G52PL == 0)
+#define MG55_12PL ~(1 << 1)
+#else
+#define MG55_12PL 0xFFFF
+#endif
+#if (G53PL >= G55PL) || (G53PL == 0)
+#define MG55_13PL ~(1 << 2)
+#else
+#define MG55_13PL 0xFFFF
+#endif
+#if (G54PL >= G55PL) || (G54PL == 0)
+#define MG55_14PL ~(1 << 3)
+#else
+#define MG55_14PL 0xFFFF
+#endif
+#if (G56PL >= G55PL) || (G56PL == 0)
+#define MG55_16PL ~(1 << 5)
+#else
+#define MG55_16PL 0xFFFF
+#endif
+#if (G57PL >= G55PL) || (G57PL == 0)
+#define MG55_17PL ~(1 << 6)
+#else
+#define MG55_17PL 0xFFFF
+#endif
+#if (G58PL >= G55PL) || (G58PL == 0)
+#define MG55_18PL ~(1 << 7)
+#else
+#define MG55_18PL 0xFFFF
+#endif
+#define MG55_15PL 0x00EF
+#define MG55 (MG55_11PL & MG55_12PL & MG55_13PL & MG55_14PL & \
+ MG55_15PL & MG55_16PL & MG55_17PL & MG55_18PL)
+// End of MG55:
+
+// Beginning of MG56:
+#if (G51PL >= G56PL) || (G51PL == 0)
+#define MG56_11PL ~(1)
+#else
+#define MG56_11PL 0xFFFF
+#endif
+#if (G52PL >= G56PL) || (G52PL == 0)
+#define MG56_12PL ~(1 << 1)
+#else
+#define MG56_12PL 0xFFFF
+#endif
+#if (G53PL >= G56PL) || (G53PL == 0)
+#define MG56_13PL ~(1 << 2)
+#else
+#define MG56_13PL 0xFFFF
+#endif
+#if (G54PL >= G56PL) || (G54PL == 0)
+#define MG56_14PL ~(1 << 3)
+#else
+#define MG56_14PL 0xFFFF
+#endif
+#if (G55PL >= G56PL) || (G55PL == 0)
+#define MG56_15PL ~(1 << 4)
+#else
+#define MG56_15PL 0xFFFF
+#endif
+#if (G57PL >= G56PL) || (G57PL == 0)
+#define MG56_17PL ~(1 << 6)
+#else
+#define MG56_17PL 0xFFFF
+#endif
+#if (G58PL >= G56PL) || (G58PL == 0)
+#define MG56_18PL ~(1 << 7)
+#else
+#define MG56_18PL 0xFFFF
+#endif
+#define MG56_16PL 0x00DF
+#define MG56 (MG56_11PL & MG56_12PL & MG56_13PL & MG56_14PL & \
+ MG56_15PL & MG56_16PL & MG56_17PL & MG56_18PL)
+// End of MG56:
+
+// Beginning of MG57:
+#if (G51PL >= G57PL) || (G51PL == 0)
+#define MG57_11PL ~(1)
+#else
+#define MG57_11PL 0xFFFF
+#endif
+#if (G52PL >= G57PL) || (G52PL == 0)
+#define MG57_12PL ~(1 << 1)
+#else
+#define MG57_12PL 0xFFFF
+#endif
+#if (G53PL >= G57PL) || (G53PL == 0)
+#define MG57_13PL ~(1 << 2)
+#else
+#define MG57_13PL 0xFFFF
+#endif
+#if (G54PL >= G57PL) || (G54PL == 0)
+#define MG57_14PL ~(1 << 3)
+#else
+#define MG57_14PL 0xFFFF
+#endif
+#if (G55PL >= G57PL) || (G55PL == 0)
+#define MG57_15PL ~(1 << 4)
+#else
+#define MG57_15PL 0xFFFF
+#endif
+#if (G56PL >= G57PL) || (G56PL == 0)
+#define MG57_16PL ~(1 << 5)
+#else
+#define MG57_16PL 0xFFFF
+#endif
+#if (G58PL >= G57PL) || (G58PL == 0)
+#define MG57_18PL ~(1 << 7)
+#else
+#define MG57_18PL 0xFFFF
+#endif
+#define MG57_17PL 0x00BF
+#define MG57 (MG57_11PL & MG57_12PL & MG57_13PL & MG57_14PL & \
+ MG57_15PL & MG57_16PL & MG57_17PL & MG57_18PL)
+// End of MG57:
+
+// Beginning of MG58:
+#if (G51PL >= G58PL) || (G51PL == 0)
+#define MG58_11PL ~(1)
+#else
+#define MG58_11PL 0xFFFF
+#endif
+#if (G52PL >= G58PL) || (G52PL == 0)
+#define MG58_12PL ~(1 << 1)
+#else
+#define MG58_12PL 0xFFFF
+#endif
+#if (G53PL >= G58PL) || (G53PL == 0)
+#define MG58_13PL ~(1 << 2)
+#else
+#define MG58_13PL 0xFFFF
+#endif
+#if (G54PL >= G58PL) || (G54PL == 0)
+#define MG58_14PL ~(1 << 3)
+#else
+#define MG58_14PL 0xFFFF
+#endif
+#if (G55PL >= G58PL) || (G55PL == 0)
+#define MG58_15PL ~(1 << 4)
+#else
+#define MG58_15PL 0xFFFF
+#endif
+#if (G56PL >= G58PL) || (G56PL == 0)
+#define MG58_16PL ~(1 << 5)
+#else
+#define MG58_16PL 0xFFFF
+#endif
+#if (G57PL >= G58PL) || (G57PL == 0)
+#define MG58_17PL ~(1 << 6)
+#else
+#define MG58_17PL 0xFFFF
+#endif
+#define MG58_18PL 0x007F
+#define MG58 (MG58_11PL & MG58_12PL & MG58_13PL & MG58_14PL & \
+ MG58_15PL & MG58_16PL & MG58_17PL & MG58_18PL)
+// End of MG58:
+
+//-------------------------------------------------------------------------------
+// Automatically generate PIEIER1 interrupt masks MG61 to MG68:
+//
+
+// Beginning of MG61:
+#if (G62PL >= G61PL) || (G62PL == 0)
+#define MG61_12PL ~(1 << 1)
+#else
+#define MG61_12PL 0xFFFF
+#endif
+#if (G63PL >= G61PL) || (G63PL == 0)
+#define MG61_13PL ~(1 << 2)
+#else
+#define MG61_13PL 0xFFFF
+#endif
+#if (G64PL >= G61PL) || (G64PL == 0)
+#define MG61_14PL ~(1 << 3)
+#else
+#define MG61_14PL 0xFFFF
+#endif
+#if (G65PL >= G61PL) || (G65PL == 0)
+#define MG61_15PL ~(1 << 4)
+#else
+#define MG61_15PL 0xFFFF
+#endif
+#if (G66PL >= G61PL) || (G66PL == 0)
+#define MG61_16PL ~(1 << 5)
+#else
+#define MG61_16PL 0xFFFF
+#endif
+#if (G67PL >= G61PL) || (G67PL == 0)
+#define MG61_17PL ~(1 << 6)
+#else
+#define MG61_17PL 0xFFFF
+#endif
+#if (G68PL >= G61PL) || (G68PL == 0)
+#define MG61_18PL ~(1 << 7)
+#else
+#define MG61_18PL 0xFFFF
+#endif
+#define MG61_11PL 0x00FE
+#define MG61 (MG61_11PL & MG61_12PL & MG61_13PL & MG61_14PL & \
+ MG61_15PL & MG61_16PL & MG61_17PL & MG61_18PL)
+// End of MG61:
+
+// Beginning of MG62:
+#if (G61PL >= G62PL) || (G61PL == 0)
+#define MG62_11PL ~(1)
+#else
+#define MG62_11PL 0xFFFF
+#endif
+#if (G63PL >= G62PL) || (G63PL == 0)
+#define MG62_13PL ~(1 << 2)
+#else
+#define MG62_13PL 0xFFFF
+#endif
+#if (G64PL >= G62PL) || (G64PL == 0)
+#define MG62_14PL ~(1 << 3)
+#else
+#define MG62_14PL 0xFFFF
+#endif
+#if (G65PL >= G62PL) || (G65PL == 0)
+#define MG62_15PL ~(1 << 4)
+#else
+#define MG62_15PL 0xFFFF
+#endif
+#if (G66PL >= G62PL) || (G66PL == 0)
+#define MG62_16PL ~(1 << 5)
+#else
+#define MG62_16PL 0xFFFF
+#endif
+#if (G67PL >= G62PL) || (G67PL == 0)
+#define MG62_17PL ~(1 << 6)
+#else
+#define MG62_17PL 0xFFFF
+#endif
+#if (G68PL >= G62PL) || (G68PL == 0)
+#define MG62_18PL ~(1 << 7)
+#else
+#define MG62_18PL 0xFFFF
+#endif
+#define MG62_12PL 0x00FD
+#define MG62 (MG62_11PL & MG62_12PL & MG62_13PL & MG62_14PL & \
+ MG62_15PL & MG62_16PL & MG62_17PL & MG62_18PL)
+// End of MG62:
+
+// Beginning of MG63:
+#if (G61PL >= G63PL) || (G61PL == 0)
+#define MG63_11PL ~(1)
+#else
+#define MG63_11PL 0xFFFF
+#endif
+#if (G62PL >= G63PL) || (G62PL == 0)
+#define MG63_12PL ~(1 << 1)
+#else
+#define MG63_12PL 0xFFFF
+#endif
+#if (G64PL >= G63PL) || (G64PL == 0)
+#define MG63_14PL ~(1 << 3)
+#else
+#define MG63_14PL 0xFFFF
+#endif
+#if (G65PL >= G63PL) || (G65PL == 0)
+#define MG63_15PL ~(1 << 4)
+#else
+#define MG63_15PL 0xFFFF
+#endif
+#if (G66PL >= G63PL) || (G66PL == 0)
+#define MG63_16PL ~(1 << 5)
+#else
+#define MG63_16PL 0xFFFF
+#endif
+#if (G67PL >= G63PL) || (G67PL == 0)
+#define MG63_17PL ~(1 << 6)
+#else
+#define MG63_17PL 0xFFFF
+#endif
+#if (G68PL >= G63PL) || (G68PL == 0)
+#define MG63_18PL ~(1 << 7)
+#else
+#define MG63_18PL 0xFFFF
+#endif
+#define MG63_13PL 0x00FB
+#define MG63 (MG63_11PL & MG63_12PL & MG63_13PL & MG63_14PL & \
+ MG63_15PL & MG63_16PL & MG63_17PL & MG63_18PL)
+// End of MG63:
+
+// Beginning of MG64:
+#if (G61PL >= G64PL) || (G61PL == 0)
+#define MG64_11PL ~(1)
+#else
+#define MG64_11PL 0xFFFF
+#endif
+#if (G62PL >= G64PL) || (G62PL == 0)
+#define MG64_12PL ~(1 << 1)
+#else
+#define MG64_12PL 0xFFFF
+#endif
+#if (G63PL >= G64PL) || (G63PL == 0)
+#define MG64_13PL ~(1 << 2)
+#else
+#define MG64_13PL 0xFFFF
+#endif
+#if (G65PL >= G64PL) || (G65PL == 0)
+#define MG64_15PL ~(1 << 4)
+#else
+#define MG64_15PL 0xFFFF
+#endif
+#if (G66PL >= G64PL) || (G66PL == 0)
+#define MG64_16PL ~(1 << 5)
+#else
+#define MG64_16PL 0xFFFF
+#endif
+#if (G67PL >= G64PL) || (G67PL == 0)
+#define MG64_17PL ~(1 << 6)
+#else
+#define MG64_17PL 0xFFFF
+#endif
+#if (G68PL >= G64PL) || (G68PL == 0)
+#define MG64_18PL ~(1 << 7)
+#else
+#define MG64_18PL 0xFFFF
+#endif
+#define MG64_14PL 0x00F7
+#define MG64 (MG64_11PL & MG64_12PL & MG64_13PL & MG64_14PL & \
+ MG64_15PL & MG64_16PL & MG64_17PL & MG64_18PL)
+// End of MG64:
+
+// Beginning of MG65:
+#if (G61PL >= G65PL) || (G61PL == 0)
+#define MG65_11PL ~(1)
+#else
+#define MG65_11PL 0xFFFF
+#endif
+#if (G62PL >= G65PL) || (G62PL == 0)
+#define MG65_12PL ~(1 << 1)
+#else
+#define MG65_12PL 0xFFFF
+#endif
+#if (G63PL >= G65PL) || (G63PL == 0)
+#define MG65_13PL ~(1 << 2)
+#else
+#define MG65_13PL 0xFFFF
+#endif
+#if (G64PL >= G65PL) || (G64PL == 0)
+#define MG65_14PL ~(1 << 3)
+#else
+#define MG65_14PL 0xFFFF
+#endif
+#if (G66PL >= G65PL) || (G66PL == 0)
+#define MG65_16PL ~(1 << 5)
+#else
+#define MG65_16PL 0xFFFF
+#endif
+#if (G67PL >= G65PL) || (G67PL == 0)
+#define MG65_17PL ~(1 << 6)
+#else
+#define MG65_17PL 0xFFFF
+#endif
+#if (G68PL >= G65PL) || (G68PL == 0)
+#define MG65_18PL ~(1 << 7)
+#else
+#define MG65_18PL 0xFFFF
+#endif
+#define MG65_15PL 0x00EF
+#define MG65 (MG65_11PL & MG65_12PL & MG65_13PL & MG65_14PL & \
+ MG65_15PL & MG65_16PL & MG65_17PL & MG65_18PL)
+// End of MG65:
+
+// Beginning of MG66:
+#if (G61PL >= G66PL) || (G61PL == 0)
+#define MG66_11PL ~(1)
+#else
+#define MG66_11PL 0xFFFF
+#endif
+#if (G62PL >= G66PL) || (G62PL == 0)
+#define MG66_12PL ~(1 << 1)
+#else
+#define MG66_12PL 0xFFFF
+#endif
+#if (G63PL >= G66PL) || (G63PL == 0)
+#define MG66_13PL ~(1 << 2)
+#else
+#define MG66_13PL 0xFFFF
+#endif
+#if (G64PL >= G66PL) || (G64PL == 0)
+#define MG66_14PL ~(1 << 3)
+#else
+#define MG66_14PL 0xFFFF
+#endif
+#if (G65PL >= G66PL) || (G65PL == 0)
+#define MG66_15PL ~(1 << 4)
+#else
+#define MG66_15PL 0xFFFF
+#endif
+#if (G67PL >= G66PL) || (G67PL == 0)
+#define MG66_17PL ~(1 << 6)
+#else
+#define MG66_17PL 0xFFFF
+#endif
+#if (G68PL >= G66PL) || (G68PL == 0)
+#define MG66_18PL ~(1 << 7)
+#else
+#define MG66_18PL 0xFFFF
+#endif
+#define MG66_16PL 0x00DF
+#define MG66 (MG66_11PL & MG66_12PL & MG66_13PL & MG66_14PL & \
+ MG66_15PL & MG66_16PL & MG66_17PL & MG66_18PL)
+// End of MG66:
+
+// Beginning of MG67:
+#if (G61PL >= G67PL) || (G61PL == 0)
+#define MG67_11PL ~(1)
+#else
+#define MG67_11PL 0xFFFF
+#endif
+#if (G62PL >= G67PL) || (G62PL == 0)
+#define MG67_12PL ~(1 << 1)
+#else
+#define MG67_12PL 0xFFFF
+#endif
+#if (G63PL >= G67PL) || (G63PL == 0)
+#define MG67_13PL ~(1 << 2)
+#else
+#define MG67_13PL 0xFFFF
+#endif
+#if (G64PL >= G67PL) || (G64PL == 0)
+#define MG67_14PL ~(1 << 3)
+#else
+#define MG67_14PL 0xFFFF
+#endif
+#if (G65PL >= G67PL) || (G65PL == 0)
+#define MG67_15PL ~(1 << 4)
+#else
+#define MG67_15PL 0xFFFF
+#endif
+#if (G66PL >= G67PL) || (G66PL == 0)
+#define MG67_16PL ~(1 << 5)
+#else
+#define MG67_16PL 0xFFFF
+#endif
+#if (G68PL >= G67PL) || (G68PL == 0)
+#define MG67_18PL ~(1 << 7)
+#else
+#define MG67_18PL 0xFFFF
+#endif
+#define MG67_17PL 0x00BF
+#define MG67 (MG67_11PL & MG67_12PL & MG67_13PL & MG67_14PL & \
+ MG67_15PL & MG67_16PL & MG67_17PL & MG67_18PL)
+// End of MG67:
+
+// Beginning of MG68:
+#if (G61PL >= G68PL) || (G61PL == 0)
+#define MG68_11PL ~(1)
+#else
+#define MG68_11PL 0xFFFF
+#endif
+#if (G62PL >= G68PL) || (G62PL == 0)
+#define MG68_12PL ~(1 << 1)
+#else
+#define MG68_12PL 0xFFFF
+#endif
+#if (G63PL >= G68PL) || (G63PL == 0)
+#define MG68_13PL ~(1 << 2)
+#else
+#define MG68_13PL 0xFFFF
+#endif
+#if (G64PL >= G68PL) || (G64PL == 0)
+#define MG68_14PL ~(1 << 3)
+#else
+#define MG68_14PL 0xFFFF
+#endif
+#if (G65PL >= G68PL) || (G65PL == 0)
+#define MG68_15PL ~(1 << 4)
+#else
+#define MG68_15PL 0xFFFF
+#endif
+#if (G66PL >= G68PL) || (G66PL == 0)
+#define MG68_16PL ~(1 << 5)
+#else
+#define MG68_16PL 0xFFFF
+#endif
+#if (G67PL >= G68PL) || (G67PL == 0)
+#define MG68_17PL ~(1 << 6)
+#else
+#define MG68_17PL 0xFFFF
+#endif
+#define MG68_18PL 0x007F
+#define MG68 (MG68_11PL & MG68_12PL & MG68_13PL & MG68_14PL & \
+ MG68_15PL & MG68_16PL & MG68_17PL & MG68_18PL)
+// End of MG68:
+
+//-------------------------------------------------------------------------------
+// Automatically generate PIEIER1 interrupt masks MG71 to MG78:
+//
+
+// Beginning of MG71:
+#if (G72PL >= G71PL) || (G72PL == 0)
+#define MG71_12PL ~(1 << 1)
+#else
+#define MG71_12PL 0xFFFF
+#endif
+#if (G73PL >= G71PL) || (G73PL == 0)
+#define MG71_13PL ~(1 << 2)
+#else
+#define MG71_13PL 0xFFFF
+#endif
+#if (G74PL >= G71PL) || (G74PL == 0)
+#define MG71_14PL ~(1 << 3)
+#else
+#define MG71_14PL 0xFFFF
+#endif
+#if (G75PL >= G71PL) || (G75PL == 0)
+#define MG71_15PL ~(1 << 4)
+#else
+#define MG71_15PL 0xFFFF
+#endif
+#if (G76PL >= G71PL) || (G76PL == 0)
+#define MG71_16PL ~(1 << 5)
+#else
+#define MG71_16PL 0xFFFF
+#endif
+#if (G77PL >= G71PL) || (G77PL == 0)
+#define MG71_17PL ~(1 << 6)
+#else
+#define MG71_17PL 0xFFFF
+#endif
+#if (G78PL >= G71PL) || (G78PL == 0)
+#define MG71_18PL ~(1 << 7)
+#else
+#define MG71_18PL 0xFFFF
+#endif
+#define MG71_11PL 0x00FE
+#define MG71 (MG71_11PL & MG71_12PL & MG71_13PL & MG71_14PL & \
+ MG71_15PL & MG71_16PL & MG71_17PL & MG71_18PL)
+// End of MG71:
+
+// Beginning of MG72:
+#if (G71PL >= G72PL) || (G71PL == 0)
+#define MG72_11PL ~(1)
+#else
+#define MG72_11PL 0xFFFF
+#endif
+#if (G73PL >= G72PL) || (G73PL == 0)
+#define MG72_13PL ~(1 << 2)
+#else
+#define MG72_13PL 0xFFFF
+#endif
+#if (G74PL >= G72PL) || (G74PL == 0)
+#define MG72_14PL ~(1 << 3)
+#else
+#define MG72_14PL 0xFFFF
+#endif
+#if (G75PL >= G72PL) || (G75PL == 0)
+#define MG72_15PL ~(1 << 4)
+#else
+#define MG72_15PL 0xFFFF
+#endif
+#if (G76PL >= G72PL) || (G76PL == 0)
+#define MG72_16PL ~(1 << 5)
+#else
+#define MG72_16PL 0xFFFF
+#endif
+#if (G77PL >= G72PL) || (G77PL == 0)
+#define MG72_17PL ~(1 << 6)
+#else
+#define MG72_17PL 0xFFFF
+#endif
+#if (G78PL >= G72PL) || (G78PL == 0)
+#define MG72_18PL ~(1 << 7)
+#else
+#define MG72_18PL 0xFFFF
+#endif
+#define MG72_12PL 0x00FD
+#define MG72 (MG72_11PL & MG72_12PL & MG72_13PL & MG72_14PL & \
+ MG72_15PL & MG72_16PL & MG72_17PL & MG72_18PL)
+// End of MG72:
+
+// Beginning of MG73:
+#if (G71PL >= G73PL) || (G71PL == 0)
+#define MG73_11PL ~(1)
+#else
+#define MG73_11PL 0xFFFF
+#endif
+#if (G72PL >= G73PL) || (G72PL == 0)
+#define MG73_12PL ~(1 << 1)
+#else
+#define MG73_12PL 0xFFFF
+#endif
+#if (G74PL >= G73PL) || (G74PL == 0)
+#define MG73_14PL ~(1 << 3)
+#else
+#define MG73_14PL 0xFFFF
+#endif
+#if (G75PL >= G73PL) || (G75PL == 0)
+#define MG73_15PL ~(1 << 4)
+#else
+#define MG73_15PL 0xFFFF
+#endif
+#if (G76PL >= G73PL) || (G76PL == 0)
+#define MG73_16PL ~(1 << 5)
+#else
+#define MG73_16PL 0xFFFF
+#endif
+#if (G77PL >= G73PL) || (G77PL == 0)
+#define MG73_17PL ~(1 << 6)
+#else
+#define MG73_17PL 0xFFFF
+#endif
+#if (G78PL >= G73PL) || (G78PL == 0)
+#define MG73_18PL ~(1 << 7)
+#else
+#define MG73_18PL 0xFFFF
+#endif
+#define MG73_13PL 0x00FB
+#define MG73 (MG73_11PL & MG73_12PL & MG73_13PL & MG73_14PL & \
+ MG73_15PL & MG73_16PL & MG73_17PL & MG73_18PL)
+// End of MG73:
+
+// Beginning of MG74:
+#if (G71PL >= G74PL) || (G71PL == 0)
+#define MG74_11PL ~(1)
+#else
+#define MG74_11PL 0xFFFF
+#endif
+#if (G72PL >= G74PL) || (G72PL == 0)
+#define MG74_12PL ~(1 << 1)
+#else
+#define MG74_12PL 0xFFFF
+#endif
+#if (G73PL >= G74PL) || (G73PL == 0)
+#define MG74_13PL ~(1 << 2)
+#else
+#define MG74_13PL 0xFFFF
+#endif
+#if (G75PL >= G74PL) || (G75PL == 0)
+#define MG74_15PL ~(1 << 4)
+#else
+#define MG74_15PL 0xFFFF
+#endif
+#if (G76PL >= G74PL) || (G76PL == 0)
+#define MG74_16PL ~(1 << 5)
+#else
+#define MG74_16PL 0xFFFF
+#endif
+#if (G77PL >= G74PL) || (G77PL == 0)
+#define MG74_17PL ~(1 << 6)
+#else
+#define MG74_17PL 0xFFFF
+#endif
+#if (G78PL >= G74PL) || (G78PL == 0)
+#define MG74_18PL ~(1 << 7)
+#else
+#define MG74_18PL 0xFFFF
+#endif
+#define MG74_14PL 0x00F7
+#define MG74 (MG74_11PL & MG74_12PL & MG74_13PL & MG74_14PL & \
+ MG74_15PL & MG74_16PL & MG74_17PL & MG74_18PL)
+// End of MG74:
+
+// Beginning of MG75:
+#if (G71PL >= G75PL) || (G71PL == 0)
+#define MG75_11PL ~(1)
+#else
+#define MG75_11PL 0xFFFF
+#endif
+#if (G72PL >= G75PL) || (G72PL == 0)
+#define MG75_12PL ~(1 << 1)
+#else
+#define MG75_12PL 0xFFFF
+#endif
+#if (G73PL >= G75PL) || (G73PL == 0)
+#define MG75_13PL ~(1 << 2)
+#else
+#define MG75_13PL 0xFFFF
+#endif
+#if (G74PL >= G75PL) || (G74PL == 0)
+#define MG75_14PL ~(1 << 3)
+#else
+#define MG75_14PL 0xFFFF
+#endif
+#if (G76PL >= G75PL) || (G76PL == 0)
+#define MG75_16PL ~(1 << 5)
+#else
+#define MG75_16PL 0xFFFF
+#endif
+#if (G77PL >= G75PL) || (G77PL == 0)
+#define MG75_17PL ~(1 << 6)
+#else
+#define MG75_17PL 0xFFFF
+#endif
+#if (G78PL >= G75PL) || (G78PL == 0)
+#define MG75_18PL ~(1 << 7)
+#else
+#define MG75_18PL 0xFFFF
+#endif
+#define MG75_15PL 0x00EF
+#define MG75 (MG75_11PL & MG75_12PL & MG75_13PL & MG75_14PL & \
+ MG75_15PL & MG75_16PL & MG75_17PL & MG75_18PL)
+// End of MG75:
+
+// Beginning of MG76:
+#if (G71PL >= G76PL) || (G71PL == 0)
+#define MG76_11PL ~(1)
+#else
+#define MG76_11PL 0xFFFF
+#endif
+#if (G72PL >= G76PL) || (G72PL == 0)
+#define MG76_12PL ~(1 << 1)
+#else
+#define MG76_12PL 0xFFFF
+#endif
+#if (G73PL >= G76PL) || (G73PL == 0)
+#define MG76_13PL ~(1 << 2)
+#else
+#define MG76_13PL 0xFFFF
+#endif
+#if (G74PL >= G76PL) || (G74PL == 0)
+#define MG76_14PL ~(1 << 3)
+#else
+#define MG76_14PL 0xFFFF
+#endif
+#if (G75PL >= G76PL) || (G75PL == 0)
+#define MG76_15PL ~(1 << 4)
+#else
+#define MG76_15PL 0xFFFF
+#endif
+#if (G77PL >= G76PL) || (G77PL == 0)
+#define MG76_17PL ~(1 << 6)
+#else
+#define MG76_17PL 0xFFFF
+#endif
+#if (G78PL >= G76PL) || (G78PL == 0)
+#define MG76_18PL ~(1 << 7)
+#else
+#define MG76_18PL 0xFFFF
+#endif
+#define MG76_16PL 0x00DF
+#define MG76 (MG76_11PL & MG76_12PL & MG76_13PL & MG76_14PL & \
+ MG76_15PL & MG76_16PL & MG76_17PL & MG76_18PL)
+// End of MG76:
+
+// Beginning of MG77:
+#if (G71PL >= G77PL) || (G71PL == 0)
+#define MG77_11PL ~(1)
+#else
+#define MG77_11PL 0xFFFF
+#endif
+#if (G72PL >= G77PL) || (G72PL == 0)
+#define MG77_12PL ~(1 << 1)
+#else
+#define MG77_12PL 0xFFFF
+#endif
+#if (G73PL >= G77PL) || (G73PL == 0)
+#define MG77_13PL ~(1 << 2)
+#else
+#define MG77_13PL 0xFFFF
+#endif
+#if (G74PL >= G77PL) || (G74PL == 0)
+#define MG77_14PL ~(1 << 3)
+#else
+#define MG77_14PL 0xFFFF
+#endif
+#if (G75PL >= G77PL) || (G75PL == 0)
+#define MG77_15PL ~(1 << 4)
+#else
+#define MG77_15PL 0xFFFF
+#endif
+#if (G76PL >= G77PL) || (G76PL == 0)
+#define MG77_16PL ~(1 << 5)
+#else
+#define MG77_16PL 0xFFFF
+#endif
+#if (G78PL >= G77PL) || (G78PL == 0)
+#define MG77_18PL ~(1 << 7)
+#else
+#define MG77_18PL 0xFFFF
+#endif
+#define MG77_17PL 0x00BF
+#define MG77 (MG77_11PL & MG77_12PL & MG77_13PL & MG77_14PL & \
+ MG77_15PL & MG77_16PL & MG77_17PL & MG77_18PL)
+// End of MG77:
+
+// Beginning of MG78:
+#if (G71PL >= G78PL) || (G71PL == 0)
+#define MG78_11PL ~(1)
+#else
+#define MG78_11PL 0xFFFF
+#endif
+#if (G72PL >= G78PL) || (G72PL == 0)
+#define MG78_12PL ~(1 << 1)
+#else
+#define MG78_12PL 0xFFFF
+#endif
+#if (G73PL >= G78PL) || (G73PL == 0)
+#define MG78_13PL ~(1 << 2)
+#else
+#define MG78_13PL 0xFFFF
+#endif
+#if (G74PL >= G78PL) || (G74PL == 0)
+#define MG78_14PL ~(1 << 3)
+#else
+#define MG78_14PL 0xFFFF
+#endif
+#if (G75PL >= G78PL) || (G75PL == 0)
+#define MG78_15PL ~(1 << 4)
+#else
+#define MG78_15PL 0xFFFF
+#endif
+#if (G76PL >= G78PL) || (G76PL == 0)
+#define MG78_16PL ~(1 << 5)
+#else
+#define MG78_16PL 0xFFFF
+#endif
+#if (G77PL >= G78PL) || (G77PL == 0)
+#define MG78_17PL ~(1 << 6)
+#else
+#define MG78_17PL 0xFFFF
+#endif
+#define MG78_18PL 0x007F
+#define MG78 (MG78_11PL & MG78_12PL & MG78_13PL & MG78_14PL & \
+ MG78_15PL & MG78_16PL & MG78_17PL & MG78_18PL)
+// End of MG78:
+
+//-------------------------------------------------------------------------------
+// Automatically generate PIEIER1 interrupt masks MG81 to MG88:
+//
+
+// Beginning of MG81:
+#if (G82PL >= G81PL) || (G82PL == 0)
+#define MG81_12PL ~(1 << 1)
+#else
+#define MG81_12PL 0xFFFF
+#endif
+#if (G83PL >= G81PL) || (G83PL == 0)
+#define MG81_13PL ~(1 << 2)
+#else
+#define MG81_13PL 0xFFFF
+#endif
+#if (G84PL >= G81PL) || (G84PL == 0)
+#define MG81_14PL ~(1 << 3)
+#else
+#define MG81_14PL 0xFFFF
+#endif
+#if (G85PL >= G81PL) || (G85PL == 0)
+#define MG81_15PL ~(1 << 4)
+#else
+#define MG81_15PL 0xFFFF
+#endif
+#if (G86PL >= G81PL) || (G86PL == 0)
+#define MG81_16PL ~(1 << 5)
+#else
+#define MG81_16PL 0xFFFF
+#endif
+#if (G87PL >= G81PL) || (G87PL == 0)
+#define MG81_17PL ~(1 << 6)
+#else
+#define MG81_17PL 0xFFFF
+#endif
+#if (G88PL >= G81PL) || (G88PL == 0)
+#define MG81_18PL ~(1 << 7)
+#else
+#define MG81_18PL 0xFFFF
+#endif
+#define MG81_11PL 0x00FE
+#define MG81 (MG81_11PL & MG81_12PL & MG81_13PL & MG81_14PL & \
+ MG81_15PL & MG81_16PL & MG81_17PL & MG81_18PL)
+// End of MG81:
+
+// Beginning of MG82:
+#if (G81PL >= G82PL) || (G81PL == 0)
+#define MG82_11PL ~(1)
+#else
+#define MG82_11PL 0xFFFF
+#endif
+#if (G83PL >= G82PL) || (G83PL == 0)
+#define MG82_13PL ~(1 << 2)
+#else
+#define MG82_13PL 0xFFFF
+#endif
+#if (G84PL >= G82PL) || (G84PL == 0)
+#define MG82_14PL ~(1 << 3)
+#else
+#define MG82_14PL 0xFFFF
+#endif
+#if (G85PL >= G82PL) || (G85PL == 0)
+#define MG82_15PL ~(1 << 4)
+#else
+#define MG82_15PL 0xFFFF
+#endif
+#if (G86PL >= G82PL) || (G86PL == 0)
+#define MG82_16PL ~(1 << 5)
+#else
+#define MG82_16PL 0xFFFF
+#endif
+#if (G87PL >= G82PL) || (G87PL == 0)
+#define MG82_17PL ~(1 << 6)
+#else
+#define MG82_17PL 0xFFFF
+#endif
+#if (G88PL >= G82PL) || (G88PL == 0)
+#define MG82_18PL ~(1 << 7)
+#else
+#define MG82_18PL 0xFFFF
+#endif
+#define MG82_12PL 0x00FD
+#define MG82 (MG82_11PL & MG82_12PL & MG82_13PL & MG82_14PL & \
+ MG82_15PL & MG82_16PL & MG82_17PL & MG82_18PL)
+// End of MG82:
+
+// Beginning of MG83:
+#if (G81PL >= G83PL) || (G81PL == 0)
+#define MG83_11PL ~(1)
+#else
+#define MG83_11PL 0xFFFF
+#endif
+#if (G82PL >= G83PL) || (G82PL == 0)
+#define MG83_12PL ~(1 << 1)
+#else
+#define MG83_12PL 0xFFFF
+#endif
+#if (G84PL >= G83PL) || (G84PL == 0)
+#define MG83_14PL ~(1 << 3)
+#else
+#define MG83_14PL 0xFFFF
+#endif
+#if (G85PL >= G83PL) || (G85PL == 0)
+#define MG83_15PL ~(1 << 4)
+#else
+#define MG83_15PL 0xFFFF
+#endif
+#if (G86PL >= G83PL) || (G86PL == 0)
+#define MG83_16PL ~(1 << 5)
+#else
+#define MG83_16PL 0xFFFF
+#endif
+#if (G87PL >= G83PL) || (G87PL == 0)
+#define MG83_17PL ~(1 << 6)
+#else
+#define MG83_17PL 0xFFFF
+#endif
+#if (G88PL >= G83PL) || (G88PL == 0)
+#define MG83_18PL ~(1 << 7)
+#else
+#define MG83_18PL 0xFFFF
+#endif
+#define MG83_13PL 0x00FB
+#define MG83 (MG83_11PL & MG83_12PL & MG83_13PL & MG83_14PL & \
+ MG83_15PL & MG83_16PL & MG83_17PL & MG83_18PL)
+// End of MG83:
+
+// Beginning of MG84:
+#if (G81PL >= G84PL) || (G81PL == 0)
+#define MG84_11PL ~(1)
+#else
+#define MG84_11PL 0xFFFF
+#endif
+#if (G82PL >= G84PL) || (G82PL == 0)
+#define MG84_12PL ~(1 << 1)
+#else
+#define MG84_12PL 0xFFFF
+#endif
+#if (G83PL >= G84PL) || (G83PL == 0)
+#define MG84_13PL ~(1 << 2)
+#else
+#define MG84_13PL 0xFFFF
+#endif
+#if (G85PL >= G84PL) || (G85PL == 0)
+#define MG84_15PL ~(1 << 4)
+#else
+#define MG84_15PL 0xFFFF
+#endif
+#if (G86PL >= G84PL) || (G86PL == 0)
+#define MG84_16PL ~(1 << 5)
+#else
+#define MG84_16PL 0xFFFF
+#endif
+#if (G87PL >= G84PL) || (G87PL == 0)
+#define MG84_17PL ~(1 << 6)
+#else
+#define MG84_17PL 0xFFFF
+#endif
+#if (G88PL >= G84PL) || (G88PL == 0)
+#define MG84_18PL ~(1 << 7)
+#else
+#define MG84_18PL 0xFFFF
+#endif
+#define MG84_14PL 0x00F7
+#define MG84 (MG84_11PL & MG84_12PL & MG84_13PL & MG84_14PL & \
+ MG84_15PL & MG84_16PL & MG84_17PL & MG84_18PL)
+// End of MG84:
+
+// Beginning of MG85:
+#if (G81PL >= G85PL) || (G81PL == 0)
+#define MG85_11PL ~(1)
+#else
+#define MG85_11PL 0xFFFF
+#endif
+#if (G82PL >= G85PL) || (G82PL == 0)
+#define MG85_12PL ~(1 << 1)
+#else
+#define MG85_12PL 0xFFFF
+#endif
+#if (G83PL >= G85PL) || (G83PL == 0)
+#define MG85_13PL ~(1 << 2)
+#else
+#define MG85_13PL 0xFFFF
+#endif
+#if (G84PL >= G85PL) || (G84PL == 0)
+#define MG85_14PL ~(1 << 3)
+#else
+#define MG85_14PL 0xFFFF
+#endif
+#if (G86PL >= G85PL) || (G86PL == 0)
+#define MG85_16PL ~(1 << 5)
+#else
+#define MG85_16PL 0xFFFF
+#endif
+#if (G87PL >= G85PL) || (G87PL == 0)
+#define MG85_17PL ~(1 << 6)
+#else
+#define MG85_17PL 0xFFFF
+#endif
+#if (G88PL >= G85PL) || (G88PL == 0)
+#define MG85_18PL ~(1 << 7)
+#else
+#define MG85_18PL 0xFFFF
+#endif
+#define MG85_15PL 0x00EF
+#define MG85 (MG85_11PL & MG85_12PL & MG85_13PL & MG85_14PL & \
+ MG85_15PL & MG85_16PL & MG85_17PL & MG85_18PL)
+// End of MG85:
+
+// Beginning of MG86:
+#if (G81PL >= G86PL) || (G81PL == 0)
+#define MG86_11PL ~(1)
+#else
+#define MG86_11PL 0xFFFF
+#endif
+#if (G82PL >= G86PL) || (G82PL == 0)
+#define MG86_12PL ~(1 << 1)
+#else
+#define MG86_12PL 0xFFFF
+#endif
+#if (G83PL >= G86PL) || (G83PL == 0)
+#define MG86_13PL ~(1 << 2)
+#else
+#define MG86_13PL 0xFFFF
+#endif
+#if (G84PL >= G86PL) || (G84PL == 0)
+#define MG86_14PL ~(1 << 3)
+#else
+#define MG86_14PL 0xFFFF
+#endif
+#if (G85PL >= G86PL) || (G85PL == 0)
+#define MG86_15PL ~(1 << 4)
+#else
+#define MG86_15PL 0xFFFF
+#endif
+#if (G87PL >= G86PL) || (G87PL == 0)
+#define MG86_17PL ~(1 << 6)
+#else
+#define MG86_17PL 0xFFFF
+#endif
+#if (G88PL >= G86PL) || (G88PL == 0)
+#define MG86_18PL ~(1 << 7)
+#else
+#define MG86_18PL 0xFFFF
+#endif
+#define MG86_16PL 0x00DF
+#define MG86 (MG86_11PL & MG86_12PL & MG86_13PL & MG86_14PL & \
+ MG86_15PL & MG86_16PL & MG86_17PL & MG86_18PL)
+// End of MG86:
+
+// Beginning of MG87:
+#if (G81PL >= G87PL) || (G81PL == 0)
+#define MG87_11PL ~(1)
+#else
+#define MG87_11PL 0xFFFF
+#endif
+#if (G82PL >= G87PL) || (G82PL == 0)
+#define MG87_12PL ~(1 << 1)
+#else
+#define MG87_12PL 0xFFFF
+#endif
+#if (G83PL >= G87PL) || (G83PL == 0)
+#define MG87_13PL ~(1 << 2)
+#else
+#define MG87_13PL 0xFFFF
+#endif
+#if (G84PL >= G87PL) || (G84PL == 0)
+#define MG87_14PL ~(1 << 3)
+#else
+#define MG87_14PL 0xFFFF
+#endif
+#if (G85PL >= G87PL) || (G85PL == 0)
+#define MG87_15PL ~(1 << 4)
+#else
+#define MG87_15PL 0xFFFF
+#endif
+#if (G86PL >= G87PL) || (G86PL == 0)
+#define MG87_16PL ~(1 << 5)
+#else
+#define MG87_16PL 0xFFFF
+#endif
+#if (G88PL >= G87PL) || (G88PL == 0)
+#define MG87_18PL ~(1 << 7)
+#else
+#define MG87_18PL 0xFFFF
+#endif
+#define MG87_17PL 0x00BF
+#define MG87 (MG87_11PL & MG87_12PL & MG87_13PL & MG87_14PL & \
+ MG87_15PL & MG87_16PL & MG87_17PL & MG87_18PL)
+// End of MG87:
+
+// Beginning of MG88:
+#if (G81PL >= G88PL) || (G81PL == 0)
+#define MG88_11PL ~(1)
+#else
+#define MG88_11PL 0xFFFF
+#endif
+#if (G82PL >= G88PL) || (G82PL == 0)
+#define MG88_12PL ~(1 << 1)
+#else
+#define MG88_12PL 0xFFFF
+#endif
+#if (G83PL >= G88PL) || (G83PL == 0)
+#define MG88_13PL ~(1 << 2)
+#else
+#define MG88_13PL 0xFFFF
+#endif
+#if (G84PL >= G88PL) || (G84PL == 0)
+#define MG88_14PL ~(1 << 3)
+#else
+#define MG88_14PL 0xFFFF
+#endif
+#if (G85PL >= G88PL) || (G85PL == 0)
+#define MG88_15PL ~(1 << 4)
+#else
+#define MG88_15PL 0xFFFF
+#endif
+#if (G86PL >= G88PL) || (G86PL == 0)
+#define MG88_16PL ~(1 << 5)
+#else
+#define MG88_16PL 0xFFFF
+#endif
+#if (G87PL >= G88PL) || (G87PL == 0)
+#define MG88_17PL ~(1 << 6)
+#else
+#define MG88_17PL 0xFFFF
+#endif
+#define MG88_18PL 0x007F
+#define MG88 (MG88_11PL & MG88_12PL & MG88_13PL & MG88_14PL & \
+ MG88_15PL & MG88_16PL & MG88_17PL & MG88_18PL)
+// End of MG88:
+
+//-------------------------------------------------------------------------------
+// Automatically generate PIEIER1 interrupt masks MG91 to MG98:
+//
+
+// Beginning of MG91:
+#if (G92PL >= G91PL) || (G92PL == 0)
+#define MG91_12PL ~(1 << 1)
+#else
+#define MG91_12PL 0xFFFF
+#endif
+#if (G93PL >= G91PL) || (G93PL == 0)
+#define MG91_13PL ~(1 << 2)
+#else
+#define MG91_13PL 0xFFFF
+#endif
+#if (G94PL >= G91PL) || (G94PL == 0)
+#define MG91_14PL ~(1 << 3)
+#else
+#define MG91_14PL 0xFFFF
+#endif
+#if (G95PL >= G91PL) || (G95PL == 0)
+#define MG91_15PL ~(1 << 4)
+#else
+#define MG91_15PL 0xFFFF
+#endif
+#if (G96PL >= G91PL) || (G96PL == 0)
+#define MG91_16PL ~(1 << 5)
+#else
+#define MG91_16PL 0xFFFF
+#endif
+#if (G97PL >= G91PL) || (G97PL == 0)
+#define MG91_17PL ~(1 << 6)
+#else
+#define MG91_17PL 0xFFFF
+#endif
+#if (G98PL >= G91PL) || (G98PL == 0)
+#define MG91_18PL ~(1 << 7)
+#else
+#define MG91_18PL 0xFFFF
+#endif
+#define MG91_11PL 0x00FE
+#define MG91 (MG91_11PL & MG91_12PL & MG91_13PL & MG91_14PL & \
+ MG91_15PL & MG91_16PL & MG91_17PL & MG91_18PL)
+// End of MG91:
+
+// Beginning of MG92:
+#if (G91PL >= G92PL) || (G91PL == 0)
+#define MG92_11PL ~(1)
+#else
+#define MG92_11PL 0xFFFF
+#endif
+#if (G93PL >= G92PL) || (G93PL == 0)
+#define MG92_13PL ~(1 << 2)
+#else
+#define MG92_13PL 0xFFFF
+#endif
+#if (G94PL >= G92PL) || (G94PL == 0)
+#define MG92_14PL ~(1 << 3)
+#else
+#define MG92_14PL 0xFFFF
+#endif
+#if (G95PL >= G92PL) || (G95PL == 0)
+#define MG92_15PL ~(1 << 4)
+#else
+#define MG92_15PL 0xFFFF
+#endif
+#if (G96PL >= G92PL) || (G96PL == 0)
+#define MG92_16PL ~(1 << 5)
+#else
+#define MG92_16PL 0xFFFF
+#endif
+#if (G97PL >= G92PL) || (G97PL == 0)
+#define MG92_17PL ~(1 << 6)
+#else
+#define MG92_17PL 0xFFFF
+#endif
+#if (G98PL >= G92PL) || (G98PL == 0)
+#define MG92_18PL ~(1 << 7)
+#else
+#define MG92_18PL 0xFFFF
+#endif
+#define MG92_12PL 0x00FD
+#define MG92 (MG92_11PL & MG92_12PL & MG92_13PL & MG92_14PL & \
+ MG92_15PL & MG92_16PL & MG92_17PL & MG92_18PL)
+// End of MG92:
+
+// Beginning of MG93:
+#if (G91PL >= G93PL) || (G91PL == 0)
+#define MG93_11PL ~(1)
+#else
+#define MG93_11PL 0xFFFF
+#endif
+#if (G92PL >= G93PL) || (G92PL == 0)
+#define MG93_12PL ~(1 << 1)
+#else
+#define MG93_12PL 0xFFFF
+#endif
+#if (G94PL >= G93PL) || (G94PL == 0)
+#define MG93_14PL ~(1 << 3)
+#else
+#define MG93_14PL 0xFFFF
+#endif
+#if (G95PL >= G93PL) || (G95PL == 0)
+#define MG93_15PL ~(1 << 4)
+#else
+#define MG93_15PL 0xFFFF
+#endif
+#if (G96PL >= G93PL) || (G96PL == 0)
+#define MG93_16PL ~(1 << 5)
+#else
+#define MG93_16PL 0xFFFF
+#endif
+#if (G97PL >= G93PL) || (G97PL == 0)
+#define MG93_17PL ~(1 << 6)
+#else
+#define MG93_17PL 0xFFFF
+#endif
+#if (G98PL >= G93PL) || (G98PL == 0)
+#define MG93_18PL ~(1 << 7)
+#else
+#define MG93_18PL 0xFFFF
+#endif
+#define MG93_13PL 0x00FB
+#define MG93 (MG93_11PL & MG93_12PL & MG93_13PL & MG93_14PL & \
+ MG93_15PL & MG93_16PL & MG93_17PL & MG93_18PL)
+// End of MG93:
+
+// Beginning of MG94:
+#if (G91PL >= G94PL) || (G91PL == 0)
+#define MG94_11PL ~(1)
+#else
+#define MG94_11PL 0xFFFF
+#endif
+#if (G92PL >= G94PL) || (G92PL == 0)
+#define MG94_12PL ~(1 << 1)
+#else
+#define MG94_12PL 0xFFFF
+#endif
+#if (G93PL >= G94PL) || (G93PL == 0)
+#define MG94_13PL ~(1 << 2)
+#else
+#define MG94_13PL 0xFFFF
+#endif
+#if (G95PL >= G94PL) || (G95PL == 0)
+#define MG94_15PL ~(1 << 4)
+#else
+#define MG94_15PL 0xFFFF
+#endif
+#if (G96PL >= G94PL) || (G96PL == 0)
+#define MG94_16PL ~(1 << 5)
+#else
+#define MG94_16PL 0xFFFF
+#endif
+#if (G97PL >= G94PL) || (G97PL == 0)
+#define MG94_17PL ~(1 << 6)
+#else
+#define MG94_17PL 0xFFFF
+#endif
+#if (G98PL >= G94PL) || (G98PL == 0)
+#define MG94_18PL ~(1 << 7)
+#else
+#define MG94_18PL 0xFFFF
+#endif
+#define MG94_14PL 0x00F7
+#define MG94 (MG94_11PL & MG94_12PL & MG94_13PL & MG94_14PL & \
+ MG94_15PL & MG94_16PL & MG94_17PL & MG94_18PL)
+// End of MG94:
+
+// Beginning of MG95:
+#if (G91PL >= G95PL) || (G91PL == 0)
+#define MG95_11PL ~(1)
+#else
+#define MG95_11PL 0xFFFF
+#endif
+#if (G92PL >= G95PL) || (G92PL == 0)
+#define MG95_12PL ~(1 << 1)
+#else
+#define MG95_12PL 0xFFFF
+#endif
+#if (G93PL >= G95PL) || (G93PL == 0)
+#define MG95_13PL ~(1 << 2)
+#else
+#define MG95_13PL 0xFFFF
+#endif
+#if (G94PL >= G95PL) || (G94PL == 0)
+#define MG95_14PL ~(1 << 3)
+#else
+#define MG95_14PL 0xFFFF
+#endif
+#if (G96PL >= G95PL) || (G96PL == 0)
+#define MG95_16PL ~(1 << 5)
+#else
+#define MG95_16PL 0xFFFF
+#endif
+#if (G97PL >= G95PL) || (G97PL == 0)
+#define MG95_17PL ~(1 << 6)
+#else
+#define MG95_17PL 0xFFFF
+#endif
+#if (G98PL >= G95PL) || (G98PL == 0)
+#define MG95_18PL ~(1 << 7)
+#else
+#define MG95_18PL 0xFFFF
+#endif
+#define MG95_15PL 0x00EF
+#define MG95 (MG95_11PL & MG95_12PL & MG95_13PL & MG95_14PL & \
+ MG95_15PL & MG95_16PL & MG95_17PL & MG95_18PL)
+// End of MG95:
+
+// Beginning of MG96:
+#if (G91PL >= G96PL) || (G91PL == 0)
+#define MG96_11PL ~(1)
+#else
+#define MG96_11PL 0xFFFF
+#endif
+#if (G92PL >= G96PL) || (G92PL == 0)
+#define MG96_12PL ~(1 << 1)
+#else
+#define MG96_12PL 0xFFFF
+#endif
+#if (G93PL >= G96PL) || (G93PL == 0)
+#define MG96_13PL ~(1 << 2)
+#else
+#define MG96_13PL 0xFFFF
+#endif
+#if (G94PL >= G96PL) || (G94PL == 0)
+#define MG96_14PL ~(1 << 3)
+#else
+#define MG96_14PL 0xFFFF
+#endif
+#if (G95PL >= G96PL) || (G95PL == 0)
+#define MG96_15PL ~(1 << 4)
+#else
+#define MG96_15PL 0xFFFF
+#endif
+#if (G97PL >= G96PL) || (G97PL == 0)
+#define MG96_17PL ~(1 << 6)
+#else
+#define MG96_17PL 0xFFFF
+#endif
+#if (G98PL >= G96PL) || (G98PL == 0)
+#define MG96_18PL ~(1 << 7)
+#else
+#define MG96_18PL 0xFFFF
+#endif
+#define MG96_16PL 0x00DF
+#define MG96 (MG96_11PL & MG96_12PL & MG96_13PL & MG96_14PL & \
+ MG96_15PL & MG96_16PL & MG96_17PL & MG96_18PL)
+// End of MG96:
+
+// Beginning of MG97:
+#if (G91PL >= G97PL) || (G91PL == 0)
+#define MG97_11PL ~(1)
+#else
+#define MG97_11PL 0xFFFF
+#endif
+#if (G92PL >= G97PL) || (G92PL == 0)
+#define MG97_12PL ~(1 << 1)
+#else
+#define MG97_12PL 0xFFFF
+#endif
+#if (G93PL >= G97PL) || (G93PL == 0)
+#define MG97_13PL ~(1 << 2)
+#else
+#define MG97_13PL 0xFFFF
+#endif
+#if (G94PL >= G97PL) || (G94PL == 0)
+#define MG97_14PL ~(1 << 3)
+#else
+#define MG97_14PL 0xFFFF
+#endif
+#if (G95PL >= G97PL) || (G95PL == 0)
+#define MG97_15PL ~(1 << 4)
+#else
+#define MG97_15PL 0xFFFF
+#endif
+#if (G96PL >= G97PL) || (G96PL == 0)
+#define MG97_16PL ~(1 << 5)
+#else
+#define MG97_16PL 0xFFFF
+#endif
+#if (G98PL >= G97PL) || (G98PL == 0)
+#define MG97_18PL ~(1 << 7)
+#else
+#define MG97_18PL 0xFFFF
+#endif
+#define MG97_17PL 0x00BF
+#define MG97 (MG97_11PL & MG97_12PL & MG97_13PL & MG97_14PL & \
+ MG97_15PL & MG97_16PL & MG97_17PL & MG97_18PL)
+// End of MG97:
+
+// Beginning of MG98:
+#if (G91PL >= G98PL) || (G91PL == 0)
+#define MG98_11PL ~(1)
+#else
+#define MG98_11PL 0xFFFF
+#endif
+#if (G92PL >= G98PL) || (G92PL == 0)
+#define MG98_12PL ~(1 << 1)
+#else
+#define MG98_12PL 0xFFFF
+#endif
+#if (G93PL >= G98PL) || (G93PL == 0)
+#define MG98_13PL ~(1 << 2)
+#else
+#define MG98_13PL 0xFFFF
+#endif
+#if (G94PL >= G98PL) || (G94PL == 0)
+#define MG98_14PL ~(1 << 3)
+#else
+#define MG98_14PL 0xFFFF
+#endif
+#if (G95PL >= G98PL) || (G95PL == 0)
+#define MG98_15PL ~(1 << 4)
+#else
+#define MG98_15PL 0xFFFF
+#endif
+#if (G96PL >= G98PL) || (G96PL == 0)
+#define MG98_16PL ~(1 << 5)
+#else
+#define MG98_16PL 0xFFFF
+#endif
+#if (G97PL >= G98PL) || (G97PL == 0)
+#define MG98_17PL ~(1 << 6)
+#else
+#define MG98_17PL 0xFFFF
+#endif
+#define MG98_18PL 0x007F
+#define MG98 (MG98_11PL & MG98_12PL & MG98_13PL & MG98_14PL & \
+ MG98_15PL & MG98_16PL & MG98_17PL & MG98_18PL)
+// End of MG98:
+
+//-------------------------------------------------------------------------------
+// Automatically generate PIEIER1 interrupt masks MG101 to MG108:
+//
+
+// Beginning of MG101:
+#if (G102PL >= G101PL) || (G102PL == 0)
+#define MG101_12PL ~(1 << 1)
+#else
+#define MG101_12PL 0xFFFF
+#endif
+#if (G103PL >= G101PL) || (G103PL == 0)
+#define MG101_13PL ~(1 << 2)
+#else
+#define MG101_13PL 0xFFFF
+#endif
+#if (G104PL >= G101PL) || (G104PL == 0)
+#define MG101_14PL ~(1 << 3)
+#else
+#define MG101_14PL 0xFFFF
+#endif
+#if (G105PL >= G101PL) || (G105PL == 0)
+#define MG101_15PL ~(1 << 4)
+#else
+#define MG101_15PL 0xFFFF
+#endif
+#if (G106PL >= G101PL) || (G106PL == 0)
+#define MG101_16PL ~(1 << 5)
+#else
+#define MG101_16PL 0xFFFF
+#endif
+#if (G107PL >= G101PL) || (G107PL == 0)
+#define MG101_17PL ~(1 << 6)
+#else
+#define MG101_17PL 0xFFFF
+#endif
+#if (G108PL >= G101PL) || (G108PL == 0)
+#define MG101_18PL ~(1 << 7)
+#else
+#define MG101_18PL 0xFFFF
+#endif
+#define MG101_11PL 0x00FE
+#define MG101 (MG101_11PL & MG101_12PL & MG101_13PL & MG101_14PL & \
+ MG101_15PL & MG101_16PL & MG101_17PL & MG101_18PL)
+// End of MG101:
+
+// Beginning of MG102:
+#if (G101PL >= G102PL) || (G101PL == 0)
+#define MG102_11PL ~(1)
+#else
+#define MG102_11PL 0xFFFF
+#endif
+#if (G103PL >= G102PL) || (G103PL == 0)
+#define MG102_13PL ~(1 << 2)
+#else
+#define MG102_13PL 0xFFFF
+#endif
+#if (G104PL >= G102PL) || (G104PL == 0)
+#define MG102_14PL ~(1 << 3)
+#else
+#define MG102_14PL 0xFFFF
+#endif
+#if (G105PL >= G102PL) || (G105PL == 0)
+#define MG102_15PL ~(1 << 4)
+#else
+#define MG102_15PL 0xFFFF
+#endif
+#if (G106PL >= G102PL) || (G106PL == 0)
+#define MG102_16PL ~(1 << 5)
+#else
+#define MG102_16PL 0xFFFF
+#endif
+#if (G107PL >= G102PL) || (G107PL == 0)
+#define MG102_17PL ~(1 << 6)
+#else
+#define MG102_17PL 0xFFFF
+#endif
+#if (G108PL >= G102PL) || (G108PL == 0)
+#define MG102_18PL ~(1 << 7)
+#else
+#define MG102_18PL 0xFFFF
+#endif
+#define MG102_12PL 0x00FD
+#define MG102 (MG102_11PL & MG102_12PL & MG102_13PL & MG102_14PL & \
+ MG102_15PL & MG102_16PL & MG102_17PL & MG102_18PL)
+// End of MG102:
+
+// Beginning of MG103:
+#if (G101PL >= G103PL) || (G101PL == 0)
+#define MG103_11PL ~(1)
+#else
+#define MG103_11PL 0xFFFF
+#endif
+#if (G102PL >= G103PL) || (G102PL == 0)
+#define MG103_12PL ~(1 << 1)
+#else
+#define MG103_12PL 0xFFFF
+#endif
+#if (G104PL >= G103PL) || (G104PL == 0)
+#define MG103_14PL ~(1 << 3)
+#else
+#define MG103_14PL 0xFFFF
+#endif
+#if (G105PL >= G103PL) || (G105PL == 0)
+#define MG103_15PL ~(1 << 4)
+#else
+#define MG103_15PL 0xFFFF
+#endif
+#if (G106PL >= G103PL) || (G106PL == 0)
+#define MG103_16PL ~(1 << 5)
+#else
+#define MG103_16PL 0xFFFF
+#endif
+#if (G107PL >= G103PL) || (G107PL == 0)
+#define MG103_17PL ~(1 << 6)
+#else
+#define MG103_17PL 0xFFFF
+#endif
+#if (G108PL >= G103PL) || (G108PL == 0)
+#define MG103_18PL ~(1 << 7)
+#else
+#define MG103_18PL 0xFFFF
+#endif
+#define MG103_13PL 0x00FB
+#define MG103 (MG103_11PL & MG103_12PL & MG103_13PL & MG103_14PL & \
+ MG103_15PL & MG103_16PL & MG103_17PL & MG103_18PL)
+// End of MG103:
+
+// Beginning of MG104:
+#if (G101PL >= G104PL) || (G101PL == 0)
+#define MG104_11PL ~(1)
+#else
+#define MG104_11PL 0xFFFF
+#endif
+#if (G102PL >= G104PL) || (G102PL == 0)
+#define MG104_12PL ~(1 << 1)
+#else
+#define MG104_12PL 0xFFFF
+#endif
+#if (G103PL >= G104PL) || (G103PL == 0)
+#define MG104_13PL ~(1 << 2)
+#else
+#define MG104_13PL 0xFFFF
+#endif
+#if (G105PL >= G104PL) || (G105PL == 0)
+#define MG104_15PL ~(1 << 4)
+#else
+#define MG104_15PL 0xFFFF
+#endif
+#if (G106PL >= G104PL) || (G106PL == 0)
+#define MG104_16PL ~(1 << 5)
+#else
+#define MG104_16PL 0xFFFF
+#endif
+#if (G107PL >= G104PL) || (G107PL == 0)
+#define MG104_17PL ~(1 << 6)
+#else
+#define MG104_17PL 0xFFFF
+#endif
+#if (G108PL >= G104PL) || (G108PL == 0)
+#define MG104_18PL ~(1 << 7)
+#else
+#define MG104_18PL 0xFFFF
+#endif
+#define MG104_14PL 0x00F7
+#define MG104 (MG104_11PL & MG104_12PL & MG104_13PL & MG104_14PL & \
+ MG104_15PL & MG104_16PL & MG104_17PL & MG104_18PL)
+// End of MG104:
+
+// Beginning of MG105:
+#if (G101PL >= G105PL) || (G101PL == 0)
+#define MG105_11PL ~(1)
+#else
+#define MG105_11PL 0xFFFF
+#endif
+#if (G102PL >= G105PL) || (G102PL == 0)
+#define MG105_12PL ~(1 << 1)
+#else
+#define MG105_12PL 0xFFFF
+#endif
+#if (G103PL >= G105PL) || (G103PL == 0)
+#define MG105_13PL ~(1 << 2)
+#else
+#define MG105_13PL 0xFFFF
+#endif
+#if (G104PL >= G105PL) || (G104PL == 0)
+#define MG105_14PL ~(1 << 3)
+#else
+#define MG105_14PL 0xFFFF
+#endif
+#if (G106PL >= G105PL) || (G106PL == 0)
+#define MG105_16PL ~(1 << 5)
+#else
+#define MG105_16PL 0xFFFF
+#endif
+#if (G107PL >= G105PL) || (G107PL == 0)
+#define MG105_17PL ~(1 << 6)
+#else
+#define MG105_17PL 0xFFFF
+#endif
+#if (G108PL >= G105PL) || (G108PL == 0)
+#define MG105_18PL ~(1 << 7)
+#else
+#define MG105_18PL 0xFFFF
+#endif
+#define MG105_15PL 0x00EF
+#define MG105 (MG105_11PL & MG105_12PL & MG105_13PL & MG105_14PL & \
+ MG105_15PL & MG105_16PL & MG105_17PL & MG105_18PL)
+// End of MG105:
+
+// Beginning of MG106:
+#if (G101PL >= G106PL) || (G101PL == 0)
+#define MG106_11PL ~(1)
+#else
+#define MG106_11PL 0xFFFF
+#endif
+#if (G102PL >= G106PL) || (G102PL == 0)
+#define MG106_12PL ~(1 << 1)
+#else
+#define MG106_12PL 0xFFFF
+#endif
+#if (G103PL >= G106PL) || (G103PL == 0)
+#define MG106_13PL ~(1 << 2)
+#else
+#define MG106_13PL 0xFFFF
+#endif
+#if (G104PL >= G106PL) || (G104PL == 0)
+#define MG106_14PL ~(1 << 3)
+#else
+#define MG106_14PL 0xFFFF
+#endif
+#if (G105PL >= G106PL) || (G105PL == 0)
+#define MG106_15PL ~(1 << 4)
+#else
+#define MG106_15PL 0xFFFF
+#endif
+#if (G107PL >= G106PL) || (G107PL == 0)
+#define MG106_17PL ~(1 << 6)
+#else
+#define MG106_17PL 0xFFFF
+#endif
+#if (G108PL >= G106PL) || (G108PL == 0)
+#define MG106_18PL ~(1 << 7)
+#else
+#define MG106_18PL 0xFFFF
+#endif
+#define MG106_16PL 0x00DF
+#define MG106 (MG106_11PL & MG106_12PL & MG106_13PL & MG106_14PL & \
+ MG106_15PL & MG106_16PL & MG106_17PL & MG106_18PL)
+// End of MG106:
+
+// Beginning of MG107:
+#if (G101PL >= G107PL) || (G101PL == 0)
+#define MG107_11PL ~(1)
+#else
+#define MG107_11PL 0xFFFF
+#endif
+#if (G102PL >= G107PL) || (G102PL == 0)
+#define MG107_12PL ~(1 << 1)
+#else
+#define MG107_12PL 0xFFFF
+#endif
+#if (G103PL >= G107PL) || (G103PL == 0)
+#define MG107_13PL ~(1 << 2)
+#else
+#define MG107_13PL 0xFFFF
+#endif
+#if (G104PL >= G107PL) || (G104PL == 0)
+#define MG107_14PL ~(1 << 3)
+#else
+#define MG107_14PL 0xFFFF
+#endif
+#if (G105PL >= G107PL) || (G105PL == 0)
+#define MG107_15PL ~(1 << 4)
+#else
+#define MG107_15PL 0xFFFF
+#endif
+#if (G106PL >= G107PL) || (G106PL == 0)
+#define MG107_16PL ~(1 << 5)
+#else
+#define MG107_16PL 0xFFFF
+#endif
+#if (G108PL >= G107PL) || (G108PL == 0)
+#define MG107_18PL ~(1 << 7)
+#else
+#define MG107_18PL 0xFFFF
+#endif
+#define MG107_17PL 0x00BF
+#define MG107 (MG107_11PL & MG107_12PL & MG107_13PL & MG107_14PL & \
+ MG107_15PL & MG107_16PL & MG107_17PL & MG107_18PL)
+// End of MG107:
+
+// Beginning of MG108:
+#if (G101PL >= G108PL) || (G101PL == 0)
+#define MG108_11PL ~(1)
+#else
+#define MG108_11PL 0xFFFF
+#endif
+#if (G102PL >= G108PL) || (G102PL == 0)
+#define MG108_12PL ~(1 << 1)
+#else
+#define MG108_12PL 0xFFFF
+#endif
+#if (G103PL >= G108PL) || (G103PL == 0)
+#define MG108_13PL ~(1 << 2)
+#else
+#define MG108_13PL 0xFFFF
+#endif
+#if (G104PL >= G108PL) || (G104PL == 0)
+#define MG108_14PL ~(1 << 3)
+#else
+#define MG108_14PL 0xFFFF
+#endif
+#if (G105PL >= G108PL) || (G105PL == 0)
+#define MG108_15PL ~(1 << 4)
+#else
+#define MG108_15PL 0xFFFF
+#endif
+#if (G106PL >= G108PL) || (G106PL == 0)
+#define MG108_16PL ~(1 << 5)
+#else
+#define MG108_16PL 0xFFFF
+#endif
+#if (G107PL >= G108PL) || (G107PL == 0)
+#define MG108_17PL ~(1 << 6)
+#else
+#define MG108_17PL 0xFFFF
+#endif
+#define MG108_18PL 0x007F
+#define MG108 (MG108_11PL & MG108_12PL & MG108_13PL & MG108_14PL & \
+ MG108_15PL & MG108_16PL & MG108_17PL & MG108_18PL)
+// End of MG108:
+
+//-------------------------------------------------------------------------------
+// Automatically generate PIEIER1 interrupt masks MG111 to MG118:
+//
+
+// Beginning of MG111:
+#if (G112PL >= G111PL) || (G112PL == 0)
+#define MG111_12PL ~(1 << 1)
+#else
+#define MG111_12PL 0xFFFF
+#endif
+#if (G113PL >= G111PL) || (G113PL == 0)
+#define MG111_13PL ~(1 << 2)
+#else
+#define MG111_13PL 0xFFFF
+#endif
+#if (G114PL >= G111PL) || (G114PL == 0)
+#define MG111_14PL ~(1 << 3)
+#else
+#define MG111_14PL 0xFFFF
+#endif
+#if (G115PL >= G111PL) || (G115PL == 0)
+#define MG111_15PL ~(1 << 4)
+#else
+#define MG111_15PL 0xFFFF
+#endif
+#if (G116PL >= G111PL) || (G116PL == 0)
+#define MG111_16PL ~(1 << 5)
+#else
+#define MG111_16PL 0xFFFF
+#endif
+#if (G117PL >= G111PL) || (G117PL == 0)
+#define MG111_17PL ~(1 << 6)
+#else
+#define MG111_17PL 0xFFFF
+#endif
+#if (G118PL >= G111PL) || (G118PL == 0)
+#define MG111_18PL ~(1 << 7)
+#else
+#define MG111_18PL 0xFFFF
+#endif
+#define MG111_11PL 0x00FE
+#define MG111 (MG111_11PL & MG111_12PL & MG111_13PL & MG111_14PL & \
+ MG111_15PL & MG111_16PL & MG111_17PL & MG111_18PL)
+// End of MG111:
+
+// Beginning of MG112:
+#if (G111PL >= G112PL) || (G111PL == 0)
+#define MG112_11PL ~(1)
+#else
+#define MG112_11PL 0xFFFF
+#endif
+#if (G113PL >= G112PL) || (G113PL == 0)
+#define MG112_13PL ~(1 << 2)
+#else
+#define MG112_13PL 0xFFFF
+#endif
+#if (G114PL >= G112PL) || (G114PL == 0)
+#define MG112_14PL ~(1 << 3)
+#else
+#define MG112_14PL 0xFFFF
+#endif
+#if (G115PL >= G112PL) || (G115PL == 0)
+#define MG112_15PL ~(1 << 4)
+#else
+#define MG112_15PL 0xFFFF
+#endif
+#if (G116PL >= G112PL) || (G116PL == 0)
+#define MG112_16PL ~(1 << 5)
+#else
+#define MG112_16PL 0xFFFF
+#endif
+#if (G117PL >= G112PL) || (G117PL == 0)
+#define MG112_17PL ~(1 << 6)
+#else
+#define MG112_17PL 0xFFFF
+#endif
+#if (G118PL >= G112PL) || (G118PL == 0)
+#define MG112_18PL ~(1 << 7)
+#else
+#define MG112_18PL 0xFFFF
+#endif
+#define MG112_12PL 0x00FD
+#define MG112 (MG112_11PL & MG112_12PL & MG112_13PL & MG112_14PL & \
+ MG112_15PL & MG112_16PL & MG112_17PL & MG112_18PL)
+// End of MG112:
+
+// Beginning of MG113:
+#if (G111PL >= G113PL) || (G111PL == 0)
+#define MG113_11PL ~(1)
+#else
+#define MG113_11PL 0xFFFF
+#endif
+#if (G112PL >= G113PL) || (G112PL == 0)
+#define MG113_12PL ~(1 << 1)
+#else
+#define MG113_12PL 0xFFFF
+#endif
+#if (G114PL >= G113PL) || (G114PL == 0)
+#define MG113_14PL ~(1 << 3)
+#else
+#define MG113_14PL 0xFFFF
+#endif
+#if (G115PL >= G113PL) || (G115PL == 0)
+#define MG113_15PL ~(1 << 4)
+#else
+#define MG113_15PL 0xFFFF
+#endif
+#if (G116PL >= G113PL) || (G116PL == 0)
+#define MG113_16PL ~(1 << 5)
+#else
+#define MG113_16PL 0xFFFF
+#endif
+#if (G117PL >= G113PL) || (G117PL == 0)
+#define MG113_17PL ~(1 << 6)
+#else
+#define MG113_17PL 0xFFFF
+#endif
+#if (G118PL >= G113PL) || (G118PL == 0)
+#define MG113_18PL ~(1 << 7)
+#else
+#define MG113_18PL 0xFFFF
+#endif
+#define MG113_13PL 0x00FB
+#define MG113 (MG113_11PL & MG113_12PL & MG113_13PL & MG113_14PL & \
+ MG113_15PL & MG113_16PL & MG113_17PL & MG113_18PL)
+// End of MG113:
+
+// Beginning of MG114:
+#if (G111PL >= G114PL) || (G111PL == 0)
+#define MG114_11PL ~(1)
+#else
+#define MG114_11PL 0xFFFF
+#endif
+#if (G112PL >= G114PL) || (G112PL == 0)
+#define MG114_12PL ~(1 << 1)
+#else
+#define MG114_12PL 0xFFFF
+#endif
+#if (G113PL >= G114PL) || (G113PL == 0)
+#define MG114_13PL ~(1 << 2)
+#else
+#define MG114_13PL 0xFFFF
+#endif
+#if (G115PL >= G114PL) || (G115PL == 0)
+#define MG114_15PL ~(1 << 4)
+#else
+#define MG114_15PL 0xFFFF
+#endif
+#if (G116PL >= G114PL) || (G116PL == 0)
+#define MG114_16PL ~(1 << 5)
+#else
+#define MG114_16PL 0xFFFF
+#endif
+#if (G117PL >= G114PL) || (G117PL == 0)
+#define MG114_17PL ~(1 << 6)
+#else
+#define MG114_17PL 0xFFFF
+#endif
+#if (G118PL >= G114PL) || (G118PL == 0)
+#define MG114_18PL ~(1 << 7)
+#else
+#define MG114_18PL 0xFFFF
+#endif
+#define MG114_14PL 0x00F7
+#define MG114 (MG114_11PL & MG114_12PL & MG114_13PL & MG114_14PL & \
+ MG114_15PL & MG114_16PL & MG114_17PL & MG114_18PL)
+// End of MG114:
+
+// Beginning of MG115:
+#if (G111PL >= G115PL) || (G111PL == 0)
+#define MG115_11PL ~(1)
+#else
+#define MG115_11PL 0xFFFF
+#endif
+#if (G112PL >= G115PL) || (G112PL == 0)
+#define MG115_12PL ~(1 << 1)
+#else
+#define MG115_12PL 0xFFFF
+#endif
+#if (G113PL >= G115PL) || (G113PL == 0)
+#define MG115_13PL ~(1 << 2)
+#else
+#define MG115_13PL 0xFFFF
+#endif
+#if (G114PL >= G115PL) || (G114PL == 0)
+#define MG115_14PL ~(1 << 3)
+#else
+#define MG115_14PL 0xFFFF
+#endif
+#if (G116PL >= G115PL) || (G116PL == 0)
+#define MG115_16PL ~(1 << 5)
+#else
+#define MG115_16PL 0xFFFF
+#endif
+#if (G117PL >= G115PL) || (G117PL == 0)
+#define MG115_17PL ~(1 << 6)
+#else
+#define MG115_17PL 0xFFFF
+#endif
+#if (G118PL >= G115PL) || (G118PL == 0)
+#define MG115_18PL ~(1 << 7)
+#else
+#define MG115_18PL 0xFFFF
+#endif
+#define MG115_15PL 0x00EF
+#define MG115 (MG115_11PL & MG115_12PL & MG115_13PL & MG115_14PL & \
+ MG115_15PL & MG115_16PL & MG115_17PL & MG115_18PL)
+// End of MG115:
+
+// Beginning of MG116:
+#if (G111PL >= G116PL) || (G111PL == 0)
+#define MG116_11PL ~(1)
+#else
+#define MG116_11PL 0xFFFF
+#endif
+#if (G112PL >= G116PL) || (G112PL == 0)
+#define MG116_12PL ~(1 << 1)
+#else
+#define MG116_12PL 0xFFFF
+#endif
+#if (G113PL >= G116PL) || (G113PL == 0)
+#define MG116_13PL ~(1 << 2)
+#else
+#define MG116_13PL 0xFFFF
+#endif
+#if (G114PL >= G116PL) || (G114PL == 0)
+#define MG116_14PL ~(1 << 3)
+#else
+#define MG116_14PL 0xFFFF
+#endif
+#if (G115PL >= G116PL) || (G115PL == 0)
+#define MG116_15PL ~(1 << 4)
+#else
+#define MG116_15PL 0xFFFF
+#endif
+#if (G117PL >= G116PL) || (G117PL == 0)
+#define MG116_17PL ~(1 << 6)
+#else
+#define MG116_17PL 0xFFFF
+#endif
+#if (G118PL >= G116PL) || (G118PL == 0)
+#define MG116_18PL ~(1 << 7)
+#else
+#define MG116_18PL 0xFFFF
+#endif
+#define MG116_16PL 0x00DF
+#define MG116 (MG116_11PL & MG116_12PL & MG116_13PL & MG116_14PL & \
+ MG116_15PL & MG116_16PL & MG116_17PL & MG116_18PL)
+// End of MG116:
+
+// Beginning of MG117:
+#if (G111PL >= G117PL) || (G111PL == 0)
+#define MG117_11PL ~(1)
+#else
+#define MG117_11PL 0xFFFF
+#endif
+#if (G112PL >= G117PL) || (G112PL == 0)
+#define MG117_12PL ~(1 << 1)
+#else
+#define MG117_12PL 0xFFFF
+#endif
+#if (G113PL >= G117PL) || (G113PL == 0)
+#define MG117_13PL ~(1 << 2)
+#else
+#define MG117_13PL 0xFFFF
+#endif
+#if (G114PL >= G117PL) || (G114PL == 0)
+#define MG117_14PL ~(1 << 3)
+#else
+#define MG117_14PL 0xFFFF
+#endif
+#if (G115PL >= G117PL) || (G115PL == 0)
+#define MG117_15PL ~(1 << 4)
+#else
+#define MG117_15PL 0xFFFF
+#endif
+#if (G116PL >= G117PL) || (G116PL == 0)
+#define MG117_16PL ~(1 << 5)
+#else
+#define MG117_16PL 0xFFFF
+#endif
+#if (G118PL >= G117PL) || (G118PL == 0)
+#define MG117_18PL ~(1 << 7)
+#else
+#define MG117_18PL 0xFFFF
+#endif
+#define MG117_17PL 0x00BF
+#define MG117 (MG117_11PL & MG117_12PL & MG117_13PL & MG117_14PL & \
+ MG117_15PL & MG117_16PL & MG117_17PL & MG117_18PL)
+// End of MG117:
+
+// Beginning of MG118:
+#if (G111PL >= G118PL) || (G111PL == 0)
+#define MG118_11PL ~(1)
+#else
+#define MG118_11PL 0xFFFF
+#endif
+#if (G112PL >= G118PL) || (G112PL == 0)
+#define MG118_12PL ~(1 << 1)
+#else
+#define MG118_12PL 0xFFFF
+#endif
+#if (G113PL >= G118PL) || (G113PL == 0)
+#define MG118_13PL ~(1 << 2)
+#else
+#define MG118_13PL 0xFFFF
+#endif
+#if (G114PL >= G118PL) || (G114PL == 0)
+#define MG118_14PL ~(1 << 3)
+#else
+#define MG118_14PL 0xFFFF
+#endif
+#if (G115PL >= G118PL) || (G115PL == 0)
+#define MG118_15PL ~(1 << 4)
+#else
+#define MG118_15PL 0xFFFF
+#endif
+#if (G116PL >= G118PL) || (G116PL == 0)
+#define MG118_16PL ~(1 << 5)
+#else
+#define MG118_16PL 0xFFFF
+#endif
+#if (G117PL >= G118PL) || (G117PL == 0)
+#define MG118_17PL ~(1 << 6)
+#else
+#define MG118_17PL 0xFFFF
+#endif
+#define MG118_18PL 0x007F
+#define MG118 (MG118_11PL & MG118_12PL & MG118_13PL & MG118_14PL & \
+ MG118_15PL & MG118_16PL & MG118_17PL & MG118_18PL)
+// End of MG118:
+
+//-------------------------------------------------------------------------------
+// Automatically generate PIEIER1 interrupt masks MG121 to MG128:
+//
+
+// Beginning of MG121:
+#if (G122PL >= G121PL) || (G122PL == 0)
+#define MG121_12PL ~(1 << 1)
+#else
+#define MG121_12PL 0xFFFF
+#endif
+#if (G123PL >= G121PL) || (G123PL == 0)
+#define MG121_13PL ~(1 << 2)
+#else
+#define MG121_13PL 0xFFFF
+#endif
+#if (G124PL >= G121PL) || (G124PL == 0)
+#define MG121_14PL ~(1 << 3)
+#else
+#define MG121_14PL 0xFFFF
+#endif
+#if (G125PL >= G121PL) || (G125PL == 0)
+#define MG121_15PL ~(1 << 4)
+#else
+#define MG121_15PL 0xFFFF
+#endif
+#if (G126PL >= G121PL) || (G126PL == 0)
+#define MG121_16PL ~(1 << 5)
+#else
+#define MG121_16PL 0xFFFF
+#endif
+#if (G127PL >= G121PL) || (G127PL == 0)
+#define MG121_17PL ~(1 << 6)
+#else
+#define MG121_17PL 0xFFFF
+#endif
+#if (G128PL >= G121PL) || (G128PL == 0)
+#define MG121_18PL ~(1 << 7)
+#else
+#define MG121_18PL 0xFFFF
+#endif
+#define MG121_11PL 0x00FE
+#define MG121 (MG121_11PL & MG121_12PL & MG121_13PL & MG121_14PL & \
+ MG121_15PL & MG121_16PL & MG121_17PL & MG121_18PL)
+// End of MG121:
+
+// Beginning of MG121:
+#if (G121PL >= G122PL) || (G121PL == 0)
+#define MG122_11PL ~(1)
+#else
+#define MG122_11PL 0xFFFF
+#endif
+#if (G123PL >= G122PL) || (G123PL == 0)
+#define MG122_13PL ~(1 << 2)
+#else
+#define MG122_13PL 0xFFFF
+#endif
+#if (G124PL >= G122PL) || (G124PL == 0)
+#define MG122_14PL ~(1 << 3)
+#else
+#define MG122_14PL 0xFFFF
+#endif
+#if (G125PL >= G122PL) || (G125PL == 0)
+#define MG122_15PL ~(1 << 4)
+#else
+#define MG122_15PL 0xFFFF
+#endif
+#if (G126PL >= G122PL) || (G126PL == 0)
+#define MG122_16PL ~(1 << 5)
+#else
+#define MG122_16PL 0xFFFF
+#endif
+#if (G127PL >= G122PL) || (G127PL == 0)
+#define MG122_17PL ~(1 << 6)
+#else
+#define MG122_17PL 0xFFFF
+#endif
+#if (G128PL >= G122PL) || (G128PL == 0)
+#define MG122_18PL ~(1 << 7)
+#else
+#define MG122_18PL 0xFFFF
+#endif
+#define MG122_12PL 0x00FD
+#define MG122 (MG122_11PL & MG122_12PL & MG122_13PL & MG122_14PL & \
+ MG122_15PL & MG122_16PL & MG122_17PL & MG122_18PL)
+// End of MG122:
+
+// Beginning of MG123:
+#if (G121PL >= G123PL) || (G121PL == 0)
+#define MG123_11PL ~(1)
+#else
+#define MG123_11PL 0xFFFF
+#endif
+#if (G122PL >= G123PL) || (G122PL == 0)
+#define MG123_12PL ~(1 << 1)
+#else
+#define MG123_12PL 0xFFFF
+#endif
+#if (G124PL >= G123PL) || (G124PL == 0)
+#define MG123_14PL ~(1 << 3)
+#else
+#define MG123_14PL 0xFFFF
+#endif
+#if (G125PL >= G123PL) || (G125PL == 0)
+#define MG123_15PL ~(1 << 4)
+#else
+#define MG123_15PL 0xFFFF
+#endif
+#if (G126PL >= G123PL) || (G126PL == 0)
+#define MG123_16PL ~(1 << 5)
+#else
+#define MG123_16PL 0xFFFF
+#endif
+#if (G127PL >= G123PL) || (G127PL == 0)
+#define MG123_17PL ~(1 << 6)
+#else
+#define MG123_17PL 0xFFFF
+#endif
+#if (G128PL >= G123PL) || (G128PL == 0)
+#define MG123_18PL ~(1 << 7)
+#else
+#define MG123_18PL 0xFFFF
+#endif
+#define MG123_13PL 0x00FB
+#define MG123 (MG123_11PL & MG123_12PL & MG123_13PL & MG123_14PL & \
+ MG123_15PL & MG123_16PL & MG123_17PL & MG123_18PL)
+// End of MG123:
+
+// Beginning of MG124:
+#if (G121PL >= G124PL) || (G121PL == 0)
+#define MG124_11PL ~(1)
+#else
+#define MG124_11PL 0xFFFF
+#endif
+#if (G122PL >= G124PL) || (G122PL == 0)
+#define MG124_12PL ~(1 << 1)
+#else
+#define MG124_12PL 0xFFFF
+#endif
+#if (G123PL >= G124PL) || (G123PL == 0)
+#define MG124_13PL ~(1 << 2)
+#else
+#define MG124_13PL 0xFFFF
+#endif
+#if (G125PL >= G124PL) || (G125PL == 0)
+#define MG124_15PL ~(1 << 4)
+#else
+#define MG124_15PL 0xFFFF
+#endif
+#if (G126PL >= G124PL) || (G126PL == 0)
+#define MG124_16PL ~(1 << 5)
+#else
+#define MG124_16PL 0xFFFF
+#endif
+#if (G127PL >= G124PL) || (G127PL == 0)
+#define MG124_17PL ~(1 << 6)
+#else
+#define MG124_17PL 0xFFFF
+#endif
+#if (G128PL >= G124PL) || (G128PL == 0)
+#define MG124_18PL ~(1 << 7)
+#else
+#define MG124_18PL 0xFFFF
+#endif
+#define MG124_14PL 0x00F7
+#define MG124 (MG124_11PL & MG124_12PL & MG124_13PL & MG124_14PL & \
+ MG124_15PL & MG124_16PL & MG124_17PL & MG124_18PL)
+// End of MG124:
+
+// Beginning of MG125:
+#if (G121PL >= G125PL) || (G121PL == 0)
+#define MG125_11PL ~(1)
+#else
+#define MG125_11PL 0xFFFF
+#endif
+#if (G122PL >= G125PL) || (G122PL == 0)
+#define MG125_12PL ~(1 << 1)
+#else
+#define MG125_12PL 0xFFFF
+#endif
+#if (G123PL >= G125PL) || (G123PL == 0)
+#define MG125_13PL ~(1 << 2)
+#else
+#define MG125_13PL 0xFFFF
+#endif
+#if (G124PL >= G125PL) || (G124PL == 0)
+#define MG125_14PL ~(1 << 3)
+#else
+#define MG125_14PL 0xFFFF
+#endif
+#if (G126PL >= G125PL) || (G126PL == 0)
+#define MG125_16PL ~(1 << 5)
+#else
+#define MG125_16PL 0xFFFF
+#endif
+#if (G127PL >= G125PL) || (G127PL == 0)
+#define MG125_17PL ~(1 << 6)
+#else
+#define MG125_17PL 0xFFFF
+#endif
+#if (G128PL >= G125PL) || (G128PL == 0)
+#define MG125_18PL ~(1 << 7)
+#else
+#define MG125_18PL 0xFFFF
+#endif
+#define MG125_15PL 0x00EF
+#define MG125 (MG125_11PL & MG125_12PL & MG125_13PL & MG125_14PL & \
+ MG125_15PL & MG125_16PL & MG125_17PL & MG125_18PL)
+// End of MG125:
+
+// Beginning of MG126:
+#if (G121PL >= G126PL) || (G121PL == 0)
+#define MG126_11PL ~(1)
+#else
+#define MG126_11PL 0xFFFF
+#endif
+#if (G122PL >= G126PL) || (G122PL == 0)
+#define MG126_12PL ~(1 << 1)
+#else
+#define MG126_12PL 0xFFFF
+#endif
+#if (G123PL >= G126PL) || (G123PL == 0)
+#define MG126_13PL ~(1 << 2)
+#else
+#define MG126_13PL 0xFFFF
+#endif
+#if (G124PL >= G126PL) || (G124PL == 0)
+#define MG126_14PL ~(1 << 3)
+#else
+#define MG126_14PL 0xFFFF
+#endif
+#if (G125PL >= G126PL) || (G125PL == 0)
+#define MG126_15PL ~(1 << 4)
+#else
+#define MG126_15PL 0xFFFF
+#endif
+#if (G127PL >= G126PL) || (G127PL == 0)
+#define MG126_17PL ~(1 << 6)
+#else
+#define MG126_17PL 0xFFFF
+#endif
+#if (G128PL >= G126PL) || (G128PL == 0)
+#define MG126_18PL ~(1 << 7)
+#else
+#define MG126_18PL 0xFFFF
+#endif
+#define MG126_16PL 0x00DF
+#define MG126 (MG126_11PL & MG126_12PL & MG126_13PL & MG126_14PL & \
+ MG126_15PL & MG126_16PL & MG126_17PL & MG126_18PL)
+// End of MG126:
+
+// Beginning of MG127:
+#if (G121PL >= G127PL) || (G121PL == 0)
+#define MG127_11PL ~(1)
+#else
+#define MG127_11PL 0xFFFF
+#endif
+#if (G122PL >= G127PL) || (G122PL == 0)
+#define MG127_12PL ~(1 << 1)
+#else
+#define MG127_12PL 0xFFFF
+#endif
+#if (G123PL >= G127PL) || (G123PL == 0)
+#define MG127_13PL ~(1 << 2)
+#else
+#define MG127_13PL 0xFFFF
+#endif
+#if (G124PL >= G127PL) || (G124PL == 0)
+#define MG127_14PL ~(1 << 3)
+#else
+#define MG127_14PL 0xFFFF
+#endif
+#if (G125PL >= G127PL) || (G125PL == 0)
+#define MG127_15PL ~(1 << 4)
+#else
+#define MG127_15PL 0xFFFF
+#endif
+#if (G126PL >= G127PL) || (G126PL == 0)
+#define MG127_16PL ~(1 << 5)
+#else
+#define MG127_16PL 0xFFFF
+#endif
+#if (G128PL >= G127PL) || (G128PL == 0)
+#define MG127_18PL ~(1 << 7)
+#else
+#define MG127_18PL 0xFFFF
+#endif
+#define MG127_17PL 0x00BF
+#define MG127 (MG127_11PL & MG127_12PL & MG127_13PL & MG127_14PL & \
+ MG127_15PL & MG127_16PL & MG127_17PL & MG127_18PL)
+// End of MG127:
+
+// Beginning of MG128:
+#if (G121PL >= G128PL) || (G121PL == 0)
+#define MG128_11PL ~(1)
+#else
+#define MG128_11PL 0xFFFF
+#endif
+#if (G122PL >= G128PL) || (G122PL == 0)
+#define MG128_12PL ~(1 << 1)
+#else
+#define MG128_12PL 0xFFFF
+#endif
+#if (G123PL >= G128PL) || (G123PL == 0)
+#define MG128_13PL ~(1 << 2)
+#else
+#define MG128_13PL 0xFFFF
+#endif
+#if (G124PL >= G128PL) || (G124PL == 0)
+#define MG128_14PL ~(1 << 3)
+#else
+#define MG128_14PL 0xFFFF
+#endif
+#if (G125PL >= G128PL) || (G125PL == 0)
+#define MG128_15PL ~(1 << 4)
+#else
+#define MG128_15PL 0xFFFF
+#endif
+#if (G126PL >= G128PL) || (G126PL == 0)
+#define MG128_16PL ~(1 << 5)
+#else
+#define MG128_16PL 0xFFFF
+#endif
+#if (G127PL >= G128PL) || (G127PL == 0)
+#define MG128_17PL ~(1 << 6)
+#else
+#define MG128_17PL 0xFFFF
+#endif
+#define MG128_18PL 0x007F
+#define MG128 (MG128_11PL & MG128_12PL & MG128_13PL & MG128_14PL & \
+ MG128_15PL & MG128_16PL & MG128_17PL & MG128_18PL)
+// End of MG128:
+
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // eof
+
+//===========================================================================
+// No more.
+//===========================================================================
diff --git a/v120/DSP2833x_common/source/DSP2833x_PieCtrl.c b/v120/DSP2833x_common/source/DSP2833x_PieCtrl.c
new file mode 100644
index 0000000..f1eafe3
--- /dev/null
+++ b/v120/DSP2833x_common/source/DSP2833x_PieCtrl.c
@@ -0,0 +1,83 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006 13:46:35 $
+//###########################################################################
+//
+// FILE: DSP2833x_PieCtrl.c
+//
+// TITLE: DSP2833x Device PIE Control Register Initialization Functions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
+
+//---------------------------------------------------------------------------
+// InitPieCtrl:
+//---------------------------------------------------------------------------
+// This function initializes the PIE control registers to a known state.
+//
+void InitPieCtrl(void)
+{
+ // Disable Interrupts at the CPU level:
+ DINT;
+
+ // Disable the PIE
+ PieCtrlRegs.PIECTRL.bit.ENPIE = 0;
+
+ // Clear all PIEIER registers:
+ PieCtrlRegs.PIEIER1.all = 0;
+ PieCtrlRegs.PIEIER2.all = 0;
+ PieCtrlRegs.PIEIER3.all = 0;
+ PieCtrlRegs.PIEIER4.all = 0;
+ PieCtrlRegs.PIEIER5.all = 0;
+ PieCtrlRegs.PIEIER6.all = 0;
+ PieCtrlRegs.PIEIER7.all = 0;
+ PieCtrlRegs.PIEIER8.all = 0;
+ PieCtrlRegs.PIEIER9.all = 0;
+ PieCtrlRegs.PIEIER10.all = 0;
+ PieCtrlRegs.PIEIER11.all = 0;
+ PieCtrlRegs.PIEIER12.all = 0;
+
+ // Clear all PIEIFR registers:
+ PieCtrlRegs.PIEIFR1.all = 0;
+ PieCtrlRegs.PIEIFR2.all = 0;
+ PieCtrlRegs.PIEIFR3.all = 0;
+ PieCtrlRegs.PIEIFR4.all = 0;
+ PieCtrlRegs.PIEIFR5.all = 0;
+ PieCtrlRegs.PIEIFR6.all = 0;
+ PieCtrlRegs.PIEIFR7.all = 0;
+ PieCtrlRegs.PIEIFR8.all = 0;
+ PieCtrlRegs.PIEIFR9.all = 0;
+ PieCtrlRegs.PIEIFR10.all = 0;
+ PieCtrlRegs.PIEIFR11.all = 0;
+ PieCtrlRegs.PIEIFR12.all = 0;
+
+
+}
+
+//---------------------------------------------------------------------------
+// EnableInterrupts:
+//---------------------------------------------------------------------------
+// This function enables the PIE module and CPU interrupts
+//
+void EnableInterrupts()
+{
+
+ // Enable the PIE
+ PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
+
+ // Enables PIE to drive a pulse into the CPU
+ PieCtrlRegs.PIEACK.all = 0xFFFF;
+
+ // Enable Interrupts at the CPU level
+ EINT;
+
+}
+
+
+//===========================================================================
+// End of file.
+//===========================================================================
diff --git a/v120/DSP2833x_common/source/DSP2833x_PieVect.c b/v120/DSP2833x_common/source/DSP2833x_PieVect.c
new file mode 100644
index 0000000..d163c54
--- /dev/null
+++ b/v120/DSP2833x_common/source/DSP2833x_PieVect.c
@@ -0,0 +1,204 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006 13:46:38 $
+//###########################################################################
+//
+// FILE: DSP2833x_PieVect.c
+//
+// TITLE: DSP2833x Devices PIE Vector Table Initialization Functions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
+
+const struct PIE_VECT_TABLE PieVectTableInit = {
+
+ PIE_RESERVED, // 0 Reserved space
+ PIE_RESERVED, // 1 Reserved space
+ PIE_RESERVED, // 2 Reserved space
+ PIE_RESERVED, // 3 Reserved space
+ PIE_RESERVED, // 4 Reserved space
+ PIE_RESERVED, // 5 Reserved space
+ PIE_RESERVED, // 6 Reserved space
+ PIE_RESERVED, // 7 Reserved space
+ PIE_RESERVED, // 8 Reserved space
+ PIE_RESERVED, // 9 Reserved space
+ PIE_RESERVED, // 10 Reserved space
+ PIE_RESERVED, // 11 Reserved space
+ PIE_RESERVED, // 12 Reserved space
+
+
+// Non-Peripheral Interrupts
+ INT13_ISR, // XINT13 or CPU-Timer 1
+ INT14_ISR, // CPU-Timer2
+ DATALOG_ISR, // Datalogging interrupt
+ RTOSINT_ISR, // RTOS interrupt
+ EMUINT_ISR, // Emulation interrupt
+ NMI_ISR, // Non-maskable interrupt
+ ILLEGAL_ISR, // Illegal operation TRAP
+ USER1_ISR, // User Defined trap 1
+ USER2_ISR, // User Defined trap 2
+ USER3_ISR, // User Defined trap 3
+ USER4_ISR, // User Defined trap 4
+ USER5_ISR, // User Defined trap 5
+ USER6_ISR, // User Defined trap 6
+ USER7_ISR, // User Defined trap 7
+ USER8_ISR, // User Defined trap 8
+ USER9_ISR, // User Defined trap 9
+ USER10_ISR, // User Defined trap 10
+ USER11_ISR, // User Defined trap 11
+ USER12_ISR, // User Defined trap 12
+
+// Group 1 PIE Vectors
+ SEQ1INT_ISR, // 1.1 ADC
+ SEQ2INT_ISR, // 1.2 ADC
+ rsvd_ISR, // 1.3
+ XINT1_ISR, // 1.4
+ XINT2_ISR, // 1.5
+ ADCINT_ISR, // 1.6 ADC
+ TINT0_ISR, // 1.7 Timer 0
+ WAKEINT_ISR, // 1.8 WD, Low Power
+
+// Group 2 PIE Vectors
+ EPWM1_TZINT_ISR, // 2.1 EPWM-1 Trip Zone
+ EPWM2_TZINT_ISR, // 2.2 EPWM-2 Trip Zone
+ EPWM3_TZINT_ISR, // 2.3 EPWM-3 Trip Zone
+ EPWM4_TZINT_ISR, // 2.4 EPWM-4 Trip Zone
+ EPWM5_TZINT_ISR, // 2.5 EPWM-5 Trip Zone
+ EPWM6_TZINT_ISR, // 2.6 EPWM-6 Trip Zone
+ rsvd_ISR, // 2.7
+ rsvd_ISR, // 2.8
+
+// Group 3 PIE Vectors
+ EPWM1_INT_ISR, // 3.1 EPWM-1 Interrupt
+ EPWM2_INT_ISR, // 3.2 EPWM-2 Interrupt
+ EPWM3_INT_ISR, // 3.3 EPWM-3 Interrupt
+ EPWM4_INT_ISR, // 3.4 EPWM-4 Interrupt
+ EPWM5_INT_ISR, // 3.5 EPWM-5 Interrupt
+ EPWM6_INT_ISR, // 3.6 EPWM-6 Interrupt
+ rsvd_ISR, // 3.7
+ rsvd_ISR, // 3.8
+
+// Group 4 PIE Vectors
+ ECAP1_INT_ISR, // 4.1 ECAP-1
+ ECAP2_INT_ISR, // 4.2 ECAP-2
+ ECAP3_INT_ISR, // 4.3 ECAP-3
+ ECAP4_INT_ISR, // 4.4 ECAP-4
+ ECAP5_INT_ISR, // 4.5 ECAP-5
+ ECAP6_INT_ISR, // 4.6 ECAP-6
+ rsvd_ISR, // 4.7
+ rsvd_ISR, // 4.8
+
+// Group 5 PIE Vectors
+ EQEP1_INT_ISR, // 5.1 EQEP-1
+ EQEP2_INT_ISR, // 5.2 EQEP-2
+ rsvd_ISR, // 5.3
+ rsvd_ISR, // 5.4
+ rsvd_ISR, // 5.5
+ rsvd_ISR, // 5.6
+ rsvd_ISR, // 5.7
+ rsvd_ISR, // 5.8
+
+
+// Group 6 PIE Vectors
+ SPIRXINTA_ISR, // 6.1 SPI-A
+ SPITXINTA_ISR, // 6.2 SPI-A
+ MRINTA_ISR, // 6.3 McBSP-A
+ MXINTA_ISR, // 6.4 McBSP-A
+ MRINTB_ISR, // 6.5 McBSP-B
+ MXINTB_ISR, // 6.6 McBSP-B
+ rsvd_ISR, // 6.7
+ rsvd_ISR, // 6.8
+
+
+// Group 7 PIE Vectors
+ DINTCH1_ISR, // 7.1 DMA channel 1
+ DINTCH2_ISR, // 7.2 DMA channel 2
+ DINTCH3_ISR, // 7.3 DMA channel 3
+ DINTCH4_ISR, // 7.4 DMA channel 4
+ DINTCH5_ISR, // 7.5 DMA channel 5
+ DINTCH6_ISR, // 7.6 DMA channel 6
+ rsvd_ISR, // 7.7
+ rsvd_ISR, // 7.8
+
+// Group 8 PIE Vectors
+ I2CINT1A_ISR, // 8.1 I2C
+ I2CINT2A_ISR, // 8.2 I2C
+ rsvd_ISR, // 8.3
+ rsvd_ISR, // 8.4
+ SCIRXINTC_ISR, // 8.5 SCI-C
+ SCITXINTC_ISR, // 8.6 SCI-C
+ rsvd_ISR, // 8.7
+ rsvd_ISR, // 8.8
+
+// Group 9 PIE Vectors
+ SCIRXINTA_ISR, // 9.1 SCI-A
+ SCITXINTA_ISR, // 9.2 SCI-A
+ SCIRXINTB_ISR, // 9.3 SCI-B
+ SCITXINTB_ISR, // 9.4 SCI-B
+ ECAN0INTA_ISR, // 9.5 eCAN-A
+ ECAN1INTA_ISR, // 9.6 eCAN-A
+ ECAN0INTB_ISR, // 9.7 eCAN-B
+ ECAN1INTB_ISR, // 9.8 eCAN-B
+
+// Group 10 PIE Vectors
+ rsvd_ISR, // 10.1
+ rsvd_ISR, // 10.2
+ rsvd_ISR, // 10.3
+ rsvd_ISR, // 10.4
+ rsvd_ISR, // 10.5
+ rsvd_ISR, // 10.6
+ rsvd_ISR, // 10.7
+ rsvd_ISR, // 10.8
+
+// Group 11 PIE Vectors
+ rsvd_ISR, // 11.1
+ rsvd_ISR, // 11.2
+ rsvd_ISR, // 11.3
+ rsvd_ISR, // 11.4
+ rsvd_ISR, // 11.5
+ rsvd_ISR, // 11.6
+ rsvd_ISR, // 11.7
+ rsvd_ISR, // 11.8
+
+// Group 12 PIE Vectors
+ XINT3_ISR, // 12.1
+ XINT4_ISR, // 12.2
+ XINT5_ISR, // 12.3
+ XINT6_ISR, // 12.4
+ XINT7_ISR, // 12.5
+ rsvd_ISR, // 12.6
+ LVF_ISR, // 12.7
+ LUF_ISR, // 12.8
+};
+
+
+//---------------------------------------------------------------------------
+// InitPieVectTable:
+//---------------------------------------------------------------------------
+// This function initializes the PIE vector table to a known state.
+// This function must be executed after boot time.
+//
+
+void InitPieVectTable(void)
+{
+ int16 i;
+ Uint32 *Source = (void *) &PieVectTableInit;
+ Uint32 *Dest = (void *) &PieVectTable;
+
+ EALLOW;
+ for(i=0; i < 128; i++)
+ *Dest++ = *Source++;
+ EDIS;
+
+ // Enable the PIE Vector Table
+ PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
+
+}
+
+//===========================================================================
+// End of file.
+//===========================================================================
diff --git a/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedDefaultIsr.c b/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedDefaultIsr.c
new file mode 100644
index 0000000..bf821e1
--- /dev/null
+++ b/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedDefaultIsr.c
@@ -0,0 +1,1863 @@
+// TI File $Revision: /main/5 $
+// Checkin $Date: January 14, 2008 11:28:12 $
+//###########################################################################
+//
+// FILE: DSP2833x_SWPrioritizedDefaultIsr.c
+//
+// TITLE: DSP2833x Device Default Software Prioritized Interrupt Service Routines.
+//
+//###########################################################################
+//
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+
+#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
+#include "DSP2833x_SWPrioritizedIsrLevels.h"
+
+
+// Connected to INT13 of CPU (use MINT13 mask):
+// Note CPU-Timer1 is reserved for TI use, however XINT13
+// ISR can be used by the user.
+#if (INT13PL != 0)
+interrupt void INT13_ISR(void) // INT13 or CPU-Timer1
+{
+ IER |= MINT13; // Set "global" priority
+ EINT;
+
+ // Insert ISR Code here
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+// Connected to INT14 of CPU (use MINT14 mask):
+#if (INT14PL != 0)
+interrupt void INT14_ISR(void) // CPU-Timer2
+{
+ IER |= MINT14; // Set "global" priority
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+// Connected to INT15 of CPU (use MINT15 mask):
+#if (INT15PL != 0)
+interrupt void DATALOG_ISR(void) // Datalogging interrupt
+{
+ IER |= MINT15; // Set "global" priority
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+// Connected to INT16 of CPU (use MINT16 mask):
+#if (INT16PL != 0)
+interrupt void RTOSINT_ISR(void) // RTOS interrupt
+{
+ IER |= MINT16; // Set "global" priority
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+// Connected to EMUINT of CPU (non-maskable):
+interrupt void EMUINT_ISR(void) // Emulation interrupt
+{
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+
+
+// Connected to NMI of CPU (non-maskable):
+interrupt void NMI_ISR(void) // Non-maskable interrupt
+{
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+
+interrupt void ILLEGAL_ISR(void) // Illegal operation TRAP
+{
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+
+
+interrupt void USER1_ISR(void) // User Defined trap 1
+{
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+
+interrupt void USER2_ISR(void) // User Defined trap 2
+{
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+
+interrupt void USER3_ISR(void) // User Defined trap 3
+{
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+
+interrupt void USER4_ISR(void) // User Defined trap 4
+{
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+
+interrupt void USER5_ISR(void) // User Defined trap 5
+{
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+
+interrupt void USER6_ISR(void) // User Defined trap 6
+{
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+
+interrupt void USER7_ISR(void) // User Defined trap 7
+{
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+
+interrupt void USER8_ISR(void) // User Defined trap 8
+{
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+
+interrupt void USER9_ISR(void) // User Defined trap 9
+{
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+
+interrupt void USER10_ISR(void) // User Defined trap 10
+{
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+
+interrupt void USER11_ISR(void) // User Defined trap 11
+{
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+
+interrupt void USER12_ISR(void) // User Defined trap 12
+{
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+
+
+// -----------------------------------------------------------
+// PIE Group 1 - MUXed into CPU INT1
+// -----------------------------------------------------------
+
+// Connected to PIEIER1_1 (use MINT1 and MG11 masks):
+#if (G11PL != 0)
+interrupt void SEQ1INT_ISR( void ) // ADC
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
+ IER |= M_INT1;
+ IER &= MINT1; // Set "global" priority
+ PieCtrlRegs.PIEIER1.all &= MG11; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER1.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER1_2 (use MINT1 and MG12 masks):
+#if (G12PL != 0)
+interrupt void SEQ2INT_ISR( void ) // ADC
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
+ IER |= M_INT1;
+ IER &= MINT1; // Set "global" priority
+ PieCtrlRegs.PIEIER1.all &= MG12; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+
+
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER1.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+
+// Connected to PIEIER1_4 (use MINT1 and MG14 masks):
+#if (G14PL != 0)
+interrupt void XINT1_ISR(void)
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
+ IER |= MINT1; // Set "global" priority
+ PieCtrlRegs.PIEIER1.all &= MG14; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER1.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+// Connected to PIEIER1_5 (use MINT1 and MG15 masks):
+#if (G15PL != 0)
+interrupt void XINT2_ISR(void)
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
+ IER |= MINT1; // Set "global" priority
+ PieCtrlRegs.PIEIER1.all &= MG15; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER1.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+
+// Connected to PIEIER1_6 (use MINT1 and MG16 masks):
+#if (G16PL != 0)
+interrupt void ADCINT_ISR(void) // ADC
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
+ IER |= M_INT1;
+ IER &= MINT1; // Set "global" priority
+ PieCtrlRegs.PIEIER1.all &= MG16; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER1.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER1_7 (use MINT1 and MG17 masks):
+#if (G17PL != 0)
+interrupt void TINT0_ISR(void) // CPU-Timer 0
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
+ IER |= M_INT1;
+ IER &= MINT1; // Set "global" priority
+ PieCtrlRegs.PIEIER1.all &= MG17; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER1.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+// Connected to PIEIER1_8 (use MINT1 and MG18 masks):
+#if (G18PL != 0)
+interrupt void WAKEINT_ISR(void) // WD/LPM
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
+ IER |= M_INT1;
+ IER &= MINT1; // Set "global" priority
+ PieCtrlRegs.PIEIER1.all &= MG18; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER1.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+
+// -----------------------------------------------------------
+// PIE Group 2 - MUXed into CPU INT2
+// -----------------------------------------------------------
+
+// Connected to PIEIER2_1 (use MINT2 and MG21 masks):
+#if (G21PL != 0)
+interrupt void EPWM1_TZINT_ISR(void) // ePWM1 Trip Zone
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
+ IER |= M_INT2;
+ IER &= MINT2; // Set "global" priority
+ PieCtrlRegs.PIEIER2.all &= MG21; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER2.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+// Connected to PIEIER2_2 (use MINT2 and MG22 masks):
+#if (G22PL != 0)
+interrupt void EPWM2_TZINT_ISR(void) // ePWM2 Trip Zone
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
+ IER |= M_INT2;
+ IER &= MINT2; // Set "global" priority
+ PieCtrlRegs.PIEIER2.all &= MG22; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER2.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+// Connected to PIEIER2_3 (use MINT2 and MG23 masks):
+#if (G23PL != 0)
+interrupt void EPWM3_TZINT_ISR(void) // ePWM3 Trip Zone
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
+ IER |= M_INT2;
+ IER &= MINT2; // Set "global" priority
+ PieCtrlRegs.PIEIER2.all &= MG23; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER2.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER2_4 (use MINT2 and MG24 masks):
+#if (G24PL != 0)
+interrupt void EPWM4_TZINT_ISR(void) // ePWM4 Trip Zone
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
+ IER |= M_INT2;
+ IER &= MINT2; // Set "global" priority
+ PieCtrlRegs.PIEIER2.all &= MG24; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER2.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER2_5 (use MINT2 and MG25 masks):
+#if (G25PL != 0)
+interrupt void EPWM5_TZINT_ISR(void) // ePWM5 Trip Zone
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
+ IER |= M_INT2;
+ IER &= MINT2; // Set "global" priority
+ PieCtrlRegs.PIEIER2.all &= MG25; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER2.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER2_6 (use MINT2 and MG26 masks):
+#if (G26PL != 0)
+interrupt void EPWM6_TZINT_ISR(void) // ePWM6 Trip Zone
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
+ IER |= M_INT2;
+ IER &= MINT2; // Set "global" priority
+ PieCtrlRegs.PIEIER2.all &= MG26; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER2.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+
+// -----------------------------------------------------------
+// PIE Group 3 - MUXed into CPU INT3
+// -----------------------------------------------------------
+
+
+// Connected to PIEIER3_1 (use MINT3 and MG31 masks):
+#if (G31PL != 0)
+interrupt void EPWM1_INT_ISR(void) // ePWM1 Interrupt
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
+ IER |= M_INT3;
+ IER &= MINT3; // Set "global" priority
+ PieCtrlRegs.PIEIER3.all &= MG31; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER3.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+// Connected to PIEIER3_2 (use MINT3 and MG32 masks):
+#if (G32PL != 0)
+interrupt void EPWM2_INT_ISR(void) // ePWM2 Interrupt
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
+ IER |= M_INT3;
+ IER &= MINT3; // Set "global" priority
+ PieCtrlRegs.PIEIER3.all &= MG32; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER3.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER3_3 (use MINT3 and MG33 masks):
+#if (G33PL != 0)
+interrupt void EPWM3_INT_ISR(void) // ePWM3 Interrupt
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
+ IER |= M_INT3;
+ IER &= MINT3; // Set "global" priority
+ PieCtrlRegs.PIEIER3.all &= MG33; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER3.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER3_4 (use MINT3 and MG34 masks):
+#if (G34PL != 0)
+interrupt void EPWM4_INT_ISR(void) // ePWM4 Interrupt
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
+ IER |= M_INT3;
+ IER &= MINT3; // Set "global" priority
+ PieCtrlRegs.PIEIER3.all &= MG34; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER3.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER3_5 (use MINT3 and MG35 masks):
+#if (G35PL != 0)
+interrupt void EPWM5_INT_ISR(void) // ePWM5 Interrupt
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
+ IER |= M_INT3;
+ IER &= MINT3; // Set "global" priority
+ PieCtrlRegs.PIEIER3.all &= MG35; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER3.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER3_6 (use MINT3 and MG36 masks):
+#if (G36PL != 0)
+interrupt void EPWM6_INT_ISR(void) // ePWM6 Interrupt
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
+ IER |= M_INT3;
+ IER &= MINT3; // Set "global" priority
+ PieCtrlRegs.PIEIER3.all &= MG36; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER3.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+
+// -----------------------------------------------------------
+// PIE Group 4 - MUXed into CPU INT4
+// -----------------------------------------------------------
+
+
+// Connected to PIEIER4_1 (use MINT4 and MG41 masks):
+#if (G41PL != 0)
+interrupt void ECAP1_INT_ISR(void) // eCAP1 Interrupt
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
+ IER |= M_INT4;
+ IER &= MINT4; // Set "global" priority
+ PieCtrlRegs.PIEIER4.all &= MG41; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER4.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER4_2 (use MINT4 and MG42 masks):
+#if (G42PL != 0)
+interrupt void ECAP2_INT_ISR(void) // eCAP2 Interrupt
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all;
+ IER |= M_INT4;
+ IER &= MINT4; // Set "global" priority
+ PieCtrlRegs.PIEIER4.all &= MG42; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER4.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER4_3 (use MINT4 and MG43 masks):
+#if (G43PL != 0)
+interrupt void ECAP3_INT_ISR(void) // eCAP3 Interrupt
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
+ IER |= M_INT4;
+ IER &= MINT4; // Set "global" priority
+ PieCtrlRegs.PIEIER4.all &= MG43; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER4.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER4_4 (use MINT4 and MG44 masks):
+#if (G44PL != 0)
+interrupt void ECAP4_INT_ISR(void) // eCAP4 Interrupt
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
+ IER |= M_INT4;
+ IER &= MINT4; // Set "global" priority
+ PieCtrlRegs.PIEIER4.all &= MG44; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER4.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER4_5 (use MINT4 and MG45 masks):
+#if (G45PL != 0)
+interrupt void ECAP5_INT_ISR(void) // eCAP5 Interrupt
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
+ IER |= M_INT4;
+ IER &= MINT4; // Set "global" priority
+ PieCtrlRegs.PIEIER4.all &= MG45; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER4.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER4_6 (use MINT4 and MG46 masks):
+#if (G46PL != 0)
+interrupt void ECAP6_INT_ISR(void) // eCAP6 Interrupt
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
+ IER |= M_INT4;
+ IER &= MINT4; // Set "global" priority
+ PieCtrlRegs.PIEIER4.all &= MG46; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER4.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+
+
+// -----------------------------------------------------------
+// PIE Group 5 - MUXed into CPU INT5
+// -----------------------------------------------------------
+
+// Connected to PIEIER5_1 (use MINT5 and MG51 masks):
+#if (G51PL != 0)
+interrupt void EQEP1_INT_ISR(void) // eQEP1 Interrupt
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all;
+ IER |= M_INT5;
+ IER &= MINT5; // Set "global" priority
+ PieCtrlRegs.PIEIER5.all &= MG51; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER5.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER5_2 (use MINT5 and MG52 masks):
+#if (G52PL != 0)
+interrupt void EQEP2_INT_ISR(void) // eQEP2 Interrupt
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all;
+ IER |= M_INT5;
+ IER &= MINT5; // Set "global" priority
+ PieCtrlRegs.PIEIER5.all &= MG52; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER5.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// -----------------------------------------------------------
+// PIE Group 6 - MUXed into CPU INT6
+// -----------------------------------------------------------
+
+// Connected to PIEIER6_1 (use MINT6 and MG61 masks):
+#if (G61PL != 0)
+interrupt void SPIRXINTA_ISR(void) // SPI-A
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
+ IER |= M_INT6;
+ IER &= MINT6; // Set "global" priority
+ PieCtrlRegs.PIEIER6.all &= MG61; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER6.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER6_2 (use MINT6 and MG62 masks):
+#if (G62PL != 0)
+interrupt void SPITXINTA_ISR(void) // SPI-A
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
+ IER |= M_INT6;
+ IER &= MINT6; // Set "global" priority
+ PieCtrlRegs.PIEIER6.all &= MG62; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER6.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+// Connected to PIEIER6_3 (use MINT6 and MG63 masks):
+#if (G63PL != 0)
+interrupt void MRINTB_ISR(void) // McBSP-B
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
+ IER |= M_INT6;
+ IER &= MINT6; // Set "global" priority
+ PieCtrlRegs.PIEIER6.all &= MG63; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER6.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER6_4 (use MINT6 and MG64 masks):
+#if (G64PL != 0)
+interrupt void MXINTB_ISR(void) // McBSP-B
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
+ IER |= M_INT6;
+ IER &= MINT6; // Set "global" priority
+ PieCtrlRegs.PIEIER6.all &= MG64; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER6.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+
+
+// Connected to PIEIER6_5 (use MINT6 and MG65 masks):
+#if (G65PL != 0)
+interrupt void MRINTA_ISR(void) // McBSP-A
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
+ IER |= M_INT6;
+ IER &= MINT6; // Set "global" priority
+ PieCtrlRegs.PIEIER6.all &= MG65; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER6.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER6_6 (use MINT6 and MG66 masks):
+#if (G66PL != 0)
+interrupt void MXINTA_ISR(void) // McBSP-A
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
+ IER |= M_INT6;
+ IER &= MINT6; // Set "global" priority
+ PieCtrlRegs.PIEIER6.all &= MG66; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER6.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+
+// -----------------------------------------------------------
+// PIE Group 7 - MUXed into CPU INT7
+// -----------------------------------------------------------
+
+// Connected to PIEIER7_1 (use MINT7 and MG71 masks):
+#if (G71PL != 0)
+interrupt void DINTCH1_ISR(void) // DMA
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
+ IER |= M_INT7;
+ IER &= MINT7; // Set "global" priority
+ PieCtrlRegs.PIEIER7.all &= MG71; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER7.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER7_2 (use MINT7 and MG72 masks):
+#if (G72PL != 0)
+interrupt void DINTCH2_ISR(void) // DMA
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
+ IER |= M_INT7;
+ IER &= MINT7; // Set "global" priority
+ PieCtrlRegs.PIEIER7.all &= MG72; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER7.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+// Connected to PIEIER7_3 (use MINT7 and MG73 masks):
+#if (G73PL != 0)
+interrupt void DINTCH3_ISR(void) // DMA
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
+ IER |= M_INT7;
+ IER &= MINT7; // Set "global" priority
+ PieCtrlRegs.PIEIER7.all &= MG73; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER7.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER7_4 (use MINT7 and MG74 masks):
+#if (G74PL != 0)
+interrupt void DINTCH4_ISR(void) // DMA
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
+ IER |= M_INT7;
+ IER &= MINT7; // Set "global" priority
+ PieCtrlRegs.PIEIER7.all &= MG74; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER7.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+
+
+// Connected to PIEIER7_5 (use MINT7 and MG75 masks):
+#if (G75PL != 0)
+interrupt void DINTCH5_ISR(void) // DMA
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
+ IER |= M_INT7;
+ IER &= MINT7; // Set "global" priority
+ PieCtrlRegs.PIEIER7.all &= MG75; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER7.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER7_6 (use MINT7 and MG76 masks):
+#if (G76PL != 0)
+interrupt void DINTCH6_ISR(void) // DMA
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
+ IER |= M_INT7;
+ IER &= MINT7; // Set "global" priority
+ PieCtrlRegs.PIEIER7.all &= MG76; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER7.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+
+// -----------------------------------------------------------
+// PIE Group 8 - MUXed into CPU INT8
+// -----------------------------------------------------------
+
+// Connected to PIEIER8_1 (use MINT8 and MG81 masks):
+#if (G81PL != 0)
+interrupt void I2CINT1A_ISR(void) // I2C-A
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all;
+ IER |= M_INT8;
+ IER &= MINT8; // Set "global" priority
+ PieCtrlRegs.PIEIER6.all &= MG81; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER8.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER8_2 (use MINT8 and MG82 masks):
+#if (G82PL != 0)
+interrupt void I2CINT2A_ISR(void) // I2C-A
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all;
+ IER |= M_INT8;
+ IER &= MINT8; // Set "global" priority
+ PieCtrlRegs.PIEIER8.all &= MG82; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER8.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER8_5 (use MINT8 and MG85 masks):
+#if (G85PL != 0)
+interrupt void SCIRXINTC_ISR(void) // SCI-C
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all;
+ IER |= M_INT8;
+ IER &= MINT8; // Set "global" priority
+ PieCtrlRegs.PIEIER6.all &= MG85; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER8.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER8_6 (use MINT8 and MG86 masks):
+#if (G82PL != 0)
+interrupt void SCITXINTC_ISR(void) // SCI-C
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all;
+ IER |= M_INT8;
+ IER &= MINT8; // Set "global" priority
+ PieCtrlRegs.PIEIER8.all &= MG86; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER8.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// -----------------------------------------------------------
+// PIE Group 9 - MUXed into CPU INT9
+// -----------------------------------------------------------
+
+// Connected to PIEIER9_1 (use MINT9 and MG91 masks):
+#if (G91PL != 0)
+interrupt void SCIRXINTA_ISR(void) // SCI-A
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
+ IER |= M_INT9;
+ IER &= MINT9; // Set "global" priority
+ PieCtrlRegs.PIEIER9.all &= MG91; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER9.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER9_2 (use MINT9 and MG92 masks):
+#if (G92PL != 0)
+interrupt void SCITXINTA_ISR(void) // SCI-A
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
+ IER |= M_INT9;
+ IER &= MINT9; // Set "global" priority
+ PieCtrlRegs.PIEIER9.all &= MG92; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER9.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+
+// Connected to PIEIER9_3 (use MINT9 and MG93 masks):
+#if (G93PL != 0)
+interrupt void SCIRXINTB_ISR(void) // SCI-B
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
+ IER |= M_INT9;
+ IER &= MINT9; // Set "global" priority
+ PieCtrlRegs.PIEIER9.all &= MG93; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER9.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER9_4 (use MINT9 and MG94 masks):
+#if (G94PL != 0)
+interrupt void SCITXINTB_ISR(void) // SCI-B
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
+ IER |= M_INT9;
+ IER &= MINT9; // Set "global" priority
+ PieCtrlRegs.PIEIER9.all &= MG94; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER9.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER9_5 (use MINT9 and MG95 masks):
+#if (G95PL != 0)
+interrupt void ECAN0INTA_ISR(void) // eCAN-A
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
+ IER |= M_INT9;
+ IER &= MINT9; // Set "global" priority
+ PieCtrlRegs.PIEIER9.all &= MG95; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER9.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER9_6 (use MINT9 and MG96 masks):
+#if (G96PL != 0)
+interrupt void ECAN1INTA_ISR(void) // eCAN-A
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
+ IER |= M_INT9;
+ IER &= MINT9; // Set "global" priority
+ PieCtrlRegs.PIEIER9.all &= MG96; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER9.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER9_7 (use MINT9 and MG97 masks):
+#if (G97PL != 0)
+interrupt void ECAN0INTB_ISR(void) // eCAN-B
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
+ IER |= M_INT9;
+ IER &= MINT9; // Set "global" priority
+ PieCtrlRegs.PIEIER9.all &= MG97; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER9.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER9_8 (use MINT9 and MG98 masks):
+#if (G98PL != 0)
+interrupt void ECAN1INTB_ISR(void) // eCAN-B
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
+ IER |= M_INT9;
+ IER &= MINT9; // Set "global" priority
+ PieCtrlRegs.PIEIER9.all &= MG98; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER9.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// -----------------------------------------------------------
+// PIE Group 10 - MUXed into CPU INT10
+// -----------------------------------------------------------
+// -----------------------------------------------------------
+// PIE Group 11 - MUXed into CPU INT11
+// -----------------------------------------------------------
+// -----------------------------------------------------------
+// PIE Group 12 - MUXed into CPU INT12
+// -----------------------------------------------------------
+
+// Connected to PIEIER9_1 (use MINT12 and MG121 masks):
+#if (G121PL != 0)
+interrupt void XINT3_ISR(void)
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
+ IER |= M_INT12;
+ IER &= MINT12; // Set "global" priority
+ PieCtrlRegs.PIEIER12.all &= MG121; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER12.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER12_2 (use MINT12 and MG122 masks):
+#if (G122PL != 0)
+interrupt void XINT4_ISR(void)
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
+ IER |= M_INT12;
+ IER &= MINT12; // Set "global" priority
+ PieCtrlRegs.PIEIER12.all &= MG122; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER12.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+
+// Connected to PIEIER12_3 (use MINT12 and MG123 masks):
+#if (G123PL != 0)
+interrupt void XINT5_ISR(void) // SCI-B
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
+ IER |= M_INT12;
+ IER &= MINT12; // Set "global" priority
+ PieCtrlRegs.PIEIER12.all &= MG123; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER12.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER12_4 (use MINT12 and MG124 masks):
+#if (G124PL != 0)
+interrupt void XINT6_ISR(void) // SCI-B
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
+ IER |= M_INT12;
+ IER &= MINT12; // Set "global" priority
+ PieCtrlRegs.PIEIER12.all &= MG124; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER12.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER12_5 (use MINT12 and MG125 masks):
+#if (G125PL != 0)
+interrupt void XINT7_ISR(void) // eCAN-A
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
+ IER |= M_INT12;
+ IER &= MINT12; // Set "global" priority
+ PieCtrlRegs.PIEIER12.all &= MG125; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER12.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER12_7 (use MINT12 and MG127 masks):
+#if (G127PL != 0)
+interrupt void LVF_ISR(void) // FPU
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
+ IER |= M_INT12;
+ IER &= MINT12; // Set "global" priority
+ PieCtrlRegs.PIEIER12.all &= MG127; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER12.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+// Connected to PIEIER12_8 (use MINT12 and MG128 masks):
+#if (G128PL != 0)
+interrupt void LUF_ISR(void) // FPU
+{
+ // Set interrupt priority:
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
+ IER |= M_INT12;
+ IER &= MINT12; // Set "global" priority
+ PieCtrlRegs.PIEIER12.all &= MG128; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ EINT;
+
+ // Insert ISR Code here.......
+
+ // Restore registers saved:
+ DINT;
+ PieCtrlRegs.PIEIER12.all = TempPIEIER;
+
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ asm (" ESTOP0");
+ for(;;);
+
+}
+#endif
+
+
+//---------------------------------------------------------------------------
+// Catch All Default ISRs:
+//
+
+interrupt void PIE_RESERVED(void) // Reserved space. For test.
+{
+ asm (" ESTOP0");
+ for(;;);
+}
+
+interrupt void INT_NOTUSED_ISR(void) // Reserved space. For test.
+{
+ asm (" ESTOP0");
+ for(;;);
+}
+
+interrupt void rsvd_ISR(void) // For test
+{
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//===========================================================================
+// No more.
+//===========================================================================
diff --git a/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedPieVect.c b/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedPieVect.c
new file mode 100644
index 0000000..99379ea
--- /dev/null
+++ b/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedPieVect.c
@@ -0,0 +1,511 @@
+// TI File $Revision: /main/2 $
+// Checkin $Date: April 4, 2007 14:25:31 $
+//###########################################################################
+//
+// FILE: DSP2833x_SWPiroritizedPieVect.c
+//
+// TITLE: DSP2833x Devices SW Prioritized PIE Vector Table Initialization.
+//
+//###########################################################################
+//
+// Original Source by A.T.
+//
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
+#include "DSP2833x_SWPrioritizedIsrLevels.h"
+
+const struct PIE_VECT_TABLE PieVectTableInit = {
+
+ PIE_RESERVED, // Reserved space
+ PIE_RESERVED, // reserved
+ PIE_RESERVED, // reserved
+ PIE_RESERVED, // reserved
+ PIE_RESERVED, // reserved
+ PIE_RESERVED, // reserved
+ PIE_RESERVED, // reserved
+ PIE_RESERVED, // reserved
+ PIE_RESERVED, // reserved
+ PIE_RESERVED, // reserved
+ PIE_RESERVED, // reserved
+ PIE_RESERVED, // reserved
+ PIE_RESERVED, // reserved
+
+// Non-Peripheral Interrupts:
+ #if (INT13PL != 0)
+ INT13_ISR, // XINT13
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (INT14PL != 0)
+ INT14_ISR, // CPU-Timer2
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (INT15PL != 0)
+ DATALOG_ISR, // Datalogging interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (INT16PL != 0)
+ RTOSINT_ISR, // RTOS interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ rsvd_ISR, // reserved interrupt
+ NMI_ISR, // Non-maskable interrupt
+ ILLEGAL_ISR, // Illegal operation TRAP
+ USER1_ISR, // User Defined trap 1
+ USER2_ISR, // User Defined trap 2
+ USER3_ISR, // User Defined trap 3
+ USER4_ISR, // User Defined trap 4
+ USER5_ISR, // User Defined trap 5
+ USER6_ISR, // User Defined trap 6
+ USER7_ISR, // User Defined trap 7
+ USER8_ISR, // User Defined trap 8
+ USER9_ISR, // User Defined trap 9
+ USER10_ISR, // User Defined trap 10
+ USER11_ISR, // User Defined trap 11
+ USER12_ISR, // User Defined trap 12
+
+// Group 1 PIE Vectors:
+ #if (G11PL != 0)
+ SEQ1INT_ISR, // ADC
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G12PL != 0)
+ SEQ2INT_ISR, // ADC
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ rsvd_ISR,
+
+ #if (G14PL != 0)
+ XINT1_ISR, // External
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G15PL != 0)
+ XINT2_ISR, // External
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G16PL != 0)
+ ADCINT_ISR, // ADC
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G17PL != 0)
+ TINT0_ISR, // Timer 0
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G18PL != 0)
+ WAKEINT_ISR, // WD & Low Power
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+// Group 2 PIE Vectors:
+ #if (G21PL != 0)
+ EPWM1_TZINT_ISR, // ePWM1 Trip Zone
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G22PL != 0)
+ EPWM2_TZINT_ISR, // ePWM2 Trip Zone
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G23PL != 0)
+ EPWM3_TZINT_ISR, // ePWM3 Trip Zone
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G24PL != 0)
+ EPWM4_TZINT_ISR, // ePWM4 Trip Zone
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G25PL != 0)
+ EPWM5_TZINT_ISR, // ePWM5 Trip Zone
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G26PL != 0)
+ EPWM6_TZINT_ISR, // ePWM6 Trip Zone
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ rsvd_ISR,
+ rsvd_ISR,
+
+// Group 3 PIE Vectors:
+ #if (G31PL != 0)
+ EPWM1_INT_ISR, // ePWM1 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G32PL != 0)
+ EPWM2_INT_ISR, // ePWM2 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G33PL != 0)
+ EPWM3_INT_ISR, // ePWM3 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G34PL != 0)
+ EPWM4_INT_ISR, // ePWM4 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G35PL != 0)
+ EPWM5_INT_ISR, // ePWM5 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G36PL != 0)
+ EPWM6_INT_ISR, // ePWM6 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ rsvd_ISR,
+ rsvd_ISR,
+
+// Group 4 PIE Vectors:
+ #if (G41PL != 0)
+ ECAP1_INT_ISR, // eCAP1 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G42PL != 0)
+ ECAP2_INT_ISR, // eCAP2 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G43PL != 0)
+ ECAP3_INT_ISR, // eCAP3 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G44PL != 0)
+ ECAP4_INT_ISR, // eCAP4 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G45PL != 0)
+ ECAP5_INT_ISR, // eCAP5 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G46PL != 0)
+ ECAP6_INT_ISR, // eCAP6 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ rsvd_ISR,
+ rsvd_ISR,
+
+// Group 5 PIE Vectors:
+ #if (G51PL != 0)
+ EQEP1_INT_ISR, // eQEP1 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G52PL != 0)
+ EQEP2_INT_ISR, // eQEP2 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+
+// Group 6 PIE Vectors:
+ #if (G61PL != 0)
+ SPIRXINTA_ISR, // SPI-A
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G62PL != 0)
+ SPITXINTA_ISR, // SPI-A
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G63PL != 0)
+ MRINTB_ISR, // McBSP-B
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G64PL != 0)
+ MXINTB_ISR, // McBSP-B
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G65PL != 0)
+ MRINTA_ISR, // McBSP-A
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G66PL != 0)
+ MXINTA_ISR, // McBSP-A
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ rsvd_ISR,
+ rsvd_ISR,
+
+// Group 7 PIE Vectors:
+ #if (G71PL != 0)
+ DINTCH1_ISR, // DMA-Channel 1 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G72PL != 0)
+ DINTCH2_ISR, // DMA-Channel 2 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G73PL != 0)
+ DINTCH3_ISR, // DMA-Channel 3 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G74PL != 0)
+ DINTCH4_ISR, // DMA-Channel 4 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G75PL != 0)
+ DINTCH5_ISR, // DMA-Channel 5 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G76PL != 0)
+ DINTCH6_ISR, // DMA-Channel 6 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ rsvd_ISR,
+ rsvd_ISR,
+
+// Group 8 PIE Vectors:
+ #if (G81PL != 0)
+ I2CINT1A_ISR, // I2C-A
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G82PL != 0)
+ I2CINT2A_ISR, // I2C-A
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ rsvd_ISR,
+ rsvd_ISR,
+
+ #if (G85PL != 0)
+ SCIRXINTC_ISR, // SCI-C
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G86PL != 0)
+ SCITXINTC_ISR, // SCI-C
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ rsvd_ISR,
+ rsvd_ISR,
+
+// Group 9 PIE Vectors:
+ #if (G91PL != 0)
+ SCIRXINTA_ISR, // SCI-A
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G92PL != 0)
+ SCITXINTA_ISR, // SCI-A
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G93PL != 0)
+ SCIRXINTB_ISR, // SCI-B
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G94PL != 0)
+ SCITXINTB_ISR, // SCI-B
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G95PL != 0)
+ ECAN0INTA_ISR, // eCAN-A
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G96PL != 0)
+ ECAN1INTA_ISR, // eCAN-A
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G97PL != 0)
+ ECAN0INTB_ISR, // eCAN-B
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G98PL != 0)
+ ECAN1INTB_ISR, // eCAN-B
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+// Group 10 PIE Vectors
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+
+// Group 11 PIE Vectors
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+
+// Group 12 PIE Vectors
+ #if (G121PL != 0)
+ XINT3_ISR, // External interrupt 3
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G122PL != 0)
+ XINT4_ISR, // External interrupt 4
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G123PL != 0)
+ XINT5_ISR, // External interrupt 5
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G124PL != 0)
+ XINT6_ISR, // External interrupt 6
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G125PL != 0)
+ XINT7_ISR, // External interrupt 7
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ rsvd_ISR,
+
+ #if (G127PL != 0)
+ LVF_ISR, // Latched overflow flag
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G128PL != 0)
+ LUF_ISR, // Latched underflow flag
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+};
+
+//---------------------------------------------------------------------------
+// InitPieVectTable:
+//---------------------------------------------------------------------------
+// This function initializes the PIE vector table to a known state.
+// This function must be executed after boot time.
+//
+
+void InitPieVectTable(void)
+{
+ int16 i;
+ Uint32 *Source = (void *) &PieVectTableInit;
+ Uint32 *Dest = (void *) &PieVectTable;
+
+ EALLOW;
+ for(i=0; i < 128; i++) {
+ *Dest++ = *Source++;
+ }
+ EDIS;
+}
+
+//===========================================================================
+// No more.
+//===========================================================================
diff --git a/v120/DSP2833x_common/source/DSP2833x_SysCtrl.c b/v120/DSP2833x_common/source/DSP2833x_SysCtrl.c
new file mode 100644
index 0000000..7d9ea10
--- /dev/null
+++ b/v120/DSP2833x_common/source/DSP2833x_SysCtrl.c
@@ -0,0 +1,415 @@
+// TI File $Revision: /main/7 $
+// Checkin $Date: September 20, 2007 13:30:31 $
+//###########################################################################
+//
+// FILE: DSP2833x_SysCtrl.c
+//
+// TITLE: DSP2833x Device System Control Initialization & Support Functions.
+//
+// DESCRIPTION:
+//
+// Example initialization of system resources.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+
+#include "DSP2833x_Device.h" // Headerfile Include File
+#include "DSP2833x_Examples.h" // Examples Include File
+
+//#include "RS485.h"
+//#include "message.h"
+
+// Functions that will be run from RAM need to be assigned to
+// a different section. This section will then be mapped to a load and
+// run address using the linker cmd file.
+
+#pragma CODE_SECTION(InitFlash, "ramfuncs");
+
+//---------------------------------------------------------------------------
+// InitSysCtrl:
+//---------------------------------------------------------------------------
+// This function initializes the System Control registers to a known state.
+// - Disables the watchdog
+// - Set the PLLCR for proper SYSCLKOUT frequency
+// - Set the pre-scaler for the high and low frequency peripheral clocks
+// - Enable the clocks to the peripherals
+
+long SYSCLKOUT, LSPCLK, HSPCLK;
+
+void InitSysCtrl(void)
+{
+
+ // Disable the watchdog
+ DisableDog();
+
+ // Initialize the PLL control: PLLCR and DIVSEL
+ // DSP28_PLLCR and DSP28_DIVSEL are defined in DSP2833x_Examples.h
+ InitPll(DSP28_PLLCR,DSP28_DIVSEL);
+
+ // Initialize the peripheral clocks
+ InitPeripheralClocks();
+}
+
+
+//---------------------------------------------------------------------------
+// Example: InitFlash:
+//---------------------------------------------------------------------------
+// This function initializes the Flash Control registers
+
+// CAUTION
+// This function MUST be executed out of RAM. Executing it
+// out of OTP/Flash will yield unpredictable results
+
+void InitFlash(void)
+{
+ EALLOW;
+ //Enable Flash Pipeline mode to improve performance
+ //of code executed from Flash.
+ FlashRegs.FOPT.bit.ENPIPE = 1;
+
+ // CAUTION
+ //Minimum waitstates required for the flash operating
+ //at a given CPU rate must be characterized by TI.
+ //Refer to the datasheet for the latest information.
+#if CPU_FRQ_150MHZ
+ //Set the Paged Waitstate for the Flash
+ FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5;
+
+ //Set the Random Waitstate for the Flash
+ FlashRegs.FBANKWAIT.bit.RANDWAIT = 5;
+
+ //Set the Waitstate for the OTP
+ FlashRegs.FOTPWAIT.bit.OTPWAIT = 8;
+#endif
+
+#if CPU_FRQ_100MHZ
+ //Set the Paged Waitstate for the Flash
+ FlashRegs.FBANKWAIT.bit.PAGEWAIT = 3;
+
+ //Set the Random Waitstate for the Flash
+ FlashRegs.FBANKWAIT.bit.RANDWAIT = 3;
+
+ //Set the Waitstate for the OTP
+ FlashRegs.FOTPWAIT.bit.OTPWAIT = 5;
+#endif
+ // CAUTION
+ //ONLY THE DEFAULT VALUE FOR THESE 2 REGISTERS SHOULD BE USED
+ FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF;
+ FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF;
+ EDIS;
+
+ //Force a pipeline flush to ensure that the write to
+ //the last register configured occurs before returning.
+
+ asm(" RPT #7 || NOP");
+}
+
+
+//---------------------------------------------------------------------------
+// Example: ServiceDog:
+//---------------------------------------------------------------------------
+// This function resets the watchdog timer.
+// Enable this function for using ServiceDog in the application
+
+void ServiceDog(void)
+{
+ if(SysCtrlRegs.PLLCR.bit.DIV == DSP28_PLLCR)
+ if(SysCtrlRegs.PLLSTS.bit.DIVSEL == DSP28_DIVSEL)
+ {
+ EALLOW;
+ SysCtrlRegs.WDKEY = 0x0055;
+ SysCtrlRegs.WDKEY = 0x00AA;
+ EDIS;
+ return;
+} }
+
+
+//---------------------------------------------------------------------------
+// Example: DisableDog:
+//---------------------------------------------------------------------------
+// This function disables the watchdog timer.
+
+void DisableDog(void)
+{
+ EALLOW;
+ SysCtrlRegs.WDCR= 0x0068;
+ EDIS;
+}
+
+//---------------------------------------------------------------------------
+// Example: InitPll:
+//---------------------------------------------------------------------------
+// This function initializes the PLLCR register.
+
+void InitPll(Uint16 divval, Uint16 divsel)
+{
+ long clkVal;
+
+ // Make sure the PLL is not running in limp mode
+ if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0)
+ {
+ // Missing external clock has been detected
+ // Replace this line with a call to an appropriate
+ // SystemShutdown(); function.
+ asm(" ESTOP0");
+ }
+
+ // DIVSEL MUST be 0 before PLLCR can be changed from
+ // 0x0000. It is set to 0 by an external reset XRSn
+ // This puts us in 1/4
+ if (SysCtrlRegs.PLLSTS.bit.DIVSEL != 0)
+ {
+ EALLOW;
+ SysCtrlRegs.PLLSTS.bit.DIVSEL = 0;
+ EDIS;
+ }
+
+ // Change the PLLCR
+// if (SysCtrlRegs.PLLCR.bit.DIV != val)
+ {
+
+ EALLOW;
+ // Before setting PLLCR turn off missing clock detect logic
+ SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1;
+ SysCtrlRegs.PLLCR.bit.DIV = divval;
+ EDIS;
+
+ clkVal = (divval)?divval:1;
+ clkVal = XCLKIN * clkVal;
+
+ // Optional: Wait for PLL to lock.
+ // During this time the CPU will switch to OSCCLK/2 until
+ // the PLL is stable. Once the PLL is stable the CPU will
+ // switch to the new PLL value.
+ //
+ // This time-to-lock is monitored by a PLL lock counter.
+ //
+ // Code is not required to sit and wait for the PLL to lock.
+ // However, if the code does anything that is timing critical,
+ // and requires the correct clock be locked, then it is best to
+ // wait until this switching has completed.
+
+ // Wait for the PLL lock bit to be set.
+
+ // The watchdog should be disabled before this loop, or fed within
+ // the loop via ServiceDog().
+
+ // Uncomment to disable the watchdog
+ DisableDog();
+
+ while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1)
+ {
+ // Uncomment to service the watchdog
+ // ServiceDog();
+ }
+
+ EALLOW;
+ SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0;
+ EDIS;
+ }
+
+ // If switching to 1/2
+ if((divsel == 1)||(divsel == 2))
+ {
+ EALLOW;
+ SysCtrlRegs.PLLSTS.bit.DIVSEL = divsel;
+ EDIS;
+ }
+
+ if(divsel == 0) clkVal /= 4;
+ if(divsel == 1) clkVal /= 4;
+ if(divsel == 2) clkVal /= 2;
+
+ // If switching to 1/1
+ // * First go to 1/2 and let the power settle
+ // The time required will depend on the system, this is only an example
+ // * Then switch to 1/1
+
+ if((divval == 0) && (divsel == 3))
+ {
+ EALLOW;
+ SysCtrlRegs.PLLSTS.bit.DIVSEL = 2;
+ DELAY_US(50L);
+// pause_us(50L);
+ SysCtrlRegs.PLLSTS.bit.DIVSEL = 3;
+ EDIS;
+ }
+
+ SYSCLKOUT = clkVal;
+}
+
+//--------------------------------------------------------------------------
+// Example: InitPeripheralClocks:
+//---------------------------------------------------------------------------
+// This function initializes the clocks to the peripheral modules.
+// First the high and low clock prescalers are set
+// Second the clocks are enabled to each peripheral.
+// To reduce power, leave clocks to unused peripherals disabled
+//
+// Note: If a peripherals clock is not enabled then you cannot
+// read or write to the registers for that peripheral
+
+void InitPeripheralClocks(void)
+{
+ long Val;
+
+ EALLOW;
+
+// HISPCP/LOSPCP prescale register settings, normally it will be set to default values
+
+#if CLKMULT == 0
+ SysCtrlRegs.HISPCP.all = 0x0000;
+#endif
+#if CLKMULT == 1
+ SysCtrlRegs.HISPCP.all = 0x0000;
+#endif
+#if CLKMULT == 2
+ SysCtrlRegs.HISPCP.all = 0x0001;
+#endif
+#if CLKMULT == 3
+ SysCtrlRegs.HISPCP.all = 0x0002;
+#endif
+#if CLKMULT == 4
+ SysCtrlRegs.HISPCP.all = 0x0002;
+#endif
+#if CLKMULT == 5
+ SysCtrlRegs.HISPCP.all = 0x0003;
+#endif
+
+ SysCtrlRegs.LOSPCP.all = 0x0000;
+
+ Val = (SysCtrlRegs.HISPCP.all)?
+ SysCtrlRegs.HISPCP.all*2 : 1;
+ Val = SYSCLKOUT / Val;
+
+ HSPCLK = Val;
+
+ Val = (SysCtrlRegs.LOSPCP.all)?
+ SysCtrlRegs.LOSPCP.all*2 : 1;
+ Val = SYSCLKOUT / Val;
+ LSPCLK = Val;
+
+// XCLKOUT to SYSCLKOUT ratio. By default XCLKOUT = 1/4 SYSCLKOUT
+ // XTIMCLK = SYSCLKOUT/2
+ XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
+ // XCLKOUT = XTIMCLK/2
+ XintfRegs.XINTCNF2.bit.CLKMODE = 1;
+ // Enable XCLKOUT
+ XintfRegs.XINTCNF2.bit.CLKOFF = 0;
+
+// Peripheral clock enables set for the selected peripherals.
+// If you are not using a peripheral leave the clock off
+// to save on power.
+//
+// Note: not all peripherals are available on all 2833x derivates.
+// Refer to the datasheet for your particular device.
+//
+// This function is not written to be an example of efficient code.
+
+ SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // ADC
+
+ // *IMPORTANT*
+ // The ADC_cal function, which copies the ADC calibration values from TI reserved
+ // OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs automatically in the
+ // Boot ROM. If the boot ROM code is bypassed during the debug process, the
+ // following function MUST be called for the ADC to function according
+ // to specification. The clocks to the ADC MUST be enabled before calling this
+ // function.
+ // See the device data manual and/or the ADC Reference
+ // Manual for more information.
+
+ ADC_cal();
+
+
+ SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 1; // I2C
+ SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 1; // SCI-A
+ SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 1; // SCI-B
+ SysCtrlRegs.PCLKCR0.bit.SCICENCLK = 1; // SCI-C
+ SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 1; // SPI-A
+ SysCtrlRegs.PCLKCR0.bit.MCBSPAENCLK = 1; // McBSP-A
+ SysCtrlRegs.PCLKCR0.bit.MCBSPBENCLK = 1; // McBSP-B
+ SysCtrlRegs.PCLKCR0.bit.ECANAENCLK=1; // eCAN-A
+ SysCtrlRegs.PCLKCR0.bit.ECANBENCLK=1; // eCAN-B
+
+ SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the ePWM
+ SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1; // ePWM1
+ SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1; // ePWM2
+ SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1; // ePWM3
+ SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1; // ePWM4
+ SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1; // ePWM5
+ SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 1; // ePWM6
+ SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the ePWM
+
+ SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 1; // eCAP3
+ SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 1; // eCAP4
+ SysCtrlRegs.PCLKCR1.bit.ECAP5ENCLK = 1; // eCAP5
+ SysCtrlRegs.PCLKCR1.bit.ECAP6ENCLK = 1; // eCAP6
+ SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 1; // eCAP1
+ SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 1; // eCAP2
+ SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 1; // eQEP1
+ SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 1; // eQEP2
+
+ SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 1; // CPU Timer 0
+ SysCtrlRegs.PCLKCR3.bit.CPUTIMER1ENCLK = 1; // CPU Timer 1
+ SysCtrlRegs.PCLKCR3.bit.CPUTIMER2ENCLK = 1; // CPU Timer 2
+
+ SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1; // DMA Clock
+ SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; // XTIMCLK
+ SysCtrlRegs.PCLKCR3.bit.GPIOINENCLK = 1; // GPIO input clock
+
+ EDIS;
+}
+
+//---------------------------------------------------------------------------
+// Example: CsmUnlock:
+//---------------------------------------------------------------------------
+// This function unlocks the CSM. User must replace 0xFFFF's with current
+// password for the DSP. Returns 1 if unlock is successful.
+
+#define STATUS_FAIL 0
+#define STATUS_SUCCESS 1
+
+Uint16 CsmUnlock()
+{
+ volatile Uint16 temp;
+
+ // Load the key registers with the current password. The 0xFFFF's are dummy
+ // passwords. User should replace them with the correct password for the DSP.
+
+ EALLOW;
+ CsmRegs.KEY0 = 0xFFFF;
+ CsmRegs.KEY1 = 0xFFFF;
+ CsmRegs.KEY2 = 0xFFFF;
+ CsmRegs.KEY3 = 0xFFFF;
+ CsmRegs.KEY4 = 0xFFFF;
+ CsmRegs.KEY5 = 0xFFFF;
+ CsmRegs.KEY6 = 0xFFFF;
+ CsmRegs.KEY7 = 0xFFFF;
+ EDIS;
+
+ // Perform a dummy read of the password locations
+ // if they match the key values, the CSM will unlock
+
+ temp = CsmPwl.PSWD0;
+ temp = CsmPwl.PSWD1;
+ temp = CsmPwl.PSWD2;
+ temp = CsmPwl.PSWD3;
+ temp = CsmPwl.PSWD4;
+ temp = CsmPwl.PSWD5;
+ temp = CsmPwl.PSWD6;
+ temp = CsmPwl.PSWD7;
+
+ // If the CSM unlocked, return succes, otherwise return
+ // failure.
+ if (CsmRegs.CSMSCR.bit.SECURE == 0) return STATUS_SUCCESS;
+ else return STATUS_FAIL;
+
+}
+
+
+//===========================================================================
+// End of file.
+//===========================================================================
diff --git a/v120/DSP2833x_common/source/DSP2833x_Xintf.c b/v120/DSP2833x_common/source/DSP2833x_Xintf.c
new file mode 100644
index 0000000..0d3619a
--- /dev/null
+++ b/v120/DSP2833x_common/source/DSP2833x_Xintf.c
@@ -0,0 +1,243 @@
+// TI File $Revision: /main/5 $
+// Checkin $Date: August 16, 2007 11:06:26 $
+//###########################################################################
+//
+// FILE: DSP2833x_Xintf.c
+//
+// TITLE: DSP2833x Device External Interface Init & Support Functions.
+//
+// DESCRIPTION:
+//
+// Example initialization function for the external interface (XINTF).
+// This example configures the XINTF to its default state. For an
+// example of how this function being used refer to the
+// examples/run_from_xintf project.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
+
+//---------------------------------------------------------------------------
+// InitXINTF:
+//---------------------------------------------------------------------------
+// This function initializes the External Interface the default reset state.
+//
+// Do not modify the timings of the XINTF while running from the XINTF. Doing
+// so can yield unpredictable results
+
+
+void InitXintf(void)
+{
+ // This shows how to write to the XINTF registers. The
+ // values used here are the default state after reset.
+ // Different hardware will require a different configuration.
+
+ // For an example of an XINTF configuration used with the
+ // F28335 eZdsp, refer to the examples/run_from_xintf project.
+
+ // Any changes to XINTF timing should only be made by code
+ // running outside of the XINTF.
+
+ // All Zones---------------------------------
+ // Timing for all zones based on XTIMCLK = 1/2 SYSCLKOUT
+ EALLOW;
+ XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
+ // No write buffering
+ XintfRegs.XINTCNF2.bit.WRBUFF = 0;
+ // XCLKOUT is enabled
+ XintfRegs.XINTCNF2.bit.CLKOFF = 0;
+ // XCLKOUT = XTIMCLK/2
+ XintfRegs.XINTCNF2.bit.CLKMODE = 1;
+
+
+ // Zone 0------------------------------------
+ // When using ready, ACTIVE must be 1 or greater
+ // Lead must always be 1 or greater
+ // Zone write timing
+ XintfRegs.XTIMING0.bit.XWRLEAD = 3;
+ XintfRegs.XTIMING0.bit.XWRACTIVE = 7;
+ XintfRegs.XTIMING0.bit.XWRTRAIL = 3;
+ // Zone read timing
+ XintfRegs.XTIMING0.bit.XRDLEAD = 3;
+ XintfRegs.XTIMING0.bit.XRDACTIVE = 7;
+ XintfRegs.XTIMING0.bit.XRDTRAIL = 3;
+
+ // double all Zone read/write lead/active/trail timing
+ XintfRegs.XTIMING0.bit.X2TIMING = 1;
+
+ // Zone will sample XREADY signal
+ XintfRegs.XTIMING0.bit.USEREADY = 1;
+ XintfRegs.XTIMING0.bit.READYMODE = 1; // sample asynchronous
+
+ // Size must be either:
+ // 0,1 = x32 or
+ // 1,1 = x16 other values are reserved
+ XintfRegs.XTIMING0.bit.XSIZE = 3;
+
+ // Zone 6------------------------------------
+ // When using ready, ACTIVE must be 1 or greater
+ // Lead must always be 1 or greater
+ // Zone write timing
+ XintfRegs.XTIMING6.bit.XWRLEAD = 3;
+ XintfRegs.XTIMING6.bit.XWRACTIVE = 7;
+ XintfRegs.XTIMING6.bit.XWRTRAIL = 3;
+ // Zone read timing
+ XintfRegs.XTIMING6.bit.XRDLEAD = 3;
+ XintfRegs.XTIMING6.bit.XRDACTIVE = 7;
+ XintfRegs.XTIMING6.bit.XRDTRAIL = 3;
+
+ // double all Zone read/write lead/active/trail timing
+ XintfRegs.XTIMING6.bit.X2TIMING = 1;
+
+ // Zone will sample XREADY signal
+ XintfRegs.XTIMING6.bit.USEREADY = 1;
+ XintfRegs.XTIMING6.bit.READYMODE = 1; // sample asynchronous
+
+ // Size must be either:
+ // 0,1 = x32 or
+ // 1,1 = x16 other values are reserved
+ XintfRegs.XTIMING6.bit.XSIZE = 3;
+
+
+ // Zone 7------------------------------------
+ // When using ready, ACTIVE must be 1 or greater
+ // Lead must always be 1 or greater
+ // Zone write timing
+ XintfRegs.XTIMING7.bit.XWRLEAD = 3;
+ XintfRegs.XTIMING7.bit.XWRACTIVE = 7;
+ XintfRegs.XTIMING7.bit.XWRTRAIL = 3;
+ // Zone read timing
+ XintfRegs.XTIMING7.bit.XRDLEAD = 3;
+ XintfRegs.XTIMING7.bit.XRDACTIVE = 7;
+ XintfRegs.XTIMING7.bit.XRDTRAIL = 3;
+
+ // double all Zone read/write lead/active/trail timing
+ XintfRegs.XTIMING7.bit.X2TIMING = 1;
+
+ // Zone will sample XREADY signal
+ XintfRegs.XTIMING7.bit.USEREADY = 1;
+ XintfRegs.XTIMING7.bit.READYMODE = 1; // sample asynchronous
+
+ // Size must be either:
+ // 0,1 = x32 or
+ // 1,1 = x16 other values are reserved
+ XintfRegs.XTIMING7.bit.XSIZE = 3;
+
+ // Bank switching
+ // Assume Zone 7 is slow, so add additional BCYC cycles
+ // when ever switching from Zone 7 to another Zone.
+ // This will help avoid bus contention.
+ XintfRegs.XBANK.bit.BANK = 7;
+ XintfRegs.XBANK.bit.BCYC = 7;
+ EDIS;
+ //Force a pipeline flush to ensure that the write to
+ //the last register configured occurs before returning.
+
+ InitXintf16Gpio();
+// InitXintf32Gpio();
+
+ asm(" RPT #7 || NOP");
+
+}
+
+void InitXintf32Gpio()
+{
+ EALLOW;
+ GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 3; // XD31
+ GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 3; // XD30
+ GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 3; // XD29
+ GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 3; // XD28
+ GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 3; // XD27
+ GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 3; // XD26
+ GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 3; // XD25
+ GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 3; // XD24
+ GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 3; // XD23
+ GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 3; // XD22
+ GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 3; // XD21
+ GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 3; // XD20
+ GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 3; // XD19
+ GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 3; // XD18
+ GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 3; // XD17
+ GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 3; // XD16
+
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 3; // XD31 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 3; // XD30 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 3; // XD29 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 3; // XD28 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 3; // XD27 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 3; // XD26 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // XD25 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // XD24 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // XD23 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // XD22 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // XD21 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // XD20 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // XD19 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // XD18 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // XD17 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 3; // XD16 asynchronous input
+
+
+ InitXintf16Gpio();
+}
+
+void InitXintf16Gpio()
+{
+ EALLOW;
+ GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 3; // XD15
+ GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 3; // XD14
+ GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 3; // XD13
+ GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 3; // XD12
+ GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 3; // XD11
+ GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 3; // XD10
+ GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 3; // XD19
+ GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 3; // XD8
+ GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // XD7
+ GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // XD6
+ GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // XD5
+ GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // XD4
+ GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // XD3
+ GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // XD2
+ GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // XD1
+ GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // XD0
+
+ GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // XA0/XWE1n
+ GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 3; // XA1
+ GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3; // XA2
+ GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3; // XA3
+ GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 3; // XA4
+ GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 3; // XA5
+ GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 3; // XA6
+ GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 3; // XA7
+
+ GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 3; // XA8
+ GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 3; // XA9
+ GpioCtrlRegs.GPCMUX2.bit.GPIO82 = 3; // XA10
+ GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 3; // XA11
+ GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3; // XA12
+ GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3; // XA13
+ GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3; // XA14
+ GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3; // XA15
+
+ GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3; // XA16
+// GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 3; // XA17
+// GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 3; // XA18
+// GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3; // XA19
+
+// GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // XREADY
+ GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // XRNW
+ GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // XWE0
+
+// GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 3; // XZCS0
+ GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // XZCS7
+// GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // XZCS6
+ EDIS;
+}
+
+//===========================================================================
+// No more.
+//===========================================================================
diff --git a/v120/DSP2833x_common/source/DSP2833x_usDelay.asm b/v120/DSP2833x_common/source/DSP2833x_usDelay.asm
new file mode 100644
index 0000000..d3878b4
--- /dev/null
+++ b/v120/DSP2833x_common/source/DSP2833x_usDelay.asm
@@ -0,0 +1,76 @@
+;// TI File $Revision: /main/4 $
+;// Checkin $Date: July 30, 2007 10:28:57 $
+;//###########################################################################
+;//
+;// FILE: DSP2833x_usDelay.asm
+;//
+;// TITLE: Simple delay function
+;//
+;// DESCRIPTION:
+;//
+;// This is a simple delay function that can be used to insert a specified
+;// delay into code.
+;//
+;// This function is only accurate if executed from internal zero-waitstate
+;// SARAM. If it is executed from waitstate memory then the delay will be
+;// longer then specified.
+;//
+;// To use this function:
+;//
+;// 1 - update the CPU clock speed in the DSP2833x_Examples.h
+;// file. For example:
+;// #define CPU_RATE 6.667L // for a 150MHz CPU clock speed
+;// or #define CPU_RATE 10.000L // for a 100MHz CPU clock speed
+;//
+;// 2 - Call this function by using the DELAY_US(A) macro
+;// that is defined in the DSP2833x_Examples.h file. This macro
+;// will convert the number of microseconds specified
+;// into a loop count for use with this function.
+;// This count will be based on the CPU frequency you specify.
+;//
+;// 3 - For the most accurate delay
+;// - Execute this function in 0 waitstate RAM.
+;// - Disable interrupts before calling the function
+;// If you do not disable interrupts, then think of
+;// this as an "at least" delay function as the actual
+;// delay may be longer.
+;//
+;// The C assembly call from the DELAY_US(time) macro will
+;// look as follows:
+;//
+;// extern void Delay(long LoopCount);
+;//
+;// MOV AL,#LowLoopCount
+;// MOV AH,#HighLoopCount
+;// LCR _Delay
+;//
+;// Or as follows (if count is less then 16-bits):
+;//
+;// MOV ACC,#LoopCount
+;// LCR _Delay
+;//
+;//
+;//###########################################################################
+;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+;// $Release Date: August 1, 2008 $
+;//###########################################################################
+
+ .def _DSP28x_usDelay
+ .sect ".text"
+
+ .global __DSP28x_usDelay
+_DSP28x_usDelay:
+ SUB ACC,#1
+ BF _DSP28x_usDelay,GEQ ;; Loop if ACC >= 0
+ LRETR
+
+;There is a 9/10 cycle overhead and each loop
+;takes five cycles. The LoopCount is given by
+;the following formula:
+; DELAY_CPU_CYCLES = 9 + 5*LoopCount
+; LoopCount = (DELAY_CPU_CYCLES - 9) / 5
+; The macro DELAY_US(A) performs this calculation for you
+;
+;//===========================================================================
+;// End of file.
+;//===========================================================================
diff --git a/v120/DSP2833x_headers/cmd/DSP2833x_Headers_BIOS.cmd b/v120/DSP2833x_headers/cmd/DSP2833x_Headers_BIOS.cmd
new file mode 100644
index 0000000..fe2d6c5
--- /dev/null
+++ b/v120/DSP2833x_headers/cmd/DSP2833x_Headers_BIOS.cmd
@@ -0,0 +1,183 @@
+/*
+// TI File $Revision: /main/9 $
+// Checkin $Date: August 8, 2008 11:09:25 $
+//###########################################################################
+//
+// FILE: DSP2833x_Headers_BIOS.cmd
+//
+// TITLE: DSP2833x Peripheral registers linker command file
+//
+// DESCRIPTION:
+//
+// This file is for use in BIOS applications.
+//
+// Linker command file to place the peripheral structures
+// used within the DSP2833x headerfiles into the correct memory
+// mapped locations.
+//
+// This version of the file does not include the PieVectorTable structure.
+// For non-BIOS applications, please use the DSP2833x_Headers_nonBIOS.cmd
+// file which includes the PieVectorTable structure.
+//
+//#####################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//#####################################################################
+*/
+
+MEMORY
+{
+ PAGE 0: /* Program Memory */
+
+ PAGE 1: /* Data Memory */
+
+ DEV_EMU : origin = 0x000880, length = 0x000180 /* device emulation registers */
+ FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */
+ CSM : origin = 0x000AE0, length = 0x000010 /* code security module registers */
+
+ ADC_MIRROR : origin = 0x000B00, length = 0x000010 /* ADC Results register mirror */
+
+ XINTF : origin = 0x000B20, length = 0x000020 /* external interface registers */
+
+ CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */
+ CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/
+ CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/
+
+ PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */
+
+ DMA : origin = 0x001000, length = 0x000200 /* DMA registers */
+
+ MCBSPA : origin = 0x005000, length = 0x000040 /* McBSP-A registers */
+ MCBSPB : origin = 0x005040, length = 0x000040 /* McBSP-B registers */
+
+ ECANA : origin = 0x006000, length = 0x000040 /* eCAN-A control and status registers */
+ ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN-A local acceptance masks */
+ ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN-A message object time stamps */
+ ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN-A object time-out registers */
+ ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN-A mailboxes */
+
+ ECANB : origin = 0x006200, length = 0x000040 /* eCAN-B control and status registers */
+ ECANB_LAM : origin = 0x006240, length = 0x000040 /* eCAN-B local acceptance masks */
+ ECANB_MOTS : origin = 0x006280, length = 0x000040 /* eCAN-B message object time stamps */
+ ECANB_MOTO : origin = 0x0062C0, length = 0x000040 /* eCAN-B object time-out registers */
+ ECANB_MBOX : origin = 0x006300, length = 0x000100 /* eCAN-B mailboxes */
+
+ EPWM1 : origin = 0x006800, length = 0x000022 /* Enhanced PWM 1 registers */
+ EPWM2 : origin = 0x006840, length = 0x000022 /* Enhanced PWM 2 registers */
+ EPWM3 : origin = 0x006880, length = 0x000022 /* Enhanced PWM 3 registers */
+ EPWM4 : origin = 0x0068C0, length = 0x000022 /* Enhanced PWM 4 registers */
+ EPWM5 : origin = 0x006900, length = 0x000022 /* Enhanced PWM 5 registers */
+ EPWM6 : origin = 0x006940, length = 0x000022 /* Enhanced PWM 6 registers */
+
+ ECAP1 : origin = 0x006A00, length = 0x000020 /* Enhanced Capture 1 registers */
+ ECAP2 : origin = 0x006A20, length = 0x000020 /* Enhanced Capture 2 registers */
+ ECAP3 : origin = 0x006A40, length = 0x000020 /* Enhanced Capture 3 registers */
+ ECAP4 : origin = 0x006A60, length = 0x000020 /* Enhanced Capture 4 registers */
+ ECAP5 : origin = 0x006A80, length = 0x000020 /* Enhanced Capture 5 registers */
+ ECAP6 : origin = 0x006AA0, length = 0x000020 /* Enhanced Capture 6 registers */
+
+ EQEP1 : origin = 0x006B00, length = 0x000040 /* Enhanced QEP 1 registers */
+ EQEP2 : origin = 0x006B40, length = 0x000040 /* Enhanced QEP 2 registers */
+
+ GPIOCTRL : origin = 0x006F80, length = 0x000040 /* GPIO control registers */
+ GPIODAT : origin = 0x006FC0, length = 0x000020 /* GPIO data registers */
+ GPIOINT : origin = 0x006FE0, length = 0x000020 /* GPIO interrupt/LPM registers */
+
+ SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */
+ SPIA : origin = 0x007040, length = 0x000010 /* SPI-A registers */
+ SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */
+ XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */
+
+ ADC : origin = 0x007100, length = 0x000020 /* ADC registers */
+
+ SCIB : origin = 0x007750, length = 0x000010 /* SCI-B registers */
+
+ SCIC : origin = 0x007770, length = 0x000010 /* SCI-C registers */
+
+ I2CA : origin = 0x007900, length = 0x000040 /* I2C-A registers */
+
+ CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */
+
+ PARTID : origin = 0x380090, length = 0x000001 /* Part ID register location */
+}
+
+
+SECTIONS
+{
+/*** The PIE Vector table is called PIEVECT by DSP/BIOS ***/
+ PieVectTableFile : > PIEVECT, PAGE = 1, TYPE = DSECT
+
+/*** Peripheral Frame 0 Register Structures ***/
+ DevEmuRegsFile : > DEV_EMU, PAGE = 1
+ FlashRegsFile : > FLASH_REGS, PAGE = 1
+ CsmRegsFile : > CSM, PAGE = 1
+ AdcMirrorFile : > ADC_MIRROR, PAGE = 1
+ XintfRegsFile : > XINTF, PAGE = 1
+ CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1
+ CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1
+ CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1
+ PieCtrlRegsFile : > PIE_CTRL, PAGE = 1
+ DmaRegsFile : > DMA, PAGE = 1
+
+/*** Peripheral Frame 3 Register Structures ***/
+ McbspaRegsFile : > MCBSPA, PAGE = 1
+ McbspbRegsFile : > MCBSPB, PAGE = 1
+
+/*** Peripheral Frame 1 Register Structures ***/
+ ECanaRegsFile : > ECANA, PAGE = 1
+ ECanaLAMRegsFile : > ECANA_LAM PAGE = 1
+ ECanaMboxesFile : > ECANA_MBOX PAGE = 1
+ ECanaMOTSRegsFile : > ECANA_MOTS PAGE = 1
+ ECanaMOTORegsFile : > ECANA_MOTO PAGE = 1
+
+ ECanbRegsFile : > ECANB, PAGE = 1
+ ECanbLAMRegsFile : > ECANB_LAM PAGE = 1
+ ECanbMboxesFile : > ECANB_MBOX PAGE = 1
+ ECanbMOTSRegsFile : > ECANB_MOTS PAGE = 1
+ ECanbMOTORegsFile : > ECANB_MOTO PAGE = 1
+
+ EPwm1RegsFile : > EPWM1 PAGE = 1
+ EPwm2RegsFile : > EPWM2 PAGE = 1
+ EPwm3RegsFile : > EPWM3 PAGE = 1
+ EPwm4RegsFile : > EPWM4 PAGE = 1
+ EPwm5RegsFile : > EPWM5 PAGE = 1
+ EPwm6RegsFile : > EPWM6 PAGE = 1
+
+ ECap1RegsFile : > ECAP1 PAGE = 1
+ ECap2RegsFile : > ECAP2 PAGE = 1
+ ECap3RegsFile : > ECAP3 PAGE = 1
+ ECap4RegsFile : > ECAP4 PAGE = 1
+ ECap5RegsFile : > ECAP5 PAGE = 1
+ ECap6RegsFile : > ECAP6 PAGE = 1
+
+ EQep1RegsFile : > EQEP1 PAGE = 1
+ EQep2RegsFile : > EQEP2 PAGE = 1
+
+ GpioCtrlRegsFile : > GPIOCTRL PAGE = 1
+ GpioDataRegsFile : > GPIODAT PAGE = 1
+ GpioIntRegsFile : > GPIOINT PAGE = 1
+
+/*** Peripheral Frame 2 Register Structures ***/
+ SysCtrlRegsFile : > SYSTEM, PAGE = 1
+ SpiaRegsFile : > SPIA, PAGE = 1
+ SciaRegsFile : > SCIA, PAGE = 1
+ XIntruptRegsFile : > XINTRUPT, PAGE = 1
+ AdcRegsFile : > ADC, PAGE = 1
+ ScibRegsFile : > SCIB, PAGE = 1
+ ScicRegsFile : > SCIC, PAGE = 1
+ I2caRegsFile : > I2CA, PAGE = 1
+
+/*** Code Security Module Register Structures ***/
+ CsmPwlFile : > CSM_PWL, PAGE = 1
+
+/*** Device Part ID Register Structures ***/
+ PartIdRegsFile : > PARTID, PAGE = 1
+
+}
+
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
\ No newline at end of file
diff --git a/v120/DSP2833x_headers/cmd/DSP2833x_Headers_nonBIOS.cmd b/v120/DSP2833x_headers/cmd/DSP2833x_Headers_nonBIOS.cmd
new file mode 100644
index 0000000..9da1026
--- /dev/null
+++ b/v120/DSP2833x_headers/cmd/DSP2833x_Headers_nonBIOS.cmd
@@ -0,0 +1,183 @@
+/*
+// TI File $Revision: /main/8 $
+// Checkin $Date: June 2, 2008 11:12:24 $
+//###########################################################################
+//
+// FILE: DSP2833x_Headers_nonBIOS.cmd
+//
+// TITLE: DSP2833x Peripheral registers linker command file
+//
+// DESCRIPTION:
+//
+// This file is for use in Non-BIOS applications.
+//
+// Linker command file to place the peripheral structures
+// used within the DSP2833x headerfiles into the correct memory
+// mapped locations.
+//
+// This version of the file includes the PieVectorTable structure.
+// For BIOS applications, please use the DSP2833x_Headers_BIOS.cmd file
+// which does not include the PieVectorTable structure.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+*/
+
+MEMORY
+{
+ PAGE 0: /* Program Memory */
+
+ PAGE 1: /* Data Memory */
+
+ DEV_EMU : origin = 0x000880, length = 0x000180 /* device emulation registers */
+ FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */
+ CSM : origin = 0x000AE0, length = 0x000010 /* code security module registers */
+
+ ADC_MIRROR : origin = 0x000B00, length = 0x000010 /* ADC Results register mirror */
+
+ XINTF : origin = 0x000B20, length = 0x000020 /* external interface registers */
+
+ CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */
+ CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/
+ CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/
+
+ PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */
+ PIE_VECT : origin = 0x000D00, length = 0x000100 /* PIE Vector Table */
+
+ DMA : origin = 0x001000, length = 0x000200 /* DMA registers */
+
+ MCBSPA : origin = 0x005000, length = 0x000040 /* McBSP-A registers */
+ MCBSPB : origin = 0x005040, length = 0x000040 /* McBSP-B registers */
+
+ ECANA : origin = 0x006000, length = 0x000040 /* eCAN-A control and status registers */
+ ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN-A local acceptance masks */
+ ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN-A message object time stamps */
+ ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN-A object time-out registers */
+ ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN-A mailboxes */
+
+ ECANB : origin = 0x006200, length = 0x000040 /* eCAN-B control and status registers */
+ ECANB_LAM : origin = 0x006240, length = 0x000040 /* eCAN-B local acceptance masks */
+ ECANB_MOTS : origin = 0x006280, length = 0x000040 /* eCAN-B message object time stamps */
+ ECANB_MOTO : origin = 0x0062C0, length = 0x000040 /* eCAN-B object time-out registers */
+ ECANB_MBOX : origin = 0x006300, length = 0x000100 /* eCAN-B mailboxes */
+
+ EPWM1 : origin = 0x006800, length = 0x000022 /* Enhanced PWM 1 registers */
+ EPWM2 : origin = 0x006840, length = 0x000022 /* Enhanced PWM 2 registers */
+ EPWM3 : origin = 0x006880, length = 0x000022 /* Enhanced PWM 3 registers */
+ EPWM4 : origin = 0x0068C0, length = 0x000022 /* Enhanced PWM 4 registers */
+ EPWM5 : origin = 0x006900, length = 0x000022 /* Enhanced PWM 5 registers */
+ EPWM6 : origin = 0x006940, length = 0x000022 /* Enhanced PWM 6 registers */
+
+ ECAP1 : origin = 0x006A00, length = 0x000020 /* Enhanced Capture 1 registers */
+ ECAP2 : origin = 0x006A20, length = 0x000020 /* Enhanced Capture 2 registers */
+ ECAP3 : origin = 0x006A40, length = 0x000020 /* Enhanced Capture 3 registers */
+ ECAP4 : origin = 0x006A60, length = 0x000020 /* Enhanced Capture 4 registers */
+ ECAP5 : origin = 0x006A80, length = 0x000020 /* Enhanced Capture 5 registers */
+ ECAP6 : origin = 0x006AA0, length = 0x000020 /* Enhanced Capture 6 registers */
+
+ EQEP1 : origin = 0x006B00, length = 0x000040 /* Enhanced QEP 1 registers */
+ EQEP2 : origin = 0x006B40, length = 0x000040 /* Enhanced QEP 2 registers */
+
+ GPIOCTRL : origin = 0x006F80, length = 0x000040 /* GPIO control registers */
+ GPIODAT : origin = 0x006FC0, length = 0x000020 /* GPIO data registers */
+ GPIOINT : origin = 0x006FE0, length = 0x000020 /* GPIO interrupt/LPM registers */
+
+ SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */
+ SPIA : origin = 0x007040, length = 0x000010 /* SPI-A registers */
+ SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */
+ XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */
+
+ ADC : origin = 0x007100, length = 0x000020 /* ADC registers */
+
+ SCIB : origin = 0x007750, length = 0x000010 /* SCI-B registers */
+
+ SCIC : origin = 0x007770, length = 0x000010 /* SCI-C registers */
+
+ I2CA : origin = 0x007900, length = 0x000040 /* I2C-A registers */
+
+ CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */
+
+ PARTID : origin = 0x380090, length = 0x000001 /* Part ID register location */
+}
+
+
+SECTIONS
+{
+ PieVectTableFile : > PIE_VECT, PAGE = 1
+
+/*** Peripheral Frame 0 Register Structures ***/
+ DevEmuRegsFile : > DEV_EMU, PAGE = 1
+ FlashRegsFile : > FLASH_REGS, PAGE = 1
+ CsmRegsFile : > CSM, PAGE = 1
+ AdcMirrorFile : > ADC_MIRROR, PAGE = 1
+ XintfRegsFile : > XINTF, PAGE = 1
+ CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1
+ CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1
+ CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1
+ PieCtrlRegsFile : > PIE_CTRL, PAGE = 1
+ DmaRegsFile : > DMA, PAGE = 1
+
+/*** Peripheral Frame 3 Register Structures ***/
+ McbspaRegsFile : > MCBSPA, PAGE = 1
+ McbspbRegsFile : > MCBSPB, PAGE = 1
+
+/*** Peripheral Frame 1 Register Structures ***/
+ ECanaRegsFile : > ECANA, PAGE = 1
+ ECanaLAMRegsFile : > ECANA_LAM PAGE = 1
+ ECanaMboxesFile : > ECANA_MBOX PAGE = 1
+ ECanaMOTSRegsFile : > ECANA_MOTS PAGE = 1
+ ECanaMOTORegsFile : > ECANA_MOTO PAGE = 1
+
+ ECanbRegsFile : > ECANB, PAGE = 1
+ ECanbLAMRegsFile : > ECANB_LAM PAGE = 1
+ ECanbMboxesFile : > ECANB_MBOX PAGE = 1
+ ECanbMOTSRegsFile : > ECANB_MOTS PAGE = 1
+ ECanbMOTORegsFile : > ECANB_MOTO PAGE = 1
+
+ EPwm1RegsFile : > EPWM1 PAGE = 1
+ EPwm2RegsFile : > EPWM2 PAGE = 1
+ EPwm3RegsFile : > EPWM3 PAGE = 1
+ EPwm4RegsFile : > EPWM4 PAGE = 1
+ EPwm5RegsFile : > EPWM5 PAGE = 1
+ EPwm6RegsFile : > EPWM6 PAGE = 1
+
+ ECap1RegsFile : > ECAP1 PAGE = 1
+ ECap2RegsFile : > ECAP2 PAGE = 1
+ ECap3RegsFile : > ECAP3 PAGE = 1
+ ECap4RegsFile : > ECAP4 PAGE = 1
+ ECap5RegsFile : > ECAP5 PAGE = 1
+ ECap6RegsFile : > ECAP6 PAGE = 1
+
+ EQep1RegsFile : > EQEP1 PAGE = 1
+ EQep2RegsFile : > EQEP2 PAGE = 1
+
+ GpioCtrlRegsFile : > GPIOCTRL PAGE = 1
+ GpioDataRegsFile : > GPIODAT PAGE = 1
+ GpioIntRegsFile : > GPIOINT PAGE = 1
+
+/*** Peripheral Frame 2 Register Structures ***/
+ SysCtrlRegsFile : > SYSTEM, PAGE = 1
+ SpiaRegsFile : > SPIA, PAGE = 1
+ SciaRegsFile : > SCIA, PAGE = 1
+ XIntruptRegsFile : > XINTRUPT, PAGE = 1
+ AdcRegsFile : > ADC, PAGE = 1
+ ScibRegsFile : > SCIB, PAGE = 1
+ ScicRegsFile : > SCIC, PAGE = 1
+ I2caRegsFile : > I2CA, PAGE = 1
+
+/*** Code Security Module Register Structures ***/
+ CsmPwlFile : > CSM_PWL, PAGE = 1
+
+/*** Device Part ID Register Structures ***/
+ PartIdRegsFile : > PARTID, PAGE = 1
+
+}
+
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
diff --git a/v120/DSP2833x_headers/include/DSP2833x_EQep.h b/v120/DSP2833x_headers/include/DSP2833x_EQep.h
new file mode 100644
index 0000000..c330165
--- /dev/null
+++ b/v120/DSP2833x_headers/include/DSP2833x_EQep.h
@@ -0,0 +1,242 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006 13:52:13 $
+//###########################################################################
+//
+// FILE: DSP2833x_EQep.h
+//
+// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module
+// Register Bit Definitions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#ifndef DSP2833x_EQEP_H
+#define DSP2833x_EQEP_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//----------------------------------------------------
+// Capture decoder control register bit definitions */
+struct QDECCTL_BITS { // bits description
+ Uint16 rsvd1:5; // 4:0 reserved
+ Uint16 QSP:1; // 5 QEPS input polarity
+ Uint16 QIP:1; // 6 QEPI input polarity
+ Uint16 QBP:1; // 7 QEPB input polarity
+ Uint16 QAP:1; // 8 QEPA input polarity
+ Uint16 IGATE:1; // 9 Index pulse gating option
+ Uint16 SWAP:1; // 10 CLK/DIR signal source for Position Counter
+ Uint16 XCR:1; // 11 External clock rate
+ Uint16 SPSEL:1; // 12 Sync output pin select
+ Uint16 SOEN:1; // 13 Enable position compare sync
+ Uint16 QSRC:2; // 15:14 Position counter source
+};
+
+union QDECCTL_REG {
+ Uint16 all;
+ struct QDECCTL_BITS bit;
+};
+
+
+//----------------------------------------------------
+// QEP control register bit definitions */
+struct QEPCTL_BITS { // bits description
+ Uint16 WDE:1; // 0 QEP watchdog enable
+ Uint16 UTE:1; // 1 QEP unit timer enable
+ Uint16 QCLM:1; // 2 QEP capture latch mode
+ Uint16 QPEN:1; // 3 Quadrature position counter enable
+ Uint16 IEL:2; // 5:4 Index event latch
+ Uint16 SEL:1; // 6 Strobe event latch
+ Uint16 SWI:1; // 7 Software init position counter
+ Uint16 IEI:2; // 9:8 Index event init of position count
+ Uint16 SEI:2; // 11:10 Strobe event init
+ Uint16 PCRM:2; // 13:12 Position counter reset
+ Uint16 FREE_SOFT:2; // 15:14 Emulation mode
+};
+
+union QEPCTL_REG {
+ Uint16 all;
+ struct QEPCTL_BITS bit;
+};
+
+
+//----------------------------------------------------
+// Quadrature capture control register bit definitions */
+struct QCAPCTL_BITS { // bits description
+ Uint16 UPPS:4; // 3:0 Unit position pre-scale
+ Uint16 CCPS:3; // 6:4 QEP capture timer pre-scale
+ Uint16 rsvd1:8; // 14:7 reserved
+ Uint16 CEN:1; // 15 Enable QEP capture
+};
+
+
+union QCAPCTL_REG {
+ Uint16 all;
+ struct QCAPCTL_BITS bit;
+};
+
+
+
+//----------------------------------------------------
+// Position compare control register bit definitions */
+struct QPOSCTL_BITS { // bits description
+ Uint16 PCSPW:12; // 11:0 Position compare sync pulse width
+ Uint16 PCE:1; // 12 Position compare enable/disable
+ Uint16 PCPOL:1; // 13 Polarity of sync output
+ Uint16 PCLOAD:1; // 14 Position compare of shadow load
+ Uint16 PCSHDW:1; // 15 Position compare shadow enable
+};
+
+union QPOSCTL_REG {
+ Uint16 all;
+ struct QPOSCTL_BITS bit;
+};
+
+//----------------------------------------------------
+// QEP interrupt control register bit definitions */
+struct QEINT_BITS { // bits description
+ Uint16 rsvd1:1; // 0 reserved
+ Uint16 PCE:1; // 1 Position counter error
+ Uint16 QPE:1; // 2 Quadrature phase error
+ Uint16 QDC:1; // 3 Quadrature dir change
+ Uint16 WTO:1; // 4 Watchdog timeout
+ Uint16 PCU:1; // 5 Position counter underflow
+ Uint16 PCO:1; // 6 Position counter overflow
+ Uint16 PCR:1; // 7 Position compare ready
+ Uint16 PCM:1; // 8 Position compare match
+ Uint16 SEL:1; // 9 Strobe event latch
+ Uint16 IEL:1; // 10 Event latch
+ Uint16 UTO:1; // 11 Unit timeout
+ Uint16 rsvd2:4; // 15:12 reserved
+};
+
+
+union QEINT_REG {
+ Uint16 all;
+ struct QEINT_BITS bit;
+};
+
+
+//----------------------------------------------------
+// QEP interrupt status register bit definitions */
+struct QFLG_BITS { // bits description
+ Uint16 INT:1; // 0 Global interrupt
+ Uint16 PCE:1; // 1 Position counter error
+ Uint16 PHE:1; // 2 Quadrature phase error
+ Uint16 QDC:1; // 3 Quadrature dir change
+ Uint16 WTO:1; // 4 Watchdog timeout
+ Uint16 PCU:1; // 5 Position counter underflow
+ Uint16 PCO:1; // 6 Position counter overflow
+ Uint16 PCR:1; // 7 Position compare ready
+ Uint16 PCM:1; // 8 Position compare match
+ Uint16 SEL:1; // 9 Strobe event latch
+ Uint16 IEL:1; // 10 Event latch
+ Uint16 UTO:1; // 11 Unit timeout
+ Uint16 rsvd2:4; // 15:12 reserved
+};
+
+
+union QFLG_REG {
+ Uint16 all;
+ struct QFLG_BITS bit;
+};
+
+//----------------------------------------------------
+// QEP interrupt force register bit definitions */
+struct QFRC_BITS { // bits description
+ Uint16 reserved:1; // 0 Reserved
+ Uint16 PCE:1; // 1 Position counter error
+ Uint16 PHE:1; // 2 Quadrature phase error
+ Uint16 QDC:1; // 3 Quadrature dir change
+ Uint16 WTO:1; // 4 Watchdog timeout
+ Uint16 PCU:1; // 5 Position counter underflow
+ Uint16 PCO:1; // 6 Position counter overflow
+ Uint16 PCR:1; // 7 Position compare ready
+ Uint16 PCM:1; // 8 Position compare match
+ Uint16 SEL:1; // 9 Strobe event latch
+ Uint16 IEL:1; // 10 Event latch
+ Uint16 UTO:1; // 11 Unit timeout
+ Uint16 rsvd2:4; // 15:12 reserved
+};
+
+
+union QFRC_REG {
+ Uint16 all;
+ struct QFRC_BITS bit;
+};
+
+// V1.1 Added UPEVNT (bit 7) This reflects changes
+// made as of F2833x Rev A devices
+//----------------------------------------------------
+// QEP status register bit definitions */
+struct QEPSTS_BITS { // bits description
+ Uint16 PCEF:1; // 0 Position counter error
+ Uint16 FIMF:1; // 1 First index marker
+ Uint16 CDEF:1; // 2 Capture direction error
+ Uint16 COEF:1; // 3 Capture overflow error
+ Uint16 QDLF:1; // 4 QEP direction latch
+ Uint16 QDF:1; // 5 Quadrature direction
+ Uint16 FIDF:1; // 6 Direction on first index marker
+ Uint16 UPEVNT:1; // 7 Unit position event flag
+ Uint16 rsvd1:8; // 15:8 reserved
+};
+
+union QEPSTS_REG {
+ Uint16 all;
+ struct QEPSTS_BITS bit;
+};
+
+//----------------------------------------------------
+
+struct EQEP_REGS {
+ Uint32 QPOSCNT; // Position counter
+ Uint32 QPOSINIT; // Position counter init
+ Uint32 QPOSMAX; // Maximum position count
+ Uint32 QPOSCMP; // Position compare
+ Uint32 QPOSILAT; // Index position latch
+ Uint32 QPOSSLAT; // Strobe position latch
+ Uint32 QPOSLAT; // Position latch
+ Uint32 QUTMR; // Unit timer
+ Uint32 QUPRD; // Unit period
+ Uint16 QWDTMR; // QEP watchdog timer
+ Uint16 QWDPRD; // QEP watchdog period
+ union QDECCTL_REG QDECCTL; // Quadrature decoder control
+ union QEPCTL_REG QEPCTL; // QEP control
+ union QCAPCTL_REG QCAPCTL; // Quadrature capture control
+ union QPOSCTL_REG QPOSCTL; // Position compare control
+ union QEINT_REG QEINT; // QEP interrupt control
+ union QFLG_REG QFLG; // QEP interrupt flag
+ union QFLG_REG QCLR; // QEP interrupt clear
+ union QFRC_REG QFRC; // QEP interrupt force
+ union QEPSTS_REG QEPSTS; // QEP status
+ Uint16 QCTMR; // QEP capture timer
+ Uint16 QCPRD; // QEP capture period
+ Uint16 QCTMRLAT; // QEP capture latch
+ Uint16 QCPRDLAT; // QEP capture period latch
+ Uint16 rsvd1[30]; // reserved
+};
+
+
+
+
+//---------------------------------------------------------------------------
+// GPI/O External References & Function Declarations:
+//
+extern volatile struct EQEP_REGS EQep1Regs;
+extern volatile struct EQEP_REGS EQep2Regs;
+
+
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_EQEP_H definition
+
+//===========================================================================
+// End of file.
+//===========================================================================
diff --git a/v120/DSP2833x_headers/include/DSP2833x_Gpio.h b/v120/DSP2833x_headers/include/DSP2833x_Gpio.h
new file mode 100644
index 0000000..5759c81
--- /dev/null
+++ b/v120/DSP2833x_headers/include/DSP2833x_Gpio.h
@@ -0,0 +1,391 @@
+// TI File $Revision: /main/4 $
+// Checkin $Date: November 15, 2007 09:58:53 $
+//###########################################################################
+//
+// FILE: DSP2833x_Gpio.h
+//
+// TITLE: DSP2833x General Purpose I/O Definitions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#ifndef DSP2833x_GPIO_H
+#define DSP2833x_GPIO_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//----------------------------------------------------
+// GPIO A control register bit definitions */
+struct GPACTRL_BITS { // bits description
+ Uint16 QUALPRD0:8; // 7:0 Qual period
+ Uint16 QUALPRD1:8; // 15:8 Qual period
+ Uint16 QUALPRD2:8; // 23:16 Qual period
+ Uint16 QUALPRD3:8; // 31:24 Qual period
+};
+
+union GPACTRL_REG {
+ Uint32 all;
+ struct GPACTRL_BITS bit;
+};
+
+//----------------------------------------------------
+// GPIO B control register bit definitions */
+struct GPBCTRL_BITS { // bits description
+ Uint16 QUALPRD0:8; // 7:0 Qual period
+ Uint16 QUALPRD1:8; // 15:8 Qual period
+ Uint16 QUALPRD2:8; // 23:16 Qual period
+ Uint16 QUALPRD3:8; // 31:24
+};
+
+union GPBCTRL_REG {
+ Uint32 all;
+ struct GPBCTRL_BITS bit;
+};
+
+//----------------------------------------------------
+// GPIO A Qual/MUX select register bit definitions */
+struct GPA1_BITS { // bits description
+ Uint16 GPIO0:2; // 1:0 GPIO0
+ Uint16 GPIO1:2; // 3:2 GPIO1
+ Uint16 GPIO2:2; // 5:4 GPIO2
+ Uint16 GPIO3:2; // 7:6 GPIO3
+ Uint16 GPIO4:2; // 9:8 GPIO4
+ Uint16 GPIO5:2; // 11:10 GPIO5
+ Uint16 GPIO6:2; // 13:12 GPIO6
+ Uint16 GPIO7:2; // 15:14 GPIO7
+ Uint16 GPIO8:2; // 17:16 GPIO8
+ Uint16 GPIO9:2; // 19:18 GPIO9
+ Uint16 GPIO10:2; // 21:20 GPIO10
+ Uint16 GPIO11:2; // 23:22 GPIO11
+ Uint16 GPIO12:2; // 25:24 GPIO12
+ Uint16 GPIO13:2; // 27:26 GPIO13
+ Uint16 GPIO14:2; // 29:28 GPIO14
+ Uint16 GPIO15:2; // 31:30 GPIO15
+};
+
+
+struct GPA2_BITS { // bits description
+ Uint16 GPIO16:2; // 1:0 GPIO16
+ Uint16 GPIO17:2; // 3:2 GPIO17
+ Uint16 GPIO18:2; // 5:4 GPIO18
+ Uint16 GPIO19:2; // 7:6 GPIO19
+ Uint16 GPIO20:2; // 9:8 GPIO20
+ Uint16 GPIO21:2; // 11:10 GPIO21
+ Uint16 GPIO22:2; // 13:12 GPIO22
+ Uint16 GPIO23:2; // 15:14 GPIO23
+ Uint16 GPIO24:2; // 17:16 GPIO24
+ Uint16 GPIO25:2; // 19:18 GPIO25
+ Uint16 GPIO26:2; // 21:20 GPIO26
+ Uint16 GPIO27:2; // 23:22 GPIO27
+ Uint16 GPIO28:2; // 25:24 GPIO28
+ Uint16 GPIO29:2; // 27:26 GPIO29
+ Uint16 GPIO30:2; // 29:28 GPIO30
+ Uint16 GPIO31:2; // 31:30 GPIO31
+};
+
+struct GPB1_BITS { // bits description
+ Uint16 GPIO32:2; // 1:0 GPIO32
+ Uint16 GPIO33:2; // 3:2 GPIO33
+ Uint16 GPIO34:2; // 5:4 GPIO34
+ Uint16 GPIO35:2; // 7:6 GPIO35
+ Uint16 GPIO36:2; // 9:8 GPIO36
+ Uint16 GPIO37:2; // 11:10 GPIO37
+ Uint16 GPIO38:2; // 13:12 GPIO38
+ Uint16 GPIO39:2; // 15:14 GPIO39
+ Uint16 GPIO40:2; // 17:16 GPIO40
+ Uint16 GPIO41:2; // 19:16 GPIO41
+ Uint16 GPIO42:2; // 21:20 GPIO42
+ Uint16 GPIO43:2; // 23:22 GPIO43
+ Uint16 GPIO44:2; // 25:24 GPIO44
+ Uint16 GPIO45:2; // 27:26 GPIO45
+ Uint16 GPIO46:2; // 29:28 GPIO46
+ Uint16 GPIO47:2; // 31:30 GPIO47
+};
+
+struct GPB2_BITS { // bits description
+ Uint16 GPIO48:2; // 1:0 GPIO48
+ Uint16 GPIO49:2; // 3:2 GPIO49
+ Uint16 GPIO50:2; // 5:4 GPIO50
+ Uint16 GPIO51:2; // 7:6 GPIO51
+ Uint16 GPIO52:2; // 9:8 GPIO52
+ Uint16 GPIO53:2; // 11:10 GPIO53
+ Uint16 GPIO54:2; // 13:12 GPIO54
+ Uint16 GPIO55:2; // 15:14 GPIO55
+ Uint16 GPIO56:2; // 17:16 GPIO56
+ Uint16 GPIO57:2; // 19:18 GPIO57
+ Uint16 GPIO58:2; // 21:20 GPIO58
+ Uint16 GPIO59:2; // 23:22 GPIO59
+ Uint16 GPIO60:2; // 25:24 GPIO60
+ Uint16 GPIO61:2; // 27:26 GPIO61
+ Uint16 GPIO62:2; // 29:28 GPIO62
+ Uint16 GPIO63:2; // 31:30 GPIO63
+};
+
+struct GPC1_BITS { // bits description
+ Uint16 GPIO64:2; // 1:0 GPIO64
+ Uint16 GPIO65:2; // 3:2 GPIO65
+ Uint16 GPIO66:2; // 5:4 GPIO66
+ Uint16 GPIO67:2; // 7:6 GPIO67
+ Uint16 GPIO68:2; // 9:8 GPIO68
+ Uint16 GPIO69:2; // 11:10 GPIO69
+ Uint16 GPIO70:2; // 13:12 GPIO70
+ Uint16 GPIO71:2; // 15:14 GPIO71
+ Uint16 GPIO72:2; // 17:16 GPIO72
+ Uint16 GPIO73:2; // 19:18 GPIO73
+ Uint16 GPIO74:2; // 21:20 GPIO74
+ Uint16 GPIO75:2; // 23:22 GPIO75
+ Uint16 GPIO76:2; // 25:24 GPIO76
+ Uint16 GPIO77:2; // 27:26 GPIO77
+ Uint16 GPIO78:2; // 29:28 GPIO78
+ Uint16 GPIO79:2; // 31:30 GPIO79
+};
+
+
+struct GPC2_BITS { // bits description
+ Uint16 GPIO80:2; // 1:0 GPIO80
+ Uint16 GPIO81:2; // 3:2 GPIO81
+ Uint16 GPIO82:2; // 5:4 GPIO82
+ Uint16 GPIO83:2; // 7:6 GPIO83
+ Uint16 GPIO84:2; // 9:8 GPIO84
+ Uint16 GPIO85:2; // 11:10 GPIO85
+ Uint16 GPIO86:2; // 13:12 GPIO86
+ Uint16 GPIO87:2; // 15:14 GPIO87
+ Uint16 rsvd:16; // 31:16 reserved
+};
+
+
+union GPA1_REG {
+ Uint32 all;
+ struct GPA1_BITS bit;
+};
+
+union GPA2_REG {
+ Uint32 all;
+ struct GPA2_BITS bit;
+};
+
+union GPB1_REG {
+ Uint32 all;
+ struct GPB1_BITS bit;
+};
+
+union GPB2_REG {
+ Uint32 all;
+ struct GPB2_BITS bit;
+};
+
+union GPC1_REG {
+ Uint32 all;
+ struct GPC1_BITS bit;
+};
+
+union GPC2_REG {
+ Uint32 all;
+ struct GPC2_BITS bit;
+};
+
+//----------------------------------------------------
+// GPIO A DIR/TOGGLE/SET/CLEAR register bit definitions */
+struct GPADAT_BITS { // bits description
+ Uint16 GPIO0:1; // 0 GPIO0
+ Uint16 GPIO1:1; // 1 GPIO1
+ Uint16 GPIO2:1; // 2 GPIO2
+ Uint16 GPIO3:1; // 3 GPIO3
+ Uint16 GPIO4:1; // 4 GPIO4
+ Uint16 GPIO5:1; // 5 GPIO5
+ Uint16 GPIO6:1; // 6 GPIO6
+ Uint16 GPIO7:1; // 7 GPIO7
+ Uint16 GPIO8:1; // 8 GPIO8
+ Uint16 GPIO9:1; // 9 GPIO9
+ Uint16 GPIO10:1; // 10 GPIO10
+ Uint16 GPIO11:1; // 11 GPIO11
+ Uint16 GPIO12:1; // 12 GPIO12
+ Uint16 GPIO13:1; // 13 GPIO13
+ Uint16 GPIO14:1; // 14 GPIO14
+ Uint16 GPIO15:1; // 15 GPIO15
+ Uint16 GPIO16:1; // 16 GPIO16
+ Uint16 GPIO17:1; // 17 GPIO17
+ Uint16 GPIO18:1; // 18 GPIO18
+ Uint16 GPIO19:1; // 19 GPIO19
+ Uint16 GPIO20:1; // 20 GPIO20
+ Uint16 GPIO21:1; // 21 GPIO21
+ Uint16 GPIO22:1; // 22 GPIO22
+ Uint16 GPIO23:1; // 23 GPIO23
+ Uint16 GPIO24:1; // 24 GPIO24
+ Uint16 GPIO25:1; // 25 GPIO25
+ Uint16 GPIO26:1; // 26 GPIO26
+ Uint16 GPIO27:1; // 27 GPIO27
+ Uint16 GPIO28:1; // 28 GPIO28
+ Uint16 GPIO29:1; // 29 GPIO29
+ Uint16 GPIO30:1; // 30 GPIO30
+ Uint16 GPIO31:1; // 31 GPIO31
+};
+
+struct GPBDAT_BITS { // bits description
+ Uint16 GPIO32:1; // 0 GPIO32
+ Uint16 GPIO33:1; // 1 GPIO33
+ Uint16 GPIO34:1; // 2 GPIO34
+ Uint16 GPIO35:1; // 3 GPIO35
+ Uint16 GPIO36:1; // 4 GPIO36
+ Uint16 GPIO37:1; // 5 GPIO37
+ Uint16 GPIO38:1; // 6 GPIO38
+ Uint16 GPIO39:1; // 7 GPIO39
+ Uint16 GPIO40:1; // 8 GPIO40
+ Uint16 GPIO41:1; // 9 GPIO41
+ Uint16 GPIO42:1; // 10 GPIO42
+ Uint16 GPIO43:1; // 11 GPIO43
+ Uint16 GPIO44:1; // 12 GPIO44
+ Uint16 GPIO45:1; // 13 GPIO45
+ Uint16 GPIO46:1; // 14 GPIO46
+ Uint16 GPIO47:1; // 15 GPIO47
+ Uint16 GPIO48:1; // 16 GPIO48
+ Uint16 GPIO49:1; // 17 GPIO49
+ Uint16 GPIO50:1; // 18 GPIO50
+ Uint16 GPIO51:1; // 19 GPIO51
+ Uint16 GPIO52:1; // 20 GPIO52
+ Uint16 GPIO53:1; // 21 GPIO53
+ Uint16 GPIO54:1; // 22 GPIO54
+ Uint16 GPIO55:1; // 23 GPIO55
+ Uint16 GPIO56:1; // 24 GPIO56
+ Uint16 GPIO57:1; // 25 GPIO57
+ Uint16 GPIO58:1; // 26 GPIO58
+ Uint16 GPIO59:1; // 27 GPIO59
+ Uint16 GPIO60:1; // 28 GPIO60
+ Uint16 GPIO61:1; // 29 GPIO61
+ Uint16 GPIO62:1; // 30 GPIO62
+ Uint16 GPIO63:1; // 31 GPIO63
+};
+
+struct GPCDAT_BITS { // bits description
+ Uint16 GPIO64:1; // 0 GPIO64
+ Uint16 GPIO65:1; // 1 GPIO65
+ Uint16 GPIO66:1; // 2 GPIO66
+ Uint16 GPIO67:1; // 3 GPIO67
+ Uint16 GPIO68:1; // 4 GPIO68
+ Uint16 GPIO69:1; // 5 GPIO69
+ Uint16 GPIO70:1; // 6 GPIO70
+ Uint16 GPIO71:1; // 7 GPIO71
+ Uint16 GPIO72:1; // 8 GPIO72
+ Uint16 GPIO73:1; // 9 GPIO73
+ Uint16 GPIO74:1; // 10 GPIO74
+ Uint16 GPIO75:1; // 11 GPIO75
+ Uint16 GPIO76:1; // 12 GPIO76
+ Uint16 GPIO77:1; // 13 GPIO77
+ Uint16 GPIO78:1; // 14 GPIO78
+ Uint16 GPIO79:1; // 15 GPIO79
+ Uint16 GPIO80:1; // 16 GPIO80
+ Uint16 GPIO81:1; // 17 GPIO81
+ Uint16 GPIO82:1; // 18 GPIO82
+ Uint16 GPIO83:1; // 19 GPIO83
+ Uint16 GPIO84:1; // 20 GPIO84
+ Uint16 GPIO85:1; // 21 GPIO85
+ Uint16 GPIO86:1; // 22 GPIO86
+ Uint16 GPIO87:1; // 23 GPIO87
+ Uint16 rsvd1:8; // 31:24 reserved
+};
+
+
+union GPADAT_REG {
+ Uint32 all;
+ struct GPADAT_BITS bit;
+};
+
+union GPBDAT_REG {
+ Uint32 all;
+ struct GPBDAT_BITS bit;
+};
+
+union GPCDAT_REG {
+ Uint32 all;
+ struct GPCDAT_BITS bit;
+};
+
+
+
+
+//----------------------------------------------------
+// GPIO Xint1/XINT2/XNMI select register bit definitions */
+struct GPIOXINT_BITS { // bits description
+ Uint16 GPIOSEL:5; // 4:0 Select GPIO interrupt input source
+ Uint16 rsvd1:11; // 15:5 reserved
+};
+
+union GPIOXINT_REG {
+ Uint16 all;
+ struct GPIOXINT_BITS bit;
+};
+
+
+struct GPIO_CTRL_REGS {
+ union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31)
+ union GPA1_REG GPAQSEL1; // GPIO A Qualifier Select 1 Register (GPIO0 to 15)
+ union GPA2_REG GPAQSEL2; // GPIO A Qualifier Select 2 Register (GPIO16 to 31)
+ union GPA1_REG GPAMUX1; // GPIO A Mux 1 Register (GPIO0 to 15)
+ union GPA2_REG GPAMUX2; // GPIO A Mux 2 Register (GPIO16 to 31)
+ union GPADAT_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31)
+ union GPADAT_REG GPAPUD; // GPIO A Pull Up Disable Register (GPIO0 to 31)
+ Uint32 rsvd1;
+ union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 63)
+ union GPB1_REG GPBQSEL1; // GPIO B Qualifier Select 1 Register (GPIO32 to 47)
+ union GPB2_REG GPBQSEL2; // GPIO B Qualifier Select 2 Register (GPIO48 to 63)
+ union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47)
+ union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63)
+ union GPBDAT_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63)
+ union GPBDAT_REG GPBPUD; // GPIO B Pull Up Disable Register (GPIO32 to 63)
+ Uint16 rsvd2[8];
+ union GPC1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79)
+ union GPC2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95)
+ union GPCDAT_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95)
+ union GPCDAT_REG GPCPUD; // GPIO C Pull Up Disable Register (GPIO64 to 95)
+};
+
+struct GPIO_DATA_REGS {
+ union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31)
+ union GPADAT_REG GPASET; // GPIO Data Set Register (GPIO0 to 31)
+ union GPADAT_REG GPACLEAR; // GPIO Data Clear Register (GPIO0 to 31)
+ union GPADAT_REG GPATOGGLE; // GPIO Data Toggle Register (GPIO0 to 31)
+ union GPBDAT_REG GPBDAT; // GPIO Data Register (GPIO32 to 63)
+ union GPBDAT_REG GPBSET; // GPIO Data Set Register (GPIO32 to 63)
+ union GPBDAT_REG GPBCLEAR; // GPIO Data Clear Register (GPIO32 to 63)
+ union GPBDAT_REG GPBTOGGLE; // GPIO Data Toggle Register (GPIO32 to 63)
+ union GPCDAT_REG GPCDAT; // GPIO Data Register (GPIO64 to 95)
+ union GPCDAT_REG GPCSET; // GPIO Data Set Register (GPIO64 to 95)
+ union GPCDAT_REG GPCCLEAR; // GPIO Data Clear Register (GPIO64 to 95)
+ union GPCDAT_REG GPCTOGGLE; // GPIO Data Toggle Register (GPIO64 to 95)
+ Uint16 rsvd1[8];
+};
+
+struct GPIO_INT_REGS {
+ union GPIOXINT_REG GPIOXINT1SEL; // XINT1 GPIO Input Selection
+ union GPIOXINT_REG GPIOXINT2SEL; // XINT2 GPIO Input Selection
+ union GPIOXINT_REG GPIOXNMISEL; // XNMI_Xint13 GPIO Input Selection
+ union GPIOXINT_REG GPIOXINT3SEL; // XINT3 GPIO Input Selection
+ union GPIOXINT_REG GPIOXINT4SEL; // XINT4 GPIO Input Selection
+ union GPIOXINT_REG GPIOXINT5SEL; // XINT5 GPIO Input Selection
+ union GPIOXINT_REG GPIOXINT6SEL; // XINT6 GPIO Input Selection
+ union GPIOXINT_REG GPIOXINT7SEL; // XINT7 GPIO Input Selection
+ union GPADAT_REG GPIOLPMSEL; // Low power modes GP I/O input select
+};
+
+
+//---------------------------------------------------------------------------
+// GPI/O External References & Function Declarations:
+//
+extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs;
+extern volatile struct GPIO_DATA_REGS GpioDataRegs;
+extern volatile struct GPIO_INT_REGS GpioIntRegs;
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_GPIO_H definition
+
+//===========================================================================
+// End of file.
+//===========================================================================
diff --git a/v120/DSP2833x_headers/include/DSP2833x_I2c.h b/v120/DSP2833x_headers/include/DSP2833x_I2c.h
new file mode 100644
index 0000000..382c12d
--- /dev/null
+++ b/v120/DSP2833x_headers/include/DSP2833x_I2c.h
@@ -0,0 +1,193 @@
+// TI File $Revision: /main/2 $
+// Checkin $Date: March 22, 2007 10:40:22 $
+//###########################################################################
+//
+// FILE: DSP2833x_I2c.h
+//
+// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module
+// Register Bit Definitions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#ifndef DSP2833x_I2C_H
+#define DSP2833x_I2C_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//----------------------------------------------------
+// I2C interrupt vector register bit definitions */
+struct I2CISRC_BITS { // bits description
+ Uint16 INTCODE:3; // 2:0 Interrupt code
+ Uint16 rsvd1:13; // 15:3 reserved
+};
+
+union I2CISRC_REG {
+ Uint16 all;
+ struct I2CISRC_BITS bit;
+};
+
+//----------------------------------------------------
+// I2C interrupt mask register bit definitions */
+struct I2CIER_BITS { // bits description
+ Uint16 ARBL:1; // 0 Arbitration lost interrupt
+ Uint16 NACK:1; // 1 No ack interrupt
+ Uint16 ARDY:1; // 2 Register access ready interrupt
+ Uint16 RRDY:1; // 3 Recieve data ready interrupt
+ Uint16 XRDY:1; // 4 Transmit data ready interrupt
+ Uint16 SCD:1; // 5 Stop condition detection
+ Uint16 AAS:1; // 6 Address as slave
+ Uint16 rsvd:9; // 15:7 reserved
+};
+
+union I2CIER_REG {
+ Uint16 all;
+ struct I2CIER_BITS bit;
+};
+
+//----------------------------------------------------
+// I2C status register bit definitions */
+struct I2CSTR_BITS { // bits description
+ Uint16 ARBL:1; // 0 Arbitration lost interrupt
+ Uint16 NACK:1; // 1 No ack interrupt
+ Uint16 ARDY:1; // 2 Register access ready interrupt
+ Uint16 RRDY:1; // 3 Recieve data ready interrupt
+ Uint16 XRDY:1; // 4 Transmit data ready interrupt
+ Uint16 SCD:1; // 5 Stop condition detection
+ Uint16 rsvd1:2; // 7:6 reserved
+ Uint16 AD0:1; // 8 Address Zero
+ Uint16 AAS:1; // 9 Address as slave
+ Uint16 XSMT:1; // 10 XMIT shift empty
+ Uint16 RSFULL:1; // 11 Recieve shift full
+ Uint16 BB:1; // 12 Bus busy
+ Uint16 NACKSNT:1; // 13 A no ack sent
+ Uint16 SDIR:1; // 14 Slave direction
+ Uint16 rsvd2:1; // 15 reserved
+};
+
+union I2CSTR_REG {
+ Uint16 all;
+ struct I2CSTR_BITS bit;
+};
+
+
+//----------------------------------------------------
+// I2C mode control register bit definitions */
+struct I2CMDR_BITS { // bits description
+ Uint16 BC:3; // 2:0 Bit count
+ Uint16 FDF:1; // 3 Free data format
+ Uint16 STB:1; // 4 Start byte
+ Uint16 IRS:1; // 5 I2C Reset not
+ Uint16 DLB:1; // 6 Digital loopback
+ Uint16 RM:1; // 7 Repeat mode
+ Uint16 XA:1; // 8 Expand address
+ Uint16 TRX:1; // 9 Transmitter/reciever
+ Uint16 MST:1; // 10 Master/slave
+ Uint16 STP:1; // 11 Stop condition
+ Uint16 rsvd1:1; // 12 reserved
+ Uint16 STT:1; // 13 Start condition
+ Uint16 FREE:1; // 14 Emulation mode
+ Uint16 NACKMOD:1; // 15 No Ack mode
+};
+
+union I2CMDR_REG {
+ Uint16 all;
+ struct I2CMDR_BITS bit;
+};
+
+//----------------------------------------------------
+// I2C pre-scaler register bit definitions */
+struct I2CPSC_BITS { // bits description
+ Uint16 IPSC:8; // 7:0 pre-scaler
+ Uint16 rsvd1:8; // 15:8 reserved
+};
+
+
+union I2CPSC_REG {
+ Uint16 all;
+ struct I2CPSC_BITS bit;
+};
+
+
+//----------------------------------------------------
+// TX FIFO control register bit definitions */
+struct I2CFFTX_BITS { // bits description
+ Uint16 TXFFIL:5; // 4:0 FIFO interrupt level
+ Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable
+ Uint16 TXFFINTCLR:1; // 6 FIFO clear
+ Uint16 TXFFINT:1; // 7 FIFO interrupt flag
+ Uint16 TXFFST:5; // 12:8 FIFO level status
+ Uint16 TXFFRST:1; // 13 FIFO reset
+ Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs
+ Uint16 rsvd1:1; // 15 reserved
+
+};
+
+union I2CFFTX_REG {
+ Uint16 all;
+ struct I2CFFTX_BITS bit;
+};
+
+//----------------------------------------------------
+// RX FIFO control register bit definitions */
+struct I2CFFRX_BITS { // bits description
+ Uint16 RXFFIL:5; // 4:0 FIFO interrupt level
+ Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable
+ Uint16 RXFFINTCLR:1; // 6 FIFO clear
+ Uint16 RXFFINT:1; // 7 FIFO interrupt flag
+ Uint16 RXFFST:5; // 12:8 FIFO level
+ Uint16 RXFFRST:1; // 13 FIFO reset
+ Uint16 rsvd1:2; // 15:14 reserved
+};
+
+union I2CFFRX_REG {
+ Uint16 all;
+ struct I2CFFRX_BITS bit;
+};
+
+
+//----------------------------------------------------
+
+struct I2C_REGS {
+ Uint16 I2COAR; // Own address register
+ union I2CIER_REG I2CIER; // Interrupt enable
+ union I2CSTR_REG I2CSTR; // Interrupt status
+ Uint16 I2CCLKL; // Clock divider low
+ Uint16 I2CCLKH; // Clock divider high
+ Uint16 I2CCNT; // Data count
+ Uint16 I2CDRR; // Data recieve
+ Uint16 I2CSAR; // Slave address
+ Uint16 I2CDXR; // Data transmit
+ union I2CMDR_REG I2CMDR; // Mode
+ union I2CISRC_REG I2CISRC; // Interrupt source
+ Uint16 rsvd1; // reserved
+ union I2CPSC_REG I2CPSC; // Pre-scaler
+ Uint16 rsvd2[19]; // reserved
+ union I2CFFTX_REG I2CFFTX; // Transmit FIFO
+ union I2CFFRX_REG I2CFFRX; // Recieve FIFO
+};
+
+
+
+
+//---------------------------------------------------------------------------
+// External References & Function Declarations:
+//
+extern volatile struct I2C_REGS I2caRegs;
+
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_I2C_H definition
+
+//===========================================================================
+// End of file.
+//===========================================================================
diff --git a/v120/DSP2833x_headers/include/DSP2833x_Mcbsp.h b/v120/DSP2833x_headers/include/DSP2833x_Mcbsp.h
new file mode 100644
index 0000000..05e4af9
--- /dev/null
+++ b/v120/DSP2833x_headers/include/DSP2833x_Mcbsp.h
@@ -0,0 +1,715 @@
+// TI File $Revision: /main/5 $
+// Checkin $Date: May 14, 2008 16:30:31 $
+//###########################################################################
+//
+// FILE: DSP2833x_Mcbsp.h
+//
+// TITLE: DSP2833x Device McBSP Register Definitions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#ifndef DSP2833x_MCBSP_H
+#define DSP2833x_MCBSP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//---------------------------------------------------------------------------
+// McBSP Individual Register Bit Definitions:
+//
+// McBSP DRR2 register bit definitions:
+struct DRR2_BITS { // bit description
+ Uint16 HWLB:8; // 16:23 High word low byte
+ Uint16 HWHB:8; // 24:31 High word high byte
+};
+
+union DRR2_REG {
+ Uint16 all;
+ struct DRR2_BITS bit;
+};
+
+// McBSP DRR1 register bit definitions:
+struct DRR1_BITS { // bit description
+ Uint16 LWLB:8; // 16:23 Low word low byte
+ Uint16 LWHB:8; // 24:31 low word high byte
+};
+
+union DRR1_REG {
+ Uint16 all;
+ struct DRR1_BITS bit;
+};
+
+// McBSP DXR2 register bit definitions:
+struct DXR2_BITS { // bit description
+ Uint16 HWLB:8; // 16:23 High word low byte
+ Uint16 HWHB:8; // 24:31 High word high byte
+};
+
+union DXR2_REG {
+ Uint16 all;
+ struct DXR2_BITS bit;
+};
+
+// McBSP DXR1 register bit definitions:
+struct DXR1_BITS { // bit description
+ Uint16 LWLB:8; // 16:23 Low word low byte
+ Uint16 LWHB:8; // 24:31 low word high byte
+};
+
+union DXR1_REG {
+ Uint16 all;
+ struct DXR1_BITS bit;
+};
+
+// SPCR2 control register bit definitions:
+struct SPCR2_BITS { // bit description
+ Uint16 XRST:1; // 0 transmit reset
+ Uint16 XRDY:1; // 1 transmit ready
+ Uint16 XEMPTY:1; // 2 Transmit empty
+ Uint16 XSYNCERR:1; // 3 Transmit syn errorINT flag
+ Uint16 XINTM:2; // 5:4 Transmit interrupt types
+ Uint16 GRST:1; // 6 CLKG reset
+ Uint16 FRST:1; // 7 Frame sync reset
+ Uint16 SOFT:1; // 8 SOFT bit
+ Uint16 FREE:1; // 9 FREE bit
+ Uint16 rsvd:6; // 15:10 reserved
+};
+
+union SPCR2_REG {
+ Uint16 all;
+ struct SPCR2_BITS bit;
+};
+
+// SPCR1 control register bit definitions:
+struct SPCR1_BITS { // bit description
+ Uint16 RRST:1; // 0 Receive reset
+ Uint16 RRDY:1; // 1 Receive ready
+ Uint16 RFULL:1; // 2 Receive full
+ Uint16 RSYNCERR:1; // 7 Receive syn error
+ Uint16 RINTM:2; // 5:4 Receive interrupt types
+ Uint16 ABIS:1; // 6 ABIS mode select
+ Uint16 DXENA:1; // 7 DX hi-z enable
+ Uint16 rsvd:3; // 10:8 reserved
+ Uint16 CLKSTP:2; // 12:11 CLKSTOP mode bit
+ Uint16 RJUST:2; // 13:14 Right justified
+ Uint16 DLB:1; // 15 Digital loop back
+};
+
+union SPCR1_REG {
+ Uint16 all;
+ struct SPCR1_BITS bit;
+};
+
+// RCR2 control register bit definitions:
+struct RCR2_BITS { // bit description
+ Uint16 RDATDLY:2; // 1:0 Receive data delay
+ Uint16 RFIG:1; // 2 Receive frame sync ignore
+ Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects
+ Uint16 RWDLEN2:3; // 7:5 Receive word length
+ Uint16 RFRLEN2:7; // 14:8 Receive Frame sync
+ Uint16 RPHASE:1; // 15 Receive Phase
+};
+
+union RCR2_REG {
+ Uint16 all;
+ struct RCR2_BITS bit;
+};
+
+// RCR1 control register bit definitions:
+struct RCR1_BITS { // bit description
+ Uint16 rsvd1:5; // 4:0 reserved
+ Uint16 RWDLEN1:3; // 7:5 Receive word length
+ Uint16 RFRLEN1:7; // 14:8 Receive frame length
+ Uint16 rsvd2:1; // 15 reserved
+};
+
+union RCR1_REG {
+ Uint16 all;
+ struct RCR1_BITS bit;
+};
+
+// XCR2 control register bit definitions:
+
+struct XCR2_BITS { // bit description
+ Uint16 XDATDLY:2; // 1:0 Transmit data delay
+ Uint16 XFIG:1; // 2 Transmit frame sync ignore
+ Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects
+ Uint16 XWDLEN2:3; // 7:5 Transmit word length
+ Uint16 XFRLEN2:7; // 14:8 Transmit Frame sync
+ Uint16 XPHASE:1; // 15 Transmit Phase
+};
+
+union XCR2_REG {
+ Uint16 all;
+ struct XCR2_BITS bit;
+};
+
+// XCR1 control register bit definitions:
+struct XCR1_BITS { // bit description
+ Uint16 rsvd1:5; // 4:0 reserved
+ Uint16 XWDLEN1:3; // 7:5 Transmit word length
+ Uint16 XFRLEN1:7; // 14:8 Transmit frame length
+ Uint16 rsvd2:1; // 15 reserved
+};
+
+union XCR1_REG {
+ Uint16 all;
+ struct XCR1_BITS bit;
+};
+
+// SRGR2 Sample rate generator control register bit definitions:
+struct SRGR2_BITS { // bit description
+ Uint16 FPER:12; // 11:0 Frame period
+ Uint16 FSGM:1; // 12 Frame sync generator mode
+ Uint16 CLKSM:1; // 13 Sample rate generator mode
+ Uint16 rsvd:1; // 14 reserved
+ Uint16 GSYNC:1; // 15 CLKG sync
+};
+
+union SRGR2_REG {
+ Uint16 all;
+ struct SRGR2_BITS bit;
+};
+
+// SRGR1 control register bit definitions:
+struct SRGR1_BITS { // bit description
+ Uint16 CLKGDV:8; // 7:0 CLKG divider
+ Uint16 FWID:8; // 15:8 Frame width
+};
+
+union SRGR1_REG {
+ Uint16 all;
+ struct SRGR1_BITS bit;
+};
+
+// MCR2 Multichannel control register bit definitions:
+struct MCR2_BITS { // bit description
+ Uint16 XMCM:2; // 1:0 Transmit multichannel mode
+ Uint16 XCBLK:3; // 2:4 Transmit current block
+ Uint16 XPABLK:2; // 5:6 Transmit partition A Block
+ Uint16 XPBBLK:2; // 7:8 Transmit partition B Block
+ Uint16 XMCME:1; // 9 Transmit multi-channel enhance mode
+ Uint16 rsvd:6; // 15:10 reserved
+};
+
+union MCR2_REG {
+ Uint16 all;
+ struct MCR2_BITS bit;
+};
+
+// MCR1 Multichannel control register bit definitions:
+struct MCR1_BITS { // bit description
+ Uint16 RMCM:1; // 0 Receive multichannel mode
+ Uint16 rsvd:1; // 1 reserved
+ Uint16 RCBLK:3; // 4:2 Receive current block
+ Uint16 RPABLK:2; // 6:5 Receive partition A Block
+ Uint16 RPBBLK:2; // 7:8 Receive partition B Block
+ Uint16 RMCME:1; // 9 Receive multi-channel enhance mode
+ Uint16 rsvd1:6; // 15:10 reserved
+};
+
+union MCR1_REG {
+ Uint16 all;
+ struct MCR1_BITS bit;
+};
+
+// RCERA control register bit definitions:
+struct RCERA_BITS { // bit description
+ Uint16 RCEA0:1; // 0 Receive Channel enable bit
+ Uint16 RCEA1:1; // 1 Receive Channel enable bit
+ Uint16 RCEA2:1; // 2 Receive Channel enable bit
+ Uint16 RCEA3:1; // 3 Receive Channel enable bit
+ Uint16 RCEA4:1; // 4 Receive Channel enable bit
+ Uint16 RCEA5:1; // 5 Receive Channel enable bit
+ Uint16 RCEA6:1; // 6 Receive Channel enable bit
+ Uint16 RCEA7:1; // 7 Receive Channel enable bit
+ Uint16 RCEA8:1; // 8 Receive Channel enable bit
+ Uint16 RCEA9:1; // 9 Receive Channel enable bit
+ Uint16 RCEA10:1; // 10 Receive Channel enable bit
+ Uint16 RCEA11:1; // 11 Receive Channel enable bit
+ Uint16 RCEA12:1; // 12 Receive Channel enable bit
+ Uint16 RCEA13:1; // 13 Receive Channel enable bit
+ Uint16 RCEA14:1; // 14 Receive Channel enable bit
+ Uint16 RCEA15:1; // 15 Receive Channel enable bit
+};
+
+union RCERA_REG {
+ Uint16 all;
+ struct RCERA_BITS bit;
+};
+
+// RCERB control register bit definitions:
+struct RCERB_BITS { // bit description
+ Uint16 RCEB0:1; // 0 Receive Channel enable bit
+ Uint16 RCEB1:1; // 1 Receive Channel enable bit
+ Uint16 RCEB2:1; // 2 Receive Channel enable bit
+ Uint16 RCEB3:1; // 3 Receive Channel enable bit
+ Uint16 RCEB4:1; // 4 Receive Channel enable bit
+ Uint16 RCEB5:1; // 5 Receive Channel enable bit
+ Uint16 RCEB6:1; // 6 Receive Channel enable bit
+ Uint16 RCEB7:1; // 7 Receive Channel enable bit
+ Uint16 RCEB8:1; // 8 Receive Channel enable bit
+ Uint16 RCEB9:1; // 9 Receive Channel enable bit
+ Uint16 RCEB10:1; // 10 Receive Channel enable bit
+ Uint16 RCEB11:1; // 11 Receive Channel enable bit
+ Uint16 RCEB12:1; // 12 Receive Channel enable bit
+ Uint16 RCEB13:1; // 13 Receive Channel enable bit
+ Uint16 RCEB14:1; // 14 Receive Channel enable bit
+ Uint16 RCEB15:1; // 15 Receive Channel enable bit
+};
+
+union RCERB_REG {
+ Uint16 all;
+ struct RCERB_BITS bit;
+};
+
+// XCERA control register bit definitions:
+struct XCERA_BITS { // bit description
+ Uint16 XCERA0:1; // 0 Receive Channel enable bit
+ Uint16 XCERA1:1; // 1 Receive Channel enable bit
+ Uint16 XCERA2:1; // 2 Receive Channel enable bit
+ Uint16 XCERA3:1; // 3 Receive Channel enable bit
+ Uint16 XCERA4:1; // 4 Receive Channel enable bit
+ Uint16 XCERA5:1; // 5 Receive Channel enable bit
+ Uint16 XCERA6:1; // 6 Receive Channel enable bit
+ Uint16 XCERA7:1; // 7 Receive Channel enable bit
+ Uint16 XCERA8:1; // 8 Receive Channel enable bit
+ Uint16 XCERA9:1; // 9 Receive Channel enable bit
+ Uint16 XCERA10:1; // 10 Receive Channel enable bit
+ Uint16 XCERA11:1; // 11 Receive Channel enable bit
+ Uint16 XCERA12:1; // 12 Receive Channel enable bit
+ Uint16 XCERA13:1; // 13 Receive Channel enable bit
+ Uint16 XCERA14:1; // 14 Receive Channel enable bit
+ Uint16 XCERA15:1; // 15 Receive Channel enable bit
+};
+
+union XCERA_REG {
+ Uint16 all;
+ struct XCERA_BITS bit;
+};
+
+// XCERB control register bit definitions:
+struct XCERB_BITS { // bit description
+ Uint16 XCERB0:1; // 0 Receive Channel enable bit
+ Uint16 XCERB1:1; // 1 Receive Channel enable bit
+ Uint16 XCERB2:1; // 2 Receive Channel enable bit
+ Uint16 XCERB3:1; // 3 Receive Channel enable bit
+ Uint16 XCERB4:1; // 4 Receive Channel enable bit
+ Uint16 XCERB5:1; // 5 Receive Channel enable bit
+ Uint16 XCERB6:1; // 6 Receive Channel enable bit
+ Uint16 XCERB7:1; // 7 Receive Channel enable bit
+ Uint16 XCERB8:1; // 8 Receive Channel enable bit
+ Uint16 XCERB9:1; // 9 Receive Channel enable bit
+ Uint16 XCERB10:1; // 10 Receive Channel enable bit
+ Uint16 XCERB11:1; // 11 Receive Channel enable bit
+ Uint16 XCERB12:1; // 12 Receive Channel enable bit
+ Uint16 XCERB13:1; // 13 Receive Channel enable bit
+ Uint16 XCERB14:1; // 14 Receive Channel enable bit
+ Uint16 XCERB15:1; // 15 Receive Channel enable bit
+};
+
+union XCERB_REG {
+ Uint16 all;
+ struct XCERB_BITS bit;
+};
+
+// PCR control register bit definitions:
+struct PCR_BITS { // bit description
+ Uint16 CLKRP:1; // 0 Receive Clock polarity
+ Uint16 CLKXP:1; // 1 Transmit clock polarity
+ Uint16 FSRP:1; // 2 Receive Frame synchronization polarity
+ Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity
+ Uint16 DR_STAT:1; // 4 DR pin status - reserved for this McBSP
+ Uint16 DX_STAT:1; // 5 DX pin status - reserved for this McBSP
+ Uint16 CLKS_STAT:1; // 6 CLKS pin status - reserved for 28x -McBSP
+ Uint16 SCLKME:1; // 7 Enhanced sample clock mode selection bit.
+ Uint16 CLKRM:1; // 8 Receiver Clock Mode
+ Uint16 CLKXM:1; // 9 Transmitter Clock Mode.
+ Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode
+ Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode
+ Uint16 RIOEN:1; // 12 General Purpose I/O Mode - reserved in this 28x-McBSP
+ Uint16 XIOEN:1; // 13 General Purpose I/O Mode - reserved in this 28x-McBSP
+ Uint16 IDEL_EN:1; // 14 reserved in this 28x-McBSP
+ Uint16 rsvd:1 ; // 15 reserved
+};
+
+union PCR_REG {
+ Uint16 all;
+ struct PCR_BITS bit;
+};
+
+// RCERC control register bit definitions:
+struct RCERC_BITS { // bit description
+ Uint16 RCEC0:1; // 0 Receive Channel enable bit
+ Uint16 RCEC1:1; // 1 Receive Channel enable bit
+ Uint16 RCEC2:1; // 2 Receive Channel enable bit
+ Uint16 RCEC3:1; // 3 Receive Channel enable bit
+ Uint16 RCEC4:1; // 4 Receive Channel enable bit
+ Uint16 RCEC5:1; // 5 Receive Channel enable bit
+ Uint16 RCEC6:1; // 6 Receive Channel enable bit
+ Uint16 RCEC7:1; // 7 Receive Channel enable bit
+ Uint16 RCEC8:1; // 8 Receive Channel enable bit
+ Uint16 RCEC9:1; // 9 Receive Channel enable bit
+ Uint16 RCEC10:1; // 10 Receive Channel enable bit
+ Uint16 RCEC11:1; // 11 Receive Channel enable bit
+ Uint16 RCEC12:1; // 12 Receive Channel enable bit
+ Uint16 RCEC13:1; // 13 Receive Channel enable bit
+ Uint16 RCEC14:1; // 14 Receive Channel enable bit
+ Uint16 RCEC15:1; // 15 Receive Channel enable bit
+};
+
+union RCERC_REG {
+ Uint16 all;
+ struct RCERC_BITS bit;
+};
+
+// RCERD control register bit definitions:
+struct RCERD_BITS { // bit description
+ Uint16 RCED0:1; // 0 Receive Channel enable bit
+ Uint16 RCED1:1; // 1 Receive Channel enable bit
+ Uint16 RCED2:1; // 2 Receive Channel enable bit
+ Uint16 RCED3:1; // 3 Receive Channel enable bit
+ Uint16 RCED4:1; // 4 Receive Channel enable bit
+ Uint16 RCED5:1; // 5 Receive Channel enable bit
+ Uint16 RCED6:1; // 6 Receive Channel enable bit
+ Uint16 RCED7:1; // 7 Receive Channel enable bit
+ Uint16 RCED8:1; // 8 Receive Channel enable bit
+ Uint16 RCED9:1; // 9 Receive Channel enable bit
+ Uint16 RCED10:1; // 10 Receive Channel enable bit
+ Uint16 RCED11:1; // 11 Receive Channel enable bit
+ Uint16 RCED12:1; // 12 Receive Channel enable bit
+ Uint16 RCED13:1; // 13 Receive Channel enable bit
+ Uint16 RCED14:1; // 14 Receive Channel enable bit
+ Uint16 RCED15:1; // 15 Receive Channel enable bit
+};
+
+union RCERD_REG {
+ Uint16 all;
+ struct RCERD_BITS bit;
+};
+
+// XCERC control register bit definitions:
+struct XCERC_BITS { // bit description
+ Uint16 XCERC0:1; // 0 Receive Channel enable bit
+ Uint16 XCERC1:1; // 1 Receive Channel enable bit
+ Uint16 XCERC2:1; // 2 Receive Channel enable bit
+ Uint16 XCERC3:1; // 3 Receive Channel enable bit
+ Uint16 XCERC4:1; // 4 Receive Channel enable bit
+ Uint16 XCERC5:1; // 5 Receive Channel enable bit
+ Uint16 XCERC6:1; // 6 Receive Channel enable bit
+ Uint16 XCERC7:1; // 7 Receive Channel enable bit
+ Uint16 XCERC8:1; // 8 Receive Channel enable bit
+ Uint16 XCERC9:1; // 9 Receive Channel enable bit
+ Uint16 XCERC10:1; // 10 Receive Channel enable bit
+ Uint16 XCERC11:1; // 11 Receive Channel enable bit
+ Uint16 XCERC12:1; // 12 Receive Channel enable bit
+ Uint16 XCERC13:1; // 13 Receive Channel enable bit
+ Uint16 XCERC14:1; // 14 Receive Channel enable bit
+ Uint16 XCERC15:1; // 15 Receive Channel enable bit
+};
+
+union XCERC_REG {
+ Uint16 all;
+ struct XCERC_BITS bit;
+};
+
+// XCERD control register bit definitions:
+struct XCERD_BITS { // bit description
+ Uint16 XCERD0:1; // 0 Receive Channel enable bit
+ Uint16 XCERD1:1; // 1 Receive Channel enable bit
+ Uint16 XCERD2:1; // 2 Receive Channel enable bit
+ Uint16 XCERD3:1; // 3 Receive Channel enable bit
+ Uint16 XCERD4:1; // 4 Receive Channel enable bit
+ Uint16 XCERD5:1; // 5 Receive Channel enable bit
+ Uint16 XCERD6:1; // 6 Receive Channel enable bit
+ Uint16 XCERD7:1; // 7 Receive Channel enable bit
+ Uint16 XCERD8:1; // 8 Receive Channel enable bit
+ Uint16 XCERD9:1; // 9 Receive Channel enable bit
+ Uint16 XCERD10:1; // 10 Receive Channel enable bit
+ Uint16 XCERD11:1; // 11 Receive Channel enable bit
+ Uint16 XCERD12:1; // 12 Receive Channel enable bit
+ Uint16 XCERD13:1; // 13 Receive Channel enable bit
+ Uint16 XCERD14:1; // 14 Receive Channel enable bit
+ Uint16 XCERD15:1; // 15 Receive Channel enable bit
+};
+
+union XCERD_REG {
+ Uint16 all;
+ struct XCERD_BITS bit;
+};
+
+// RCERE control register bit definitions:
+struct RCERE_BITS { // bit description
+ Uint16 RCEE0:1; // 0 Receive Channel enable bit
+ Uint16 RCEE1:1; // 1 Receive Channel enable bit
+ Uint16 RCEE2:1; // 2 Receive Channel enable bit
+ Uint16 RCEE3:1; // 3 Receive Channel enable bit
+ Uint16 RCEE4:1; // 4 Receive Channel enable bit
+ Uint16 RCEE5:1; // 5 Receive Channel enable bit
+ Uint16 RCEE6:1; // 6 Receive Channel enable bit
+ Uint16 RCEE7:1; // 7 Receive Channel enable bit
+ Uint16 RCEE8:1; // 8 Receive Channel enable bit
+ Uint16 RCEE9:1; // 9 Receive Channel enable bit
+ Uint16 RCEE10:1; // 10 Receive Channel enable bit
+ Uint16 RCEE11:1; // 11 Receive Channel enable bit
+ Uint16 RCEE12:1; // 12 Receive Channel enable bit
+ Uint16 RCEE13:1; // 13 Receive Channel enable bit
+ Uint16 RCEE14:1; // 14 Receive Channel enable bit
+ Uint16 RCEE15:1; // 15 Receive Channel enable bit
+};
+
+union RCERE_REG {
+ Uint16 all;
+ struct RCERE_BITS bit;
+};
+
+// RCERF control register bit definitions:
+struct RCERF_BITS { // bit description
+ Uint16 RCEF0:1; // 0 Receive Channel enable bit
+ Uint16 RCEF1:1; // 1 Receive Channel enable bit
+ Uint16 RCEF2:1; // 2 Receive Channel enable bit
+ Uint16 RCEF3:1; // 3 Receive Channel enable bit
+ Uint16 RCEF4:1; // 4 Receive Channel enable bit
+ Uint16 RCEF5:1; // 5 Receive Channel enable bit
+ Uint16 RCEF6:1; // 6 Receive Channel enable bit
+ Uint16 RCEF7:1; // 7 Receive Channel enable bit
+ Uint16 RCEF8:1; // 8 Receive Channel enable bit
+ Uint16 RCEF9:1; // 9 Receive Channel enable bit
+ Uint16 RCEF10:1; // 10 Receive Channel enable bit
+ Uint16 RCEF11:1; // 11 Receive Channel enable bit
+ Uint16 RCEF12:1; // 12 Receive Channel enable bit
+ Uint16 RCEF13:1; // 13 Receive Channel enable bit
+ Uint16 RCEF14:1; // 14 Receive Channel enable bit
+ Uint16 RCEF15:1; // 15 Receive Channel enable bit
+};
+
+union RCERF_REG {
+ Uint16 all;
+ struct RCERF_BITS bit;
+};
+
+// XCERE control register bit definitions:
+struct XCERE_BITS { // bit description
+ Uint16 XCERE0:1; // 0 Receive Channel enable bit
+ Uint16 XCERE1:1; // 1 Receive Channel enable bit
+ Uint16 XCERE2:1; // 2 Receive Channel enable bit
+ Uint16 XCERE3:1; // 3 Receive Channel enable bit
+ Uint16 XCERE4:1; // 4 Receive Channel enable bit
+ Uint16 XCERE5:1; // 5 Receive Channel enable bit
+ Uint16 XCERE6:1; // 6 Receive Channel enable bit
+ Uint16 XCERE7:1; // 7 Receive Channel enable bit
+ Uint16 XCERE8:1; // 8 Receive Channel enable bit
+ Uint16 XCERE9:1; // 9 Receive Channel enable bit
+ Uint16 XCERE10:1; // 10 Receive Channel enable bit
+ Uint16 XCERE11:1; // 11 Receive Channel enable bit
+ Uint16 XCERE12:1; // 12 Receive Channel enable bit
+ Uint16 XCERE13:1; // 13 Receive Channel enable bit
+ Uint16 XCERE14:1; // 14 Receive Channel enable bit
+ Uint16 XCERE15:1; // 15 Receive Channel enable bit
+};
+
+union XCERE_REG {
+ Uint16 all;
+ struct XCERE_BITS bit;
+};
+
+// XCERF control register bit definitions:
+struct XCERF_BITS { // bit description
+ Uint16 XCERF0:1; // 0 Receive Channel enable bit
+ Uint16 XCERF1:1; // 1 Receive Channel enable bit
+ Uint16 XCERF2:1; // 2 Receive Channel enable bit
+ Uint16 XCERF3:1; // 3 Receive Channel enable bit
+ Uint16 XCERF4:1; // 4 Receive Channel enable bit
+ Uint16 XCERF5:1; // 5 Receive Channel enable bit
+ Uint16 XCERF6:1; // 6 Receive Channel enable bit
+ Uint16 XCERF7:1; // 7 Receive Channel enable bit
+ Uint16 XCERF8:1; // 8 Receive Channel enable bit
+ Uint16 XCERF9:1; // 9 Receive Channel enable bit
+ Uint16 XCERF10:1; // 10 Receive Channel enable bit
+ Uint16 XCERF11:1; // 11 Receive Channel enable bit
+ Uint16 XCERF12:1; // 12 Receive Channel enable bit
+ Uint16 XCERF13:1; // 13 Receive Channel enable bit
+ Uint16 XCERF14:1; // 14 Receive Channel enable bit
+ Uint16 XCERF15:1; // 15 Receive Channel enable bit
+};
+
+union XCERF_REG {
+ Uint16 all;
+ struct XCERF_BITS bit;
+};
+
+// RCERG control register bit definitions:
+struct RCERG_BITS { // bit description
+ Uint16 RCEG0:1; // 0 Receive Channel enable bit
+ Uint16 RCEG1:1; // 1 Receive Channel enable bit
+ Uint16 RCEG2:1; // 2 Receive Channel enable bit
+ Uint16 RCEG3:1; // 3 Receive Channel enable bit
+ Uint16 RCEG4:1; // 4 Receive Channel enable bit
+ Uint16 RCEG5:1; // 5 Receive Channel enable bit
+ Uint16 RCEG6:1; // 6 Receive Channel enable bit
+ Uint16 RCEG7:1; // 7 Receive Channel enable bit
+ Uint16 RCEG8:1; // 8 Receive Channel enable bit
+ Uint16 RCEG9:1; // 9 Receive Channel enable bit
+ Uint16 RCEG10:1; // 10 Receive Channel enable bit
+ Uint16 RCEG11:1; // 11 Receive Channel enable bit
+ Uint16 RCEG12:1; // 12 Receive Channel enable bit
+ Uint16 RCEG13:1; // 13 Receive Channel enable bit
+ Uint16 RCEG14:1; // 14 Receive Channel enable bit
+ Uint16 RCEG15:1; // 15 Receive Channel enable bit
+};
+
+union RCERG_REG {
+ Uint16 all;
+ struct RCERG_BITS bit;
+};
+
+// RCERH control register bit definitions:
+struct RCERH_BITS { // bit description
+ Uint16 RCEH0:1; // 0 Receive Channel enable bit
+ Uint16 RCEH1:1; // 1 Receive Channel enable bit
+ Uint16 RCEH2:1; // 2 Receive Channel enable bit
+ Uint16 RCEH3:1; // 3 Receive Channel enable bit
+ Uint16 RCEH4:1; // 4 Receive Channel enable bit
+ Uint16 RCEH5:1; // 5 Receive Channel enable bit
+ Uint16 RCEH6:1; // 6 Receive Channel enable bit
+ Uint16 RCEH7:1; // 7 Receive Channel enable bit
+ Uint16 RCEH8:1; // 8 Receive Channel enable bit
+ Uint16 RCEH9:1; // 9 Receive Channel enable bit
+ Uint16 RCEH10:1; // 10 Receive Channel enable bit
+ Uint16 RCEH11:1; // 11 Receive Channel enable bit
+ Uint16 RCEH12:1; // 12 Receive Channel enable bit
+ Uint16 RCEH13:1; // 13 Receive Channel enable bit
+ Uint16 RCEH14:1; // 14 Receive Channel enable bit
+ Uint16 RCEH15:1; // 15 Receive Channel enable bit
+};
+
+union RCERH_REG {
+ Uint16 all;
+ struct RCERH_BITS bit;
+};
+
+// XCERG control register bit definitions:
+struct XCERG_BITS { // bit description
+ Uint16 XCERG0:1; // 0 Receive Channel enable bit
+ Uint16 XCERG1:1; // 1 Receive Channel enable bit
+ Uint16 XCERG2:1; // 2 Receive Channel enable bit
+ Uint16 XCERG3:1; // 3 Receive Channel enable bit
+ Uint16 XCERG4:1; // 4 Receive Channel enable bit
+ Uint16 XCERG5:1; // 5 Receive Channel enable bit
+ Uint16 XCERG6:1; // 6 Receive Channel enable bit
+ Uint16 XCERG7:1; // 7 Receive Channel enable bit
+ Uint16 XCERG8:1; // 8 Receive Channel enable bit
+ Uint16 XCERG9:1; // 9 Receive Channel enable bit
+ Uint16 XCERG10:1; // 10 Receive Channel enable bit
+ Uint16 XCERG11:1; // 11 Receive Channel enable bit
+ Uint16 XCERG12:1; // 12 Receive Channel enable bit
+ Uint16 XCERG13:1; // 13 Receive Channel enable bit
+ Uint16 XCERG14:1; // 14 Receive Channel enable bit
+ Uint16 XCERG15:1; // 15 Receive Channel enable bit
+};
+
+union XCERG_REG {
+ Uint16 all;
+ struct XCERG_BITS bit;
+};
+
+// XCERH control register bit definitions:
+struct XCERH_BITS { // bit description
+ Uint16 XCEH0:1; // 0 Receive Channel enable bit
+ Uint16 XCEH1:1; // 1 Receive Channel enable bit
+ Uint16 XCEH2:1; // 2 Receive Channel enable bit
+ Uint16 XCEH3:1; // 3 Receive Channel enable bit
+ Uint16 XCEH4:1; // 4 Receive Channel enable bit
+ Uint16 XCEH5:1; // 5 Receive Channel enable bit
+ Uint16 XCEH6:1; // 6 Receive Channel enable bit
+ Uint16 XCEH7:1; // 7 Receive Channel enable bit
+ Uint16 XCEH8:1; // 8 Receive Channel enable bit
+ Uint16 XCEH9:1; // 9 Receive Channel enable bit
+ Uint16 XCEH10:1; // 10 Receive Channel enable bit
+ Uint16 XCEH11:1; // 11 Receive Channel enable bit
+ Uint16 XCEH12:1; // 12 Receive Channel enable bit
+ Uint16 XCEH13:1; // 13 Receive Channel enable bit
+ Uint16 XCEH14:1; // 14 Receive Channel enable bit
+ Uint16 XCEH15:1; // 15 Receive Channel enable bit
+};
+
+union XCERH_REG {
+ Uint16 all;
+ struct XCERH_BITS bit;
+};
+
+
+// McBSP Interrupt enable register for RINT/XINT
+struct MFFINT_BITS { // bits description
+ Uint16 XINT:1; // 0 XINT interrupt enable
+ Uint16 rsvd1:1; // 1 reserved
+ Uint16 RINT:1; // 2 RINT interrupt enable
+ Uint16 rsvd2:13; // 15:3 reserved
+};
+
+union MFFINT_REG {
+ Uint16 all;
+ struct MFFINT_BITS bit;
+};
+
+
+//---------------------------------------------------------------------------
+// McBSP Register File:
+//
+struct MCBSP_REGS {
+ union DRR2_REG DRR2; // MCBSP Data receive register bits 31-16
+ union DRR1_REG DRR1; // MCBSP Data receive register bits 15-0
+ union DXR2_REG DXR2; // MCBSP Data transmit register bits 31-16
+ union DXR1_REG DXR1; // MCBSP Data transmit register bits 15-0
+ union SPCR2_REG SPCR2; // MCBSP control register bits 31-16
+ union SPCR1_REG SPCR1; // MCBSP control register bits 15-0
+ union RCR2_REG RCR2; // MCBSP receive control register bits 31-16
+ union RCR1_REG RCR1; // MCBSP receive control register bits 15-0
+ union XCR2_REG XCR2; // MCBSP transmit control register bits 31-16
+ union XCR1_REG XCR1; // MCBSP transmit control register bits 15-0
+ union SRGR2_REG SRGR2; // MCBSP sample rate gen register bits 31-16
+ union SRGR1_REG SRGR1; // MCBSP sample rate gen register bits 15-0
+ union MCR2_REG MCR2; // MCBSP multichannel register bits 31-16
+ union MCR1_REG MCR1; // MCBSP multichannel register bits 15-0
+ union RCERA_REG RCERA; // MCBSP Receive channel enable partition A
+ union RCERB_REG RCERB; // MCBSP Receive channel enable partition B
+ union XCERA_REG XCERA; // MCBSP Transmit channel enable partition A
+ union XCERB_REG XCERB; // MCBSP Transmit channel enable partition B
+ union PCR_REG PCR; // MCBSP Pin control register bits 15-0
+ union RCERC_REG RCERC; // MCBSP Receive channel enable partition C
+ union RCERD_REG RCERD; // MCBSP Receive channel enable partition D
+ union XCERC_REG XCERC; // MCBSP Transmit channel enable partition C
+ union XCERD_REG XCERD; // MCBSP Transmit channel enable partition D
+ union RCERE_REG RCERE; // MCBSP Receive channel enable partition E
+ union RCERF_REG RCERF; // MCBSP Receive channel enable partition F
+ union XCERE_REG XCERE; // MCBSP Transmit channel enable partition E
+ union XCERF_REG XCERF; // MCBSP Transmit channel enable partition F
+ union RCERG_REG RCERG; // MCBSP Receive channel enable partition G
+ union RCERH_REG RCERH; // MCBSP Receive channel enable partition H
+ union XCERG_REG XCERG; // MCBSP Transmit channel enable partition G
+ union XCERH_REG XCERH; // MCBSP Transmit channel enable partition H
+ Uint16 rsvd1[4]; // reserved
+ union MFFINT_REG MFFINT; // MCBSP Interrupt enable register for RINT/XINT
+ Uint16 rsvd2; // reserved
+};
+
+//---------------------------------------------------------------------------
+// McBSP External References & Function Declarations:
+//
+extern volatile struct MCBSP_REGS McbspaRegs;
+extern volatile struct MCBSP_REGS McbspbRegs;
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_MCBSP_H definition
+
+//===========================================================================
+// No more.
+//===========================================================================
diff --git a/v120/DSP2833x_headers/include/DSP2833x_PieCtrl.h b/v120/DSP2833x_headers/include/DSP2833x_PieCtrl.h
new file mode 100644
index 0000000..1ab6e9d
--- /dev/null
+++ b/v120/DSP2833x_headers/include/DSP2833x_PieCtrl.h
@@ -0,0 +1,153 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006 13:52:24 $
+//###########################################################################
+//
+// FILE: DSP2833x_PieCtrl.h
+//
+// TITLE: DSP2833x Device PIE Control Register Definitions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+
+#ifndef DSP2833x_PIE_CTRL_H
+#define DSP2833x_PIE_CTRL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//---------------------------------------------------------------------------
+// PIE Control Register Bit Definitions:
+//
+// PIECTRL: Register bit definitions:
+struct PIECTRL_BITS { // bits description
+ Uint16 ENPIE:1; // 0 Enable PIE block
+ Uint16 PIEVECT:15; // 15:1 Fetched vector address
+};
+
+union PIECTRL_REG {
+ Uint16 all;
+ struct PIECTRL_BITS bit;
+};
+
+// PIEIER: Register bit definitions:
+struct PIEIER_BITS { // bits description
+ Uint16 INTx1:1; // 0 INTx.1
+ Uint16 INTx2:1; // 1 INTx.2
+ Uint16 INTx3:1; // 2 INTx.3
+ Uint16 INTx4:1; // 3 INTx.4
+ Uint16 INTx5:1; // 4 INTx.5
+ Uint16 INTx6:1; // 5 INTx.6
+ Uint16 INTx7:1; // 6 INTx.7
+ Uint16 INTx8:1; // 7 INTx.8
+ Uint16 rsvd:8; // 15:8 reserved
+};
+
+union PIEIER_REG {
+ Uint16 all;
+ struct PIEIER_BITS bit;
+};
+
+// PIEIFR: Register bit definitions:
+struct PIEIFR_BITS { // bits description
+ Uint16 INTx1:1; // 0 INTx.1
+ Uint16 INTx2:1; // 1 INTx.2
+ Uint16 INTx3:1; // 2 INTx.3
+ Uint16 INTx4:1; // 3 INTx.4
+ Uint16 INTx5:1; // 4 INTx.5
+ Uint16 INTx6:1; // 5 INTx.6
+ Uint16 INTx7:1; // 6 INTx.7
+ Uint16 INTx8:1; // 7 INTx.8
+ Uint16 rsvd:8; // 15:8 reserved
+};
+
+union PIEIFR_REG {
+ Uint16 all;
+ struct PIEIFR_BITS bit;
+};
+
+// PIEACK: Register bit definitions:
+struct PIEACK_BITS { // bits description
+ Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1
+ Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2
+ Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3
+ Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4
+ Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5
+ Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6
+ Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7
+ Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8
+ Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9
+ Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10
+ Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11
+ Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12
+ Uint16 rsvd:4; // 15:12 reserved
+};
+
+union PIEACK_REG {
+ Uint16 all;
+ struct PIEACK_BITS bit;
+};
+
+//---------------------------------------------------------------------------
+// PIE Control Register File:
+//
+struct PIE_CTRL_REGS {
+ union PIECTRL_REG PIECTRL; // PIE control register
+ union PIEACK_REG PIEACK; // PIE acknowledge
+ union PIEIER_REG PIEIER1; // PIE int1 IER register
+ union PIEIFR_REG PIEIFR1; // PIE int1 IFR register
+ union PIEIER_REG PIEIER2; // PIE INT2 IER register
+ union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register
+ union PIEIER_REG PIEIER3; // PIE INT3 IER register
+ union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register
+ union PIEIER_REG PIEIER4; // PIE INT4 IER register
+ union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register
+ union PIEIER_REG PIEIER5; // PIE INT5 IER register
+ union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register
+ union PIEIER_REG PIEIER6; // PIE INT6 IER register
+ union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register
+ union PIEIER_REG PIEIER7; // PIE INT7 IER register
+ union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register
+ union PIEIER_REG PIEIER8; // PIE INT8 IER register
+ union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register
+ union PIEIER_REG PIEIER9; // PIE INT9 IER register
+ union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register
+ union PIEIER_REG PIEIER10; // PIE int10 IER register
+ union PIEIFR_REG PIEIFR10; // PIE int10 IFR register
+ union PIEIER_REG PIEIER11; // PIE int11 IER register
+ union PIEIFR_REG PIEIFR11; // PIE int11 IFR register
+ union PIEIER_REG PIEIER12; // PIE int12 IER register
+ union PIEIFR_REG PIEIFR12; // PIE int12 IFR register
+};
+
+#define PIEACK_GROUP1 0x0001
+#define PIEACK_GROUP2 0x0002
+#define PIEACK_GROUP3 0x0004
+#define PIEACK_GROUP4 0x0008
+#define PIEACK_GROUP5 0x0010
+#define PIEACK_GROUP6 0x0020
+#define PIEACK_GROUP7 0x0040
+#define PIEACK_GROUP8 0x0080
+#define PIEACK_GROUP9 0x0100
+#define PIEACK_GROUP10 0x0200
+#define PIEACK_GROUP11 0x0400
+#define PIEACK_GROUP12 0x0800
+
+//---------------------------------------------------------------------------
+// PIE Control Registers External References & Function Declarations:
+//
+extern volatile struct PIE_CTRL_REGS PieCtrlRegs;
+
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_PIE_CTRL_H definition
+
+//===========================================================================
+// End of file.
+//===========================================================================
diff --git a/v120/DSP2833x_headers/include/DSP2833x_PieVect.h b/v120/DSP2833x_headers/include/DSP2833x_PieVect.h
new file mode 100644
index 0000000..acddab7
--- /dev/null
+++ b/v120/DSP2833x_headers/include/DSP2833x_PieVect.h
@@ -0,0 +1,208 @@
+// TI File $Revision: /main/2 $
+// Checkin $Date: March 16, 2007 09:00:21 $
+//###########################################################################
+//
+// FILE: DSP2833x_PieVect.h
+//
+// TITLE: DSP2833x Devices PIE Vector Table Definitions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#ifndef DSP2833x_PIE_VECT_H
+#define DSP2833x_PIE_VECT_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//---------------------------------------------------------------------------
+// PIE Interrupt Vector Table Definition:
+//
+// Create a user type called PINT (pointer to interrupt):
+
+typedef interrupt void(*PINT)(void);
+
+// Define Vector Table:
+struct PIE_VECT_TABLE {
+
+// Reset is never fetched from this table.
+// It will always be fetched from 0x3FFFC0 in
+// boot ROM
+
+ PINT PIE1_RESERVED;
+ PINT PIE2_RESERVED;
+ PINT PIE3_RESERVED;
+ PINT PIE4_RESERVED;
+ PINT PIE5_RESERVED;
+ PINT PIE6_RESERVED;
+ PINT PIE7_RESERVED;
+ PINT PIE8_RESERVED;
+ PINT PIE9_RESERVED;
+ PINT PIE10_RESERVED;
+ PINT PIE11_RESERVED;
+ PINT PIE12_RESERVED;
+ PINT PIE13_RESERVED;
+
+// Non-Peripheral Interrupts:
+ PINT XINT13; // XINT13 / CPU-Timer1
+ PINT TINT2; // CPU-Timer2
+ PINT DATALOG; // Datalogging interrupt
+ PINT RTOSINT; // RTOS interrupt
+ PINT EMUINT; // Emulation interrupt
+ PINT XNMI; // Non-maskable interrupt
+ PINT ILLEGAL; // Illegal operation TRAP
+ PINT USER1; // User Defined trap 1
+ PINT USER2; // User Defined trap 2
+ PINT USER3; // User Defined trap 3
+ PINT USER4; // User Defined trap 4
+ PINT USER5; // User Defined trap 5
+ PINT USER6; // User Defined trap 6
+ PINT USER7; // User Defined trap 7
+ PINT USER8; // User Defined trap 8
+ PINT USER9; // User Defined trap 9
+ PINT USER10; // User Defined trap 10
+ PINT USER11; // User Defined trap 11
+ PINT USER12; // User Defined trap 12
+
+// Group 1 PIE Peripheral Vectors:
+ PINT SEQ1INT;
+ PINT SEQ2INT;
+ PINT rsvd1_3;
+ PINT XINT1;
+ PINT XINT2;
+ PINT ADCINT; // ADC
+ PINT TINT0; // Timer 0
+ PINT WAKEINT; // WD
+
+// Group 2 PIE Peripheral Vectors:
+ PINT EPWM1_TZINT; // EPWM-1
+ PINT EPWM2_TZINT; // EPWM-2
+ PINT EPWM3_TZINT; // EPWM-3
+ PINT EPWM4_TZINT; // EPWM-4
+ PINT EPWM5_TZINT; // EPWM-5
+ PINT EPWM6_TZINT; // EPWM-6
+ PINT rsvd2_7;
+ PINT rsvd2_8;
+
+// Group 3 PIE Peripheral Vectors:
+ PINT EPWM1_INT; // EPWM-1
+ PINT EPWM2_INT; // EPWM-2
+ PINT EPWM3_INT; // EPWM-3
+ PINT EPWM4_INT; // EPWM-4
+ PINT EPWM5_INT; // EPWM-5
+ PINT EPWM6_INT; // EPWM-6
+ PINT rsvd3_7;
+ PINT rsvd3_8;
+
+// Group 4 PIE Peripheral Vectors:
+ PINT ECAP1_INT; // ECAP-1
+ PINT ECAP2_INT; // ECAP-2
+ PINT ECAP3_INT; // ECAP-3
+ PINT ECAP4_INT; // ECAP-4
+ PINT ECAP5_INT; // ECAP-5
+ PINT ECAP6_INT; // ECAP-6
+ PINT rsvd4_7;
+ PINT rsvd4_8;
+
+// Group 5 PIE Peripheral Vectors:
+ PINT EQEP1_INT; // EQEP-1
+ PINT EQEP2_INT; // EQEP-2
+ PINT rsvd5_3;
+ PINT rsvd5_4;
+ PINT rsvd5_5;
+ PINT rsvd5_6;
+ PINT rsvd5_7;
+ PINT rsvd5_8;
+
+// Group 6 PIE Peripheral Vectors:
+ PINT SPIRXINTA; // SPI-A
+ PINT SPITXINTA; // SPI-A
+ PINT MRINTB; // McBSP-B
+ PINT MXINTB; // McBSP-B
+ PINT MRINTA; // McBSP-A
+ PINT MXINTA; // McBSP-A
+ PINT rsvd6_7;
+ PINT rsvd6_8;
+
+// Group 7 PIE Peripheral Vectors:
+ PINT DINTCH1; // DMA
+ PINT DINTCH2; // DMA
+ PINT DINTCH3; // DMA
+ PINT DINTCH4; // DMA
+ PINT DINTCH5; // DMA
+ PINT DINTCH6; // DMA
+ PINT rsvd7_7;
+ PINT rsvd7_8;
+
+// Group 8 PIE Peripheral Vectors:
+ PINT I2CINT1A; // I2C-A
+ PINT I2CINT2A; // I2C-A
+ PINT rsvd8_3;
+ PINT rsvd8_4;
+ PINT SCIRXINTC; // SCI-C
+ PINT SCITXINTC; // SCI-C
+ PINT rsvd8_7;
+ PINT rsvd8_8;
+
+// Group 9 PIE Peripheral Vectors:
+ PINT SCIRXINTA; // SCI-A
+ PINT SCITXINTA; // SCI-A
+ PINT SCIRXINTB; // SCI-B
+ PINT SCITXINTB; // SCI-B
+ PINT ECAN0INTA; // eCAN-A
+ PINT ECAN1INTA; // eCAN-A
+ PINT ECAN0INTB; // eCAN-B
+ PINT ECAN1INTB; // eCAN-B
+
+// Group 10 PIE Peripheral Vectors:
+ PINT rsvd10_1;
+ PINT rsvd10_2;
+ PINT rsvd10_3;
+ PINT rsvd10_4;
+ PINT rsvd10_5;
+ PINT rsvd10_6;
+ PINT rsvd10_7;
+ PINT rsvd10_8;
+
+// Group 11 PIE Peripheral Vectors:
+ PINT rsvd11_1;
+ PINT rsvd11_2;
+ PINT rsvd11_3;
+ PINT rsvd11_4;
+ PINT rsvd11_5;
+ PINT rsvd11_6;
+ PINT rsvd11_7;
+ PINT rsvd11_8;
+
+// Group 12 PIE Peripheral Vectors:
+ PINT XINT3; // External interrupt
+ PINT XINT4;
+ PINT XINT5;
+ PINT XINT6;
+ PINT XINT7;
+ PINT rsvd12_6;
+ PINT LVF; // Latched overflow
+ PINT LUF; // Latched underflow
+};
+
+//---------------------------------------------------------------------------
+// PIE Interrupt Vector Table External References & Function Declarations:
+//
+extern struct PIE_VECT_TABLE PieVectTable;
+
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_PIE_VECT_H definition
+
+//===========================================================================
+// End of file.
+//===========================================================================
+
diff --git a/v120/DSP2833x_headers/include/DSP2833x_Sci.h b/v120/DSP2833x_headers/include/DSP2833x_Sci.h
new file mode 100644
index 0000000..7c17822
--- /dev/null
+++ b/v120/DSP2833x_headers/include/DSP2833x_Sci.h
@@ -0,0 +1,235 @@
+// TI File $Revision: /main/2 $
+// Checkin $Date: March 1, 2007 15:57:02 $
+//###########################################################################
+//
+// FILE: DSP2833x_Sci.h
+//
+// TITLE: DSP2833x Device SCI Register Definitions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#ifndef DSP2833x_SCI_H
+#define DSP2833x_SCI_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//---------------------------------------------------------------------------
+// SCI Individual Register Bit Definitions
+
+//----------------------------------------------------------
+// SCICCR communication control register bit definitions:
+//
+
+struct SCICCR_BITS { // bit description
+ Uint16 SCICHAR:3; // 2:0 Character length control
+ Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control
+ Uint16 LOOPBKENA:1; // 4 Loop Back enable
+ Uint16 PARITYENA:1; // 5 Parity enable
+ Uint16 PARITY:1; // 6 Even or Odd Parity
+ Uint16 STOPBITS:1; // 7 Number of Stop Bits
+ Uint16 rsvd1:8; // 15:8 reserved
+};
+
+
+union SCICCR_REG {
+ Uint16 all;
+ struct SCICCR_BITS bit;
+};
+
+//-------------------------------------------
+// SCICTL1 control register 1 bit definitions:
+//
+
+struct SCICTL1_BITS { // bit description
+ Uint16 RXENA:1; // 0 SCI receiver enable
+ Uint16 TXENA:1; // 1 SCI transmitter enable
+ Uint16 SLEEP:1; // 2 SCI sleep
+ Uint16 TXWAKE:1; // 3 Transmitter wakeup method
+ Uint16 rsvd:1; // 4 reserved
+ Uint16 SWRESET:1; // 5 Software reset
+ Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable
+ Uint16 rsvd1:9; // 15:7 reserved
+
+};
+
+union SCICTL1_REG {
+ Uint16 all;
+ struct SCICTL1_BITS bit;
+};
+
+//---------------------------------------------
+// SCICTL2 control register 2 bit definitions:
+//
+
+struct SCICTL2_BITS { // bit description
+ Uint16 TXINTENA:1; // 0 Transmit interrupt enable
+ Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable
+ Uint16 rsvd:4; // 5:2 reserved
+ Uint16 TXEMPTY:1; // 6 Transmitter empty flag
+ Uint16 TXRDY:1; // 7 Transmitter ready flag
+ Uint16 rsvd1:8; // 15:8 reserved
+
+};
+
+union SCICTL2_REG {
+ Uint16 all;
+ struct SCICTL2_BITS bit;
+};
+
+//---------------------------------------------------
+// SCIRXST Receiver status register bit definitions:
+//
+
+struct SCIRXST_BITS { // bit description
+ Uint16 rsvd:1; // 0 reserved
+ Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag
+ Uint16 PE:1; // 2 Parity error flag
+ Uint16 OE:1; // 3 Overrun error flag
+ Uint16 FE:1; // 4 Framing error flag
+ Uint16 BRKDT:1; // 5 Break-detect flag
+ Uint16 RXRDY:1; // 6 Receiver ready flag
+ Uint16 RXERROR:1; // 7 Receiver error flag
+
+};
+
+union SCIRXST_REG {
+ Uint16 all;
+ struct SCIRXST_BITS bit;
+};
+
+//----------------------------------------------------
+// SCIRXBUF Receiver Data Buffer with FIFO bit definitions:
+//
+
+struct SCIRXBUF_BITS { // bits description
+ Uint16 RXDT:8; // 7:0 Receive word
+ Uint16 rsvd:6; // 13:8 reserved
+ Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode
+ Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode
+};
+
+union SCIRXBUF_REG {
+ Uint16 all;
+ struct SCIRXBUF_BITS bit;
+};
+
+//--------------------------------------------------
+// SCIPRI Priority control register bit definitions:
+//
+//
+
+struct SCIPRI_BITS { // bit description
+ Uint16 rsvd:3; // 2:0 reserved
+ Uint16 FREE:1; // 3 Free emulation suspend mode
+ Uint16 SOFT:1; // 4 Soft emulation suspend mode
+ Uint16 rsvd1:3; // 7:5 reserved
+};
+
+union SCIPRI_REG {
+ Uint16 all;
+ struct SCIPRI_BITS bit;
+};
+
+//-------------------------------------------------
+// SCI FIFO Transmit register bit definitions:
+//
+//
+
+struct SCIFFTX_BITS { // bit description
+ Uint16 TXFFIL:5; // 4:0 Interrupt level
+ Uint16 TXFFIENA:1; // 5 Interrupt enable
+ Uint16 TXFFINTCLR:1; // 6 Clear INT flag
+ Uint16 TXFFINT:1; // 7 INT flag
+ Uint16 TXFFST:5; // 12:8 FIFO status
+ Uint16 TXFIFOXRESET:1; // 13 FIFO reset
+ Uint16 SCIFFENA:1; // 14 Enhancement enable
+ Uint16 SCIRST:1; // 15 SCI reset rx/tx channels
+
+};
+
+union SCIFFTX_REG {
+ Uint16 all;
+ struct SCIFFTX_BITS bit;
+};
+
+//------------------------------------------------
+// SCI FIFO recieve register bit definitions:
+//
+//
+
+struct SCIFFRX_BITS { // bits description
+ Uint16 RXFFIL:5; // 4:0 Interrupt level
+ Uint16 RXFFIENA:1; // 5 Interrupt enable
+ Uint16 RXFFINTCLR:1; // 6 Clear INT flag
+ Uint16 RXFFINT:1; // 7 INT flag
+ Uint16 RXFFST:5; // 12:8 FIFO status
+ Uint16 RXFIFORESET:1; // 13 FIFO reset
+ Uint16 RXFFOVRCLR:1; // 14 Clear overflow
+ Uint16 RXFFOVF:1; // 15 FIFO overflow
+
+};
+
+union SCIFFRX_REG {
+ Uint16 all;
+ struct SCIFFRX_BITS bit;
+};
+
+// SCI FIFO control register bit definitions:
+struct SCIFFCT_BITS { // bits description
+ Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay
+ Uint16 rsvd:5; // 12:8 reserved
+ Uint16 CDC:1; // 13 Auto baud mode enable
+ Uint16 ABDCLR:1; // 14 Auto baud clear
+ Uint16 ABD:1; // 15 Auto baud detect
+};
+
+union SCIFFCT_REG {
+ Uint16 all;
+ struct SCIFFCT_BITS bit;
+};
+
+//---------------------------------------------------------------------------
+// SCI Register File:
+//
+struct SCI_REGS {
+ union SCICCR_REG SCICCR; // Communications control register
+ union SCICTL1_REG SCICTL1; // Control register 1
+ Uint16 SCIHBAUD; // Baud rate (high) register
+ Uint16 SCILBAUD; // Baud rate (low) register
+ union SCICTL2_REG SCICTL2; // Control register 2
+ union SCIRXST_REG SCIRXST; // Recieve status register
+ Uint16 SCIRXEMU; // Recieve emulation buffer register
+ union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer
+ Uint16 rsvd1; // reserved
+ Uint16 SCITXBUF; // Transmit data buffer
+ union SCIFFTX_REG SCIFFTX; // FIFO transmit register
+ union SCIFFRX_REG SCIFFRX; // FIFO recieve register
+ union SCIFFCT_REG SCIFFCT; // FIFO control register
+ Uint16 rsvd2; // reserved
+ Uint16 rsvd3; // reserved
+ union SCIPRI_REG SCIPRI; // FIFO Priority control
+};
+
+//---------------------------------------------------------------------------
+// SCI External References & Function Declarations:
+//
+extern volatile struct SCI_REGS SciaRegs;
+extern volatile struct SCI_REGS ScibRegs;
+extern volatile struct SCI_REGS ScicRegs;
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_SCI_H definition
+
+//===========================================================================
+// End of file.
+//===========================================================================
+
diff --git a/v120/DSP2833x_headers/include/DSP2833x_Spi.h b/v120/DSP2833x_headers/include/DSP2833x_Spi.h
new file mode 100644
index 0000000..1325c59
--- /dev/null
+++ b/v120/DSP2833x_headers/include/DSP2833x_Spi.h
@@ -0,0 +1,183 @@
+// TI File $Revision: /main/3 $
+// Checkin $Date: April 17, 2008 11:08:27 $
+//###########################################################################
+//
+// FILE: DSP2833x_Spi.h
+//
+// TITLE: DSP2833x Device SPI Register Definitions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#ifndef DSP2833x_SPI_H
+#define DSP2833x_SPI_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//---------------------------------------------------------------------------
+// SPI Individual Register Bit Definitions:
+//
+// SPI FIFO Transmit register bit definitions:
+struct SPIFFTX_BITS { // bit description
+ Uint16 TXFFIL:5; // 4:0 Interrupt level
+ Uint16 TXFFIENA:1; // 5 Interrupt enable
+ Uint16 TXFFINTCLR:1; // 6 Clear INT flag
+ Uint16 TXFFINT:1; // 7 INT flag
+ Uint16 TXFFST:5; // 12:8 FIFO status
+ Uint16 TXFIFO:1; // 13 FIFO reset
+ Uint16 SPIFFENA:1; // 14 Enhancement enable
+ Uint16 SPIRST:1; // 15 Reset SPI
+};
+
+union SPIFFTX_REG {
+ Uint16 all;
+ struct SPIFFTX_BITS bit;
+};
+
+//--------------------------------------------
+// SPI FIFO recieve register bit definitions:
+//
+//
+struct SPIFFRX_BITS { // bits description
+ Uint16 RXFFIL:5; // 4:0 Interrupt level
+ Uint16 RXFFIENA:1; // 5 Interrupt enable
+ Uint16 RXFFINTCLR:1; // 6 Clear INT flag
+ Uint16 RXFFINT:1; // 7 INT flag
+ Uint16 RXFFST:5; // 12:8 FIFO status
+ Uint16 RXFIFORESET:1; // 13 FIFO reset
+ Uint16 RXFFOVFCLR:1; // 14 Clear overflow
+ Uint16 RXFFOVF:1; // 15 FIFO overflow
+
+};
+
+union SPIFFRX_REG {
+ Uint16 all;
+ struct SPIFFRX_BITS bit;
+};
+
+//--------------------------------------------
+// SPI FIFO control register bit definitions:
+//
+//
+struct SPIFFCT_BITS { // bits description
+ Uint16 TXDLY:8; // 7:0 FIFO transmit delay
+ Uint16 rsvd:8; // 15:8 reserved
+};
+
+union SPIFFCT_REG {
+ Uint16 all;
+ struct SPIFFCT_BITS bit;
+};
+
+//---------------------------------------------
+// SPI configuration register bit definitions:
+//
+//
+struct SPICCR_BITS { // bits description
+ Uint16 SPICHAR:4; // 3:0 Character length control
+ Uint16 SPILBK:1; // 4 Loop-back enable/disable
+ Uint16 rsvd1:1; // 5 reserved
+ Uint16 CLKPOLARITY:1; // 6 Clock polarity
+ Uint16 SPISWRESET:1; // 7 SPI SW Reset
+ Uint16 rsvd2:8; // 15:8 reserved
+};
+
+union SPICCR_REG {
+ Uint16 all;
+ struct SPICCR_BITS bit;
+};
+
+//-------------------------------------------------
+// SPI operation control register bit definitions:
+//
+//
+struct SPICTL_BITS { // bits description
+ Uint16 SPIINTENA:1; // 0 Interrupt enable
+ Uint16 TALK:1; // 1 Master/Slave transmit enable
+ Uint16 MASTER_SLAVE:1; // 2 Network control mode
+ Uint16 CLK_PHASE:1; // 3 Clock phase select
+ Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable
+ Uint16 rsvd:11; // 15:5 reserved
+};
+
+union SPICTL_REG {
+ Uint16 all;
+ struct SPICTL_BITS bit;
+};
+
+//--------------------------------------
+// SPI status register bit definitions:
+//
+//
+struct SPISTS_BITS { // bits description
+ Uint16 rsvd1:5; // 4:0 reserved
+ Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag
+ Uint16 INT_FLAG:1; // 6 SPI interrupt flag
+ Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag
+ Uint16 rsvd2:8; // 15:8 reserved
+};
+
+union SPISTS_REG {
+ Uint16 all;
+ struct SPISTS_BITS bit;
+};
+
+//------------------------------------------------
+// SPI priority control register bit definitions:
+//
+//
+struct SPIPRI_BITS { // bits description
+ Uint16 rsvd1:4; // 3:0 reserved
+ Uint16 FREE:1; // 4 Free emulation mode control
+ Uint16 SOFT:1; // 5 Soft emulation mode control
+ Uint16 rsvd2:1; // 6 reserved
+ Uint16 rsvd3:9; // 15:7 reserved
+};
+
+union SPIPRI_REG {
+ Uint16 all;
+ struct SPIPRI_BITS bit;
+};
+
+//---------------------------------------------------------------------------
+// SPI Register File:
+//
+struct SPI_REGS {
+ union SPICCR_REG SPICCR; // Configuration register
+ union SPICTL_REG SPICTL; // Operation control register
+ union SPISTS_REG SPISTS; // Status register
+ Uint16 rsvd1; // reserved
+ Uint16 SPIBRR; // Baud Rate
+ Uint16 rsvd2; // reserved
+ Uint16 SPIRXEMU; // Emulation buffer
+ Uint16 SPIRXBUF; // Serial input buffer
+ Uint16 SPITXBUF; // Serial output buffer
+ Uint16 SPIDAT; // Serial data
+ union SPIFFTX_REG SPIFFTX; // FIFO transmit register
+ union SPIFFRX_REG SPIFFRX; // FIFO recieve register
+ union SPIFFCT_REG SPIFFCT; // FIFO control register
+ Uint16 rsvd3[2]; // reserved
+ union SPIPRI_REG SPIPRI; // FIFO Priority control
+};
+
+//---------------------------------------------------------------------------
+// SPI External References & Function Declarations:
+//
+extern volatile struct SPI_REGS SpiaRegs;
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_SPI_H definition
+
+//===========================================================================
+// End of file.
+//===========================================================================
+
diff --git a/v120/DSP2833x_headers/include/DSP2833x_SysCtrl.h b/v120/DSP2833x_headers/include/DSP2833x_SysCtrl.h
new file mode 100644
index 0000000..f8bc343
--- /dev/null
+++ b/v120/DSP2833x_headers/include/DSP2833x_SysCtrl.h
@@ -0,0 +1,383 @@
+// TI File $Revision: /main/5 $
+// Checkin $Date: May 12, 2008 09:34:58 $
+//###########################################################################
+//
+// FILE: DSP2833x_SysCtrl.h
+//
+// TITLE: DSP2833x Device System Control Register Definitions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#ifndef DSP2833x_SYS_CTRL_H
+#define DSP2833x_SYS_CTRL_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//---------------------------------------------------------------------------
+// System Control Individual Register Bit Definitions:
+//
+
+
+// PLL Status Register
+struct PLLSTS_BITS { // bits description
+ Uint16 PLLLOCKS:1; // 0 PLL lock status
+ Uint16 rsvd1:1; // 1 reserved
+ Uint16 PLLOFF:1; // 2 PLL off bit
+ Uint16 MCLKSTS:1; // 3 Missing clock status bit
+ Uint16 MCLKCLR:1; // 4 Missing clock clear bit
+ Uint16 OSCOFF:1; // 5 Oscillator clock off
+ Uint16 MCLKOFF:1; // 6 Missing clock detect
+ Uint16 DIVSEL:2; // 7 Divide Select
+ Uint16 rsvd2:7; // 15:7 reserved
+};
+
+union PLLSTS_REG {
+ Uint16 all;
+ struct PLLSTS_BITS bit;
+};
+
+// High speed peripheral clock register bit definitions:
+struct HISPCP_BITS { // bits description
+ Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT
+ Uint16 rsvd1:13; // 15:3 reserved
+};
+
+union HISPCP_REG {
+ Uint16 all;
+ struct HISPCP_BITS bit;
+};
+
+// Low speed peripheral clock register bit definitions:
+struct LOSPCP_BITS { // bits description
+ Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT
+ Uint16 rsvd1:13; // 15:3 reserved
+};
+
+union LOSPCP_REG {
+ Uint16 all;
+ struct LOSPCP_BITS bit;
+};
+
+// Peripheral clock control register 0 bit definitions:
+struct PCLKCR0_BITS { // bits description
+ Uint16 rsvd1:2; // 1:0 reserved
+ Uint16 TBCLKSYNC:1; // 2 EWPM Module TBCLK enable/sync
+ Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC
+ Uint16 I2CAENCLK:1; // 4 Enable SYSCLKOUT to I2C-A
+ Uint16 SCICENCLK:1; // 5 Enalbe low speed clk to SCI-C
+ Uint16 rsvd2:2; // 7:6 reserved
+ Uint16 SPIAENCLK:1; // 8 Enable low speed clk to SPI-A
+ Uint16 rsvd3:1; // 9 reserved
+ Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A
+ Uint16 SCIBENCLK:1; // 11 Enable low speed clk to SCI-B
+ Uint16 MCBSPAENCLK:1; // 12 Enable low speed clk to McBSP-A
+ Uint16 MCBSPBENCLK:1; // 13 Enable low speed clk to McBSP-B
+ Uint16 ECANAENCLK:1; // 14 Enable system clk to eCAN-A
+ Uint16 ECANBENCLK:1; // 15 Enable system clk to eCAN-B
+};
+
+union PCLKCR0_REG {
+ Uint16 all;
+ struct PCLKCR0_BITS bit;
+};
+
+// Peripheral clock control register 1 bit definitions:
+struct PCLKCR1_BITS { // bits description
+ Uint16 EPWM1ENCLK:1; // 0 Enable SYSCLKOUT to EPWM1
+ Uint16 EPWM2ENCLK:1; // 1 Enable SYSCLKOUT to EPWM2
+ Uint16 EPWM3ENCLK:1; // 2 Enable SYSCLKOUT to EPWM3
+ Uint16 EPWM4ENCLK:1; // 3 Enable SYSCLKOUT to EPWM4
+ Uint16 EPWM5ENCLK:1; // 4 Enable SYSCLKOUT to EPWM5
+ Uint16 EPWM6ENCLK:1; // 5 Enable SYSCLKOUT to EPWM6
+ Uint16 rsvd1:2; // 7:6 reserved
+ Uint16 ECAP1ENCLK:1; // 8 Enable SYSCLKOUT to ECAP1
+ Uint16 ECAP2ENCLK:1; // 9 Enable SYSCLKOUT to ECAP2
+ Uint16 ECAP3ENCLK:1; // 10 Enable SYSCLKOUT to ECAP3
+ Uint16 ECAP4ENCLK:1; // 11 Enable SYSCLKOUT to ECAP4
+ Uint16 ECAP5ENCLK:1; // 12 Enable SYSCLKOUT to ECAP5
+ Uint16 ECAP6ENCLK:1; // 13 Enable SYSCLKOUT to ECAP6
+ Uint16 EQEP1ENCLK:1; // 14 Enable SYSCLKOUT to EQEP1
+ Uint16 EQEP2ENCLK:1; // 15 Enable SYSCLKOUT to EQEP2
+};
+
+union PCLKCR1_REG {
+ Uint16 all;
+ struct PCLKCR1_BITS bit;
+};
+
+
+// Peripheral clock control register 2 bit definitions:
+struct PCLKCR3_BITS { // bits description
+ Uint16 rsvd1:8; // 7:0 reserved
+ Uint16 CPUTIMER0ENCLK:1; // 8 Enable SYSCLKOUT to CPU-Timer 0
+ Uint16 CPUTIMER1ENCLK:1; // 9 Enable SYSCLKOUT to CPU-Timer 1
+ Uint16 CPUTIMER2ENCLK:1; // 10 Enable SYSCLKOUT to CPU-Timer 2
+ Uint16 DMAENCLK:1; // 11 Enable the DMA clock
+ Uint16 XINTFENCLK:1; // 12 Enable SYSCLKOUT to XINTF
+ Uint16 GPIOINENCLK:1; // Enable GPIO input clock
+ Uint16 rsvd2:2; // 15:14 reserved
+};
+
+union PCLKCR3_REG {
+ Uint16 all;
+ struct PCLKCR3_BITS bit;
+};
+
+
+
+// PLL control register bit definitions:
+struct PLLCR_BITS { // bits description
+ Uint16 DIV:4; // 3:0 Set clock ratio for the PLL
+ Uint16 rsvd1:12; // 15:4 reserved
+};
+
+union PLLCR_REG {
+ Uint16 all;
+ struct PLLCR_BITS bit;
+};
+
+// Low Power Mode 0 control register bit definitions:
+struct LPMCR0_BITS { // bits description
+ Uint16 LPM:2; // 1:0 Set the low power mode
+ Uint16 QUALSTDBY:6; // 7:2 Qualification
+ Uint16 rsvd1:7; // 14:8 reserved
+ Uint16 WDINTE:1; // 15 Enables WD to wake the device from STANDBY
+};
+
+union LPMCR0_REG {
+ Uint16 all;
+ struct LPMCR0_BITS bit;
+};
+
+// Dual-mapping configuration register bit definitions:
+struct MAPCNF_BITS { // bits description
+ Uint16 MAPEPWM:1; // 0 EPWM dual-map enable
+ Uint16 rsvd1:15; // 15:1 reserved
+};
+
+union MAPCNF_REG {
+ Uint16 all;
+ struct MAPCNF_BITS bit;
+};
+
+//---------------------------------------------------------------------------
+// System Control Register File:
+//
+struct SYS_CTRL_REGS {
+ Uint16 rsvd1; // 0
+ union PLLSTS_REG PLLSTS; // 1
+ Uint16 rsvd2[8]; // 2-9
+ union HISPCP_REG HISPCP; // 10: High-speed peripheral clock pre-scaler
+ union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler
+ union PCLKCR0_REG PCLKCR0; // 12: Peripheral clock control register
+ union PCLKCR1_REG PCLKCR1; // 13: Peripheral clock control register
+ union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0
+ Uint16 rsvd3; // 15: reserved
+ union PCLKCR3_REG PCLKCR3; // 16: Peripheral clock control register
+ union PLLCR_REG PLLCR; // 17: PLL control register
+ // No bit definitions are defined for SCSR because
+ // a read-modify-write instruction can clear the WDOVERRIDE bit
+ Uint16 SCSR; // 18: System control and status register
+ Uint16 WDCNTR; // 19: WD counter register
+ Uint16 rsvd4; // 20
+ Uint16 WDKEY; // 21: WD reset key register
+ Uint16 rsvd5[3]; // 22-24
+ // No bit definitions are defined for WDCR because
+ // the proper value must be written to the WDCHK field
+ // whenever writing to this register.
+ Uint16 WDCR; // 25: WD timer control register
+ Uint16 rsvd6[4]; // 26-29
+ union MAPCNF_REG MAPCNF; // 30: Dual-mapping configuration register
+ Uint16 rsvd7[1]; // 31
+};
+
+
+/* --------------------------------------------------- */
+/* CSM Registers */
+/* */
+/* ----------------------------------------------------*/
+
+/* CSM Status & Control register bit definitions */
+struct CSMSCR_BITS { // bit description
+ Uint16 SECURE:1; // 0 Secure flag
+ Uint16 rsvd1:14; // 14-1 reserved
+ Uint16 FORCESEC:1; // 15 Force Secure control bit
+
+};
+
+/* Allow access to the bit fields or entire register */
+union CSMSCR_REG {
+ Uint16 all;
+ struct CSMSCR_BITS bit;
+};
+
+/* CSM Register File */
+struct CSM_REGS {
+ Uint16 KEY0; // KEY reg bits 15-0
+ Uint16 KEY1; // KEY reg bits 31-16
+ Uint16 KEY2; // KEY reg bits 47-32
+ Uint16 KEY3; // KEY reg bits 63-48
+ Uint16 KEY4; // KEY reg bits 79-64
+ Uint16 KEY5; // KEY reg bits 95-80
+ Uint16 KEY6; // KEY reg bits 111-96
+ Uint16 KEY7; // KEY reg bits 127-112
+ Uint16 rsvd1; // reserved
+ Uint16 rsvd2; // reserved
+ Uint16 rsvd3; // reserved
+ Uint16 rsvd4; // reserved
+ Uint16 rsvd5; // reserved
+ Uint16 rsvd6; // reserved
+ Uint16 rsvd7; // reserved
+ union CSMSCR_REG CSMSCR; // CSM Status & Control register
+};
+
+/* Password locations */
+struct CSM_PWL {
+ Uint16 PSWD0; // PSWD bits 15-0
+ Uint16 PSWD1; // PSWD bits 31-16
+ Uint16 PSWD2; // PSWD bits 47-32
+ Uint16 PSWD3; // PSWD bits 63-48
+ Uint16 PSWD4; // PSWD bits 79-64
+ Uint16 PSWD5; // PSWD bits 95-80
+ Uint16 PSWD6; // PSWD bits 111-96
+ Uint16 PSWD7; // PSWD bits 127-112
+};
+
+
+
+/* Flash Registers */
+
+#define FLASH_SLEEP 0x0000;
+#define FLASH_STANDBY 0x0001;
+#define FLASH_ACTIVE 0x0003;
+
+
+/* Flash Option Register bit definitions */
+struct FOPT_BITS { // bit description
+ Uint16 ENPIPE:1; // 0 Enable Pipeline Mode
+ Uint16 rsvd:15; // 1-15 reserved
+};
+
+/* Allow access to the bit fields or entire register */
+union FOPT_REG {
+ Uint16 all;
+ struct FOPT_BITS bit;
+};
+
+/* Flash Power Modes Register bit definitions */
+struct FPWR_BITS { // bit description
+ Uint16 PWR:2; // 0-1 Power Mode bits
+ Uint16 rsvd:14; // 2-15 reserved
+};
+
+/* Allow access to the bit fields or entire register */
+union FPWR_REG {
+ Uint16 all;
+ struct FPWR_BITS bit;
+};
+
+
+/* Flash Status Register bit definitions */
+struct FSTATUS_BITS { // bit description
+ Uint16 PWRS:2; // 0-1 Power Mode Status bits
+ Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits
+ Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits
+ Uint16 rsvd1:4; // 4-7 reserved
+ Uint16 V3STAT:1; // 8 VDD3V Status Latch bit
+ Uint16 rsvd2:7; // 9-15 reserved
+};
+
+/* Allow access to the bit fields or entire register */
+union FSTATUS_REG {
+ Uint16 all;
+ struct FSTATUS_BITS bit;
+};
+
+/* Flash Sleep to Standby Wait Counter Register bit definitions */
+struct FSTDBYWAIT_BITS { // bit description
+ Uint16 STDBYWAIT:9; // 0-8 Bank/Pump Sleep to Standby Wait Count bits
+ Uint16 rsvd:7; // 9-15 reserved
+};
+
+/* Allow access to the bit fields or entire register */
+union FSTDBYWAIT_REG {
+ Uint16 all;
+ struct FSTDBYWAIT_BITS bit;
+};
+
+/* Flash Standby to Active Wait Counter Register bit definitions */
+struct FACTIVEWAIT_BITS { // bit description
+ Uint16 ACTIVEWAIT:9; // 0-8 Bank/Pump Standby to Active Wait Count bits
+ Uint16 rsvd:7; // 9-15 reserved
+};
+
+/* Allow access to the bit fields or entire register */
+union FACTIVEWAIT_REG {
+ Uint16 all;
+ struct FACTIVEWAIT_BITS bit;
+};
+
+/* Bank Read Access Wait State Register bit definitions */
+struct FBANKWAIT_BITS { // bit description
+ Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits
+ Uint16 rsvd1:4; // 4-7 reserved
+ Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits
+ Uint16 rsvd2:4; // 12-15 reserved
+};
+
+/* Allow access to the bit fields or entire register */
+union FBANKWAIT_REG {
+ Uint16 all;
+ struct FBANKWAIT_BITS bit;
+};
+
+/* OTP Read Access Wait State Register bit definitions */
+struct FOTPWAIT_BITS { // bit description
+ Uint16 OTPWAIT:5; // 0-4 OTP Read Wait State bits
+ Uint16 rsvd:11; // 5-15 reserved
+};
+
+/* Allow access to the bit fields or entire register */
+union FOTPWAIT_REG {
+ Uint16 all;
+ struct FOTPWAIT_BITS bit;
+};
+
+
+struct FLASH_REGS {
+ union FOPT_REG FOPT; // Option Register
+ Uint16 rsvd1; // reserved
+ union FPWR_REG FPWR; // Power Modes Register
+ union FSTATUS_REG FSTATUS; // Status Register
+ union FSTDBYWAIT_REG FSTDBYWAIT; // Pump/Bank Sleep to Standby Wait State Register
+ union FACTIVEWAIT_REG FACTIVEWAIT; // Pump/Bank Standby to Active Wait State Register
+ union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register
+ union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register
+};
+
+//---------------------------------------------------------------------------
+// System Control External References & Function Declarations:
+//
+extern volatile struct SYS_CTRL_REGS SysCtrlRegs;
+extern volatile struct CSM_REGS CsmRegs;
+extern volatile struct CSM_PWL CsmPwl;
+extern volatile struct FLASH_REGS FlashRegs;
+
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_SYS_CTRL_H definition
+
+//===========================================================================
+// End of file.
+//===========================================================================
+
diff --git a/v120/DSP2833x_headers/include/DSP2833x_XIntrupt.h b/v120/DSP2833x_headers/include/DSP2833x_XIntrupt.h
new file mode 100644
index 0000000..6f860f6
--- /dev/null
+++ b/v120/DSP2833x_headers/include/DSP2833x_XIntrupt.h
@@ -0,0 +1,83 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006 13:52:39 $
+//###########################################################################
+//
+// FILE: DSP2833x_XIntrupt.h
+//
+// TITLE: DSP2833x Device External Interrupt Register Definitions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#ifndef DSP2833x_XINTRUPT_H
+#define DSP2833x_XINTRUPT_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//---------------------------------------------------------------------------
+
+struct XINTCR_BITS {
+ Uint16 ENABLE:1; // 0 enable/disable
+ Uint16 rsvd1:1; // 1 reserved
+ Uint16 POLARITY:2; // 3:2 pos/neg, both triggered
+ Uint16 rsvd2:12; //15:4 reserved
+};
+
+union XINTCR_REG {
+ Uint16 all;
+ struct XINTCR_BITS bit;
+};
+
+struct XNMICR_BITS {
+ Uint16 ENABLE:1; // 0 enable/disable
+ Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to int13
+ Uint16 POLARITY:2; // 3:2 pos/neg, or both triggered
+ Uint16 rsvd2:12; // 15:4 reserved
+};
+
+union XNMICR_REG {
+ Uint16 all;
+ struct XNMICR_BITS bit;
+};
+
+
+
+
+//---------------------------------------------------------------------------
+// External Interrupt Register File:
+//
+struct XINTRUPT_REGS {
+ union XINTCR_REG XINT1CR;
+ union XINTCR_REG XINT2CR;
+ union XINTCR_REG XINT3CR;
+ union XINTCR_REG XINT4CR;
+ union XINTCR_REG XINT5CR;
+ union XINTCR_REG XINT6CR;
+ union XINTCR_REG XINT7CR;
+ union XNMICR_REG XNMICR;
+ Uint16 XINT1CTR;
+ Uint16 XINT2CTR;
+ Uint16 rsvd[5];
+ Uint16 XNMICTR;
+};
+
+//---------------------------------------------------------------------------
+// External Interrupt References & Function Declarations:
+//
+extern volatile struct XINTRUPT_REGS XIntruptRegs;
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_XINTF_H definition
+
+//===========================================================================
+// End of file.
+//===========================================================================
+
diff --git a/v120/DSP2833x_headers/include/DSP2833x_Xintf.h b/v120/DSP2833x_headers/include/DSP2833x_Xintf.h
new file mode 100644
index 0000000..cb68744
--- /dev/null
+++ b/v120/DSP2833x_headers/include/DSP2833x_Xintf.h
@@ -0,0 +1,120 @@
+// TI File $Revision: /main/3 $
+// Checkin $Date: March 20, 2007 16:34:08 $
+//###########################################################################
+//
+// FILE: DSP2833x_Xintf.h
+//
+// TITLE: DSP2833x Device External Interface Register Definitions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#ifndef DSP2833x_XINTF_H
+#define DSP2833x_XINTF_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+// XINTF timing register bit definitions:
+struct XTIMING_BITS { // bits description
+ Uint16 XWRTRAIL:2; // 1:0 Write access trail timing
+ Uint16 XWRACTIVE:3; // 4:2 Write access active timing
+ Uint16 XWRLEAD:2; // 6:5 Write access lead timing
+ Uint16 XRDTRAIL:2; // 8:7 Read access trail timing
+ Uint16 XRDACTIVE:3; // 11:9 Read access active timing
+ Uint16 XRDLEAD:2; // 13:12 Read access lead timing
+ Uint16 USEREADY:1; // 14 Extend access using HW waitstates
+ Uint16 READYMODE:1; // 15 Ready mode
+ Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b
+ Uint16 rsvd1:4; // 21:18 reserved
+ Uint16 X2TIMING:1; // 22 Double lead/active/trail timing
+ Uint16 rsvd3:9; // 31:23 reserved
+};
+
+union XTIMING_REG {
+ Uint32 all;
+ struct XTIMING_BITS bit;
+};
+
+// XINTF control register bit definitions:
+struct XINTCNF2_BITS { // bits description
+ Uint16 WRBUFF:2; // 1:0 Write buffer depth
+ Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK
+ Uint16 CLKOFF:1; // 3 Disable XCLKOUT
+ Uint16 rsvd1:2; // 5:4 reserved
+ Uint16 WLEVEL:2; // 7:6 Current level of the write buffer
+ Uint16 rsvd2:1; // 8 reserved
+ Uint16 HOLD:1; // 9 Hold enable/disable
+ Uint16 HOLDS:1; // 10 Current state of HOLDn input
+ Uint16 HOLDAS:1; // 11 Current state of HOLDAn output
+ Uint16 rsvd3:4; // 15:12 reserved
+ Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK
+ Uint16 rsvd4:13; // 31:19 reserved
+};
+
+union XINTCNF2_REG {
+ Uint32 all;
+ struct XINTCNF2_BITS bit;
+};
+
+// XINTF bank switching register bit definitions:
+struct XBANK_BITS { // bits description
+ Uint16 BANK:3; // 2:0 Zone for which banking is enabled
+ Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add
+ Uint16 rsvd:10; // 15:6 reserved
+};
+
+union XBANK_REG {
+ Uint16 all;
+ struct XBANK_BITS bit;
+};
+
+struct XRESET_BITS {
+ Uint16 XHARDRESET:1;
+ Uint16 rsvd1:15;
+};
+
+union XRESET_REG {
+ Uint16 all;
+ struct XBANK_BITS bit;
+};
+
+
+//---------------------------------------------------------------------------
+// XINTF Register File:
+//
+struct XINTF_REGS {
+ union XTIMING_REG XTIMING0;
+ Uint32 rsvd1[5];
+ union XTIMING_REG XTIMING6;
+ union XTIMING_REG XTIMING7;
+ Uint32 rsvd2[2];
+ union XINTCNF2_REG XINTCNF2;
+ Uint32 rsvd3;
+ union XBANK_REG XBANK;
+ Uint16 rsvd4;
+ Uint16 XREVISION;
+ Uint16 rsvd5[2];
+ union XRESET_REG XRESET;
+};
+
+//---------------------------------------------------------------------------
+// XINTF External References & Function Declarations:
+//
+extern volatile struct XINTF_REGS XintfRegs;
+
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_XINTF_H definition
+
+//===========================================================================
+// No more.
+//===========================================================================
diff --git a/v120/DSP2833x_headers/source/DSP2833x_GlobalVariableDefs.c b/v120/DSP2833x_headers/source/DSP2833x_GlobalVariableDefs.c
new file mode 100644
index 0000000..d7cd332
--- /dev/null
+++ b/v120/DSP2833x_headers/source/DSP2833x_GlobalVariableDefs.c
@@ -0,0 +1,444 @@
+// TI File $Revision: /main/4 $
+// Checkin $Date: June 2, 2008 11:12:33 $
+//###########################################################################
+//
+// FILE: DSP2833x_GlobalVariableDefs.c
+//
+// TITLE: DSP2833x Global Variables and Data Section Pragmas.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
+
+//---------------------------------------------------------------------------
+// Define Global Peripheral Variables:
+//
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("AdcRegsFile")
+#else
+#pragma DATA_SECTION(AdcRegs,"AdcRegsFile");
+#endif
+volatile struct ADC_REGS AdcRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("AdcMirrorFile")
+#else
+#pragma DATA_SECTION(AdcMirror,"AdcMirrorFile");
+#endif
+volatile struct ADC_RESULT_MIRROR_REGS AdcMirror;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("CpuTimer0RegsFile")
+#else
+#pragma DATA_SECTION(CpuTimer0Regs,"CpuTimer0RegsFile");
+#endif
+volatile struct CPUTIMER_REGS CpuTimer0Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("CpuTimer1RegsFile")
+#else
+#pragma DATA_SECTION(CpuTimer1Regs,"CpuTimer1RegsFile");
+#endif
+volatile struct CPUTIMER_REGS CpuTimer1Regs;
+
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("CpuTimer2RegsFile")
+#else
+#pragma DATA_SECTION(CpuTimer2Regs,"CpuTimer2RegsFile");
+#endif
+volatile struct CPUTIMER_REGS CpuTimer2Regs;
+
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("CsmPwlFile")
+#else
+#pragma DATA_SECTION(CsmPwl,"CsmPwlFile");
+#endif
+volatile struct CSM_PWL CsmPwl;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("CsmRegsFile")
+#else
+#pragma DATA_SECTION(CsmRegs,"CsmRegsFile");
+#endif
+volatile struct CSM_REGS CsmRegs;
+
+
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("DevEmuRegsFile")
+#else
+#pragma DATA_SECTION(DevEmuRegs,"DevEmuRegsFile");
+#endif
+volatile struct DEV_EMU_REGS DevEmuRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("DmaRegsFile")
+#else
+#pragma DATA_SECTION(DmaRegs,"DmaRegsFile");
+#endif
+volatile struct DMA_REGS DmaRegs;
+
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECanaRegsFile")
+#else
+#pragma DATA_SECTION(ECanaRegs,"ECanaRegsFile");
+#endif
+volatile struct ECAN_REGS ECanaRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECanaMboxesFile")
+#else
+#pragma DATA_SECTION(ECanaMboxes,"ECanaMboxesFile");
+#endif
+volatile struct ECAN_MBOXES ECanaMboxes;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECanaLAMRegsFile")
+#else
+#pragma DATA_SECTION(ECanaLAMRegs,"ECanaLAMRegsFile");
+#endif
+volatile struct LAM_REGS ECanaLAMRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECanaMOTSRegsFile")
+#else
+#pragma DATA_SECTION(ECanaMOTSRegs,"ECanaMOTSRegsFile");
+#endif
+volatile struct MOTS_REGS ECanaMOTSRegs;
+
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECanaMOTORegsFile")
+#else
+#pragma DATA_SECTION(ECanaMOTORegs,"ECanaMOTORegsFile");
+#endif
+volatile struct MOTO_REGS ECanaMOTORegs;
+
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECanbRegsFile")
+#else
+#pragma DATA_SECTION(ECanbRegs,"ECanbRegsFile");
+#endif
+volatile struct ECAN_REGS ECanbRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECanbMboxesFile")
+#else
+#pragma DATA_SECTION(ECanbMboxes,"ECanbMboxesFile");
+#endif
+volatile struct ECAN_MBOXES ECanbMboxes;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECanbLAMRegsFile")
+#else
+#pragma DATA_SECTION(ECanbLAMRegs,"ECanbLAMRegsFile");
+#endif
+volatile struct LAM_REGS ECanbLAMRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECanbMOTSRegsFile")
+#else
+#pragma DATA_SECTION(ECanbMOTSRegs,"ECanbMOTSRegsFile");
+#endif
+volatile struct MOTS_REGS ECanbMOTSRegs;
+
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECanbMOTORegsFile")
+#else
+#pragma DATA_SECTION(ECanbMOTORegs,"ECanbMOTORegsFile");
+#endif
+volatile struct MOTO_REGS ECanbMOTORegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwm1RegsFile")
+#else
+#pragma DATA_SECTION(EPwm1Regs,"EPwm1RegsFile");
+#endif
+volatile struct EPWM_REGS EPwm1Regs;
+
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwm2RegsFile")
+#else
+#pragma DATA_SECTION(EPwm2Regs,"EPwm2RegsFile");
+#endif
+volatile struct EPWM_REGS EPwm2Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwm3RegsFile")
+#else
+#pragma DATA_SECTION(EPwm3Regs,"EPwm3RegsFile");
+#endif
+volatile struct EPWM_REGS EPwm3Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwm4RegsFile")
+#else
+#pragma DATA_SECTION(EPwm4Regs,"EPwm4RegsFile");
+#endif
+volatile struct EPWM_REGS EPwm4Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwm5RegsFile")
+#else
+#pragma DATA_SECTION(EPwm5Regs,"EPwm5RegsFile");
+#endif
+volatile struct EPWM_REGS EPwm5Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwm6RegsFile")
+#else
+#pragma DATA_SECTION(EPwm6Regs,"EPwm6RegsFile");
+#endif
+volatile struct EPWM_REGS EPwm6Regs;
+
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECap1RegsFile")
+#else
+#pragma DATA_SECTION(ECap1Regs,"ECap1RegsFile");
+#endif
+volatile struct ECAP_REGS ECap1Regs;
+
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECap2RegsFile")
+#else
+#pragma DATA_SECTION(ECap2Regs,"ECap2RegsFile");
+#endif
+volatile struct ECAP_REGS ECap2Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECap3RegsFile")
+#else
+#pragma DATA_SECTION(ECap3Regs,"ECap3RegsFile");
+#endif
+volatile struct ECAP_REGS ECap3Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECap4RegsFile")
+#else
+#pragma DATA_SECTION(ECap4Regs,"ECap4RegsFile");
+#endif
+volatile struct ECAP_REGS ECap4Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECap5RegsFile")
+#else
+#pragma DATA_SECTION(ECap5Regs,"ECap5RegsFile");
+#endif
+volatile struct ECAP_REGS ECap5Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECap6RegsFile")
+#else
+#pragma DATA_SECTION(ECap6Regs,"ECap6RegsFile");
+#endif
+volatile struct ECAP_REGS ECap6Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EQep1RegsFile")
+#else
+#pragma DATA_SECTION(EQep1Regs,"EQep1RegsFile");
+#endif
+volatile struct EQEP_REGS EQep1Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EQep2RegsFile")
+#else
+#pragma DATA_SECTION(EQep2Regs,"EQep2RegsFile");
+#endif
+volatile struct EQEP_REGS EQep2Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("GpioCtrlRegsFile")
+#else
+#pragma DATA_SECTION(GpioCtrlRegs,"GpioCtrlRegsFile");
+#endif
+volatile struct GPIO_CTRL_REGS GpioCtrlRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("GpioDataRegsFile")
+#else
+#pragma DATA_SECTION(GpioDataRegs,"GpioDataRegsFile");
+#endif
+volatile struct GPIO_DATA_REGS GpioDataRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("GpioIntRegsFile")
+#else
+#pragma DATA_SECTION(GpioIntRegs,"GpioIntRegsFile");
+#endif
+volatile struct GPIO_INT_REGS GpioIntRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("I2caRegsFile")
+#else
+#pragma DATA_SECTION(I2caRegs,"I2caRegsFile");
+#endif
+volatile struct I2C_REGS I2caRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("McbspaRegsFile")
+#else
+#pragma DATA_SECTION(McbspaRegs,"McbspaRegsFile");
+#endif
+volatile struct MCBSP_REGS McbspaRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("McbspbRegsFile")
+#else
+#pragma DATA_SECTION(McbspbRegs,"McbspbRegsFile");
+#endif
+volatile struct MCBSP_REGS McbspbRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("PartIdRegsFile")
+#else
+#pragma DATA_SECTION(PartIdRegs,"PartIdRegsFile");
+#endif
+volatile struct PARTID_REGS PartIdRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("PieCtrlRegsFile")
+#else
+#pragma DATA_SECTION(PieCtrlRegs,"PieCtrlRegsFile");
+#endif
+volatile struct PIE_CTRL_REGS PieCtrlRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("PieVectTableFile")
+#else
+#pragma DATA_SECTION(PieVectTable,"PieVectTableFile");
+#endif
+struct PIE_VECT_TABLE PieVectTable;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("SciaRegsFile")
+#else
+#pragma DATA_SECTION(SciaRegs,"SciaRegsFile");
+#endif
+volatile struct SCI_REGS SciaRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ScibRegsFile")
+#else
+#pragma DATA_SECTION(ScibRegs,"ScibRegsFile");
+#endif
+volatile struct SCI_REGS ScibRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ScicRegsFile")
+#else
+#pragma DATA_SECTION(ScicRegs,"ScicRegsFile");
+#endif
+volatile struct SCI_REGS ScicRegs;
+
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("SpiaRegsFile")
+#else
+#pragma DATA_SECTION(SpiaRegs,"SpiaRegsFile");
+#endif
+volatile struct SPI_REGS SpiaRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("SysCtrlRegsFile")
+#else
+#pragma DATA_SECTION(SysCtrlRegs,"SysCtrlRegsFile");
+#endif
+volatile struct SYS_CTRL_REGS SysCtrlRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("FlashRegsFile")
+#else
+#pragma DATA_SECTION(FlashRegs,"FlashRegsFile");
+#endif
+volatile struct FLASH_REGS FlashRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("XIntruptRegsFile")
+#else
+#pragma DATA_SECTION(XIntruptRegs,"XIntruptRegsFile");
+#endif
+volatile struct XINTRUPT_REGS XIntruptRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("XintfRegsFile")
+#else
+#pragma DATA_SECTION(XintfRegs,"XintfRegsFile");
+#endif
+volatile struct XINTF_REGS XintfRegs;
+
+
+
+//===========================================================================
+// End of file.
+//===========================================================================
+
+
+
+
+
+
+
+
+