Stanislav/altera
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

В описании предыдущего коммита ошибка: память определялась как синхронная.

Browse Source 
Увеличили размерность памяти 8х32. Со стороны контроллера ввели ножки nBL. Это выбор байта (от 0 до 3) в ячейки памяти. Добавили описание блока памяти. После синтеза, который стал занимать намного больше времени, блок памяти перестал определятся как синхронная память. Данные по загрузке ПЛИС:
Total logic elements    10,706 / 24,624 ( 43 % )
Total combinational functions  6,603 / 24,624 ( 27 % )
Dedicated logic registers  8,249 / 24,624 ( 33 % )
Total registers    8249
Total pins    25 / 149 ( 17 % )
Total PLLs    1 / 4 ( 25 % )
This commit is contained in:
sokolovstanislav 2024-03-14 11:27:47 +03:00
parent 8c0178953a
commit beef10a15b
14 changed files with 12222 additions and 2680 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

211
MainController/MainController.bdf
View File

@ -34,11 +34,11 @@ applicable agreement for further details.
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 264 104 320 216))
(annotation_block (location)(rect 320 104 376 216))
)
(pin
(input)
(rect 376 144 544 160)
(rect 392 24 560 40)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "FPGA_CLK" (rect 5 0 61 12)(font "Arial" ))
(pt 168 8)
@ -51,7 +51,7 @@ applicable agreement for further details.
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 328 144 376 160))
(annotation_block (location)(rect 344 24 392 40))
)
(pin
(input)
@ -104,9 +104,25 @@ applicable agreement for further details.
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 320 280 376 296))
)
(pin
(input)
(rect 376 296 544 312)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "nBL[1..0]" (rect 5 0 50 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
)
(pin
(output)
(rect 1144 40 1320 56)
(rect 1144 24 1320 40)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "FPGA_LED_1" (rect 90 0 158 12)(font "Arial" ))
(pt 0 8)
@ -119,11 +135,11 @@ applicable agreement for further details.
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 1320 40 1376 56))
(annotation_block (location)(rect 1320 24 1376 40))
)
(pin
(output)
(rect 1144 64 1320 80)
(rect 1144 112 1320 128)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "FPGA_LED_2" (rect 90 0 158 12)(font "Arial" ))
(pt 0 8)
@ -136,11 +152,11 @@ applicable agreement for further details.
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 1320 64 1376 80))
(annotation_block (location)(rect 1320 112 1376 128))
)
(pin
(output)
(rect 1144 88 1320 104)
(rect 1144 128 1320 144)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "FPGA_LED_3" (rect 90 0 158 12)(font "Arial" ))
(pt 0 8)
@ -153,7 +169,7 @@ applicable agreement for further details.
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 1320 88 1376 104))
(annotation_block (location)(rect 1320 128 1376 144))
)
(pin
(bidir)
@ -172,10 +188,10 @@ applicable agreement for further details.
)
(flipy)
(text "VCC" (rect 152 7 172 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 200 120 256 232))
(annotation_block (location)(rect 248 120 304 232))
)
(symbol
(rect 632 104 784 216)
(rect 632 88 784 200)
(text "AlteraPLL" (rect 5 0 52 12)(font "Arial" ))
(text "inst" (rect 8 96 25 108)(font "Arial" ))
(port
@ -218,7 +234,7 @@ applicable agreement for further details.
)
)
(symbol
(rect 632 16 752 96)
(rect 632 0 752 80)
(text "LedBlink" (rect 5 0 46 12)(font "Arial" ))
(text "inst2" (rect 8 64 31 76)(font "Arial" ))
(port
@ -242,7 +258,7 @@ applicable agreement for further details.
(symbol
(rect 952 176 1152 384)
(text "RAM" (rect 5 0 28 12)(font "Arial" ))
(text "inst3" (rect 8 192 31 204)(font "Arial" ))
(text "inst1" (rect 8 192 31 204)(font "Arial" ))
(port
(pt 0 32)
(input)
@ -281,31 +297,38 @@ applicable agreement for further details.
(port
(pt 0 112)
(input)
(text "address1[7..0]" (rect 0 0 70 12)(font "Arial" ))
(text "address1[7..0]" (rect 21 107 91 119)(font "Arial" ))
(text "bl0[1..0]" (rect 0 0 40 12)(font "Arial" ))
(text "bl0[1..0]" (rect 21 107 61 119)(font "Arial" ))
(line (pt 0 112)(pt 16 112)(line_width 3))
)
(port
(pt 0 128)
(input)
(text "we1" (rect 0 0 18 12)(font "Arial" ))
(text "we1" (rect 21 123 39 135)(font "Arial" ))
(line (pt 0 128)(pt 16 128))
(text "address1[7..0]" (rect 0 0 70 12)(font "Arial" ))
(text "address1[7..0]" (rect 21 123 91 135)(font "Arial" ))
(line (pt 0 128)(pt 16 128)(line_width 3))
)
(port
(pt 0 144)
(input)
(text "oe1" (rect 0 0 17 12)(font "Arial" ))
(text "oe1" (rect 21 139 38 151)(font "Arial" ))
(text "we1" (rect 0 0 18 12)(font "Arial" ))
(text "we1" (rect 21 139 39 151)(font "Arial" ))
(line (pt 0 144)(pt 16 144))
)
(port
(pt 0 160)
(input)
(text "ce1" (rect 0 0 17 12)(font "Arial" ))
(text "ce1" (rect 21 155 38 167)(font "Arial" ))
(text "oe1" (rect 0 0 17 12)(font "Arial" ))
(text "oe1" (rect 21 155 38 167)(font "Arial" ))
(line (pt 0 160)(pt 16 160))
)
(port
(pt 0 176)
(input)
(text "ce1" (rect 0 0 17 12)(font "Arial" ))
(text "ce1" (rect 21 171 38 183)(font "Arial" ))
(line (pt 0 176)(pt 16 176))
)
(port
(pt 200 32)
(bidir)
@ -316,8 +339,8 @@ applicable agreement for further details.
(port
(pt 200 48)
(bidir)
(text "data1[7..0]" (rect 0 0 53 12)(font "Arial" ))
(text "data1[7..0]" (rect 139 43 192 55)(font "Arial" ))
(text "data1[31..0]" (rect 0 0 59 12)(font "Arial" ))
(text "data1[31..0]" (rect 136 43 195 55)(font "Arial" ))
(line (pt 200 48)(pt 184 48)(line_width 3))
)
(drawing
@ -338,40 +361,6 @@ applicable agreement for further details.
(pt 592 624)
(bus)
)
(connector
(pt 544 152)
(pt 608 152)
)
(connector
(pt 608 152)
(pt 632 152)
)
(connector
(pt 784 136)
(pt 832 136)
)
(connector
(pt 608 48)
(pt 608 152)
)
(connector
(pt 608 48)
(pt 632 48)
)
(connector
(pt 752 48)
(pt 1144 48)
)
(connector
(pt 1168 160)
(pt 1168 208)
(bus)
)
(connector
(pt 1168 208)
(pt 1152 208)
(bus)
)
(connector
(pt 544 224)
(pt 592 224)
@ -382,10 +371,6 @@ applicable agreement for further details.
(pt 952 224)
(bus)
)
(connector
(pt 952 208)
(pt 832 208)
)
(connector
(pt 544 256)
(pt 560 256)
@ -395,37 +380,63 @@ applicable agreement for further details.
(pt 952 256)
)
(connector
(pt 544 272)
(pt 904 272)
(pt 1168 160)
(pt 1168 208)
(bus)
)
(connector
(pt 904 272)
(pt 904 240)
(pt 1152 208)
(pt 1168 208)
(bus)
)
(connector
(pt 952 240)
(pt 904 240)
(pt 608 136)
(pt 632 136)
)
(connector
(pt 920 288)
(pt 544 288)
(pt 608 32)
(pt 608 136)
)
(connector
(pt 920 288)
(pt 920 272)
(pt 560 32)
(pt 608 32)
)
(connector
(pt 920 272)
(pt 952 272)
(pt 608 32)
(pt 632 32)
)
(connector
(pt 888 240)
(pt 888 160)
(pt 608 208)
(pt 952 208)
)
(connector
(pt 608 136)
(pt 608 208)
)
(connector
(pt 608 208)
(pt 608 624)
)
(connector
(pt 752 32)
(pt 1144 32)
)
(connector
(pt 784 136)
(pt 1144 136)
)
(connector
(pt 784 120)
(pt 1144 120)
)
(connector
(pt 856 240)
(pt 856 160)
(bus)
)
(connector
(pt 1168 160)
(pt 888 160)
(pt 856 160)
(bus)
)
(connector
@ -435,47 +446,51 @@ applicable agreement for further details.
)
(connector
(pt 576 240)
(pt 888 240)
(pt 856 240)
(bus)
)
(connector
(pt 832 72)
(pt 1144 72)
(pt 544 272)
(pt 872 272)
)
(connector
(pt 832 136)
(pt 832 72)
(pt 872 272)
(pt 872 240)
)
(connector
(pt 784 152)
(pt 856 152)
(pt 952 240)
(pt 872 240)
)
(connector
(pt 856 152)
(pt 856 96)
(pt 544 288)
(pt 888 288)
)
(connector
(pt 856 96)
(pt 1144 96)
(pt 888 288)
(pt 888 272)
)
(connector
(pt 832 208)
(pt 832 304)
(pt 952 272)
(pt 888 272)
)
(connector
(pt 832 304)
(pt 608 304)
(pt 952 288)
(pt 904 288)
(bus)
)
(connector
(pt 608 152)
(pt 608 304)
(pt 904 288)
(pt 904 304)
(bus)
)
(connector
(pt 608 304)
(pt 608 624)
(pt 904 304)
(pt 544 304)
(bus)
)
(junction (pt 608 152))
(junction (pt 592 224))
(junction (pt 560 256))
(junction (pt 576 240))
(junction (pt 608 304))
(junction (pt 608 136))
(junction (pt 608 32))
(junction (pt 608 208))

2
MainController/MainController.qsf
View File

@ -103,4 +103,6 @@ set_location_assignment PIN_167 -to FPGA_LED_2
set_location_assignment PIN_168 -to FPGA_LED_3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_LED_2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_LED_3
set_location_assignment PIN_197 -to nBL[1]
set_location_assignment PIN_200 -to nBL[0]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

29
MainController/RAM.bsf
View File

@ -61,31 +61,38 @@ applicable agreement for further details.
(port
(pt 0 112)
(input)
(text "address1[7..0]" (rect 0 0 55 12)(font "Arial" ))
(text "address1[7..0]" (rect 21 107 76 119)(font "Arial" ))
(text "bl0[1..0]" (rect 0 0 29 12)(font "Arial" ))
(text "bl0[1..0]" (rect 21 107 50 119)(font "Arial" ))
(line (pt 0 112)(pt 16 112)(line_width 3))
)
(port
(pt 0 128)
(input)
(text "we1" (rect 0 0 14 12)(font "Arial" ))
(text "we1" (rect 21 123 35 135)(font "Arial" ))
(line (pt 0 128)(pt 16 128)(line_width 1))
(text "address1[7..0]" (rect 0 0 55 12)(font "Arial" ))
(text "address1[7..0]" (rect 21 123 76 135)(font "Arial" ))
(line (pt 0 128)(pt 16 128)(line_width 3))
)
(port
(pt 0 144)
(input)
(text "oe1" (rect 0 0 12 12)(font "Arial" ))
(text "oe1" (rect 21 139 33 151)(font "Arial" ))
(text "we1" (rect 0 0 14 12)(font "Arial" ))
(text "we1" (rect 21 139 35 151)(font "Arial" ))
(line (pt 0 144)(pt 16 144)(line_width 1))
)
(port
(pt 0 160)
(input)
(text "ce1" (rect 0 0 12 12)(font "Arial" ))
(text "ce1" (rect 21 155 33 167)(font "Arial" ))
(text "oe1" (rect 0 0 12 12)(font "Arial" ))
(text "oe1" (rect 21 155 33 167)(font "Arial" ))
(line (pt 0 160)(pt 16 160)(line_width 1))
)
(port
(pt 0 176)
(input)
(text "ce1" (rect 0 0 12 12)(font "Arial" ))
(text "ce1" (rect 21 171 33 183)(font "Arial" ))
(line (pt 0 176)(pt 16 176)(line_width 1))
)
(port
(pt 200 32)
(bidir)
@ -96,8 +103,8 @@ applicable agreement for further details.
(port
(pt 200 48)
(bidir)
(text "data1[7..0]" (rect 0 0 40 12)(font "Arial" ))
(text "data1[7..0]" (rect 139 43 179 55)(font "Arial" ))
(text "data1[31..0]" (rect 0 0 43 12)(font "Arial" ))
(text "data1[31..0]" (rect 136 43 179 55)(font "Arial" ))
(line (pt 200 48)(pt 184 48)(line_width 3))
)
(drawing

49
MainController/RAM.vhd
View File

@ -2,8 +2,13 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Блок памяти способен асинхронно принимать данные с двух устройств одновременно
-- Блок памяти (8х32) способен принимать данные с двух устройств одновременно;
-- Со стороны контроллера - постфикс "0" - данные грузятся в ячейку памяти четырьмя транзакциями, поскольку шина данных здесь всего 8 бит;
-- Со стороны ПЛИС - постфикс "1" - данные грузятся за одну транзакцию (шина данных 32х разрядная);
-- Для работы с контроллером дополнительно введены два бита BL для определения с какой частью ячейки памяти работаем;
-- Когда в комментариях говорю "со стороны ПЛИС" - это значит, что есть IP блок диспетчеризации,
-- который получает свежайшие данные от остальных IP блоков на ПЛИС, создает приоритетную очередь и грузит эти данные в ячейки памяти;
entity RAM is
port(
clk : in std_logic;
@ -13,8 +18,9 @@ entity RAM is
we0 : in std_logic;
oe0 : in std_logic;
ce0 : in std_logic;
bl0 : in std_logic_vector(1 downto 0);
data1 : inout std_logic_vector(7 downto 0);
data1 : inout std_logic_vector(31 downto 0);
address1 : in std_logic_vector(7 downto 0);
we1 : in std_logic;
oe1 : in std_logic;
@ -24,7 +30,7 @@ end entity;
architecture behavorial of RAM is
type mem is array (255 downto 0) of std_logic_vector(7 downto 0);
type mem is array (255 downto 0) of std_logic_vector(31 downto 0);
signal memory : mem;
signal we0Prev : std_logic := '0';
@ -41,26 +47,28 @@ signal stateMM1 : MemoryMachine := Waiting;
begin
-- автомат для работы с памятью со стороны контроллера
process(clk)
variable addr : integer range 0 to 255 := 0;
variable addr0 : integer range 0 to 255 := 0;
variable part0 : integer range 0 to 3 := 0;
variable addr1 : integer range 0 to 255 := 0;
begin
if rising_edge(clk) then
case stateMM0 is
when Waiting =>
if ce0 = '0' and ce0Prev = '1' then
addr := conv_integer(address0);
addr0 := conv_integer(address0);
part0 := conv_integer(bl0);
if oe0 = '0' then -- этот if можно перенести на следующий такт, чтобы успела установиться ножка output enable
stateMM0 <= Reading;
else
stateMM0 <= Writing;
end if;
else
addr := 0;
data0 <= (others => 'Z');
end if;
when Reading =>
data0 <= memory(addr);
data0 <= memory(addr0)(7 + part0*8 downto part0*8);
if oe0 = '1' and oe0Prev = '0' then
stateMM0 <= Waiting;
elsif ce0 = '1' then
@ -68,39 +76,32 @@ begin
end if;
when Writing =>
if we0 = '0' and we0Prev = '1' then
memory(addr) <= data0;
memory(addr0)(7 + part0*8 downto part0*8) <= data0;
stateMM0 <= Waiting;
elsif ce0 = '1' then
stateMM0 <= Waiting;
end if;
when others =>
end case;
oe0Prev <= oe0;
ce0Prev <= ce0;
we0Prev <= we0;
end if;
end process;
-- автомат для работы с памятью со стороны контроллера
process(clk)
variable addr : integer range 0 to 255 := 0;
begin
if rising_edge(clk) then
case stateMM1 is
when Waiting =>
if ce1 = '0' and ce1Prev = '1' then
addr := conv_integer(address1);
addr1 := conv_integer(address1);
if oe1 = '0' then -- этот if можно перенести на следующий такт, чтобы успела установиться ножка output enable
stateMM1 <= Reading;
else
stateMM1 <= Writing;
end if;
else
addr := 0;
data1 <= (others => 'Z');
end if;
when Reading =>
data1 <= memory(addr);
data1 <= memory(addr1);
if oe1 = '1' and oe1Prev = '0' then
stateMM1 <= Waiting;
elsif ce0 = '1' then
@ -108,20 +109,20 @@ begin
end if;
when Writing =>
if we1 = '0' and we1Prev = '1' then
memory(addr) <= data1;
memory(addr1) <= data1;
stateMM1 <= Waiting;
elsif ce0 = '1' then
stateMM1 <= Waiting;
end if;
when others =>
end case;
oe1Prev <= oe1;
ce1Prev <= ce1;
we1Prev <= we1;
end if;
end process;
-- process(clk)
-- variable addr : integer range 0 to 255;
-- begin

11073
MainController/output_files/MainController.fit.rpt
View File

File diff suppressed because it is too large Load Diff

14
MainController/output_files/MainController.fit.summary
View File

@ -1,16 +1,16 @@
Fitter Status : Successful - Tue Mar 12 17:46:50 2024
Fitter Status : Successful - Thu Mar 14 11:15:33 2024
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name : MainController
Top-level Entity Name : MainController
Family : Cyclone III
Device : EP3C25Q240C8
Timing Models : Final
Total logic elements : 95 / 24,624 ( < 1 % )
Total combinational functions : 67 / 24,624 ( < 1 % )
Dedicated logic registers : 80 / 24,624 ( < 1 % )
Total registers : 80
Total pins : 23 / 149 ( 15 % )
Total logic elements : 10,706 / 24,624 ( 43 % )
Total combinational functions : 6,603 / 24,624 ( 27 % )
Dedicated logic registers : 8,249 / 24,624 ( 33 % )
Total registers : 8249
Total pins : 25 / 149 ( 17 % )
Total virtual pins : 0
Total memory bits : 2,048 / 608,256 ( < 1 % )
Total memory bits : 0 / 608,256 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % )
Total PLLs : 1 / 4 ( 25 % )

32
MainController/output_files/MainController.flow.rpt
View File

@ -1,5 +1,5 @@
Flow report for MainController
Tue Mar 12 17:46:57 2024
Thu Mar 14 11:15:55 2024
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
@ -40,20 +40,20 @@ applicable agreement for further details.
+----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+---------------------------------------------+
; Flow Status ; Successful - Tue Mar 12 17:46:57 2024 ;
; Flow Status ; Successful - Thu Mar 14 11:15:55 2024 ;
; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
; Revision Name ; MainController ;
; Top-level Entity Name ; MainController ;
; Family ; Cyclone III ;
; Device ; EP3C25Q240C8 ;
; Timing Models ; Final ;
; Total logic elements ; 95 / 24,624 ( < 1 % ) ;
; Total combinational functions ; 67 / 24,624 ( < 1 % ) ;
; Dedicated logic registers ; 80 / 24,624 ( < 1 % ) ;
; Total registers ; 80 ;
; Total pins ; 23 / 149 ( 15 % ) ;
; Total logic elements ; 10,706 / 24,624 ( 43 % ) ;
; Total combinational functions ; 6,603 / 24,624 ( 27 % ) ;
; Dedicated logic registers ; 8,249 / 24,624 ( 33 % ) ;
; Total registers ; 8249 ;
; Total pins ; 25 / 149 ( 17 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 2,048 / 608,256 ( < 1 % ) ;
; Total memory bits ; 0 / 608,256 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ;
; Total PLLs ; 1 / 4 ( 25 % ) ;
+------------------------------------+---------------------------------------------+
@ -64,7 +64,7 @@ applicable agreement for further details.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 03/12/2024 17:46:43 ;
; Start date & time ; 03/14/2024 11:14:32 ;
; Main task ; Compilation ;
; Revision Name ; MainController ;
+-------------------+---------------------+
@ -75,7 +75,7 @@ applicable agreement for further details.
+-------------------------------------+--------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+--------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 30902508249626.171025480308064 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 30902508249626.171040407115236 ; -- ; -- ; -- ;
; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; <None> ; -- ; -- ;
; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ;
@ -97,12 +97,12 @@ applicable agreement for further details.
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:02 ; 1.0 ; 4712 MB ; 00:00:02 ;
; Fitter ; 00:00:05 ; 1.0 ; 5391 MB ; 00:00:05 ;
; Assembler ; 00:00:01 ; 1.0 ; 4585 MB ; 00:00:01 ;
; TimeQuest Timing Analyzer ; 00:00:02 ; 1.0 ; 4700 MB ; 00:00:01 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4565 MB ; 00:00:01 ;
; Total ; 00:00:11 ; -- ; -- ; 00:00:10 ;
; Analysis & Synthesis ; 00:00:21 ; 1.0 ; 4793 MB ; 00:00:21 ;
; Fitter ; 00:00:38 ; 2.2 ; 5541 MB ; 00:00:53 ;
; Assembler ; 00:00:02 ; 1.0 ; 4629 MB ; 00:00:02 ;
; TimeQuest Timing Analyzer ; 00:00:05 ; 1.8 ; 4845 MB ; 00:00:08 ;
; EDA Netlist Writer ; 00:00:09 ; 1.0 ; 4655 MB ; 00:00:09 ;
; Total ; 00:01:15 ; -- ; -- ; 00:01:33 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+

2
MainController/output_files/MainController.jdi
View File

@ -1,6 +1,6 @@
<sld_project_info>
<project>
<hash md5_digest_80b="0d51c70841a35edea1b2"/>
<hash md5_digest_80b="f67729d38ecc74603ef1"/>
</project>
<file_info>
<file device="EP3C25Q240C8" path="MainController.sof" usercode="0xFFFFFFFF"/>

617
MainController/output_files/MainController.map.rpt
View File

@ -1,5 +1,5 @@
Analysis & Synthesis report for MainController
Tue Mar 12 17:46:44 2024
Thu Mar 14 11:14:54 2024
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
@ -13,26 +13,18 @@ Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. Analysis & Synthesis RAM Summary
9. Analysis & Synthesis IP Cores Summary
10. State Machine - |MainController|RAM:inst3|stateMM1
11. State Machine - |MainController|RAM:inst3|stateMM0
12. Registers Removed During Synthesis
13. Removed Registers Triggering Further Register Optimizations
14. General Register Statistics
15. Inverted Register Statistics
16. Registers Added for RAM Pass-Through Logic
17. Registers Packed Into Inferred Megafunctions
18. Multiplexer Restructuring Statistics (Restructuring Performed)
19. Source assignments for RAM:inst3|altsyncram:memory_rtl_1|altsyncram_lkc1:auto_generated
20. Source assignments for RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated
21. Parameter Settings for User Entity Instance: AlteraPLL:inst|altpll:altpll_component
22. Parameter Settings for Inferred Entity Instance: RAM:inst3|altsyncram:memory_rtl_1
23. Parameter Settings for Inferred Entity Instance: RAM:inst3|altsyncram:memory_rtl_0
24. altpll Parameter Settings by Entity Instance
25. altsyncram Parameter Settings by Entity Instance
26. Elapsed Time Per Partition
27. Analysis & Synthesis Messages
8. Analysis & Synthesis IP Cores Summary
9. State Machine - |MainController|RAM:inst1|stateMM1
10. State Machine - |MainController|RAM:inst1|stateMM0
11. Registers Removed During Synthesis
12. Removed Registers Triggering Further Register Optimizations
13. General Register Statistics
14. Inverted Register Statistics
15. Multiplexer Restructuring Statistics (Restructuring Performed)
16. Parameter Settings for User Entity Instance: AlteraPLL:inst|altpll:altpll_component
17. altpll Parameter Settings by Entity Instance
18. Elapsed Time Per Partition
19. Analysis & Synthesis Messages
@ -58,18 +50,18 @@ applicable agreement for further details.
+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Mar 12 17:46:44 2024 ;
; Analysis & Synthesis Status ; Successful - Thu Mar 14 11:14:54 2024 ;
; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
; Revision Name ; MainController ;
; Top-level Entity Name ; MainController ;
; Family ; Cyclone III ;
; Total logic elements ; 102 ;
; Total combinational functions ; 67 ;
; Dedicated logic registers ; 80 ;
; Total registers ; 80 ;
; Total pins ; 23 ;
; Total logic elements ; 14,815 ;
; Total combinational functions ; 6,603 ;
; Dedicated logic registers ; 8,249 ;
; Total registers ; 8249 ;
; Total pins ; 25 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 2,048 ;
; Total memory bits ; 0 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 1 ;
+------------------------------------+---------------------------------------------+
@ -171,40 +163,31 @@ applicable agreement for further details.
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; Maximum used ; 4 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processors 2-8 ; 0.0% ;
; Processors 2-4 ; < 0.1% ;
; Processors 5-8 ; 0.0% ;
+----------------------------+-------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------------+---------+
; MainController.bdf ; yes ; User Block Diagram/Schematic File ; D:/GITEA/altera/MainController/MainController.bdf ; ;
; AlteraPLL.vhd ; yes ; User Wizard-Generated File ; D:/GITEA/altera/MainController/AlteraPLL.vhd ; ;
; RAM.vhd ; yes ; User VHDL File ; D:/GITEA/altera/MainController/RAM.vhd ; ;
; LedBlink.vhd ; yes ; User VHDL File ; D:/GITEA/altera/MainController/LedBlink.vhd ; ;
; altpll.tdf ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/altpll.tdf ; ;
; aglobal131.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/aglobal131.inc ; ;
; stratix_pll.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/stratix_pll.inc ; ;
; stratixii_pll.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/stratixii_pll.inc ; ;
; cycloneii_pll.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/cycloneii_pll.inc ; ;
; db/alterapll_altpll.v ; yes ; Auto-Generated Megafunction ; D:/GITEA/altera/MainController/db/alterapll_altpll.v ; ;
; altsyncram.tdf ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/altsyncram.tdf ; ;
; stratix_ram_block.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/stratix_ram_block.inc ; ;
; lpm_mux.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/lpm_mux.inc ; ;
; lpm_decode.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/lpm_decode.inc ; ;
; a_rdenreg.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/a_rdenreg.inc ; ;
; altrom.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/altrom.inc ; ;
; altram.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/altram.inc ; ;
; altdpram.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/altdpram.inc ; ;
; db/altsyncram_lkc1.tdf ; yes ; Auto-Generated Megafunction ; D:/GITEA/altera/MainController/db/altsyncram_lkc1.tdf ; ;
; db/altsyncram_8bi1.tdf ; yes ; Auto-Generated Megafunction ; D:/GITEA/altera/MainController/db/altsyncram_8bi1.tdf ; ;
+----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------------+---------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+---------+
; MainController.bdf ; yes ; User Block Diagram/Schematic File ; D:/GITEA/altera/MainController/MainController.bdf ; ;
; AlteraPLL.vhd ; yes ; User Wizard-Generated File ; D:/GITEA/altera/MainController/AlteraPLL.vhd ; ;
; RAM.vhd ; yes ; User VHDL File ; D:/GITEA/altera/MainController/RAM.vhd ; ;
; LedBlink.vhd ; yes ; User VHDL File ; D:/GITEA/altera/MainController/LedBlink.vhd ; ;
; altpll.tdf ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/altpll.tdf ; ;
; aglobal131.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/aglobal131.inc ; ;
; stratix_pll.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/stratix_pll.inc ; ;
; stratixii_pll.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/stratixii_pll.inc ; ;
; cycloneii_pll.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/cycloneii_pll.inc ; ;
; db/alterapll_altpll.v ; yes ; Auto-Generated Megafunction ; D:/GITEA/altera/MainController/db/alterapll_altpll.v ; ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+---------+
+--------------------------------------------------------------+
@ -212,32 +195,31 @@ applicable agreement for further details.
+---------------------------------------------+----------------+
; Resource ; Usage ;
+---------------------------------------------+----------------+
; Estimated Total logic elements ; 102 ;
; Estimated Total logic elements ; 14,815 ;
; ; ;
; Total combinational functions ; 67 ;
; Total combinational functions ; 6603 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 20 ;
; -- 3 input functions ; 20 ;
; -- <=2 input functions ; 27 ;
; -- 4 input functions ; 5550 ;
; -- 3 input functions ; 260 ;
; -- <=2 input functions ; 793 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 44 ;
; -- normal mode ; 6580 ;
; -- arithmetic mode ; 23 ;
; ; ;
; Total registers ; 80 ;
; -- Dedicated logic registers ; 80 ;
; Total registers ; 8249 ;
; -- Dedicated logic registers ; 8249 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 23 ;
; Total memory bits ; 2048 ;
; I/O pins ; 25 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 1 ;
; -- PLLs ; 1 ;
; ; ;
; Maximum fan-out node ; FPGA_CLK~input ;
; Maximum fan-out ; 89 ;
; Total fan-out ; 622 ;
; Average fan-out ; 2.96 ;
; Maximum fan-out ; 8250 ;
; Total fan-out ; 49361 ;
; Average fan-out ; 3.31 ;
+---------------------------------------------+----------------+
@ -246,27 +228,16 @@ applicable agreement for further details.
+--------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+--------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------+--------------+
; |MainController ; 67 (0) ; 80 (0) ; 2048 ; 0 ; 0 ; 0 ; 23 ; 0 ; |MainController ; work ;
; |MainController ; 6603 (0) ; 8249 (0) ; 0 ; 0 ; 0 ; 0 ; 25 ; 0 ; |MainController ; work ;
; |AlteraPLL:inst| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |MainController|AlteraPLL:inst ; work ;
; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |MainController|AlteraPLL:inst|altpll:altpll_component ; work ;
; |AlteraPLL_altpll:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |MainController|AlteraPLL:inst|altpll:altpll_component|AlteraPLL_altpll:auto_generated ; work ;
; |LedBlink:inst2| ; 36 (36) ; 25 (25) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |MainController|LedBlink:inst2 ; work ;
; |RAM:inst3| ; 31 (31) ; 55 (55) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |MainController|RAM:inst3 ; work ;
; |altsyncram:memory_rtl_0| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |MainController|RAM:inst3|altsyncram:memory_rtl_0 ; work ;
; |altsyncram_8bi1:auto_generated| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |MainController|RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated ; work ;
; |LedBlink:inst2| ; 33 (33) ; 25 (25) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |MainController|LedBlink:inst2 ; work ;
; |RAM:inst1| ; 6570 (6570) ; 8224 (8224) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |MainController|RAM:inst1 ; work ;
+--------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+-----------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+-----------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 256 ; 8 ; 256 ; 8 ; 2048 ; None ;
+-----------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary ;
+--------+--------------+---------+--------------+--------------+--------------------------------+----------------------------------------------+
@ -278,7 +249,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Encoding Type: One-Hot
+---------------------------------------------------------------------------+
; State Machine - |MainController|RAM:inst3|stateMM1 ;
; State Machine - |MainController|RAM:inst1|stateMM1 ;
+------------------+------------------+------------------+------------------+
; Name ; stateMM1.Reading ; stateMM1.Writing ; stateMM1.Waiting ;
+------------------+------------------+------------------+------------------+
@ -290,7 +261,7 @@ Encoding Type: One-Hot
Encoding Type: One-Hot
+---------------------------------------------------------------------------+
; State Machine - |MainController|RAM:inst3|stateMM0 ;
; State Machine - |MainController|RAM:inst1|stateMM0 ;
+------------------+------------------+------------------+------------------+
; Name ; stateMM0.Reading ; stateMM0.Writing ; stateMM0.Waiting ;
+------------------+------------------+------------------+------------------+
@ -305,37 +276,110 @@ Encoding Type: One-Hot
+----------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+----------------------------------------+----------------------------------------+
; RAM:inst3|oe1Prev ; Lost fanout ;
; RAM:inst3|ce1Prev ; Stuck at GND due to stuck port data_in ;
; RAM:inst3|we1Prev ; Stuck at GND due to stuck port data_in ;
; RAM:inst3|\process_1:addr[0..7] ; Stuck at GND due to stuck port data_in ;
; RAM:inst3|data1[0]~en ; Lost fanout ;
; RAM:inst3|data1[1]~en ; Lost fanout ;
; RAM:inst3|data1[2]~en ; Lost fanout ;
; RAM:inst3|data1[3]~en ; Lost fanout ;
; RAM:inst3|data1[4]~en ; Lost fanout ;
; RAM:inst3|data1[5]~en ; Lost fanout ;
; RAM:inst3|data1[6]~en ; Lost fanout ;
; RAM:inst3|data1[7]~en ; Lost fanout ;
; RAM:inst3|stateMM1.Reading ; Lost fanout ;
; RAM:inst3|stateMM1.Writing ; Stuck at GND due to stuck port data_in ;
; RAM:inst3|stateMM1.Waiting ; Lost fanout ;
; Total Number of Removed Registers = 22 ; ;
; RAM:inst1|oe1Prev ; Lost fanout ;
; RAM:inst1|ce1Prev ; Stuck at GND due to stuck port data_in ;
; RAM:inst1|we1Prev ; Stuck at GND due to stuck port data_in ;
; RAM:inst1|data1[31]~reg0 ; Lost fanout ;
; RAM:inst1|data1[31]~en ; Lost fanout ;
; RAM:inst1|data1[30]~reg0 ; Lost fanout ;
; RAM:inst1|data1[30]~en ; Lost fanout ;
; RAM:inst1|data1[29]~reg0 ; Lost fanout ;
; RAM:inst1|data1[29]~en ; Lost fanout ;
; RAM:inst1|data1[28]~reg0 ; Lost fanout ;
; RAM:inst1|data1[28]~en ; Lost fanout ;
; RAM:inst1|data1[27]~reg0 ; Lost fanout ;
; RAM:inst1|data1[27]~en ; Lost fanout ;
; RAM:inst1|data1[26]~reg0 ; Lost fanout ;
; RAM:inst1|data1[26]~en ; Lost fanout ;
; RAM:inst1|data1[25]~reg0 ; Lost fanout ;
; RAM:inst1|data1[25]~en ; Lost fanout ;
; RAM:inst1|data1[24]~reg0 ; Lost fanout ;
; RAM:inst1|data1[24]~en ; Lost fanout ;
; RAM:inst1|data1[23]~reg0 ; Lost fanout ;
; RAM:inst1|data1[23]~en ; Lost fanout ;
; RAM:inst1|data1[22]~reg0 ; Lost fanout ;
; RAM:inst1|data1[22]~en ; Lost fanout ;
; RAM:inst1|data1[21]~reg0 ; Lost fanout ;
; RAM:inst1|data1[21]~en ; Lost fanout ;
; RAM:inst1|data1[20]~reg0 ; Lost fanout ;
; RAM:inst1|data1[20]~en ; Lost fanout ;
; RAM:inst1|data1[19]~reg0 ; Lost fanout ;
; RAM:inst1|data1[19]~en ; Lost fanout ;
; RAM:inst1|data1[18]~reg0 ; Lost fanout ;
; RAM:inst1|data1[18]~en ; Lost fanout ;
; RAM:inst1|data1[17]~reg0 ; Lost fanout ;
; RAM:inst1|data1[17]~en ; Lost fanout ;
; RAM:inst1|data1[16]~reg0 ; Lost fanout ;
; RAM:inst1|data1[16]~en ; Lost fanout ;
; RAM:inst1|data1[15]~reg0 ; Lost fanout ;
; RAM:inst1|data1[15]~en ; Lost fanout ;
; RAM:inst1|data1[14]~reg0 ; Lost fanout ;
; RAM:inst1|data1[14]~en ; Lost fanout ;
; RAM:inst1|data1[13]~reg0 ; Lost fanout ;
; RAM:inst1|data1[13]~en ; Lost fanout ;
; RAM:inst1|data1[12]~reg0 ; Lost fanout ;
; RAM:inst1|data1[12]~en ; Lost fanout ;
; RAM:inst1|data1[11]~reg0 ; Lost fanout ;
; RAM:inst1|data1[11]~en ; Lost fanout ;
; RAM:inst1|data1[10]~reg0 ; Lost fanout ;
; RAM:inst1|data1[10]~en ; Lost fanout ;
; RAM:inst1|data1[9]~reg0 ; Lost fanout ;
; RAM:inst1|data1[9]~en ; Lost fanout ;
; RAM:inst1|data1[8]~reg0 ; Lost fanout ;
; RAM:inst1|data1[8]~en ; Lost fanout ;
; RAM:inst1|data1[7]~reg0 ; Lost fanout ;
; RAM:inst1|data1[7]~en ; Lost fanout ;
; RAM:inst1|data1[6]~reg0 ; Lost fanout ;
; RAM:inst1|data1[6]~en ; Lost fanout ;
; RAM:inst1|data1[5]~reg0 ; Lost fanout ;
; RAM:inst1|data1[5]~en ; Lost fanout ;
; RAM:inst1|data1[4]~reg0 ; Lost fanout ;
; RAM:inst1|data1[4]~en ; Lost fanout ;
; RAM:inst1|data1[3]~reg0 ; Lost fanout ;
; RAM:inst1|data1[3]~en ; Lost fanout ;
; RAM:inst1|data1[2]~reg0 ; Lost fanout ;
; RAM:inst1|data1[2]~en ; Lost fanout ;
; RAM:inst1|data1[1]~reg0 ; Lost fanout ;
; RAM:inst1|data1[1]~en ; Lost fanout ;
; RAM:inst1|data1[0]~reg0 ; Lost fanout ;
; RAM:inst1|data1[0]~en ; Lost fanout ;
; RAM:inst1|addr1[0..7] ; Lost fanout ;
; RAM:inst1|stateMM1.Waiting ; Lost fanout ;
; RAM:inst1|stateMM1.Writing ; Lost fanout ;
; RAM:inst1|stateMM1.Reading ; Lost fanout ;
; Total Number of Removed Registers = 78 ; ;
+----------------------------------------+----------------------------------------+
+----------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations ;
+----------------------------+---------------------------+-------------------------------------------------------------+
; Register name ; Reason for Removal ; Registers Removed due to This Register ;
+----------------------------+---------------------------+-------------------------------------------------------------+
; RAM:inst3|ce1Prev ; Stuck at GND ; RAM:inst3|\process_1:addr[0], RAM:inst3|\process_1:addr[1], ;
; ; due to stuck port data_in ; RAM:inst3|\process_1:addr[2], RAM:inst3|\process_1:addr[3], ;
; ; ; RAM:inst3|\process_1:addr[4], RAM:inst3|\process_1:addr[5], ;
; ; ; RAM:inst3|\process_1:addr[6], RAM:inst3|\process_1:addr[7] ;
; RAM:inst3|stateMM1.Writing ; Stuck at GND ; RAM:inst3|stateMM1.Waiting ;
; ; due to stuck port data_in ; ;
+----------------------------+---------------------------+-------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations ;
+-------------------+---------------------------+------------------------------------------------------------------------------------+
; Register name ; Reason for Removal ; Registers Removed due to This Register ;
+-------------------+---------------------------+------------------------------------------------------------------------------------+
; RAM:inst1|we1Prev ; Stuck at GND ; RAM:inst1|data1[31]~reg0, RAM:inst1|data1[31]~en, RAM:inst1|data1[30]~reg0, ;
; ; due to stuck port data_in ; RAM:inst1|data1[30]~en, RAM:inst1|data1[29]~reg0, RAM:inst1|data1[29]~en, ;
; ; ; RAM:inst1|data1[28]~reg0, RAM:inst1|data1[28]~en, RAM:inst1|data1[27]~reg0, ;
; ; ; RAM:inst1|data1[27]~en, RAM:inst1|data1[26]~reg0, RAM:inst1|data1[26]~en, ;
; ; ; RAM:inst1|data1[25]~reg0, RAM:inst1|data1[25]~en, RAM:inst1|data1[24]~reg0, ;
; ; ; RAM:inst1|data1[24]~en, RAM:inst1|data1[23]~reg0, RAM:inst1|data1[23]~en, ;
; ; ; RAM:inst1|data1[22]~reg0, RAM:inst1|data1[22]~en, RAM:inst1|data1[21]~reg0, ;
; ; ; RAM:inst1|data1[21]~en, RAM:inst1|data1[20]~reg0, RAM:inst1|data1[20]~en, ;
; ; ; RAM:inst1|data1[19]~reg0, RAM:inst1|data1[19]~en, RAM:inst1|data1[18]~reg0, ;
; ; ; RAM:inst1|data1[18]~en, RAM:inst1|data1[17]~reg0, RAM:inst1|data1[17]~en, ;
; ; ; RAM:inst1|data1[16]~reg0, RAM:inst1|data1[16]~en, RAM:inst1|data1[15]~reg0, ;
; ; ; RAM:inst1|data1[15]~en, RAM:inst1|data1[14]~reg0, RAM:inst1|data1[14]~en, ;
; ; ; RAM:inst1|data1[13]~reg0, RAM:inst1|data1[13]~en, RAM:inst1|data1[12]~reg0, ;
; ; ; RAM:inst1|data1[12]~en, RAM:inst1|data1[11]~reg0, RAM:inst1|data1[11]~en, ;
; ; ; RAM:inst1|data1[10]~reg0, RAM:inst1|data1[10]~en, RAM:inst1|data1[9]~reg0, ;
; ; ; RAM:inst1|data1[9]~en, RAM:inst1|data1[8]~reg0, RAM:inst1|data1[8]~en, ;
; ; ; RAM:inst1|data1[7]~reg0, RAM:inst1|data1[7]~en, RAM:inst1|data1[6]~reg0, ;
; ; ; RAM:inst1|data1[6]~en, RAM:inst1|data1[5]~reg0, RAM:inst1|data1[5]~en, ;
; ; ; RAM:inst1|data1[4]~reg0, RAM:inst1|data1[4]~en, RAM:inst1|data1[3]~reg0, ;
; ; ; RAM:inst1|data1[3]~en, RAM:inst1|data1[2]~reg0, RAM:inst1|data1[2]~en, ;
; ; ; RAM:inst1|data1[1]~reg0, RAM:inst1|data1[1]~en, RAM:inst1|data1[0]~reg0, ;
; ; ; RAM:inst1|data1[0]~en, RAM:inst1|addr1[4], RAM:inst1|addr1[5], RAM:inst1|addr1[6], ;
; ; ; RAM:inst1|addr1[7] ;
+-------------------+---------------------------+------------------------------------------------------------------------------------+
+------------------------------------------------------+
@ -343,12 +387,12 @@ Encoding Type: One-Hot
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 80 ;
; Total registers ; 8249 ;
; Number of registers using Synchronous Clear ; 24 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 34 ;
; Number of registers using Clock Enable ; 8220 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
@ -363,81 +407,15 @@ Encoding Type: One-Hot
+----------------------------------------+---------+
+------------------------------------------------------------+
; Registers Added for RAM Pass-Through Logic ;
+-----------------------------------+------------------------+
; Register Name ; RAM Name ;
+-----------------------------------+------------------------+
; RAM:inst3|memory_rtl_0_bypass[0] ; RAM:inst3|memory_rtl_0 ;
; RAM:inst3|memory_rtl_0_bypass[1] ; RAM:inst3|memory_rtl_0 ;
; RAM:inst3|memory_rtl_0_bypass[2] ; RAM:inst3|memory_rtl_0 ;
; RAM:inst3|memory_rtl_0_bypass[3] ; RAM:inst3|memory_rtl_0 ;
; RAM:inst3|memory_rtl_0_bypass[4] ; RAM:inst3|memory_rtl_0 ;
; RAM:inst3|memory_rtl_0_bypass[5] ; RAM:inst3|memory_rtl_0 ;
; RAM:inst3|memory_rtl_0_bypass[6] ; RAM:inst3|memory_rtl_0 ;
; RAM:inst3|memory_rtl_0_bypass[7] ; RAM:inst3|memory_rtl_0 ;
; RAM:inst3|memory_rtl_0_bypass[8] ; RAM:inst3|memory_rtl_0 ;
; RAM:inst3|memory_rtl_0_bypass[9] ; RAM:inst3|memory_rtl_0 ;
; RAM:inst3|memory_rtl_0_bypass[10] ; RAM:inst3|memory_rtl_0 ;
; RAM:inst3|memory_rtl_0_bypass[11] ; RAM:inst3|memory_rtl_0 ;
; RAM:inst3|memory_rtl_0_bypass[12] ; RAM:inst3|memory_rtl_0 ;
; RAM:inst3|memory_rtl_0_bypass[13] ; RAM:inst3|memory_rtl_0 ;
; RAM:inst3|memory_rtl_0_bypass[14] ; RAM:inst3|memory_rtl_0 ;
; RAM:inst3|memory_rtl_0_bypass[15] ; RAM:inst3|memory_rtl_0 ;
; RAM:inst3|memory_rtl_0_bypass[16] ; RAM:inst3|memory_rtl_0 ;
; RAM:inst3|memory_rtl_0_bypass[17] ; RAM:inst3|memory_rtl_0 ;
; RAM:inst3|memory_rtl_0_bypass[18] ; RAM:inst3|memory_rtl_0 ;
; RAM:inst3|memory_rtl_0_bypass[19] ; RAM:inst3|memory_rtl_0 ;
; RAM:inst3|memory_rtl_0_bypass[20] ; RAM:inst3|memory_rtl_0 ;
; RAM:inst3|memory_rtl_0_bypass[21] ; RAM:inst3|memory_rtl_0 ;
; RAM:inst3|memory_rtl_0_bypass[22] ; RAM:inst3|memory_rtl_0 ;
; RAM:inst3|memory_rtl_0_bypass[23] ; RAM:inst3|memory_rtl_0 ;
; RAM:inst3|memory_rtl_0_bypass[24] ; RAM:inst3|memory_rtl_0 ;
+-----------------------------------+------------------------+
+---------------------------------------------------------+
; Registers Packed Into Inferred Megafunctions ;
+-------------------------+------------------------+------+
; Register Name ; Megafunction ; Type ;
+-------------------------+------------------------+------+
; RAM:inst3|data1[0]~reg0 ; RAM:inst3|memory_rtl_1 ; RAM ;
; RAM:inst3|data1[1]~reg0 ; RAM:inst3|memory_rtl_1 ; RAM ;
; RAM:inst3|data1[2]~reg0 ; RAM:inst3|memory_rtl_1 ; RAM ;
; RAM:inst3|data1[3]~reg0 ; RAM:inst3|memory_rtl_1 ; RAM ;
; RAM:inst3|data1[4]~reg0 ; RAM:inst3|memory_rtl_1 ; RAM ;
; RAM:inst3|data1[5]~reg0 ; RAM:inst3|memory_rtl_1 ; RAM ;
; RAM:inst3|data1[6]~reg0 ; RAM:inst3|memory_rtl_1 ; RAM ;
; RAM:inst3|data1[7]~reg0 ; RAM:inst3|memory_rtl_1 ; RAM ;
+-------------------------+------------------------+------+
+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |MainController|RAM:inst3|Selector32 ;
; 6:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; No ; |MainController|RAM:inst3|Selector3 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
+-----------------------------------------------------------------------------------------+
; Source assignments for RAM:inst3|altsyncram:memory_rtl_1|altsyncram_lkc1:auto_generated ;
+---------------------------------+--------------------+------+---------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+---------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+---------------------------+
+-----------------------------------------------------------------------------------------+
; Source assignments for RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated ;
+---------------------------------+--------------------+------+---------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+---------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+---------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------+
; 1024:1 ; 8 bits ; 5456 LEs ; 5456 LEs ; 0 LEs ; Yes ; |MainController|RAM:inst1|data0[7]~reg0 ;
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |MainController|RAM:inst1|Selector33 ;
; 6:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; No ; |MainController|RAM:inst1|Selector30 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------+
+-------------------------------------------------------------------------------------+
@ -814,128 +792,6 @@ Encoding Type: One-Hot
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: RAM:inst3|altsyncram:memory_rtl_1 ;
+------------------------------------+----------------------+------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+----------------------+------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; DUAL_PORT ; Untyped ;
; WIDTH_A ; 8 ; Untyped ;
; WIDTHAD_A ; 8 ; Untyped ;
; NUMWORDS_A ; 256 ; Untyped ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 8 ; Untyped ;
; WIDTHAD_B ; 8 ; Untyped ;
; NUMWORDS_B ; 256 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Untyped ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; UNUSED ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
; ENABLE_ECC ; FALSE ; Untyped ;
; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;
; WIDTH_ECCSTATUS ; 3 ; Untyped ;
; DEVICE_FAMILY ; Cyclone III ; Untyped ;
; CBXI_PARAMETER ; altsyncram_lkc1 ; Untyped ;
+------------------------------------+----------------------+------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: RAM:inst3|altsyncram:memory_rtl_0 ;
+------------------------------------+----------------------+------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+----------------------+------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; DUAL_PORT ; Untyped ;
; WIDTH_A ; 8 ; Untyped ;
; WIDTHAD_A ; 8 ; Untyped ;
; NUMWORDS_A ; 256 ; Untyped ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 8 ; Untyped ;
; WIDTHAD_B ; 8 ; Untyped ;
; NUMWORDS_B ; 256 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK0 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Untyped ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; UNUSED ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
; ENABLE_ECC ; FALSE ; Untyped ;
; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;
; WIDTH_ECCSTATUS ; 3 ; Untyped ;
; DEVICE_FAMILY ; Cyclone III ; Untyped ;
; CBXI_PARAMETER ; altsyncram_8bi1 ; Untyped ;
+------------------------------------+----------------------+------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+------------------------------------------------------------------------+
; altpll Parameter Settings by Entity Instance ;
+-------------------------------+----------------------------------------+
@ -953,43 +809,12 @@ Note: In order to hide this table in the UI and the text report file, please set
+-------------------------------+----------------------------------------+
+-------------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance ;
+-------------------------------------------+-----------------------------------+
; Name ; Value ;
+-------------------------------------------+-----------------------------------+
; Number of entity instances ; 2 ;
; Entity Instance ; RAM:inst3|altsyncram:memory_rtl_1 ;
; -- OPERATION_MODE ; DUAL_PORT ;
; -- WIDTH_A ; 8 ;
; -- NUMWORDS_A ; 256 ;
; -- OUTDATA_REG_A ; UNREGISTERED ;
; -- WIDTH_B ; 8 ;
; -- NUMWORDS_B ; 256 ;
; -- ADDRESS_REG_B ; CLOCK1 ;
; -- OUTDATA_REG_B ; UNREGISTERED ;
; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
; Entity Instance ; RAM:inst3|altsyncram:memory_rtl_0 ;
; -- OPERATION_MODE ; DUAL_PORT ;
; -- WIDTH_A ; 8 ;
; -- NUMWORDS_A ; 256 ;
; -- OUTDATA_REG_A ; UNREGISTERED ;
; -- WIDTH_B ; 8 ;
; -- NUMWORDS_B ; 256 ;
; -- ADDRESS_REG_B ; CLOCK0 ;
; -- OUTDATA_REG_B ; UNREGISTERED ;
; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ;
+-------------------------------------------+-----------------------------------+
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:00 ;
; Top ; 00:00:18 ;
+----------------+--------------+
@ -999,7 +824,7 @@ Note: In order to hide this table in the UI and the text report file, please set
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Info: Processing started: Tue Mar 12 17:46:42 2024
Info: Processing started: Thu Mar 14 11:14:31 2024
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off MainController -c MainController
Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
Info (12021): Found 1 design units, including 1 entities, in source file maincontroller.bdf
@ -1081,103 +906,21 @@ Info (12133): Instantiated megafunction "AlteraPLL:inst|altpll:altpll_component"
Info (12021): Found 1 design units, including 1 entities, in source file db/alterapll_altpll.v
Info (12023): Found entity 1: AlteraPLL_altpll
Info (12128): Elaborating entity "AlteraPLL_altpll" for hierarchy "AlteraPLL:inst|altpll:altpll_component|AlteraPLL_altpll:auto_generated"
Info (12128): Elaborating entity "RAM" for hierarchy "RAM:inst3"
Warning (276020): Inferred RAM node "RAM:inst3|memory_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
Warning (276027): Inferred dual-clock RAM node "RAM:inst3|memory_rtl_1" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design.
Info (19000): Inferred 2 megafunctions from design logic
Info (276029): Inferred altsyncram megafunction from the following design logic: "RAM:inst3|memory_rtl_0"
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
Info (286033): Parameter WIDTH_A set to 8
Info (286033): Parameter WIDTHAD_A set to 8
Info (286033): Parameter NUMWORDS_A set to 256
Info (286033): Parameter WIDTH_B set to 8
Info (286033): Parameter WIDTHAD_B set to 8
Info (286033): Parameter NUMWORDS_B set to 256
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
Info (276029): Inferred altsyncram megafunction from the following design logic: "RAM:inst3|memory_rtl_1"
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
Info (286033): Parameter WIDTH_A set to 8
Info (286033): Parameter WIDTHAD_A set to 8
Info (286033): Parameter NUMWORDS_A set to 256
Info (286033): Parameter WIDTH_B set to 8
Info (286033): Parameter WIDTHAD_B set to 8
Info (286033): Parameter NUMWORDS_B set to 256
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
Info (286033): Parameter ADDRESS_REG_B set to CLOCK1
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (12130): Elaborated megafunction instantiation "RAM:inst3|altsyncram:memory_rtl_1"
Info (12133): Instantiated megafunction "RAM:inst3|altsyncram:memory_rtl_1" with the following parameter:
Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
Info (12134): Parameter "WIDTH_A" = "8"
Info (12134): Parameter "WIDTHAD_A" = "8"
Info (12134): Parameter "NUMWORDS_A" = "256"
Info (12134): Parameter "WIDTH_B" = "8"
Info (12134): Parameter "WIDTHAD_B" = "8"
Info (12134): Parameter "NUMWORDS_B" = "256"
Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"
Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK1"
Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_lkc1.tdf
Info (12023): Found entity 1: altsyncram_lkc1
Info (12130): Elaborated megafunction instantiation "RAM:inst3|altsyncram:memory_rtl_0"
Info (12133): Instantiated megafunction "RAM:inst3|altsyncram:memory_rtl_0" with the following parameter:
Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
Info (12134): Parameter "WIDTH_A" = "8"
Info (12134): Parameter "WIDTHAD_A" = "8"
Info (12134): Parameter "NUMWORDS_A" = "256"
Info (12134): Parameter "WIDTH_B" = "8"
Info (12134): Parameter "WIDTHAD_B" = "8"
Info (12134): Parameter "NUMWORDS_B" = "256"
Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"
Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0"
Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
Info (12134): Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_8bi1.tdf
Info (12023): Found entity 1: altsyncram_8bi1
Warning (14284): Synthesized away the following node(s):
Warning (14285): Synthesized away the following RAM node(s):
Warning (14320): Synthesized away node "RAM:inst3|altsyncram:memory_rtl_1|altsyncram_lkc1:auto_generated|ram_block1a0"
Warning (14320): Synthesized away node "RAM:inst3|altsyncram:memory_rtl_1|altsyncram_lkc1:auto_generated|ram_block1a1"
Warning (14320): Synthesized away node "RAM:inst3|altsyncram:memory_rtl_1|altsyncram_lkc1:auto_generated|ram_block1a2"
Warning (14320): Synthesized away node "RAM:inst3|altsyncram:memory_rtl_1|altsyncram_lkc1:auto_generated|ram_block1a3"
Warning (14320): Synthesized away node "RAM:inst3|altsyncram:memory_rtl_1|altsyncram_lkc1:auto_generated|ram_block1a4"
Warning (14320): Synthesized away node "RAM:inst3|altsyncram:memory_rtl_1|altsyncram_lkc1:auto_generated|ram_block1a5"
Warning (14320): Synthesized away node "RAM:inst3|altsyncram:memory_rtl_1|altsyncram_lkc1:auto_generated|ram_block1a6"
Warning (14320): Synthesized away node "RAM:inst3|altsyncram:memory_rtl_1|altsyncram_lkc1:auto_generated|ram_block1a7"
Info (12128): Elaborating entity "RAM" for hierarchy "RAM:inst1"
Info (286030): Timing-Driven Synthesis is running
Info (17049): 11 registers lost all their fanouts during netlist optimizations.
Info (17049): 76 registers lost all their fanouts during netlist optimizations.
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 143 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 12 input pins
Info (21057): Implemented 14842 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 14 input pins
Info (21059): Implemented 3 output pins
Info (21060): Implemented 8 bidirectional pins
Info (21061): Implemented 111 logic cells
Info (21064): Implemented 8 RAM segments
Info (21061): Implemented 14816 logic cells
Info (21065): Implemented 1 PLLs
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 12 warnings
Info: Peak virtual memory: 4712 megabytes
Info: Processing ended: Tue Mar 12 17:46:44 2024
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 4793 megabytes
Info: Processing ended: Thu Mar 14 11:14:54 2024
Info: Elapsed time: 00:00:23
Info: Total CPU time (on all processors): 00:00:23

14
MainController/output_files/MainController.map.summary
View File

@ -1,14 +1,14 @@
Analysis & Synthesis Status : Successful - Tue Mar 12 17:46:44 2024
Analysis & Synthesis Status : Successful - Thu Mar 14 11:14:54 2024
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name : MainController
Top-level Entity Name : MainController
Family : Cyclone III
Total logic elements : 102
Total combinational functions : 67
Dedicated logic registers : 80
Total registers : 80
Total pins : 23
Total logic elements : 14,815
Total combinational functions : 6,603
Dedicated logic registers : 8,249
Total registers : 8249
Total pins : 25
Total virtual pins : 0
Total memory bits : 2,048
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 1

4
MainController/output_files/MainController.pin
View File

@ -264,10 +264,10 @@ GND : 193 : gnd : :
Data[0] : 194 : bidir : 3.3-V LVTTL : : 7 : Y
Address[7] : 195 : input : 3.3-V LVTTL : : 7 : Y
Address[0] : 196 : input : 3.3-V LVTTL : : 7 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : 197 : : : : 7 :
nBL[1] : 197 : input : 2.5 V : : 7 : Y
VCCINT : 198 : power : : 1.2V : :
GND : 199 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 200 : : : : 7 :
nBL[0] : 200 : input : 2.5 V : : 7 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : 201 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 202 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 203 : : : : 7 :

BIN
MainController/output_files/MainController.sof
View File

Binary file not shown.

2843
MainController/output_files/MainController.sta.rpt
View File

File diff suppressed because it is too large Load Diff

12
MainController/output_files/MainController.sta.summary
View File

@ -3,7 +3,7 @@ TimeQuest Timing Analyzer Summary
------------------------------------------------------------
Type : Slow 1200mV 85C Model Setup 'FPGA_CLK'
Slack : 33.637
Slack : 20.350
TNS : 0.000
Type : Slow 1200mV 85C Model Hold 'FPGA_CLK'
@ -11,11 +11,11 @@ Slack : 0.454
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'FPGA_CLK'
Slack : 19.618
Slack : 19.752
TNS : 0.000
Type : Slow 1200mV 0C Model Setup 'FPGA_CLK'
Slack : 34.094
Slack : 21.115
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'FPGA_CLK'
@ -23,11 +23,11 @@ Slack : 0.402
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'FPGA_CLK'
Slack : 19.600
Slack : 19.746
TNS : 0.000
Type : Fast 1200mV 0C Model Setup 'FPGA_CLK'
Slack : 37.258
Slack : 30.708
TNS : 0.000
Type : Fast 1200mV 0C Model Hold 'FPGA_CLK'
@ -35,7 +35,7 @@ Slack : 0.186
TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'FPGA_CLK'
Slack : 19.206
Slack : 19.267
TNS : 0.000
------------------------------------------------------------