Откорректировал блок памяти RAM для возможной работы с двумя устройствами одновременно. Одно из них - внешний контроллер. Вторым будет блок сбора информации для обновления данных. Сейчас в блоке памяти нет взаимной блокировки для двух независимых процессов и, существует возможность записать в одну и ту же ячейку памяти в один и тот же момент времени разные значения. В нашем проекте поскольку дальше будет введено ограничение, которое обяжет писать служебные и критические (напрямую участвующие в алгоритмах работы преобразователем частоты) данные только в определенные заранее известные регистры, такое невозможно. Память на уровне использования программистом будет поделена две области. Ту, в которую можно писать и считать записанное значение и ту, из которой можно будет только считать значения. Со стороны устройства будут использованы для записи только те ячейки, которые процессор будет только читать. Со стороны процессора будут использованы для записи только те ячейки, которые блоки внутри устройства будут только читать.

This commit is contained in:
sokolovstanislav 2024-03-04 18:16:35 +03:00
parent 7ee9a34a42
commit 6bb13aec36
3 changed files with 219 additions and 162 deletions

View File

@ -23,7 +23,7 @@ applicable agreement for further details.
(input)
(rect 376 248 544 264)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
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(pt 168 8)
(drawing
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@ -37,41 +37,9 @@ applicable agreement for further details.
)
(pin
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(pt 168 8)
(drawing
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@ -87,7 +55,7 @@ applicable agreement for further details.
(input)
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(pt 168 8)
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@ -99,6 +67,40 @@ applicable agreement for further details.
)
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@ -143,9 +145,9 @@ applicable agreement for further details.
)
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@ -154,49 +156,63 @@ applicable agreement for further details.
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@ -213,50 +229,6 @@ applicable agreement for further details.
(pt 592 624)
(bus)
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@ -269,7 +241,51 @@ applicable agreement for further details.
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View File

@ -20,9 +20,9 @@ applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
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(text "RAM" (rect 5 0 28 12)(font "Arial" ))
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@ -31,48 +31,62 @@ applicable agreement for further details.
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)

View File

@ -2,16 +2,21 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Блок памяти способен асинхронно принимать данные с двух устройств одновременно
entity RAM is
port(
clk : in std_logic;
data : in std_logic_vector(15 downto 0);
address : in std_logic_vector(7 downto 0);
clkMCU : in std_logic;
dataMCU : inout std_logic_vector(15 downto 0);
addressMCU : inout std_logic_vector(7 downto 0);
-- write when 0, read when 1
wr : in std_logic
data0 : inout std_logic_vector(15 downto 0);
address0 : in std_logic_vector(7 downto 0);
wr0 : in std_logic;
clk0 : in std_logic;
data1 : inout std_logic_vector(15 downto 0);
address1 : in std_logic_vector(7 downto 0);
wr1 : in std_logic;
clk1 : in std_logic
);
end entity;
@ -20,23 +25,45 @@ architecture behavorial of RAM is
type mem is array (255 downto 0) of std_logic_vector(15 downto 0);
signal memory : mem;
signal clkMCUPrev : std_logic := '0';
signal clk0Prev : std_logic := '0';
signal clk1Prev : std_logic := '0';
begin
process(clk)
variable addr : integer range 0 to 255;
variable addr0 : integer range 0 to 255;
variable addr1 : integer range 0 to 255;
begin
if rising_edge(clk) then
if clkMCU = '1' and clkMCUPrev = '0' then
addr := conv_integer(addressMCU); -- переменной addr присваивается новое значение сразу. Удобно для преобразования типов.
if (wr = '0') then
memory(addr) <= dataMCU; -- тут уже новое значение переменной addr
if clk1 = '1' and clk1Prev = '0' then
addr1 := conv_integer(address1); -- переменной addr1 присваивается новое значение сразу. Удобно для преобразования типов.
if (wr1 = '0') then
memory(addr1) <= data1; -- тут уже новое значение переменной addr1
else
dataMCU <= memory(addr);
data1 <= memory(addr1);
end if;
end if;
clkMCUPrev <= clkMCU;
if clk1 = '0' and clk1Prev = '1' then
data1 <= (others => 'Z');
end if;
clk1Prev <= clk1;
if clk0 = '1' and clk0Prev = '0' then
addr0 := conv_integer(address0); -- переменной addr0 присваивается новое значение сразу. Удобно для преобразования типов.
if (wr0 = '0') then
memory(addr0) <= data0; -- тут уже новое значение переменной addr0
else
data0 <= memory(addr0);
end if;
end if;
if clk0 = '0' and clk0Prev = '1' then
data0 <= (others => 'Z');
end if;
clk0Prev <= clk0;
end if;
end process;