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Начали проект переноса ПО под Альтеру. В проект MainController добавлен блок умножителя частоты и блок памяти на 255 ячеек по 16 бит данных. В память можно записать значение в ячейки и прочитать их оттуда. Преднастроек или каких либо зарезервированных ячеек пока нет. В отличие от проекта для Spartan2 здесь не будет ServiceDataDispatch. Вместо него данные из MCU будут сразу же грузиться в логические блоки (PWM, HWP и другие).

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sokolovstanislav 2024-03-04 17:16:43 +03:00
commit 7ee9a34a42
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64
MainController/AlteraPLL.bsf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 168 128)
(text "AlteraPLL" (rect 5 0 47 12)(font "Arial" ))
(text "inst" (rect 8 96 20 108)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "areset" (rect 0 0 24 12)(font "Arial" ))
(text "areset" (rect 21 27 45 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "inclk0" (rect 0 0 21 12)(font "Arial" ))
(text "inclk0" (rect 21 43 42 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 152 32)
(output)
(text "c0" (rect 0 0 9 12)(font "Arial" ))
(text "c0" (rect 122 27 131 39)(font "Arial" ))
(line (pt 152 32)(pt 136 32)(line_width 1))
)
(port
(pt 152 48)
(output)
(text "c1" (rect 0 0 8 12)(font "Arial" ))
(text "c1" (rect 123 43 131 55)(font "Arial" ))
(line (pt 152 48)(pt 136 48)(line_width 1))
)
(port
(pt 152 64)
(output)
(text "locked" (rect 0 0 24 12)(font "Arial" ))
(text "locked" (rect 107 59 131 71)(font "Arial" ))
(line (pt 152 64)(pt 136 64)(line_width 1))
)
(drawing
(rectangle (rect 16 16 136 96)(line_width 1))
)
)

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MainController/AlteraPLL.cmp Normal file
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--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component AlteraPLL
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;

12
MainController/AlteraPLL.ppf Normal file
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<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="AlteraPLL" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="areset" direction="input" scope="external" />
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="c1" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" />
</global>
</pinplan>

5
MainController/AlteraPLL.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "AlteraPLL.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "AlteraPLL.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "AlteraPLL.ppf"]

397
MainController/AlteraPLL.vhd Normal file
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-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: AlteraPLL.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY AlteraPLL IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END AlteraPLL;
ARCHITECTURE SYN OF alterapll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 4,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 8,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 40000,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=AlteraPLL",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "200.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "8"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "200.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "AlteraPLL.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL AlteraPLL.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL AlteraPLL.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL AlteraPLL.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL AlteraPLL.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL AlteraPLL.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL AlteraPLL_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

275
MainController/MainController.bdf Normal file
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@ -0,0 +1,275 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "graphic" (version "1.4"))
(pin
(input)
(rect 376 248 544 264)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "ClkRAM" (rect 5 0 46 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 352 232 544 248)
(text "INPUT" (rect 149 0 177 10)(font "Arial" (font_size 6)))
(text "AddressRAM[7..0]" (rect 5 0 95 12)(font "Arial" ))
(pt 192 8)
(drawing
(line (pt 108 12)(pt 133 12))
(line (pt 108 4)(pt 133 4))
(line (pt 137 8)(pt 192 8))
(line (pt 108 12)(pt 108 4))
(line (pt 133 4)(pt 137 8))
(line (pt 133 12)(pt 137 8))
)
(text "VCC" (rect 152 7 172 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 368 216 544 232)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "DataRAM[15..0]" (rect 5 0 85 12)(font "Arial" ))
(pt 176 8)
(drawing
(line (pt 92 12)(pt 117 12))
(line (pt 92 4)(pt 117 4))
(line (pt 121 8)(pt 176 8))
(line (pt 92 12)(pt 92 4))
(line (pt 117 4)(pt 121 8))
(line (pt 117 12)(pt 121 8))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 376 144 544 160)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "Clk" (rect 5 0 22 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 376 264 544 280)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "WR" (rect 5 0 24 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
)
(symbol
(rect 632 104 784 216)
(text "AlteraPLL" (rect 5 0 52 12)(font "Arial" ))
(text "inst" (rect 8 96 25 108)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "areset" (rect 0 0 30 12)(font "Arial" ))
(text "areset" (rect 21 27 51 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "inclk0" (rect 0 0 28 12)(font "Arial" ))
(text "inclk0" (rect 21 43 49 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 152 32)
(output)
(text "c0" (rect 0 0 11 12)(font "Arial" ))
(text "c0" (rect 122 27 133 39)(font "Arial" ))
(line (pt 152 32)(pt 136 32))
)
(port
(pt 152 48)
(output)
(text "c1" (rect 0 0 11 12)(font "Arial" ))
(text "c1" (rect 122 43 133 55)(font "Arial" ))
(line (pt 152 48)(pt 136 48))
)
(port
(pt 152 64)
(output)
(text "locked" (rect 0 0 31 12)(font "Arial" ))
(text "locked" (rect 105 59 136 71)(font "Arial" ))
(line (pt 152 64)(pt 136 64))
)
(drawing
(rectangle (rect 16 16 136 96))
)
)
(symbol
(rect 816 176 1040 320)
(text "RAM" (rect 5 0 28 12)(font "Arial" ))
(text "inst4" (rect 8 128 31 140)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 14 12)(font "Arial" ))
(text "clk" (rect 21 27 35 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 224 48)
(input)
(text "data[15..0]" (rect 0 0 53 12)(font "Arial" ))
(text "data[15..0]" (rect 146 40 199 52)(font "Arial" ))
(line (pt 208 48)(pt 224 48)(line_width 3))
)
(port
(pt 224 64)
(input)
(text "address[7..0]" (rect 0 0 64 12)(font "Arial" ))
(text "address[7..0]" (rect 135 56 199 68)(font "Arial" ))
(line (pt 208 64)(pt 224 64)(line_width 3))
)
(port
(pt 0 80)
(input)
(text "clkMCU" (rect 0 0 38 12)(font "Arial" ))
(text "clkMCU" (rect 21 75 59 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80))
)
(port
(pt 0 96)
(input)
(text "wr" (rect 0 0 10 12)(font "Arial" ))
(text "wr" (rect 21 91 31 103)(font "Arial" ))
(line (pt 0 96)(pt 16 96))
)
(port
(pt 0 48)
(bidir)
(text "dataMCU[15..0]" (rect 0 0 77 12)(font "Arial" ))
(text "dataMCU[15..0]" (rect 24 40 101 52)(font "Arial" ))
(line (pt 16 48)(pt 0 48)(line_width 3))
)
(port
(pt 0 64)
(bidir)
(text "addressMCU[7..0]" (rect 0 0 89 12)(font "Arial" ))
(text "addressMCU[7..0]" (rect 24 56 113 68)(font "Arial" ))
(line (pt 16 64)(pt 0 64)(line_width 3))
)
(drawing
(rectangle (rect 16 16 208 128))
)
)
(connector
(pt 560 256)
(pt 560 624)
)
(connector
(pt 576 240)
(pt 576 624)
(bus)
)
(connector
(pt 592 224)
(pt 592 624)
(bus)
)
(connector
(pt 544 224)
(pt 592 224)
(bus)
)
(connector
(pt 544 240)
(pt 576 240)
(bus)
)
(connector
(pt 544 256)
(pt 560 256)
)
(connector
(pt 560 256)
(pt 816 256)
)
(connector
(pt 544 272)
(pt 816 272)
)
(connector
(pt 592 224)
(pt 816 224)
(bus)
)
(connector
(pt 576 240)
(pt 816 240)
(bus)
)
(connector
(pt 816 208)
(pt 800 208)
)
(connector
(pt 800 136)
(pt 784 136)
)
(connector
(pt 800 208)
(pt 800 136)
)
(connector
(pt 608 152)
(pt 608 624)
)
(connector
(pt 544 152)
(pt 608 152)
)
(connector
(pt 608 152)
(pt 632 152)
)
(junction (pt 560 256))
(junction (pt 576 240))
(junction (pt 592 224))
(junction (pt 608 152))

30
MainController/MainController.qpf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
# Date created = 14:32:32 March 04, 2024
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "14:32:32 March 04, 2024"
# Revisions
PROJECT_REVISION = "MainController"

58
MainController/MainController.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
# Date created = 14:32:32 March 04, 2024
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# MainController_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE EP3C25Q240C8
set_global_assignment -name TOP_LEVEL_ENTITY MainController
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:32:32 MARCH 04, 2024"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name BDF_FILE MainController.bdf
set_global_assignment -name QIP_FILE AlteraPLL.qip
set_global_assignment -name VHDL_FILE RAM.vhd
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

78
MainController/RAM.bsf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 64 64 288 208)
(text "RAM" (rect 5 0 28 12)(font "Arial" ))
(text "inst" (rect 8 128 25 140)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 14 12)(font "Arial" ))
(text "clk" (rect 21 27 35 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 224 48)
(input)
(text "data[15..0]" (rect 0 0 53 12)(font "Arial" ))
(text "data[15..0]" (rect 146 40 199 52)(font "Arial" ))
(line (pt 208 48)(pt 224 48)(line_width 3))
)
(port
(pt 224 64)
(input)
(text "address[7..0]" (rect 0 0 64 12)(font "Arial" ))
(text "address[7..0]" (rect 135 56 199 68)(font "Arial" ))
(line (pt 208 64)(pt 224 64)(line_width 3))
)
(port
(pt 0 80)
(input)
(text "clkMCU" (rect 0 0 38 12)(font "Arial" ))
(text "clkMCU" (rect 21 75 59 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80))
)
(port
(pt 0 96)
(input)
(text "wr" (rect 0 0 10 12)(font "Arial" ))
(text "wr" (rect 21 91 31 103)(font "Arial" ))
(line (pt 0 96)(pt 16 96))
)
(port
(pt 0 48)
(bidir)
(text "dataMCU[15..0]" (rect 0 0 77 12)(font "Arial" ))
(text "dataMCU[15..0]" (rect 24 40 101 52)(font "Arial" ))
(line (pt 16 48)(pt 0 48)(line_width 3))
)
(port
(pt 0 64)
(bidir)
(text "addressMCU[7..0]" (rect 0 0 89 12)(font "Arial" ))
(text "addressMCU[7..0]" (rect 24 56 113 68)(font "Arial" ))
(line (pt 16 64)(pt 0 64)(line_width 3))
)
(drawing
(rectangle (rect 16 16 208 128))
)
)

43
MainController/RAM.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RAM is
port(
clk : in std_logic;
data : in std_logic_vector(15 downto 0);
address : in std_logic_vector(7 downto 0);
clkMCU : in std_logic;
dataMCU : inout std_logic_vector(15 downto 0);
addressMCU : inout std_logic_vector(7 downto 0);
-- write when 0, read when 1
wr : in std_logic
);
end entity;
architecture behavorial of RAM is
type mem is array (255 downto 0) of std_logic_vector(15 downto 0);
signal memory : mem;
signal clkMCUPrev : std_logic := '0';
begin
process(clk)
variable addr : integer range 0 to 255;
begin
if rising_edge(clk) then
if clkMCU = '1' and clkMCUPrev = '0' then
addr := conv_integer(addressMCU); -- переменной addr присваивается новое значение сразу. Удобно для преобразования типов.
if (wr = '0') then
memory(addr) <= dataMCU; -- тут уже новое значение переменной addr
else
dataMCU <= memory(addr);
end if;
end if;
clkMCUPrev <= clkMCU;
end if;
end process;
end behavorial;

775
MainController/output_files/MainController.map.rpt Normal file
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Analysis & Synthesis report for MainController
Mon Mar 04 16:44:59 2024
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. Analysis & Synthesis IP Cores Summary
9. General Register Statistics
10. Parameter Settings for User Entity Instance: AlteraPLL:inst|altpll:altpll_component
11. altpll Parameter Settings by Entity Instance
12. Elapsed Time Per Partition
13. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Mar 04 16:44:59 2024 ;
; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
; Revision Name ; MainController ;
; Top-level Entity Name ; MainController ;
; Family ; Cyclone III ;
; Total logic elements ; 0 ;
; Total combinational functions ; 0 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 27 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
+------------------------------------+---------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device ; EP3C25Q240C8 ; ;
; Top-level entity name ; MainController ; MainController ;
; Family name ; Cyclone III ; Cyclone IV GX ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; On ; On ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
; Synthesis Seed ; 1 ; 1 ;
+----------------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processors 2-8 ; 0.0% ;
+----------------------------+-------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+---------+
; MainController.bdf ; yes ; User Block Diagram/Schematic File ; D:/GITEA/altera/MainController/MainController.bdf ; ;
; AlteraPLL.vhd ; yes ; User Wizard-Generated File ; D:/GITEA/altera/MainController/AlteraPLL.vhd ; ;
; RAM.vhd ; yes ; User VHDL File ; D:/GITEA/altera/MainController/RAM.vhd ; ;
; altpll.tdf ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/altpll.tdf ; ;
; aglobal131.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/aglobal131.inc ; ;
; stratix_pll.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/stratix_pll.inc ; ;
; stratixii_pll.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/stratixii_pll.inc ; ;
; cycloneii_pll.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/cycloneii_pll.inc ; ;
; db/alterapll_altpll.v ; yes ; Auto-Generated Megafunction ; D:/GITEA/altera/MainController/db/alterapll_altpll.v ; ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+---------+
+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; ; ;
; Total combinational functions ; 0 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 0 ;
; -- 3 input functions ; 0 ;
; -- <=2 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 0 ;
; -- arithmetic mode ; 0 ;
; ; ;
; Total registers ; 0 ;
; -- Dedicated logic registers ; 0 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 27 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Maximum fan-out node ; Clk ;
; Maximum fan-out ; 1 ;
; Total fan-out ; 27 ;
; Average fan-out ; 0.50 ;
+---------------------------------------------+-------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |MainController ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 27 ; 0 ; |MainController ; work ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary ;
+--------+--------------+---------+--------------+--------------+--------------------------------+----------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
+--------+--------------+---------+--------------+--------------+--------------------------------+----------------------------------------------+
; Altera ; ALTPLL ; 13.1 ; N/A ; N/A ; |MainController|AlteraPLL:inst ; D:/GITEA/altera/MainController/AlteraPLL.vhd ;
+--------+--------------+---------+--------------+--------------+--------------------------------+----------------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: AlteraPLL:inst|altpll:altpll_component ;
+-------------------------------+-----------------------------+-----------------------+
; Parameter Name ; Value ; Type ;
+-------------------------------+-----------------------------+-----------------------+
; OPERATION_MODE ; NORMAL ; Untyped ;
; PLL_TYPE ; AUTO ; Untyped ;
; LPM_HINT ; CBX_MODULE_PREFIX=AlteraPLL ; Untyped ;
; QUALIFY_CONF_DONE ; OFF ; Untyped ;
; COMPENSATE_CLOCK ; CLK0 ; Untyped ;
; SCAN_CHAIN ; LONG ; Untyped ;
; PRIMARY_CLOCK ; INCLK0 ; Untyped ;
; INCLK0_INPUT_FREQUENCY ; 40000 ; Signed Integer ;
; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ;
; GATE_LOCK_SIGNAL ; NO ; Untyped ;
; GATE_LOCK_COUNTER ; 0 ; Untyped ;
; LOCK_HIGH ; 1 ; Untyped ;
; LOCK_LOW ; 1 ; Untyped ;
; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ;
; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ;
; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ;
; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ;
; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ;
; SKIP_VCO ; OFF ; Untyped ;
; SWITCH_OVER_COUNTER ; 0 ; Untyped ;
; SWITCH_OVER_TYPE ; AUTO ; Untyped ;
; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ;
; BANDWIDTH ; 0 ; Untyped ;
; BANDWIDTH_TYPE ; AUTO ; Untyped ;
; SPREAD_FREQUENCY ; 0 ; Untyped ;
; DOWN_SPREAD ; 0 ; Untyped ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ;
; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ;
; CLK9_MULTIPLY_BY ; 0 ; Untyped ;
; CLK8_MULTIPLY_BY ; 0 ; Untyped ;
; CLK7_MULTIPLY_BY ; 0 ; Untyped ;
; CLK6_MULTIPLY_BY ; 0 ; Untyped ;
; CLK5_MULTIPLY_BY ; 1 ; Untyped ;
; CLK4_MULTIPLY_BY ; 1 ; Untyped ;
; CLK3_MULTIPLY_BY ; 1 ; Untyped ;
; CLK2_MULTIPLY_BY ; 1 ; Untyped ;
; CLK1_MULTIPLY_BY ; 8 ; Signed Integer ;
; CLK0_MULTIPLY_BY ; 4 ; Signed Integer ;
; CLK9_DIVIDE_BY ; 0 ; Untyped ;
; CLK8_DIVIDE_BY ; 0 ; Untyped ;
; CLK7_DIVIDE_BY ; 0 ; Untyped ;
; CLK6_DIVIDE_BY ; 0 ; Untyped ;
; CLK5_DIVIDE_BY ; 1 ; Untyped ;
; CLK4_DIVIDE_BY ; 1 ; Untyped ;
; CLK3_DIVIDE_BY ; 1 ; Untyped ;
; CLK2_DIVIDE_BY ; 1 ; Untyped ;
; CLK1_DIVIDE_BY ; 1 ; Signed Integer ;
; CLK0_DIVIDE_BY ; 1 ; Signed Integer ;
; CLK9_PHASE_SHIFT ; 0 ; Untyped ;
; CLK8_PHASE_SHIFT ; 0 ; Untyped ;
; CLK7_PHASE_SHIFT ; 0 ; Untyped ;
; CLK6_PHASE_SHIFT ; 0 ; Untyped ;
; CLK5_PHASE_SHIFT ; 0 ; Untyped ;
; CLK4_PHASE_SHIFT ; 0 ; Untyped ;
; CLK3_PHASE_SHIFT ; 0 ; Untyped ;
; CLK2_PHASE_SHIFT ; 0 ; Untyped ;
; CLK1_PHASE_SHIFT ; 0 ; Untyped ;
; CLK0_PHASE_SHIFT ; 0 ; Untyped ;
; CLK5_TIME_DELAY ; 0 ; Untyped ;
; CLK4_TIME_DELAY ; 0 ; Untyped ;
; CLK3_TIME_DELAY ; 0 ; Untyped ;
; CLK2_TIME_DELAY ; 0 ; Untyped ;
; CLK1_TIME_DELAY ; 0 ; Untyped ;
; CLK0_TIME_DELAY ; 0 ; Untyped ;
; CLK9_DUTY_CYCLE ; 50 ; Untyped ;
; CLK8_DUTY_CYCLE ; 50 ; Untyped ;
; CLK7_DUTY_CYCLE ; 50 ; Untyped ;
; CLK6_DUTY_CYCLE ; 50 ; Untyped ;
; CLK5_DUTY_CYCLE ; 50 ; Untyped ;
; CLK4_DUTY_CYCLE ; 50 ; Untyped ;
; CLK3_DUTY_CYCLE ; 50 ; Untyped ;
; CLK2_DUTY_CYCLE ; 50 ; Untyped ;
; CLK1_DUTY_CYCLE ; 50 ; Signed Integer ;
; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ;
; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; LOCK_WINDOW_UI ; 0.05 ; Untyped ;
; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ;
; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ;
; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ;
; DPA_MULTIPLY_BY ; 0 ; Untyped ;
; DPA_DIVIDE_BY ; 1 ; Untyped ;
; DPA_DIVIDER ; 0 ; Untyped ;
; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ;
; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ;
; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ;
; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ;
; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ;
; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ;
; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ;
; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ;
; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ;
; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ;
; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ;
; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ;
; EXTCLK3_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK2_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK1_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK0_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ;
; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ;
; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ;
; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ;
; VCO_MULTIPLY_BY ; 0 ; Untyped ;
; VCO_DIVIDE_BY ; 0 ; Untyped ;
; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ;
; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ;
; VCO_MIN ; 0 ; Untyped ;
; VCO_MAX ; 0 ; Untyped ;
; VCO_CENTER ; 0 ; Untyped ;
; PFD_MIN ; 0 ; Untyped ;
; PFD_MAX ; 0 ; Untyped ;
; M_INITIAL ; 0 ; Untyped ;
; M ; 0 ; Untyped ;
; N ; 1 ; Untyped ;
; M2 ; 1 ; Untyped ;
; N2 ; 1 ; Untyped ;
; SS ; 1 ; Untyped ;
; C0_HIGH ; 0 ; Untyped ;
; C1_HIGH ; 0 ; Untyped ;
; C2_HIGH ; 0 ; Untyped ;
; C3_HIGH ; 0 ; Untyped ;
; C4_HIGH ; 0 ; Untyped ;
; C5_HIGH ; 0 ; Untyped ;
; C6_HIGH ; 0 ; Untyped ;
; C7_HIGH ; 0 ; Untyped ;
; C8_HIGH ; 0 ; Untyped ;
; C9_HIGH ; 0 ; Untyped ;
; C0_LOW ; 0 ; Untyped ;
; C1_LOW ; 0 ; Untyped ;
; C2_LOW ; 0 ; Untyped ;
; C3_LOW ; 0 ; Untyped ;
; C4_LOW ; 0 ; Untyped ;
; C5_LOW ; 0 ; Untyped ;
; C6_LOW ; 0 ; Untyped ;
; C7_LOW ; 0 ; Untyped ;
; C8_LOW ; 0 ; Untyped ;
; C9_LOW ; 0 ; Untyped ;
; C0_INITIAL ; 0 ; Untyped ;
; C1_INITIAL ; 0 ; Untyped ;
; C2_INITIAL ; 0 ; Untyped ;
; C3_INITIAL ; 0 ; Untyped ;
; C4_INITIAL ; 0 ; Untyped ;
; C5_INITIAL ; 0 ; Untyped ;
; C6_INITIAL ; 0 ; Untyped ;
; C7_INITIAL ; 0 ; Untyped ;
; C8_INITIAL ; 0 ; Untyped ;
; C9_INITIAL ; 0 ; Untyped ;
; C0_MODE ; BYPASS ; Untyped ;
; C1_MODE ; BYPASS ; Untyped ;
; C2_MODE ; BYPASS ; Untyped ;
; C3_MODE ; BYPASS ; Untyped ;
; C4_MODE ; BYPASS ; Untyped ;
; C5_MODE ; BYPASS ; Untyped ;
; C6_MODE ; BYPASS ; Untyped ;
; C7_MODE ; BYPASS ; Untyped ;
; C8_MODE ; BYPASS ; Untyped ;
; C9_MODE ; BYPASS ; Untyped ;
; C0_PH ; 0 ; Untyped ;
; C1_PH ; 0 ; Untyped ;
; C2_PH ; 0 ; Untyped ;
; C3_PH ; 0 ; Untyped ;
; C4_PH ; 0 ; Untyped ;
; C5_PH ; 0 ; Untyped ;
; C6_PH ; 0 ; Untyped ;
; C7_PH ; 0 ; Untyped ;
; C8_PH ; 0 ; Untyped ;
; C9_PH ; 0 ; Untyped ;
; L0_HIGH ; 1 ; Untyped ;
; L1_HIGH ; 1 ; Untyped ;
; G0_HIGH ; 1 ; Untyped ;
; G1_HIGH ; 1 ; Untyped ;
; G2_HIGH ; 1 ; Untyped ;
; G3_HIGH ; 1 ; Untyped ;
; E0_HIGH ; 1 ; Untyped ;
; E1_HIGH ; 1 ; Untyped ;
; E2_HIGH ; 1 ; Untyped ;
; E3_HIGH ; 1 ; Untyped ;
; L0_LOW ; 1 ; Untyped ;
; L1_LOW ; 1 ; Untyped ;
; G0_LOW ; 1 ; Untyped ;
; G1_LOW ; 1 ; Untyped ;
; G2_LOW ; 1 ; Untyped ;
; G3_LOW ; 1 ; Untyped ;
; E0_LOW ; 1 ; Untyped ;
; E1_LOW ; 1 ; Untyped ;
; E2_LOW ; 1 ; Untyped ;
; E3_LOW ; 1 ; Untyped ;
; L0_INITIAL ; 1 ; Untyped ;
; L1_INITIAL ; 1 ; Untyped ;
; G0_INITIAL ; 1 ; Untyped ;
; G1_INITIAL ; 1 ; Untyped ;
; G2_INITIAL ; 1 ; Untyped ;
; G3_INITIAL ; 1 ; Untyped ;
; E0_INITIAL ; 1 ; Untyped ;
; E1_INITIAL ; 1 ; Untyped ;
; E2_INITIAL ; 1 ; Untyped ;
; E3_INITIAL ; 1 ; Untyped ;
; L0_MODE ; BYPASS ; Untyped ;
; L1_MODE ; BYPASS ; Untyped ;
; G0_MODE ; BYPASS ; Untyped ;
; G1_MODE ; BYPASS ; Untyped ;
; G2_MODE ; BYPASS ; Untyped ;
; G3_MODE ; BYPASS ; Untyped ;
; E0_MODE ; BYPASS ; Untyped ;
; E1_MODE ; BYPASS ; Untyped ;
; E2_MODE ; BYPASS ; Untyped ;
; E3_MODE ; BYPASS ; Untyped ;
; L0_PH ; 0 ; Untyped ;
; L1_PH ; 0 ; Untyped ;
; G0_PH ; 0 ; Untyped ;
; G1_PH ; 0 ; Untyped ;
; G2_PH ; 0 ; Untyped ;
; G3_PH ; 0 ; Untyped ;
; E0_PH ; 0 ; Untyped ;
; E1_PH ; 0 ; Untyped ;
; E2_PH ; 0 ; Untyped ;
; E3_PH ; 0 ; Untyped ;
; M_PH ; 0 ; Untyped ;
; C1_USE_CASC_IN ; OFF ; Untyped ;
; C2_USE_CASC_IN ; OFF ; Untyped ;
; C3_USE_CASC_IN ; OFF ; Untyped ;
; C4_USE_CASC_IN ; OFF ; Untyped ;
; C5_USE_CASC_IN ; OFF ; Untyped ;
; C6_USE_CASC_IN ; OFF ; Untyped ;
; C7_USE_CASC_IN ; OFF ; Untyped ;
; C8_USE_CASC_IN ; OFF ; Untyped ;
; C9_USE_CASC_IN ; OFF ; Untyped ;
; CLK0_COUNTER ; G0 ; Untyped ;
; CLK1_COUNTER ; G0 ; Untyped ;
; CLK2_COUNTER ; G0 ; Untyped ;
; CLK3_COUNTER ; G0 ; Untyped ;
; CLK4_COUNTER ; G0 ; Untyped ;
; CLK5_COUNTER ; G0 ; Untyped ;
; CLK6_COUNTER ; E0 ; Untyped ;
; CLK7_COUNTER ; E1 ; Untyped ;
; CLK8_COUNTER ; E2 ; Untyped ;
; CLK9_COUNTER ; E3 ; Untyped ;
; L0_TIME_DELAY ; 0 ; Untyped ;
; L1_TIME_DELAY ; 0 ; Untyped ;
; G0_TIME_DELAY ; 0 ; Untyped ;
; G1_TIME_DELAY ; 0 ; Untyped ;
; G2_TIME_DELAY ; 0 ; Untyped ;
; G3_TIME_DELAY ; 0 ; Untyped ;
; E0_TIME_DELAY ; 0 ; Untyped ;
; E1_TIME_DELAY ; 0 ; Untyped ;
; E2_TIME_DELAY ; 0 ; Untyped ;
; E3_TIME_DELAY ; 0 ; Untyped ;
; M_TIME_DELAY ; 0 ; Untyped ;
; N_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK3_COUNTER ; E3 ; Untyped ;
; EXTCLK2_COUNTER ; E2 ; Untyped ;
; EXTCLK1_COUNTER ; E1 ; Untyped ;
; EXTCLK0_COUNTER ; E0 ; Untyped ;
; ENABLE0_COUNTER ; L0 ; Untyped ;
; ENABLE1_COUNTER ; L0 ; Untyped ;
; CHARGE_PUMP_CURRENT ; 2 ; Untyped ;
; LOOP_FILTER_R ; 1.000000 ; Untyped ;
; LOOP_FILTER_C ; 5 ; Untyped ;
; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ;
; LOOP_FILTER_R_BITS ; 9999 ; Untyped ;
; LOOP_FILTER_C_BITS ; 9999 ; Untyped ;
; VCO_POST_SCALE ; 0 ; Untyped ;
; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ;
; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ;
; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ;
; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ;
; PORT_CLK0 ; PORT_USED ; Untyped ;
; PORT_CLK1 ; PORT_USED ; Untyped ;
; PORT_CLK2 ; PORT_UNUSED ; Untyped ;
; PORT_CLK3 ; PORT_UNUSED ; Untyped ;
; PORT_CLK4 ; PORT_UNUSED ; Untyped ;
; PORT_CLK5 ; PORT_UNUSED ; Untyped ;
; PORT_CLK6 ; PORT_UNUSED ; Untyped ;
; PORT_CLK7 ; PORT_UNUSED ; Untyped ;
; PORT_CLK8 ; PORT_UNUSED ; Untyped ;
; PORT_CLK9 ; PORT_UNUSED ; Untyped ;
; PORT_SCANDATA ; PORT_UNUSED ; Untyped ;
; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ;
; PORT_SCANDONE ; PORT_UNUSED ; Untyped ;
; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ;
; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ;
; PORT_INCLK1 ; PORT_UNUSED ; Untyped ;
; PORT_INCLK0 ; PORT_USED ; Untyped ;
; PORT_FBIN ; PORT_UNUSED ; Untyped ;
; PORT_PLLENA ; PORT_UNUSED ; Untyped ;
; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ;
; PORT_ARESET ; PORT_USED ; Untyped ;
; PORT_PFDENA ; PORT_UNUSED ; Untyped ;
; PORT_SCANCLK ; PORT_UNUSED ; Untyped ;
; PORT_SCANACLR ; PORT_UNUSED ; Untyped ;
; PORT_SCANREAD ; PORT_UNUSED ; Untyped ;
; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ;
; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_LOCKED ; PORT_USED ; Untyped ;
; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ;
; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ;
; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ;
; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ;
; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ;
; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ;
; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ;
; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ;
; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ;
; M_TEST_SOURCE ; 5 ; Untyped ;
; C0_TEST_SOURCE ; 5 ; Untyped ;
; C1_TEST_SOURCE ; 5 ; Untyped ;
; C2_TEST_SOURCE ; 5 ; Untyped ;
; C3_TEST_SOURCE ; 5 ; Untyped ;
; C4_TEST_SOURCE ; 5 ; Untyped ;
; C5_TEST_SOURCE ; 5 ; Untyped ;
; C6_TEST_SOURCE ; 5 ; Untyped ;
; C7_TEST_SOURCE ; 5 ; Untyped ;
; C8_TEST_SOURCE ; 5 ; Untyped ;
; C9_TEST_SOURCE ; 5 ; Untyped ;
; CBXI_PARAMETER ; AlteraPLL_altpll ; Untyped ;
; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ;
; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ;
; WIDTH_CLOCK ; 5 ; Signed Integer ;
; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ;
; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ;
; DEVICE_FAMILY ; Cyclone III ; Untyped ;
; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+-------------------------------+-----------------------------+-----------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+------------------------------------------------------------------------+
; altpll Parameter Settings by Entity Instance ;
+-------------------------------+----------------------------------------+
; Name ; Value ;
+-------------------------------+----------------------------------------+
; Number of entity instances ; 1 ;
; Entity Instance ; AlteraPLL:inst|altpll:altpll_component ;
; -- OPERATION_MODE ; NORMAL ;
; -- PLL_TYPE ; AUTO ;
; -- PRIMARY_CLOCK ; INCLK0 ;
; -- INCLK0_INPUT_FREQUENCY ; 40000 ;
; -- INCLK1_INPUT_FREQUENCY ; 0 ;
; -- VCO_MULTIPLY_BY ; 0 ;
; -- VCO_DIVIDE_BY ; 0 ;
+-------------------------------+----------------------------------------+
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:00 ;
+----------------+--------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Info: Processing started: Mon Mar 04 16:44:57 2024
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off MainController -c MainController
Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
Info (12021): Found 1 design units, including 1 entities, in source file maincontroller.bdf
Info (12023): Found entity 1: MainController
Info (12021): Found 2 design units, including 1 entities, in source file alterapll.vhd
Info (12022): Found design unit 1: alterapll-SYN
Info (12023): Found entity 1: AlteraPLL
Info (12021): Found 2 design units, including 1 entities, in source file ram.vhd
Info (12022): Found design unit 1: RAM-behavorial
Info (12023): Found entity 1: RAM
Info (12127): Elaborating entity "MainController" for the top level hierarchy
Info (12128): Elaborating entity "AlteraPLL" for hierarchy "AlteraPLL:inst"
Info (12128): Elaborating entity "altpll" for hierarchy "AlteraPLL:inst|altpll:altpll_component"
Info (12130): Elaborated megafunction instantiation "AlteraPLL:inst|altpll:altpll_component"
Info (12133): Instantiated megafunction "AlteraPLL:inst|altpll:altpll_component" with the following parameter:
Info (12134): Parameter "bandwidth_type" = "AUTO"
Info (12134): Parameter "clk0_divide_by" = "1"
Info (12134): Parameter "clk0_duty_cycle" = "50"
Info (12134): Parameter "clk0_multiply_by" = "4"
Info (12134): Parameter "clk0_phase_shift" = "0"
Info (12134): Parameter "clk1_divide_by" = "1"
Info (12134): Parameter "clk1_duty_cycle" = "50"
Info (12134): Parameter "clk1_multiply_by" = "8"
Info (12134): Parameter "clk1_phase_shift" = "0"
Info (12134): Parameter "compensate_clock" = "CLK0"
Info (12134): Parameter "inclk0_input_frequency" = "40000"
Info (12134): Parameter "intended_device_family" = "Cyclone III"
Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=AlteraPLL"
Info (12134): Parameter "lpm_type" = "altpll"
Info (12134): Parameter "operation_mode" = "NORMAL"
Info (12134): Parameter "pll_type" = "AUTO"
Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
Info (12134): Parameter "port_areset" = "PORT_USED"
Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
Info (12134): Parameter "port_inclk0" = "PORT_USED"
Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
Info (12134): Parameter "port_locked" = "PORT_USED"
Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
Info (12134): Parameter "port_clk0" = "PORT_USED"
Info (12134): Parameter "port_clk1" = "PORT_USED"
Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
Info (12134): Parameter "self_reset_on_loss_lock" = "OFF"
Info (12134): Parameter "width_clock" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/alterapll_altpll.v
Info (12023): Found entity 1: AlteraPLL_altpll
Info (12128): Elaborating entity "AlteraPLL_altpll" for hierarchy "AlteraPLL:inst|altpll:altpll_component|AlteraPLL_altpll:auto_generated"
Info (12128): Elaborating entity "RAM" for hierarchy "RAM:inst4"
Warning (14284): Synthesized away the following node(s):
Warning (14285): Synthesized away the following PLL node(s):
Warning (14320): Synthesized away node "AlteraPLL:inst|altpll:altpll_component|AlteraPLL_altpll:auto_generated|wire_pll1_clk[0]"
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 27 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "Clk"
Warning (15610): No output dependent on input pin "ClkRAM"
Warning (15610): No output dependent on input pin "WR"
Warning (15610): No output dependent on input pin "AddressRAM[7]"
Warning (15610): No output dependent on input pin "AddressRAM[6]"
Warning (15610): No output dependent on input pin "AddressRAM[5]"
Warning (15610): No output dependent on input pin "AddressRAM[4]"
Warning (15610): No output dependent on input pin "AddressRAM[3]"
Warning (15610): No output dependent on input pin "AddressRAM[2]"
Warning (15610): No output dependent on input pin "AddressRAM[1]"
Warning (15610): No output dependent on input pin "AddressRAM[0]"
Warning (15610): No output dependent on input pin "DataRAM[15]"
Warning (15610): No output dependent on input pin "DataRAM[14]"
Warning (15610): No output dependent on input pin "DataRAM[13]"
Warning (15610): No output dependent on input pin "DataRAM[12]"
Warning (15610): No output dependent on input pin "DataRAM[11]"
Warning (15610): No output dependent on input pin "DataRAM[10]"
Warning (15610): No output dependent on input pin "DataRAM[9]"
Warning (15610): No output dependent on input pin "DataRAM[8]"
Warning (15610): No output dependent on input pin "DataRAM[7]"
Warning (15610): No output dependent on input pin "DataRAM[6]"
Warning (15610): No output dependent on input pin "DataRAM[5]"
Warning (15610): No output dependent on input pin "DataRAM[4]"
Warning (15610): No output dependent on input pin "DataRAM[3]"
Warning (15610): No output dependent on input pin "DataRAM[2]"
Warning (15610): No output dependent on input pin "DataRAM[1]"
Warning (15610): No output dependent on input pin "DataRAM[0]"
Info (21057): Implemented 27 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 27 input pins
Info (21059): Implemented 0 output pins
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 31 warnings
Info: Peak virtual memory: 4684 megabytes
Info: Processing ended: Mon Mar 04 16:44:59 2024
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01

426
MainController/simulation/modelsim/MainController.vho Normal file
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@ -0,0 +1,426 @@
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- VENDOR "Altera"
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"
-- DATE "03/04/2024 16:45:11"
--
-- Device: Altera EP3C25Q240C8 Package PQFP240
--
--
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
--
LIBRARY CYCLONEIII;
LIBRARY IEEE;
USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MainController IS
PORT (
Clk : IN std_logic;
ClkRAM : IN std_logic;
WR : IN std_logic;
AddressRAM : IN std_logic_vector(7 DOWNTO 0);
DataRAM : IN std_logic_vector(15 DOWNTO 0)
);
END MainController;
-- Design Ports Information
-- Clk => Location: PIN_81, I/O Standard: 2.5 V, Current Strength: Default
-- ClkRAM => Location: PIN_127, I/O Standard: 2.5 V, Current Strength: Default
-- WR => Location: PIN_98, I/O Standard: 2.5 V, Current Strength: Default
-- AddressRAM[7] => Location: PIN_41, I/O Standard: 2.5 V, Current Strength: Default
-- AddressRAM[6] => Location: PIN_132, I/O Standard: 2.5 V, Current Strength: Default
-- AddressRAM[5] => Location: PIN_230, I/O Standard: 2.5 V, Current Strength: Default
-- AddressRAM[4] => Location: PIN_135, I/O Standard: 2.5 V, Current Strength: Default
-- AddressRAM[3] => Location: PIN_65, I/O Standard: 2.5 V, Current Strength: Default
-- AddressRAM[2] => Location: PIN_181, I/O Standard: 2.5 V, Current Strength: Default
-- AddressRAM[1] => Location: PIN_64, I/O Standard: 2.5 V, Current Strength: Default
-- AddressRAM[0] => Location: PIN_173, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[15] => Location: PIN_103, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[14] => Location: PIN_145, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[13] => Location: PIN_38, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[12] => Location: PIN_144, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[11] => Location: PIN_160, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[10] => Location: PIN_149, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[9] => Location: PIN_150, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[8] => Location: PIN_133, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[7] => Location: PIN_151, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[6] => Location: PIN_152, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[5] => Location: PIN_197, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[4] => Location: PIN_113, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[3] => Location: PIN_161, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[2] => Location: PIN_168, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[1] => Location: PIN_166, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[0] => Location: PIN_119, I/O Standard: 2.5 V, Current Strength: Default
ARCHITECTURE structure OF MainController IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_Clk : std_logic;
SIGNAL ww_ClkRAM : std_logic;
SIGNAL ww_WR : std_logic;
SIGNAL ww_AddressRAM : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_DataRAM : std_logic_vector(15 DOWNTO 0);
SIGNAL \Clk~input_o\ : std_logic;
SIGNAL \ClkRAM~input_o\ : std_logic;
SIGNAL \WR~input_o\ : std_logic;
SIGNAL \AddressRAM[7]~input_o\ : std_logic;
SIGNAL \AddressRAM[6]~input_o\ : std_logic;
SIGNAL \AddressRAM[5]~input_o\ : std_logic;
SIGNAL \AddressRAM[4]~input_o\ : std_logic;
SIGNAL \AddressRAM[3]~input_o\ : std_logic;
SIGNAL \AddressRAM[2]~input_o\ : std_logic;
SIGNAL \AddressRAM[1]~input_o\ : std_logic;
SIGNAL \AddressRAM[0]~input_o\ : std_logic;
SIGNAL \DataRAM[15]~input_o\ : std_logic;
SIGNAL \DataRAM[14]~input_o\ : std_logic;
SIGNAL \DataRAM[13]~input_o\ : std_logic;
SIGNAL \DataRAM[12]~input_o\ : std_logic;
SIGNAL \DataRAM[11]~input_o\ : std_logic;
SIGNAL \DataRAM[10]~input_o\ : std_logic;
SIGNAL \DataRAM[9]~input_o\ : std_logic;
SIGNAL \DataRAM[8]~input_o\ : std_logic;
SIGNAL \DataRAM[7]~input_o\ : std_logic;
SIGNAL \DataRAM[6]~input_o\ : std_logic;
SIGNAL \DataRAM[5]~input_o\ : std_logic;
SIGNAL \DataRAM[4]~input_o\ : std_logic;
SIGNAL \DataRAM[3]~input_o\ : std_logic;
SIGNAL \DataRAM[2]~input_o\ : std_logic;
SIGNAL \DataRAM[1]~input_o\ : std_logic;
SIGNAL \DataRAM[0]~input_o\ : std_logic;
BEGIN
ww_Clk <= Clk;
ww_ClkRAM <= ClkRAM;
ww_WR <= WR;
ww_AddressRAM <= AddressRAM;
ww_DataRAM <= DataRAM;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
-- Location: IOIBUF_X14_Y0_N8
\Clk~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_Clk,
o => \Clk~input_o\);
-- Location: IOIBUF_X53_Y6_N15
\ClkRAM~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_ClkRAM,
o => \ClkRAM~input_o\);
-- Location: IOIBUF_X34_Y0_N22
\WR~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_WR,
o => \WR~input_o\);
-- Location: IOIBUF_X0_Y12_N1
\AddressRAM[7]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_AddressRAM(7),
o => \AddressRAM[7]~input_o\);
-- Location: IOIBUF_X53_Y9_N15
\AddressRAM[6]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_AddressRAM(6),
o => \AddressRAM[6]~input_o\);
-- Location: IOIBUF_X14_Y34_N8
\AddressRAM[5]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_AddressRAM(5),
o => \AddressRAM[5]~input_o\);
-- Location: IOIBUF_X53_Y10_N15
\AddressRAM[4]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_AddressRAM(4),
o => \AddressRAM[4]~input_o\);
-- Location: IOIBUF_X3_Y0_N22
\AddressRAM[3]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_AddressRAM(3),
o => \AddressRAM[3]~input_o\);
-- Location: IOIBUF_X51_Y34_N8
\AddressRAM[2]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_AddressRAM(2),
o => \AddressRAM[2]~input_o\);
-- Location: IOIBUF_X1_Y0_N1
\AddressRAM[1]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_AddressRAM(1),
o => \AddressRAM[1]~input_o\);
-- Location: IOIBUF_X53_Y26_N22
\AddressRAM[0]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_AddressRAM(0),
o => \AddressRAM[0]~input_o\);
-- Location: IOIBUF_X36_Y0_N8
\DataRAM[15]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(15),
o => \DataRAM[15]~input_o\);
-- Location: IOIBUF_X53_Y14_N1
\DataRAM[14]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(14),
o => \DataRAM[14]~input_o\);
-- Location: IOIBUF_X0_Y14_N8
\DataRAM[13]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(13),
o => \DataRAM[13]~input_o\);
-- Location: IOIBUF_X53_Y14_N8
\DataRAM[12]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(12),
o => \DataRAM[12]~input_o\);
-- Location: IOIBUF_X53_Y20_N15
\DataRAM[11]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(11),
o => \DataRAM[11]~input_o\);
-- Location: IOIBUF_X53_Y17_N22
\DataRAM[10]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(10),
o => \DataRAM[10]~input_o\);
-- Location: IOIBUF_X53_Y17_N15
\DataRAM[9]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(9),
o => \DataRAM[9]~input_o\);
-- Location: IOIBUF_X53_Y9_N8
\DataRAM[8]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(8),
o => \DataRAM[8]~input_o\);
-- Location: IOIBUF_X53_Y17_N8
\DataRAM[7]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(7),
o => \DataRAM[7]~input_o\);
-- Location: IOIBUF_X53_Y17_N1
\DataRAM[6]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(6),
o => \DataRAM[6]~input_o\);
-- Location: IOIBUF_X38_Y34_N22
\DataRAM[5]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(5),
o => \DataRAM[5]~input_o\);
-- Location: IOIBUF_X45_Y0_N15
\DataRAM[4]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(4),
o => \DataRAM[4]~input_o\);
-- Location: IOIBUF_X53_Y21_N22
\DataRAM[3]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(3),
o => \DataRAM[3]~input_o\);
-- Location: IOIBUF_X53_Y23_N15
\DataRAM[2]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(2),
o => \DataRAM[2]~input_o\);
-- Location: IOIBUF_X53_Y22_N1
\DataRAM[1]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(1),
o => \DataRAM[1]~input_o\);
-- Location: IOIBUF_X51_Y0_N15
\DataRAM[0]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(0),
o => \DataRAM[0]~input_o\);
END structure;