427 lines
12 KiB
VHDL
427 lines
12 KiB
VHDL
-- Copyright (C) 1991-2013 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, Altera MegaCore Function License
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-- Agreement, or other applicable license agreement, including,
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-- without limitation, that your use is for the sole purpose of
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-- programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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-- VENDOR "Altera"
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-- PROGRAM "Quartus II 64-Bit"
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-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"
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-- DATE "03/04/2024 16:45:11"
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--
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-- Device: Altera EP3C25Q240C8 Package PQFP240
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--
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--
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-- This VHDL file should be used for ModelSim-Altera (VHDL) only
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--
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LIBRARY CYCLONEIII;
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LIBRARY IEEE;
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USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
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USE IEEE.STD_LOGIC_1164.ALL;
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ENTITY MainController IS
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PORT (
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Clk : IN std_logic;
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ClkRAM : IN std_logic;
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WR : IN std_logic;
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AddressRAM : IN std_logic_vector(7 DOWNTO 0);
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DataRAM : IN std_logic_vector(15 DOWNTO 0)
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);
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END MainController;
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-- Design Ports Information
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-- Clk => Location: PIN_81, I/O Standard: 2.5 V, Current Strength: Default
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-- ClkRAM => Location: PIN_127, I/O Standard: 2.5 V, Current Strength: Default
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-- WR => Location: PIN_98, I/O Standard: 2.5 V, Current Strength: Default
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-- AddressRAM[7] => Location: PIN_41, I/O Standard: 2.5 V, Current Strength: Default
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-- AddressRAM[6] => Location: PIN_132, I/O Standard: 2.5 V, Current Strength: Default
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-- AddressRAM[5] => Location: PIN_230, I/O Standard: 2.5 V, Current Strength: Default
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-- AddressRAM[4] => Location: PIN_135, I/O Standard: 2.5 V, Current Strength: Default
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-- AddressRAM[3] => Location: PIN_65, I/O Standard: 2.5 V, Current Strength: Default
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-- AddressRAM[2] => Location: PIN_181, I/O Standard: 2.5 V, Current Strength: Default
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-- AddressRAM[1] => Location: PIN_64, I/O Standard: 2.5 V, Current Strength: Default
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-- AddressRAM[0] => Location: PIN_173, I/O Standard: 2.5 V, Current Strength: Default
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-- DataRAM[15] => Location: PIN_103, I/O Standard: 2.5 V, Current Strength: Default
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-- DataRAM[14] => Location: PIN_145, I/O Standard: 2.5 V, Current Strength: Default
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-- DataRAM[13] => Location: PIN_38, I/O Standard: 2.5 V, Current Strength: Default
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-- DataRAM[12] => Location: PIN_144, I/O Standard: 2.5 V, Current Strength: Default
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-- DataRAM[11] => Location: PIN_160, I/O Standard: 2.5 V, Current Strength: Default
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-- DataRAM[10] => Location: PIN_149, I/O Standard: 2.5 V, Current Strength: Default
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-- DataRAM[9] => Location: PIN_150, I/O Standard: 2.5 V, Current Strength: Default
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-- DataRAM[8] => Location: PIN_133, I/O Standard: 2.5 V, Current Strength: Default
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-- DataRAM[7] => Location: PIN_151, I/O Standard: 2.5 V, Current Strength: Default
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-- DataRAM[6] => Location: PIN_152, I/O Standard: 2.5 V, Current Strength: Default
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-- DataRAM[5] => Location: PIN_197, I/O Standard: 2.5 V, Current Strength: Default
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-- DataRAM[4] => Location: PIN_113, I/O Standard: 2.5 V, Current Strength: Default
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-- DataRAM[3] => Location: PIN_161, I/O Standard: 2.5 V, Current Strength: Default
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-- DataRAM[2] => Location: PIN_168, I/O Standard: 2.5 V, Current Strength: Default
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-- DataRAM[1] => Location: PIN_166, I/O Standard: 2.5 V, Current Strength: Default
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-- DataRAM[0] => Location: PIN_119, I/O Standard: 2.5 V, Current Strength: Default
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ARCHITECTURE structure OF MainController IS
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SIGNAL gnd : std_logic := '0';
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SIGNAL vcc : std_logic := '1';
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SIGNAL unknown : std_logic := 'X';
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SIGNAL devoe : std_logic := '1';
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SIGNAL devclrn : std_logic := '1';
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SIGNAL devpor : std_logic := '1';
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SIGNAL ww_devoe : std_logic;
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SIGNAL ww_devclrn : std_logic;
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SIGNAL ww_devpor : std_logic;
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SIGNAL ww_Clk : std_logic;
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SIGNAL ww_ClkRAM : std_logic;
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SIGNAL ww_WR : std_logic;
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SIGNAL ww_AddressRAM : std_logic_vector(7 DOWNTO 0);
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SIGNAL ww_DataRAM : std_logic_vector(15 DOWNTO 0);
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SIGNAL \Clk~input_o\ : std_logic;
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SIGNAL \ClkRAM~input_o\ : std_logic;
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SIGNAL \WR~input_o\ : std_logic;
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SIGNAL \AddressRAM[7]~input_o\ : std_logic;
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SIGNAL \AddressRAM[6]~input_o\ : std_logic;
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SIGNAL \AddressRAM[5]~input_o\ : std_logic;
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SIGNAL \AddressRAM[4]~input_o\ : std_logic;
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SIGNAL \AddressRAM[3]~input_o\ : std_logic;
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SIGNAL \AddressRAM[2]~input_o\ : std_logic;
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SIGNAL \AddressRAM[1]~input_o\ : std_logic;
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SIGNAL \AddressRAM[0]~input_o\ : std_logic;
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SIGNAL \DataRAM[15]~input_o\ : std_logic;
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SIGNAL \DataRAM[14]~input_o\ : std_logic;
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SIGNAL \DataRAM[13]~input_o\ : std_logic;
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SIGNAL \DataRAM[12]~input_o\ : std_logic;
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SIGNAL \DataRAM[11]~input_o\ : std_logic;
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SIGNAL \DataRAM[10]~input_o\ : std_logic;
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SIGNAL \DataRAM[9]~input_o\ : std_logic;
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SIGNAL \DataRAM[8]~input_o\ : std_logic;
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SIGNAL \DataRAM[7]~input_o\ : std_logic;
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SIGNAL \DataRAM[6]~input_o\ : std_logic;
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SIGNAL \DataRAM[5]~input_o\ : std_logic;
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SIGNAL \DataRAM[4]~input_o\ : std_logic;
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SIGNAL \DataRAM[3]~input_o\ : std_logic;
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SIGNAL \DataRAM[2]~input_o\ : std_logic;
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SIGNAL \DataRAM[1]~input_o\ : std_logic;
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SIGNAL \DataRAM[0]~input_o\ : std_logic;
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BEGIN
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ww_Clk <= Clk;
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ww_ClkRAM <= ClkRAM;
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ww_WR <= WR;
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ww_AddressRAM <= AddressRAM;
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ww_DataRAM <= DataRAM;
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ww_devoe <= devoe;
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ww_devclrn <= devclrn;
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ww_devpor <= devpor;
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-- Location: IOIBUF_X14_Y0_N8
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\Clk~input\ : cycloneiii_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_Clk,
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o => \Clk~input_o\);
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-- Location: IOIBUF_X53_Y6_N15
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\ClkRAM~input\ : cycloneiii_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_ClkRAM,
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o => \ClkRAM~input_o\);
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-- Location: IOIBUF_X34_Y0_N22
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\WR~input\ : cycloneiii_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_WR,
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o => \WR~input_o\);
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-- Location: IOIBUF_X0_Y12_N1
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\AddressRAM[7]~input\ : cycloneiii_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_AddressRAM(7),
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o => \AddressRAM[7]~input_o\);
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-- Location: IOIBUF_X53_Y9_N15
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\AddressRAM[6]~input\ : cycloneiii_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_AddressRAM(6),
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o => \AddressRAM[6]~input_o\);
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-- Location: IOIBUF_X14_Y34_N8
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\AddressRAM[5]~input\ : cycloneiii_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_AddressRAM(5),
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o => \AddressRAM[5]~input_o\);
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-- Location: IOIBUF_X53_Y10_N15
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\AddressRAM[4]~input\ : cycloneiii_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_AddressRAM(4),
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o => \AddressRAM[4]~input_o\);
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-- Location: IOIBUF_X3_Y0_N22
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\AddressRAM[3]~input\ : cycloneiii_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_AddressRAM(3),
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o => \AddressRAM[3]~input_o\);
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-- Location: IOIBUF_X51_Y34_N8
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\AddressRAM[2]~input\ : cycloneiii_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_AddressRAM(2),
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o => \AddressRAM[2]~input_o\);
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-- Location: IOIBUF_X1_Y0_N1
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\AddressRAM[1]~input\ : cycloneiii_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_AddressRAM(1),
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o => \AddressRAM[1]~input_o\);
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-- Location: IOIBUF_X53_Y26_N22
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\AddressRAM[0]~input\ : cycloneiii_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_AddressRAM(0),
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o => \AddressRAM[0]~input_o\);
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-- Location: IOIBUF_X36_Y0_N8
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\DataRAM[15]~input\ : cycloneiii_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_DataRAM(15),
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o => \DataRAM[15]~input_o\);
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-- Location: IOIBUF_X53_Y14_N1
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\DataRAM[14]~input\ : cycloneiii_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_DataRAM(14),
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o => \DataRAM[14]~input_o\);
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-- Location: IOIBUF_X0_Y14_N8
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\DataRAM[13]~input\ : cycloneiii_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_DataRAM(13),
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o => \DataRAM[13]~input_o\);
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-- Location: IOIBUF_X53_Y14_N8
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\DataRAM[12]~input\ : cycloneiii_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_DataRAM(12),
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o => \DataRAM[12]~input_o\);
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-- Location: IOIBUF_X53_Y20_N15
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\DataRAM[11]~input\ : cycloneiii_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_DataRAM(11),
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o => \DataRAM[11]~input_o\);
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-- Location: IOIBUF_X53_Y17_N22
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\DataRAM[10]~input\ : cycloneiii_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_DataRAM(10),
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o => \DataRAM[10]~input_o\);
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-- Location: IOIBUF_X53_Y17_N15
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\DataRAM[9]~input\ : cycloneiii_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_DataRAM(9),
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o => \DataRAM[9]~input_o\);
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-- Location: IOIBUF_X53_Y9_N8
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\DataRAM[8]~input\ : cycloneiii_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_DataRAM(8),
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o => \DataRAM[8]~input_o\);
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-- Location: IOIBUF_X53_Y17_N8
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\DataRAM[7]~input\ : cycloneiii_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_DataRAM(7),
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o => \DataRAM[7]~input_o\);
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-- Location: IOIBUF_X53_Y17_N1
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\DataRAM[6]~input\ : cycloneiii_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_DataRAM(6),
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o => \DataRAM[6]~input_o\);
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-- Location: IOIBUF_X38_Y34_N22
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\DataRAM[5]~input\ : cycloneiii_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_DataRAM(5),
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o => \DataRAM[5]~input_o\);
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-- Location: IOIBUF_X45_Y0_N15
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\DataRAM[4]~input\ : cycloneiii_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_DataRAM(4),
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o => \DataRAM[4]~input_o\);
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-- Location: IOIBUF_X53_Y21_N22
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\DataRAM[3]~input\ : cycloneiii_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_DataRAM(3),
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o => \DataRAM[3]~input_o\);
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-- Location: IOIBUF_X53_Y23_N15
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\DataRAM[2]~input\ : cycloneiii_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_DataRAM(2),
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o => \DataRAM[2]~input_o\);
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-- Location: IOIBUF_X53_Y22_N1
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\DataRAM[1]~input\ : cycloneiii_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_DataRAM(1),
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o => \DataRAM[1]~input_o\);
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-- Location: IOIBUF_X51_Y0_N15
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\DataRAM[0]~input\ : cycloneiii_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_DataRAM(0),
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o => \DataRAM[0]~input_o\);
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END structure;
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