altera/MainController/simulation/modelsim/MainController.vho

-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"

-- DATE "03/12/2024 17:46:57"

-- 
-- Device: Altera EP3C25Q240C8 Package PQFP240
-- 

-- 
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
-- 

LIBRARY ALTERA;
LIBRARY CYCLONEIII;
LIBRARY IEEE;
USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY 	MainController IS
    PORT (
	FPGA_LED_1 : OUT std_logic;
	FPGA_CLK : IN std_logic;
	FPGA_LED_2 : OUT std_logic;
	FPGA_LED_3 : OUT std_logic;
	Data : INOUT std_logic_vector(7 DOWNTO 0);
	nWE : IN std_logic;
	nOE : IN std_logic;
	nCE : IN std_logic;
	Address : IN std_logic_vector(7 DOWNTO 0)
	);
END MainController;

-- Design Ports Information
-- FPGA_LED_1	=>  Location: PIN_166,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
-- FPGA_LED_2	=>  Location: PIN_167,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
-- FPGA_LED_3	=>  Location: PIN_168,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
-- Data[7]	=>  Location: PIN_221,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
-- Data[6]	=>  Location: PIN_223,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
-- Data[5]	=>  Location: PIN_224,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
-- Data[4]	=>  Location: PIN_226,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
-- Data[3]	=>  Location: PIN_187,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
-- Data[2]	=>  Location: PIN_188,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
-- Data[1]	=>  Location: PIN_189,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
-- Data[0]	=>  Location: PIN_194,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
-- FPGA_CLK	=>  Location: PIN_31,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
-- nCE	=>  Location: PIN_219,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
-- nWE	=>  Location: PIN_218,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
-- Address[0]	=>  Location: PIN_196,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
-- Address[1]	=>  Location: PIN_231,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
-- Address[2]	=>  Location: PIN_234,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
-- Address[3]	=>  Location: PIN_233,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
-- Address[4]	=>  Location: PIN_232,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
-- Address[5]	=>  Location: PIN_235,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
-- Address[6]	=>  Location: PIN_230,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
-- Address[7]	=>  Location: PIN_195,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
-- nOE	=>  Location: PIN_217,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default


ARCHITECTURE structure OF MainController IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_FPGA_LED_1 : std_logic;
SIGNAL ww_FPGA_CLK : std_logic;
SIGNAL ww_FPGA_LED_2 : std_logic;
SIGNAL ww_FPGA_LED_3 : std_logic;
SIGNAL ww_nWE : std_logic;
SIGNAL ww_nOE : std_logic;
SIGNAL ww_nCE : std_logic;
SIGNAL ww_Address : std_logic_vector(7 DOWNTO 0);
SIGNAL \inst|altpll_component|auto_generated|pll1_INCLK_bus\ : std_logic_vector(1 DOWNTO 0);
SIGNAL \inst|altpll_component|auto_generated|pll1_CLK_bus\ : std_logic_vector(4 DOWNTO 0);
SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(35 DOWNTO 0);
SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(35 DOWNTO 0);
SIGNAL \inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \FPGA_CLK~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \FPGA_CLK~input_o\ : std_logic;
SIGNAL \FPGA_CLK~inputclkctrl_outclk\ : std_logic;
SIGNAL \nCE~input_o\ : std_logic;
SIGNAL \Address[5]~input_o\ : std_logic;
SIGNAL \inst3|ce0Prev~q\ : std_logic;
SIGNAL \inst3|addr~5_combout\ : std_logic;
SIGNAL \inst3|memory_rtl_0_bypass[12]~feeder_combout\ : std_logic;
SIGNAL \nWE~input_o\ : std_logic;
SIGNAL \inst3|we0Prev~q\ : std_logic;
SIGNAL \nOE~input_o\ : std_logic;
SIGNAL \inst3|Selector3~3_combout\ : std_logic;
SIGNAL \inst3|Selector3~2_combout\ : std_logic;
SIGNAL \inst3|stateMM0.Writing~q\ : std_logic;
SIGNAL \inst3|memory~48_combout\ : std_logic;
SIGNAL \inst3|oe0Prev~q\ : std_logic;
SIGNAL \inst3|Selector3~0_combout\ : std_logic;
SIGNAL \inst3|Selector3~1_combout\ : std_logic;
SIGNAL \inst3|Selector2~0_combout\ : std_logic;
SIGNAL \inst3|stateMM0.Waiting~q\ : std_logic;
SIGNAL \inst3|memory_rtl_0_bypass[11]~feeder_combout\ : std_logic;
SIGNAL \Address[4]~input_o\ : std_logic;
SIGNAL \inst3|addr~4_combout\ : std_logic;
SIGNAL \inst3|memory~37_combout\ : std_logic;
SIGNAL \Address[2]~input_o\ : std_logic;
SIGNAL \inst3|addr~2_combout\ : std_logic;
SIGNAL \inst3|memory_rtl_0_bypass[6]~feeder_combout\ : std_logic;
SIGNAL \Address[3]~input_o\ : std_logic;
SIGNAL \inst3|addr~3_combout\ : std_logic;
SIGNAL \inst3|memory~35_combout\ : std_logic;
SIGNAL \Address[0]~input_o\ : std_logic;
SIGNAL \inst3|addr~0_combout\ : std_logic;
SIGNAL \inst3|memory_rtl_0_bypass[2]~feeder_combout\ : std_logic;
SIGNAL \Address[1]~input_o\ : std_logic;
SIGNAL \inst3|addr~1_combout\ : std_logic;
SIGNAL \inst3|memory_rtl_0_bypass[4]~feeder_combout\ : std_logic;
SIGNAL \inst3|memory~34_combout\ : std_logic;
SIGNAL \inst3|memory~36_combout\ : std_logic;
SIGNAL \Address[7]~input_o\ : std_logic;
SIGNAL \inst3|addr~7_combout\ : std_logic;
SIGNAL \Address[6]~input_o\ : std_logic;
SIGNAL \inst3|addr~6_combout\ : std_logic;
SIGNAL \inst3|memory_rtl_0_bypass[13]~feeder_combout\ : std_logic;
SIGNAL \inst3|memory_rtl_0_bypass[16]~feeder_combout\ : std_logic;
SIGNAL \inst3|memory~38_combout\ : std_logic;
SIGNAL \inst3|memory~39_combout\ : std_logic;
SIGNAL \inst3|stateMM0.Waiting~_wirecell_combout\ : std_logic;
SIGNAL \Data[0]~input_o\ : std_logic;
SIGNAL \Data[1]~input_o\ : std_logic;
SIGNAL \Data[2]~input_o\ : std_logic;
SIGNAL \Data[3]~input_o\ : std_logic;
SIGNAL \Data[4]~input_o\ : std_logic;
SIGNAL \Data[5]~input_o\ : std_logic;
SIGNAL \Data[6]~input_o\ : std_logic;
SIGNAL \Data[7]~input_o\ : std_logic;
SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a7\ : std_logic;
SIGNAL \inst3|memory_rtl_0_bypass[24]~feeder_combout\ : std_logic;
SIGNAL \inst3|memory~40_combout\ : std_logic;
SIGNAL \inst3|Selector4~0_combout\ : std_logic;
SIGNAL \inst3|stateMM0.Reading~q\ : std_logic;
SIGNAL \inst3|Selector74~0_combout\ : std_logic;
SIGNAL \inst3|data0[7]~reg0_q\ : std_logic;
SIGNAL \inst3|data0[7]~enfeeder_combout\ : std_logic;
SIGNAL \inst3|data0[7]~en_q\ : std_logic;
SIGNAL \inst3|memory_rtl_0_bypass[23]~feeder_combout\ : std_logic;
SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a6\ : std_logic;
SIGNAL \inst3|memory~41_combout\ : std_logic;
SIGNAL \inst3|data0[6]~reg0_q\ : std_logic;
SIGNAL \inst3|data0[6]~enfeeder_combout\ : std_logic;
SIGNAL \inst3|data0[6]~en_q\ : std_logic;
SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a5\ : std_logic;
SIGNAL \inst3|memory_rtl_0_bypass[22]~feeder_combout\ : std_logic;
SIGNAL \inst3|memory~42_combout\ : std_logic;
SIGNAL \inst3|data0[5]~reg0_q\ : std_logic;
SIGNAL \inst3|data0[5]~enfeeder_combout\ : std_logic;
SIGNAL \inst3|data0[5]~en_q\ : std_logic;
SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a4\ : std_logic;
SIGNAL \inst3|memory_rtl_0_bypass[21]~feeder_combout\ : std_logic;
SIGNAL \inst3|memory~43_combout\ : std_logic;
SIGNAL \inst3|data0[4]~reg0_q\ : std_logic;
SIGNAL \inst3|data0[4]~enfeeder_combout\ : std_logic;
SIGNAL \inst3|data0[4]~en_q\ : std_logic;
SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a3\ : std_logic;
SIGNAL \inst3|memory~44_combout\ : std_logic;
SIGNAL \inst3|data0[3]~reg0_q\ : std_logic;
SIGNAL \inst3|data0[3]~enfeeder_combout\ : std_logic;
SIGNAL \inst3|data0[3]~en_q\ : std_logic;
SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a2\ : std_logic;
SIGNAL \inst3|memory~45_combout\ : std_logic;
SIGNAL \inst3|data0[2]~reg0_q\ : std_logic;
SIGNAL \inst3|data0[2]~enfeeder_combout\ : std_logic;
SIGNAL \inst3|data0[2]~en_q\ : std_logic;
SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a1\ : std_logic;
SIGNAL \inst3|memory~46_combout\ : std_logic;
SIGNAL \inst3|data0[1]~reg0_q\ : std_logic;
SIGNAL \inst3|data0[1]~enfeeder_combout\ : std_logic;
SIGNAL \inst3|data0[1]~en_q\ : std_logic;
SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic;
SIGNAL \inst3|memory~47_combout\ : std_logic;
SIGNAL \inst3|data0[0]~reg0_q\ : std_logic;
SIGNAL \inst3|data0[0]~enfeeder_combout\ : std_logic;
SIGNAL \inst3|data0[0]~en_q\ : std_logic;
SIGNAL \inst2|counter[0]~24_combout\ : std_logic;
SIGNAL \inst2|counter[13]~51\ : std_logic;
SIGNAL \inst2|counter[14]~52_combout\ : std_logic;
SIGNAL \inst2|counter[14]~53\ : std_logic;
SIGNAL \inst2|counter[15]~54_combout\ : std_logic;
SIGNAL \inst2|counter[15]~55\ : std_logic;
SIGNAL \inst2|counter[16]~56_combout\ : std_logic;
SIGNAL \inst2|counter[16]~57\ : std_logic;
SIGNAL \inst2|counter[17]~58_combout\ : std_logic;
SIGNAL \inst2|counter[17]~59\ : std_logic;
SIGNAL \inst2|counter[18]~60_combout\ : std_logic;
SIGNAL \inst2|counter[18]~61\ : std_logic;
SIGNAL \inst2|counter[19]~62_combout\ : std_logic;
SIGNAL \inst2|counter[19]~63\ : std_logic;
SIGNAL \inst2|counter[20]~64_combout\ : std_logic;
SIGNAL \inst2|counter[20]~65\ : std_logic;
SIGNAL \inst2|counter[21]~66_combout\ : std_logic;
SIGNAL \inst2|LessThan0~8_combout\ : std_logic;
SIGNAL \inst2|counter[21]~67\ : std_logic;
SIGNAL \inst2|counter[22]~68_combout\ : std_logic;
SIGNAL \inst2|counter[22]~69\ : std_logic;
SIGNAL \inst2|counter[23]~70_combout\ : std_logic;
SIGNAL \inst2|LessThan0~9_combout\ : std_logic;
SIGNAL \inst2|LessThan0~2_combout\ : std_logic;
SIGNAL \inst2|LessThan0~3_combout\ : std_logic;
SIGNAL \inst2|LessThan0~0_combout\ : std_logic;
SIGNAL \inst2|LessThan0~1_combout\ : std_logic;
SIGNAL \inst2|LessThan0~4_combout\ : std_logic;
SIGNAL \inst2|LessThan0~6_combout\ : std_logic;
SIGNAL \inst2|LessThan0~10_combout\ : std_logic;
SIGNAL \inst2|counter[0]~25\ : std_logic;
SIGNAL \inst2|counter[1]~26_combout\ : std_logic;
SIGNAL \inst2|counter[1]~27\ : std_logic;
SIGNAL \inst2|counter[2]~28_combout\ : std_logic;
SIGNAL \inst2|counter[2]~29\ : std_logic;
SIGNAL \inst2|counter[3]~30_combout\ : std_logic;
SIGNAL \inst2|counter[3]~31\ : std_logic;
SIGNAL \inst2|counter[4]~32_combout\ : std_logic;
SIGNAL \inst2|counter[4]~33\ : std_logic;
SIGNAL \inst2|counter[5]~34_combout\ : std_logic;
SIGNAL \inst2|counter[5]~35\ : std_logic;
SIGNAL \inst2|counter[6]~36_combout\ : std_logic;
SIGNAL \inst2|counter[6]~37\ : std_logic;
SIGNAL \inst2|counter[7]~38_combout\ : std_logic;
SIGNAL \inst2|counter[7]~39\ : std_logic;
SIGNAL \inst2|counter[8]~40_combout\ : std_logic;
SIGNAL \inst2|counter[8]~41\ : std_logic;
SIGNAL \inst2|counter[9]~42_combout\ : std_logic;
SIGNAL \inst2|counter[9]~43\ : std_logic;
SIGNAL \inst2|counter[10]~44_combout\ : std_logic;
SIGNAL \inst2|counter[10]~45\ : std_logic;
SIGNAL \inst2|counter[11]~46_combout\ : std_logic;
SIGNAL \inst2|counter[11]~47\ : std_logic;
SIGNAL \inst2|counter[12]~48_combout\ : std_logic;
SIGNAL \inst2|counter[12]~49\ : std_logic;
SIGNAL \inst2|counter[13]~50_combout\ : std_logic;
SIGNAL \inst2|LessThan0~5_combout\ : std_logic;
SIGNAL \inst2|LessThan0~7_combout\ : std_logic;
SIGNAL \inst2|ledBuf~0_combout\ : std_logic;
SIGNAL \inst2|ledBuf~q\ : std_logic;
SIGNAL \inst|altpll_component|auto_generated|wire_pll1_fbout\ : std_logic;
SIGNAL \inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk\ : std_logic;
SIGNAL \inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk\ : std_logic;
SIGNAL \inst3|addr\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \inst3|memory_rtl_0_bypass\ : std_logic_vector(0 TO 24);
SIGNAL \inst|altpll_component|auto_generated|wire_pll1_clk\ : std_logic_vector(4 DOWNTO 0);
SIGNAL \inst2|counter\ : std_logic_vector(23 DOWNTO 0);
SIGNAL \inst3|ALT_INV_stateMM0.Waiting~_wirecell_combout\ : std_logic;
SIGNAL \inst3|ALT_INV_stateMM0.Waiting~q\ : std_logic;
SIGNAL \inst2|ALT_INV_ledBuf~q\ : std_logic;

BEGIN

FPGA_LED_1 <= ww_FPGA_LED_1;
ww_FPGA_CLK <= FPGA_CLK;
FPGA_LED_2 <= ww_FPGA_LED_2;
FPGA_LED_3 <= ww_FPGA_LED_3;
ww_nWE <= nWE;
ww_nOE <= nOE;
ww_nCE <= nCE;
ww_Address <= Address;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

\inst|altpll_component|auto_generated|pll1_INCLK_bus\ <= (gnd & \FPGA_CLK~input_o\);

\inst|altpll_component|auto_generated|wire_pll1_clk\(0) <= \inst|altpll_component|auto_generated|pll1_CLK_bus\(0);
\inst|altpll_component|auto_generated|wire_pll1_clk\(1) <= \inst|altpll_component|auto_generated|pll1_CLK_bus\(1);
\inst|altpll_component|auto_generated|wire_pll1_clk\(2) <= \inst|altpll_component|auto_generated|pll1_CLK_bus\(2);
\inst|altpll_component|auto_generated|wire_pll1_clk\(3) <= \inst|altpll_component|auto_generated|pll1_CLK_bus\(3);
\inst|altpll_component|auto_generated|wire_pll1_clk\(4) <= \inst|altpll_component|auto_generated|pll1_CLK_bus\(4);

\inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & \Data[7]~input_o\
& \Data[6]~input_o\ & \Data[5]~input_o\ & \Data[4]~input_o\ & \Data[3]~input_o\ & \Data[2]~input_o\ & \Data[1]~input_o\ & \Data[0]~input_o\);

\inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\inst3|addr\(7) & \inst3|addr\(6) & \inst3|addr\(5) & \inst3|addr\(4) & \inst3|addr\(3) & \inst3|addr\(2) & \inst3|addr\(1) & \inst3|addr\(0));

\inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\inst3|addr~7_combout\ & \inst3|addr~6_combout\ & \inst3|addr~5_combout\ & \inst3|addr~4_combout\ & \inst3|addr~3_combout\ & \inst3|addr~2_combout\ & \inst3|addr~1_combout\ & 
\inst3|addr~0_combout\);

\inst3|memory_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0);
\inst3|memory_rtl_0|auto_generated|ram_block1a1\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(1);
\inst3|memory_rtl_0|auto_generated|ram_block1a2\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(2);
\inst3|memory_rtl_0|auto_generated|ram_block1a3\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(3);
\inst3|memory_rtl_0|auto_generated|ram_block1a4\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(4);
\inst3|memory_rtl_0|auto_generated|ram_block1a5\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(5);
\inst3|memory_rtl_0|auto_generated|ram_block1a6\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(6);
\inst3|memory_rtl_0|auto_generated|ram_block1a7\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(7);

\inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \inst|altpll_component|auto_generated|wire_pll1_clk\(1));

\inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \inst|altpll_component|auto_generated|wire_pll1_clk\(0));

\FPGA_CLK~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \FPGA_CLK~input_o\);
\inst3|ALT_INV_stateMM0.Waiting~_wirecell_combout\ <= NOT \inst3|stateMM0.Waiting~_wirecell_combout\;
\inst3|ALT_INV_stateMM0.Waiting~q\ <= NOT \inst3|stateMM0.Waiting~q\;
\inst2|ALT_INV_ledBuf~q\ <= NOT \inst2|ledBuf~q\;

-- Location: IOOBUF_X53_Y22_N2
\FPGA_LED_1~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst2|ALT_INV_ledBuf~q\,
	devoe => ww_devoe,
	o => ww_FPGA_LED_1);

-- Location: IOOBUF_X53_Y23_N23
\FPGA_LED_2~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk\,
	devoe => ww_devoe,
	o => ww_FPGA_LED_2);

-- Location: IOOBUF_X53_Y23_N16
\FPGA_LED_3~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk\,
	devoe => ww_devoe,
	o => ww_FPGA_LED_3);

-- Location: IOOBUF_X18_Y34_N2
\Data[7]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst3|data0[7]~reg0_q\,
	oe => \inst3|data0[7]~en_q\,
	devoe => ww_devoe,
	o => Data(7));

-- Location: IOOBUF_X18_Y34_N23
\Data[6]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst3|data0[6]~reg0_q\,
	oe => \inst3|data0[6]~en_q\,
	devoe => ww_devoe,
	o => Data(6));

-- Location: IOOBUF_X16_Y34_N2
\Data[5]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst3|data0[5]~reg0_q\,
	oe => \inst3|data0[5]~en_q\,
	devoe => ww_devoe,
	o => Data(5));

-- Location: IOOBUF_X16_Y34_N16
\Data[4]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst3|data0[4]~reg0_q\,
	oe => \inst3|data0[4]~en_q\,
	devoe => ww_devoe,
	o => Data(4));

-- Location: IOOBUF_X45_Y34_N9
\Data[3]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst3|data0[3]~reg0_q\,
	oe => \inst3|data0[3]~en_q\,
	devoe => ww_devoe,
	o => Data(3));

-- Location: IOOBUF_X45_Y34_N16
\Data[2]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst3|data0[2]~reg0_q\,
	oe => \inst3|data0[2]~en_q\,
	devoe => ww_devoe,
	o => Data(2));

-- Location: IOOBUF_X45_Y34_N23
\Data[1]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst3|data0[1]~reg0_q\,
	oe => \inst3|data0[1]~en_q\,
	devoe => ww_devoe,
	o => Data(1));

-- Location: IOOBUF_X40_Y34_N9
\Data[0]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst3|data0[0]~reg0_q\,
	oe => \inst3|data0[0]~en_q\,
	devoe => ww_devoe,
	o => Data(0));

-- Location: IOIBUF_X0_Y16_N1
\FPGA_CLK~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_FPGA_CLK,
	o => \FPGA_CLK~input_o\);

-- Location: CLKCTRL_G2
\FPGA_CLK~inputclkctrl\ : cycloneiii_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \FPGA_CLK~inputclkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \FPGA_CLK~inputclkctrl_outclk\);

-- Location: IOIBUF_X20_Y34_N15
\nCE~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_nCE,
	o => \nCE~input_o\);

-- Location: IOIBUF_X7_Y34_N15
\Address[5]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_Address(5),
	o => \Address[5]~input_o\);

-- Location: FF_X27_Y29_N31
\inst3|ce0Prev\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	asdata => \nCE~input_o\,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|ce0Prev~q\);

-- Location: LCCOMB_X34_Y24_N26
\inst3|addr~5\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|addr~5_combout\ = (!\nCE~input_o\ & (\Address[5]~input_o\ & \inst3|ce0Prev~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \nCE~input_o\,
	datac => \Address[5]~input_o\,
	datad => \inst3|ce0Prev~q\,
	combout => \inst3|addr~5_combout\);

-- Location: LCCOMB_X32_Y23_N12
\inst3|memory_rtl_0_bypass[12]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|memory_rtl_0_bypass[12]~feeder_combout\ = \inst3|addr~5_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst3|addr~5_combout\,
	combout => \inst3|memory_rtl_0_bypass[12]~feeder_combout\);

-- Location: IOIBUF_X20_Y34_N8
\nWE~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_nWE,
	o => \nWE~input_o\);

-- Location: FF_X27_Y29_N21
\inst3|we0Prev\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	asdata => \nWE~input_o\,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|we0Prev~q\);

-- Location: IOIBUF_X20_Y34_N1
\nOE~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_nOE,
	o => \nOE~input_o\);

-- Location: LCCOMB_X27_Y29_N14
\inst3|Selector3~3\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|Selector3~3_combout\ = (\nOE~input_o\ & (!\nCE~input_o\ & (\inst3|ce0Prev~q\ & !\inst3|stateMM0.Waiting~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \nOE~input_o\,
	datab => \nCE~input_o\,
	datac => \inst3|ce0Prev~q\,
	datad => \inst3|stateMM0.Waiting~q\,
	combout => \inst3|Selector3~3_combout\);

-- Location: LCCOMB_X27_Y29_N30
\inst3|Selector3~2\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|Selector3~2_combout\ = (\inst3|stateMM0.Waiting~q\ & (((\inst3|Selector3~1_combout\)))) # (!\inst3|stateMM0.Waiting~q\ & (!\nCE~input_o\ & (\inst3|ce0Prev~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101000010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|stateMM0.Waiting~q\,
	datab => \nCE~input_o\,
	datac => \inst3|ce0Prev~q\,
	datad => \inst3|Selector3~1_combout\,
	combout => \inst3|Selector3~2_combout\);

-- Location: FF_X27_Y29_N15
\inst3|stateMM0.Writing\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|Selector3~3_combout\,
	ena => \inst3|Selector3~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|stateMM0.Writing~q\);

-- Location: LCCOMB_X27_Y29_N20
\inst3|memory~48\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|memory~48_combout\ = (!\nWE~input_o\ & (\inst3|we0Prev~q\ & \inst3|stateMM0.Writing~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \nWE~input_o\,
	datac => \inst3|we0Prev~q\,
	datad => \inst3|stateMM0.Writing~q\,
	combout => \inst3|memory~48_combout\);

-- Location: FF_X27_Y29_N25
\inst3|oe0Prev\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	asdata => \nOE~input_o\,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|oe0Prev~q\);

-- Location: LCCOMB_X27_Y29_N24
\inst3|Selector3~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|Selector3~0_combout\ = (\nOE~input_o\ & (!\inst3|oe0Prev~q\ & !\inst3|stateMM0.Writing~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \nOE~input_o\,
	datac => \inst3|oe0Prev~q\,
	datad => \inst3|stateMM0.Writing~q\,
	combout => \inst3|Selector3~0_combout\);

-- Location: LCCOMB_X27_Y29_N2
\inst3|Selector3~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|Selector3~1_combout\ = (\inst3|memory~48_combout\) # ((\nCE~input_o\) # (\inst3|Selector3~0_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111101110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|memory~48_combout\,
	datab => \nCE~input_o\,
	datad => \inst3|Selector3~0_combout\,
	combout => \inst3|Selector3~1_combout\);

-- Location: LCCOMB_X27_Y29_N8
\inst3|Selector2~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|Selector2~0_combout\ = (\inst3|stateMM0.Waiting~q\ & (((!\inst3|Selector3~1_combout\)))) # (!\inst3|stateMM0.Waiting~q\ & (\inst3|ce0Prev~q\ & (!\nCE~input_o\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000001011110010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|ce0Prev~q\,
	datab => \nCE~input_o\,
	datac => \inst3|stateMM0.Waiting~q\,
	datad => \inst3|Selector3~1_combout\,
	combout => \inst3|Selector2~0_combout\);

-- Location: FF_X27_Y29_N9
\inst3|stateMM0.Waiting\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|Selector2~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|stateMM0.Waiting~q\);

-- Location: FF_X32_Y23_N13
\inst3|memory_rtl_0_bypass[12]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|memory_rtl_0_bypass[12]~feeder_combout\,
	ena => \inst3|ALT_INV_stateMM0.Waiting~q\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|memory_rtl_0_bypass\(12));

-- Location: FF_X34_Y24_N27
\inst3|addr[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|addr~5_combout\,
	ena => \inst3|ALT_INV_stateMM0.Waiting~q\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|addr\(5));

-- Location: LCCOMB_X32_Y23_N2
\inst3|memory_rtl_0_bypass[11]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|memory_rtl_0_bypass[11]~feeder_combout\ = \inst3|addr\(5)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst3|addr\(5),
	combout => \inst3|memory_rtl_0_bypass[11]~feeder_combout\);

-- Location: FF_X32_Y23_N3
\inst3|memory_rtl_0_bypass[11]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|memory_rtl_0_bypass[11]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|memory_rtl_0_bypass\(11));

-- Location: IOIBUF_X14_Y34_N22
\Address[4]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_Address(4),
	o => \Address[4]~input_o\);

-- Location: LCCOMB_X34_Y24_N0
\inst3|addr~4\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|addr~4_combout\ = (!\nCE~input_o\ & (\Address[4]~input_o\ & \inst3|ce0Prev~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \nCE~input_o\,
	datac => \Address[4]~input_o\,
	datad => \inst3|ce0Prev~q\,
	combout => \inst3|addr~4_combout\);

-- Location: FF_X32_Y23_N7
\inst3|memory_rtl_0_bypass[10]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	asdata => \inst3|addr~4_combout\,
	sload => VCC,
	ena => \inst3|ALT_INV_stateMM0.Waiting~q\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|memory_rtl_0_bypass\(10));

-- Location: FF_X34_Y24_N1
\inst3|addr[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|addr~4_combout\,
	ena => \inst3|ALT_INV_stateMM0.Waiting~q\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|addr\(4));

-- Location: FF_X32_Y23_N1
\inst3|memory_rtl_0_bypass[9]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	asdata => \inst3|addr\(4),
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|memory_rtl_0_bypass\(9));

-- Location: LCCOMB_X32_Y23_N6
\inst3|memory~37\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|memory~37_combout\ = (\inst3|memory_rtl_0_bypass\(12) & (\inst3|memory_rtl_0_bypass\(11) & (\inst3|memory_rtl_0_bypass\(10) $ (!\inst3|memory_rtl_0_bypass\(9))))) # (!\inst3|memory_rtl_0_bypass\(12) & (!\inst3|memory_rtl_0_bypass\(11) & 
-- (\inst3|memory_rtl_0_bypass\(10) $ (!\inst3|memory_rtl_0_bypass\(9)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1001000000001001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|memory_rtl_0_bypass\(12),
	datab => \inst3|memory_rtl_0_bypass\(11),
	datac => \inst3|memory_rtl_0_bypass\(10),
	datad => \inst3|memory_rtl_0_bypass\(9),
	combout => \inst3|memory~37_combout\);

-- Location: IOIBUF_X7_Y34_N8
\Address[2]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_Address(2),
	o => \Address[2]~input_o\);

-- Location: LCCOMB_X34_Y24_N12
\inst3|addr~2\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|addr~2_combout\ = (!\nCE~input_o\ & (\Address[2]~input_o\ & \inst3|ce0Prev~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \nCE~input_o\,
	datac => \Address[2]~input_o\,
	datad => \inst3|ce0Prev~q\,
	combout => \inst3|addr~2_combout\);

-- Location: LCCOMB_X34_Y24_N14
\inst3|memory_rtl_0_bypass[6]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|memory_rtl_0_bypass[6]~feeder_combout\ = \inst3|addr~2_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst3|addr~2_combout\,
	combout => \inst3|memory_rtl_0_bypass[6]~feeder_combout\);

-- Location: FF_X34_Y24_N15
\inst3|memory_rtl_0_bypass[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|memory_rtl_0_bypass[6]~feeder_combout\,
	ena => \inst3|ALT_INV_stateMM0.Waiting~q\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|memory_rtl_0_bypass\(6));

-- Location: IOIBUF_X7_Y34_N1
\Address[3]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_Address(3),
	o => \Address[3]~input_o\);

-- Location: LCCOMB_X34_Y24_N30
\inst3|addr~3\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|addr~3_combout\ = (\inst3|ce0Prev~q\ & (\Address[3]~input_o\ & !\nCE~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|ce0Prev~q\,
	datab => \Address[3]~input_o\,
	datad => \nCE~input_o\,
	combout => \inst3|addr~3_combout\);

-- Location: FF_X34_Y24_N31
\inst3|addr[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|addr~3_combout\,
	ena => \inst3|ALT_INV_stateMM0.Waiting~q\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|addr\(3));

-- Location: FF_X27_Y29_N1
\inst3|memory_rtl_0_bypass[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	asdata => \inst3|addr\(3),
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|memory_rtl_0_bypass\(7));

-- Location: FF_X34_Y24_N13
\inst3|addr[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|addr~2_combout\,
	ena => \inst3|ALT_INV_stateMM0.Waiting~q\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|addr\(2));

-- Location: FF_X27_Y29_N23
\inst3|memory_rtl_0_bypass[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	asdata => \inst3|addr\(2),
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|memory_rtl_0_bypass\(5));

-- Location: FF_X34_Y24_N5
\inst3|memory_rtl_0_bypass[8]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	asdata => \inst3|addr~3_combout\,
	sload => VCC,
	ena => \inst3|ALT_INV_stateMM0.Waiting~q\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|memory_rtl_0_bypass\(8));

-- Location: LCCOMB_X27_Y29_N22
\inst3|memory~35\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|memory~35_combout\ = (\inst3|memory_rtl_0_bypass\(6) & (\inst3|memory_rtl_0_bypass\(5) & (\inst3|memory_rtl_0_bypass\(7) $ (!\inst3|memory_rtl_0_bypass\(8))))) # (!\inst3|memory_rtl_0_bypass\(6) & (!\inst3|memory_rtl_0_bypass\(5) & 
-- (\inst3|memory_rtl_0_bypass\(7) $ (!\inst3|memory_rtl_0_bypass\(8)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000010000100001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|memory_rtl_0_bypass\(6),
	datab => \inst3|memory_rtl_0_bypass\(7),
	datac => \inst3|memory_rtl_0_bypass\(5),
	datad => \inst3|memory_rtl_0_bypass\(8),
	combout => \inst3|memory~35_combout\);

-- Location: IOIBUF_X38_Y34_N15
\Address[0]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_Address(0),
	o => \Address[0]~input_o\);

-- Location: LCCOMB_X34_Y24_N24
\inst3|addr~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|addr~0_combout\ = (\inst3|ce0Prev~q\ & (!\nCE~input_o\ & \Address[0]~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010000000100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|ce0Prev~q\,
	datab => \nCE~input_o\,
	datac => \Address[0]~input_o\,
	combout => \inst3|addr~0_combout\);

-- Location: LCCOMB_X34_Y24_N18
\inst3|memory_rtl_0_bypass[2]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|memory_rtl_0_bypass[2]~feeder_combout\ = \inst3|addr~0_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst3|addr~0_combout\,
	combout => \inst3|memory_rtl_0_bypass[2]~feeder_combout\);

-- Location: FF_X34_Y24_N19
\inst3|memory_rtl_0_bypass[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|memory_rtl_0_bypass[2]~feeder_combout\,
	ena => \inst3|ALT_INV_stateMM0.Waiting~q\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|memory_rtl_0_bypass\(2));

-- Location: IOIBUF_X14_Y34_N15
\Address[1]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_Address(1),
	o => \Address[1]~input_o\);

-- Location: LCCOMB_X34_Y24_N2
\inst3|addr~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|addr~1_combout\ = (\Address[1]~input_o\ & (!\nCE~input_o\ & \inst3|ce0Prev~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010001000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \Address[1]~input_o\,
	datab => \nCE~input_o\,
	datad => \inst3|ce0Prev~q\,
	combout => \inst3|addr~1_combout\);

-- Location: FF_X34_Y24_N3
\inst3|addr[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|addr~1_combout\,
	ena => \inst3|ALT_INV_stateMM0.Waiting~q\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|addr\(1));

-- Location: FF_X27_Y29_N29
\inst3|memory_rtl_0_bypass[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	asdata => \inst3|addr\(1),
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|memory_rtl_0_bypass\(3));

-- Location: FF_X34_Y24_N25
\inst3|addr[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|addr~0_combout\,
	ena => \inst3|ALT_INV_stateMM0.Waiting~q\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|addr\(0));

-- Location: FF_X27_Y29_N11
\inst3|memory_rtl_0_bypass[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	asdata => \inst3|addr\(0),
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|memory_rtl_0_bypass\(1));

-- Location: LCCOMB_X34_Y24_N16
\inst3|memory_rtl_0_bypass[4]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|memory_rtl_0_bypass[4]~feeder_combout\ = \inst3|addr~1_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst3|addr~1_combout\,
	combout => \inst3|memory_rtl_0_bypass[4]~feeder_combout\);

-- Location: FF_X34_Y24_N17
\inst3|memory_rtl_0_bypass[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|memory_rtl_0_bypass[4]~feeder_combout\,
	ena => \inst3|ALT_INV_stateMM0.Waiting~q\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|memory_rtl_0_bypass\(4));

-- Location: LCCOMB_X27_Y29_N10
\inst3|memory~34\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|memory~34_combout\ = (\inst3|memory_rtl_0_bypass\(2) & (\inst3|memory_rtl_0_bypass\(1) & (\inst3|memory_rtl_0_bypass\(3) $ (!\inst3|memory_rtl_0_bypass\(4))))) # (!\inst3|memory_rtl_0_bypass\(2) & (!\inst3|memory_rtl_0_bypass\(1) & 
-- (\inst3|memory_rtl_0_bypass\(3) $ (!\inst3|memory_rtl_0_bypass\(4)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000010000100001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|memory_rtl_0_bypass\(2),
	datab => \inst3|memory_rtl_0_bypass\(3),
	datac => \inst3|memory_rtl_0_bypass\(1),
	datad => \inst3|memory_rtl_0_bypass\(4),
	combout => \inst3|memory~34_combout\);

-- Location: LCCOMB_X27_Y29_N18
\inst3|memory~36\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|memory~36_combout\ = (\inst3|memory~35_combout\ & \inst3|memory~34_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst3|memory~35_combout\,
	datad => \inst3|memory~34_combout\,
	combout => \inst3|memory~36_combout\);

-- Location: FF_X27_Y29_N17
\inst3|memory_rtl_0_bypass[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	asdata => \inst3|memory~48_combout\,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|memory_rtl_0_bypass\(0));

-- Location: IOIBUF_X38_Y34_N1
\Address[7]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_Address(7),
	o => \Address[7]~input_o\);

-- Location: LCCOMB_X34_Y24_N22
\inst3|addr~7\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|addr~7_combout\ = (\inst3|ce0Prev~q\ & (!\nCE~input_o\ & \Address[7]~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010001000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|ce0Prev~q\,
	datab => \nCE~input_o\,
	datad => \Address[7]~input_o\,
	combout => \inst3|addr~7_combout\);

-- Location: FF_X34_Y24_N23
\inst3|addr[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|addr~7_combout\,
	ena => \inst3|ALT_INV_stateMM0.Waiting~q\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|addr\(7));

-- Location: FF_X34_Y24_N11
\inst3|memory_rtl_0_bypass[15]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	asdata => \inst3|addr\(7),
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|memory_rtl_0_bypass\(15));

-- Location: IOIBUF_X14_Y34_N8
\Address[6]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_Address(6),
	o => \Address[6]~input_o\);

-- Location: LCCOMB_X34_Y24_N20
\inst3|addr~6\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|addr~6_combout\ = (\Address[6]~input_o\ & (!\nCE~input_o\ & \inst3|ce0Prev~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010001000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \Address[6]~input_o\,
	datab => \nCE~input_o\,
	datad => \inst3|ce0Prev~q\,
	combout => \inst3|addr~6_combout\);

-- Location: FF_X34_Y24_N21
\inst3|addr[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|addr~6_combout\,
	ena => \inst3|ALT_INV_stateMM0.Waiting~q\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|addr\(6));

-- Location: LCCOMB_X34_Y24_N8
\inst3|memory_rtl_0_bypass[13]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|memory_rtl_0_bypass[13]~feeder_combout\ = \inst3|addr\(6)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst3|addr\(6),
	combout => \inst3|memory_rtl_0_bypass[13]~feeder_combout\);

-- Location: FF_X34_Y24_N9
\inst3|memory_rtl_0_bypass[13]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|memory_rtl_0_bypass[13]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|memory_rtl_0_bypass\(13));

-- Location: FF_X34_Y24_N7
\inst3|memory_rtl_0_bypass[14]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	asdata => \inst3|addr~6_combout\,
	sload => VCC,
	ena => \inst3|ALT_INV_stateMM0.Waiting~q\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|memory_rtl_0_bypass\(14));

-- Location: LCCOMB_X34_Y24_N28
\inst3|memory_rtl_0_bypass[16]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|memory_rtl_0_bypass[16]~feeder_combout\ = \inst3|addr~7_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst3|addr~7_combout\,
	combout => \inst3|memory_rtl_0_bypass[16]~feeder_combout\);

-- Location: FF_X34_Y24_N29
\inst3|memory_rtl_0_bypass[16]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|memory_rtl_0_bypass[16]~feeder_combout\,
	ena => \inst3|ALT_INV_stateMM0.Waiting~q\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|memory_rtl_0_bypass\(16));

-- Location: LCCOMB_X34_Y24_N6
\inst3|memory~38\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|memory~38_combout\ = (\inst3|memory_rtl_0_bypass\(15) & (\inst3|memory_rtl_0_bypass\(16) & (\inst3|memory_rtl_0_bypass\(13) $ (!\inst3|memory_rtl_0_bypass\(14))))) # (!\inst3|memory_rtl_0_bypass\(15) & (!\inst3|memory_rtl_0_bypass\(16) & 
-- (\inst3|memory_rtl_0_bypass\(13) $ (!\inst3|memory_rtl_0_bypass\(14)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000001001000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|memory_rtl_0_bypass\(15),
	datab => \inst3|memory_rtl_0_bypass\(13),
	datac => \inst3|memory_rtl_0_bypass\(14),
	datad => \inst3|memory_rtl_0_bypass\(16),
	combout => \inst3|memory~38_combout\);

-- Location: LCCOMB_X27_Y29_N16
\inst3|memory~39\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|memory~39_combout\ = (\inst3|memory~37_combout\ & (\inst3|memory~36_combout\ & (\inst3|memory_rtl_0_bypass\(0) & \inst3|memory~38_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|memory~37_combout\,
	datab => \inst3|memory~36_combout\,
	datac => \inst3|memory_rtl_0_bypass\(0),
	datad => \inst3|memory~38_combout\,
	combout => \inst3|memory~39_combout\);

-- Location: LCCOMB_X35_Y33_N24
\inst3|stateMM0.Waiting~_wirecell\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|stateMM0.Waiting~_wirecell_combout\ = !\inst3|stateMM0.Waiting~q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst3|stateMM0.Waiting~q\,
	combout => \inst3|stateMM0.Waiting~_wirecell_combout\);

-- Location: IOIBUF_X40_Y34_N8
\Data[0]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => Data(0),
	o => \Data[0]~input_o\);

-- Location: IOIBUF_X45_Y34_N22
\Data[1]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => Data(1),
	o => \Data[1]~input_o\);

-- Location: IOIBUF_X45_Y34_N15
\Data[2]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => Data(2),
	o => \Data[2]~input_o\);

-- Location: IOIBUF_X45_Y34_N8
\Data[3]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => Data(3),
	o => \Data[3]~input_o\);

-- Location: IOIBUF_X16_Y34_N15
\Data[4]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => Data(4),
	o => \Data[4]~input_o\);

-- Location: IOIBUF_X16_Y34_N1
\Data[5]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => Data(5),
	o => \Data[5]~input_o\);

-- Location: IOIBUF_X18_Y34_N22
\Data[6]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => Data(6),
	o => \Data[6]~input_o\);

-- Location: IOIBUF_X18_Y34_N1
\Data[7]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => Data(7),
	o => \Data[7]~input_o\);

-- Location: M9K_X33_Y29_N0
\inst3|memory_rtl_0|auto_generated|ram_block1a0\ : cycloneiii_ram_block
-- pragma translate_off
GENERIC MAP (
	data_interleave_offset_in_bits => 1,
	data_interleave_width_in_bits => 1,
	logical_ram_name => "RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ALTSYNCRAM",
	mixed_port_feed_through_mode => "old",
	operation_mode => "dual_port",
	port_a_address_clear => "none",
	port_a_address_width => 8,
	port_a_byte_enable_clock => "none",
	port_a_data_out_clear => "none",
	port_a_data_out_clock => "none",
	port_a_data_width => 36,
	port_a_first_address => 0,
	port_a_first_bit_number => 0,
	port_a_last_address => 255,
	port_a_logical_ram_depth => 256,
	port_a_logical_ram_width => 8,
	port_a_read_during_write_mode => "new_data_with_nbe_read",
	port_b_address_clear => "none",
	port_b_address_clock => "clock0",
	port_b_address_width => 8,
	port_b_data_out_clear => "none",
	port_b_data_out_clock => "none",
	port_b_data_width => 36,
	port_b_first_address => 0,
	port_b_first_bit_number => 0,
	port_b_last_address => 255,
	port_b_logical_ram_depth => 256,
	port_b_logical_ram_width => 8,
	port_b_read_during_write_mode => "new_data_with_nbe_read",
	port_b_read_enable_clock => "clock0",
	ram_block_type => "M9K")
-- pragma translate_on
PORT MAP (
	portawe => \inst3|memory~48_combout\,
	portbre => VCC,
	portbaddrstall => \inst3|ALT_INV_stateMM0.Waiting~_wirecell_combout\,
	clk0 => \FPGA_CLK~inputclkctrl_outclk\,
	portadatain => \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\,
	portaaddr => \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\,
	portbaddr => \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	portbdataout => \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\);

-- Location: LCCOMB_X35_Y29_N24
\inst3|memory_rtl_0_bypass[24]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|memory_rtl_0_bypass[24]~feeder_combout\ = \Data[7]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \Data[7]~input_o\,
	combout => \inst3|memory_rtl_0_bypass[24]~feeder_combout\);

-- Location: FF_X35_Y29_N25
\inst3|memory_rtl_0_bypass[24]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|memory_rtl_0_bypass[24]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|memory_rtl_0_bypass\(24));

-- Location: LCCOMB_X35_Y29_N0
\inst3|memory~40\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|memory~40_combout\ = (\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0_bypass\(24)))) # (!\inst3|memory~39_combout\ & (\inst3|memory_rtl_0|auto_generated|ram_block1a7\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110000110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst3|memory~39_combout\,
	datac => \inst3|memory_rtl_0|auto_generated|ram_block1a7\,
	datad => \inst3|memory_rtl_0_bypass\(24),
	combout => \inst3|memory~40_combout\);

-- Location: LCCOMB_X27_Y29_N12
\inst3|Selector4~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|Selector4~0_combout\ = (!\nOE~input_o\ & (!\nCE~input_o\ & (\inst3|ce0Prev~q\ & !\inst3|stateMM0.Waiting~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \nOE~input_o\,
	datab => \nCE~input_o\,
	datac => \inst3|ce0Prev~q\,
	datad => \inst3|stateMM0.Waiting~q\,
	combout => \inst3|Selector4~0_combout\);

-- Location: FF_X27_Y29_N13
\inst3|stateMM0.Reading\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|Selector4~0_combout\,
	ena => \inst3|Selector3~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|stateMM0.Reading~q\);

-- Location: LCCOMB_X27_Y29_N26
\inst3|Selector74~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|Selector74~0_combout\ = (\inst3|stateMM0.Reading~q\) # ((!\inst3|stateMM0.Waiting~q\ & ((\nCE~input_o\) # (!\inst3|ce0Prev~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101011101111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|stateMM0.Reading~q\,
	datab => \nCE~input_o\,
	datac => \inst3|ce0Prev~q\,
	datad => \inst3|stateMM0.Waiting~q\,
	combout => \inst3|Selector74~0_combout\);

-- Location: FF_X35_Y29_N1
\inst3|data0[7]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|memory~40_combout\,
	ena => \inst3|Selector74~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|data0[7]~reg0_q\);

-- Location: LCCOMB_X35_Y33_N16
\inst3|data0[7]~enfeeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|data0[7]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst3|stateMM0.Waiting~q\,
	combout => \inst3|data0[7]~enfeeder_combout\);

-- Location: FF_X35_Y33_N17
\inst3|data0[7]~en\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|data0[7]~enfeeder_combout\,
	ena => \inst3|Selector74~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|data0[7]~en_q\);

-- Location: LCCOMB_X35_Y29_N26
\inst3|memory_rtl_0_bypass[23]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|memory_rtl_0_bypass[23]~feeder_combout\ = \Data[6]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \Data[6]~input_o\,
	combout => \inst3|memory_rtl_0_bypass[23]~feeder_combout\);

-- Location: FF_X35_Y29_N27
\inst3|memory_rtl_0_bypass[23]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|memory_rtl_0_bypass[23]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|memory_rtl_0_bypass\(23));

-- Location: LCCOMB_X35_Y29_N18
\inst3|memory~41\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|memory~41_combout\ = (\inst3|memory~39_combout\ & (\inst3|memory_rtl_0_bypass\(23))) # (!\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0|auto_generated|ram_block1a6\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011100010111000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|memory_rtl_0_bypass\(23),
	datab => \inst3|memory~39_combout\,
	datac => \inst3|memory_rtl_0|auto_generated|ram_block1a6\,
	combout => \inst3|memory~41_combout\);

-- Location: FF_X35_Y29_N19
\inst3|data0[6]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|memory~41_combout\,
	ena => \inst3|Selector74~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|data0[6]~reg0_q\);

-- Location: LCCOMB_X35_Y33_N18
\inst3|data0[6]~enfeeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|data0[6]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst3|stateMM0.Waiting~q\,
	combout => \inst3|data0[6]~enfeeder_combout\);

-- Location: FF_X35_Y33_N19
\inst3|data0[6]~en\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|data0[6]~enfeeder_combout\,
	ena => \inst3|Selector74~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|data0[6]~en_q\);

-- Location: LCCOMB_X35_Y29_N28
\inst3|memory_rtl_0_bypass[22]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|memory_rtl_0_bypass[22]~feeder_combout\ = \Data[5]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \Data[5]~input_o\,
	combout => \inst3|memory_rtl_0_bypass[22]~feeder_combout\);

-- Location: FF_X35_Y29_N29
\inst3|memory_rtl_0_bypass[22]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|memory_rtl_0_bypass[22]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|memory_rtl_0_bypass\(22));

-- Location: LCCOMB_X35_Y29_N20
\inst3|memory~42\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|memory~42_combout\ = (\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0_bypass\(22)))) # (!\inst3|memory~39_combout\ & (\inst3|memory_rtl_0|auto_generated|ram_block1a5\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101000001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|memory_rtl_0|auto_generated|ram_block1a5\,
	datac => \inst3|memory~39_combout\,
	datad => \inst3|memory_rtl_0_bypass\(22),
	combout => \inst3|memory~42_combout\);

-- Location: FF_X35_Y29_N21
\inst3|data0[5]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|memory~42_combout\,
	ena => \inst3|Selector74~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|data0[5]~reg0_q\);

-- Location: LCCOMB_X35_Y33_N4
\inst3|data0[5]~enfeeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|data0[5]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst3|stateMM0.Waiting~q\,
	combout => \inst3|data0[5]~enfeeder_combout\);

-- Location: FF_X35_Y33_N5
\inst3|data0[5]~en\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|data0[5]~enfeeder_combout\,
	ena => \inst3|Selector74~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|data0[5]~en_q\);

-- Location: LCCOMB_X35_Y29_N14
\inst3|memory_rtl_0_bypass[21]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|memory_rtl_0_bypass[21]~feeder_combout\ = \Data[4]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \Data[4]~input_o\,
	combout => \inst3|memory_rtl_0_bypass[21]~feeder_combout\);

-- Location: FF_X35_Y29_N15
\inst3|memory_rtl_0_bypass[21]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|memory_rtl_0_bypass[21]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|memory_rtl_0_bypass\(21));

-- Location: LCCOMB_X35_Y29_N30
\inst3|memory~43\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|memory~43_combout\ = (\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0_bypass\(21)))) # (!\inst3|memory~39_combout\ & (\inst3|memory_rtl_0|auto_generated|ram_block1a4\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110001011100010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|memory_rtl_0|auto_generated|ram_block1a4\,
	datab => \inst3|memory~39_combout\,
	datac => \inst3|memory_rtl_0_bypass\(21),
	combout => \inst3|memory~43_combout\);

-- Location: FF_X35_Y29_N31
\inst3|data0[4]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|memory~43_combout\,
	ena => \inst3|Selector74~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|data0[4]~reg0_q\);

-- Location: LCCOMB_X35_Y33_N6
\inst3|data0[4]~enfeeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|data0[4]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst3|stateMM0.Waiting~q\,
	combout => \inst3|data0[4]~enfeeder_combout\);

-- Location: FF_X35_Y33_N7
\inst3|data0[4]~en\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|data0[4]~enfeeder_combout\,
	ena => \inst3|Selector74~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|data0[4]~en_q\);

-- Location: FF_X35_Y29_N9
\inst3|memory_rtl_0_bypass[20]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	asdata => \Data[3]~input_o\,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|memory_rtl_0_bypass\(20));

-- Location: LCCOMB_X35_Y29_N16
\inst3|memory~44\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|memory~44_combout\ = (\inst3|memory~39_combout\ & (\inst3|memory_rtl_0_bypass\(20))) # (!\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0|auto_generated|ram_block1a3\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111001111000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst3|memory~39_combout\,
	datac => \inst3|memory_rtl_0_bypass\(20),
	datad => \inst3|memory_rtl_0|auto_generated|ram_block1a3\,
	combout => \inst3|memory~44_combout\);

-- Location: FF_X35_Y29_N17
\inst3|data0[3]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|memory~44_combout\,
	ena => \inst3|Selector74~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|data0[3]~reg0_q\);

-- Location: LCCOMB_X35_Y33_N8
\inst3|data0[3]~enfeeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|data0[3]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst3|stateMM0.Waiting~q\,
	combout => \inst3|data0[3]~enfeeder_combout\);

-- Location: FF_X35_Y33_N9
\inst3|data0[3]~en\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|data0[3]~enfeeder_combout\,
	ena => \inst3|Selector74~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|data0[3]~en_q\);

-- Location: FF_X35_Y29_N11
\inst3|memory_rtl_0_bypass[19]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	asdata => \Data[2]~input_o\,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|memory_rtl_0_bypass\(19));

-- Location: LCCOMB_X35_Y29_N2
\inst3|memory~45\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|memory~45_combout\ = (\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0_bypass\(19)))) # (!\inst3|memory~39_combout\ & (\inst3|memory_rtl_0|auto_generated|ram_block1a2\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110000110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst3|memory~39_combout\,
	datac => \inst3|memory_rtl_0|auto_generated|ram_block1a2\,
	datad => \inst3|memory_rtl_0_bypass\(19),
	combout => \inst3|memory~45_combout\);

-- Location: FF_X35_Y29_N3
\inst3|data0[2]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|memory~45_combout\,
	ena => \inst3|Selector74~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|data0[2]~reg0_q\);

-- Location: LCCOMB_X35_Y33_N2
\inst3|data0[2]~enfeeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|data0[2]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst3|stateMM0.Waiting~q\,
	combout => \inst3|data0[2]~enfeeder_combout\);

-- Location: FF_X35_Y33_N3
\inst3|data0[2]~en\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|data0[2]~enfeeder_combout\,
	ena => \inst3|Selector74~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|data0[2]~en_q\);

-- Location: FF_X35_Y29_N13
\inst3|memory_rtl_0_bypass[18]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	asdata => \Data[1]~input_o\,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|memory_rtl_0_bypass\(18));

-- Location: LCCOMB_X35_Y29_N4
\inst3|memory~46\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|memory~46_combout\ = (\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0_bypass\(18)))) # (!\inst3|memory~39_combout\ & (\inst3|memory_rtl_0|auto_generated|ram_block1a1\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110000110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst3|memory~39_combout\,
	datac => \inst3|memory_rtl_0|auto_generated|ram_block1a1\,
	datad => \inst3|memory_rtl_0_bypass\(18),
	combout => \inst3|memory~46_combout\);

-- Location: FF_X35_Y29_N5
\inst3|data0[1]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|memory~46_combout\,
	ena => \inst3|Selector74~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|data0[1]~reg0_q\);

-- Location: LCCOMB_X35_Y33_N20
\inst3|data0[1]~enfeeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|data0[1]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst3|stateMM0.Waiting~q\,
	combout => \inst3|data0[1]~enfeeder_combout\);

-- Location: FF_X35_Y33_N21
\inst3|data0[1]~en\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|data0[1]~enfeeder_combout\,
	ena => \inst3|Selector74~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|data0[1]~en_q\);

-- Location: FF_X35_Y29_N23
\inst3|memory_rtl_0_bypass[17]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	asdata => \Data[0]~input_o\,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|memory_rtl_0_bypass\(17));

-- Location: LCCOMB_X35_Y29_N6
\inst3|memory~47\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|memory~47_combout\ = (\inst3|memory~39_combout\ & (\inst3|memory_rtl_0_bypass\(17))) # (!\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0|auto_generated|ram_block1a0~portbdataout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011100010111000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|memory_rtl_0_bypass\(17),
	datab => \inst3|memory~39_combout\,
	datac => \inst3|memory_rtl_0|auto_generated|ram_block1a0~portbdataout\,
	combout => \inst3|memory~47_combout\);

-- Location: FF_X35_Y29_N7
\inst3|data0[0]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|memory~47_combout\,
	ena => \inst3|Selector74~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|data0[0]~reg0_q\);

-- Location: LCCOMB_X35_Y33_N22
\inst3|data0[0]~enfeeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|data0[0]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst3|stateMM0.Waiting~q\,
	combout => \inst3|data0[0]~enfeeder_combout\);

-- Location: FF_X35_Y33_N23
\inst3|data0[0]~en\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst3|data0[0]~enfeeder_combout\,
	ena => \inst3|Selector74~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|data0[0]~en_q\);

-- Location: LCCOMB_X26_Y29_N8
\inst2|counter[0]~24\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|counter[0]~24_combout\ = \inst2|counter\(0) $ (VCC)
-- \inst2|counter[0]~25\ = CARRY(\inst2|counter\(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001111001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst2|counter\(0),
	datad => VCC,
	combout => \inst2|counter[0]~24_combout\,
	cout => \inst2|counter[0]~25\);

-- Location: LCCOMB_X26_Y28_N2
\inst2|counter[13]~50\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|counter[13]~50_combout\ = (\inst2|counter\(13) & (!\inst2|counter[12]~49\)) # (!\inst2|counter\(13) & ((\inst2|counter[12]~49\) # (GND)))
-- \inst2|counter[13]~51\ = CARRY((!\inst2|counter[12]~49\) # (!\inst2|counter\(13)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \inst2|counter\(13),
	datad => VCC,
	cin => \inst2|counter[12]~49\,
	combout => \inst2|counter[13]~50_combout\,
	cout => \inst2|counter[13]~51\);

-- Location: LCCOMB_X26_Y28_N4
\inst2|counter[14]~52\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|counter[14]~52_combout\ = (\inst2|counter\(14) & (\inst2|counter[13]~51\ $ (GND))) # (!\inst2|counter\(14) & (!\inst2|counter[13]~51\ & VCC))
-- \inst2|counter[14]~53\ = CARRY((\inst2|counter\(14) & !\inst2|counter[13]~51\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \inst2|counter\(14),
	datad => VCC,
	cin => \inst2|counter[13]~51\,
	combout => \inst2|counter[14]~52_combout\,
	cout => \inst2|counter[14]~53\);

-- Location: FF_X26_Y28_N5
\inst2|counter[14]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst2|counter[14]~52_combout\,
	sclr => \inst2|LessThan0~10_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst2|counter\(14));

-- Location: LCCOMB_X26_Y28_N6
\inst2|counter[15]~54\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|counter[15]~54_combout\ = (\inst2|counter\(15) & (!\inst2|counter[14]~53\)) # (!\inst2|counter\(15) & ((\inst2|counter[14]~53\) # (GND)))
-- \inst2|counter[15]~55\ = CARRY((!\inst2|counter[14]~53\) # (!\inst2|counter\(15)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst2|counter\(15),
	datad => VCC,
	cin => \inst2|counter[14]~53\,
	combout => \inst2|counter[15]~54_combout\,
	cout => \inst2|counter[15]~55\);

-- Location: FF_X26_Y28_N7
\inst2|counter[15]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst2|counter[15]~54_combout\,
	sclr => \inst2|LessThan0~10_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst2|counter\(15));

-- Location: LCCOMB_X26_Y28_N8
\inst2|counter[16]~56\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|counter[16]~56_combout\ = (\inst2|counter\(16) & (\inst2|counter[15]~55\ $ (GND))) # (!\inst2|counter\(16) & (!\inst2|counter[15]~55\ & VCC))
-- \inst2|counter[16]~57\ = CARRY((\inst2|counter\(16) & !\inst2|counter[15]~55\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \inst2|counter\(16),
	datad => VCC,
	cin => \inst2|counter[15]~55\,
	combout => \inst2|counter[16]~56_combout\,
	cout => \inst2|counter[16]~57\);

-- Location: FF_X26_Y28_N9
\inst2|counter[16]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst2|counter[16]~56_combout\,
	sclr => \inst2|LessThan0~10_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst2|counter\(16));

-- Location: LCCOMB_X26_Y28_N10
\inst2|counter[17]~58\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|counter[17]~58_combout\ = (\inst2|counter\(17) & (!\inst2|counter[16]~57\)) # (!\inst2|counter\(17) & ((\inst2|counter[16]~57\) # (GND)))
-- \inst2|counter[17]~59\ = CARRY((!\inst2|counter[16]~57\) # (!\inst2|counter\(17)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst2|counter\(17),
	datad => VCC,
	cin => \inst2|counter[16]~57\,
	combout => \inst2|counter[17]~58_combout\,
	cout => \inst2|counter[17]~59\);

-- Location: FF_X26_Y28_N11
\inst2|counter[17]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst2|counter[17]~58_combout\,
	sclr => \inst2|LessThan0~10_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst2|counter\(17));

-- Location: LCCOMB_X26_Y28_N12
\inst2|counter[18]~60\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|counter[18]~60_combout\ = (\inst2|counter\(18) & (\inst2|counter[17]~59\ $ (GND))) # (!\inst2|counter\(18) & (!\inst2|counter[17]~59\ & VCC))
-- \inst2|counter[18]~61\ = CARRY((\inst2|counter\(18) & !\inst2|counter[17]~59\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010010100001010",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst2|counter\(18),
	datad => VCC,
	cin => \inst2|counter[17]~59\,
	combout => \inst2|counter[18]~60_combout\,
	cout => \inst2|counter[18]~61\);

-- Location: FF_X26_Y28_N13
\inst2|counter[18]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst2|counter[18]~60_combout\,
	sclr => \inst2|LessThan0~10_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst2|counter\(18));

-- Location: LCCOMB_X26_Y28_N14
\inst2|counter[19]~62\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|counter[19]~62_combout\ = (\inst2|counter\(19) & (!\inst2|counter[18]~61\)) # (!\inst2|counter\(19) & ((\inst2|counter[18]~61\) # (GND)))
-- \inst2|counter[19]~63\ = CARRY((!\inst2|counter[18]~61\) # (!\inst2|counter\(19)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \inst2|counter\(19),
	datad => VCC,
	cin => \inst2|counter[18]~61\,
	combout => \inst2|counter[19]~62_combout\,
	cout => \inst2|counter[19]~63\);

-- Location: FF_X26_Y28_N15
\inst2|counter[19]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst2|counter[19]~62_combout\,
	sclr => \inst2|LessThan0~10_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst2|counter\(19));

-- Location: LCCOMB_X26_Y28_N16
\inst2|counter[20]~64\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|counter[20]~64_combout\ = (\inst2|counter\(20) & (\inst2|counter[19]~63\ $ (GND))) # (!\inst2|counter\(20) & (!\inst2|counter[19]~63\ & VCC))
-- \inst2|counter[20]~65\ = CARRY((\inst2|counter\(20) & !\inst2|counter[19]~63\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \inst2|counter\(20),
	datad => VCC,
	cin => \inst2|counter[19]~63\,
	combout => \inst2|counter[20]~64_combout\,
	cout => \inst2|counter[20]~65\);

-- Location: FF_X26_Y28_N17
\inst2|counter[20]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst2|counter[20]~64_combout\,
	sclr => \inst2|LessThan0~10_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst2|counter\(20));

-- Location: LCCOMB_X26_Y28_N18
\inst2|counter[21]~66\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|counter[21]~66_combout\ = (\inst2|counter\(21) & (!\inst2|counter[20]~65\)) # (!\inst2|counter\(21) & ((\inst2|counter[20]~65\) # (GND)))
-- \inst2|counter[21]~67\ = CARRY((!\inst2|counter[20]~65\) # (!\inst2|counter\(21)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \inst2|counter\(21),
	datad => VCC,
	cin => \inst2|counter[20]~65\,
	combout => \inst2|counter[21]~66_combout\,
	cout => \inst2|counter[21]~67\);

-- Location: FF_X26_Y28_N19
\inst2|counter[21]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst2|counter[21]~66_combout\,
	sclr => \inst2|LessThan0~10_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst2|counter\(21));

-- Location: LCCOMB_X26_Y28_N26
\inst2|LessThan0~8\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|LessThan0~8_combout\ = (((!\inst2|counter\(21)) # (!\inst2|counter\(19))) # (!\inst2|counter\(20))) # (!\inst2|counter\(18))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst2|counter\(18),
	datab => \inst2|counter\(20),
	datac => \inst2|counter\(19),
	datad => \inst2|counter\(21),
	combout => \inst2|LessThan0~8_combout\);

-- Location: LCCOMB_X26_Y28_N20
\inst2|counter[22]~68\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|counter[22]~68_combout\ = (\inst2|counter\(22) & (\inst2|counter[21]~67\ $ (GND))) # (!\inst2|counter\(22) & (!\inst2|counter[21]~67\ & VCC))
-- \inst2|counter[22]~69\ = CARRY((\inst2|counter\(22) & !\inst2|counter[21]~67\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \inst2|counter\(22),
	datad => VCC,
	cin => \inst2|counter[21]~67\,
	combout => \inst2|counter[22]~68_combout\,
	cout => \inst2|counter[22]~69\);

-- Location: FF_X26_Y28_N21
\inst2|counter[22]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst2|counter[22]~68_combout\,
	sclr => \inst2|LessThan0~10_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst2|counter\(22));

-- Location: LCCOMB_X26_Y28_N22
\inst2|counter[23]~70\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|counter[23]~70_combout\ = \inst2|counter\(23) $ (\inst2|counter[22]~69\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011010",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst2|counter\(23),
	cin => \inst2|counter[22]~69\,
	combout => \inst2|counter[23]~70_combout\);

-- Location: FF_X26_Y28_N23
\inst2|counter[23]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst2|counter[23]~70_combout\,
	sclr => \inst2|LessThan0~10_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst2|counter\(23));

-- Location: LCCOMB_X26_Y28_N28
\inst2|LessThan0~9\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|LessThan0~9_combout\ = (\inst2|LessThan0~8_combout\) # ((!\inst2|counter\(22)) # (!\inst2|counter\(23)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst2|LessThan0~8_combout\,
	datac => \inst2|counter\(23),
	datad => \inst2|counter\(22),
	combout => \inst2|LessThan0~9_combout\);

-- Location: LCCOMB_X25_Y23_N18
\inst2|LessThan0~2\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|LessThan0~2_combout\ = (!\inst2|counter\(13) & (!\inst2|counter\(16) & (!\inst2|counter\(15) & !\inst2|counter\(6))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst2|counter\(13),
	datab => \inst2|counter\(16),
	datac => \inst2|counter\(15),
	datad => \inst2|counter\(6),
	combout => \inst2|LessThan0~2_combout\);

-- Location: LCCOMB_X26_Y29_N4
\inst2|LessThan0~3\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|LessThan0~3_combout\ = (!\inst2|counter\(7) & (!\inst2|counter\(10) & (!\inst2|counter\(9) & !\inst2|counter\(8))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst2|counter\(7),
	datab => \inst2|counter\(10),
	datac => \inst2|counter\(9),
	datad => \inst2|counter\(8),
	combout => \inst2|LessThan0~3_combout\);

-- Location: LCCOMB_X26_Y29_N0
\inst2|LessThan0~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|LessThan0~0_combout\ = (!\inst2|counter\(4) & (!\inst2|counter\(2) & ((!\inst2|counter\(0)) # (!\inst2|counter\(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000010011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst2|counter\(1),
	datab => \inst2|counter\(4),
	datac => \inst2|counter\(0),
	datad => \inst2|counter\(2),
	combout => \inst2|LessThan0~0_combout\);

-- Location: LCCOMB_X26_Y29_N2
\inst2|LessThan0~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|LessThan0~1_combout\ = (\inst2|LessThan0~0_combout\) # (((!\inst2|counter\(4) & !\inst2|counter\(3))) # (!\inst2|counter\(5)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst2|counter\(4),
	datab => \inst2|LessThan0~0_combout\,
	datac => \inst2|counter\(3),
	datad => \inst2|counter\(5),
	combout => \inst2|LessThan0~1_combout\);

-- Location: LCCOMB_X26_Y29_N6
\inst2|LessThan0~4\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|LessThan0~4_combout\ = (!\inst2|counter\(11) & (\inst2|LessThan0~2_combout\ & (\inst2|LessThan0~3_combout\ & \inst2|LessThan0~1_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst2|counter\(11),
	datab => \inst2|LessThan0~2_combout\,
	datac => \inst2|LessThan0~3_combout\,
	datad => \inst2|LessThan0~1_combout\,
	combout => \inst2|LessThan0~4_combout\);

-- Location: LCCOMB_X26_Y28_N24
\inst2|LessThan0~6\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|LessThan0~6_combout\ = ((!\inst2|counter\(14) & (!\inst2|counter\(16) & !\inst2|counter\(15)))) # (!\inst2|counter\(17))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101010101010111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst2|counter\(17),
	datab => \inst2|counter\(14),
	datac => \inst2|counter\(16),
	datad => \inst2|counter\(15),
	combout => \inst2|LessThan0~6_combout\);

-- Location: LCCOMB_X26_Y28_N30
\inst2|LessThan0~10\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|LessThan0~10_combout\ = (!\inst2|LessThan0~5_combout\ & (!\inst2|LessThan0~9_combout\ & (!\inst2|LessThan0~4_combout\ & !\inst2|LessThan0~6_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst2|LessThan0~5_combout\,
	datab => \inst2|LessThan0~9_combout\,
	datac => \inst2|LessThan0~4_combout\,
	datad => \inst2|LessThan0~6_combout\,
	combout => \inst2|LessThan0~10_combout\);

-- Location: FF_X26_Y29_N9
\inst2|counter[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst2|counter[0]~24_combout\,
	sclr => \inst2|LessThan0~10_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst2|counter\(0));

-- Location: LCCOMB_X26_Y29_N10
\inst2|counter[1]~26\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|counter[1]~26_combout\ = (\inst2|counter\(1) & (!\inst2|counter[0]~25\)) # (!\inst2|counter\(1) & ((\inst2|counter[0]~25\) # (GND)))
-- \inst2|counter[1]~27\ = CARRY((!\inst2|counter[0]~25\) # (!\inst2|counter\(1)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst2|counter\(1),
	datad => VCC,
	cin => \inst2|counter[0]~25\,
	combout => \inst2|counter[1]~26_combout\,
	cout => \inst2|counter[1]~27\);

-- Location: FF_X26_Y29_N11
\inst2|counter[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst2|counter[1]~26_combout\,
	sclr => \inst2|LessThan0~10_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst2|counter\(1));

-- Location: LCCOMB_X26_Y29_N12
\inst2|counter[2]~28\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|counter[2]~28_combout\ = (\inst2|counter\(2) & (\inst2|counter[1]~27\ $ (GND))) # (!\inst2|counter\(2) & (!\inst2|counter[1]~27\ & VCC))
-- \inst2|counter[2]~29\ = CARRY((\inst2|counter\(2) & !\inst2|counter[1]~27\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010010100001010",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst2|counter\(2),
	datad => VCC,
	cin => \inst2|counter[1]~27\,
	combout => \inst2|counter[2]~28_combout\,
	cout => \inst2|counter[2]~29\);

-- Location: FF_X26_Y29_N13
\inst2|counter[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst2|counter[2]~28_combout\,
	sclr => \inst2|LessThan0~10_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst2|counter\(2));

-- Location: LCCOMB_X26_Y29_N14
\inst2|counter[3]~30\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|counter[3]~30_combout\ = (\inst2|counter\(3) & (!\inst2|counter[2]~29\)) # (!\inst2|counter\(3) & ((\inst2|counter[2]~29\) # (GND)))
-- \inst2|counter[3]~31\ = CARRY((!\inst2|counter[2]~29\) # (!\inst2|counter\(3)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \inst2|counter\(3),
	datad => VCC,
	cin => \inst2|counter[2]~29\,
	combout => \inst2|counter[3]~30_combout\,
	cout => \inst2|counter[3]~31\);

-- Location: FF_X26_Y29_N15
\inst2|counter[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst2|counter[3]~30_combout\,
	sclr => \inst2|LessThan0~10_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst2|counter\(3));

-- Location: LCCOMB_X26_Y29_N16
\inst2|counter[4]~32\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|counter[4]~32_combout\ = (\inst2|counter\(4) & (\inst2|counter[3]~31\ $ (GND))) # (!\inst2|counter\(4) & (!\inst2|counter[3]~31\ & VCC))
-- \inst2|counter[4]~33\ = CARRY((\inst2|counter\(4) & !\inst2|counter[3]~31\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \inst2|counter\(4),
	datad => VCC,
	cin => \inst2|counter[3]~31\,
	combout => \inst2|counter[4]~32_combout\,
	cout => \inst2|counter[4]~33\);

-- Location: FF_X26_Y29_N17
\inst2|counter[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst2|counter[4]~32_combout\,
	sclr => \inst2|LessThan0~10_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst2|counter\(4));

-- Location: LCCOMB_X26_Y29_N18
\inst2|counter[5]~34\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|counter[5]~34_combout\ = (\inst2|counter\(5) & (!\inst2|counter[4]~33\)) # (!\inst2|counter\(5) & ((\inst2|counter[4]~33\) # (GND)))
-- \inst2|counter[5]~35\ = CARRY((!\inst2|counter[4]~33\) # (!\inst2|counter\(5)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \inst2|counter\(5),
	datad => VCC,
	cin => \inst2|counter[4]~33\,
	combout => \inst2|counter[5]~34_combout\,
	cout => \inst2|counter[5]~35\);

-- Location: FF_X26_Y29_N19
\inst2|counter[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst2|counter[5]~34_combout\,
	sclr => \inst2|LessThan0~10_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst2|counter\(5));

-- Location: LCCOMB_X26_Y29_N20
\inst2|counter[6]~36\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|counter[6]~36_combout\ = (\inst2|counter\(6) & (\inst2|counter[5]~35\ $ (GND))) # (!\inst2|counter\(6) & (!\inst2|counter[5]~35\ & VCC))
-- \inst2|counter[6]~37\ = CARRY((\inst2|counter\(6) & !\inst2|counter[5]~35\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \inst2|counter\(6),
	datad => VCC,
	cin => \inst2|counter[5]~35\,
	combout => \inst2|counter[6]~36_combout\,
	cout => \inst2|counter[6]~37\);

-- Location: FF_X26_Y29_N21
\inst2|counter[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst2|counter[6]~36_combout\,
	sclr => \inst2|LessThan0~10_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst2|counter\(6));

-- Location: LCCOMB_X26_Y29_N22
\inst2|counter[7]~38\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|counter[7]~38_combout\ = (\inst2|counter\(7) & (!\inst2|counter[6]~37\)) # (!\inst2|counter\(7) & ((\inst2|counter[6]~37\) # (GND)))
-- \inst2|counter[7]~39\ = CARRY((!\inst2|counter[6]~37\) # (!\inst2|counter\(7)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst2|counter\(7),
	datad => VCC,
	cin => \inst2|counter[6]~37\,
	combout => \inst2|counter[7]~38_combout\,
	cout => \inst2|counter[7]~39\);

-- Location: FF_X26_Y29_N23
\inst2|counter[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst2|counter[7]~38_combout\,
	sclr => \inst2|LessThan0~10_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst2|counter\(7));

-- Location: LCCOMB_X26_Y29_N24
\inst2|counter[8]~40\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|counter[8]~40_combout\ = (\inst2|counter\(8) & (\inst2|counter[7]~39\ $ (GND))) # (!\inst2|counter\(8) & (!\inst2|counter[7]~39\ & VCC))
-- \inst2|counter[8]~41\ = CARRY((\inst2|counter\(8) & !\inst2|counter[7]~39\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \inst2|counter\(8),
	datad => VCC,
	cin => \inst2|counter[7]~39\,
	combout => \inst2|counter[8]~40_combout\,
	cout => \inst2|counter[8]~41\);

-- Location: FF_X26_Y29_N25
\inst2|counter[8]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst2|counter[8]~40_combout\,
	sclr => \inst2|LessThan0~10_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst2|counter\(8));

-- Location: LCCOMB_X26_Y29_N26
\inst2|counter[9]~42\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|counter[9]~42_combout\ = (\inst2|counter\(9) & (!\inst2|counter[8]~41\)) # (!\inst2|counter\(9) & ((\inst2|counter[8]~41\) # (GND)))
-- \inst2|counter[9]~43\ = CARRY((!\inst2|counter[8]~41\) # (!\inst2|counter\(9)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst2|counter\(9),
	datad => VCC,
	cin => \inst2|counter[8]~41\,
	combout => \inst2|counter[9]~42_combout\,
	cout => \inst2|counter[9]~43\);

-- Location: FF_X26_Y29_N27
\inst2|counter[9]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst2|counter[9]~42_combout\,
	sclr => \inst2|LessThan0~10_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst2|counter\(9));

-- Location: LCCOMB_X26_Y29_N28
\inst2|counter[10]~44\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|counter[10]~44_combout\ = (\inst2|counter\(10) & (\inst2|counter[9]~43\ $ (GND))) # (!\inst2|counter\(10) & (!\inst2|counter[9]~43\ & VCC))
-- \inst2|counter[10]~45\ = CARRY((\inst2|counter\(10) & !\inst2|counter[9]~43\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \inst2|counter\(10),
	datad => VCC,
	cin => \inst2|counter[9]~43\,
	combout => \inst2|counter[10]~44_combout\,
	cout => \inst2|counter[10]~45\);

-- Location: FF_X26_Y29_N29
\inst2|counter[10]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst2|counter[10]~44_combout\,
	sclr => \inst2|LessThan0~10_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst2|counter\(10));

-- Location: LCCOMB_X26_Y29_N30
\inst2|counter[11]~46\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|counter[11]~46_combout\ = (\inst2|counter\(11) & (!\inst2|counter[10]~45\)) # (!\inst2|counter\(11) & ((\inst2|counter[10]~45\) # (GND)))
-- \inst2|counter[11]~47\ = CARRY((!\inst2|counter[10]~45\) # (!\inst2|counter\(11)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst2|counter\(11),
	datad => VCC,
	cin => \inst2|counter[10]~45\,
	combout => \inst2|counter[11]~46_combout\,
	cout => \inst2|counter[11]~47\);

-- Location: FF_X26_Y29_N31
\inst2|counter[11]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst2|counter[11]~46_combout\,
	sclr => \inst2|LessThan0~10_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst2|counter\(11));

-- Location: LCCOMB_X26_Y28_N0
\inst2|counter[12]~48\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|counter[12]~48_combout\ = (\inst2|counter\(12) & (\inst2|counter[11]~47\ $ (GND))) # (!\inst2|counter\(12) & (!\inst2|counter[11]~47\ & VCC))
-- \inst2|counter[12]~49\ = CARRY((\inst2|counter\(12) & !\inst2|counter[11]~47\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \inst2|counter\(12),
	datad => VCC,
	cin => \inst2|counter[11]~47\,
	combout => \inst2|counter[12]~48_combout\,
	cout => \inst2|counter[12]~49\);

-- Location: FF_X26_Y28_N1
\inst2|counter[12]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst2|counter[12]~48_combout\,
	sclr => \inst2|LessThan0~10_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst2|counter\(12));

-- Location: FF_X26_Y28_N3
\inst2|counter[13]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst2|counter[13]~50_combout\,
	sclr => \inst2|LessThan0~10_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst2|counter\(13));

-- Location: LCCOMB_X25_Y23_N4
\inst2|LessThan0~5\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|LessThan0~5_combout\ = (!\inst2|counter\(13) & (!\inst2|counter\(15) & (!\inst2|counter\(12) & !\inst2|counter\(16))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst2|counter\(13),
	datab => \inst2|counter\(15),
	datac => \inst2|counter\(12),
	datad => \inst2|counter\(16),
	combout => \inst2|LessThan0~5_combout\);

-- Location: LCCOMB_X25_Y23_N6
\inst2|LessThan0~7\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|LessThan0~7_combout\ = (\inst2|LessThan0~5_combout\) # (\inst2|LessThan0~6_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst2|LessThan0~5_combout\,
	datad => \inst2|LessThan0~6_combout\,
	combout => \inst2|LessThan0~7_combout\);

-- Location: LCCOMB_X25_Y23_N8
\inst2|ledBuf~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|ledBuf~0_combout\ = \inst2|ledBuf~q\ $ (((!\inst2|LessThan0~7_combout\ & (!\inst2|LessThan0~9_combout\ & !\inst2|LessThan0~4_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011100001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst2|LessThan0~7_combout\,
	datab => \inst2|LessThan0~9_combout\,
	datac => \inst2|ledBuf~q\,
	datad => \inst2|LessThan0~4_combout\,
	combout => \inst2|ledBuf~0_combout\);

-- Location: FF_X25_Y23_N9
\inst2|ledBuf\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \FPGA_CLK~inputclkctrl_outclk\,
	d => \inst2|ledBuf~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst2|ledBuf~q\);

-- Location: PLL_1
\inst|altpll_component|auto_generated|pll1\ : cycloneiii_pll
-- pragma translate_off
GENERIC MAP (
	auto_settings => "false",
	bandwidth_type => "medium",
	c0_high => 3,
	c0_initial => 1,
	c0_low => 3,
	c0_mode => "even",
	c0_ph => 0,
	c1_high => 2,
	c1_initial => 1,
	c1_low => 1,
	c1_mode => "odd",
	c1_ph => 0,
	c1_use_casc_in => "off",
	c2_high => 0,
	c2_initial => 0,
	c2_low => 0,
	c2_mode => "bypass",
	c2_ph => 0,
	c2_use_casc_in => "off",
	c3_high => 0,
	c3_initial => 0,
	c3_low => 0,
	c3_mode => "bypass",
	c3_ph => 0,
	c3_use_casc_in => "off",
	c4_high => 0,
	c4_initial => 0,
	c4_low => 0,
	c4_mode => "bypass",
	c4_ph => 0,
	c4_use_casc_in => "off",
	charge_pump_current_bits => 1,
	clk0_counter => "c0",
	clk0_divide_by => 1,
	clk0_duty_cycle => 50,
	clk0_multiply_by => 4,
	clk0_phase_shift => "0",
	clk1_counter => "c1",
	clk1_divide_by => 1,
	clk1_duty_cycle => 50,
	clk1_multiply_by => 8,
	clk1_phase_shift => "0",
	clk2_counter => "unused",
	clk2_divide_by => 0,
	clk2_duty_cycle => 50,
	clk2_multiply_by => 0,
	clk2_phase_shift => "0",
	clk3_counter => "unused",
	clk3_divide_by => 0,
	clk3_duty_cycle => 50,
	clk3_multiply_by => 0,
	clk3_phase_shift => "0",
	clk4_counter => "unused",
	clk4_divide_by => 0,
	clk4_duty_cycle => 50,
	clk4_multiply_by => 0,
	clk4_phase_shift => "0",
	compensate_clock => "clock0",
	inclk0_input_frequency => 40000,
	inclk1_input_frequency => 0,
	loop_filter_c_bits => 0,
	loop_filter_r_bits => 24,
	m => 24,
	m_initial => 1,
	m_ph => 0,
	n => 1,
	operation_mode => "normal",
	pfd_max => 200000,
	pfd_min => 3076,
	pll_compensation_delay => 7057,
	self_reset_on_loss_lock => "off",
	simulation_type => "timing",
	switch_over_type => "auto",
	vco_center => 1538,
	vco_divide_by => 0,
	vco_frequency_control => "auto",
	vco_max => 3333,
	vco_min => 1538,
	vco_multiply_by => 0,
	vco_phase_shift_step => 208,
	vco_post_scale => 2)
-- pragma translate_on
PORT MAP (
	areset => GND,
	fbin => \inst|altpll_component|auto_generated|wire_pll1_fbout\,
	inclk => \inst|altpll_component|auto_generated|pll1_INCLK_bus\,
	fbout => \inst|altpll_component|auto_generated|wire_pll1_fbout\,
	clk => \inst|altpll_component|auto_generated|pll1_CLK_bus\);

-- Location: CLKCTRL_G3
\inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl\ : cycloneiii_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk\);

-- Location: CLKCTRL_G4
\inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl\ : cycloneiii_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk\);
END structure;