altera/MainController/simulation/modelsim/MainController.vho

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-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- VENDOR "Altera"
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"
-- DATE "03/04/2024 16:45:11"
--
-- Device: Altera EP3C25Q240C8 Package PQFP240
--
--
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
--
LIBRARY CYCLONEIII;
LIBRARY IEEE;
USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MainController IS
PORT (
Clk : IN std_logic;
ClkRAM : IN std_logic;
WR : IN std_logic;
AddressRAM : IN std_logic_vector(7 DOWNTO 0);
DataRAM : IN std_logic_vector(15 DOWNTO 0)
);
END MainController;
-- Design Ports Information
-- Clk => Location: PIN_81, I/O Standard: 2.5 V, Current Strength: Default
-- ClkRAM => Location: PIN_127, I/O Standard: 2.5 V, Current Strength: Default
-- WR => Location: PIN_98, I/O Standard: 2.5 V, Current Strength: Default
-- AddressRAM[7] => Location: PIN_41, I/O Standard: 2.5 V, Current Strength: Default
-- AddressRAM[6] => Location: PIN_132, I/O Standard: 2.5 V, Current Strength: Default
-- AddressRAM[5] => Location: PIN_230, I/O Standard: 2.5 V, Current Strength: Default
-- AddressRAM[4] => Location: PIN_135, I/O Standard: 2.5 V, Current Strength: Default
-- AddressRAM[3] => Location: PIN_65, I/O Standard: 2.5 V, Current Strength: Default
-- AddressRAM[2] => Location: PIN_181, I/O Standard: 2.5 V, Current Strength: Default
-- AddressRAM[1] => Location: PIN_64, I/O Standard: 2.5 V, Current Strength: Default
-- AddressRAM[0] => Location: PIN_173, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[15] => Location: PIN_103, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[14] => Location: PIN_145, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[13] => Location: PIN_38, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[12] => Location: PIN_144, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[11] => Location: PIN_160, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[10] => Location: PIN_149, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[9] => Location: PIN_150, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[8] => Location: PIN_133, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[7] => Location: PIN_151, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[6] => Location: PIN_152, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[5] => Location: PIN_197, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[4] => Location: PIN_113, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[3] => Location: PIN_161, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[2] => Location: PIN_168, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[1] => Location: PIN_166, I/O Standard: 2.5 V, Current Strength: Default
-- DataRAM[0] => Location: PIN_119, I/O Standard: 2.5 V, Current Strength: Default
ARCHITECTURE structure OF MainController IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_Clk : std_logic;
SIGNAL ww_ClkRAM : std_logic;
SIGNAL ww_WR : std_logic;
SIGNAL ww_AddressRAM : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_DataRAM : std_logic_vector(15 DOWNTO 0);
SIGNAL \Clk~input_o\ : std_logic;
SIGNAL \ClkRAM~input_o\ : std_logic;
SIGNAL \WR~input_o\ : std_logic;
SIGNAL \AddressRAM[7]~input_o\ : std_logic;
SIGNAL \AddressRAM[6]~input_o\ : std_logic;
SIGNAL \AddressRAM[5]~input_o\ : std_logic;
SIGNAL \AddressRAM[4]~input_o\ : std_logic;
SIGNAL \AddressRAM[3]~input_o\ : std_logic;
SIGNAL \AddressRAM[2]~input_o\ : std_logic;
SIGNAL \AddressRAM[1]~input_o\ : std_logic;
SIGNAL \AddressRAM[0]~input_o\ : std_logic;
SIGNAL \DataRAM[15]~input_o\ : std_logic;
SIGNAL \DataRAM[14]~input_o\ : std_logic;
SIGNAL \DataRAM[13]~input_o\ : std_logic;
SIGNAL \DataRAM[12]~input_o\ : std_logic;
SIGNAL \DataRAM[11]~input_o\ : std_logic;
SIGNAL \DataRAM[10]~input_o\ : std_logic;
SIGNAL \DataRAM[9]~input_o\ : std_logic;
SIGNAL \DataRAM[8]~input_o\ : std_logic;
SIGNAL \DataRAM[7]~input_o\ : std_logic;
SIGNAL \DataRAM[6]~input_o\ : std_logic;
SIGNAL \DataRAM[5]~input_o\ : std_logic;
SIGNAL \DataRAM[4]~input_o\ : std_logic;
SIGNAL \DataRAM[3]~input_o\ : std_logic;
SIGNAL \DataRAM[2]~input_o\ : std_logic;
SIGNAL \DataRAM[1]~input_o\ : std_logic;
SIGNAL \DataRAM[0]~input_o\ : std_logic;
BEGIN
ww_Clk <= Clk;
ww_ClkRAM <= ClkRAM;
ww_WR <= WR;
ww_AddressRAM <= AddressRAM;
ww_DataRAM <= DataRAM;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
-- Location: IOIBUF_X14_Y0_N8
\Clk~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_Clk,
o => \Clk~input_o\);
-- Location: IOIBUF_X53_Y6_N15
\ClkRAM~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_ClkRAM,
o => \ClkRAM~input_o\);
-- Location: IOIBUF_X34_Y0_N22
\WR~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_WR,
o => \WR~input_o\);
-- Location: IOIBUF_X0_Y12_N1
\AddressRAM[7]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_AddressRAM(7),
o => \AddressRAM[7]~input_o\);
-- Location: IOIBUF_X53_Y9_N15
\AddressRAM[6]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_AddressRAM(6),
o => \AddressRAM[6]~input_o\);
-- Location: IOIBUF_X14_Y34_N8
\AddressRAM[5]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_AddressRAM(5),
o => \AddressRAM[5]~input_o\);
-- Location: IOIBUF_X53_Y10_N15
\AddressRAM[4]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_AddressRAM(4),
o => \AddressRAM[4]~input_o\);
-- Location: IOIBUF_X3_Y0_N22
\AddressRAM[3]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_AddressRAM(3),
o => \AddressRAM[3]~input_o\);
-- Location: IOIBUF_X51_Y34_N8
\AddressRAM[2]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_AddressRAM(2),
o => \AddressRAM[2]~input_o\);
-- Location: IOIBUF_X1_Y0_N1
\AddressRAM[1]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_AddressRAM(1),
o => \AddressRAM[1]~input_o\);
-- Location: IOIBUF_X53_Y26_N22
\AddressRAM[0]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_AddressRAM(0),
o => \AddressRAM[0]~input_o\);
-- Location: IOIBUF_X36_Y0_N8
\DataRAM[15]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(15),
o => \DataRAM[15]~input_o\);
-- Location: IOIBUF_X53_Y14_N1
\DataRAM[14]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(14),
o => \DataRAM[14]~input_o\);
-- Location: IOIBUF_X0_Y14_N8
\DataRAM[13]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(13),
o => \DataRAM[13]~input_o\);
-- Location: IOIBUF_X53_Y14_N8
\DataRAM[12]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(12),
o => \DataRAM[12]~input_o\);
-- Location: IOIBUF_X53_Y20_N15
\DataRAM[11]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(11),
o => \DataRAM[11]~input_o\);
-- Location: IOIBUF_X53_Y17_N22
\DataRAM[10]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(10),
o => \DataRAM[10]~input_o\);
-- Location: IOIBUF_X53_Y17_N15
\DataRAM[9]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(9),
o => \DataRAM[9]~input_o\);
-- Location: IOIBUF_X53_Y9_N8
\DataRAM[8]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(8),
o => \DataRAM[8]~input_o\);
-- Location: IOIBUF_X53_Y17_N8
\DataRAM[7]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(7),
o => \DataRAM[7]~input_o\);
-- Location: IOIBUF_X53_Y17_N1
\DataRAM[6]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(6),
o => \DataRAM[6]~input_o\);
-- Location: IOIBUF_X38_Y34_N22
\DataRAM[5]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(5),
o => \DataRAM[5]~input_o\);
-- Location: IOIBUF_X45_Y0_N15
\DataRAM[4]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(4),
o => \DataRAM[4]~input_o\);
-- Location: IOIBUF_X53_Y21_N22
\DataRAM[3]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(3),
o => \DataRAM[3]~input_o\);
-- Location: IOIBUF_X53_Y23_N15
\DataRAM[2]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(2),
o => \DataRAM[2]~input_o\);
-- Location: IOIBUF_X53_Y22_N1
\DataRAM[1]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(1),
o => \DataRAM[1]~input_o\);
-- Location: IOIBUF_X51_Y0_N15
\DataRAM[0]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_DataRAM(0),
o => \DataRAM[0]~input_o\);
END structure;