2024-03-04 17:16:43 +03:00
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-- Copyright (C) 1991-2013 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, Altera MegaCore Function License
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-- Agreement, or other applicable license agreement, including,
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-- without limitation, that your use is for the sole purpose of
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-- programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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-- VENDOR "Altera"
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-- PROGRAM "Quartus II 64-Bit"
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-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"
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2024-03-12 16:30:45 +03:00
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-- DATE "03/12/2024 16:24:29"
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2024-03-04 17:16:43 +03:00
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--
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-- Device: Altera EP3C25Q240C8 Package PQFP240
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--
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--
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-- This VHDL file should be used for ModelSim-Altera (VHDL) only
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--
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2024-03-12 16:30:45 +03:00
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LIBRARY ALTERA;
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2024-03-04 17:16:43 +03:00
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LIBRARY CYCLONEIII;
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LIBRARY IEEE;
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2024-03-12 16:30:45 +03:00
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USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
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USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
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USE IEEE.STD_LOGIC_1164.ALL;
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ENTITY MainController IS
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PORT (
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2024-03-12 16:30:45 +03:00
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FPGA_LED_1 : OUT std_logic;
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FPGA_CLK : IN std_logic;
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Data : INOUT std_logic_vector(7 DOWNTO 0);
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Address : IN std_logic_vector(7 DOWNTO 0);
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nOE : IN std_logic;
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nWE : IN std_logic;
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nCE : IN std_logic
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);
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END MainController;
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-- Design Ports Information
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-- FPGA_LED_1 => Location: PIN_166, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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-- Address[7] => Location: PIN_195, I/O Standard: 3.3-V LVTTL, Current Strength: Default
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-- Address[6] => Location: PIN_230, I/O Standard: 3.3-V LVTTL, Current Strength: Default
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-- Address[5] => Location: PIN_235, I/O Standard: 3.3-V LVTTL, Current Strength: Default
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-- Address[4] => Location: PIN_232, I/O Standard: 3.3-V LVTTL, Current Strength: Default
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-- Address[3] => Location: PIN_233, I/O Standard: 3.3-V LVTTL, Current Strength: Default
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-- Address[2] => Location: PIN_234, I/O Standard: 3.3-V LVTTL, Current Strength: Default
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-- Address[1] => Location: PIN_231, I/O Standard: 3.3-V LVTTL, Current Strength: Default
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-- Address[0] => Location: PIN_196, I/O Standard: 3.3-V LVTTL, Current Strength: Default
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-- nOE => Location: PIN_217, I/O Standard: 3.3-V LVTTL, Current Strength: Default
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-- nWE => Location: PIN_218, I/O Standard: 3.3-V LVTTL, Current Strength: Default
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-- nCE => Location: PIN_219, I/O Standard: 3.3-V LVTTL, Current Strength: Default
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-- Data[7] => Location: PIN_221, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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-- Data[6] => Location: PIN_223, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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-- Data[5] => Location: PIN_224, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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-- Data[4] => Location: PIN_226, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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-- Data[3] => Location: PIN_187, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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-- Data[2] => Location: PIN_188, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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-- Data[1] => Location: PIN_189, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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-- Data[0] => Location: PIN_194, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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-- FPGA_CLK => Location: PIN_31, I/O Standard: 3.3-V LVTTL, Current Strength: Default
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ARCHITECTURE structure OF MainController IS
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SIGNAL gnd : std_logic := '0';
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SIGNAL vcc : std_logic := '1';
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SIGNAL unknown : std_logic := 'X';
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SIGNAL devoe : std_logic := '1';
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SIGNAL devclrn : std_logic := '1';
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SIGNAL devpor : std_logic := '1';
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SIGNAL ww_devoe : std_logic;
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SIGNAL ww_devclrn : std_logic;
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SIGNAL ww_devpor : std_logic;
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SIGNAL ww_FPGA_LED_1 : std_logic;
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SIGNAL ww_FPGA_CLK : std_logic;
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SIGNAL ww_Address : std_logic_vector(7 DOWNTO 0);
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SIGNAL ww_nOE : std_logic;
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SIGNAL ww_nWE : std_logic;
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SIGNAL ww_nCE : std_logic;
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SIGNAL \FPGA_CLK~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
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SIGNAL \Address[7]~input_o\ : std_logic;
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SIGNAL \Address[6]~input_o\ : std_logic;
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SIGNAL \Address[5]~input_o\ : std_logic;
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SIGNAL \Address[4]~input_o\ : std_logic;
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SIGNAL \Address[3]~input_o\ : std_logic;
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SIGNAL \Address[2]~input_o\ : std_logic;
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SIGNAL \Address[1]~input_o\ : std_logic;
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SIGNAL \Address[0]~input_o\ : std_logic;
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SIGNAL \nOE~input_o\ : std_logic;
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SIGNAL \nWE~input_o\ : std_logic;
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SIGNAL \nCE~input_o\ : std_logic;
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SIGNAL \Data[7]~input_o\ : std_logic;
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SIGNAL \Data[6]~input_o\ : std_logic;
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SIGNAL \Data[5]~input_o\ : std_logic;
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SIGNAL \Data[4]~input_o\ : std_logic;
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SIGNAL \Data[3]~input_o\ : std_logic;
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SIGNAL \Data[2]~input_o\ : std_logic;
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SIGNAL \Data[1]~input_o\ : std_logic;
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SIGNAL \Data[0]~input_o\ : std_logic;
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SIGNAL \Data[7]~output_o\ : std_logic;
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SIGNAL \Data[6]~output_o\ : std_logic;
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SIGNAL \Data[5]~output_o\ : std_logic;
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SIGNAL \Data[4]~output_o\ : std_logic;
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SIGNAL \Data[3]~output_o\ : std_logic;
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SIGNAL \Data[2]~output_o\ : std_logic;
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SIGNAL \Data[1]~output_o\ : std_logic;
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SIGNAL \Data[0]~output_o\ : std_logic;
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SIGNAL \FPGA_LED_1~output_o\ : std_logic;
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SIGNAL \FPGA_CLK~input_o\ : std_logic;
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SIGNAL \FPGA_CLK~inputclkctrl_outclk\ : std_logic;
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SIGNAL \inst2|counter[0]~24_combout\ : std_logic;
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SIGNAL \inst2|counter[0]~25\ : std_logic;
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SIGNAL \inst2|counter[1]~26_combout\ : std_logic;
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SIGNAL \inst2|counter[1]~27\ : std_logic;
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SIGNAL \inst2|counter[2]~28_combout\ : std_logic;
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SIGNAL \inst2|counter[2]~29\ : std_logic;
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SIGNAL \inst2|counter[3]~30_combout\ : std_logic;
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SIGNAL \inst2|counter[3]~31\ : std_logic;
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SIGNAL \inst2|counter[4]~32_combout\ : std_logic;
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SIGNAL \inst2|counter[4]~33\ : std_logic;
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SIGNAL \inst2|counter[5]~34_combout\ : std_logic;
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SIGNAL \inst2|counter[5]~35\ : std_logic;
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SIGNAL \inst2|counter[6]~36_combout\ : std_logic;
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SIGNAL \inst2|counter[6]~37\ : std_logic;
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SIGNAL \inst2|counter[7]~38_combout\ : std_logic;
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SIGNAL \inst2|counter[7]~39\ : std_logic;
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SIGNAL \inst2|counter[8]~40_combout\ : std_logic;
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SIGNAL \inst2|counter[8]~41\ : std_logic;
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SIGNAL \inst2|counter[9]~42_combout\ : std_logic;
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SIGNAL \inst2|counter[9]~43\ : std_logic;
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SIGNAL \inst2|counter[10]~44_combout\ : std_logic;
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SIGNAL \inst2|counter[10]~45\ : std_logic;
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SIGNAL \inst2|counter[11]~46_combout\ : std_logic;
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SIGNAL \inst2|counter[11]~47\ : std_logic;
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SIGNAL \inst2|counter[12]~48_combout\ : std_logic;
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SIGNAL \inst2|counter[12]~49\ : std_logic;
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SIGNAL \inst2|counter[13]~50_combout\ : std_logic;
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SIGNAL \inst2|counter[13]~51\ : std_logic;
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SIGNAL \inst2|counter[14]~52_combout\ : std_logic;
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SIGNAL \inst2|counter[14]~53\ : std_logic;
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SIGNAL \inst2|counter[15]~54_combout\ : std_logic;
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SIGNAL \inst2|counter[15]~55\ : std_logic;
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SIGNAL \inst2|counter[16]~56_combout\ : std_logic;
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SIGNAL \inst2|counter[16]~57\ : std_logic;
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SIGNAL \inst2|counter[17]~58_combout\ : std_logic;
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SIGNAL \inst2|LessThan0~0_combout\ : std_logic;
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SIGNAL \inst2|counter[17]~59\ : std_logic;
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SIGNAL \inst2|counter[18]~60_combout\ : std_logic;
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SIGNAL \inst2|counter[18]~61\ : std_logic;
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SIGNAL \inst2|counter[19]~62_combout\ : std_logic;
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SIGNAL \inst2|counter[19]~63\ : std_logic;
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SIGNAL \inst2|counter[20]~64_combout\ : std_logic;
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SIGNAL \inst2|counter[20]~65\ : std_logic;
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SIGNAL \inst2|counter[21]~66_combout\ : std_logic;
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SIGNAL \inst2|counter[21]~67\ : std_logic;
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SIGNAL \inst2|counter[22]~68_combout\ : std_logic;
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SIGNAL \inst2|counter[22]~69\ : std_logic;
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SIGNAL \inst2|counter[23]~70_combout\ : std_logic;
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SIGNAL \inst2|LessThan0~1_combout\ : std_logic;
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SIGNAL \inst2|LessThan0~2_combout\ : std_logic;
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SIGNAL \inst2|LessThan0~5_combout\ : std_logic;
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SIGNAL \inst2|LessThan0~3_combout\ : std_logic;
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SIGNAL \inst2|LessThan0~4_combout\ : std_logic;
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SIGNAL \inst2|LessThan0~6_combout\ : std_logic;
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SIGNAL \inst2|LessThan0~7_combout\ : std_logic;
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SIGNAL \inst2|LessThan0~8_combout\ : std_logic;
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SIGNAL \inst2|ledBuf~0_combout\ : std_logic;
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SIGNAL \inst2|ledBuf~q\ : std_logic;
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SIGNAL \inst2|counter\ : std_logic_vector(23 DOWNTO 0);
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SIGNAL \inst2|ALT_INV_LessThan0~8_combout\ : std_logic;
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SIGNAL \inst2|ALT_INV_ledBuf~q\ : std_logic;
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BEGIN
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FPGA_LED_1 <= ww_FPGA_LED_1;
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ww_FPGA_CLK <= FPGA_CLK;
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ww_Address <= Address;
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ww_nOE <= nOE;
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ww_nWE <= nWE;
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ww_nCE <= nCE;
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ww_devoe <= devoe;
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ww_devclrn <= devclrn;
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ww_devpor <= devpor;
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2024-03-12 16:30:45 +03:00
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\FPGA_CLK~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \FPGA_CLK~input_o\);
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\inst2|ALT_INV_LessThan0~8_combout\ <= NOT \inst2|LessThan0~8_combout\;
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\inst2|ALT_INV_ledBuf~q\ <= NOT \inst2|ledBuf~q\;
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-- Location: IOOBUF_X18_Y34_N2
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\Data[7]~output\ : cycloneiii_io_obuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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open_drain_output => "true")
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-- pragma translate_on
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PORT MAP (
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i => VCC,
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devoe => ww_devoe,
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o => \Data[7]~output_o\);
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2024-03-12 16:30:45 +03:00
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-- Location: IOOBUF_X18_Y34_N23
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\Data[6]~output\ : cycloneiii_io_obuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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open_drain_output => "true")
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2024-03-04 17:16:43 +03:00
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-- pragma translate_on
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PORT MAP (
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i => VCC,
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devoe => ww_devoe,
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o => \Data[6]~output_o\);
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2024-03-12 16:30:45 +03:00
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-- Location: IOOBUF_X16_Y34_N2
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\Data[5]~output\ : cycloneiii_io_obuf
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2024-03-04 17:16:43 +03:00
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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open_drain_output => "true")
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2024-03-04 17:16:43 +03:00
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-- pragma translate_on
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PORT MAP (
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i => VCC,
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devoe => ww_devoe,
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o => \Data[5]~output_o\);
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2024-03-12 16:30:45 +03:00
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-- Location: IOOBUF_X16_Y34_N16
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\Data[4]~output\ : cycloneiii_io_obuf
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2024-03-04 17:16:43 +03:00
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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2024-03-12 16:30:45 +03:00
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open_drain_output => "true")
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2024-03-04 17:16:43 +03:00
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-- pragma translate_on
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PORT MAP (
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i => VCC,
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devoe => ww_devoe,
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o => \Data[4]~output_o\);
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-- Location: IOOBUF_X45_Y34_N9
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\Data[3]~output\ : cycloneiii_io_obuf
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2024-03-04 17:16:43 +03:00
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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2024-03-12 16:30:45 +03:00
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open_drain_output => "true")
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2024-03-04 17:16:43 +03:00
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-- pragma translate_on
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PORT MAP (
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2024-03-12 16:30:45 +03:00
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i => VCC,
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devoe => ww_devoe,
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o => \Data[3]~output_o\);
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2024-03-04 17:16:43 +03:00
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2024-03-12 16:30:45 +03:00
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-- Location: IOOBUF_X45_Y34_N16
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\Data[2]~output\ : cycloneiii_io_obuf
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2024-03-04 17:16:43 +03:00
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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2024-03-12 16:30:45 +03:00
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open_drain_output => "true")
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2024-03-04 17:16:43 +03:00
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
2024-03-12 16:30:45 +03:00
|
|
|
i => VCC,
|
|
|
|
devoe => ww_devoe,
|
|
|
|
o => \Data[2]~output_o\);
|
2024-03-04 17:16:43 +03:00
|
|
|
|
2024-03-12 16:30:45 +03:00
|
|
|
-- Location: IOOBUF_X45_Y34_N23
|
|
|
|
\Data[1]~output\ : cycloneiii_io_obuf
|
2024-03-04 17:16:43 +03:00
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
bus_hold => "false",
|
2024-03-12 16:30:45 +03:00
|
|
|
open_drain_output => "true")
|
2024-03-04 17:16:43 +03:00
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
2024-03-12 16:30:45 +03:00
|
|
|
i => VCC,
|
|
|
|
devoe => ww_devoe,
|
|
|
|
o => \Data[1]~output_o\);
|
2024-03-04 17:16:43 +03:00
|
|
|
|
2024-03-12 16:30:45 +03:00
|
|
|
-- Location: IOOBUF_X40_Y34_N9
|
|
|
|
\Data[0]~output\ : cycloneiii_io_obuf
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
bus_hold => "false",
|
|
|
|
open_drain_output => "true")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
i => VCC,
|
|
|
|
devoe => ww_devoe,
|
|
|
|
o => \Data[0]~output_o\);
|
|
|
|
|
|
|
|
-- Location: IOOBUF_X53_Y22_N2
|
|
|
|
\FPGA_LED_1~output\ : cycloneiii_io_obuf
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
bus_hold => "false",
|
|
|
|
open_drain_output => "false")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
i => \inst2|ALT_INV_ledBuf~q\,
|
|
|
|
devoe => ww_devoe,
|
|
|
|
o => \FPGA_LED_1~output_o\);
|
|
|
|
|
|
|
|
-- Location: IOIBUF_X0_Y16_N1
|
|
|
|
\FPGA_CLK~input\ : cycloneiii_io_ibuf
|
2024-03-04 17:16:43 +03:00
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
bus_hold => "false",
|
|
|
|
simulate_z_as => "z")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
2024-03-12 16:30:45 +03:00
|
|
|
i => ww_FPGA_CLK,
|
|
|
|
o => \FPGA_CLK~input_o\);
|
|
|
|
|
|
|
|
-- Location: CLKCTRL_G4
|
|
|
|
\FPGA_CLK~inputclkctrl\ : cycloneiii_clkctrl
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
clock_type => "global clock",
|
|
|
|
ena_register_mode => "none")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
inclk => \FPGA_CLK~inputclkctrl_INCLK_bus\,
|
|
|
|
devclrn => ww_devclrn,
|
|
|
|
devpor => ww_devpor,
|
|
|
|
outclk => \FPGA_CLK~inputclkctrl_outclk\);
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y14_N8
|
|
|
|
\inst2|counter[0]~24\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|counter[0]~24_combout\ = \inst2|counter\(0) $ (VCC)
|
|
|
|
-- \inst2|counter[0]~25\ = CARRY(\inst2|counter\(0))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "0101010110101010",
|
|
|
|
sum_lutc_input => "datac")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
dataa => \inst2|counter\(0),
|
|
|
|
datad => VCC,
|
|
|
|
combout => \inst2|counter[0]~24_combout\,
|
|
|
|
cout => \inst2|counter[0]~25\);
|
|
|
|
|
|
|
|
-- Location: FF_X51_Y14_N9
|
|
|
|
\inst2|counter[0]\ : dffeas
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
is_wysiwyg => "true",
|
|
|
|
power_up => "low")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
clk => \FPGA_CLK~inputclkctrl_outclk\,
|
|
|
|
d => \inst2|counter[0]~24_combout\,
|
|
|
|
sclr => \inst2|ALT_INV_LessThan0~8_combout\,
|
|
|
|
devclrn => ww_devclrn,
|
|
|
|
devpor => ww_devpor,
|
|
|
|
q => \inst2|counter\(0));
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y14_N10
|
|
|
|
\inst2|counter[1]~26\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|counter[1]~26_combout\ = (\inst2|counter\(1) & (!\inst2|counter[0]~25\)) # (!\inst2|counter\(1) & ((\inst2|counter[0]~25\) # (GND)))
|
|
|
|
-- \inst2|counter[1]~27\ = CARRY((!\inst2|counter[0]~25\) # (!\inst2|counter\(1)))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "0011110000111111",
|
|
|
|
sum_lutc_input => "cin")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
datab => \inst2|counter\(1),
|
|
|
|
datad => VCC,
|
|
|
|
cin => \inst2|counter[0]~25\,
|
|
|
|
combout => \inst2|counter[1]~26_combout\,
|
|
|
|
cout => \inst2|counter[1]~27\);
|
|
|
|
|
|
|
|
-- Location: FF_X51_Y14_N11
|
|
|
|
\inst2|counter[1]\ : dffeas
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
is_wysiwyg => "true",
|
|
|
|
power_up => "low")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
clk => \FPGA_CLK~inputclkctrl_outclk\,
|
|
|
|
d => \inst2|counter[1]~26_combout\,
|
|
|
|
sclr => \inst2|ALT_INV_LessThan0~8_combout\,
|
|
|
|
devclrn => ww_devclrn,
|
|
|
|
devpor => ww_devpor,
|
|
|
|
q => \inst2|counter\(1));
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y14_N12
|
|
|
|
\inst2|counter[2]~28\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|counter[2]~28_combout\ = (\inst2|counter\(2) & (\inst2|counter[1]~27\ $ (GND))) # (!\inst2|counter\(2) & (!\inst2|counter[1]~27\ & VCC))
|
|
|
|
-- \inst2|counter[2]~29\ = CARRY((\inst2|counter\(2) & !\inst2|counter[1]~27\))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "1100001100001100",
|
|
|
|
sum_lutc_input => "cin")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
datab => \inst2|counter\(2),
|
|
|
|
datad => VCC,
|
|
|
|
cin => \inst2|counter[1]~27\,
|
|
|
|
combout => \inst2|counter[2]~28_combout\,
|
|
|
|
cout => \inst2|counter[2]~29\);
|
|
|
|
|
|
|
|
-- Location: FF_X51_Y14_N13
|
|
|
|
\inst2|counter[2]\ : dffeas
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
is_wysiwyg => "true",
|
|
|
|
power_up => "low")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
clk => \FPGA_CLK~inputclkctrl_outclk\,
|
|
|
|
d => \inst2|counter[2]~28_combout\,
|
|
|
|
sclr => \inst2|ALT_INV_LessThan0~8_combout\,
|
|
|
|
devclrn => ww_devclrn,
|
|
|
|
devpor => ww_devpor,
|
|
|
|
q => \inst2|counter\(2));
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y14_N14
|
|
|
|
\inst2|counter[3]~30\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|counter[3]~30_combout\ = (\inst2|counter\(3) & (!\inst2|counter[2]~29\)) # (!\inst2|counter\(3) & ((\inst2|counter[2]~29\) # (GND)))
|
|
|
|
-- \inst2|counter[3]~31\ = CARRY((!\inst2|counter[2]~29\) # (!\inst2|counter\(3)))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "0011110000111111",
|
|
|
|
sum_lutc_input => "cin")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
datab => \inst2|counter\(3),
|
|
|
|
datad => VCC,
|
|
|
|
cin => \inst2|counter[2]~29\,
|
|
|
|
combout => \inst2|counter[3]~30_combout\,
|
|
|
|
cout => \inst2|counter[3]~31\);
|
|
|
|
|
|
|
|
-- Location: FF_X51_Y14_N15
|
|
|
|
\inst2|counter[3]\ : dffeas
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
is_wysiwyg => "true",
|
|
|
|
power_up => "low")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
clk => \FPGA_CLK~inputclkctrl_outclk\,
|
|
|
|
d => \inst2|counter[3]~30_combout\,
|
|
|
|
sclr => \inst2|ALT_INV_LessThan0~8_combout\,
|
|
|
|
devclrn => ww_devclrn,
|
|
|
|
devpor => ww_devpor,
|
|
|
|
q => \inst2|counter\(3));
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y14_N16
|
|
|
|
\inst2|counter[4]~32\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|counter[4]~32_combout\ = (\inst2|counter\(4) & (\inst2|counter[3]~31\ $ (GND))) # (!\inst2|counter\(4) & (!\inst2|counter[3]~31\ & VCC))
|
|
|
|
-- \inst2|counter[4]~33\ = CARRY((\inst2|counter\(4) & !\inst2|counter[3]~31\))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "1010010100001010",
|
|
|
|
sum_lutc_input => "cin")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
dataa => \inst2|counter\(4),
|
|
|
|
datad => VCC,
|
|
|
|
cin => \inst2|counter[3]~31\,
|
|
|
|
combout => \inst2|counter[4]~32_combout\,
|
|
|
|
cout => \inst2|counter[4]~33\);
|
2024-03-04 17:16:43 +03:00
|
|
|
|
2024-03-12 16:30:45 +03:00
|
|
|
-- Location: FF_X51_Y14_N17
|
|
|
|
\inst2|counter[4]\ : dffeas
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
is_wysiwyg => "true",
|
|
|
|
power_up => "low")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
clk => \FPGA_CLK~inputclkctrl_outclk\,
|
|
|
|
d => \inst2|counter[4]~32_combout\,
|
|
|
|
sclr => \inst2|ALT_INV_LessThan0~8_combout\,
|
|
|
|
devclrn => ww_devclrn,
|
|
|
|
devpor => ww_devpor,
|
|
|
|
q => \inst2|counter\(4));
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y14_N18
|
|
|
|
\inst2|counter[5]~34\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|counter[5]~34_combout\ = (\inst2|counter\(5) & (!\inst2|counter[4]~33\)) # (!\inst2|counter\(5) & ((\inst2|counter[4]~33\) # (GND)))
|
|
|
|
-- \inst2|counter[5]~35\ = CARRY((!\inst2|counter[4]~33\) # (!\inst2|counter\(5)))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "0011110000111111",
|
|
|
|
sum_lutc_input => "cin")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
datab => \inst2|counter\(5),
|
|
|
|
datad => VCC,
|
|
|
|
cin => \inst2|counter[4]~33\,
|
|
|
|
combout => \inst2|counter[5]~34_combout\,
|
|
|
|
cout => \inst2|counter[5]~35\);
|
|
|
|
|
|
|
|
-- Location: FF_X51_Y14_N19
|
|
|
|
\inst2|counter[5]\ : dffeas
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
is_wysiwyg => "true",
|
|
|
|
power_up => "low")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
clk => \FPGA_CLK~inputclkctrl_outclk\,
|
|
|
|
d => \inst2|counter[5]~34_combout\,
|
|
|
|
sclr => \inst2|ALT_INV_LessThan0~8_combout\,
|
|
|
|
devclrn => ww_devclrn,
|
|
|
|
devpor => ww_devpor,
|
|
|
|
q => \inst2|counter\(5));
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y14_N20
|
|
|
|
\inst2|counter[6]~36\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|counter[6]~36_combout\ = (\inst2|counter\(6) & (\inst2|counter[5]~35\ $ (GND))) # (!\inst2|counter\(6) & (!\inst2|counter[5]~35\ & VCC))
|
|
|
|
-- \inst2|counter[6]~37\ = CARRY((\inst2|counter\(6) & !\inst2|counter[5]~35\))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "1100001100001100",
|
|
|
|
sum_lutc_input => "cin")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
datab => \inst2|counter\(6),
|
|
|
|
datad => VCC,
|
|
|
|
cin => \inst2|counter[5]~35\,
|
|
|
|
combout => \inst2|counter[6]~36_combout\,
|
|
|
|
cout => \inst2|counter[6]~37\);
|
|
|
|
|
|
|
|
-- Location: FF_X51_Y14_N21
|
|
|
|
\inst2|counter[6]\ : dffeas
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
is_wysiwyg => "true",
|
|
|
|
power_up => "low")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
clk => \FPGA_CLK~inputclkctrl_outclk\,
|
|
|
|
d => \inst2|counter[6]~36_combout\,
|
|
|
|
sclr => \inst2|ALT_INV_LessThan0~8_combout\,
|
|
|
|
devclrn => ww_devclrn,
|
|
|
|
devpor => ww_devpor,
|
|
|
|
q => \inst2|counter\(6));
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y14_N22
|
|
|
|
\inst2|counter[7]~38\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|counter[7]~38_combout\ = (\inst2|counter\(7) & (!\inst2|counter[6]~37\)) # (!\inst2|counter\(7) & ((\inst2|counter[6]~37\) # (GND)))
|
|
|
|
-- \inst2|counter[7]~39\ = CARRY((!\inst2|counter[6]~37\) # (!\inst2|counter\(7)))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "0011110000111111",
|
|
|
|
sum_lutc_input => "cin")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
datab => \inst2|counter\(7),
|
|
|
|
datad => VCC,
|
|
|
|
cin => \inst2|counter[6]~37\,
|
|
|
|
combout => \inst2|counter[7]~38_combout\,
|
|
|
|
cout => \inst2|counter[7]~39\);
|
|
|
|
|
|
|
|
-- Location: FF_X51_Y14_N23
|
|
|
|
\inst2|counter[7]\ : dffeas
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
is_wysiwyg => "true",
|
|
|
|
power_up => "low")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
clk => \FPGA_CLK~inputclkctrl_outclk\,
|
|
|
|
d => \inst2|counter[7]~38_combout\,
|
|
|
|
sclr => \inst2|ALT_INV_LessThan0~8_combout\,
|
|
|
|
devclrn => ww_devclrn,
|
|
|
|
devpor => ww_devpor,
|
|
|
|
q => \inst2|counter\(7));
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y14_N24
|
|
|
|
\inst2|counter[8]~40\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|counter[8]~40_combout\ = (\inst2|counter\(8) & (\inst2|counter[7]~39\ $ (GND))) # (!\inst2|counter\(8) & (!\inst2|counter[7]~39\ & VCC))
|
|
|
|
-- \inst2|counter[8]~41\ = CARRY((\inst2|counter\(8) & !\inst2|counter[7]~39\))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "1100001100001100",
|
|
|
|
sum_lutc_input => "cin")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
datab => \inst2|counter\(8),
|
|
|
|
datad => VCC,
|
|
|
|
cin => \inst2|counter[7]~39\,
|
|
|
|
combout => \inst2|counter[8]~40_combout\,
|
|
|
|
cout => \inst2|counter[8]~41\);
|
|
|
|
|
|
|
|
-- Location: FF_X51_Y14_N25
|
|
|
|
\inst2|counter[8]\ : dffeas
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
is_wysiwyg => "true",
|
|
|
|
power_up => "low")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
clk => \FPGA_CLK~inputclkctrl_outclk\,
|
|
|
|
d => \inst2|counter[8]~40_combout\,
|
|
|
|
sclr => \inst2|ALT_INV_LessThan0~8_combout\,
|
|
|
|
devclrn => ww_devclrn,
|
|
|
|
devpor => ww_devpor,
|
|
|
|
q => \inst2|counter\(8));
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y14_N26
|
|
|
|
\inst2|counter[9]~42\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|counter[9]~42_combout\ = (\inst2|counter\(9) & (!\inst2|counter[8]~41\)) # (!\inst2|counter\(9) & ((\inst2|counter[8]~41\) # (GND)))
|
|
|
|
-- \inst2|counter[9]~43\ = CARRY((!\inst2|counter[8]~41\) # (!\inst2|counter\(9)))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "0101101001011111",
|
|
|
|
sum_lutc_input => "cin")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
dataa => \inst2|counter\(9),
|
|
|
|
datad => VCC,
|
|
|
|
cin => \inst2|counter[8]~41\,
|
|
|
|
combout => \inst2|counter[9]~42_combout\,
|
|
|
|
cout => \inst2|counter[9]~43\);
|
|
|
|
|
|
|
|
-- Location: FF_X51_Y14_N27
|
|
|
|
\inst2|counter[9]\ : dffeas
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
is_wysiwyg => "true",
|
|
|
|
power_up => "low")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
clk => \FPGA_CLK~inputclkctrl_outclk\,
|
|
|
|
d => \inst2|counter[9]~42_combout\,
|
|
|
|
sclr => \inst2|ALT_INV_LessThan0~8_combout\,
|
|
|
|
devclrn => ww_devclrn,
|
|
|
|
devpor => ww_devpor,
|
|
|
|
q => \inst2|counter\(9));
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y14_N28
|
|
|
|
\inst2|counter[10]~44\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|counter[10]~44_combout\ = (\inst2|counter\(10) & (\inst2|counter[9]~43\ $ (GND))) # (!\inst2|counter\(10) & (!\inst2|counter[9]~43\ & VCC))
|
|
|
|
-- \inst2|counter[10]~45\ = CARRY((\inst2|counter\(10) & !\inst2|counter[9]~43\))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "1100001100001100",
|
|
|
|
sum_lutc_input => "cin")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
datab => \inst2|counter\(10),
|
|
|
|
datad => VCC,
|
|
|
|
cin => \inst2|counter[9]~43\,
|
|
|
|
combout => \inst2|counter[10]~44_combout\,
|
|
|
|
cout => \inst2|counter[10]~45\);
|
|
|
|
|
|
|
|
-- Location: FF_X51_Y14_N29
|
|
|
|
\inst2|counter[10]\ : dffeas
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
is_wysiwyg => "true",
|
|
|
|
power_up => "low")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
clk => \FPGA_CLK~inputclkctrl_outclk\,
|
|
|
|
d => \inst2|counter[10]~44_combout\,
|
|
|
|
sclr => \inst2|ALT_INV_LessThan0~8_combout\,
|
|
|
|
devclrn => ww_devclrn,
|
|
|
|
devpor => ww_devpor,
|
|
|
|
q => \inst2|counter\(10));
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y14_N30
|
|
|
|
\inst2|counter[11]~46\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|counter[11]~46_combout\ = (\inst2|counter\(11) & (!\inst2|counter[10]~45\)) # (!\inst2|counter\(11) & ((\inst2|counter[10]~45\) # (GND)))
|
|
|
|
-- \inst2|counter[11]~47\ = CARRY((!\inst2|counter[10]~45\) # (!\inst2|counter\(11)))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "0101101001011111",
|
|
|
|
sum_lutc_input => "cin")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
dataa => \inst2|counter\(11),
|
|
|
|
datad => VCC,
|
|
|
|
cin => \inst2|counter[10]~45\,
|
|
|
|
combout => \inst2|counter[11]~46_combout\,
|
|
|
|
cout => \inst2|counter[11]~47\);
|
|
|
|
|
|
|
|
-- Location: FF_X51_Y14_N31
|
|
|
|
\inst2|counter[11]\ : dffeas
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
is_wysiwyg => "true",
|
|
|
|
power_up => "low")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
clk => \FPGA_CLK~inputclkctrl_outclk\,
|
|
|
|
d => \inst2|counter[11]~46_combout\,
|
|
|
|
sclr => \inst2|ALT_INV_LessThan0~8_combout\,
|
|
|
|
devclrn => ww_devclrn,
|
|
|
|
devpor => ww_devpor,
|
|
|
|
q => \inst2|counter\(11));
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y13_N0
|
|
|
|
\inst2|counter[12]~48\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|counter[12]~48_combout\ = (\inst2|counter\(12) & (\inst2|counter[11]~47\ $ (GND))) # (!\inst2|counter\(12) & (!\inst2|counter[11]~47\ & VCC))
|
|
|
|
-- \inst2|counter[12]~49\ = CARRY((\inst2|counter\(12) & !\inst2|counter[11]~47\))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "1100001100001100",
|
|
|
|
sum_lutc_input => "cin")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
datab => \inst2|counter\(12),
|
|
|
|
datad => VCC,
|
|
|
|
cin => \inst2|counter[11]~47\,
|
|
|
|
combout => \inst2|counter[12]~48_combout\,
|
|
|
|
cout => \inst2|counter[12]~49\);
|
|
|
|
|
|
|
|
-- Location: FF_X51_Y13_N1
|
|
|
|
\inst2|counter[12]\ : dffeas
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
is_wysiwyg => "true",
|
|
|
|
power_up => "low")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
clk => \FPGA_CLK~inputclkctrl_outclk\,
|
|
|
|
d => \inst2|counter[12]~48_combout\,
|
|
|
|
sclr => \inst2|ALT_INV_LessThan0~8_combout\,
|
|
|
|
devclrn => ww_devclrn,
|
|
|
|
devpor => ww_devpor,
|
|
|
|
q => \inst2|counter\(12));
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y13_N2
|
|
|
|
\inst2|counter[13]~50\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|counter[13]~50_combout\ = (\inst2|counter\(13) & (!\inst2|counter[12]~49\)) # (!\inst2|counter\(13) & ((\inst2|counter[12]~49\) # (GND)))
|
|
|
|
-- \inst2|counter[13]~51\ = CARRY((!\inst2|counter[12]~49\) # (!\inst2|counter\(13)))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "0011110000111111",
|
|
|
|
sum_lutc_input => "cin")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
datab => \inst2|counter\(13),
|
|
|
|
datad => VCC,
|
|
|
|
cin => \inst2|counter[12]~49\,
|
|
|
|
combout => \inst2|counter[13]~50_combout\,
|
|
|
|
cout => \inst2|counter[13]~51\);
|
|
|
|
|
|
|
|
-- Location: FF_X51_Y13_N3
|
|
|
|
\inst2|counter[13]\ : dffeas
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
is_wysiwyg => "true",
|
|
|
|
power_up => "low")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
clk => \FPGA_CLK~inputclkctrl_outclk\,
|
|
|
|
d => \inst2|counter[13]~50_combout\,
|
|
|
|
sclr => \inst2|ALT_INV_LessThan0~8_combout\,
|
|
|
|
devclrn => ww_devclrn,
|
|
|
|
devpor => ww_devpor,
|
|
|
|
q => \inst2|counter\(13));
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y13_N4
|
|
|
|
\inst2|counter[14]~52\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|counter[14]~52_combout\ = (\inst2|counter\(14) & (\inst2|counter[13]~51\ $ (GND))) # (!\inst2|counter\(14) & (!\inst2|counter[13]~51\ & VCC))
|
|
|
|
-- \inst2|counter[14]~53\ = CARRY((\inst2|counter\(14) & !\inst2|counter[13]~51\))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "1100001100001100",
|
|
|
|
sum_lutc_input => "cin")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
datab => \inst2|counter\(14),
|
|
|
|
datad => VCC,
|
|
|
|
cin => \inst2|counter[13]~51\,
|
|
|
|
combout => \inst2|counter[14]~52_combout\,
|
|
|
|
cout => \inst2|counter[14]~53\);
|
|
|
|
|
|
|
|
-- Location: FF_X51_Y13_N5
|
|
|
|
\inst2|counter[14]\ : dffeas
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
is_wysiwyg => "true",
|
|
|
|
power_up => "low")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
clk => \FPGA_CLK~inputclkctrl_outclk\,
|
|
|
|
d => \inst2|counter[14]~52_combout\,
|
|
|
|
sclr => \inst2|ALT_INV_LessThan0~8_combout\,
|
|
|
|
devclrn => ww_devclrn,
|
|
|
|
devpor => ww_devpor,
|
|
|
|
q => \inst2|counter\(14));
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y13_N6
|
|
|
|
\inst2|counter[15]~54\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|counter[15]~54_combout\ = (\inst2|counter\(15) & (!\inst2|counter[14]~53\)) # (!\inst2|counter\(15) & ((\inst2|counter[14]~53\) # (GND)))
|
|
|
|
-- \inst2|counter[15]~55\ = CARRY((!\inst2|counter[14]~53\) # (!\inst2|counter\(15)))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "0101101001011111",
|
|
|
|
sum_lutc_input => "cin")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
dataa => \inst2|counter\(15),
|
|
|
|
datad => VCC,
|
|
|
|
cin => \inst2|counter[14]~53\,
|
|
|
|
combout => \inst2|counter[15]~54_combout\,
|
|
|
|
cout => \inst2|counter[15]~55\);
|
|
|
|
|
|
|
|
-- Location: FF_X51_Y13_N7
|
|
|
|
\inst2|counter[15]\ : dffeas
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
is_wysiwyg => "true",
|
|
|
|
power_up => "low")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
clk => \FPGA_CLK~inputclkctrl_outclk\,
|
|
|
|
d => \inst2|counter[15]~54_combout\,
|
|
|
|
sclr => \inst2|ALT_INV_LessThan0~8_combout\,
|
|
|
|
devclrn => ww_devclrn,
|
|
|
|
devpor => ww_devpor,
|
|
|
|
q => \inst2|counter\(15));
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y13_N8
|
|
|
|
\inst2|counter[16]~56\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|counter[16]~56_combout\ = (\inst2|counter\(16) & (\inst2|counter[15]~55\ $ (GND))) # (!\inst2|counter\(16) & (!\inst2|counter[15]~55\ & VCC))
|
|
|
|
-- \inst2|counter[16]~57\ = CARRY((\inst2|counter\(16) & !\inst2|counter[15]~55\))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "1100001100001100",
|
|
|
|
sum_lutc_input => "cin")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
datab => \inst2|counter\(16),
|
|
|
|
datad => VCC,
|
|
|
|
cin => \inst2|counter[15]~55\,
|
|
|
|
combout => \inst2|counter[16]~56_combout\,
|
|
|
|
cout => \inst2|counter[16]~57\);
|
|
|
|
|
|
|
|
-- Location: FF_X51_Y13_N9
|
|
|
|
\inst2|counter[16]\ : dffeas
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
is_wysiwyg => "true",
|
|
|
|
power_up => "low")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
clk => \FPGA_CLK~inputclkctrl_outclk\,
|
|
|
|
d => \inst2|counter[16]~56_combout\,
|
|
|
|
sclr => \inst2|ALT_INV_LessThan0~8_combout\,
|
|
|
|
devclrn => ww_devclrn,
|
|
|
|
devpor => ww_devpor,
|
|
|
|
q => \inst2|counter\(16));
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y13_N10
|
|
|
|
\inst2|counter[17]~58\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|counter[17]~58_combout\ = (\inst2|counter\(17) & (!\inst2|counter[16]~57\)) # (!\inst2|counter\(17) & ((\inst2|counter[16]~57\) # (GND)))
|
|
|
|
-- \inst2|counter[17]~59\ = CARRY((!\inst2|counter[16]~57\) # (!\inst2|counter\(17)))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "0101101001011111",
|
|
|
|
sum_lutc_input => "cin")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
dataa => \inst2|counter\(17),
|
|
|
|
datad => VCC,
|
|
|
|
cin => \inst2|counter[16]~57\,
|
|
|
|
combout => \inst2|counter[17]~58_combout\,
|
|
|
|
cout => \inst2|counter[17]~59\);
|
|
|
|
|
|
|
|
-- Location: FF_X51_Y13_N11
|
|
|
|
\inst2|counter[17]\ : dffeas
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
is_wysiwyg => "true",
|
|
|
|
power_up => "low")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
clk => \FPGA_CLK~inputclkctrl_outclk\,
|
|
|
|
d => \inst2|counter[17]~58_combout\,
|
|
|
|
sclr => \inst2|ALT_INV_LessThan0~8_combout\,
|
|
|
|
devclrn => ww_devclrn,
|
|
|
|
devpor => ww_devpor,
|
|
|
|
q => \inst2|counter\(17));
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X50_Y13_N20
|
|
|
|
\inst2|LessThan0~0\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|LessThan0~0_combout\ = ((!\inst2|counter\(15) & (!\inst2|counter\(16) & !\inst2|counter\(14)))) # (!\inst2|counter\(17))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "0000111100011111",
|
|
|
|
sum_lutc_input => "datac")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
dataa => \inst2|counter\(15),
|
|
|
|
datab => \inst2|counter\(16),
|
|
|
|
datac => \inst2|counter\(17),
|
|
|
|
datad => \inst2|counter\(14),
|
|
|
|
combout => \inst2|LessThan0~0_combout\);
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y13_N12
|
|
|
|
\inst2|counter[18]~60\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|counter[18]~60_combout\ = (\inst2|counter\(18) & (\inst2|counter[17]~59\ $ (GND))) # (!\inst2|counter\(18) & (!\inst2|counter[17]~59\ & VCC))
|
|
|
|
-- \inst2|counter[18]~61\ = CARRY((\inst2|counter\(18) & !\inst2|counter[17]~59\))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "1010010100001010",
|
|
|
|
sum_lutc_input => "cin")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
dataa => \inst2|counter\(18),
|
|
|
|
datad => VCC,
|
|
|
|
cin => \inst2|counter[17]~59\,
|
|
|
|
combout => \inst2|counter[18]~60_combout\,
|
|
|
|
cout => \inst2|counter[18]~61\);
|
|
|
|
|
|
|
|
-- Location: FF_X51_Y13_N13
|
|
|
|
\inst2|counter[18]\ : dffeas
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
is_wysiwyg => "true",
|
|
|
|
power_up => "low")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
clk => \FPGA_CLK~inputclkctrl_outclk\,
|
|
|
|
d => \inst2|counter[18]~60_combout\,
|
|
|
|
sclr => \inst2|ALT_INV_LessThan0~8_combout\,
|
|
|
|
devclrn => ww_devclrn,
|
|
|
|
devpor => ww_devpor,
|
|
|
|
q => \inst2|counter\(18));
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y13_N14
|
|
|
|
\inst2|counter[19]~62\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|counter[19]~62_combout\ = (\inst2|counter\(19) & (!\inst2|counter[18]~61\)) # (!\inst2|counter\(19) & ((\inst2|counter[18]~61\) # (GND)))
|
|
|
|
-- \inst2|counter[19]~63\ = CARRY((!\inst2|counter[18]~61\) # (!\inst2|counter\(19)))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "0011110000111111",
|
|
|
|
sum_lutc_input => "cin")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
datab => \inst2|counter\(19),
|
|
|
|
datad => VCC,
|
|
|
|
cin => \inst2|counter[18]~61\,
|
|
|
|
combout => \inst2|counter[19]~62_combout\,
|
|
|
|
cout => \inst2|counter[19]~63\);
|
|
|
|
|
|
|
|
-- Location: FF_X51_Y13_N15
|
|
|
|
\inst2|counter[19]\ : dffeas
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
is_wysiwyg => "true",
|
|
|
|
power_up => "low")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
clk => \FPGA_CLK~inputclkctrl_outclk\,
|
|
|
|
d => \inst2|counter[19]~62_combout\,
|
|
|
|
sclr => \inst2|ALT_INV_LessThan0~8_combout\,
|
|
|
|
devclrn => ww_devclrn,
|
|
|
|
devpor => ww_devpor,
|
|
|
|
q => \inst2|counter\(19));
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y13_N16
|
|
|
|
\inst2|counter[20]~64\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|counter[20]~64_combout\ = (\inst2|counter\(20) & (\inst2|counter[19]~63\ $ (GND))) # (!\inst2|counter\(20) & (!\inst2|counter[19]~63\ & VCC))
|
|
|
|
-- \inst2|counter[20]~65\ = CARRY((\inst2|counter\(20) & !\inst2|counter[19]~63\))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "1100001100001100",
|
|
|
|
sum_lutc_input => "cin")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
datab => \inst2|counter\(20),
|
|
|
|
datad => VCC,
|
|
|
|
cin => \inst2|counter[19]~63\,
|
|
|
|
combout => \inst2|counter[20]~64_combout\,
|
|
|
|
cout => \inst2|counter[20]~65\);
|
|
|
|
|
|
|
|
-- Location: FF_X51_Y13_N17
|
|
|
|
\inst2|counter[20]\ : dffeas
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
is_wysiwyg => "true",
|
|
|
|
power_up => "low")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
clk => \FPGA_CLK~inputclkctrl_outclk\,
|
|
|
|
d => \inst2|counter[20]~64_combout\,
|
|
|
|
sclr => \inst2|ALT_INV_LessThan0~8_combout\,
|
|
|
|
devclrn => ww_devclrn,
|
|
|
|
devpor => ww_devpor,
|
|
|
|
q => \inst2|counter\(20));
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y13_N18
|
|
|
|
\inst2|counter[21]~66\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|counter[21]~66_combout\ = (\inst2|counter\(21) & (!\inst2|counter[20]~65\)) # (!\inst2|counter\(21) & ((\inst2|counter[20]~65\) # (GND)))
|
|
|
|
-- \inst2|counter[21]~67\ = CARRY((!\inst2|counter[20]~65\) # (!\inst2|counter\(21)))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "0011110000111111",
|
|
|
|
sum_lutc_input => "cin")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
datab => \inst2|counter\(21),
|
|
|
|
datad => VCC,
|
|
|
|
cin => \inst2|counter[20]~65\,
|
|
|
|
combout => \inst2|counter[21]~66_combout\,
|
|
|
|
cout => \inst2|counter[21]~67\);
|
|
|
|
|
|
|
|
-- Location: FF_X51_Y13_N19
|
|
|
|
\inst2|counter[21]\ : dffeas
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
is_wysiwyg => "true",
|
|
|
|
power_up => "low")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
clk => \FPGA_CLK~inputclkctrl_outclk\,
|
|
|
|
d => \inst2|counter[21]~66_combout\,
|
|
|
|
sclr => \inst2|ALT_INV_LessThan0~8_combout\,
|
|
|
|
devclrn => ww_devclrn,
|
|
|
|
devpor => ww_devpor,
|
|
|
|
q => \inst2|counter\(21));
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y13_N20
|
|
|
|
\inst2|counter[22]~68\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|counter[22]~68_combout\ = (\inst2|counter\(22) & (\inst2|counter[21]~67\ $ (GND))) # (!\inst2|counter\(22) & (!\inst2|counter[21]~67\ & VCC))
|
|
|
|
-- \inst2|counter[22]~69\ = CARRY((\inst2|counter\(22) & !\inst2|counter[21]~67\))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "1100001100001100",
|
|
|
|
sum_lutc_input => "cin")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
datab => \inst2|counter\(22),
|
|
|
|
datad => VCC,
|
|
|
|
cin => \inst2|counter[21]~67\,
|
|
|
|
combout => \inst2|counter[22]~68_combout\,
|
|
|
|
cout => \inst2|counter[22]~69\);
|
|
|
|
|
|
|
|
-- Location: FF_X51_Y13_N21
|
|
|
|
\inst2|counter[22]\ : dffeas
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
is_wysiwyg => "true",
|
|
|
|
power_up => "low")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
clk => \FPGA_CLK~inputclkctrl_outclk\,
|
|
|
|
d => \inst2|counter[22]~68_combout\,
|
|
|
|
sclr => \inst2|ALT_INV_LessThan0~8_combout\,
|
|
|
|
devclrn => ww_devclrn,
|
|
|
|
devpor => ww_devpor,
|
|
|
|
q => \inst2|counter\(22));
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y13_N22
|
|
|
|
\inst2|counter[23]~70\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|counter[23]~70_combout\ = \inst2|counter\(23) $ (\inst2|counter[22]~69\)
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "0101101001011010",
|
|
|
|
sum_lutc_input => "cin")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
dataa => \inst2|counter\(23),
|
|
|
|
cin => \inst2|counter[22]~69\,
|
|
|
|
combout => \inst2|counter[23]~70_combout\);
|
|
|
|
|
|
|
|
-- Location: FF_X51_Y13_N23
|
|
|
|
\inst2|counter[23]\ : dffeas
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
is_wysiwyg => "true",
|
|
|
|
power_up => "low")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
clk => \FPGA_CLK~inputclkctrl_outclk\,
|
|
|
|
d => \inst2|counter[23]~70_combout\,
|
|
|
|
sclr => \inst2|ALT_INV_LessThan0~8_combout\,
|
|
|
|
devclrn => ww_devclrn,
|
|
|
|
devpor => ww_devpor,
|
|
|
|
q => \inst2|counter\(23));
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y13_N24
|
|
|
|
\inst2|LessThan0~1\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|LessThan0~1_combout\ = (((!\inst2|counter\(21)) # (!\inst2|counter\(19))) # (!\inst2|counter\(20))) # (!\inst2|counter\(18))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "0111111111111111",
|
|
|
|
sum_lutc_input => "datac")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
dataa => \inst2|counter\(18),
|
|
|
|
datab => \inst2|counter\(20),
|
|
|
|
datac => \inst2|counter\(19),
|
|
|
|
datad => \inst2|counter\(21),
|
|
|
|
combout => \inst2|LessThan0~1_combout\);
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y13_N30
|
|
|
|
\inst2|LessThan0~2\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|LessThan0~2_combout\ = ((\inst2|LessThan0~1_combout\) # (!\inst2|counter\(23))) # (!\inst2|counter\(22))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "1111111100111111",
|
|
|
|
sum_lutc_input => "datac")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
datab => \inst2|counter\(22),
|
|
|
|
datac => \inst2|counter\(23),
|
|
|
|
datad => \inst2|LessThan0~1_combout\,
|
|
|
|
combout => \inst2|LessThan0~2_combout\);
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y14_N4
|
|
|
|
\inst2|LessThan0~5\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|LessThan0~5_combout\ = (!\inst2|counter\(9) & (!\inst2|counter\(8) & (!\inst2|counter\(7) & !\inst2|counter\(10))))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "0000000000000001",
|
|
|
|
sum_lutc_input => "datac")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
dataa => \inst2|counter\(9),
|
|
|
|
datab => \inst2|counter\(8),
|
|
|
|
datac => \inst2|counter\(7),
|
|
|
|
datad => \inst2|counter\(10),
|
|
|
|
combout => \inst2|LessThan0~5_combout\);
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y14_N0
|
|
|
|
\inst2|LessThan0~3\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|LessThan0~3_combout\ = (!\inst2|counter\(2) & (!\inst2|counter\(4) & ((!\inst2|counter\(1)) # (!\inst2|counter\(0)))))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "0000000100010001",
|
|
|
|
sum_lutc_input => "datac")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
dataa => \inst2|counter\(2),
|
|
|
|
datab => \inst2|counter\(4),
|
|
|
|
datac => \inst2|counter\(0),
|
|
|
|
datad => \inst2|counter\(1),
|
|
|
|
combout => \inst2|LessThan0~3_combout\);
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y14_N6
|
|
|
|
\inst2|LessThan0~4\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|LessThan0~4_combout\ = ((\inst2|LessThan0~3_combout\) # ((!\inst2|counter\(4) & !\inst2|counter\(3)))) # (!\inst2|counter\(5))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "1111111100110111",
|
|
|
|
sum_lutc_input => "datac")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
dataa => \inst2|counter\(4),
|
|
|
|
datab => \inst2|counter\(5),
|
|
|
|
datac => \inst2|counter\(3),
|
|
|
|
datad => \inst2|LessThan0~3_combout\,
|
|
|
|
combout => \inst2|LessThan0~4_combout\);
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y14_N2
|
|
|
|
\inst2|LessThan0~6\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|LessThan0~6_combout\ = (!\inst2|counter\(11) & (!\inst2|counter\(6) & (\inst2|LessThan0~5_combout\ & \inst2|LessThan0~4_combout\)))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "0001000000000000",
|
|
|
|
sum_lutc_input => "datac")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
dataa => \inst2|counter\(11),
|
|
|
|
datab => \inst2|counter\(6),
|
|
|
|
datac => \inst2|LessThan0~5_combout\,
|
|
|
|
datad => \inst2|LessThan0~4_combout\,
|
|
|
|
combout => \inst2|LessThan0~6_combout\);
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y13_N28
|
|
|
|
\inst2|LessThan0~7\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|LessThan0~7_combout\ = (\inst2|counter\(16)) # ((\inst2|counter\(13)) # ((\inst2|counter\(12) & !\inst2|LessThan0~6_combout\)))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "1111101011111110",
|
|
|
|
sum_lutc_input => "datac")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
dataa => \inst2|counter\(16),
|
|
|
|
datab => \inst2|counter\(12),
|
|
|
|
datac => \inst2|counter\(13),
|
|
|
|
datad => \inst2|LessThan0~6_combout\,
|
|
|
|
combout => \inst2|LessThan0~7_combout\);
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X51_Y13_N26
|
|
|
|
\inst2|LessThan0~8\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|LessThan0~8_combout\ = (\inst2|LessThan0~0_combout\) # ((\inst2|LessThan0~2_combout\) # ((!\inst2|counter\(15) & !\inst2|LessThan0~7_combout\)))
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "1111110011111101",
|
|
|
|
sum_lutc_input => "datac")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
dataa => \inst2|counter\(15),
|
|
|
|
datab => \inst2|LessThan0~0_combout\,
|
|
|
|
datac => \inst2|LessThan0~2_combout\,
|
|
|
|
datad => \inst2|LessThan0~7_combout\,
|
|
|
|
combout => \inst2|LessThan0~8_combout\);
|
|
|
|
|
|
|
|
-- Location: LCCOMB_X52_Y13_N0
|
|
|
|
\inst2|ledBuf~0\ : cycloneiii_lcell_comb
|
|
|
|
-- Equation(s):
|
|
|
|
-- \inst2|ledBuf~0_combout\ = \inst2|ledBuf~q\ $ (!\inst2|LessThan0~8_combout\)
|
|
|
|
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
lut_mask => "1111000000001111",
|
|
|
|
sum_lutc_input => "datac")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
datac => \inst2|ledBuf~q\,
|
|
|
|
datad => \inst2|LessThan0~8_combout\,
|
|
|
|
combout => \inst2|ledBuf~0_combout\);
|
|
|
|
|
|
|
|
-- Location: FF_X52_Y13_N1
|
|
|
|
\inst2|ledBuf\ : dffeas
|
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
is_wysiwyg => "true",
|
|
|
|
power_up => "low")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
|
|
|
clk => \FPGA_CLK~inputclkctrl_outclk\,
|
|
|
|
d => \inst2|ledBuf~0_combout\,
|
|
|
|
devclrn => ww_devclrn,
|
|
|
|
devpor => ww_devpor,
|
|
|
|
q => \inst2|ledBuf~q\);
|
|
|
|
|
|
|
|
-- Location: IOIBUF_X38_Y34_N1
|
|
|
|
\Address[7]~input\ : cycloneiii_io_ibuf
|
2024-03-04 17:16:43 +03:00
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
bus_hold => "false",
|
|
|
|
simulate_z_as => "z")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
2024-03-12 16:30:45 +03:00
|
|
|
i => ww_Address(7),
|
|
|
|
o => \Address[7]~input_o\);
|
2024-03-04 17:16:43 +03:00
|
|
|
|
2024-03-12 16:30:45 +03:00
|
|
|
-- Location: IOIBUF_X14_Y34_N8
|
|
|
|
\Address[6]~input\ : cycloneiii_io_ibuf
|
2024-03-04 17:16:43 +03:00
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
bus_hold => "false",
|
|
|
|
simulate_z_as => "z")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
2024-03-12 16:30:45 +03:00
|
|
|
i => ww_Address(6),
|
|
|
|
o => \Address[6]~input_o\);
|
2024-03-04 17:16:43 +03:00
|
|
|
|
2024-03-12 16:30:45 +03:00
|
|
|
-- Location: IOIBUF_X7_Y34_N15
|
|
|
|
\Address[5]~input\ : cycloneiii_io_ibuf
|
2024-03-04 17:16:43 +03:00
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
bus_hold => "false",
|
|
|
|
simulate_z_as => "z")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
2024-03-12 16:30:45 +03:00
|
|
|
i => ww_Address(5),
|
|
|
|
o => \Address[5]~input_o\);
|
2024-03-04 17:16:43 +03:00
|
|
|
|
2024-03-12 16:30:45 +03:00
|
|
|
-- Location: IOIBUF_X14_Y34_N22
|
|
|
|
\Address[4]~input\ : cycloneiii_io_ibuf
|
2024-03-04 17:16:43 +03:00
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
bus_hold => "false",
|
|
|
|
simulate_z_as => "z")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
2024-03-12 16:30:45 +03:00
|
|
|
i => ww_Address(4),
|
|
|
|
o => \Address[4]~input_o\);
|
2024-03-04 17:16:43 +03:00
|
|
|
|
2024-03-12 16:30:45 +03:00
|
|
|
-- Location: IOIBUF_X7_Y34_N1
|
|
|
|
\Address[3]~input\ : cycloneiii_io_ibuf
|
2024-03-04 17:16:43 +03:00
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
bus_hold => "false",
|
|
|
|
simulate_z_as => "z")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
2024-03-12 16:30:45 +03:00
|
|
|
i => ww_Address(3),
|
|
|
|
o => \Address[3]~input_o\);
|
2024-03-04 17:16:43 +03:00
|
|
|
|
2024-03-12 16:30:45 +03:00
|
|
|
-- Location: IOIBUF_X7_Y34_N8
|
|
|
|
\Address[2]~input\ : cycloneiii_io_ibuf
|
2024-03-04 17:16:43 +03:00
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
bus_hold => "false",
|
|
|
|
simulate_z_as => "z")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
2024-03-12 16:30:45 +03:00
|
|
|
i => ww_Address(2),
|
|
|
|
o => \Address[2]~input_o\);
|
2024-03-04 17:16:43 +03:00
|
|
|
|
2024-03-12 16:30:45 +03:00
|
|
|
-- Location: IOIBUF_X14_Y34_N15
|
|
|
|
\Address[1]~input\ : cycloneiii_io_ibuf
|
2024-03-04 17:16:43 +03:00
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
bus_hold => "false",
|
|
|
|
simulate_z_as => "z")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
2024-03-12 16:30:45 +03:00
|
|
|
i => ww_Address(1),
|
|
|
|
o => \Address[1]~input_o\);
|
2024-03-04 17:16:43 +03:00
|
|
|
|
2024-03-12 16:30:45 +03:00
|
|
|
-- Location: IOIBUF_X38_Y34_N15
|
|
|
|
\Address[0]~input\ : cycloneiii_io_ibuf
|
2024-03-04 17:16:43 +03:00
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
bus_hold => "false",
|
|
|
|
simulate_z_as => "z")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
2024-03-12 16:30:45 +03:00
|
|
|
i => ww_Address(0),
|
|
|
|
o => \Address[0]~input_o\);
|
2024-03-04 17:16:43 +03:00
|
|
|
|
2024-03-12 16:30:45 +03:00
|
|
|
-- Location: IOIBUF_X20_Y34_N1
|
|
|
|
\nOE~input\ : cycloneiii_io_ibuf
|
2024-03-04 17:16:43 +03:00
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
bus_hold => "false",
|
|
|
|
simulate_z_as => "z")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
2024-03-12 16:30:45 +03:00
|
|
|
i => ww_nOE,
|
|
|
|
o => \nOE~input_o\);
|
2024-03-04 17:16:43 +03:00
|
|
|
|
2024-03-12 16:30:45 +03:00
|
|
|
-- Location: IOIBUF_X20_Y34_N8
|
|
|
|
\nWE~input\ : cycloneiii_io_ibuf
|
2024-03-04 17:16:43 +03:00
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
bus_hold => "false",
|
|
|
|
simulate_z_as => "z")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
2024-03-12 16:30:45 +03:00
|
|
|
i => ww_nWE,
|
|
|
|
o => \nWE~input_o\);
|
2024-03-04 17:16:43 +03:00
|
|
|
|
2024-03-12 16:30:45 +03:00
|
|
|
-- Location: IOIBUF_X20_Y34_N15
|
|
|
|
\nCE~input\ : cycloneiii_io_ibuf
|
2024-03-04 17:16:43 +03:00
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
bus_hold => "false",
|
|
|
|
simulate_z_as => "z")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
2024-03-12 16:30:45 +03:00
|
|
|
i => ww_nCE,
|
|
|
|
o => \nCE~input_o\);
|
2024-03-04 17:16:43 +03:00
|
|
|
|
2024-03-12 16:30:45 +03:00
|
|
|
-- Location: IOIBUF_X18_Y34_N1
|
|
|
|
\Data[7]~input\ : cycloneiii_io_ibuf
|
2024-03-04 17:16:43 +03:00
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
bus_hold => "false",
|
|
|
|
simulate_z_as => "z")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
2024-03-12 16:30:45 +03:00
|
|
|
i => Data(7),
|
|
|
|
o => \Data[7]~input_o\);
|
2024-03-04 17:16:43 +03:00
|
|
|
|
2024-03-12 16:30:45 +03:00
|
|
|
-- Location: IOIBUF_X18_Y34_N22
|
|
|
|
\Data[6]~input\ : cycloneiii_io_ibuf
|
2024-03-04 17:16:43 +03:00
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
bus_hold => "false",
|
|
|
|
simulate_z_as => "z")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
2024-03-12 16:30:45 +03:00
|
|
|
i => Data(6),
|
|
|
|
o => \Data[6]~input_o\);
|
2024-03-04 17:16:43 +03:00
|
|
|
|
2024-03-12 16:30:45 +03:00
|
|
|
-- Location: IOIBUF_X16_Y34_N1
|
|
|
|
\Data[5]~input\ : cycloneiii_io_ibuf
|
2024-03-04 17:16:43 +03:00
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
bus_hold => "false",
|
|
|
|
simulate_z_as => "z")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
2024-03-12 16:30:45 +03:00
|
|
|
i => Data(5),
|
|
|
|
o => \Data[5]~input_o\);
|
2024-03-04 17:16:43 +03:00
|
|
|
|
2024-03-12 16:30:45 +03:00
|
|
|
-- Location: IOIBUF_X16_Y34_N15
|
|
|
|
\Data[4]~input\ : cycloneiii_io_ibuf
|
2024-03-04 17:16:43 +03:00
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
bus_hold => "false",
|
|
|
|
simulate_z_as => "z")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
2024-03-12 16:30:45 +03:00
|
|
|
i => Data(4),
|
|
|
|
o => \Data[4]~input_o\);
|
2024-03-04 17:16:43 +03:00
|
|
|
|
2024-03-12 16:30:45 +03:00
|
|
|
-- Location: IOIBUF_X45_Y34_N8
|
|
|
|
\Data[3]~input\ : cycloneiii_io_ibuf
|
2024-03-04 17:16:43 +03:00
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
bus_hold => "false",
|
|
|
|
simulate_z_as => "z")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
2024-03-12 16:30:45 +03:00
|
|
|
i => Data(3),
|
|
|
|
o => \Data[3]~input_o\);
|
2024-03-04 17:16:43 +03:00
|
|
|
|
2024-03-12 16:30:45 +03:00
|
|
|
-- Location: IOIBUF_X45_Y34_N15
|
|
|
|
\Data[2]~input\ : cycloneiii_io_ibuf
|
2024-03-04 17:16:43 +03:00
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
bus_hold => "false",
|
|
|
|
simulate_z_as => "z")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
2024-03-12 16:30:45 +03:00
|
|
|
i => Data(2),
|
|
|
|
o => \Data[2]~input_o\);
|
2024-03-04 17:16:43 +03:00
|
|
|
|
2024-03-12 16:30:45 +03:00
|
|
|
-- Location: IOIBUF_X45_Y34_N22
|
|
|
|
\Data[1]~input\ : cycloneiii_io_ibuf
|
2024-03-04 17:16:43 +03:00
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
bus_hold => "false",
|
|
|
|
simulate_z_as => "z")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
2024-03-12 16:30:45 +03:00
|
|
|
i => Data(1),
|
|
|
|
o => \Data[1]~input_o\);
|
2024-03-04 17:16:43 +03:00
|
|
|
|
2024-03-12 16:30:45 +03:00
|
|
|
-- Location: IOIBUF_X40_Y34_N8
|
|
|
|
\Data[0]~input\ : cycloneiii_io_ibuf
|
2024-03-04 17:16:43 +03:00
|
|
|
-- pragma translate_off
|
|
|
|
GENERIC MAP (
|
|
|
|
bus_hold => "false",
|
|
|
|
simulate_z_as => "z")
|
|
|
|
-- pragma translate_on
|
|
|
|
PORT MAP (
|
2024-03-12 16:30:45 +03:00
|
|
|
i => Data(0),
|
|
|
|
o => \Data[0]~input_o\);
|
|
|
|
|
|
|
|
ww_FPGA_LED_1 <= \FPGA_LED_1~output_o\;
|
|
|
|
|
|
|
|
Data(7) <= \Data[7]~output_o\;
|
|
|
|
|
|
|
|
Data(6) <= \Data[6]~output_o\;
|
|
|
|
|
|
|
|
Data(5) <= \Data[5]~output_o\;
|
|
|
|
|
|
|
|
Data(4) <= \Data[4]~output_o\;
|
|
|
|
|
|
|
|
Data(3) <= \Data[3]~output_o\;
|
|
|
|
|
|
|
|
Data(2) <= \Data[2]~output_o\;
|
|
|
|
|
|
|
|
Data(1) <= \Data[1]~output_o\;
|
|
|
|
|
|
|
|
Data(0) <= \Data[0]~output_o\;
|
2024-03-04 17:16:43 +03:00
|
|
|
END structure;
|
|
|
|
|
|
|
|
|