Stanislav 657d998426 Добавлен модуль контроля входного вектора, который способен писать в DDR память напрямую.

2025-12-04 18:06:44 +03:00

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AckCheckerBlock

Update IP_AXI_ADC in the part of hwp_interrupt

2024-04-13 16:13:27 +03:00

AckCheckerConcept

Added the compatibility another cores

2023-05-03 12:18:32 +03:00

BUS_16IN

Added previous cors

2023-04-27 17:42:38 +03:00

BUS_16OUT

Added previous cors

2023-04-27 17:42:38 +03:00

BusBlock16IN

Added previous cors

2023-04-27 17:42:38 +03:00

BusBlock16OUT

Added previous cors

2023-04-27 17:42:38 +03:00

DifferentialSignal

Added previous cors

2023-04-27 17:42:38 +03:00

EventCapturer64bit/EventCapturer64bit

Добавлен модуль контроля входного вектора, который способен писать в DDR память напрямую.

2025-12-04 18:06:44 +03:00

Inverter_3lvl

Added the first IP core from HDL coder

2023-07-05 15:56:24 +03:00

P0N_3lvl/P0N_3lvl

Added the first IP core from HDL coder

2023-07-05 15:56:24 +03:00