Шаблон проекта с моей расширенной библиотекой MyLibs

.gitignore

@@ -0,0 +1,49 @@
+# ---> uVision
+# git ignore file for Keil µVision Project
+
+# Project User Settings
+*.uvguix.*
+
+# Listing Files
+*.i
+*.lst
+*.m51
+*.m66
+*.map
+
+# Object Files
+*.axf
+*.b[0-2][0-9]
+*.b3[0-1]
+*.bak
+*.build_log.htm
+*.crf
+*.d
+*.dep
+*.elf
+*.htm
+*.iex
+*.lnp
+*.o
+*.obj
+*.sbr
+
+# Firmware Files
+*.bin
+*.h86
+*.hex
+
+# Build Files
+*.bat
+
+# Debugger Files
+*.ini
+*.scvd
+
+# JLink Files
+JLinkLog.txt
+JLinkSettings.ini
+
+# Other Files
+
+/Objects/

.gitmodules

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+[submodule "Core/ExtendedLibs"]
+	path = Core/ExtendedLibs
+	url = https://git.arktika.cyou/Razvalyaev/STM32_ExtendedLibs.git
+	branch = release

Core/App/gpio.c

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+/*==============================================================================
+ * Инициализация портов с использованием бибилотеки PLIB035
+ *------------------------------------------------------------------------------
+ * ЦНИИ СЭТ, Разваляев Алексей <wot890089@mail.ru>
+ *==============================================================================
+ * Конфигурация портов настраивается в gpio.h
+ *                                  ЦНИИ СЭТ
+ *==============================================================================
+ */
+
+//-- Includes ------------------------------------------------------------------
+#include "gpio.h"
+
+//-- Defines -------------------------------------------------------------------
+
+//-- Peripheral init functions -------------------------------------------------
+void gpio_init(void)
+{
+  RCU_AHBClkCmd(RCU_AHBClk_GPIOA, ENABLE);
+  RCU_AHBRstCmd(RCU_AHBRst_GPIOA, ENABLE);
+  
+  /* Сброс пинов */
+  GPIO_DeInit(GPIOA);
+  GPIO_DeInit(GPIOB);
+  
+  // Инициализируем порт A
+  for (int i = 0; i < sizeof(gpioa_config) / sizeof(gpioa_config[0]); i++)
+  {
+      GPIO_Init(GPIOA, &gpioa_config[i]);
+  }
+  
+  // Инициализируем порт B
+  for (int i = 0; i < sizeof(gpiob_config) / sizeof(gpiob_config[0]); i++)
+  {
+      GPIO_Init(GPIOB, &gpiob_config[i]);
+  }
+  
+  
+  
+  
+  
+  
+  
+  
+  
+//  GPIO_StructInit(&gpio_init); 
+//  gpio_init.Digital = ENABLE;  
+//  GPIO_Init(GPIOA, &gpio_init);
+//  GPIO_Init(GPIOB, &gpio_init);
+//
+//  /* Инициализация выходных пинов Пуш-Пулл */
+//  gpio_init.Out = ENABLE;
+//  gpio_init.OutMode = GPIO_OutMode_PP;
+//  
+//  gpio_init.Pin = GPIO_OUT_PP_PA_PINS;
+//  GPIO_Init(GPIOA, &gpio_init);
+//  gpio_init.Pin = GPIO_OUT_PP_PB_PINS;
+//  GPIO_Init(GPIOB, &gpio_init);
+//  
+//  /* Инициализация выходных пинов Открытый сток */
+//  gpio_init.Out = ENABLE;
+//  gpio_init.OutMode = GPIO_OutMode_OD;
+//  
+//  gpio_init.Pin = GPIO_OUT_OD_PA_PINS;
+//  GPIO_Init(GPIOA, &gpio_init);
+//  gpio_init.Pin = GPIO_OUT_OD_PB_PINS;
+//  GPIO_Init(GPIOB, &gpio_init);
+}

Core/App/gpio.h

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+/*==============================================================================
+ * Конфигурация портов с использованием бибилотеки PLIB035
+ *------------------------------------------------------------------------------
+ * ЦНИИ СЭТ, Разваляев Алексей <wot890089@mail.ru>
+ *==============================================================================
+ * Реализация функций инициализации портов находится в gpio.c
+ *                                  ЦНИИ СЭТ
+ *==============================================================================
+ */
+#ifndef __GPIO_H
+#define __GPIO_H
+//-- Includes ------------------------------------------------------------------
+#include "main.h"
+
+//-- Defines -------------------------------------------------------------------
+// Дефайны для режима пина      OutEnable,  AltFuncEnable,  DigitalEnable 
+#define GPIO_PinMode_Unused     DISABLE,    DISABLE,        DISABLE
+#define GPIO_PinMode_Input      DISABLE,    DISABLE,        ENABLE
+#define GPIO_PinMode_Output     ENABLE,     DISABLE,        ENABLE
+#define GPIO_PinMode_AltFunc    DISABLE,    ENABLE,         ENABLE
+//#define GPIO_PinMode_Analog     DISABLE,    DISABLE,        DISABLE
+
+
+
+
+static GPIO_Init_TypeDef gpioa_config[] = {
+  // Пин,         Режим,                Выходной режим,   Входной режим,        Подтяжка,               Нагрузка/Скорость
+  { GPIO_Pin_0,   GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_1,   GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_2,   GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_3,   GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_4,   GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_5,   GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_6,   GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_7,   GPIO_PinMode_Output,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_8,   GPIO_PinMode_Output,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_9,   GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_10,  GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_11,  GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_12,  GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_13,  GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_14,  GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_15,  GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+};
+
+static GPIO_Init_TypeDef gpiob_config[] = {
+  { GPIO_Pin_0,   GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_1,   GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_2,   GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_3,   GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_4,   GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_5,   GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_6,   GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_7,   GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_8,   GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_9,   GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_10,  GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_11,  GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_12,  GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_13,  GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_14,  GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+  { GPIO_Pin_15,  GPIO_PinMode_Unused,  GPIO_OutMode_PP,  GPIO_InMode_Schmitt,  GPIO_PullMode_Disable,  GPIO_DriveMode_HighFast },
+};
+
+
+
+
+
+
+
+
+// Другой вариант
+//#define GPIO_OUT_PP_PA_PINS   /*  GPIO_Pin_0  | */ \
+//                              /*  GPIO_Pin_1  | */ \
+//                              /*  GPIO_Pin_2  | */ \
+//                              /*  GPIO_Pin_3  | */ \
+//                              /*  GPIO_Pin_4  | */ \
+//                              /*  GPIO_Pin_5  | */ \
+//                              /*  GPIO_Pin_6  | */ \
+//                                GPIO_Pin_7  |  \
+//                                GPIO_Pin_8  |  \
+//                              /*  GPIO_Pin_9  | */ \
+//                              /*  GPIO_Pin_10 | */ \
+//                              /*  GPIO_Pin_11 | */ \
+//                              /*  GPIO_Pin_12 | */ \
+//                              /*  GPIO_Pin_13 | */ \
+//                              /*  GPIO_Pin_14 | */ \
+//                              /*  GPIO_Pin_15 | */ \
+//                                  0
+
+//#define GPIO_OUT_PP_PB_PINS   /*  GPIO_Pin_0  | */ \
+//                              /*  GPIO_Pin_1  | */ \
+//                              /*  GPIO_Pin_2  | */ \
+//                              /*  GPIO_Pin_3  | */ \
+//                              /*  GPIO_Pin_4  | */ \
+//                              /*  GPIO_Pin_5  | */ \
+//                              /*  GPIO_Pin_6  | */ \
+//                              /*  GPIO_Pin_7  | */ \
+//                              /*  GPIO_Pin_8  | */ \
+//                              /*  GPIO_Pin_9  | */ \
+//                              /*  GPIO_Pin_10 | */ \
+//                              /*  GPIO_Pin_11 | */ \
+//                              /*  GPIO_Pin_12 | */ \
+//                              /*  GPIO_Pin_13 | */ \
+//                              /*  GPIO_Pin_14 | */ \
+//                              /*  GPIO_Pin_15 | */ \
+//                                  0
+//                              
+//                              
+//#define GPIO_OUT_OD_PA_PINS   /*  GPIO_Pin_0  | */ \
+//                              /*  GPIO_Pin_1  | */ \
+//                              /*  GPIO_Pin_2  | */ \
+//                              /*  GPIO_Pin_3  | */ \
+//                              /*  GPIO_Pin_4  | */ \
+//                              /*  GPIO_Pin_5  | */ \
+//                              /*  GPIO_Pin_6  | */ \
+//                              /*  GPIO_Pin_7  | */ \
+//                              /*  GPIO_Pin_8  | */ \
+//                              /*  GPIO_Pin_9  | */ \
+//                              /*  GPIO_Pin_10 | */ \
+//                              /*  GPIO_Pin_11 | */ \
+//                              /*  GPIO_Pin_12 | */ \
+//                              /*  GPIO_Pin_13 | */ \
+//                              /*  GPIO_Pin_14 | */ \
+//                              /*  GPIO_Pin_15 | */ \
+//                                  0
+//                              
+//#define GPIO_OUT_OD_PB_PINS   /*  GPIO_Pin_0  | */ \
+//                              /*  GPIO_Pin_1  | */ \
+//                              /*  GPIO_Pin_2  | */ \
+//                              /*  GPIO_Pin_3  | */ \
+//                              /*  GPIO_Pin_4  | */ \
+//                              /*  GPIO_Pin_5  | */ \
+//                              /*  GPIO_Pin_6  | */ \
+//                              /*  GPIO_Pin_7  | */ \
+//                              /*  GPIO_Pin_8  | */ \
+//                              /*  GPIO_Pin_9  | */ \
+//                              /*  GPIO_Pin_10 | */ \
+//                              /*  GPIO_Pin_11 | */ \
+//                              /*  GPIO_Pin_12 | */ \
+//                              /*  GPIO_Pin_13 | */ \
+//                              /*  GPIO_Pin_14 | */ \
+//                              /*  GPIO_Pin_15 | */ \
+//                                  0
+
+//-- Exported functions prototypes ---------------------------------------------
+void gpio_init(void);
+
+#endif /*__GPIO_H*/

Core/App/main.c

@@ -0,0 +1,68 @@
+/*==============================================================================
+ * Шаблон проекта для К1921ВК035 с использованием бибилотеки PLIB035
+ *------------------------------------------------------------------------------
+ * НИИЭТ, Богдан Колбов <kolbov@niiet.ru>
+ *==============================================================================
+ * ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ ПРЕДОСТАВЛЯЕТСЯ «КАК ЕСТЬ», БЕЗ КАКИХ-ЛИБО
+ * ГАРАНТИЙ, ЯВНО ВЫРАЖЕННЫХ ИЛИ ПОДРАЗУМЕВАЕМЫХ, ВКЛЮЧАЯ ГАРАНТИИ ТОВАРНОЙ
+ * ПРИГОДНОСТИ, СООТВЕТСТВИЯ ПО ЕГО КОНКРЕТНОМУ НАЗНАЧЕНИЮ И ОТСУТСТВИЯ
+ * НАРУШЕНИЙ, НО НЕ ОГРАНИЧИВАЯСЬ ИМИ. ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ
+ * ПРЕДНАЗНАЧЕНО ДЛЯ ОЗНАКОМИТЕЛЬНЫХ ЦЕЛЕЙ И НАПРАВЛЕНО ТОЛЬКО НА
+ * ПРЕДОСТАВЛЕНИЕ ДОПОЛНИТЕЛЬНОЙ ИНФОРМАЦИИ О ПРОДУКТЕ, С ЦЕЛЬЮ СОХРАНИТЬ ВРЕМЯ
+ * ПОТРЕБИТЕЛЮ. НИ В КАКОМ СЛУЧАЕ АВТОРЫ ИЛИ ПРАВООБЛАДАТЕЛИ НЕ НЕСУТ
+ * ОТВЕТСТВЕННОСТИ ПО КАКИМ-ЛИБО ИСКАМ, ЗА ПРЯМОЙ ИЛИ КОСВЕННЫЙ УЩЕРБ, ИЛИ
+ * ПО ИНЫМ ТРЕБОВАНИЯМ, ВОЗНИКШИМ ИЗ-ЗА ИСПОЛЬЗОВАНИЯ ПРОГРАММНОГО ОБЕСПЕЧЕНИЯ
+ * ИЛИ ИНЫХ ДЕЙСТВИЙ С ПРОГРАММНЫМ ОБЕСПЕЧЕНИЕМ.
+ *
+ *                              2018 АО "НИИЭТ"
+ *==============================================================================
+ */
+
+//-- Includes ------------------------------------------------------------------
+#include "main.h"
+#include "rcu.h"
+#include "gpio.h"
+
+//-- Defines -------------------------------------------------------------------
+
+//-- Peripheral init functions -------------------------------------------------
+void periph_init()
+{
+  SystemCoreClockUpdate();
+  sysclk_init();
+  gpio_init();
+  retarget_init();
+  printf("\nAll peripherals inited, SYSCLK = %3d MHz\n", (int)(SystemCoreClock / 1E6));
+}
+
+//-- Main ----------------------------------------------------------------------
+int main()
+{
+  periph_init();
+  
+  while (1) {
+    
+  };
+  //return 0;
+}
+
+
+
+
+//-- Assert --------------------------------------------------------------------
+void Error_Handler(void)
+{
+  __disable_irq();
+  while (1)
+  {
+  }
+}
+
+#if defined USE_FULL_ASSERT
+void assert_failed(uint8_t* file, uint32_t line)
+{
+  printf("Assert failed: file %s on line %d\n", file, (int)line);
+  while (1) {
+  };
+}
+#endif /* USE_FULL_ASSERT */

Core/App/main.h

@@ -0,0 +1,35 @@
+/*==============================================================================
+ * Шаблон проекта для К1921ВК035 с использованием бибилотеки PLIB035
+ *------------------------------------------------------------------------------
+ * НИИЭТ, Богдан Колбов <kolbov@niiet.ru>
+ *==============================================================================
+ * ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ ПРЕДОСТАВЛЯЕТСЯ «КАК ЕСТЬ», БЕЗ КАКИХ-ЛИБО
+ * ГАРАНТИЙ, ЯВНО ВЫРАЖЕННЫХ ИЛИ ПОДРАЗУМЕВАЕМЫХ, ВКЛЮЧАЯ ГАРАНТИИ ТОВАРНОЙ
+ * ПРИГОДНОСТИ, СООТВЕТСТВИЯ ПО ЕГО КОНКРЕТНОМУ НАЗНАЧЕНИЮ И ОТСУТСТВИЯ
+ * НАРУШЕНИЙ, НО НЕ ОГРАНИЧИВАЯСЬ ИМИ. ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ
+ * ПРЕДНАЗНАЧЕНО ДЛЯ ОЗНАКОМИТЕЛЬНЫХ ЦЕЛЕЙ И НАПРАВЛЕНО ТОЛЬКО НА
+ * ПРЕДОСТАВЛЕНИЕ ДОПОЛНИТЕЛЬНОЙ ИНФОРМАЦИИ О ПРОДУКТЕ, С ЦЕЛЬЮ СОХРАНИТЬ ВРЕМЯ
+ * ПОТРЕБИТЕЛЮ. НИ В КАКОМ СЛУЧАЕ АВТОРЫ ИЛИ ПРАВООБЛАДАТЕЛИ НЕ НЕСУТ
+ * ОТВЕТСТВЕННОСТИ ПО КАКИМ-ЛИБО ИСКАМ, ЗА ПРЯМОЙ ИЛИ КОСВЕННЫЙ УЩЕРБ, ИЛИ
+ * ПО ИНЫМ ТРЕБОВАНИЯМ, ВОЗНИКШИМ ИЗ-ЗА ИСПОЛЬЗОВАНИЯ ПРОГРАММНОГО ОБЕСПЕЧЕНИЯ
+ * ИЛИ ИНЫХ ДЕЙСТВИЙ С ПРОГРАММНЫМ ОБЕСПЕЧЕНИЕМ.
+ *
+ *                              2018 АО "НИИЭТ"
+ *==============================================================================
+ */
+#ifndef __MAIN_H
+#define __MAIN_H
+
+//-- Includes ------------------------------------------------------------------
+#include "plib035.h"
+#include "retarget_conf.h"
+#include "mylibs_include.h"
+
+//-- Defines -------------------------------------------------------------------
+
+//-- Exported variables --------------------------------------------------------
+
+//-- Exported functions prototypes ---------------------------------------------
+void Error_Handler(void);
+
+#endif /* __MAIN_H */

Core/App/rcu.c

@@ -0,0 +1,31 @@
+/*==============================================================================
+ * Инициализация тактирования с использованием бибилотеки PLIB035
+ *------------------------------------------------------------------------------
+ * ЦНИИ СЭТ, Разваляев Алексей <wot890089@mail.ru>
+ *==============================================================================
+ *                                  ЦНИИ СЭТ
+ *==============================================================================
+ */
+
+//-- Includes ------------------------------------------------------------------
+#include "rcu.h"
+
+//-- Defines -------------------------------------------------------------------
+
+//-- Peripheral init functions -------------------------------------------------
+void sysclk_init(void)
+{
+  OperationStatus status;
+  status = RCU_PLL_AutoConfig(MCU_CLOCK_MHZ*__MHZ, OS_Type);
+  if (status == ERROR)
+  {
+    Error_Handler();
+  }
+  SystemCoreClockUpdate();
+  RCU_ClkOutConfig(RCU_SysPeriphClk_PLLClk, 1, ENABLE);
+  RCU_ClkOutCmd(ENABLE);
+      
+  /*  Прерывание должно быть каждую миллисекунду:
+      Для тактирования N Гц это каждый N / 1000 тик */
+  SysTick_Config(MCU_CLOCK_MHZ*__MHZ/1000);
+}

Core/App/rcu.h

@@ -0,0 +1,22 @@
+/*==============================================================================
+ * Инициализация тактирования с использованием бибилотеки PLIB035
+ *------------------------------------------------------------------------------
+ * ЦНИИ СЭТ, Разваляев Алексей <wot890089@mail.ru>
+ *==============================================================================
+ *                                  ЦНИИ СЭТ
+ *==============================================================================
+ */
+#ifndef __RCU_H
+#define __RCU_H
+//-- Includes ------------------------------------------------------------------
+#include "main.h"
+
+//-- Defines -------------------------------------------------------------------
+static RCU_PLL_Ref_TypeDef OS_Type = RCU_PLL_Ref_OSEClk;
+#define MCU_CLOCK_MHZ 100
+#define __MHZ 1000000
+
+//-- Exported functions prototypes ---------------------------------------------
+void sysclk_init(void);
+
+#endif /*__RCU_H*/

Core/App/vk035_it.c

@@ -0,0 +1,106 @@
+/*==============================================================================
+ * Прерывания микроконтроллера 1921ВК035
+ *------------------------------------------------------------------------------
+ * ЦНИИ СЭТ, Разваляев Алексей <wot890089@mail.ru>
+ *==============================================================================
+ *                                  ЦНИИ СЭТ
+ *==============================================================================
+ */
+
+//-- Includes ------------------------------------------------------------------
+#include "main.h"
+#include "plib035.h"
+#include "retarget_conf.h"
+
+
+/******************************************************************************/
+/* STM32G4xx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32g4xx.s).                    */
+/******************************************************************************/
+
+
+
+
+/******************************************************************************/
+/*           Cortex-M4 Processor Interruption and Exception Handlers          */
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  uwTick++;
+}

Core/Config/SEGGER_RTT_Conf.h

@@ -0,0 +1,429 @@
+/*********************************************************************
+*                    SEGGER Microcontroller GmbH                     *
+*                        The Embedded Experts                        *
+**********************************************************************
+*                                                                    *
+*            (c) 1995 - 2021 SEGGER Microcontroller GmbH             *
+*                                                                    *
+*       www.segger.com     Support: support@segger.com               *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+*       SEGGER RTT * Real Time Transfer for embedded targets         *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+* All rights reserved.                                               *
+*                                                                    *
+* SEGGER strongly recommends to not make any changes                 *
+* to or modify the source code of this software in order to stay     *
+* compatible with the RTT protocol and J-Link.                       *
+*                                                                    *
+* Redistribution and use in source and binary forms, with or         *
+* without modification, are permitted provided that the following    *
+* condition is met:                                                  *
+*                                                                    *
+* o Redistributions of source code must retain the above copyright   *
+*   notice, this condition and the following disclaimer.             *
+*                                                                    *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
+* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
+* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
+* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
+* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
+* DAMAGE.                                                            *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+*       RTT version: 8.10g                                           *
+*                                                                    *
+**********************************************************************
+
+---------------------------END-OF-HEADER------------------------------
+File    : SEGGER_RTT_Conf.h
+Purpose : Implementation of SEGGER real-time transfer (RTT) which
+          allows real-time communication on targets which support
+          debugger memory accesses while the CPU is running.
+Revision: $Rev: 24316 $
+
+*/
+
+#ifndef SEGGER_RTT_CONF_H
+#define SEGGER_RTT_CONF_H
+
+#ifdef __IAR_SYSTEMS_ICC__
+  #include <intrinsics.h>
+#endif
+
+/*********************************************************************
+*
+*       Defines, configurable
+*
+**********************************************************************
+*/
+
+//
+// Take in and set to correct values for Cortex-A systems with CPU cache
+//
+//#define SEGGER_RTT_CPU_CACHE_LINE_SIZE            (32)          // Largest cache line size (in bytes) in the current system
+//#define SEGGER_RTT_UNCACHED_OFF                   (0xFB000000)  // Address alias where RTT CB and buffers can be accessed uncached
+//
+// Most common case:
+// Up-channel 0: RTT
+// Up-channel 1: SystemView
+//
+#ifndef   SEGGER_RTT_MAX_NUM_UP_BUFFERS
+  #define SEGGER_RTT_MAX_NUM_UP_BUFFERS             (3)     // Max. number of up-buffers (T->H) available on this target    (Default: 3)
+#endif
+//
+// Most common case:
+// Down-channel 0: RTT
+// Down-channel 1: SystemView
+//
+#ifndef   SEGGER_RTT_MAX_NUM_DOWN_BUFFERS
+  #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS           (3)     // Max. number of down-buffers (H->T) available on this target  (Default: 3)
+#endif
+
+#ifndef   BUFFER_SIZE_UP
+  #define BUFFER_SIZE_UP                            (4096)  // Size of the buffer for terminal output of target, up to host (Default: 1k)
+#endif
+
+#ifndef   BUFFER_SIZE_DOWN
+  #define BUFFER_SIZE_DOWN                          (16)    // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16)
+#endif
+
+#ifndef   SEGGER_RTT_PRINTF_BUFFER_SIZE
+  #define SEGGER_RTT_PRINTF_BUFFER_SIZE             (64u)    // Size of buffer for RTT printf to bulk-send chars via RTT     (Default: 64)
+#endif
+
+#ifndef   SEGGER_RTT_MODE_DEFAULT
+  #define SEGGER_RTT_MODE_DEFAULT                   SEGGER_RTT_MODE_NO_BLOCK_TRIM // Mode for pre-initialized terminal channel (buffer 0)
+#endif
+
+/*********************************************************************
+*
+*       RTT memcpy configuration
+*
+*       memcpy() is good for large amounts of data,
+*       but the overhead is big for small amounts, which are usually stored via RTT.
+*       With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead.
+*
+*       SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions.
+*       This is may be required with memory access restrictions,
+*       such as on Cortex-A devices with MMU.
+*/
+#ifndef   SEGGER_RTT_MEMCPY_USE_BYTELOOP
+  #define SEGGER_RTT_MEMCPY_USE_BYTELOOP              0 // 0: Use memcpy/SEGGER_RTT_MEMCPY, 1: Use a simple byte-loop
+#endif
+//
+// Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets
+//
+//#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__))
+//  #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes)      SEGGER_memcpy((pDest), (pSrc), (NumBytes))
+//#endif
+
+//
+// Target is not allowed to perform other RTT operations while string still has not been stored completely.
+// Otherwise we would probably end up with a mixed string in the buffer.
+// If using  RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here.
+//
+// SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4.
+// Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches.
+// When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly.
+// (Higher priority = lower priority number)
+// Default value for embOS: 128u
+// Default configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+// In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are implemented in NVIC
+// or define SEGGER_RTT_LOCK() to completely disable interrupts.
+//
+#ifndef   SEGGER_RTT_MAX_INTERRUPT_PRIORITY
+  #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY         (0x20)   // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20)
+#endif
+
+/*********************************************************************
+*
+*       RTT lock configuration for SEGGER Embedded Studio,
+*       Rowley CrossStudio and GCC
+*/
+#if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || defined(__clang__)) && !defined (__CC_ARM) && !defined(WIN32))
+  #if (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__))
+    #define SEGGER_RTT_LOCK()   {                                                                   \
+                                    unsigned int _SEGGER_RTT__LockState;                                         \
+                                  __asm volatile ("mrs   %0, primask  \n\t"                         \
+                                                  "movs  r1, #1       \n\t"                         \
+                                                  "msr   primask, r1  \n\t"                         \
+                                                  : "=r" (_SEGGER_RTT__LockState)                                \
+                                                  :                                                 \
+                                                  : "r1", "cc"                                      \
+                                                  );
+
+    #define SEGGER_RTT_UNLOCK()   __asm volatile ("msr   primask, %0  \n\t"                         \
+                                                  :                                                 \
+                                                  : "r" (_SEGGER_RTT__LockState)                                 \
+                                                  :                                                 \
+                                                  );                                                \
+                                }
+  #elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__))
+    #ifndef   SEGGER_RTT_MAX_INTERRUPT_PRIORITY
+      #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY   (0x20)
+    #endif
+    #define SEGGER_RTT_LOCK()   {                                                                   \
+                                    unsigned int _SEGGER_RTT__LockState;                                         \
+                                  __asm volatile ("mrs   %0, basepri  \n\t"                         \
+                                                  "mov   r1, %1       \n\t"                         \
+                                                  "msr   basepri, r1  \n\t"                         \
+                                                  : "=r" (_SEGGER_RTT__LockState)                                \
+                                                  : "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY)          \
+                                                  : "r1", "cc"                                      \
+                                                  );
+
+    #define SEGGER_RTT_UNLOCK()   __asm volatile ("msr   basepri, %0  \n\t"                         \
+                                                  :                                                 \
+                                                  : "r" (_SEGGER_RTT__LockState)                                 \
+                                                  :                                                 \
+                                                  );                                                \
+                                }
+
+  #elif (defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7R__))
+    #define SEGGER_RTT_LOCK() {                                                \
+                                 unsigned int _SEGGER_RTT__LockState;                       \
+                                 __asm volatile ("mrs r1, CPSR \n\t"           \
+                                                 "mov %0, r1 \n\t"             \
+                                                 "orr r1, r1, #0xC0 \n\t"      \
+                                                 "msr CPSR_c, r1 \n\t"         \
+                                                 : "=r" (_SEGGER_RTT__LockState)            \
+                                                 :                             \
+                                                 : "r1", "cc"                  \
+                                                 );
+
+    #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t"              \
+                                                "mrs r1, CPSR \n\t"            \
+                                                "bic r1, r1, #0xC0 \n\t"       \
+                                                "and r0, r0, #0xC0 \n\t"       \
+                                                "orr r1, r1, r0 \n\t"          \
+                                                "msr CPSR_c, r1 \n\t"          \
+                                                :                              \
+                                                : "r" (_SEGGER_RTT__LockState)              \
+                                                : "r0", "r1", "cc"             \
+                                                );                             \
+                            }
+  #elif defined(__riscv) || defined(__riscv_xlen)
+    #define SEGGER_RTT_LOCK()  {                                               \
+                                 unsigned int _SEGGER_RTT__LockState;                       \
+                                 __asm volatile ("csrr  %0, mstatus  \n\t"     \
+                                                 "csrci mstatus, 8   \n\t"     \
+                                                 "andi  %0, %0,  8   \n\t"     \
+                                                 : "=r" (_SEGGER_RTT__LockState)            \
+                                                 :                             \
+                                                 :                             \
+                                                );
+
+  #define SEGGER_RTT_UNLOCK()    __asm volatile ("csrr  a1, mstatus  \n\t"     \
+                                                 "or    %0, %0, a1   \n\t"     \
+                                                 "csrs  mstatus, %0  \n\t"     \
+                                                 :                             \
+                                                 : "r"  (_SEGGER_RTT__LockState)            \
+                                                 : "a1"                        \
+                                                );                             \
+                               }
+  #else
+    #define SEGGER_RTT_LOCK()
+    #define SEGGER_RTT_UNLOCK()
+  #endif
+#endif
+
+/*********************************************************************
+*
+*       RTT lock configuration for IAR EWARM
+*/
+#ifdef __ICCARM__
+  #if (defined (__ARM6M__)          && (__CORE__ == __ARM6M__))             ||                      \
+      (defined (__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__))
+    #define SEGGER_RTT_LOCK()   {                                                                   \
+                                  unsigned int _SEGGER_RTT__LockState;                                           \
+                                  _SEGGER_RTT__LockState = __get_PRIMASK();                                      \
+                                  __set_PRIMASK(1);
+
+    #define SEGGER_RTT_UNLOCK()   __set_PRIMASK(_SEGGER_RTT__LockState);                                         \
+                                }
+  #elif (defined (__ARM7EM__)         && (__CORE__ == __ARM7EM__))          ||                      \
+        (defined (__ARM7M__)          && (__CORE__ == __ARM7M__))           ||                      \
+        (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__))  ||                      \
+        (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__))
+    #ifndef   SEGGER_RTT_MAX_INTERRUPT_PRIORITY
+      #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY   (0x20)
+    #endif
+    #define SEGGER_RTT_LOCK()   {                                                                   \
+                                  unsigned int _SEGGER_RTT__LockState;                                           \
+                                  _SEGGER_RTT__LockState = __get_BASEPRI();                                      \
+                                  __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY);
+
+    #define SEGGER_RTT_UNLOCK()   __set_BASEPRI(_SEGGER_RTT__LockState);                                         \
+                                }
+  #elif (defined (__ARM7A__) && (__CORE__ == __ARM7A__))                    ||                      \
+        (defined (__ARM7R__) && (__CORE__ == __ARM7R__))
+    #define SEGGER_RTT_LOCK() {                                                                     \
+                                 unsigned int _SEGGER_RTT__LockState;                                            \
+                                 __asm volatile ("mrs r1, CPSR \n\t"                                \
+                                                 "mov %0, r1 \n\t"                                  \
+                                                 "orr r1, r1, #0xC0 \n\t"                           \
+                                                 "msr CPSR_c, r1 \n\t"                              \
+                                                 : "=r" (_SEGGER_RTT__LockState)                                 \
+                                                 :                                                  \
+                                                 : "r1", "cc"                                       \
+                                                 );
+
+    #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t"                                   \
+                                                "mrs r1, CPSR \n\t"                                 \
+                                                "bic r1, r1, #0xC0 \n\t"                            \
+                                                "and r0, r0, #0xC0 \n\t"                            \
+                                                "orr r1, r1, r0 \n\t"                               \
+                                                "msr CPSR_c, r1 \n\t"                               \
+                                                :                                                   \
+                                                : "r" (_SEGGER_RTT__LockState)                                   \
+                                                : "r0", "r1", "cc"                                  \
+                                                );                                                  \
+                            }
+  #endif
+#endif
+
+/*********************************************************************
+*
+*       RTT lock configuration for IAR RX
+*/
+#ifdef __ICCRX__
+  #define SEGGER_RTT_LOCK()   {                                                                     \
+                                unsigned long _SEGGER_RTT__LockState;                                            \
+                                _SEGGER_RTT__LockState = __get_interrupt_state();                                \
+                                __disable_interrupt();
+
+  #define SEGGER_RTT_UNLOCK()   __set_interrupt_state(_SEGGER_RTT__LockState);                                   \
+                              }
+#endif
+
+/*********************************************************************
+*
+*       RTT lock configuration for IAR RL78
+*/
+#ifdef __ICCRL78__
+  #define SEGGER_RTT_LOCK()   {                                                                     \
+                                __istate_t _SEGGER_RTT__LockState;                                               \
+                                _SEGGER_RTT__LockState = __get_interrupt_state();                                \
+                                __disable_interrupt();
+
+  #define SEGGER_RTT_UNLOCK()   __set_interrupt_state(_SEGGER_RTT__LockState);                                   \
+                              }
+#endif
+
+/*********************************************************************
+*
+*       RTT lock configuration for KEIL ARM
+*/
+#ifdef __CC_ARM
+  #if (defined __TARGET_ARCH_6S_M)
+    #define SEGGER_RTT_LOCK()   {                                                                   \
+                                  unsigned int _SEGGER_RTT__LockState;                                           \
+                                  register unsigned char _SEGGER_RTT__PRIMASK __asm( "primask");                 \
+                                  _SEGGER_RTT__LockState = _SEGGER_RTT__PRIMASK;                                              \
+                                  _SEGGER_RTT__PRIMASK = 1u;                                                     \
+                                  __schedule_barrier();
+
+    #define SEGGER_RTT_UNLOCK()   _SEGGER_RTT__PRIMASK = _SEGGER_RTT__LockState;                                              \
+                                  __schedule_barrier();                                             \
+                                }
+  #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M))
+    #ifndef   SEGGER_RTT_MAX_INTERRUPT_PRIORITY
+      #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY   (0x20)
+    #endif
+    #define SEGGER_RTT_LOCK()   {                                                                   \
+                                  unsigned int _SEGGER_RTT__LockState;                                           \
+                                  register unsigned char BASEPRI __asm( "basepri");                 \
+                                  _SEGGER_RTT__LockState = BASEPRI;                                              \
+                                  BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY;                      \
+                                  __schedule_barrier();
+
+    #define SEGGER_RTT_UNLOCK()   BASEPRI = _SEGGER_RTT__LockState;                                              \
+                                  __schedule_barrier();                                             \
+                                }
+  #endif
+#endif
+
+/*********************************************************************
+*
+*       RTT lock configuration for TI ARM
+*/
+#ifdef __TI_ARM__
+  #if defined (__TI_ARM_V6M0__)
+    #define SEGGER_RTT_LOCK()   {                                                                   \
+                                  unsigned int _SEGGER_RTT__LockState;                                           \
+                                  _SEGGER_RTT__LockState = __get_PRIMASK();                                      \
+                                  __set_PRIMASK(1);
+
+    #define SEGGER_RTT_UNLOCK()   __set_PRIMASK(_SEGGER_RTT__LockState);                                         \
+                                }
+  #elif (defined (__TI_ARM_V7M3__) || defined (__TI_ARM_V7M4__))
+    #ifndef   SEGGER_RTT_MAX_INTERRUPT_PRIORITY
+      #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY   (0x20)
+    #endif
+    #define SEGGER_RTT_LOCK()   {                                                                   \
+                                  unsigned int _SEGGER_RTT__LockState;                                           \
+                                  _SEGGER_RTT__LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY);
+
+    #define SEGGER_RTT_UNLOCK()   _set_interrupt_priority(_SEGGER_RTT__LockState);                               \
+                                }
+  #endif
+#endif
+
+/*********************************************************************
+*
+*       RTT lock configuration for CCRX
+*/
+#ifdef __RX
+  #include <machine.h>
+  #define SEGGER_RTT_LOCK()   {                                                                     \
+                                unsigned long _SEGGER_RTT__LockState;                                            \
+                                _SEGGER_RTT__LockState = get_psw() & 0x010000;                                   \
+                                clrpsw_i();
+
+  #define SEGGER_RTT_UNLOCK()   set_psw(get_psw() | _SEGGER_RTT__LockState);                                     \
+                              }
+#endif
+
+/*********************************************************************
+*
+*       RTT lock configuration for embOS Simulation on Windows
+*       (Can also be used for generic RTT locking with embOS)
+*/
+#if defined(WIN32) || defined(SEGGER_RTT_LOCK_EMBOS)
+
+void OS_SIM_EnterCriticalSection(void);
+void OS_SIM_LeaveCriticalSection(void);
+
+#define SEGGER_RTT_LOCK()       {                                                                   \
+                                  OS_SIM_EnterCriticalSection();
+
+#define SEGGER_RTT_UNLOCK()       OS_SIM_LeaveCriticalSection();                                    \
+                                }
+#endif
+
+/*********************************************************************
+*
+*       RTT lock configuration fallback
+*/
+#ifndef   SEGGER_RTT_LOCK
+  #define SEGGER_RTT_LOCK()                // Lock RTT (nestable)   (i.e. disable interrupts)
+#endif
+
+#ifndef   SEGGER_RTT_UNLOCK
+  #define SEGGER_RTT_UNLOCK()              // Unlock RTT (nestable) (i.e. enable previous interrupt lock state)
+#endif
+
+#endif
+/*************************** End of file ****************************/

Core/Config/mylibs_config.h

@@ -0,0 +1,132 @@
+/** 
+**************************************************************************
+* @file mylibs_config.h
+* @brief Конфигурации для библиотек MyLibs
+**************************************************************************
+* @defgroup MYLIBS_CONFIG   Configs
+* @ingroup  MYLIBS_ALL
+* @brief    Конфигурации для библиотек MyLibs
+* @{
+*************************************************************************/
+#ifndef __MYLIBS_CONFIG_H_
+#define __MYLIBS_CONFIG_H_
+#include "plib035.h"
+#include "retarget_conf.h"
+
+// user includes
+
+/** 
+  * @addtogroup TRACE_CONFIG   Trace configs
+  * @ingroup    MYLIBS_CONFIG
+  * @brief      Конфигурация трекеров и трассировки
+  * @{
+  */
+
+#define TRACKERS_ENABLE           ///< Включить трекеры
+#define SERIAL_TRACE_ENABLE       ///< Включить serial трассировку
+#define RTT_TRACE_ENABLE          ///< Включить serial трассировку через RTT
+#define SWO_TRACE_ENABLE          ///< Включить serial трассировку через SWO
+/**
+  * @brief Уровень log serial трассировки @ref log_printf
+  *  - LOG_LEVEL == 0 - логирование отключено (макрос пустой)
+  *  - LOG_LEVEL == 1 - выводится время и TAG
+  *  - LOG_LEVEL >= 2 - выводится время, TAG, имя файла и номер строки
+  */
+#define LOG_LEVEL 1
+
+#define RTT_FLASH_BUFFER_SIZE   1024                    ///< Размер буфера RTT в Flash
+#define RTT_FLASH_SECTOR        FLASH_SECTOR_11         ///< Сектор FLASH куда положится RTT буфер
+#define RTT_FLASH_SECTOR_START  0x080E0000              ///< Начало сектора RTT_FLASH_SECTOR
+#define RTT_FLASH_SECTOR_END    0x080FFFFF              ///< Конец сектора RTT_FLASH_SECTOR
+
+
+#define HARDFAULT_SERIAL_TRACE  ///< Включить обработку и serial трассировку Hardfault
+#define HF_RTT_TAG_BASE         0xDEAD0000              ///< базовый тег для HardFault
+#define HF_RTT_TAIL_SIZE        RTT_FLASH_BUFFER_SIZE   ///< Размер буфера RTT, который сохранится при Hardfault
+#define HF_STACK_DUMP_WORDS     32                      ///< Сколько слов стека будет проанализировано во время Hardfault
+#define HF_FLASH_ADDR           ((uint32_t)0x080FF000)  ///< Адрес FLASH куда положится RTT буфер
+#define HF_RAM_END              0x20030000              ///< Конец RAM памяти (чтобы во время анализа стека не выйти за пределы)
+
+#define GPIO_TRACE_ENABLE         ///< Включить GPIO трассировку
+
+/** TRACE_CONFIG
+  * @}
+  */
+
+
+/** 
+  * @addtogroup FILTER_CONFIG   Filter configs
+  * @ingroup    MYLIBS_CONFIG
+  * @brief      Конфигурация фильтров
+  * @{
+  */
+
+
+#define FILTERS_ENABLE              ///<  Включить библиотеку фильтров
+//#define FILTER_MEDIAN_MAX_SIZE      ///< Максимальный размер окна медианного фильтра (по умолчанию 5)
+//#define FILTER_AVERAGE_MAX_SIZE     ///< Максимальный размер окна усредняющего фильтра (по умолчанию 8)
+//#define FILTER_POLY_MAX_ORDER       ///< Максимальный порядок полинома (по умолчанию 4)
+#define FILTERS_DISABLE_MOVING_AVERAGE
+/** GEN_CONFIG
+  * @}
+  */
+  
+  
+/** 
+  * @addtogroup GEN_CONFIG   Genetic configs
+  * @ingroup    MYLIBS_CONFIG
+  * @brief      Конфигурация генетического алгоритма обучения
+  * @{
+  */
+
+#define GEN_OPTIMIZATION_ENABLE       ///< Включить оптимизацию параметров
+#define GEN_MAX_PARAMS       20       ///< Максимальное количество параметров
+#define GEN_MAX_CANDIDATES   100      ///< Максимальное количество кандидатов для обучения
+
+/** GEN_CONFIG
+  * @}
+  */
+
+
+/** 
+  * @addtogroup GEN_CONFIG   Genetic configs
+  * @ingroup    MYLIBS_CONFIG
+  * @brief      Конфигурация генетического алгоритма обучения
+  * @{
+  */
+
+
+#define BENCH_TIME_ENABLE             ///< Включить бенч времени
+#define BENCH_TIME_MAX_CHANNELS 16    ///< Максимальное количество каналов измерения
+
+/** GEN_CONFIG
+  * @}
+  */
+
+
+
+/** 
+  * @addtogroup LIBS_CONFIG   Libraries configs
+  * @ingroup    MYLIBS_CONFIG
+  * @brief      Подключение различных модулей библиотеки
+  * @{
+  */
+extern uint32_t uwTick;
+#define local_time()      (uwTick)      ///< Локальное время
+
+#define INCLUDE_FILTERS               ///< Подключить библиотеку с фильтрами
+#define INCLUDE_GEN_OPTIMIZER      ///< Подключить библиотеку для оптимизации параметров
+#define INCLUDE_BIT_ACCESS_LIB        ///< Подключить библиотеку с typedef с битовыми полями
+#define INCLUDE_TRACKERS_LIB          ///< Подключить библиотеку с трекерами
+#define INCLUDE_TRACE_LIB             ///< Подключить библиотеку с трейсами
+#define INCLUDE_BENCH_TIME            ///< Подключить библиотеку с бенчмарком времени
+//#define FREERTOS_DELAY                ///< Использовать FreeRTOS задержку, вместо HAL
+
+/** LIBS_CONFIG
+  * @}
+  */
+
+/** MYLIBS_CONFIG
+  * @}
+  */
+#endif //__MYLIBS_CONFIG_H_

Core/Config/mylibs_include.h

@@ -0,0 +1,141 @@
+/** 
+**************************************************************************
+* @file mylibs_include.h
+* @brief Заголочный файл для всех библиотек
+**************************************************************************
+* @details
+Здесь нужно собрать библиотеки и дефайны, которые должны быть видны во всем проекте,
+чтобы не подключать 100 инклюдов в каждом ".c" файле
+**************************************************************************
+* @defgroup MYLIBS_ALL      My Libs
+* @brief    Все используемые MyLibs библиотеки
+* @details
+Для подключения библиотеки необходимо:
+- Сконфигурировать mylibs_config.h:
+  - Подключить заголовочный файл HAL библиотеки конкретного МК (напр. stm32f4xx_hal.h)
+  - Подключить другие заголовочные файлы которые общие для всего проекта и должны быть видны
+  - Подключить mylibs_include.h туда, где необходим доступ к библиотекам.
+
+*************************************************************************/
+#ifndef __MYLIBS_INCLUDE_H_
+#define __MYLIBS_INCLUDE_H_
+
+#include "mylibs_defs.h"
+
+
+#ifdef ARM_MATH_CM4
+  #include "arm_math.h"
+#else
+  #include "math.h"
+#endif
+
+
+#ifdef INCLUDE_BIT_ACCESS_LIB
+#include "bit_access.h"
+#endif
+
+#ifdef INCLUDE_TRACKERS_LIB
+#include "trackers.h"
+#else
+  #define TrackerTypeDef(num_user_vars) void *
+  #define num_of_usercnts(_user_)                               0
+  #define assert_tracecnt(_cntstruct_, _uservarnumb_)           0
+  #define if_assert_usertracker(_cntstruct_, _uservarnumb_)     if(0)
+  #define tern_assert_usertracker(_cntstruct_, _uservarnumb_)   0
+  #define TrackerGet_Ok(_cntstruct_)                            dummy
+  #define TrackerGet_Err(_cntstruct_)                           dummy
+  #define TrackerGet_Warn(_cntstruct_)                          dummy 
+  #define TrackerGet_User(_cntstruct_, _uservarnumb_)           dummy
+  #define TrackerCnt_Ok(_cntstruct_)                              
+  #define TrackerCnt_Err(_cntstruct_)                             
+  #define TrackerCnt_Warn(_cntstruct_)                            
+  #define TrackerCnt_User(_cntstruct_, _uservarnumb_)                 
+  #define TrackerWrite_User(_cntstruct_, _uservarnumb_, _val_)
+  #define TrackerClear_All(_cntstruct_)                        
+  #define TrackerClear_Ok(_cntstruct_)                         
+  #define TrackerClear_Err(_cntstruct_)                        
+  #define TrackerClear_Warn(_cntstruct_)                       
+  #define TrackerClear_User(_cntstruct_)                       
+  #define TrackerClear_UserAll(_cntstruct_)   
+#endif
+
+#ifdef INCLUDE_TRACE_LIB
+#include "trace.h"
+#else
+#define my_printf(...)
+#define log_printf(TAG, fmt, ...)  
+#define TRACE_GPIO_SET(_gpio_,_pin_)
+#define TRACE_GPIO_RESET(_gpio_,_pin_)
+#define RTT_FlashPrepare(...)
+#define RTT_EraseFlash(...)    0
+#define RTT_SaveToFlash(...)   0
+#define RTT_ReadFromFlash(...) 0
+#define HF_CheckRecovered(...) 0
+#define HF_HandleFault(...)
+#endif
+
+#ifdef INCLUDE_GEN_OPTIMIZER
+#include "gen_optimizer.h"
+#else
+typedef struct {
+  uint16_t n_params; 
+  uint16_t n_cand; 
+  uint16_t n_best; 
+  uint16_t iq_mutation; 
+  int32_t loss[0]; 
+  int32_t candidates[0][0]; 
+} GenOptimizer_t;
+#define GenOptimizer_Init(opt, n_params, n_cand, n_best, iq_mutation, start_params)
+#define GenOptimizer_Step(opt, params, LossFunc)
+#define PARAM_SCALE_Q16(x, min_val, max_val)            (x)
+#define PARAM_UNSCALE_Q16(q16_val, min_val, max_val)    (q16_val)
+#endif
+
+
+
+#ifdef INCLUDE_BENCH_TIME
+#include "bench_time.h"
+#else //BENCH_TIME_ENABLE
+#define BenchTime_Init()
+#define BenchTime_Start(channel, ticks, tick_period)  0
+#define BenchTime_End(channel, ticks)                 0
+#define BenchTime_GetMin(channel)       0
+#define BenchTime_GetMax(channel)       0
+#define BenchTime_GetAverage(channel)   0
+#define BenchTime_GetCount(channel)     0
+#define BenchTime_GetLast(channel)      0
+#define BenchTime_ResetStats(channel)
+#endif //BENCH_TIME_ENABLE
+
+#ifdef INCLUDE_FILTERS
+#include "filters.h"
+#else //INCLUDE_FILTERS
+#endif //INCLUDE_FILTERS
+
+#ifdef INCLUDE_GENERAL_PERIPH_LIBS
+
+#include "__general_flash.h"
+#include "general_gpio.h"
+#ifdef HAL_SPI_MODULE_ENABLED
+#include "general_spi.h"
+#endif
+#ifdef HAL_UART_MODULE_ENABLED
+#include "general_uart.h"
+#endif
+#ifdef HAL_TIM_MODULE_ENABLED
+#include "general_tim.h"
+#endif
+
+#endif //INCLUDE_GENERAL_PERIPH_LIBS
+
+
+
+
+/////////////////////////---USER SETTINGS---/////////////////////////
+// user includes
+
+// user settings
+/////////////////////////---USER SETTINGS---/////////////////////////
+
+
+#endif // __MYLIBS_INCLUDE_H_

Listings/Firmware.map

@@ -0,0 +1,1953 @@
+Component: ARM Compiler 5.06 update 7 (build 960) Tool: armlink [4d3601]
+
+==============================================================================
+
+Section Cross References
+
+    main.o(i.GenOptimizer_Init) refers to rand.o(.text) for srand
+    main.o(i.GenOptimizer_Init) refers to rand.o(.emb_text) for rand
+    main.o(i.GenOptimizer_Init) refers to system_k1921vk035.o(.data) for uwTick
+    main.o(i.GenOptimizer_Step) refers to qsortnoex.o(.text) for qsort
+    main.o(i.GenOptimizer_Step) refers to rand.o(.emb_text) for rand
+    main.o(i.GenOptimizer_Step) refers to main.o(.data) for g_sort_opt
+    main.o(i.GenOptimizer_Step) refers to main.o(i.cmp_idx) for cmp_idx
+    main.o(i.assert_failed) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+    main.o(i.assert_failed) refers to _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) for _printf_d
+    main.o(i.assert_failed) refers to _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) for _printf_s
+    main.o(i.assert_failed) refers to _printf_dec.o(.text) for _printf_int_dec
+    main.o(i.assert_failed) refers to _printf_str.o(.text) for _printf_str
+    main.o(i.assert_failed) refers to noretval__2printf.o(.text) for __2printf
+    main.o(i.cmp_idx) refers to main.o(.data) for g_sort_opt
+    main.o(i.main) refers to main.o(i.periph_init) for periph_init
+    main.o(i.periph_init) refers to _printf_pad.o(.text) for _printf_pre_padding
+    main.o(i.periph_init) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+    main.o(i.periph_init) refers to _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) for _printf_d
+    main.o(i.periph_init) refers to _printf_dec.o(.text) for _printf_int_dec
+    main.o(i.periph_init) refers to system_k1921vk035.o(i.SystemCoreClockUpdate) for SystemCoreClockUpdate
+    main.o(i.periph_init) refers to rcu.o(i.sysclk_init) for sysclk_init
+    main.o(i.periph_init) refers to gpio.o(i.gpio_init) for gpio_init
+    main.o(i.periph_init) refers to retarget_conf.o(i.retarget_init) for retarget_init
+    main.o(i.periph_init) refers to dflt_clz.o(x$fpl$dfltu) for __aeabi_ui2d
+    main.o(i.periph_init) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv
+    main.o(i.periph_init) refers to dfix.o(x$fpl$dfix) for __aeabi_d2iz
+    main.o(i.periph_init) refers to noretval__2printf.o(.text) for __2printf
+    main.o(i.periph_init) refers to system_k1921vk035.o(.data) for SystemCoreClock
+    gpio.o(i.GenOptimizer_Init) refers to rand.o(.text) for srand
+    gpio.o(i.GenOptimizer_Init) refers to rand.o(.emb_text) for rand
+    gpio.o(i.GenOptimizer_Init) refers to system_k1921vk035.o(.data) for uwTick
+    gpio.o(i.GenOptimizer_Step) refers to qsortnoex.o(.text) for qsort
+    gpio.o(i.GenOptimizer_Step) refers to rand.o(.emb_text) for rand
+    gpio.o(i.GenOptimizer_Step) refers to gpio.o(.data) for g_sort_opt
+    gpio.o(i.GenOptimizer_Step) refers to gpio.o(i.cmp_idx) for cmp_idx
+    gpio.o(i.RCU_AHBClkCmd) refers to main.o(i.assert_failed) for assert_failed
+    gpio.o(i.RCU_AHBRstCmd) refers to main.o(i.assert_failed) for assert_failed
+    gpio.o(i.RCU_AHBRstCmd) refers to gpio.o(i.RCU_AHBClkCmd) for i.RCU_AHBClkCmd
+    gpio.o(i.cmp_idx) refers to gpio.o(.data) for g_sort_opt
+    gpio.o(i.gpio_init) refers to gpio.o(i.RCU_AHBClkCmd) for RCU_AHBClkCmd
+    gpio.o(i.gpio_init) refers to gpio.o(i.RCU_AHBRstCmd) for RCU_AHBRstCmd
+    gpio.o(i.gpio_init) refers to plib035_gpio.o(i.GPIO_DeInit) for GPIO_DeInit
+    gpio.o(i.gpio_init) refers to plib035_gpio.o(i.GPIO_Init) for GPIO_Init
+    gpio.o(i.gpio_init) refers to gpio.o(.data) for gpioa_config
+    rcu.o(i.GenOptimizer_Init) refers to rand.o(.text) for srand
+    rcu.o(i.GenOptimizer_Init) refers to rand.o(.emb_text) for rand
+    rcu.o(i.GenOptimizer_Init) refers to system_k1921vk035.o(.data) for uwTick
+    rcu.o(i.GenOptimizer_Step) refers to qsortnoex.o(.text) for qsort
+    rcu.o(i.GenOptimizer_Step) refers to rand.o(.emb_text) for rand
+    rcu.o(i.GenOptimizer_Step) refers to rcu.o(.data) for g_sort_opt
+    rcu.o(i.GenOptimizer_Step) refers to rcu.o(i.cmp_idx) for cmp_idx
+    rcu.o(i.RCU_ClkOutConfig) refers to main.o(i.assert_failed) for assert_failed
+    rcu.o(i.RCU_ClkOutConfig) refers to rcu.o(i.sysclk_init) for i.sysclk_init
+    rcu.o(i.cmp_idx) refers to rcu.o(.data) for g_sort_opt
+    rcu.o(i.sysclk_init) refers to plib035_rcu.o(i.RCU_PLL_AutoConfig) for RCU_PLL_AutoConfig
+    rcu.o(i.sysclk_init) refers to main.o(i.Error_Handler) for Error_Handler
+    rcu.o(i.sysclk_init) refers to system_k1921vk035.o(i.SystemCoreClockUpdate) for SystemCoreClockUpdate
+    rcu.o(i.sysclk_init) refers to rcu.o(i.RCU_ClkOutConfig) for RCU_ClkOutConfig
+    rcu.o(i.sysclk_init) refers to main.o(i.assert_failed) for assert_failed
+    rcu.o(i.sysclk_init) refers to rcu.o(.data) for OS_Type
+    vk035_it.o(i.GenOptimizer_Init) refers to rand.o(.text) for srand
+    vk035_it.o(i.GenOptimizer_Init) refers to rand.o(.emb_text) for rand
+    vk035_it.o(i.GenOptimizer_Init) refers to system_k1921vk035.o(.data) for uwTick
+    vk035_it.o(i.GenOptimizer_Step) refers to qsortnoex.o(.text) for qsort
+    vk035_it.o(i.GenOptimizer_Step) refers to rand.o(.emb_text) for rand
+    vk035_it.o(i.GenOptimizer_Step) refers to vk035_it.o(.data) for g_sort_opt
+    vk035_it.o(i.GenOptimizer_Step) refers to vk035_it.o(i.cmp_idx) for cmp_idx
+    vk035_it.o(i.SysTick_Handler) refers to system_k1921vk035.o(.data) for uwTick
+    vk035_it.o(i.cmp_idx) refers to vk035_it.o(.data) for g_sort_opt
+    segger_rtt.o(i.SEGGER_RTT_AllocDownBuffer) refers to segger_rtt.o(i._DoInit) for _DoInit
+    segger_rtt.o(i.SEGGER_RTT_AllocDownBuffer) refers to segger_rtt.o(.bss) for _SEGGER_RTT
+    segger_rtt.o(i.SEGGER_RTT_AllocUpBuffer) refers to segger_rtt.o(i._DoInit) for _DoInit
+    segger_rtt.o(i.SEGGER_RTT_AllocUpBuffer) refers to segger_rtt.o(.bss) for _SEGGER_RTT
+    segger_rtt.o(i.SEGGER_RTT_ConfigDownBuffer) refers to segger_rtt.o(i._DoInit) for _DoInit
+    segger_rtt.o(i.SEGGER_RTT_ConfigDownBuffer) refers to segger_rtt.o(.bss) for _SEGGER_RTT
+    segger_rtt.o(i.SEGGER_RTT_ConfigUpBuffer) refers to segger_rtt.o(i._DoInit) for _DoInit
+    segger_rtt.o(i.SEGGER_RTT_ConfigUpBuffer) refers to segger_rtt.o(.bss) for _SEGGER_RTT
+    segger_rtt.o(i.SEGGER_RTT_GetAvailWriteSpace) refers to segger_rtt.o(i._GetAvailWriteSpace) for _GetAvailWriteSpace
+    segger_rtt.o(i.SEGGER_RTT_GetAvailWriteSpace) refers to segger_rtt.o(.bss) for _SEGGER_RTT
+    segger_rtt.o(i.SEGGER_RTT_GetBytesInBuffer) refers to segger_rtt.o(.bss) for _SEGGER_RTT
+    segger_rtt.o(i.SEGGER_RTT_GetKey) refers to segger_rtt.o(i.SEGGER_RTT_Read) for SEGGER_RTT_Read
+    segger_rtt.o(i.SEGGER_RTT_HasData) refers to segger_rtt.o(.bss) for _SEGGER_RTT
+    segger_rtt.o(i.SEGGER_RTT_HasDataUp) refers to segger_rtt.o(.bss) for _SEGGER_RTT
+    segger_rtt.o(i.SEGGER_RTT_HasKey) refers to segger_rtt.o(i._DoInit) for _DoInit
+    segger_rtt.o(i.SEGGER_RTT_HasKey) refers to segger_rtt.o(.bss) for _SEGGER_RTT
+    segger_rtt.o(i.SEGGER_RTT_Init) refers to segger_rtt.o(i._DoInit) for _DoInit
+    segger_rtt.o(i.SEGGER_RTT_PutChar) refers to segger_rtt.o(i._DoInit) for _DoInit
+    segger_rtt.o(i.SEGGER_RTT_PutChar) refers to segger_rtt.o(.bss) for _SEGGER_RTT
+    segger_rtt.o(i.SEGGER_RTT_PutCharSkip) refers to segger_rtt.o(i._DoInit) for _DoInit
+    segger_rtt.o(i.SEGGER_RTT_PutCharSkip) refers to segger_rtt.o(.bss) for _SEGGER_RTT
+    segger_rtt.o(i.SEGGER_RTT_PutCharSkipNoLock) refers to segger_rtt.o(.bss) for _SEGGER_RTT
+    segger_rtt.o(i.SEGGER_RTT_Read) refers to segger_rtt.o(i.SEGGER_RTT_ReadNoLock) for SEGGER_RTT_ReadNoLock
+    segger_rtt.o(i.SEGGER_RTT_ReadNoLock) refers to segger_rtt.o(i._DoInit) for _DoInit
+    segger_rtt.o(i.SEGGER_RTT_ReadNoLock) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy
+    segger_rtt.o(i.SEGGER_RTT_ReadNoLock) refers to segger_rtt.o(.bss) for _SEGGER_RTT
+    segger_rtt.o(i.SEGGER_RTT_ReadUpBuffer) refers to segger_rtt.o(i.SEGGER_RTT_ReadUpBufferNoLock) for SEGGER_RTT_ReadUpBufferNoLock
+    segger_rtt.o(i.SEGGER_RTT_ReadUpBufferNoLock) refers to segger_rtt.o(i._DoInit) for _DoInit
+    segger_rtt.o(i.SEGGER_RTT_ReadUpBufferNoLock) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy
+    segger_rtt.o(i.SEGGER_RTT_ReadUpBufferNoLock) refers to segger_rtt.o(.bss) for _SEGGER_RTT
+    segger_rtt.o(i.SEGGER_RTT_SetFlagsDownBuffer) refers to segger_rtt.o(i._DoInit) for _DoInit
+    segger_rtt.o(i.SEGGER_RTT_SetFlagsDownBuffer) refers to segger_rtt.o(.bss) for _SEGGER_RTT
+    segger_rtt.o(i.SEGGER_RTT_SetFlagsUpBuffer) refers to segger_rtt.o(i._DoInit) for _DoInit
+    segger_rtt.o(i.SEGGER_RTT_SetFlagsUpBuffer) refers to segger_rtt.o(.bss) for _SEGGER_RTT
+    segger_rtt.o(i.SEGGER_RTT_SetNameDownBuffer) refers to segger_rtt.o(i._DoInit) for _DoInit
+    segger_rtt.o(i.SEGGER_RTT_SetNameDownBuffer) refers to segger_rtt.o(.bss) for _SEGGER_RTT
+    segger_rtt.o(i.SEGGER_RTT_SetNameUpBuffer) refers to segger_rtt.o(i._DoInit) for _DoInit
+    segger_rtt.o(i.SEGGER_RTT_SetNameUpBuffer) refers to segger_rtt.o(.bss) for _SEGGER_RTT
+    segger_rtt.o(i.SEGGER_RTT_SetTerminal) refers to segger_rtt.o(i._DoInit) for _DoInit
+    segger_rtt.o(i.SEGGER_RTT_SetTerminal) refers to segger_rtt.o(i._WriteBlocking) for _WriteBlocking
+    segger_rtt.o(i.SEGGER_RTT_SetTerminal) refers to segger_rtt.o(i._GetAvailWriteSpace) for _GetAvailWriteSpace
+    segger_rtt.o(i.SEGGER_RTT_SetTerminal) refers to segger_rtt.o(i._WriteNoCheck) for _WriteNoCheck
+    segger_rtt.o(i.SEGGER_RTT_SetTerminal) refers to segger_rtt.o(.bss) for _SEGGER_RTT
+    segger_rtt.o(i.SEGGER_RTT_SetTerminal) refers to segger_rtt.o(.constdata) for _aTerminalId
+    segger_rtt.o(i.SEGGER_RTT_SetTerminal) refers to segger_rtt.o(.data) for _ActiveTerminal
+    segger_rtt.o(i.SEGGER_RTT_TerminalOut) refers to segger_rtt.o(i._DoInit) for _DoInit
+    segger_rtt.o(i.SEGGER_RTT_TerminalOut) refers to strlen.o(.text) for strlen
+    segger_rtt.o(i.SEGGER_RTT_TerminalOut) refers to segger_rtt.o(i._GetAvailWriteSpace) for _GetAvailWriteSpace
+    segger_rtt.o(i.SEGGER_RTT_TerminalOut) refers to segger_rtt.o(i._PostTerminalSwitch) for _PostTerminalSwitch
+    segger_rtt.o(i.SEGGER_RTT_TerminalOut) refers to segger_rtt.o(i._WriteBlocking) for _WriteBlocking
+    segger_rtt.o(i.SEGGER_RTT_TerminalOut) refers to segger_rtt.o(.bss) for _SEGGER_RTT
+    segger_rtt.o(i.SEGGER_RTT_TerminalOut) refers to segger_rtt.o(.data) for _ActiveTerminal
+    segger_rtt.o(i.SEGGER_RTT_WaitKey) refers to segger_rtt.o(i.SEGGER_RTT_GetKey) for SEGGER_RTT_GetKey
+    segger_rtt.o(i.SEGGER_RTT_Write) refers to segger_rtt.o(i._DoInit) for _DoInit
+    segger_rtt.o(i.SEGGER_RTT_Write) refers to segger_rtt.o(i.SEGGER_RTT_WriteNoLock) for SEGGER_RTT_WriteNoLock
+    segger_rtt.o(i.SEGGER_RTT_Write) refers to segger_rtt.o(.bss) for _SEGGER_RTT
+    segger_rtt.o(i.SEGGER_RTT_WriteDownBuffer) refers to segger_rtt.o(i._DoInit) for _DoInit
+    segger_rtt.o(i.SEGGER_RTT_WriteDownBuffer) refers to segger_rtt.o(i.SEGGER_RTT_WriteDownBufferNoLock) for SEGGER_RTT_WriteDownBufferNoLock
+    segger_rtt.o(i.SEGGER_RTT_WriteDownBuffer) refers to segger_rtt.o(.bss) for _SEGGER_RTT
+    segger_rtt.o(i.SEGGER_RTT_WriteDownBufferNoLock) refers to segger_rtt.o(i._GetAvailWriteSpace) for _GetAvailWriteSpace
+    segger_rtt.o(i.SEGGER_RTT_WriteDownBufferNoLock) refers to segger_rtt.o(i._WriteNoCheck) for _WriteNoCheck
+    segger_rtt.o(i.SEGGER_RTT_WriteDownBufferNoLock) refers to segger_rtt.o(i._WriteBlocking) for _WriteBlocking
+    segger_rtt.o(i.SEGGER_RTT_WriteDownBufferNoLock) refers to segger_rtt.o(.bss) for _SEGGER_RTT
+    segger_rtt.o(i.SEGGER_RTT_WriteNoLock) refers to segger_rtt.o(i._GetAvailWriteSpace) for _GetAvailWriteSpace
+    segger_rtt.o(i.SEGGER_RTT_WriteNoLock) refers to segger_rtt.o(i._WriteNoCheck) for _WriteNoCheck
+    segger_rtt.o(i.SEGGER_RTT_WriteNoLock) refers to segger_rtt.o(i._WriteBlocking) for _WriteBlocking
+    segger_rtt.o(i.SEGGER_RTT_WriteNoLock) refers to segger_rtt.o(.bss) for _SEGGER_RTT
+    segger_rtt.o(i.SEGGER_RTT_WriteSkipNoLock) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy
+    segger_rtt.o(i.SEGGER_RTT_WriteSkipNoLock) refers to segger_rtt.o(.bss) for _SEGGER_RTT
+    segger_rtt.o(i.SEGGER_RTT_WriteString) refers to strlen.o(.text) for strlen
+    segger_rtt.o(i.SEGGER_RTT_WriteString) refers to segger_rtt.o(i.SEGGER_RTT_Write) for SEGGER_RTT_Write
+    segger_rtt.o(i.SEGGER_RTT_WriteWithOverwriteNoLock) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy
+    segger_rtt.o(i.SEGGER_RTT_WriteWithOverwriteNoLock) refers to segger_rtt.o(.bss) for _SEGGER_RTT
+    segger_rtt.o(i._DoInit) refers to rt_memclr_w.o(.text) for __aeabi_memclr4
+    segger_rtt.o(i._DoInit) refers to segger_rtt.o(.bss) for _SEGGER_RTT
+    segger_rtt.o(i._DoInit) refers to segger_rtt.o(.constdata) for _aInitStr
+    segger_rtt.o(i._PostTerminalSwitch) refers to segger_rtt.o(i._WriteBlocking) for _WriteBlocking
+    segger_rtt.o(i._PostTerminalSwitch) refers to segger_rtt.o(.constdata) for _aTerminalId
+    segger_rtt.o(i._WriteBlocking) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy
+    segger_rtt.o(i._WriteNoCheck) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy
+    segger_rtt_printf.o(i.SEGGER_RTT_printf) refers to segger_rtt_printf.o(i.SEGGER_RTT_vprintf) for SEGGER_RTT_vprintf
+    segger_rtt_printf.o(i.SEGGER_RTT_vprintf) refers to segger_rtt_printf.o(i._StoreChar) for _StoreChar
+    segger_rtt_printf.o(i.SEGGER_RTT_vprintf) refers to segger_rtt_printf.o(i._PrintInt) for _PrintInt
+    segger_rtt_printf.o(i.SEGGER_RTT_vprintf) refers to segger_rtt_printf.o(i._PrintUnsigned) for _PrintUnsigned
+    segger_rtt_printf.o(i.SEGGER_RTT_vprintf) refers to segger_rtt.o(i.SEGGER_RTT_Write) for SEGGER_RTT_Write
+    segger_rtt_printf.o(i._PrintInt) refers to segger_rtt_printf.o(i._StoreChar) for _StoreChar
+    segger_rtt_printf.o(i._PrintInt) refers to segger_rtt_printf.o(i._PrintUnsigned) for _PrintUnsigned
+    segger_rtt_printf.o(i._PrintUnsigned) refers to segger_rtt_printf.o(i._StoreChar) for _StoreChar
+    segger_rtt_printf.o(i._PrintUnsigned) refers to segger_rtt_printf.o(.constdata) for _aV2C
+    segger_rtt_printf.o(i._StoreChar) refers to segger_rtt.o(i.SEGGER_RTT_Write) for SEGGER_RTT_Write
+    filters.o(i.FilterAverageInt_Init) refers to filters.o(i.FilterAverageInt_Process) for FilterAverageInt_Process
+    filters.o(i.FilterAverageInt_Process) refers to llsdiv.o(.text) for __aeabi_ldivmod
+    filters.o(i.FilterAverage_Init) refers to filters.o(i.FilterAverage_Process) for FilterAverage_Process
+    filters.o(i.FilterBandPassDerivative_Init) refers to sinf.o(i.__hardfp_sinf) for __hardfp_sinf
+    filters.o(i.FilterBandPassDerivative_Init) refers to cosf.o(i.__hardfp_cosf) for __hardfp_cosf
+    filters.o(i.FilterBandPassDerivative_Init) refers to filters.o(i.FilterBandPassDerivative_Process) for FilterBandPassDerivative_Process
+    filters.o(i.FilterExpInt_Init) refers to filters.o(i.FilterExpInt_Process) for FilterExpInt_Process
+    filters.o(i.FilterExpInt_Process) refers to llsdiv.o(.text) for __aeabi_ldivmod
+    filters.o(i.FilterExp_Init) refers to filters.o(i.FilterExp_Process) for FilterExp_Process
+    filters.o(i.FilterLUTInt_Init) refers to filters.o(i.FilterLUTInt_Process) for FilterLUTInt_Process
+    filters.o(i.FilterLUTInt_Process) refers to llsdiv.o(.text) for __aeabi_ldivmod
+    filters.o(i.FilterLUT_Init) refers to filters.o(i.FilterLUT_Process) for FilterLUT_Process
+    filters.o(i.FilterMedianInt_Init) refers to filters.o(i.FilterMedianInt_Process) for FilterMedianInt_Process
+    filters.o(i.FilterMedian_Init) refers to filters.o(i.FilterMedian_Process) for FilterMedian_Process
+    filters.o(i.FilterMedian_Process) refers to rt_memcpy_w.o(.text) for __aeabi_memcpy4
+    filters.o(i.FilterMedian_Process) refers to qsortnoex.o(.text) for qsort
+    filters.o(i.FilterMedian_Process) refers to filters.o(i.Filter_float_compare) for Filter_float_compare
+    filters.o(i.FilterPolyInt_Init) refers to rt_memcpy_w.o(.text) for __aeabi_memcpy4
+    filters.o(i.FilterPolyInt_Init) refers to filters.o(i.FilterPolyInt_Process) for FilterPolyInt_Process
+    filters.o(i.FilterPolyInt_Process) refers to llsdiv.o(.text) for __aeabi_ldivmod
+    filters.o(i.FilterPoly_Init) refers to rt_memcpy_w.o(.text) for __aeabi_memcpy4
+    filters.o(i.FilterPoly_Init) refers to filters.o(i.FilterPoly_Process) for FilterPoly_Process
+    filters.o(i.FilterRMSInt_Init) refers to rt_memclr_w.o(.text) for __aeabi_memclr4
+    filters.o(i.FilterRMSInt_Init) refers to filters.o(i.FilterRMSInt_Process) for FilterRMSInt_Process
+    filters.o(i.FilterRMSInt_Process) refers to llsdiv.o(.text) for __aeabi_ldivmod
+    filters.o(i.FilterRMSInt_Process) refers to ffltll_clz.o(x$fpl$ffltll) for __aeabi_l2f
+    filters.o(i.FilterRMS_Init) refers to rt_memclr_w.o(.text) for __aeabi_memclr4
+    filters.o(i.FilterRMS_Init) refers to filters.o(i.FilterRMS_Process) for FilterRMS_Process
+    system_k1921vk035.o(i.SystemCoreClockUpdate) refers to system_k1921vk035.o(.data) for SystemCoreClock
+    system_k1921vk035.o(i.SystemInit) refers to system_k1921vk035.o(i.ClkInit) for ClkInit
+    system_k1921vk035.o(i.SystemInit) refers to system_k1921vk035.o(i.FPUInit) for FPUInit
+    startup_k1921vk035.o(STACK) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
+    startup_k1921vk035.o(HEAP) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
+    startup_k1921vk035.o(RESET) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
+    startup_k1921vk035.o(RESET) refers to startup_k1921vk035.o(STACK) for __initial_sp
+    startup_k1921vk035.o(RESET) refers to startup_k1921vk035.o(.text) for Reset_Handler
+    startup_k1921vk035.o(RESET) refers to vk035_it.o(i.NMI_Handler) for NMI_Handler
+    startup_k1921vk035.o(RESET) refers to vk035_it.o(i.HardFault_Handler) for HardFault_Handler
+    startup_k1921vk035.o(RESET) refers to vk035_it.o(i.MemManage_Handler) for MemManage_Handler
+    startup_k1921vk035.o(RESET) refers to vk035_it.o(i.BusFault_Handler) for BusFault_Handler
+    startup_k1921vk035.o(RESET) refers to vk035_it.o(i.UsageFault_Handler) for UsageFault_Handler
+    startup_k1921vk035.o(RESET) refers to vk035_it.o(i.SVC_Handler) for SVC_Handler
+    startup_k1921vk035.o(RESET) refers to vk035_it.o(i.DebugMon_Handler) for DebugMon_Handler
+    startup_k1921vk035.o(RESET) refers to vk035_it.o(i.PendSV_Handler) for PendSV_Handler
+    startup_k1921vk035.o(RESET) refers to vk035_it.o(i.SysTick_Handler) for SysTick_Handler
+    startup_k1921vk035.o(.text) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
+    startup_k1921vk035.o(.text) refers to system_k1921vk035.o(i.SystemInit) for SystemInit
+    startup_k1921vk035.o(.text) refers to __main.o(!!!main) for __main
+    startup_k1921vk035.o(.text) refers to startup_k1921vk035.o(HEAP) for Heap_Mem
+    startup_k1921vk035.o(.text) refers to startup_k1921vk035.o(STACK) for Stack_Mem
+    plib035_adc.o(i.ADC_DC_ChannelConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_adc.o(i.ADC_DC_ChannelConfig) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init
+    plib035_adc.o(i.ADC_DC_Config) refers to main.o(i.assert_failed) for assert_failed
+    plib035_adc.o(i.ADC_DC_Config) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init
+    plib035_adc.o(i.ADC_DC_Init) refers to plib035_adc.o(i.ADC_DC_OutputCmd) for ADC_DC_OutputCmd
+    plib035_adc.o(i.ADC_DC_Init) refers to plib035_adc.o(i.ADC_DC_SetThresholdLow) for ADC_DC_SetThresholdLow
+    plib035_adc.o(i.ADC_DC_Init) refers to plib035_adc.o(i.ADC_DC_SetThresholdHigh) for ADC_DC_SetThresholdHigh
+    plib035_adc.o(i.ADC_DC_Init) refers to plib035_adc.o(i.ADC_DC_SourceConfig) for ADC_DC_SourceConfig
+    plib035_adc.o(i.ADC_DC_Init) refers to plib035_adc.o(i.ADC_DC_ChannelConfig) for ADC_DC_ChannelConfig
+    plib035_adc.o(i.ADC_DC_Init) refers to plib035_adc.o(i.ADC_DC_Config) for ADC_DC_Config
+    plib035_adc.o(i.ADC_DC_OutputCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_adc.o(i.ADC_DC_OutputCmd) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init
+    plib035_adc.o(i.ADC_DC_SetThresholdHigh) refers to main.o(i.assert_failed) for assert_failed
+    plib035_adc.o(i.ADC_DC_SetThresholdHigh) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init
+    plib035_adc.o(i.ADC_DC_SetThresholdLow) refers to main.o(i.assert_failed) for assert_failed
+    plib035_adc.o(i.ADC_DC_SetThresholdLow) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init
+    plib035_adc.o(i.ADC_DC_SourceConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_adc.o(i.ADC_DC_SourceConfig) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init
+    plib035_adc.o(i.ADC_DeInit) refers to plib035_adc.o(i.RCU_ADCRstCmd) for RCU_ADCRstCmd
+    plib035_adc.o(i.ADC_SEQ_DCEnableCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_adc.o(i.ADC_SEQ_DCEnableCmd) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init
+    plib035_adc.o(i.ADC_SEQ_DMACmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_adc.o(i.ADC_SEQ_DMACmd) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init
+    plib035_adc.o(i.ADC_SEQ_DMAConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_adc.o(i.ADC_SEQ_DMAConfig) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init
+    plib035_adc.o(i.ADC_SEQ_Init) refers to main.o(i.assert_failed) for assert_failed
+    plib035_adc.o(i.ADC_SEQ_Init) refers to plib035_adc.o(i.ADC_SEQ_SwStartEnCmd) for ADC_SEQ_SwStartEnCmd
+    plib035_adc.o(i.ADC_SEQ_Init) refers to plib035_adc.o(i.ADC_SEQ_ReqConfig) for ADC_SEQ_ReqConfig
+    plib035_adc.o(i.ADC_SEQ_Init) refers to plib035_adc.o(i.ADC_SEQ_ReqMaxConfig) for ADC_SEQ_ReqMaxConfig
+    plib035_adc.o(i.ADC_SEQ_Init) refers to plib035_adc.o(i.ADC_SEQ_ReqAverageConfig) for ADC_SEQ_ReqAverageConfig
+    plib035_adc.o(i.ADC_SEQ_Init) refers to plib035_adc.o(i.ADC_SEQ_ReqAverageCmd) for ADC_SEQ_ReqAverageCmd
+    plib035_adc.o(i.ADC_SEQ_Init) refers to plib035_adc.o(i.ADC_SEQ_RestartConfig) for ADC_SEQ_RestartConfig
+    plib035_adc.o(i.ADC_SEQ_Init) refers to plib035_adc.o(i.ADC_SEQ_RestartAverageCmd) for ADC_SEQ_RestartAverageCmd
+    plib035_adc.o(i.ADC_SEQ_Init) refers to plib035_adc.o(i.ADC_SEQ_SetRestartTimer) for ADC_SEQ_SetRestartTimer
+    plib035_adc.o(i.ADC_SEQ_Init) refers to plib035_adc.o(i.ADC_SEQ_DCEnableCmd) for ADC_SEQ_DCEnableCmd
+    plib035_adc.o(i.ADC_SEQ_Init) refers to plib035_adc.o(i.ADC_SEQ_DMAConfig) for ADC_SEQ_DMAConfig
+    plib035_adc.o(i.ADC_SEQ_Init) refers to plib035_adc.o(i.ADC_SEQ_DMACmd) for ADC_SEQ_DMACmd
+    plib035_adc.o(i.ADC_SEQ_ReqAverageCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_adc.o(i.ADC_SEQ_ReqAverageCmd) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init
+    plib035_adc.o(i.ADC_SEQ_ReqAverageConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_adc.o(i.ADC_SEQ_ReqAverageConfig) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init
+    plib035_adc.o(i.ADC_SEQ_ReqConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_adc.o(i.ADC_SEQ_ReqConfig) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init
+    plib035_adc.o(i.ADC_SEQ_ReqMaxConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_adc.o(i.ADC_SEQ_ReqMaxConfig) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init
+    plib035_adc.o(i.ADC_SEQ_RestartAverageCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_adc.o(i.ADC_SEQ_RestartAverageCmd) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init
+    plib035_adc.o(i.ADC_SEQ_RestartConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_adc.o(i.ADC_SEQ_RestartConfig) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init
+    plib035_adc.o(i.ADC_SEQ_SetRestartTimer) refers to main.o(i.assert_failed) for assert_failed
+    plib035_adc.o(i.ADC_SEQ_SetRestartTimer) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init
+    plib035_adc.o(i.ADC_SEQ_SwStartEnCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_adc.o(i.ADC_SEQ_SwStartEnCmd) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init
+    plib035_adc.o(i.RCU_ADCRstCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_dma.o(i.DMA_AltCtrlCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_dma.o(i.DMA_AltCtrlCmd) refers to plib035_dma.o(i.DMA_ProtectConfig) for i.DMA_ProtectConfig
+    plib035_dma.o(i.DMA_ChannelEnableCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_dma.o(i.DMA_ChannelEnableCmd) refers to plib035_dma.o(i.DMA_ProtectConfig) for i.DMA_ProtectConfig
+    plib035_dma.o(i.DMA_ChannelInit) refers to main.o(i.assert_failed) for assert_failed
+    plib035_dma.o(i.DMA_HighPriorityCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_dma.o(i.DMA_HighPriorityCmd) refers to plib035_dma.o(i.DMA_ProtectConfig) for i.DMA_ProtectConfig
+    plib035_dma.o(i.DMA_Init) refers to plib035_dma.o(i.DMA_ProtectConfig) for DMA_ProtectConfig
+    plib035_dma.o(i.DMA_Init) refers to plib035_dma.o(i.DMA_UseBurstCmd) for DMA_UseBurstCmd
+    plib035_dma.o(i.DMA_Init) refers to plib035_dma.o(i.DMA_AltCtrlCmd) for DMA_AltCtrlCmd
+    plib035_dma.o(i.DMA_Init) refers to plib035_dma.o(i.DMA_HighPriorityCmd) for DMA_HighPriorityCmd
+    plib035_dma.o(i.DMA_Init) refers to plib035_dma.o(i.DMA_ReqMaskCmd) for DMA_ReqMaskCmd
+    plib035_dma.o(i.DMA_Init) refers to plib035_dma.o(i.DMA_ChannelEnableCmd) for DMA_ChannelEnableCmd
+    plib035_dma.o(i.DMA_ProtectConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_dma.o(i.DMA_ReqMaskCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_dma.o(i.DMA_ReqMaskCmd) refers to plib035_dma.o(i.DMA_ProtectConfig) for i.DMA_ProtectConfig
+    plib035_dma.o(i.DMA_UseBurstCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_dma.o(i.DMA_UseBurstCmd) refers to plib035_dma.o(i.DMA_ProtectConfig) for i.DMA_ProtectConfig
+    plib035_ecap.o(i.ECAP_Capture_Init) refers to plib035_ecap.o(i.ECAP_Capture_ModeConfig) for ECAP_Capture_ModeConfig
+    plib035_ecap.o(i.ECAP_Capture_Init) refers to plib035_ecap.o(i.ECAP_Capture_StopConfig) for ECAP_Capture_StopConfig
+    plib035_ecap.o(i.ECAP_Capture_Init) refers to plib035_ecap.o(i.ECAP_Capture_PrescaleConfig) for ECAP_Capture_PrescaleConfig
+    plib035_ecap.o(i.ECAP_Capture_Init) refers to plib035_ecap.o(i.ECAP_Capture_PolarityEvt0Config) for ECAP_Capture_PolarityEvt0Config
+    plib035_ecap.o(i.ECAP_Capture_Init) refers to plib035_ecap.o(i.ECAP_Capture_PolarityEvt1Config) for ECAP_Capture_PolarityEvt1Config
+    plib035_ecap.o(i.ECAP_Capture_Init) refers to plib035_ecap.o(i.ECAP_Capture_PolarityEvt2Config) for ECAP_Capture_PolarityEvt2Config
+    plib035_ecap.o(i.ECAP_Capture_Init) refers to plib035_ecap.o(i.ECAP_Capture_PolarityEvt3Config) for ECAP_Capture_PolarityEvt3Config
+    plib035_ecap.o(i.ECAP_Capture_Init) refers to plib035_ecap.o(i.ECAP_Capture_RstEvt0Cmd) for ECAP_Capture_RstEvt0Cmd
+    plib035_ecap.o(i.ECAP_Capture_Init) refers to plib035_ecap.o(i.ECAP_Capture_RstEvt1Cmd) for ECAP_Capture_RstEvt1Cmd
+    plib035_ecap.o(i.ECAP_Capture_Init) refers to plib035_ecap.o(i.ECAP_Capture_RstEvt2Cmd) for ECAP_Capture_RstEvt2Cmd
+    plib035_ecap.o(i.ECAP_Capture_Init) refers to plib035_ecap.o(i.ECAP_Capture_RstEvt3Cmd) for ECAP_Capture_RstEvt3Cmd
+    plib035_ecap.o(i.ECAP_Capture_ModeConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_ecap.o(i.ECAP_Capture_ModeConfig) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init
+    plib035_ecap.o(i.ECAP_Capture_PolarityEvt0Config) refers to main.o(i.assert_failed) for assert_failed
+    plib035_ecap.o(i.ECAP_Capture_PolarityEvt0Config) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init
+    plib035_ecap.o(i.ECAP_Capture_PolarityEvt1Config) refers to main.o(i.assert_failed) for assert_failed
+    plib035_ecap.o(i.ECAP_Capture_PolarityEvt1Config) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init
+    plib035_ecap.o(i.ECAP_Capture_PolarityEvt2Config) refers to main.o(i.assert_failed) for assert_failed
+    plib035_ecap.o(i.ECAP_Capture_PolarityEvt2Config) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init
+    plib035_ecap.o(i.ECAP_Capture_PolarityEvt3Config) refers to main.o(i.assert_failed) for assert_failed
+    plib035_ecap.o(i.ECAP_Capture_PolarityEvt3Config) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init
+    plib035_ecap.o(i.ECAP_Capture_PrescaleConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_ecap.o(i.ECAP_Capture_PrescaleConfig) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init
+    plib035_ecap.o(i.ECAP_Capture_RstEvt0Cmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_ecap.o(i.ECAP_Capture_RstEvt0Cmd) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init
+    plib035_ecap.o(i.ECAP_Capture_RstEvt1Cmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_ecap.o(i.ECAP_Capture_RstEvt1Cmd) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init
+    plib035_ecap.o(i.ECAP_Capture_RstEvt2Cmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_ecap.o(i.ECAP_Capture_RstEvt2Cmd) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init
+    plib035_ecap.o(i.ECAP_Capture_RstEvt3Cmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_ecap.o(i.ECAP_Capture_RstEvt3Cmd) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init
+    plib035_ecap.o(i.ECAP_Capture_StopConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_ecap.o(i.ECAP_Capture_StopConfig) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init
+    plib035_ecap.o(i.ECAP_DeInit) refers to main.o(i.assert_failed) for assert_failed
+    plib035_ecap.o(i.ECAP_DeInit) refers to plib035_ecap.o(i.RCU_APBRstCmd) for RCU_APBRstCmd
+    plib035_ecap.o(i.ECAP_HaltConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_ecap.o(i.ECAP_HaltConfig) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init
+    plib035_ecap.o(i.ECAP_Init) refers to plib035_ecap.o(i.ECAP_HaltConfig) for ECAP_HaltConfig
+    plib035_ecap.o(i.ECAP_Init) refers to plib035_ecap.o(i.ECAP_SyncOutConfig) for ECAP_SyncOutConfig
+    plib035_ecap.o(i.ECAP_Init) refers to plib035_ecap.o(i.ECAP_SyncCmd) for ECAP_SyncCmd
+    plib035_ecap.o(i.ECAP_Init) refers to plib035_ecap.o(i.ECAP_ModeConfig) for ECAP_ModeConfig
+    plib035_ecap.o(i.ECAP_ModeConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_ecap.o(i.ECAP_ModeConfig) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init
+    plib035_ecap.o(i.ECAP_PWM_Init) refers to main.o(i.assert_failed) for assert_failed
+    plib035_ecap.o(i.ECAP_PWM_Init) refers to plib035_ecap.o(i.ECAP_PWM_PolarityConfig) for ECAP_PWM_PolarityConfig
+    plib035_ecap.o(i.ECAP_PWM_PolarityConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_ecap.o(i.ECAP_PWM_PolarityConfig) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init
+    plib035_ecap.o(i.ECAP_SyncCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_ecap.o(i.ECAP_SyncCmd) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init
+    plib035_ecap.o(i.ECAP_SyncOutConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_ecap.o(i.ECAP_SyncOutConfig) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init
+    plib035_ecap.o(i.RCU_APBRstCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_gpio.o(i.GPIO_AltFuncCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_gpio.o(i.GPIO_AltFuncCmd) refers to plib035_gpio.o(i.GPIO_DigitalCmd) for i.GPIO_DigitalCmd
+    plib035_gpio.o(i.GPIO_DeInit) refers to main.o(i.assert_failed) for assert_failed
+    plib035_gpio.o(i.GPIO_DeInit) refers to plib035_gpio.o(i.RCU_AHBRstCmd) for RCU_AHBRstCmd
+    plib035_gpio.o(i.GPIO_DigitalCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_gpio.o(i.GPIO_DriveModeConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_gpio.o(i.GPIO_DriveModeConfig) refers to plib035_gpio.o(i.GPIO_ModeConfig) for GPIO_ModeConfig
+    plib035_gpio.o(i.GPIO_InModeConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_gpio.o(i.GPIO_InModeConfig) refers to plib035_gpio.o(i.GPIO_ModeConfig) for GPIO_ModeConfig
+    plib035_gpio.o(i.GPIO_Init) refers to plib035_gpio.o(i.GPIO_OutCmd) for GPIO_OutCmd
+    plib035_gpio.o(i.GPIO_Init) refers to plib035_gpio.o(i.GPIO_AltFuncCmd) for GPIO_AltFuncCmd
+    plib035_gpio.o(i.GPIO_Init) refers to plib035_gpio.o(i.GPIO_OutModeConfig) for GPIO_OutModeConfig
+    plib035_gpio.o(i.GPIO_Init) refers to plib035_gpio.o(i.GPIO_InModeConfig) for GPIO_InModeConfig
+    plib035_gpio.o(i.GPIO_Init) refers to plib035_gpio.o(i.GPIO_PullModeConfig) for GPIO_PullModeConfig
+    plib035_gpio.o(i.GPIO_Init) refers to plib035_gpio.o(i.GPIO_DriveModeConfig) for GPIO_DriveModeConfig
+    plib035_gpio.o(i.GPIO_Init) refers to plib035_gpio.o(i.GPIO_DigitalCmd) for GPIO_DigitalCmd
+    plib035_gpio.o(i.GPIO_OutCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_gpio.o(i.GPIO_OutCmd) refers to plib035_gpio.o(i.GPIO_DigitalCmd) for i.GPIO_DigitalCmd
+    plib035_gpio.o(i.GPIO_OutModeConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_gpio.o(i.GPIO_OutModeConfig) refers to plib035_gpio.o(i.GPIO_ModeConfig) for GPIO_ModeConfig
+    plib035_gpio.o(i.GPIO_PullModeConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_gpio.o(i.GPIO_PullModeConfig) refers to plib035_gpio.o(i.GPIO_ModeConfig) for GPIO_ModeConfig
+    plib035_gpio.o(i.RCU_AHBRstCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_i2c.o(i.I2C_FSFreqConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_i2c.o(i.I2C_HSFreqConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_i2c.o(i.I2C_HSFreqConfig) refers to plib035_i2c.o(i.I2C_FSFreqConfig) for i.I2C_FSFreqConfig
+    plib035_mflash.o(i.MFLASH_EraseFull) refers to main.o(i.assert_failed) for assert_failed
+    plib035_mflash.o(i.MFLASH_EraseFull) refers to plib035_mflash.o(i.MFLASH_SetCmd) for MFLASH_SetCmd
+    plib035_mflash.o(i.MFLASH_EraseFull) refers to plib035_mflash.o(i.MFLASH_BusyStatus) for MFLASH_BusyStatus
+    plib035_mflash.o(i.MFLASH_ErasePage) refers to main.o(i.assert_failed) for assert_failed
+    plib035_mflash.o(i.MFLASH_ErasePage) refers to plib035_mflash.o(i.MFLASH_SetAddr) for MFLASH_SetAddr
+    plib035_mflash.o(i.MFLASH_ErasePage) refers to plib035_mflash.o(i.MFLASH_SetCmd) for MFLASH_SetCmd
+    plib035_mflash.o(i.MFLASH_ErasePage) refers to plib035_mflash.o(i.MFLASH_BusyStatus) for MFLASH_BusyStatus
+    plib035_mflash.o(i.MFLASH_ReadData) refers to main.o(i.assert_failed) for assert_failed
+    plib035_mflash.o(i.MFLASH_ReadData) refers to plib035_mflash.o(i.MFLASH_SetAddr) for MFLASH_SetAddr
+    plib035_mflash.o(i.MFLASH_ReadData) refers to plib035_mflash.o(i.MFLASH_SetCmd) for MFLASH_SetCmd
+    plib035_mflash.o(i.MFLASH_ReadData) refers to plib035_mflash.o(i.MFLASH_BusyStatus) for MFLASH_BusyStatus
+    plib035_mflash.o(i.MFLASH_WriteData) refers to main.o(i.assert_failed) for assert_failed
+    plib035_mflash.o(i.MFLASH_WriteData) refers to plib035_mflash.o(i.MFLASH_SetAddr) for MFLASH_SetAddr
+    plib035_mflash.o(i.MFLASH_WriteData) refers to plib035_mflash.o(i.MFLASH_SetCmd) for MFLASH_SetCmd
+    plib035_mflash.o(i.MFLASH_WriteData) refers to plib035_mflash.o(i.MFLASH_BusyStatus) for MFLASH_BusyStatus
+    plib035_mflash.o(i.MFLASH_WriteData) refers to plib035_mflash.o(i.MFLASH_ReadData) for i.MFLASH_ReadData
+    plib035_pwm.o(i.PWM_AQ_ActionAConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_AQ_ActionBConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_AQ_Init) refers to plib035_pwm.o(i.PWM_AQ_ActionAConfig) for PWM_AQ_ActionAConfig
+    plib035_pwm.o(i.PWM_AQ_Init) refers to plib035_pwm.o(i.PWM_AQ_ActionBConfig) for PWM_AQ_ActionBConfig
+    plib035_pwm.o(i.PWM_CMP_CmpADirectLoadCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_CMP_CmpALoadEventConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_CMP_Init) refers to plib035_pwm.o(i.PWM_CMP_CmpALoadEventConfig) for PWM_CMP_CmpALoadEventConfig
+    plib035_pwm.o(i.PWM_CMP_Init) refers to plib035_pwm.o(i.PWM_CMP_CmpADirectLoadCmd) for PWM_CMP_CmpADirectLoadCmd
+    plib035_pwm.o(i.PWM_CMP_Init) refers to plib035_pwm.o(i.PWM_CMP_SetCmpA) for PWM_CMP_SetCmpA
+    plib035_pwm.o(i.PWM_CMP_Init) refers to plib035_pwm.o(i.PWM_CMP_SetCmpB) for PWM_CMP_SetCmpB
+    plib035_pwm.o(i.PWM_CMP_SetCmpA) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_CMP_SetCmpA) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_CMP_SetCmpB) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_CMP_SetCmpB) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_DB_InConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_DB_InConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_DB_Init) refers to plib035_pwm.o(i.PWM_DB_InConfig) for PWM_DB_InConfig
+    plib035_pwm.o(i.PWM_DB_Init) refers to plib035_pwm.o(i.PWM_DB_OutConfig) for PWM_DB_OutConfig
+    plib035_pwm.o(i.PWM_DB_Init) refers to plib035_pwm.o(i.PWM_DB_PolarityConfig) for PWM_DB_PolarityConfig
+    plib035_pwm.o(i.PWM_DB_Init) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_DB_Init) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_DB_OutConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_DB_OutConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_DB_PolarityConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_DB_PolarityConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_DeInit) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_DeInit) refers to plib035_pwm.o(i.RCU_APBRstCmd) for RCU_APBRstCmd
+    plib035_pwm.o(i.PWM_ET_DRQACmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_ET_DRQACmd) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_ET_DRQAEventConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_ET_DRQAEventConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_ET_DRQAPeriodConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_ET_DRQAPeriodConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_ET_DRQBCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_ET_DRQBCmd) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_ET_DRQBEventConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_ET_DRQBEventConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_ET_DRQBPeriodConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_ET_DRQBPeriodConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_ET_Init) refers to plib035_pwm.o(i.PWM_ET_SOCAEventConfig) for PWM_ET_SOCAEventConfig
+    plib035_pwm.o(i.PWM_ET_Init) refers to plib035_pwm.o(i.PWM_ET_SOCAPeriodConfig) for PWM_ET_SOCAPeriodConfig
+    plib035_pwm.o(i.PWM_ET_Init) refers to plib035_pwm.o(i.PWM_ET_SOCACmd) for PWM_ET_SOCACmd
+    plib035_pwm.o(i.PWM_ET_Init) refers to plib035_pwm.o(i.PWM_ET_SOCBEventConfig) for PWM_ET_SOCBEventConfig
+    plib035_pwm.o(i.PWM_ET_Init) refers to plib035_pwm.o(i.PWM_ET_SOCBPeriodConfig) for PWM_ET_SOCBPeriodConfig
+    plib035_pwm.o(i.PWM_ET_Init) refers to plib035_pwm.o(i.PWM_ET_SOCBCmd) for PWM_ET_SOCBCmd
+    plib035_pwm.o(i.PWM_ET_Init) refers to plib035_pwm.o(i.PWM_ET_DRQAEventConfig) for PWM_ET_DRQAEventConfig
+    plib035_pwm.o(i.PWM_ET_Init) refers to plib035_pwm.o(i.PWM_ET_DRQAPeriodConfig) for PWM_ET_DRQAPeriodConfig
+    plib035_pwm.o(i.PWM_ET_Init) refers to plib035_pwm.o(i.PWM_ET_DRQACmd) for PWM_ET_DRQACmd
+    plib035_pwm.o(i.PWM_ET_Init) refers to plib035_pwm.o(i.PWM_ET_DRQBEventConfig) for PWM_ET_DRQBEventConfig
+    plib035_pwm.o(i.PWM_ET_Init) refers to plib035_pwm.o(i.PWM_ET_DRQBPeriodConfig) for PWM_ET_DRQBPeriodConfig
+    plib035_pwm.o(i.PWM_ET_Init) refers to plib035_pwm.o(i.PWM_ET_DRQBCmd) for PWM_ET_DRQBCmd
+    plib035_pwm.o(i.PWM_ET_SOCACmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_ET_SOCACmd) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_ET_SOCAEventConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_ET_SOCAEventConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_ET_SOCAPeriodConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_ET_SOCAPeriodConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_ET_SOCBCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_ET_SOCBCmd) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_ET_SOCBEventConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_ET_SOCBEventConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_ET_SOCBPeriodConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_ET_SOCBPeriodConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_HD_ActionAConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_HD_ActionAConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_HD_ActionBConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_HD_ActionBConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_HD_CycleCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_HD_CycleCmd) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_HD_Init) refers to plib035_pwm.o(i.PWM_HD_ActionAConfig) for PWM_HD_ActionAConfig
+    plib035_pwm.o(i.PWM_HD_Init) refers to plib035_pwm.o(i.PWM_HD_ActionBConfig) for PWM_HD_ActionBConfig
+    plib035_pwm.o(i.PWM_HD_Init) refers to plib035_pwm.o(i.PWM_HD_SourceCmd) for PWM_HD_SourceCmd
+    plib035_pwm.o(i.PWM_HD_Init) refers to plib035_pwm.o(i.PWM_HD_CycleCmd) for PWM_HD_CycleCmd
+    plib035_pwm.o(i.PWM_HD_Init) refers to plib035_pwm.o(i.PWM_HD_OneShotCmd) for PWM_HD_OneShotCmd
+    plib035_pwm.o(i.PWM_HD_OneShotCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_HD_OneShotCmd) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_HD_SourceCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_HD_SourceCmd) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_TB_ClkDivConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_TB_HaltConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_TB_HaltConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_TB_Init) refers to plib035_pwm.o(i.PWM_TB_HaltConfig) for PWM_TB_HaltConfig
+    plib035_pwm.o(i.PWM_TB_Init) refers to plib035_pwm.o(i.PWM_TB_PhaseSyncCmd) for PWM_TB_PhaseSyncCmd
+    plib035_pwm.o(i.PWM_TB_Init) refers to plib035_pwm.o(i.PWM_TB_PhaseSyncDirConfig) for PWM_TB_PhaseSyncDirConfig
+    plib035_pwm.o(i.PWM_TB_Init) refers to plib035_pwm.o(i.PWM_TB_ClkDivConfig) for PWM_TB_ClkDivConfig
+    plib035_pwm.o(i.PWM_TB_Init) refers to plib035_pwm.o(i.PWM_TB_SyncOutConfig) for PWM_TB_SyncOutConfig
+    plib035_pwm.o(i.PWM_TB_Init) refers to plib035_pwm.o(i.PWM_TB_PeriodDirectLoadCmd) for PWM_TB_PeriodDirectLoadCmd
+    plib035_pwm.o(i.PWM_TB_Init) refers to plib035_pwm.o(i.PWM_TB_ModeConfig) for PWM_TB_ModeConfig
+    plib035_pwm.o(i.PWM_TB_Init) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_TB_ModeConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_TB_ModeConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_TB_PeriodDirectLoadCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_TB_PeriodDirectLoadCmd) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_TB_PhaseSyncCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_TB_PhaseSyncCmd) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_TB_PhaseSyncDirConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_TB_PhaseSyncDirConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_TB_SyncOutConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_TB_SyncOutConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_TZ_ActionAConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_TZ_ActionAConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_TZ_ActionBConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_TZ_ActionBConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_TZ_CycleCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_TZ_CycleCmd) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_TZ_Init) refers to plib035_pwm.o(i.PWM_TZ_ActionAConfig) for PWM_TZ_ActionAConfig
+    plib035_pwm.o(i.PWM_TZ_Init) refers to plib035_pwm.o(i.PWM_TZ_ActionBConfig) for PWM_TZ_ActionBConfig
+    plib035_pwm.o(i.PWM_TZ_Init) refers to plib035_pwm.o(i.PWM_TZ_CycleCmd) for PWM_TZ_CycleCmd
+    plib035_pwm.o(i.PWM_TZ_Init) refers to plib035_pwm.o(i.PWM_TZ_OneShotCmd) for PWM_TZ_OneShotCmd
+    plib035_pwm.o(i.PWM_TZ_OneShotCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_TZ_OneShotCmd) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.RCU_APBRstCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_qep.o(i.QEP_CAP_DivConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_qep.o(i.QEP_CAP_DivConfig) refers to plib035_qep.o(i.QEP_PC_Init) for i.QEP_PC_Init
+    plib035_qep.o(i.QEP_CAP_Init) refers to main.o(i.assert_failed) for assert_failed
+    plib035_qep.o(i.QEP_CAP_Init) refers to plib035_qep.o(i.QEP_CAP_DivConfig) for QEP_CAP_DivConfig
+    plib035_qep.o(i.QEP_CAP_Init) refers to plib035_qep.o(i.QEP_PC_Init) for i.QEP_PC_Init
+    plib035_qep.o(i.QEP_CMP_Init) refers to main.o(i.assert_failed) for assert_failed
+    plib035_qep.o(i.QEP_CMP_Init) refers to plib035_qep.o(i.QEP_PC_Init) for i.QEP_PC_Init
+    plib035_qep.o(i.QEP_DeInit) refers to plib035_qep.o(i.RCU_APBRstCmd) for RCU_APBRstCmd
+    plib035_qep.o(i.QEP_PC_Init) refers to main.o(i.assert_failed) for assert_failed
+    plib035_qep.o(i.RCU_APBRstCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_rcu.o(i.MFLASH_LatencyConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_rcu.o(i.RCU_GetADCClkFreq) refers to plib035_rcu.o(i.getPeriphClkFreq) for getPeriphClkFreq
+    plib035_rcu.o(i.RCU_GetClkOutFreq) refers to plib035_rcu.o(i.getSysPeriphClkFreq) for getSysPeriphClkFreq
+    plib035_rcu.o(i.RCU_GetPLLDivClkFreq) refers to plib035_rcu.o(i.RCU_GetPLLClkFreq) for RCU_GetPLLClkFreq
+    plib035_rcu.o(i.RCU_GetSPIClkFreq) refers to plib035_rcu.o(i.getPeriphClkFreq) for getPeriphClkFreq
+    plib035_rcu.o(i.RCU_GetSysClkFreq) refers to plib035_rcu.o(i.getSysClkFreq) for getSysClkFreq
+    plib035_rcu.o(i.RCU_GetTraceClkFreq) refers to plib035_rcu.o(i.getSysPeriphClkFreq) for getSysPeriphClkFreq
+    plib035_rcu.o(i.RCU_GetUARTClkFreq) refers to plib035_rcu.o(i.getPeriphClkFreq) for getPeriphClkFreq
+    plib035_rcu.o(i.RCU_GetWDTClkFreq) refers to plib035_rcu.o(i.getSysPeriphClkFreq) for getSysPeriphClkFreq
+    plib035_rcu.o(i.RCU_PLL_AutoConfig) refers to plib035_rcu.o(i.RCU_PLL_StructInit) for RCU_PLL_StructInit
+    plib035_rcu.o(i.RCU_PLL_AutoConfig) refers to plib035_rcu.o(i.RCU_PLL_Init) for RCU_PLL_Init
+    plib035_rcu.o(i.RCU_PLL_AutoConfig) refers to plib035_rcu.o(i.MFLASH_LatencyConfig) for MFLASH_LatencyConfig
+    plib035_rcu.o(i.RCU_PLL_AutoConfig) refers to plib035_rcu.o(i.RCU_SysClkChangeCmd) for RCU_SysClkChangeCmd
+    plib035_rcu.o(i.RCU_PLL_DeInit) refers to plib035_rcu.o(i.RCU_PLL_OutCmd) for RCU_PLL_OutCmd
+    plib035_rcu.o(i.RCU_PLL_Init) refers to main.o(i.assert_failed) for assert_failed
+    plib035_rcu.o(i.RCU_PLL_Init) refers to plib035_rcu.o(i.RCU_PLL_OutCmd) for RCU_PLL_OutCmd
+    plib035_rcu.o(i.RCU_PLL_OutCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_rcu.o(i.RCU_SysClkChangeCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_rcu.o(i.getPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetOSEClkFreq) for RCU_GetOSEClkFreq
+    plib035_rcu.o(i.getPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetPLLClkFreq) for RCU_GetPLLClkFreq
+    plib035_rcu.o(i.getPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetPLLDivClkFreq) for RCU_GetPLLDivClkFreq
+    plib035_rcu.o(i.getPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetOSIClkFreq) for RCU_GetOSIClkFreq
+    plib035_rcu.o(i.getSysClkFreq) refers to plib035_rcu.o(i.RCU_GetOSIClkFreq) for RCU_GetOSIClkFreq
+    plib035_rcu.o(i.getSysClkFreq) refers to plib035_rcu.o(i.RCU_GetOSEClkFreq) for RCU_GetOSEClkFreq
+    plib035_rcu.o(i.getSysClkFreq) refers to plib035_rcu.o(i.RCU_GetPLLClkFreq) for RCU_GetPLLClkFreq
+    plib035_rcu.o(i.getSysClkFreq) refers to plib035_rcu.o(i.RCU_GetPLLDivClkFreq) for RCU_GetPLLDivClkFreq
+    plib035_rcu.o(i.getSysPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetOSEClkFreq) for RCU_GetOSEClkFreq
+    plib035_rcu.o(i.getSysPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetPLLClkFreq) for RCU_GetPLLClkFreq
+    plib035_rcu.o(i.getSysPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetPLLDivClkFreq) for RCU_GetPLLDivClkFreq
+    plib035_rcu.o(i.getSysPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetOSIClkFreq) for RCU_GetOSIClkFreq
+    plib035_spi.o(i.RCU_SPIRstCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_spi.o(i.SPI_DataWidthConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_spi.o(i.SPI_DataWidthConfig) refers to plib035_spi.o(i.SPI_Init) for i.SPI_Init
+    plib035_spi.o(i.SPI_DeInit) refers to plib035_spi.o(i.RCU_SPIRstCmd) for RCU_SPIRstCmd
+    plib035_spi.o(i.SPI_Init) refers to plib035_spi.o(i.SPI_SCKDivConfig) for SPI_SCKDivConfig
+    plib035_spi.o(i.SPI_Init) refers to plib035_spi.o(i.SPI_DataWidthConfig) for SPI_DataWidthConfig
+    plib035_spi.o(i.SPI_Init) refers to main.o(i.assert_failed) for assert_failed
+    plib035_spi.o(i.SPI_SCKDivConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_spi.o(i.SPI_SCKDivConfig) refers to plib035_spi.o(i.SPI_Init) for i.SPI_Init
+    plib035_tmr.o(i.TMR_FreqConfig) refers to plib035_tmr.o(i.TMR_SetLoad) for TMR_SetLoad
+    plib035_tmr.o(i.TMR_PeriodConfig) refers to plib035_tmr.o(i.TMR_SetLoad) for TMR_SetLoad
+    plib035_tmr.o(i.TMR_SetLoad) refers to main.o(i.assert_failed) for assert_failed
+    plib035_uart.o(i.RCU_UARTRstCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_uart.o(i.UART_AutoBaudConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_uart.o(i.UART_AutoBaudConfig) refers to plib035_rcu.o(i.RCU_GetUARTClkFreq) for RCU_GetUARTClkFreq
+    plib035_uart.o(i.UART_AutoBaudConfig) refers to plib035_uart.o(i.UART_BaudDivConfig) for UART_BaudDivConfig
+    plib035_uart.o(i.UART_BaudDivConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_uart.o(i.UART_BaudDivConfig) refers to plib035_uart.o(i.UART_DataWidthConfig) for i.UART_DataWidthConfig
+    plib035_uart.o(i.UART_DataWidthConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_uart.o(i.UART_DeInit) refers to main.o(i.assert_failed) for assert_failed
+    plib035_uart.o(i.UART_DeInit) refers to plib035_uart.o(i.RCU_UARTRstCmd) for RCU_UARTRstCmd
+    plib035_uart.o(i.UART_FIFOCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_uart.o(i.UART_FIFOCmd) refers to plib035_uart.o(i.UART_DataWidthConfig) for i.UART_DataWidthConfig
+    plib035_uart.o(i.UART_Init) refers to plib035_uart.o(i.UART_AutoBaudConfig) for UART_AutoBaudConfig
+    plib035_uart.o(i.UART_Init) refers to plib035_uart.o(i.UART_DataWidthConfig) for UART_DataWidthConfig
+    plib035_uart.o(i.UART_Init) refers to plib035_uart.o(i.UART_StopBitConfig) for UART_StopBitConfig
+    plib035_uart.o(i.UART_Init) refers to plib035_uart.o(i.UART_ParityBitConfig) for UART_ParityBitConfig
+    plib035_uart.o(i.UART_Init) refers to plib035_uart.o(i.UART_FIFOCmd) for UART_FIFOCmd
+    plib035_uart.o(i.UART_Init) refers to plib035_uart.o(i.UART_TxCmd) for UART_TxCmd
+    plib035_uart.o(i.UART_Init) refers to plib035_uart.o(i.UART_RxCmd) for UART_RxCmd
+    plib035_uart.o(i.UART_ParityBitConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_uart.o(i.UART_ParityBitConfig) refers to plib035_uart.o(i.UART_DataWidthConfig) for i.UART_DataWidthConfig
+    plib035_uart.o(i.UART_RxCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_uart.o(i.UART_RxCmd) refers to plib035_uart.o(i.UART_DataWidthConfig) for i.UART_DataWidthConfig
+    plib035_uart.o(i.UART_StopBitConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_uart.o(i.UART_StopBitConfig) refers to plib035_uart.o(i.UART_DataWidthConfig) for i.UART_DataWidthConfig
+    plib035_uart.o(i.UART_TxCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_uart.o(i.UART_TxCmd) refers to plib035_uart.o(i.UART_DataWidthConfig) for i.UART_DataWidthConfig
+    retarget.o(.rev16_text) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi
+    retarget.o(.revsh_text) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi
+    retarget.o(.rrx_text) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi
+    retarget.o(i._sys_exit) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi
+    retarget.o(i._ttywrch) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi
+    retarget.o(i._ttywrch) refers to retarget_conf.o(i.retarget_put_char) for retarget_put_char
+    retarget.o(i.ferror) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi
+    retarget.o(i.fgetc) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi
+    retarget.o(i.fgetc) refers to retarget_conf.o(i.retarget_get_char) for retarget_get_char
+    retarget.o(i.fputc) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi
+    retarget.o(i.fputc) refers to retarget_conf.o(i.retarget_put_char) for retarget_put_char
+    retarget.o(.data) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi
+    retarget_conf.o(i.retarget_init) refers to system_k1921vk035.o(.data) for SystemCoreClock
+    llsdiv.o(.text) refers to lludivv7m.o(.text) for __aeabi_uldivmod
+    __2printf.o(.text) refers to _printf_char_file.o(.text) for _printf_char_file
+    __2printf.o(.text) refers to retarget.o(.data) for __stdout
+    noretval__2printf.o(.text) refers to _printf_char_file.o(.text) for _printf_char_file
+    noretval__2printf.o(.text) refers to retarget.o(.data) for __stdout
+    __printf.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+    _printf_str.o(.text) refers (Special) to _printf_char.o(.text) for _printf_cs_common
+    _printf_str.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding
+    _printf_str.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding
+    _printf_dec.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common
+    __printf_flags.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+    __printf_flags.o(.text) refers to __printf_flags.o(.constdata) for .constdata
+    __printf_ss.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+    __printf_flags_ss.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+    __printf_flags_ss.o(.text) refers to __printf_flags_ss.o(.constdata) for .constdata
+    __printf_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit
+    __printf_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+    __printf_flags_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit
+    __printf_flags_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+    __printf_flags_wp.o(.text) refers to __printf_flags_wp.o(.constdata) for .constdata
+    __printf_ss_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit
+    __printf_ss_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+    __printf_flags_ss_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit
+    __printf_flags_ss_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+    __printf_flags_ss_wp.o(.text) refers to __printf_flags_ss_wp.o(.constdata) for .constdata
+    _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) refers (Weak) to _printf_char.o(.text) for _printf_string
+    _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) refers (Weak) to _printf_dec.o(.text) for _printf_int_dec
+    _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) refers (Special) to _printf_percent_end.o(.ARM.Collect$$_printf_percent$$00000017) for _printf_percent_end
+    rand.o(.emb_text) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000D) for __rt_lib_init_rand_2
+    rand.o(.emb_text) refers to rand.o(.text) for _rand_init
+    rand.o(.emb_text) refers to rand.o(.bss) for _random_number_data
+    rand.o(.text) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000D) for __rt_lib_init_rand_2
+    rand.o(.text) refers to rand.o(.bss) for .bss
+    rand.o(.bss) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000D) for __rt_lib_init_rand_2
+    rt_memcpy_v6.o(.text) refers to rt_memcpy_w.o(.text) for __aeabi_memcpy4
+    __main.o(!!!main) refers to __rtentry.o(.ARM.Collect$$rtentry$$00000000) for __rt_entry
+    ddiv.o(x$fpl$drdiv) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    ddiv.o(x$fpl$drdiv) refers to ddiv.o(x$fpl$ddiv) for ddiv_entry
+    ddiv.o(x$fpl$ddiv) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    ddiv.o(x$fpl$ddiv) refers to dretinf.o(x$fpl$dretinf) for __fpl_dretinf
+    ddiv.o(x$fpl$ddiv) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf
+    dfix.o(x$fpl$dfix) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    dfix.o(x$fpl$dfix) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf
+    dfix.o(x$fpl$dfixr) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    dfix.o(x$fpl$dfixr) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf
+    dflt_clz.o(x$fpl$dfltu) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    dflt_clz.o(x$fpl$dflt) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    dflt_clz.o(x$fpl$dfltn) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    ffltll_clz.o(x$fpl$ffltll) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    cosf.o(i.__hardfp_cosf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    cosf.o(i.__hardfp_cosf) refers to rredf.o(i.__mathlib_rredf2) for __mathlib_rredf2
+    cosf.o(i.__hardfp_cosf) refers to _rserrno.o(.text) for __set_errno
+    cosf.o(i.__hardfp_cosf) refers to funder.o(i.__mathlib_flt_invalid) for __mathlib_flt_invalid
+    cosf.o(i.__hardfp_cosf) refers to funder.o(i.__mathlib_flt_infnan) for __mathlib_flt_infnan
+    cosf.o(i.__softfp_cosf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    cosf.o(i.__softfp_cosf) refers to cosf.o(i.__hardfp_cosf) for __hardfp_cosf
+    cosf.o(i.cosf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    cosf.o(i.cosf) refers to cosf.o(i.__hardfp_cosf) for __hardfp_cosf
+    cosf_x.o(i.____hardfp_cosf$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    cosf_x.o(i.____hardfp_cosf$lsc) refers to rredf.o(i.__mathlib_rredf2) for __mathlib_rredf2
+    cosf_x.o(i.____hardfp_cosf$lsc) refers to _rserrno.o(.text) for __set_errno
+    cosf_x.o(i.____hardfp_cosf$lsc) refers to funder.o(i.__mathlib_flt_infnan) for __mathlib_flt_infnan
+    cosf_x.o(i.____softfp_cosf$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    cosf_x.o(i.____softfp_cosf$lsc) refers to cosf_x.o(i.____hardfp_cosf$lsc) for ____hardfp_cosf$lsc
+    cosf_x.o(i.__cosf$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    cosf_x.o(i.__cosf$lsc) refers to cosf_x.o(i.____hardfp_cosf$lsc) for ____hardfp_cosf$lsc
+    sinf.o(i.__hardfp_sinf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    sinf.o(i.__hardfp_sinf) refers to rredf.o(i.__mathlib_rredf2) for __mathlib_rredf2
+    sinf.o(i.__hardfp_sinf) refers to fpclassifyf.o(i.__ARM_fpclassifyf) for __ARM_fpclassifyf
+    sinf.o(i.__hardfp_sinf) refers to funder.o(i.__mathlib_flt_underflow) for __mathlib_flt_underflow
+    sinf.o(i.__hardfp_sinf) refers to _rserrno.o(.text) for __set_errno
+    sinf.o(i.__hardfp_sinf) refers to funder.o(i.__mathlib_flt_invalid) for __mathlib_flt_invalid
+    sinf.o(i.__hardfp_sinf) refers to funder.o(i.__mathlib_flt_infnan) for __mathlib_flt_infnan
+    sinf.o(i.__softfp_sinf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    sinf.o(i.__softfp_sinf) refers to sinf.o(i.__hardfp_sinf) for __hardfp_sinf
+    sinf.o(i.sinf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    sinf.o(i.sinf) refers to sinf.o(i.__hardfp_sinf) for __hardfp_sinf
+    sinf_x.o(i.____hardfp_sinf$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    sinf_x.o(i.____hardfp_sinf$lsc) refers to rredf.o(i.__mathlib_rredf2) for __mathlib_rredf2
+    sinf_x.o(i.____hardfp_sinf$lsc) refers to _rserrno.o(.text) for __set_errno
+    sinf_x.o(i.____hardfp_sinf$lsc) refers to funder.o(i.__mathlib_flt_infnan) for __mathlib_flt_infnan
+    sinf_x.o(i.____softfp_sinf$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    sinf_x.o(i.____softfp_sinf$lsc) refers to sinf_x.o(i.____hardfp_sinf$lsc) for ____hardfp_sinf$lsc
+    sinf_x.o(i.__sinf$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    sinf_x.o(i.__sinf$lsc) refers to sinf_x.o(i.____hardfp_sinf$lsc) for ____hardfp_sinf$lsc
+    __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for __rt_entry_li
+    __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for __rt_entry_main
+    __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) for __rt_entry_postli_1
+    __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000009) for __rt_entry_postsh_1
+    __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000002) for __rt_entry_presh_1
+    __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for __rt_entry_sh
+    _rserrno.o(.text) refers to rt_errno_addr_intlibspace.o(.text) for __aeabi_errno_addr
+    _printf_intcommon.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding
+    _printf_intcommon.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding
+    _printf_intcommon.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding
+    _printf_char.o(.text) refers (Weak) to _printf_str.o(.text) for _printf_str
+    _printf_char_file.o(.text) refers to _printf_char_common.o(.text) for _printf_char_common
+    _printf_char_file.o(.text) refers to retarget.o(i.ferror) for ferror
+    _printf_char_file.o(.text) refers to retarget.o(i.fputc) for fputc
+    libinit2.o(.ARM.Collect$$libinit$$00000001) refers to fpinit.o(x$fpl$fpinit) for _fp_init
+    libinit2.o(.ARM.Collect$$libinit$$0000000D) refers (Weak) to rand.o(.text) for _rand_init
+    libinit2.o(.ARM.Collect$$libinit$$00000010) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
+    libinit2.o(.ARM.Collect$$libinit$$00000012) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
+    libinit2.o(.ARM.Collect$$libinit$$00000014) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
+    libinit2.o(.ARM.Collect$$libinit$$00000016) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
+    libinit2.o(.ARM.Collect$$libinit$$00000018) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
+    libinit2.o(.ARM.Collect$$libinit$$00000026) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer
+    libinit2.o(.ARM.Collect$$libinit$$00000027) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer
+    dnaninf.o(x$fpl$dnaninf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    dretinf.o(x$fpl$dretinf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    fpclassifyf.o(i.__ARM_fpclassifyf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    rredf.o(i.__mathlib_rredf2) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    rredf.o(i.__mathlib_rredf2) refers to rredf.o(.constdata) for .constdata
+    rredf.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    __rtentry2.o(.ARM.Collect$$rtentry$$00000008) refers to boardinit2.o(.text) for _platform_post_stackheap_init
+    __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) refers to libinit.o(.ARM.Collect$$libinit$$00000000) for __rt_lib_init
+    __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) refers to boardinit3.o(.text) for _platform_post_lib_init
+    __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to main.o(i.main) for main
+    __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to exit.o(.text) for exit
+    __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000001) for .ARM.Collect$$rtentry$$00000001
+    __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000008) for .ARM.Collect$$rtentry$$00000008
+    __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for .ARM.Collect$$rtentry$$0000000A
+    __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) for .ARM.Collect$$rtentry$$0000000B
+    __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for .ARM.Collect$$rtentry$$0000000D
+    __rtentry4.o(.ARM.Collect$$rtentry$$00000004) refers to sys_stackheap_outer.o(.text) for __user_setup_stackheap
+    __rtentry4.o(.ARM.exidx) refers to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for .ARM.Collect$$rtentry$$00000004
+    aeabi_ldiv0_sigfpe.o(.text) refers to rt_div0.o(.text) for __rt_div0
+    rt_errno_addr.o(.text) refers to rt_errno_addr.o(.bss) for __aeabi_errno_addr_data
+    rt_errno_addr_intlibspace.o(.text) refers to libspace.o(.bss) for __libspace_start
+    _printf_char_common.o(.text) refers to __printf_wp.o(.text) for __printf
+    argv_veneer.o(.emb_text) refers to no_argv.o(.text) for __ARM_get_argv
+    libspace.o(.text) refers to libspace.o(.bss) for __libspace_start
+    sys_stackheap_outer.o(.text) refers to libspace.o(.text) for __user_perproc_libspace
+    sys_stackheap_outer.o(.text) refers to startup_k1921vk035.o(.text) for __user_initial_stackheap
+    rt_div0.o(.text) refers to defsig_fpe_outer.o(.text) for __rt_SIGFPE
+    exit.o(.text) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for __rt_exit
+    _get_argv_nomalloc.o(.text) refers (Special) to hrguard.o(.text) for __heap_region$guard
+    _get_argv_nomalloc.o(.text) refers to defsig_rtmem_outer.o(.text) for __rt_SIGRTMEM
+    _get_argv_nomalloc.o(.text) refers to sys_command.o(.text) for _sys_command_string
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002E) for __rt_lib_init_alloca_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002C) for __rt_lib_init_argv_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001B) for __rt_lib_init_atexit_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000021) for __rt_lib_init_clock_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000032) for __rt_lib_init_cpp_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000030) for __rt_lib_init_exceptions_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000001) for __rt_lib_init_fp_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001F) for __rt_lib_init_fp_trap_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000023) for __rt_lib_init_getenv_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000A) for __rt_lib_init_heap_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000011) for __rt_lib_init_lc_collate_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000013) for __rt_lib_init_lc_ctype_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000015) for __rt_lib_init_lc_monetary_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000017) for __rt_lib_init_lc_numeric_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000019) for __rt_lib_init_lc_time_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000004) for __rt_lib_init_preinit_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000E) for __rt_lib_init_rand_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000033) for __rt_lib_init_return
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001D) for __rt_lib_init_signal_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000025) for __rt_lib_init_stdio_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000C) for __rt_lib_init_user_alloc_1
+    sys_command.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting
+    sys_command.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function
+    rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit
+    rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls
+    rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1
+    rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit
+    rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls
+    rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1
+    rtexit.o(.ARM.exidx) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for .ARM.Collect$$rtexit$$00000000
+    defsig_fpe_outer.o(.text) refers to defsig_fpe_inner.o(.text) for __rt_SIGFPE_inner
+    defsig_fpe_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit
+    defsig_fpe_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise
+    defsig_rtmem_outer.o(.text) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner
+    defsig_rtmem_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit
+    defsig_rtmem_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise
+    rtexit2.o(.ARM.Collect$$rtexit$$00000003) refers to libshutdown.o(.ARM.Collect$$libshutdown$$00000000) for __rt_lib_shutdown
+    rtexit2.o(.ARM.Collect$$rtexit$$00000004) refers to retarget.o(i._sys_exit) for _sys_exit
+    rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000001) for .ARM.Collect$$rtexit$$00000001
+    rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for .ARM.Collect$$rtexit$$00000003
+    rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for .ARM.Collect$$rtexit$$00000004
+    rt_raise.o(.text) refers to __raise.o(.text) for __raise
+    rt_raise.o(.text) refers to retarget.o(i._sys_exit) for _sys_exit
+    defsig_exit.o(.text) refers to retarget.o(i._sys_exit) for _sys_exit
+    defsig_fpe_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+    defsig_rtmem_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+    __raise.o(.text) refers to defsig.o(CL$$defsig) for __default_signal_handler
+    defsig_general.o(.text) refers to retarget.o(i._ttywrch) for _ttywrch
+    libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) for __rt_lib_shutdown_cpp_1
+    libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) for __rt_lib_shutdown_fini_1
+    libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000009) for __rt_lib_shutdown_fp_trap_1
+    libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000011) for __rt_lib_shutdown_heap_1
+    libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000012) for __rt_lib_shutdown_return
+    libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) for __rt_lib_shutdown_signal_1
+    libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000006) for __rt_lib_shutdown_stdio_1
+    libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000E) for __rt_lib_shutdown_user_alloc_1
+    defsig.o(CL$$defsig) refers to defsig_fpe_inner.o(.text) for __rt_SIGFPE_inner
+    defsig.o(CL$$defsig) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner
+    defsig_abrt_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+    defsig_rtred_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+    defsig_stak_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+    defsig_pvfn_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+    defsig_cppl_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+    defsig_segv_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+    defsig_other.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+
+
+==============================================================================
+
+Removing Unused input sections from the image.
+
+    Removing main.o(.rev16_text), (4 bytes).
+    Removing main.o(.revsh_text), (4 bytes).
+    Removing main.o(.rrx_text), (6 bytes).
+    Removing main.o(i.GenOptimizer_Init), (416 bytes).
+    Removing main.o(i.GenOptimizer_Step), (980 bytes).
+    Removing main.o(i.cmp_idx), (104 bytes).
+    Removing main.o(.bss), (512 bytes).
+    Removing main.o(.data), (396 bytes).
+    Removing gpio.o(.rev16_text), (4 bytes).
+    Removing gpio.o(.revsh_text), (4 bytes).
+    Removing gpio.o(.rrx_text), (6 bytes).
+    Removing gpio.o(i.GenOptimizer_Init), (416 bytes).
+    Removing gpio.o(i.GenOptimizer_Step), (980 bytes).
+    Removing gpio.o(i.cmp_idx), (104 bytes).
+    Removing gpio.o(.bss), (512 bytes).
+    Removing rcu.o(.rev16_text), (4 bytes).
+    Removing rcu.o(.revsh_text), (4 bytes).
+    Removing rcu.o(.rrx_text), (6 bytes).
+    Removing rcu.o(i.GenOptimizer_Init), (416 bytes).
+    Removing rcu.o(i.GenOptimizer_Step), (980 bytes).
+    Removing rcu.o(i.cmp_idx), (104 bytes).
+    Removing rcu.o(.bss), (512 bytes).
+    Removing vk035_it.o(.rev16_text), (4 bytes).
+    Removing vk035_it.o(.revsh_text), (4 bytes).
+    Removing vk035_it.o(.rrx_text), (6 bytes).
+    Removing vk035_it.o(i.GenOptimizer_Init), (416 bytes).
+    Removing vk035_it.o(i.GenOptimizer_Step), (980 bytes).
+    Removing vk035_it.o(i.cmp_idx), (104 bytes).
+    Removing vk035_it.o(.bss), (512 bytes).
+    Removing vk035_it.o(.data), (8 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_AllocDownBuffer), (200 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_AllocUpBuffer), (200 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_ConfigDownBuffer), (120 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_ConfigUpBuffer), (120 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_GetAvailWriteSpace), (28 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_GetBytesInBuffer), (68 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_GetKey), (32 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_HasData), (28 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_HasDataUp), (28 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_HasKey), (48 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_Init), (8 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_PutChar), (128 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_PutCharSkip), (116 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_PutCharSkipNoLock), (56 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_Read), (56 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_ReadNoLock), (172 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_ReadUpBuffer), (56 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_ReadUpBufferNoLock), (172 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_SetFlagsDownBuffer), (96 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_SetFlagsUpBuffer), (96 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_SetNameDownBuffer), (96 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_SetNameUpBuffer), (96 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_SetTerminal), (160 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_TerminalOut), (260 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_WaitKey), (14 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_Write), (76 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_WriteDownBuffer), (76 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_WriteDownBufferNoLock), (132 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_WriteNoLock), (132 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_WriteSkipNoLock), (160 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_WriteString), (26 bytes).
+    Removing segger_rtt.o(i.SEGGER_RTT_WriteWithOverwriteNoLock), (180 bytes).
+    Removing segger_rtt.o(i._DoInit), (116 bytes).
+    Removing segger_rtt.o(i._GetAvailWriteSpace), (28 bytes).
+    Removing segger_rtt.o(i._PostTerminalSwitch), (36 bytes).
+    Removing segger_rtt.o(i._WriteBlocking), (118 bytes).
+    Removing segger_rtt.o(i._WriteNoCheck), (88 bytes).
+    Removing segger_rtt.o(.bss), (4280 bytes).
+    Removing segger_rtt.o(.constdata), (33 bytes).
+    Removing segger_rtt.o(.data), (1 bytes).
+    Removing segger_rtt_printf.o(i.SEGGER_RTT_printf), (34 bytes).
+    Removing segger_rtt_printf.o(i.SEGGER_RTT_vprintf), (544 bytes).
+    Removing segger_rtt_printf.o(i._PrintInt), (236 bytes).
+    Removing segger_rtt_printf.o(i._PrintUnsigned), (236 bytes).
+    Removing segger_rtt_printf.o(i._StoreChar), (68 bytes).
+    Removing segger_rtt_printf.o(.constdata), (16 bytes).
+    Removing filters.o(.rev16_text), (4 bytes).
+    Removing filters.o(.revsh_text), (4 bytes).
+    Removing filters.o(.rrx_text), (6 bytes).
+    Removing filters.o(i.FilterAverageInt_Init), (72 bytes).
+    Removing filters.o(i.FilterAverageInt_Process), (94 bytes).
+    Removing filters.o(i.FilterAverage_Init), (76 bytes).
+    Removing filters.o(i.FilterAverage_Process), (104 bytes).
+    Removing filters.o(i.FilterBandPassDerivative_Init), (308 bytes).
+    Removing filters.o(i.FilterBandPassDerivative_Process), (126 bytes).
+    Removing filters.o(i.FilterExpInt_Init), (48 bytes).
+    Removing filters.o(i.FilterExpInt_Process), (88 bytes).
+    Removing filters.o(i.FilterExp_Init), (60 bytes).
+    Removing filters.o(i.FilterExp_Process), (78 bytes).
+    Removing filters.o(i.FilterLUTInt_Init), (64 bytes).
+    Removing filters.o(i.FilterLUTInt_Process), (318 bytes).
+    Removing filters.o(i.FilterLUT_Init), (64 bytes).
+    Removing filters.o(i.FilterLUT_Process), (248 bytes).
+    Removing filters.o(i.FilterMedianInt_Init), (88 bytes).
+    Removing filters.o(i.FilterMedianInt_Process), (218 bytes).
+    Removing filters.o(i.FilterMedian_Init), (84 bytes).
+    Removing filters.o(i.FilterMedian_Process), (124 bytes).
+    Removing filters.o(i.FilterPolyInt_Init), (80 bytes).
+    Removing filters.o(i.FilterPolyInt_Process), (160 bytes).
+    Removing filters.o(i.FilterPoly_Init), (72 bytes).
+    Removing filters.o(i.FilterPoly_Process), (84 bytes).
+    Removing filters.o(i.FilterRMSInt_Init), (96 bytes).
+    Removing filters.o(i.FilterRMSInt_Process), (286 bytes).
+    Removing filters.o(i.FilterRMS_Init), (104 bytes).
+    Removing filters.o(i.FilterRMS_Process), (224 bytes).
+    Removing filters.o(i.Filter_float_compare), (52 bytes).
+    Removing filters.o(.data), (4 bytes).
+    Removing system_k1921vk035.o(.rev16_text), (4 bytes).
+    Removing system_k1921vk035.o(.revsh_text), (4 bytes).
+    Removing system_k1921vk035.o(.rrx_text), (6 bytes).
+    Removing plib035_adc.o(.rev16_text), (4 bytes).
+    Removing plib035_adc.o(.revsh_text), (4 bytes).
+    Removing plib035_adc.o(.rrx_text), (6 bytes).
+    Removing plib035_adc.o(i.ADC_DC_ChannelConfig), (92 bytes).
+    Removing plib035_adc.o(i.ADC_DC_Config), (124 bytes).
+    Removing plib035_adc.o(i.ADC_DC_Init), (58 bytes).
+    Removing plib035_adc.o(i.ADC_DC_OutputCmd), (84 bytes).
+    Removing plib035_adc.o(i.ADC_DC_SetThresholdHigh), (88 bytes).
+    Removing plib035_adc.o(i.ADC_DC_SetThresholdLow), (88 bytes).
+    Removing plib035_adc.o(i.ADC_DC_SourceConfig), (84 bytes).
+    Removing plib035_adc.o(i.ADC_DC_StructInit), (18 bytes).
+    Removing plib035_adc.o(i.ADC_DeInit), (16 bytes).
+    Removing plib035_adc.o(i.ADC_SEQ_DCEnableCmd), (124 bytes).
+    Removing plib035_adc.o(i.ADC_SEQ_DMACmd), (88 bytes).
+    Removing plib035_adc.o(i.ADC_SEQ_DMAConfig), (108 bytes).
+    Removing plib035_adc.o(i.ADC_SEQ_Init), (224 bytes).
+    Removing plib035_adc.o(i.ADC_SEQ_ReqAverageCmd), (88 bytes).
+    Removing plib035_adc.o(i.ADC_SEQ_ReqAverageConfig), (108 bytes).
+    Removing plib035_adc.o(i.ADC_SEQ_ReqConfig), (132 bytes).
+    Removing plib035_adc.o(i.ADC_SEQ_ReqMaxConfig), (96 bytes).
+    Removing plib035_adc.o(i.ADC_SEQ_RestartAverageCmd), (88 bytes).
+    Removing plib035_adc.o(i.ADC_SEQ_RestartConfig), (88 bytes).
+    Removing plib035_adc.o(i.ADC_SEQ_SetRestartTimer), (88 bytes).
+    Removing plib035_adc.o(i.ADC_SEQ_StructInit), (68 bytes).
+    Removing plib035_adc.o(i.ADC_SEQ_SwStartEnCmd), (72 bytes).
+    Removing plib035_adc.o(i.RCU_ADCRstCmd), (84 bytes).
+    Removing plib035_can.o(.rev16_text), (4 bytes).
+    Removing plib035_can.o(.revsh_text), (4 bytes).
+    Removing plib035_can.o(.rrx_text), (6 bytes).
+    Removing plib035_dma.o(.rev16_text), (4 bytes).
+    Removing plib035_dma.o(.revsh_text), (4 bytes).
+    Removing plib035_dma.o(.rrx_text), (6 bytes).
+    Removing plib035_dma.o(i.DMA_AltCtrlCmd), (68 bytes).
+    Removing plib035_dma.o(i.DMA_ChannelDeInit), (10 bytes).
+    Removing plib035_dma.o(i.DMA_ChannelEnableCmd), (68 bytes).
+    Removing plib035_dma.o(i.DMA_ChannelInit), (584 bytes).
+    Removing plib035_dma.o(i.DMA_ChannelStructInit), (50 bytes).
+    Removing plib035_dma.o(i.DMA_DeInit), (28 bytes).
+    Removing plib035_dma.o(i.DMA_HighPriorityCmd), (68 bytes).
+    Removing plib035_dma.o(i.DMA_Init), (52 bytes).
+    Removing plib035_dma.o(i.DMA_ProtectConfig), (148 bytes).
+    Removing plib035_dma.o(i.DMA_ReqMaskCmd), (68 bytes).
+    Removing plib035_dma.o(i.DMA_StructInit), (28 bytes).
+    Removing plib035_dma.o(i.DMA_UseBurstCmd), (68 bytes).
+    Removing plib035_ecap.o(.rev16_text), (4 bytes).
+    Removing plib035_ecap.o(.revsh_text), (4 bytes).
+    Removing plib035_ecap.o(.rrx_text), (6 bytes).
+    Removing plib035_ecap.o(i.ECAP_Capture_Init), (96 bytes).
+    Removing plib035_ecap.o(i.ECAP_Capture_ModeConfig), (80 bytes).
+    Removing plib035_ecap.o(i.ECAP_Capture_PolarityEvt0Config), (80 bytes).
+    Removing plib035_ecap.o(i.ECAP_Capture_PolarityEvt1Config), (80 bytes).
+    Removing plib035_ecap.o(i.ECAP_Capture_PolarityEvt2Config), (80 bytes).
+    Removing plib035_ecap.o(i.ECAP_Capture_PolarityEvt3Config), (80 bytes).
+    Removing plib035_ecap.o(i.ECAP_Capture_PrescaleConfig), (80 bytes).
+    Removing plib035_ecap.o(i.ECAP_Capture_RstEvt0Cmd), (80 bytes).
+    Removing plib035_ecap.o(i.ECAP_Capture_RstEvt1Cmd), (80 bytes).
+    Removing plib035_ecap.o(i.ECAP_Capture_RstEvt2Cmd), (80 bytes).
+    Removing plib035_ecap.o(i.ECAP_Capture_RstEvt3Cmd), (80 bytes).
+    Removing plib035_ecap.o(i.ECAP_Capture_StopConfig), (80 bytes).
+    Removing plib035_ecap.o(i.ECAP_Capture_StructInit), (28 bytes).
+    Removing plib035_ecap.o(i.ECAP_DeInit), (124 bytes).
+    Removing plib035_ecap.o(i.ECAP_HaltConfig), (84 bytes).
+    Removing plib035_ecap.o(i.ECAP_Init), (40 bytes).
+    Removing plib035_ecap.o(i.ECAP_ModeConfig), (80 bytes).
+    Removing plib035_ecap.o(i.ECAP_PWM_Init), (148 bytes).
+    Removing plib035_ecap.o(i.ECAP_PWM_PolarityConfig), (80 bytes).
+    Removing plib035_ecap.o(i.ECAP_PWM_StructInit), (18 bytes).
+    Removing plib035_ecap.o(i.ECAP_StructInit), (12 bytes).
+    Removing plib035_ecap.o(i.ECAP_SyncCmd), (80 bytes).
+    Removing plib035_ecap.o(i.ECAP_SyncOutConfig), (84 bytes).
+    Removing plib035_ecap.o(i.RCU_APBRstCmd), (160 bytes).
+    Removing plib035_gpio.o(.rev16_text), (4 bytes).
+    Removing plib035_gpio.o(.revsh_text), (4 bytes).
+    Removing plib035_gpio.o(.rrx_text), (6 bytes).
+    Removing plib035_gpio.o(i.GPIO_StructInit), (24 bytes).
+    Removing plib035_i2c.o(.rev16_text), (4 bytes).
+    Removing plib035_i2c.o(.revsh_text), (4 bytes).
+    Removing plib035_i2c.o(.rrx_text), (6 bytes).
+    Removing plib035_i2c.o(i.I2C_FSFreqConfig), (128 bytes).
+    Removing plib035_i2c.o(i.I2C_HSFreqConfig), (96 bytes).
+    Removing plib035_mflash.o(.rev16_text), (4 bytes).
+    Removing plib035_mflash.o(.revsh_text), (4 bytes).
+    Removing plib035_mflash.o(.rrx_text), (6 bytes).
+    Removing plib035_mflash.o(i.MFLASH_BusyStatus), (16 bytes).
+    Removing plib035_mflash.o(i.MFLASH_EraseFull), (92 bytes).
+    Removing plib035_mflash.o(i.MFLASH_ErasePage), (136 bytes).
+    Removing plib035_mflash.o(i.MFLASH_ReadData), (224 bytes).
+    Removing plib035_mflash.o(i.MFLASH_SetAddr), (12 bytes).
+    Removing plib035_mflash.o(i.MFLASH_SetCmd), (20 bytes).
+    Removing plib035_mflash.o(i.MFLASH_WriteData), (188 bytes).
+    Removing plib035_pmu.o(.rev16_text), (4 bytes).
+    Removing plib035_pmu.o(.revsh_text), (4 bytes).
+    Removing plib035_pmu.o(.rrx_text), (6 bytes).
+    Removing plib035_pwm.o(.rev16_text), (4 bytes).
+    Removing plib035_pwm.o(.revsh_text), (4 bytes).
+    Removing plib035_pwm.o(.rrx_text), (6 bytes).
+    Removing plib035_pwm.o(i.PWM_AQ_ActionAConfig), (168 bytes).
+    Removing plib035_pwm.o(i.PWM_AQ_ActionBConfig), (168 bytes).
+    Removing plib035_pwm.o(i.PWM_AQ_Init), (128 bytes).
+    Removing plib035_pwm.o(i.PWM_AQ_StructInit), (28 bytes).
+    Removing plib035_pwm.o(i.PWM_CMP_CmpADirectLoadCmd), (116 bytes).
+    Removing plib035_pwm.o(i.PWM_CMP_CmpALoadEventConfig), (124 bytes).
+    Removing plib035_pwm.o(i.PWM_CMP_Init), (56 bytes).
+    Removing plib035_pwm.o(i.PWM_CMP_SetCmpA), (80 bytes).
+    Removing plib035_pwm.o(i.PWM_CMP_SetCmpB), (80 bytes).
+    Removing plib035_pwm.o(i.PWM_CMP_StructInit), (16 bytes).
+    Removing plib035_pwm.o(i.PWM_DB_InConfig), (88 bytes).
+    Removing plib035_pwm.o(i.PWM_DB_Init), (164 bytes).
+    Removing plib035_pwm.o(i.PWM_DB_OutConfig), (88 bytes).
+    Removing plib035_pwm.o(i.PWM_DB_PolarityConfig), (88 bytes).
+    Removing plib035_pwm.o(i.PWM_DB_StructInit), (14 bytes).
+    Removing plib035_pwm.o(i.PWM_DeInit), (120 bytes).
+    Removing plib035_pwm.o(i.PWM_ET_DRQACmd), (80 bytes).
+    Removing plib035_pwm.o(i.PWM_ET_DRQAEventConfig), (100 bytes).
+    Removing plib035_pwm.o(i.PWM_ET_DRQAPeriodConfig), (80 bytes).
+    Removing plib035_pwm.o(i.PWM_ET_DRQBCmd), (80 bytes).
+    Removing plib035_pwm.o(i.PWM_ET_DRQBEventConfig), (100 bytes).
+    Removing plib035_pwm.o(i.PWM_ET_DRQBPeriodConfig), (80 bytes).
+    Removing plib035_pwm.o(i.PWM_ET_Init), (104 bytes).
+    Removing plib035_pwm.o(i.PWM_ET_SOCACmd), (80 bytes).
+    Removing plib035_pwm.o(i.PWM_ET_SOCAEventConfig), (100 bytes).
+    Removing plib035_pwm.o(i.PWM_ET_SOCAPeriodConfig), (80 bytes).
+    Removing plib035_pwm.o(i.PWM_ET_SOCBCmd), (80 bytes).
+    Removing plib035_pwm.o(i.PWM_ET_SOCBEventConfig), (100 bytes).
+    Removing plib035_pwm.o(i.PWM_ET_SOCBPeriodConfig), (80 bytes).
+    Removing plib035_pwm.o(i.PWM_ET_StructInit), (42 bytes).
+    Removing plib035_pwm.o(i.PWM_HD_ActionAConfig), (92 bytes).
+    Removing plib035_pwm.o(i.PWM_HD_ActionBConfig), (92 bytes).
+    Removing plib035_pwm.o(i.PWM_HD_CycleCmd), (84 bytes).
+    Removing plib035_pwm.o(i.PWM_HD_Init), (50 bytes).
+    Removing plib035_pwm.o(i.PWM_HD_OneShotCmd), (84 bytes).
+    Removing plib035_pwm.o(i.PWM_HD_SourceCmd), (96 bytes).
+    Removing plib035_pwm.o(i.PWM_HD_StructInit), (16 bytes).
+    Removing plib035_pwm.o(i.PWM_TB_ClkDivConfig), (192 bytes).
+    Removing plib035_pwm.o(i.PWM_TB_HaltConfig), (80 bytes).
+    Removing plib035_pwm.o(i.PWM_TB_Init), (236 bytes).
+    Removing plib035_pwm.o(i.PWM_TB_ModeConfig), (88 bytes).
+    Removing plib035_pwm.o(i.PWM_TB_PeriodDirectLoadCmd), (80 bytes).
+    Removing plib035_pwm.o(i.PWM_TB_PhaseSyncCmd), (80 bytes).
+    Removing plib035_pwm.o(i.PWM_TB_PhaseSyncDirConfig), (80 bytes).
+    Removing plib035_pwm.o(i.PWM_TB_StructInit), (24 bytes).
+    Removing plib035_pwm.o(i.PWM_TB_SyncOutConfig), (88 bytes).
+    Removing plib035_pwm.o(i.PWM_TZ_ActionAConfig), (88 bytes).
+    Removing plib035_pwm.o(i.PWM_TZ_ActionBConfig), (88 bytes).
+    Removing plib035_pwm.o(i.PWM_TZ_CycleCmd), (80 bytes).
+    Removing plib035_pwm.o(i.PWM_TZ_Init), (40 bytes).
+    Removing plib035_pwm.o(i.PWM_TZ_OneShotCmd), (80 bytes).
+    Removing plib035_pwm.o(i.PWM_TZ_StructInit), (12 bytes).
+    Removing plib035_pwm.o(i.RCU_APBRstCmd), (160 bytes).
+    Removing plib035_qep.o(.rev16_text), (4 bytes).
+    Removing plib035_qep.o(.revsh_text), (4 bytes).
+    Removing plib035_qep.o(.rrx_text), (6 bytes).
+    Removing plib035_qep.o(i.QEP_CAP_DivConfig), (136 bytes).
+    Removing plib035_qep.o(i.QEP_CAP_Init), (136 bytes).
+    Removing plib035_qep.o(i.QEP_CAP_StructInit), (18 bytes).
+    Removing plib035_qep.o(i.QEP_CMP_Init), (224 bytes).
+    Removing plib035_qep.o(i.QEP_CMP_StructInit), (18 bytes).
+    Removing plib035_qep.o(i.QEP_DeInit), (22 bytes).
+    Removing plib035_qep.o(i.QEP_PC_Init), (340 bytes).
+    Removing plib035_qep.o(i.QEP_PC_StructInit), (24 bytes).
+    Removing plib035_qep.o(i.RCU_APBRstCmd), (160 bytes).
+    Removing plib035_rcu.o(.rev16_text), (4 bytes).
+    Removing plib035_rcu.o(.revsh_text), (4 bytes).
+    Removing plib035_rcu.o(.rrx_text), (6 bytes).
+    Removing plib035_rcu.o(i.RCU_GetADCClkFreq), (56 bytes).
+    Removing plib035_rcu.o(i.RCU_GetClkOutFreq), (52 bytes).
+    Removing plib035_rcu.o(i.RCU_GetOSEClkFreq), (8 bytes).
+    Removing plib035_rcu.o(i.RCU_GetOSIClkFreq), (8 bytes).
+    Removing plib035_rcu.o(i.RCU_GetPLLClkFreq), (72 bytes).
+    Removing plib035_rcu.o(i.RCU_GetPLLDivClkFreq), (28 bytes).
+    Removing plib035_rcu.o(i.RCU_GetSPIClkFreq), (56 bytes).
+    Removing plib035_rcu.o(i.RCU_GetSysClkFreq), (28 bytes).
+    Removing plib035_rcu.o(i.RCU_GetTraceClkFreq), (52 bytes).
+    Removing plib035_rcu.o(i.RCU_GetUARTClkFreq), (60 bytes).
+    Removing plib035_rcu.o(i.RCU_GetWDTClkFreq), (52 bytes).
+    Removing plib035_rcu.o(i.RCU_PLL_DeInit), (24 bytes).
+    Removing plib035_rcu.o(i.getPeriphClkFreq), (60 bytes).
+    Removing plib035_rcu.o(i.getSysClkFreq), (60 bytes).
+    Removing plib035_rcu.o(i.getSysPeriphClkFreq), (60 bytes).
+    Removing plib035_spi.o(.rev16_text), (4 bytes).
+    Removing plib035_spi.o(.revsh_text), (4 bytes).
+    Removing plib035_spi.o(.rrx_text), (6 bytes).
+    Removing plib035_spi.o(i.RCU_SPIRstCmd), (84 bytes).
+    Removing plib035_spi.o(i.SPI_DataWidthConfig), (88 bytes).
+    Removing plib035_spi.o(i.SPI_DeInit), (16 bytes).
+    Removing plib035_spi.o(i.SPI_Init), (136 bytes).
+    Removing plib035_spi.o(i.SPI_SCKDivConfig), (72 bytes).
+    Removing plib035_spi.o(i.SPI_StructInit), (20 bytes).
+    Removing plib035_tmr.o(.rev16_text), (4 bytes).
+    Removing plib035_tmr.o(.revsh_text), (4 bytes).
+    Removing plib035_tmr.o(.rrx_text), (6 bytes).
+    Removing plib035_tmr.o(i.TMR_FreqConfig), (26 bytes).
+    Removing plib035_tmr.o(i.TMR_PeriodConfig), (36 bytes).
+    Removing plib035_tmr.o(i.TMR_SetLoad), (100 bytes).
+    Removing plib035_uart.o(.rev16_text), (4 bytes).
+    Removing plib035_uart.o(.revsh_text), (4 bytes).
+    Removing plib035_uart.o(.rrx_text), (6 bytes).
+    Removing plib035_uart.o(i.RCU_UARTRstCmd), (88 bytes).
+    Removing plib035_uart.o(i.UART_AutoBaudConfig), (184 bytes).
+    Removing plib035_uart.o(i.UART_BaudDivConfig), (88 bytes).
+    Removing plib035_uart.o(i.UART_DataWidthConfig), (112 bytes).
+    Removing plib035_uart.o(i.UART_DeInit), (100 bytes).
+    Removing plib035_uart.o(i.UART_FIFOCmd), (72 bytes).
+    Removing plib035_uart.o(i.UART_Init), (64 bytes).
+    Removing plib035_uart.o(i.UART_ParityBitConfig), (84 bytes).
+    Removing plib035_uart.o(i.UART_RxCmd), (72 bytes).
+    Removing plib035_uart.o(i.UART_StopBitConfig), (68 bytes).
+    Removing plib035_uart.o(i.UART_StructInit), (24 bytes).
+    Removing plib035_uart.o(i.UART_TxCmd), (72 bytes).
+    Removing plib035_wdt.o(.rev16_text), (4 bytes).
+    Removing plib035_wdt.o(.revsh_text), (4 bytes).
+    Removing plib035_wdt.o(.rrx_text), (6 bytes).
+    Removing retarget.o(.rev16_text), (4 bytes).
+    Removing retarget.o(.revsh_text), (4 bytes).
+    Removing retarget.o(.rrx_text), (6 bytes).
+    Removing retarget.o(i._ttywrch), (12 bytes).
+    Removing retarget.o(i.fgetc), (10 bytes).
+    Removing retarget_conf.o(.rev16_text), (4 bytes).
+    Removing retarget_conf.o(.revsh_text), (4 bytes).
+    Removing retarget_conf.o(.rrx_text), (6 bytes).
+    Removing retarget_conf.o(i.retarget_get_char), (28 bytes).
+
+331 unused section(s) (total 35598 bytes) removed from the image.
+
+==============================================================================
+
+Image Symbol Table
+
+    Local Symbols
+
+    Symbol Name                              Value     Ov Type        Size  Object(Section)
+
+    RESET                                    0x00000000   Section      344  startup_k1921vk035.o(RESET)
+    ../clib/angel/boardlib.s                 0x00000000   Number         0  boardshut.o ABSOLUTE
+    ../clib/angel/boardlib.s                 0x00000000   Number         0  boardinit1.o ABSOLUTE
+    ../clib/angel/boardlib.s                 0x00000000   Number         0  boardinit2.o ABSOLUTE
+    ../clib/angel/boardlib.s                 0x00000000   Number         0  boardinit3.o ABSOLUTE
+    ../clib/angel/dczerorl2.s                0x00000000   Number         0  __dczerorl2.o ABSOLUTE
+    ../clib/angel/handlers.s                 0x00000000   Number         0  __scatter_zi.o ABSOLUTE
+    ../clib/angel/kernel.s                   0x00000000   Number         0  __rtentry4.o ABSOLUTE
+    ../clib/angel/kernel.s                   0x00000000   Number         0  __rtentry.o ABSOLUTE
+    ../clib/angel/kernel.s                   0x00000000   Number         0  rtexit.o ABSOLUTE
+    ../clib/angel/kernel.s                   0x00000000   Number         0  __rtentry2.o ABSOLUTE
+    ../clib/angel/kernel.s                   0x00000000   Number         0  rtexit2.o ABSOLUTE
+    ../clib/angel/rt.s                       0x00000000   Number         0  rt_div0.o ABSOLUTE
+    ../clib/angel/rt.s                       0x00000000   Number         0  rt_raise.o ABSOLUTE
+    ../clib/angel/rt.s                       0x00000000   Number         0  aeabi_ldiv0.o ABSOLUTE
+    ../clib/angel/rt.s                       0x00000000   Number         0  aeabi_ldiv0_sigfpe.o ABSOLUTE
+    ../clib/angel/rt.s                       0x00000000   Number         0  rt_errno_addr.o ABSOLUTE
+    ../clib/angel/rt.s                       0x00000000   Number         0  rt_errno_addr_intlibspace.o ABSOLUTE
+    ../clib/angel/scatter.s                  0x00000000   Number         0  __scatter.o ABSOLUTE
+    ../clib/angel/startup.s                  0x00000000   Number         0  __main.o ABSOLUTE
+    ../clib/angel/sys.s                      0x00000000   Number         0  libspace.o ABSOLUTE
+    ../clib/angel/sys.s                      0x00000000   Number         0  use_no_semi.o ABSOLUTE
+    ../clib/angel/sys.s                      0x00000000   Number         0  sys_stackheap_outer.o ABSOLUTE
+    ../clib/angel/sys.s                      0x00000000   Number         0  indicate_semi.o ABSOLUTE
+    ../clib/angel/sysapp.c                   0x00000000   Number         0  sys_command.o ABSOLUTE
+    ../clib/armsys.c                         0x00000000   Number         0  no_argv.o ABSOLUTE
+    ../clib/armsys.c                         0x00000000   Number         0  _get_argv_nomalloc.o ABSOLUTE
+    ../clib/armsys.c                         0x00000000   Number         0  argv_veneer.o ABSOLUTE
+    ../clib/armsys.c                         0x00000000   Number         0  argv_veneer.o ABSOLUTE
+    ../clib/fenv.c                           0x00000000   Number         0  _rserrno.o ABSOLUTE
+    ../clib/heapalloc.c                      0x00000000   Number         0  hrguard.o ABSOLUTE
+    ../clib/heapaux.c                        0x00000000   Number         0  heapauxi.o ABSOLUTE
+    ../clib/libinit.s                        0x00000000   Number         0  libshutdown.o ABSOLUTE
+    ../clib/libinit.s                        0x00000000   Number         0  libshutdown2.o ABSOLUTE
+    ../clib/libinit.s                        0x00000000   Number         0  libinit.o ABSOLUTE
+    ../clib/libinit.s                        0x00000000   Number         0  libinit2.o ABSOLUTE
+    ../clib/longlong.s                       0x00000000   Number         0  llsdiv.o ABSOLUTE
+    ../clib/longlong.s                       0x00000000   Number         0  lludivv7m.o ABSOLUTE
+    ../clib/memcpset.s                       0x00000000   Number         0  rt_memclr_w.o ABSOLUTE
+    ../clib/memcpset.s                       0x00000000   Number         0  rt_memcpy_w.o ABSOLUTE
+    ../clib/memcpset.s                       0x00000000   Number         0  rt_memcpy_v6.o ABSOLUTE
+    ../clib/misc.s                           0x00000000   Number         0  printf_stubs.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  __printf.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  _printf_char_file.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  _printf_char.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  __printf_flags.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  __printf_ss.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  __printf_flags_ss.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  __printf_wp.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  _printf_dec.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  _printf_str.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  __printf_flags_wp.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  __printf_ss_wp.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  __printf_flags_ss_wp.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  noretval__2printf.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  __2printf.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  _printf_pad.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  _printf_char_common.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  __printf_nopercent.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  _printf_intcommon.o ABSOLUTE
+    ../clib/printf_percent.s                 0x00000000   Number         0  _printf_s.o ABSOLUTE
+    ../clib/printf_percent.s                 0x00000000   Number         0  _printf_percent.o ABSOLUTE
+    ../clib/printf_percent.s                 0x00000000   Number         0  _printf_percent_end.o ABSOLUTE
+    ../clib/printf_percent.s                 0x00000000   Number         0  _printf_d.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_fpe_inner.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_exit.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_rtmem_formal.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_fpe_formal.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_fpe_outer.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_general.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_other.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_segv_inner.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_cppl_inner.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_pvfn_inner.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_stak_inner.o ABSOLUTE
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+    Reset_Handler                            0x00000249   Thumb Code     8  startup_k1921vk035.o(.text)
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+    ADC_SEQ0_IRQHandler                      0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    ADC_SEQ1_IRQHandler                      0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    CAN0_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    CAN10_IRQHandler                         0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    CAN11_IRQHandler                         0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    CAN12_IRQHandler                         0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    CAN13_IRQHandler                         0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    CAN14_IRQHandler                         0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    CAN15_IRQHandler                         0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    CAN1_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    CAN2_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    CAN3_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    CAN4_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    CAN5_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    CAN6_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    CAN7_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    CAN8_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    CAN9_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH0_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH10_IRQHandler                      0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH11_IRQHandler                      0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH12_IRQHandler                      0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH13_IRQHandler                      0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH14_IRQHandler                      0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH15_IRQHandler                      0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH1_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH2_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH3_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH4_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH5_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH6_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH7_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH8_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH9_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    ECAP0_IRQHandler                         0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    ECAP1_IRQHandler                         0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    ECAP2_IRQHandler                         0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    FPU_IRQHandler                           0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    GPIOA_IRQHandler                         0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    GPIOB_IRQHandler                         0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    I2C_IRQHandler                           0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    MFLASH_IRQHandler                        0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    PWM0_HD_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    PWM0_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    PWM0_TZ_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    PWM1_HD_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    PWM1_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
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+    PWM2_HD_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
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+    TMR2_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    TMR3_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
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+    UART0_TD_IRQHandler                      0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
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+    __fplib_config_pureend_doubles           0x00001939   Thumb Code     0  fpinit.o(x$fpl$fpinit)
+    __I$use$fp                               0x0000193a   Number         0  usenofp.o(x$fpl$usenofp)
+    Region$$Table$$Base                      0x0000193c   Number         0  anon$$obj.o(Region$$Table)
+    Region$$Table$$Limit                     0x0000195c   Number         0  anon$$obj.o(Region$$Table)
+    SystemCoreClock                          0x20000194   Data           4  system_k1921vk035.o(.data)
+    uwTick                                   0x20000198   Data           4  system_k1921vk035.o(.data)
+    __stdout                                 0x2000019c   Data           4  retarget.o(.data)
+    __stdin                                  0x200001a0   Data           4  retarget.o(.data)
+    __libspace_start                         0x200001a4   Data          96  libspace.o(.bss)
+    __temporary_stack_top$libspace           0x20000204   Data           0  libspace.o(.bss)
+
+
+
+==============================================================================
+
+Memory Map of the image
+
+  Image Entry point : 0x00000249
+
+  Load Region LR_1 (Base: 0x00000000, Size: 0x00001b00, Max: 0xffffffff, ABSOLUTE, COMPRESSED[0x00001980])
+
+    Execution Region ER_RO (Exec base: 0x00000000, Load base: 0x00000000, Size: 0x0000195c, Max: 0xffffffff, ABSOLUTE)
+
+    Exec Addr    Load Addr    Size         Type   Attr      Idx    E Section Name        Object
+
+    0x00000000   0x00000000   0x00000158   Data   RO          926    RESET               startup_k1921vk035.o
+    0x00000158   0x00000158   0x00000008   Code   RO         2411  * !!!main             c_w.l(__main.o)
+    0x00000160   0x00000160   0x00000034   Code   RO         2660    !!!scatter          c_w.l(__scatter.o)
+    0x00000194   0x00000194   0x0000005a   Code   RO         2658    !!dczerorl2         c_w.l(__dczerorl2.o)
+    0x000001ee   0x000001ee   0x00000002   PAD
+    0x000001f0   0x000001f0   0x0000001c   Code   RO         2662    !!handler_zi        c_w.l(__scatter_zi.o)
+    0x0000020c   0x0000020c   0x00000000   Code   RO         2393    .ARM.Collect$$_printf_percent$$00000000  c_w.l(_printf_percent.o)
+    0x0000020c   0x0000020c   0x00000006   Code   RO         2392    .ARM.Collect$$_printf_percent$$00000009  c_w.l(_printf_d.o)
+    0x00000212   0x00000212   0x00000006   Code   RO         2391    .ARM.Collect$$_printf_percent$$00000014  c_w.l(_printf_s.o)
+    0x00000218   0x00000218   0x00000004   Code   RO         2464    .ARM.Collect$$_printf_percent$$00000017  c_w.l(_printf_percent_end.o)
+    0x0000021c   0x0000021c   0x00000002   Code   RO         2584    .ARM.Collect$$libinit$$00000000  c_w.l(libinit.o)
+    0x0000021e   0x0000021e   0x00000004   Code   RO         2465    .ARM.Collect$$libinit$$00000001  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         2468    .ARM.Collect$$libinit$$00000004  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         2471    .ARM.Collect$$libinit$$0000000A  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         2473    .ARM.Collect$$libinit$$0000000C  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         2475    .ARM.Collect$$libinit$$0000000E  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         2478    .ARM.Collect$$libinit$$00000011  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         2480    .ARM.Collect$$libinit$$00000013  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         2482    .ARM.Collect$$libinit$$00000015  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         2484    .ARM.Collect$$libinit$$00000017  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         2486    .ARM.Collect$$libinit$$00000019  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         2488    .ARM.Collect$$libinit$$0000001B  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         2490    .ARM.Collect$$libinit$$0000001D  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         2492    .ARM.Collect$$libinit$$0000001F  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         2494    .ARM.Collect$$libinit$$00000021  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         2496    .ARM.Collect$$libinit$$00000023  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         2498    .ARM.Collect$$libinit$$00000025  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         2502    .ARM.Collect$$libinit$$0000002C  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         2504    .ARM.Collect$$libinit$$0000002E  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         2506    .ARM.Collect$$libinit$$00000030  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         2508    .ARM.Collect$$libinit$$00000032  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000002   Code   RO         2509    .ARM.Collect$$libinit$$00000033  c_w.l(libinit2.o)
+    0x00000224   0x00000224   0x00000002   Code   RO         2621    .ARM.Collect$$libshutdown$$00000000  c_w.l(libshutdown.o)
+    0x00000226   0x00000226   0x00000000   Code   RO         2625    .ARM.Collect$$libshutdown$$00000002  c_w.l(libshutdown2.o)
+    0x00000226   0x00000226   0x00000000   Code   RO         2627    .ARM.Collect$$libshutdown$$00000004  c_w.l(libshutdown2.o)
+    0x00000226   0x00000226   0x00000000   Code   RO         2629    .ARM.Collect$$libshutdown$$00000006  c_w.l(libshutdown2.o)
+    0x00000226   0x00000226   0x00000000   Code   RO         2632    .ARM.Collect$$libshutdown$$00000009  c_w.l(libshutdown2.o)
+    0x00000226   0x00000226   0x00000000   Code   RO         2635    .ARM.Collect$$libshutdown$$0000000C  c_w.l(libshutdown2.o)
+    0x00000226   0x00000226   0x00000000   Code   RO         2637    .ARM.Collect$$libshutdown$$0000000E  c_w.l(libshutdown2.o)
+    0x00000226   0x00000226   0x00000000   Code   RO         2640    .ARM.Collect$$libshutdown$$00000011  c_w.l(libshutdown2.o)
+    0x00000226   0x00000226   0x00000002   Code   RO         2641    .ARM.Collect$$libshutdown$$00000012  c_w.l(libshutdown2.o)
+    0x00000228   0x00000228   0x00000000   Code   RO         2453    .ARM.Collect$$rtentry$$00000000  c_w.l(__rtentry.o)
+    0x00000228   0x00000228   0x00000000   Code   RO         2535    .ARM.Collect$$rtentry$$00000002  c_w.l(__rtentry2.o)
+    0x00000228   0x00000228   0x00000006   Code   RO         2547    .ARM.Collect$$rtentry$$00000004  c_w.l(__rtentry4.o)
+    0x0000022e   0x0000022e   0x00000000   Code   RO         2537    .ARM.Collect$$rtentry$$00000009  c_w.l(__rtentry2.o)
+    0x0000022e   0x0000022e   0x00000004   Code   RO         2538    .ARM.Collect$$rtentry$$0000000A  c_w.l(__rtentry2.o)
+    0x00000232   0x00000232   0x00000000   Code   RO         2540    .ARM.Collect$$rtentry$$0000000C  c_w.l(__rtentry2.o)
+    0x00000232   0x00000232   0x00000008   Code   RO         2541    .ARM.Collect$$rtentry$$0000000D  c_w.l(__rtentry2.o)
+    0x0000023a   0x0000023a   0x00000002   Code   RO         2587    .ARM.Collect$$rtexit$$00000000  c_w.l(rtexit.o)
+    0x0000023c   0x0000023c   0x00000000   Code   RO         2601    .ARM.Collect$$rtexit$$00000002  c_w.l(rtexit2.o)
+    0x0000023c   0x0000023c   0x00000004   Code   RO         2602    .ARM.Collect$$rtexit$$00000003  c_w.l(rtexit2.o)
+    0x00000240   0x00000240   0x00000006   Code   RO         2603    .ARM.Collect$$rtexit$$00000004  c_w.l(rtexit2.o)
+    0x00000246   0x00000246   0x00000002   PAD
+    0x00000248   0x00000248   0x00000040   Code   RO          927  * .text               startup_k1921vk035.o
+    0x00000288   0x00000288   0x00000002   Code   RO         2355    .text               c_w.l(use_no_semi.o)
+    0x0000028a   0x0000028a   0x00000002   PAD
+    0x0000028c   0x0000028c   0x00000018   Code   RO         2361    .text               c_w.l(noretval__2printf.o)
+    0x000002a4   0x000002a4   0x0000004e   Code   RO         2365    .text               c_w.l(_printf_pad.o)
+    0x000002f2   0x000002f2   0x00000052   Code   RO         2367    .text               c_w.l(_printf_str.o)
+    0x00000344   0x00000344   0x00000078   Code   RO         2369    .text               c_w.l(_printf_dec.o)
+    0x000003bc   0x000003bc   0x0000010e   Code   RO         2379    .text               c_w.l(__printf_wp.o)
+    0x000004ca   0x000004ca   0x00000006   Code   RO         2409    .text               c_w.l(heapauxi.o)
+    0x000004d0   0x000004d0   0x000000b2   Code   RO         2458    .text               c_w.l(_printf_intcommon.o)
+    0x00000582   0x00000582   0x0000002c   Code   RO         2460    .text               c_w.l(_printf_char.o)
+    0x000005ae   0x000005ae   0x00000002   PAD
+    0x000005b0   0x000005b0   0x00000024   Code   RO         2462    .text               c_w.l(_printf_char_file.o)
+    0x000005d4   0x000005d4   0x00000030   Code   RO         2558    .text               c_w.l(_printf_char_common.o)
+    0x00000604   0x00000604   0x00000008   Code   RO         2564    .text               c_w.l(libspace.o)
+    0x0000060c   0x0000060c   0x0000004a   Code   RO         2567    .text               c_w.l(sys_stackheap_outer.o)
+    0x00000656   0x00000656   0x00000012   Code   RO         2573    .text               c_w.l(exit.o)
+    0x00000668   0x00000668   0x00000004   Code   RO          322    i.BusFault_Handler  vk035_it.o
+    0x0000066c   0x0000066c   0x000000a4   Code   RO          879    i.ClkInit           system_k1921vk035.o
+    0x00000710   0x00000710   0x00000002   Code   RO          323    i.DebugMon_Handler  vk035_it.o
+    0x00000712   0x00000712   0x00000006   Code   RO            4    i.Error_Handler     main.o
+    0x00000718   0x00000718   0x00000030   Code   RO          880    i.FPUInit           system_k1921vk035.o
+    0x00000748   0x00000748   0x00000060   Code   RO         1334    i.GPIO_AltFuncCmd   plib035_gpio.o
+    0x000007a8   0x000007a8   0x00000064   Code   RO         1335    i.GPIO_DeInit       plib035_gpio.o
+    0x0000080c   0x0000080c   0x00000084   Code   RO         1336    i.GPIO_DigitalCmd   plib035_gpio.o
+    0x00000890   0x00000890   0x00000084   Code   RO         1337    i.GPIO_DriveModeConfig  plib035_gpio.o
+    0x00000914   0x00000914   0x00000080   Code   RO         1338    i.GPIO_InModeConfig  plib035_gpio.o
+    0x00000994   0x00000994   0x0000004e   Code   RO         1339    i.GPIO_Init         plib035_gpio.o
+    0x000009e2   0x000009e2   0x0000002e   Code   RO         1340    i.GPIO_ModeConfig   plib035_gpio.o
+    0x00000a10   0x00000a10   0x00000060   Code   RO         1341    i.GPIO_OutCmd       plib035_gpio.o
+    0x00000a70   0x00000a70   0x00000080   Code   RO         1342    i.GPIO_OutModeConfig  plib035_gpio.o
+    0x00000af0   0x00000af0   0x00000080   Code   RO         1343    i.GPIO_PullModeConfig  plib035_gpio.o
+    0x00000b70   0x00000b70   0x00000004   Code   RO          326    i.HardFault_Handler  vk035_it.o
+    0x00000b74   0x00000b74   0x0000004c   Code   RO         1910    i.MFLASH_LatencyConfig  plib035_rcu.o
+    0x00000bc0   0x00000bc0   0x00000004   Code   RO          327    i.MemManage_Handler  vk035_it.o
+    0x00000bc4   0x00000bc4   0x00000004   Code   RO          328    i.NMI_Handler       vk035_it.o
+    0x00000bc8   0x00000bc8   0x00000002   Code   RO          329    i.PendSV_Handler    vk035_it.o
+    0x00000bca   0x00000bca   0x00000002   PAD
+    0x00000bcc   0x00000bcc   0x00000074   Code   RO          215    i.RCU_AHBClkCmd     gpio.o
+    0x00000c40   0x00000c40   0x00000050   Code   RO          216    i.RCU_AHBRstCmd     gpio.o
+    0x00000c90   0x00000c90   0x00000074   Code   RO         1345    i.RCU_AHBRstCmd     plib035_gpio.o
+    0x00000d04   0x00000d04   0x0000006c   Code   RO          270    i.RCU_ClkOutConfig  rcu.o
+    0x00000d70   0x00000d70   0x000001a8   Code   RO         1922    i.RCU_PLL_AutoConfig  plib035_rcu.o
+    0x00000f18   0x00000f18   0x00000128   Code   RO         1924    i.RCU_PLL_Init      plib035_rcu.o
+    0x00001040   0x00001040   0x00000050   Code   RO         1925    i.RCU_PLL_OutCmd    plib035_rcu.o
+    0x00001090   0x00001090   0x00000010   Code   RO         1926    i.RCU_PLL_StructInit  plib035_rcu.o
+    0x000010a0   0x000010a0   0x000000d4   Code   RO         1927    i.RCU_SysClkChangeCmd  plib035_rcu.o
+    0x00001174   0x00001174   0x00000002   Code   RO          330    i.SVC_Handler       vk035_it.o
+    0x00001176   0x00001176   0x00000002   PAD
+    0x00001178   0x00001178   0x00000010   Code   RO          331    i.SysTick_Handler   vk035_it.o
+    0x00001188   0x00001188   0x00000090   Code   RO          881    i.SystemCoreClockUpdate  system_k1921vk035.o
+    0x00001218   0x00001218   0x0000000c   Code   RO          882    i.SystemInit        system_k1921vk035.o
+    0x00001224   0x00001224   0x00000004   Code   RO          332    i.UsageFault_Handler  vk035_it.o
+    0x00001228   0x00001228   0x0000000e   Code   RO         2381    i._is_digit         c_w.l(__printf_wp.o)
+    0x00001236   0x00001236   0x00000004   Code   RO         2256    i._sys_exit         retarget.o
+    0x0000123a   0x0000123a   0x00000002   PAD
+    0x0000123c   0x0000123c   0x00000038   Code   RO            7    i.assert_failed     main.o
+    0x00001274   0x00001274   0x00000008   Code   RO         2258    i.ferror            retarget.o
+    0x0000127c   0x0000127c   0x0000000e   Code   RO         2260    i.fputc             retarget.o
+    0x0000128a   0x0000128a   0x00000002   PAD
+    0x0000128c   0x0000128c   0x00000064   Code   RO          218    i.gpio_init         gpio.o
+    0x000012f0   0x000012f0   0x00000008   Code   RO            9    i.main              main.o
+    0x000012f8   0x000012f8   0x00000080   Code   RO           10    i.periph_init       main.o
+    0x00001378   0x00001378   0x000000e4   Code   RO         2321    i.retarget_init     retarget_conf.o
+    0x0000145c   0x0000145c   0x0000001c   Code   RO         2322    i.retarget_put_char  retarget_conf.o
+    0x00001478   0x00001478   0x000000dc   Code   RO          272    i.sysclk_init       rcu.o
+    0x00001554   0x00001554   0x000002b0   Code   RO         2414    x$fpl$ddiv          fz_wm.l(ddiv.o)
+    0x00001804   0x00001804   0x0000005e   Code   RO         2417    x$fpl$dfix          fz_wm.l(dfix.o)
+    0x00001862   0x00001862   0x00000026   Code   RO         2421    x$fpl$dfltu         fz_wm.l(dflt_clz.o)
+    0x00001888   0x00001888   0x0000009c   Code   RO         2510    x$fpl$dnaninf       fz_wm.l(dnaninf.o)
+    0x00001924   0x00001924   0x0000000c   Code   RO         2512    x$fpl$dretinf       fz_wm.l(dretinf.o)
+    0x00001930   0x00001930   0x0000000a   Code   RO         2562    x$fpl$fpinit        fz_wm.l(fpinit.o)
+    0x0000193a   0x0000193a   0x00000000   Code   RO         2514    x$fpl$usenofp       fz_wm.l(usenofp.o)
+    0x0000193a   0x0000193a   0x00000002   PAD
+    0x0000193c   0x0000193c   0x00000020   Data   RO         2656    Region$$Table       anon$$obj.o
+
+
+    Execution Region ER_RW (Exec base: 0x20000000, Load base: 0x0000195c, Size: 0x000001a4, Max: 0xffffffff, ABSOLUTE, COMPRESSED[0x00000024])
+
+    Exec Addr    Load Addr    Size         Type   Attr      Idx    E Section Name        Object
+
+    0x20000000   COMPRESSED   0x00000188   Data   RW          220    .data               gpio.o
+    0x20000188   COMPRESSED   0x00000009   Data   RW          274    .data               rcu.o
+    0x20000191   COMPRESSED   0x00000003   PAD
+    0x20000194   COMPRESSED   0x00000008   Data   RW          883    .data               system_k1921vk035.o
+    0x2000019c   COMPRESSED   0x00000008   Data   RW         2261    .data               retarget.o
+
+
+    Execution Region ER_ZI (Exec base: 0x200001a4, Load base: 0x00001980, Size: 0x00000664, Max: 0xffffffff, ABSOLUTE)
+
+    Exec Addr    Load Addr    Size         Type   Attr      Idx    E Section Name        Object
+
+    0x200001a4        -       0x00000060   Zero   RW         2565    .bss                c_w.l(libspace.o)
+    0x20000204   0x00001980   0x00000004   PAD
+    0x20000208        -       0x00000200   Zero   RW          925    HEAP                startup_k1921vk035.o
+    0x20000408        -       0x00000400   Zero   RW          924    STACK               startup_k1921vk035.o
+
+
+==============================================================================
+
+Image component sizes
+
+
+      Code (inc. data)   RO Data    RW Data    ZI Data      Debug   Object Name
+
+       296         72          0        392          0      11008   gpio.o
+       198         96          0          0          0     206397   main.o
+      1180        352          0          0          0      12760   plib035_gpio.o
+      1104        266          0          0          0      13951   plib035_rcu.o
+       328         80          0          9          0      40469   rcu.o
+        26          0          0          8          0       3375   retarget.o
+       256         34          0          0          0       1204   retarget_conf.o
+        64         26        344          0       1536        892   startup_k1921vk035.o
+       368         34          0          8          0       2906   system_k1921vk035.o
+        42          4          0          0          0       3994   vk035_it.o
+
+    ----------------------------------------------------------------------
+      3870        964        376        420       1536     296956   Object Totals
+         0          0         32          0          0          0   (incl. Generated)
+         8          0          0          3          0          0   (incl. Padding)
+
+    ----------------------------------------------------------------------
+
+      Code (inc. data)   RO Data    RW Data    ZI Data      Debug   Library Member Name
+
+        90          0          0          0          0          0   __dczerorl2.o
+         8          0          0          0          0         68   __main.o
+       284          0          0          0          0        156   __printf_wp.o
+         0          0          0          0          0          0   __rtentry.o
+        12          0          0          0          0          0   __rtentry2.o
+         6          0          0          0          0          0   __rtentry4.o
+        52          8          0          0          0          0   __scatter.o
+        28          0          0          0          0          0   __scatter_zi.o
+        44          0          0          0          0        108   _printf_char.o
+        48          6          0          0          0         96   _printf_char_common.o
+        36          4          0          0          0         80   _printf_char_file.o
+         6          0          0          0          0          0   _printf_d.o
+       120         16          0          0          0         92   _printf_dec.o
+       178          0          0          0          0         88   _printf_intcommon.o
+        78          0          0          0          0        108   _printf_pad.o
+         0          0          0          0          0          0   _printf_percent.o
+         4          0          0          0          0          0   _printf_percent_end.o
+         6          0          0          0          0          0   _printf_s.o
+        82          0          0          0          0         80   _printf_str.o
+        18          0          0          0          0         80   exit.o
+         6          0          0          0          0        152   heapauxi.o
+         2          0          0          0          0          0   libinit.o
+         6          0          0          0          0          0   libinit2.o
+         2          0          0          0          0          0   libshutdown.o
+         2          0          0          0          0          0   libshutdown2.o
+         8          4          0          0         96         68   libspace.o
+        24          4          0          0          0         84   noretval__2printf.o
+         2          0          0          0          0          0   rtexit.o
+        10          0          0          0          0          0   rtexit2.o
+        74          0          0          0          0         80   sys_stackheap_outer.o
+         2          0          0          0          0         68   use_no_semi.o
+       688        140          0          0          0        256   ddiv.o
+        94          4          0          0          0        140   dfix.o
+        38          0          0          0          0        116   dflt_clz.o
+       156          4          0          0          0        140   dnaninf.o
+        12          0          0          0          0        116   dretinf.o
+        10          0          0          0          0        116   fpinit.o
+         0          0          0          0          0          0   usenofp.o
+
+    ----------------------------------------------------------------------
+      2246        190          0          0        100       2292   Library Totals
+        10          0          0          0          4          0   (incl. Padding)
+
+    ----------------------------------------------------------------------
+
+      Code (inc. data)   RO Data    RW Data    ZI Data      Debug   Library Name
+
+      1238         42          0          0         96       1408   c_w.l
+       998        148          0          0          0        884   fz_wm.l
+
+    ----------------------------------------------------------------------
+      2246        190          0          0        100       2292   Library Totals
+
+    ----------------------------------------------------------------------
+
+==============================================================================
+
+
+      Code (inc. data)   RO Data    RW Data    ZI Data      Debug   
+
+      6116       1154        376        420       1636     294324   Grand Totals
+      6116       1154        376         36       1636     294324   ELF Image Totals (compressed)
+      6116       1154        376         36          0          0   ROM Totals
+
+==============================================================================
+
+    Total RO  Size (Code + RO Data)                 6492 (   6.34kB)
+    Total RW  Size (RW Data + ZI Data)              2056 (   2.01kB)
+    Total ROM Size (Code + RO Data + RW Data)       6528 (   6.38kB)
+
+==============================================================================
+

Listings/startup_k1921vk035.lst

@@ -0,0 +1,1961 @@
+
+
+
+ARM Macro Assembler    Page 1 
+
+
+    1 00000000         ;******************** (C) COPYRIGHT 2018 NIIET *********
+                       ***********
+    2 00000000         ;* File Name          : startup_K1921VK035.s
+    3 00000000         ;* Author             : NIIET 
+    4 00000000         ;* Version            : V1.7
+    5 00000000         ;* Date               : 02.05.2018
+    6 00000000         ;* Description        : K1921VK035 vector table for MDK-
+                       ARM 
+    7 00000000         ;*                      toolchain.  
+    8 00000000         ;*                      This module performs:
+    9 00000000         ;*                      - Set the initial SP
+   10 00000000         ;*                      - Set the initial PC == Reset_Ha
+                       ndler
+   11 00000000         ;*                      - Set the vector table entries w
+                       ith the exceptions ISR address
+   12 00000000         ;*                      - Configure the clock system
+   13 00000000         ;*                      - Branches to __main in the C li
+                       brary (which eventually
+   14 00000000         ;*                        calls main()).
+   15 00000000         ;*                      After Reset the CortexM4 process
+                       or is in Thread mode,
+   16 00000000         ;*                      priority is Privileged, and the 
+                       Stack is set to Main.
+   17 00000000         ;* <<< Use Configuration Wizard in Context Menu >>>   
+   18 00000000         ;*******************************************************
+                       ************************
+   19 00000000         ; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS A
+                       T PROVIDING CUSTOMERS
+   20 00000000         ; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN OR
+                       DER FOR THEM TO SAVE TIME.
+   21 00000000         ; AS A RESULT, NIIET SHALL NOT BE HELD LIABLE FOR ANY DI
+                       RECT,
+   22 00000000         ; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY 
+                       CLAIMS ARISING FROM THE
+   23 00000000         ; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOM
+                       ERS OF THE CODING
+   24 00000000         ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR 
+                       PRODUCTS.
+   25 00000000         ;*******************************************************
+                       ************************
+   26 00000000         
+   27 00000000         ; Amount of memory (in bytes) allocated for Stack
+   28 00000000         ; Tailor this value to your application needs
+   29 00000000         ; <h> Stack Configuration
+   30 00000000         ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+   31 00000000         ; </h>
+   32 00000000         
+   33 00000000 00000400 
+                       Stack_Size
+                               EQU              0x00000400
+   34 00000000         
+   35 00000000                 AREA             STACK, NOINIT, READWRITE, ALIGN
+=3
+   36 00000000         Stack_Mem
+                               SPACE            Stack_Size
+   37 00000400         __initial_sp
+   38 00000400         
+   39 00000400         
+   40 00000400         ; <h> Heap Configuration
+
+
+
+ARM Macro Assembler    Page 2 
+
+
+   41 00000400         ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+   42 00000400         ; </h>
+   43 00000400         
+   44 00000400 00000200 
+                       Heap_Size
+                               EQU              0x00000200
+   45 00000400         
+   46 00000400                 AREA             HEAP, NOINIT, READWRITE, ALIGN=
+3
+   47 00000000         __heap_base
+   48 00000000         Heap_Mem
+                               SPACE            Heap_Size
+   49 00000200         __heap_limit
+   50 00000200         
+   51 00000200                 PRESERVE8
+   52 00000200                 THUMB
+   53 00000200         
+   54 00000200         
+   55 00000200         ; Vector Table Mapped to Address 0 at Reset
+   56 00000200                 AREA             RESET, DATA, READONLY
+   57 00000000                 EXPORT           __Vectors
+   58 00000000                 EXPORT           __Vectors_End
+   59 00000000                 EXPORT           __Vectors_Size
+   60 00000000         
+   61 00000000 00000000 
+                       __Vectors
+                               DCD              __initial_sp ; Top of Stack
+   62 00000004 00000000        DCD              Reset_Handler ; Reset Handler
+   63 00000008 00000000        DCD              NMI_Handler ; NMI Handler
+   64 0000000C 00000000        DCD              HardFault_Handler ; Hard Fault 
+                                                            Handler
+   65 00000010 00000000        DCD              MemManage_Handler 
+                                                            ; MPU Fault Handler
+                                                            
+   66 00000014 00000000        DCD              BusFault_Handler 
+                                                            ; Bus Fault Handler
+                                                            
+   67 00000018 00000000        DCD              UsageFault_Handler ; Usage Faul
+                                                            t Handler
+   68 0000001C 00000000        DCD              0           ; Reserved
+   69 00000020 00000000        DCD              0           ; Reserved
+   70 00000024 00000000        DCD              0           ; Reserved
+   71 00000028 00000000        DCD              0           ; Reserved
+   72 0000002C 00000000        DCD              SVC_Handler ; SVCall Handler
+   73 00000030 00000000        DCD              DebugMon_Handler ; Debug Monito
+                                                            r Handler
+   74 00000034 00000000        DCD              0           ; Reserved
+   75 00000038 00000000        DCD              PendSV_Handler ; PendSV Handler
+                                                            
+   76 0000003C 00000000        DCD              SysTick_Handler 
+                                                            ; SysTick Handler
+   77 00000040         
+   78 00000040         ; External Interrupts
+   79 00000040 00000000        DCD              WDT_IRQHandler ; Watchdog timer
+                                                             interrupt
+   80 00000044 00000000        DCD              RCU_IRQHandler ; Reset and cloc
+                                                            k unit interrupt
+   81 00000048 00000000        DCD              MFLASH_IRQHandler 
+                                                            ; MFLASH interrupt
+
+
+
+ARM Macro Assembler    Page 3 
+
+
+   82 0000004C 00000000        DCD              GPIOA_IRQHandler 
+                                                            ; GPIO A interrupt
+   83 00000050 00000000        DCD              GPIOB_IRQHandler 
+                                                            ; GPIO B interrupt
+   84 00000054 00000000        DCD              DMA_CH0_IRQHandler ; DMA channe
+                                                            l 0 interrupt
+   85 00000058 00000000        DCD              DMA_CH1_IRQHandler ; DMA channe
+                                                            l 1 interrupt
+   86 0000005C 00000000        DCD              DMA_CH2_IRQHandler ; DMA channe
+                                                            l 2 interrupt
+   87 00000060 00000000        DCD              DMA_CH3_IRQHandler ; DMA channe
+                                                            l 3 interrupt
+   88 00000064 00000000        DCD              DMA_CH4_IRQHandler ; DMA channe
+                                                            l 4 interrupt
+   89 00000068 00000000        DCD              DMA_CH5_IRQHandler ; DMA channe
+                                                            l 5 interrupt
+   90 0000006C 00000000        DCD              DMA_CH6_IRQHandler ; DMA channe
+                                                            l 6 interrupt
+   91 00000070 00000000        DCD              DMA_CH7_IRQHandler ; DMA channe
+                                                            l 7 interrupt
+   92 00000074 00000000        DCD              DMA_CH8_IRQHandler ; DMA channe
+                                                            l 8 interrupt
+   93 00000078 00000000        DCD              DMA_CH9_IRQHandler ; DMA channe
+                                                            l 9 interrupt
+   94 0000007C 00000000        DCD              DMA_CH10_IRQHandler ; DMA chann
+                                                            el 10 interrupt
+   95 00000080 00000000        DCD              DMA_CH11_IRQHandler ; DMA chann
+                                                            el 11 interrupt
+   96 00000084 00000000        DCD              DMA_CH12_IRQHandler ; DMA chann
+                                                            el 12 interrupt
+   97 00000088 00000000        DCD              DMA_CH13_IRQHandler ; DMA chann
+                                                            el 13 interrupt
+   98 0000008C 00000000        DCD              DMA_CH14_IRQHandler ; DMA chann
+                                                            el 14 interrupt
+   99 00000090 00000000        DCD              DMA_CH15_IRQHandler ; DMA chann
+                                                            el 15 interrupt
+  100 00000094 00000000        DCD              TMR0_IRQHandler 
+                                                            ; Timer 0 interrupt
+                                                            
+  101 00000098 00000000        DCD              TMR1_IRQHandler 
+                                                            ; Timer 1 interrupt
+                                                            
+  102 0000009C 00000000        DCD              TMR2_IRQHandler 
+                                                            ; Timer 2 interrupt
+                                                            
+  103 000000A0 00000000        DCD              TMR3_IRQHandler 
+                                                            ; Timer 3 interrupt
+                                                            
+  104 000000A4 00000000        DCD              UART0_TD_IRQHandler ; UART0 Tra
+                                                            nsmit Done interrup
+                                                            t
+  105 000000A8 00000000        DCD              UART0_RX_IRQHandler ; UART0 Rec
+                                                            ieve interrupt
+  106 000000AC 00000000        DCD              UART0_TX_IRQHandler ; UART0 Tra
+                                                            nsmit interrupt
+  107 000000B0 00000000        DCD              UART0_E_RT_IRQHandler ; UART0 E
+                                                            rror and Receive Ti
+                                                            meout interrupt
+  108 000000B4 00000000        DCD              UART1_TD_IRQHandler ; UART1 Tra
+
+
+
+ARM Macro Assembler    Page 4 
+
+
+                                                            nsmit Done interrup
+                                                            t
+  109 000000B8 00000000        DCD              UART1_RX_IRQHandler ; UART1 Rec
+                                                            ieve interrupt
+  110 000000BC 00000000        DCD              UART1_TX_IRQHandler ; UART1 Tra
+                                                            nsmit interrupt
+  111 000000C0 00000000        DCD              UART1_E_RT_IRQHandler ; UART1 E
+                                                            rror and Receive Ti
+                                                            meout interrupt
+  112 000000C4 00000000        DCD              SPI_RO_RT_IRQHandler ; SPI RX F
+                                                            IFO overrun and Rec
+                                                            eive Timeout interr
+                                                            upt
+  113 000000C8 00000000        DCD              SPI_RX_IRQHandler ; SPI Receive
+                                                             interrupt
+  114 000000CC 00000000        DCD              SPI_TX_IRQHandler ; SPI Transmi
+                                                            t interrupt
+  115 000000D0 00000000        DCD              I2C_IRQHandler ; I2C interrupt
+  116 000000D4 00000000        DCD              ECAP0_IRQHandler 
+                                                            ; ECAP0 interrupt
+  117 000000D8 00000000        DCD              ECAP1_IRQHandler 
+                                                            ; ECAP1 interrupt
+  118 000000DC 00000000        DCD              ECAP2_IRQHandler 
+                                                            ; ECAP2 interrupt
+  119 000000E0 00000000        DCD              PWM0_IRQHandler 
+                                                            ; PWM0 interrupt
+  120 000000E4 00000000        DCD              PWM0_HD_IRQHandler 
+                                                            ; PWM0 HD interrupt
+                                                            
+  121 000000E8 00000000        DCD              PWM0_TZ_IRQHandler 
+                                                            ; PWM0 TZ interrupt
+                                                            
+  122 000000EC 00000000        DCD              PWM1_IRQHandler 
+                                                            ; PWM1 interrupt
+  123 000000F0 00000000        DCD              PWM1_HD_IRQHandler 
+                                                            ; PWM1 HD interrupt
+                                                            
+  124 000000F4 00000000        DCD              PWM1_TZ_IRQHandler 
+                                                            ; PWM1 TZ interrupt
+                                                            
+  125 000000F8 00000000        DCD              PWM2_IRQHandler 
+                                                            ; PWM2 interrupt
+  126 000000FC 00000000        DCD              PWM2_HD_IRQHandler 
+                                                            ; PWM2 HD interrupt
+                                                            
+  127 00000100 00000000        DCD              PWM2_TZ_IRQHandler 
+                                                            ; PWM2 TZ interrupt
+                                                            
+  128 00000104 00000000        DCD              QEP_IRQHandler ; QEP interrupt
+  129 00000108 00000000        DCD              ADC_SEQ0_IRQHandler ; ADC Seque
+                                                            ncer 0 interrupt
+  130 0000010C 00000000        DCD              ADC_SEQ1_IRQHandler ; ADC Seque
+                                                            ncer 1 interrupt
+  131 00000110 00000000        DCD              ADC_DC_IRQHandler ; ADC Digital
+                                                             Comparator interru
+                                                            pt
+  132 00000114 00000000        DCD              CAN0_IRQHandler 
+                                                            ; CAN0 interrupt
+  133 00000118 00000000        DCD              CAN1_IRQHandler 
+
+
+
+ARM Macro Assembler    Page 5 
+
+
+                                                            ; CAN1 interrupt
+  134 0000011C 00000000        DCD              CAN2_IRQHandler 
+                                                            ; CAN2 interrupt
+  135 00000120 00000000        DCD              CAN3_IRQHandler 
+                                                            ; CAN3 interrupt
+  136 00000124 00000000        DCD              CAN4_IRQHandler 
+                                                            ; CAN4 interrupt
+  137 00000128 00000000        DCD              CAN5_IRQHandler 
+                                                            ; CAN5 interrupt
+  138 0000012C 00000000        DCD              CAN6_IRQHandler 
+                                                            ; CAN6 interrupt
+  139 00000130 00000000        DCD              CAN7_IRQHandler 
+                                                            ; CAN7 interrupt
+  140 00000134 00000000        DCD              CAN8_IRQHandler 
+                                                            ; CAN8 interrupt
+  141 00000138 00000000        DCD              CAN9_IRQHandler 
+                                                            ; CAN9 interrupt
+  142 0000013C 00000000        DCD              CAN10_IRQHandler 
+                                                            ; CAN10 interrupt
+  143 00000140 00000000        DCD              CAN11_IRQHandler 
+                                                            ; CAN11 interrupt
+  144 00000144 00000000        DCD              CAN12_IRQHandler 
+                                                            ; CAN12 interrupt
+  145 00000148 00000000        DCD              CAN13_IRQHandler 
+                                                            ; CAN13 interrupt
+  146 0000014C 00000000        DCD              CAN14_IRQHandler 
+                                                            ; CAN14 interrupt
+  147 00000150 00000000        DCD              CAN15_IRQHandler 
+                                                            ; CAN15 interrupt
+  148 00000154 00000000        DCD              FPU_IRQHandler ; FPU exception 
+                                                            interrupt
+  149 00000158         
+  150 00000158         __Vectors_End
+  151 00000158         
+  152 00000158 00000158 
+                       __Vectors_Size
+                               EQU              __Vectors_End - __Vectors
+  153 00000158         
+  154 00000158                 AREA             |.text|, CODE, READONLY
+  155 00000000         
+  156 00000000         ; Reset handler
+  157 00000000         Reset_Handler
+                               PROC
+  158 00000000                 EXPORT           Reset_Handler             [WEAK
+]
+  159 00000000                 IMPORT           __main
+  160 00000000                 IMPORT           SystemInit
+  161 00000000 4809            LDR              R0, =SystemInit
+  162 00000002 4780            BLX              R0
+  163 00000004 4809            LDR              R0, =__main
+  164 00000006 4700            BX               R0
+  165 00000008                 ENDP
+  166 00000008         
+  167 00000008         ; Dummy Exception Handlers (infinite loops which can be 
+                       modified)
+  168 00000008         
+  169 00000008         NMI_Handler
+                               PROC
+  170 00000008                 EXPORT           NMI_Handler                [WEA
+
+
+
+ARM Macro Assembler    Page 6 
+
+
+K]
+  171 00000008 E7FE            B                .
+  172 0000000A                 ENDP
+  174 0000000A         HardFault_Handler
+                               PROC
+  175 0000000A                 EXPORT           HardFault_Handler          [WEA
+K]
+  176 0000000A E7FE            B                .
+  177 0000000C                 ENDP
+  179 0000000C         MemManage_Handler
+                               PROC
+  180 0000000C                 EXPORT           MemManage_Handler          [WEA
+K]
+  181 0000000C E7FE            B                .
+  182 0000000E                 ENDP
+  184 0000000E         BusFault_Handler
+                               PROC
+  185 0000000E                 EXPORT           BusFault_Handler           [WEA
+K]
+  186 0000000E E7FE            B                .
+  187 00000010                 ENDP
+  189 00000010         UsageFault_Handler
+                               PROC
+  190 00000010                 EXPORT           UsageFault_Handler         [WEA
+K]
+  191 00000010 E7FE            B                .
+  192 00000012                 ENDP
+  193 00000012         SVC_Handler
+                               PROC
+  194 00000012                 EXPORT           SVC_Handler                [WEA
+K]
+  195 00000012 E7FE            B                .
+  196 00000014                 ENDP
+  198 00000014         DebugMon_Handler
+                               PROC
+  199 00000014                 EXPORT           DebugMon_Handler           [WEA
+K]
+  200 00000014 E7FE            B                .
+  201 00000016                 ENDP
+  202 00000016         PendSV_Handler
+                               PROC
+  203 00000016                 EXPORT           PendSV_Handler             [WEA
+K]
+  204 00000016 E7FE            B                .
+  205 00000018                 ENDP
+  206 00000018         SysTick_Handler
+                               PROC
+  207 00000018                 EXPORT           SysTick_Handler            [WEA
+K]
+  208 00000018 E7FE            B                .
+  209 0000001A                 ENDP
+  210 0000001A         
+  211 0000001A         Default_Handler
+                               PROC
+  212 0000001A         
+  213 0000001A                 EXPORT           WDT_IRQHandler           [WEAK]
+  214 0000001A                 EXPORT           RCU_IRQHandler           [WEAK]
+  215 0000001A                 EXPORT           MFLASH_IRQHandler           [WE
+AK]
+
+
+
+ARM Macro Assembler    Page 7 
+
+
+  216 0000001A                 EXPORT           GPIOA_IRQHandler           [WEA
+K]
+  217 0000001A                 EXPORT           GPIOB_IRQHandler           [WEA
+K]
+  218 0000001A                 EXPORT           DMA_CH0_IRQHandler           [W
+EAK]
+  219 0000001A                 EXPORT           DMA_CH1_IRQHandler           [W
+EAK]
+  220 0000001A                 EXPORT           DMA_CH2_IRQHandler           [W
+EAK]
+  221 0000001A                 EXPORT           DMA_CH3_IRQHandler           [W
+EAK]
+  222 0000001A                 EXPORT           DMA_CH4_IRQHandler           [W
+EAK]
+  223 0000001A                 EXPORT           DMA_CH5_IRQHandler           [W
+EAK]
+  224 0000001A                 EXPORT           DMA_CH6_IRQHandler           [W
+EAK]
+  225 0000001A                 EXPORT           DMA_CH7_IRQHandler           [W
+EAK]
+  226 0000001A                 EXPORT           DMA_CH8_IRQHandler           [W
+EAK]
+  227 0000001A                 EXPORT           DMA_CH9_IRQHandler           [W
+EAK]
+  228 0000001A                 EXPORT           DMA_CH10_IRQHandler           [
+WEAK]
+  229 0000001A                 EXPORT           DMA_CH11_IRQHandler           [
+WEAK]
+  230 0000001A                 EXPORT           DMA_CH12_IRQHandler           [
+WEAK]
+  231 0000001A                 EXPORT           DMA_CH13_IRQHandler           [
+WEAK]
+  232 0000001A                 EXPORT           DMA_CH14_IRQHandler           [
+WEAK]
+  233 0000001A                 EXPORT           DMA_CH15_IRQHandler           [
+WEAK]
+  234 0000001A                 EXPORT           TMR0_IRQHandler           [WEAK
+]
+  235 0000001A                 EXPORT           TMR1_IRQHandler           [WEAK
+]
+  236 0000001A                 EXPORT           TMR2_IRQHandler           [WEAK
+]
+  237 0000001A                 EXPORT           TMR3_IRQHandler           [WEAK
+]
+  238 0000001A                 EXPORT           UART0_TD_IRQHandler           [
+WEAK]
+  239 0000001A                 EXPORT           UART0_RX_IRQHandler           [
+WEAK]
+  240 0000001A                 EXPORT           UART0_TX_IRQHandler           [
+WEAK]
+  241 0000001A                 EXPORT           UART0_E_RT_IRQHandler          
+ [WEAK]
+  242 0000001A                 EXPORT           UART1_TD_IRQHandler           [
+WEAK]
+  243 0000001A                 EXPORT           UART1_RX_IRQHandler           [
+WEAK]
+  244 0000001A                 EXPORT           UART1_TX_IRQHandler           [
+WEAK]
+  245 0000001A                 EXPORT           UART1_E_RT_IRQHandler          
+
+
+
+ARM Macro Assembler    Page 8 
+
+
+ [WEAK]
+  246 0000001A                 EXPORT           SPI_RO_RT_IRQHandler           
+[WEAK]
+  247 0000001A                 EXPORT           SPI_RX_IRQHandler           [WE
+AK]
+  248 0000001A                 EXPORT           SPI_TX_IRQHandler           [WE
+AK]
+  249 0000001A                 EXPORT           I2C_IRQHandler           [WEAK]
+  250 0000001A                 EXPORT           ECAP0_IRQHandler           [WEA
+K]
+  251 0000001A                 EXPORT           ECAP1_IRQHandler           [WEA
+K]
+  252 0000001A                 EXPORT           ECAP2_IRQHandler           [WEA
+K]
+  253 0000001A                 EXPORT           PWM0_IRQHandler           [WEAK
+]
+  254 0000001A                 EXPORT           PWM0_HD_IRQHandler           [W
+EAK]
+  255 0000001A                 EXPORT           PWM0_TZ_IRQHandler           [W
+EAK]
+  256 0000001A                 EXPORT           PWM1_IRQHandler           [WEAK
+]
+  257 0000001A                 EXPORT           PWM1_HD_IRQHandler           [W
+EAK]
+  258 0000001A                 EXPORT           PWM1_TZ_IRQHandler           [W
+EAK]
+  259 0000001A                 EXPORT           PWM2_IRQHandler           [WEAK
+]
+  260 0000001A                 EXPORT           PWM2_HD_IRQHandler           [W
+EAK]
+  261 0000001A                 EXPORT           PWM2_TZ_IRQHandler           [W
+EAK]
+  262 0000001A                 EXPORT           QEP_IRQHandler           [WEAK]
+  263 0000001A                 EXPORT           ADC_SEQ0_IRQHandler           [
+WEAK]
+  264 0000001A                 EXPORT           ADC_SEQ1_IRQHandler           [
+WEAK]
+  265 0000001A                 EXPORT           ADC_DC_IRQHandler           [WE
+AK]
+  266 0000001A                 EXPORT           CAN0_IRQHandler           [WEAK
+]
+  267 0000001A                 EXPORT           CAN1_IRQHandler           [WEAK
+]
+  268 0000001A                 EXPORT           CAN2_IRQHandler           [WEAK
+]
+  269 0000001A                 EXPORT           CAN3_IRQHandler           [WEAK
+]
+  270 0000001A                 EXPORT           CAN4_IRQHandler           [WEAK
+]
+  271 0000001A                 EXPORT           CAN5_IRQHandler           [WEAK
+]
+  272 0000001A                 EXPORT           CAN6_IRQHandler           [WEAK
+]
+  273 0000001A                 EXPORT           CAN7_IRQHandler           [WEAK
+]
+  274 0000001A                 EXPORT           CAN8_IRQHandler           [WEAK
+]
+  275 0000001A                 EXPORT           CAN9_IRQHandler           [WEAK
+]
+
+
+
+ARM Macro Assembler    Page 9 
+
+
+  276 0000001A                 EXPORT           CAN10_IRQHandler           [WEA
+K]
+  277 0000001A                 EXPORT           CAN11_IRQHandler           [WEA
+K]
+  278 0000001A                 EXPORT           CAN12_IRQHandler           [WEA
+K]
+  279 0000001A                 EXPORT           CAN13_IRQHandler           [WEA
+K]
+  280 0000001A                 EXPORT           CAN14_IRQHandler           [WEA
+K]
+  281 0000001A                 EXPORT           CAN15_IRQHandler           [WEA
+K]
+  282 0000001A                 EXPORT           FPU_IRQHandler           [WEAK]
+  283 0000001A         
+  284 0000001A         
+  285 0000001A         
+  286 0000001A         WDT_IRQHandler
+  287 0000001A         RCU_IRQHandler
+  288 0000001A         MFLASH_IRQHandler
+  289 0000001A         GPIOA_IRQHandler
+  290 0000001A         GPIOB_IRQHandler
+  291 0000001A         DMA_CH0_IRQHandler
+  292 0000001A         DMA_CH1_IRQHandler
+  293 0000001A         DMA_CH2_IRQHandler
+  294 0000001A         DMA_CH3_IRQHandler
+  295 0000001A         DMA_CH4_IRQHandler
+  296 0000001A         DMA_CH5_IRQHandler
+  297 0000001A         DMA_CH6_IRQHandler
+  298 0000001A         DMA_CH7_IRQHandler
+  299 0000001A         DMA_CH8_IRQHandler
+  300 0000001A         DMA_CH9_IRQHandler
+  301 0000001A         DMA_CH10_IRQHandler
+  302 0000001A         DMA_CH11_IRQHandler
+  303 0000001A         DMA_CH12_IRQHandler
+  304 0000001A         DMA_CH13_IRQHandler
+  305 0000001A         DMA_CH14_IRQHandler
+  306 0000001A         DMA_CH15_IRQHandler
+  307 0000001A         TMR0_IRQHandler
+  308 0000001A         TMR1_IRQHandler
+  309 0000001A         TMR2_IRQHandler
+  310 0000001A         TMR3_IRQHandler
+  311 0000001A         UART0_TD_IRQHandler
+  312 0000001A         UART0_RX_IRQHandler
+  313 0000001A         UART0_TX_IRQHandler
+  314 0000001A         UART0_E_RT_IRQHandler
+  315 0000001A         UART1_TD_IRQHandler
+  316 0000001A         UART1_RX_IRQHandler
+  317 0000001A         UART1_TX_IRQHandler
+  318 0000001A         UART1_E_RT_IRQHandler
+  319 0000001A         SPI_RO_RT_IRQHandler
+  320 0000001A         SPI_RX_IRQHandler
+  321 0000001A         SPI_TX_IRQHandler
+  322 0000001A         I2C_IRQHandler
+  323 0000001A         ECAP0_IRQHandler
+  324 0000001A         ECAP1_IRQHandler
+  325 0000001A         ECAP2_IRQHandler
+  326 0000001A         PWM0_IRQHandler
+  327 0000001A         PWM0_HD_IRQHandler
+  328 0000001A         PWM0_TZ_IRQHandler
+
+
+
+ARM Macro Assembler    Page 10 
+
+
+  329 0000001A         PWM1_IRQHandler
+  330 0000001A         PWM1_HD_IRQHandler
+  331 0000001A         PWM1_TZ_IRQHandler
+  332 0000001A         PWM2_IRQHandler
+  333 0000001A         PWM2_HD_IRQHandler
+  334 0000001A         PWM2_TZ_IRQHandler
+  335 0000001A         QEP_IRQHandler
+  336 0000001A         ADC_SEQ0_IRQHandler
+  337 0000001A         ADC_SEQ1_IRQHandler
+  338 0000001A         ADC_DC_IRQHandler
+  339 0000001A         CAN0_IRQHandler
+  340 0000001A         CAN1_IRQHandler
+  341 0000001A         CAN2_IRQHandler
+  342 0000001A         CAN3_IRQHandler
+  343 0000001A         CAN4_IRQHandler
+  344 0000001A         CAN5_IRQHandler
+  345 0000001A         CAN6_IRQHandler
+  346 0000001A         CAN7_IRQHandler
+  347 0000001A         CAN8_IRQHandler
+  348 0000001A         CAN9_IRQHandler
+  349 0000001A         CAN10_IRQHandler
+  350 0000001A         CAN11_IRQHandler
+  351 0000001A         CAN12_IRQHandler
+  352 0000001A         CAN13_IRQHandler
+  353 0000001A         CAN14_IRQHandler
+  354 0000001A         CAN15_IRQHandler
+  355 0000001A         FPU_IRQHandler
+  356 0000001A         
+  357 0000001A         
+  358 0000001A         
+  359 0000001A E7FE            B                .
+  360 0000001C         
+  361 0000001C                 ENDP
+  362 0000001C         
+  363 0000001C                 ALIGN
+  364 0000001C         
+  365 0000001C         ;*******************************************************
+                       ************************
+  366 0000001C         ; User Stack and Heap initialization
+  367 0000001C         ;*******************************************************
+                       ************************
+  368 0000001C                 IF               :DEF:__MICROLIB
+  375 0000001C         
+  376 0000001C                 IMPORT           __use_two_region_memory
+  377 0000001C                 EXPORT           __user_initial_stackheap
+  378 0000001C         
+  379 0000001C         __user_initial_stackheap
+  380 0000001C         
+  381 0000001C 4804            LDR              R0, =  Heap_Mem
+  382 0000001E 4905            LDR              R1, =(Stack_Mem + Stack_Size)
+  383 00000020 4A05            LDR              R2, = (Heap_Mem +  Heap_Size)
+  384 00000022 4B06            LDR              R3, = Stack_Mem
+  385 00000024 4770            BX               LR
+  386 00000026         
+  387 00000026 00 00           ALIGN
+  388 00000028         
+  389 00000028                 ENDIF
+  390 00000028         
+  391 00000028                 END
+
+
+
+ARM Macro Assembler    Page 11 
+
+
+              00000000 
+              00000000 
+              00000000 
+              00000400 
+              00000200 
+              00000000 
+Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M4.fp.sp --apcs=
+interwork --depend=.\objects\startup_k1921vk035.d -o.\objects\startup_k1921vk03
+5.o -IC:\Users\I\AppData\Local\Arm\Packs\NIIET\K1921VK035_DFP\2.0.6\Device\Incl
+ude --predefine="__UVISION_VERSION SETA 538" --predefine="K1921VK035 SETA 1" --
+list=.\listings\startup_k1921vk035.lst platform\Device\NIIET\K1921VK035\Source\
+ARM\startup_K1921VK035.s
+
+
+
+ARM Macro Assembler    Page 1 Alphabetic symbol ordering
+Relocatable symbols
+
+STACK 00000000
+
+Symbol: STACK
+   Definitions
+      At line 35 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+   Uses
+      None
+Comment: STACK unused
+Stack_Mem 00000000
+
+Symbol: Stack_Mem
+   Definitions
+      At line 36 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+   Uses
+      At line 382 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 384 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+__initial_sp 00000400
+
+Symbol: __initial_sp
+   Definitions
+      At line 37 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+   Uses
+      At line 61 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+Comment: __initial_sp used once
+3 symbols
+
+
+
+ARM Macro Assembler    Page 1 Alphabetic symbol ordering
+Relocatable symbols
+
+HEAP 00000000
+
+Symbol: HEAP
+   Definitions
+      At line 46 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+   Uses
+      None
+Comment: HEAP unused
+Heap_Mem 00000000
+
+Symbol: Heap_Mem
+   Definitions
+      At line 48 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+   Uses
+      At line 381 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 383 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+__heap_base 00000000
+
+Symbol: __heap_base
+   Definitions
+      At line 47 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+   Uses
+      None
+Comment: __heap_base unused
+__heap_limit 00000200
+
+Symbol: __heap_limit
+   Definitions
+      At line 49 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+   Uses
+      None
+Comment: __heap_limit unused
+4 symbols
+
+
+
+ARM Macro Assembler    Page 1 Alphabetic symbol ordering
+Relocatable symbols
+
+RESET 00000000
+
+Symbol: RESET
+   Definitions
+      At line 56 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+   Uses
+      None
+Comment: RESET unused
+__Vectors 00000000
+
+Symbol: __Vectors
+   Definitions
+      At line 61 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+   Uses
+      At line 57 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 152 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+__Vectors_End 00000158
+
+Symbol: __Vectors_End
+   Definitions
+      At line 150 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 58 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 152 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+3 symbols
+
+
+
+ARM Macro Assembler    Page 1 Alphabetic symbol ordering
+Relocatable symbols
+
+.text 00000000
+
+Symbol: .text
+   Definitions
+      At line 154 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      None
+Comment: .text unused
+ADC_DC_IRQHandler 0000001A
+
+Symbol: ADC_DC_IRQHandler
+   Definitions
+      At line 338 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 131 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 265 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+ADC_SEQ0_IRQHandler 0000001A
+
+Symbol: ADC_SEQ0_IRQHandler
+   Definitions
+      At line 336 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 129 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 263 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+ADC_SEQ1_IRQHandler 0000001A
+
+Symbol: ADC_SEQ1_IRQHandler
+   Definitions
+      At line 337 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 130 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 264 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+BusFault_Handler 0000000E
+
+Symbol: BusFault_Handler
+   Definitions
+      At line 184 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 66 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 185 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+CAN0_IRQHandler 0000001A
+
+
+
+
+ARM Macro Assembler    Page 2 Alphabetic symbol ordering
+Relocatable symbols
+
+Symbol: CAN0_IRQHandler
+   Definitions
+      At line 339 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 132 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 266 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+CAN10_IRQHandler 0000001A
+
+Symbol: CAN10_IRQHandler
+   Definitions
+      At line 349 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 142 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 276 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+CAN11_IRQHandler 0000001A
+
+Symbol: CAN11_IRQHandler
+   Definitions
+      At line 350 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 143 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 277 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+CAN12_IRQHandler 0000001A
+
+Symbol: CAN12_IRQHandler
+   Definitions
+      At line 351 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 144 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 278 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+CAN13_IRQHandler 0000001A
+
+Symbol: CAN13_IRQHandler
+   Definitions
+      At line 352 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 145 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 279 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+CAN14_IRQHandler 0000001A
+
+
+
+ARM Macro Assembler    Page 3 Alphabetic symbol ordering
+Relocatable symbols
+
+
+Symbol: CAN14_IRQHandler
+   Definitions
+      At line 353 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 146 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 280 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+CAN15_IRQHandler 0000001A
+
+Symbol: CAN15_IRQHandler
+   Definitions
+      At line 354 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 147 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 281 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+CAN1_IRQHandler 0000001A
+
+Symbol: CAN1_IRQHandler
+   Definitions
+      At line 340 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 133 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 267 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+CAN2_IRQHandler 0000001A
+
+Symbol: CAN2_IRQHandler
+   Definitions
+      At line 341 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 134 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 268 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+CAN3_IRQHandler 0000001A
+
+Symbol: CAN3_IRQHandler
+   Definitions
+      At line 342 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 135 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 269 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+
+
+
+ARM Macro Assembler    Page 4 Alphabetic symbol ordering
+Relocatable symbols
+
+CAN4_IRQHandler 0000001A
+
+Symbol: CAN4_IRQHandler
+   Definitions
+      At line 343 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 136 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 270 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+CAN5_IRQHandler 0000001A
+
+Symbol: CAN5_IRQHandler
+   Definitions
+      At line 344 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 137 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 271 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+CAN6_IRQHandler 0000001A
+
+Symbol: CAN6_IRQHandler
+   Definitions
+      At line 345 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 138 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 272 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+CAN7_IRQHandler 0000001A
+
+Symbol: CAN7_IRQHandler
+   Definitions
+      At line 346 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 139 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 273 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+CAN8_IRQHandler 0000001A
+
+Symbol: CAN8_IRQHandler
+   Definitions
+      At line 347 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 140 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 274 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+
+
+ARM Macro Assembler    Page 5 Alphabetic symbol ordering
+Relocatable symbols
+
+
+CAN9_IRQHandler 0000001A
+
+Symbol: CAN9_IRQHandler
+   Definitions
+      At line 348 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 141 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 275 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+DMA_CH0_IRQHandler 0000001A
+
+Symbol: DMA_CH0_IRQHandler
+   Definitions
+      At line 291 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 84 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 218 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+DMA_CH10_IRQHandler 0000001A
+
+Symbol: DMA_CH10_IRQHandler
+   Definitions
+      At line 301 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 94 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 228 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+DMA_CH11_IRQHandler 0000001A
+
+Symbol: DMA_CH11_IRQHandler
+   Definitions
+      At line 302 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 95 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 229 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+DMA_CH12_IRQHandler 0000001A
+
+Symbol: DMA_CH12_IRQHandler
+   Definitions
+      At line 303 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 96 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 230 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+
+
+
+ARM Macro Assembler    Page 6 Alphabetic symbol ordering
+Relocatable symbols
+
+1921VK035.s
+
+DMA_CH13_IRQHandler 0000001A
+
+Symbol: DMA_CH13_IRQHandler
+   Definitions
+      At line 304 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 97 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 231 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+DMA_CH14_IRQHandler 0000001A
+
+Symbol: DMA_CH14_IRQHandler
+   Definitions
+      At line 305 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 98 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 232 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+DMA_CH15_IRQHandler 0000001A
+
+Symbol: DMA_CH15_IRQHandler
+   Definitions
+      At line 306 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 99 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 233 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+DMA_CH1_IRQHandler 0000001A
+
+Symbol: DMA_CH1_IRQHandler
+   Definitions
+      At line 292 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 85 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 219 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+DMA_CH2_IRQHandler 0000001A
+
+Symbol: DMA_CH2_IRQHandler
+   Definitions
+      At line 293 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 86 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+
+
+
+ARM Macro Assembler    Page 7 Alphabetic symbol ordering
+Relocatable symbols
+
+      At line 220 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+DMA_CH3_IRQHandler 0000001A
+
+Symbol: DMA_CH3_IRQHandler
+   Definitions
+      At line 294 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 87 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 221 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+DMA_CH4_IRQHandler 0000001A
+
+Symbol: DMA_CH4_IRQHandler
+   Definitions
+      At line 295 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 88 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 222 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+DMA_CH5_IRQHandler 0000001A
+
+Symbol: DMA_CH5_IRQHandler
+   Definitions
+      At line 296 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 89 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 223 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+DMA_CH6_IRQHandler 0000001A
+
+Symbol: DMA_CH6_IRQHandler
+   Definitions
+      At line 297 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 90 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 224 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+DMA_CH7_IRQHandler 0000001A
+
+Symbol: DMA_CH7_IRQHandler
+   Definitions
+      At line 298 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 91 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+
+
+
+ARM Macro Assembler    Page 8 Alphabetic symbol ordering
+Relocatable symbols
+
+921VK035.s
+      At line 225 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+DMA_CH8_IRQHandler 0000001A
+
+Symbol: DMA_CH8_IRQHandler
+   Definitions
+      At line 299 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 92 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 226 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+DMA_CH9_IRQHandler 0000001A
+
+Symbol: DMA_CH9_IRQHandler
+   Definitions
+      At line 300 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 93 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 227 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+DebugMon_Handler 00000014
+
+Symbol: DebugMon_Handler
+   Definitions
+      At line 198 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 73 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 199 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+Default_Handler 0000001A
+
+Symbol: Default_Handler
+   Definitions
+      At line 211 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      None
+Comment: Default_Handler unused
+ECAP0_IRQHandler 0000001A
+
+Symbol: ECAP0_IRQHandler
+   Definitions
+      At line 323 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 116 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 250 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+
+
+
+ARM Macro Assembler    Page 9 Alphabetic symbol ordering
+Relocatable symbols
+
+1921VK035.s
+
+ECAP1_IRQHandler 0000001A
+
+Symbol: ECAP1_IRQHandler
+   Definitions
+      At line 324 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 117 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 251 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+ECAP2_IRQHandler 0000001A
+
+Symbol: ECAP2_IRQHandler
+   Definitions
+      At line 325 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 118 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 252 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+FPU_IRQHandler 0000001A
+
+Symbol: FPU_IRQHandler
+   Definitions
+      At line 355 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 148 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 282 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+GPIOA_IRQHandler 0000001A
+
+Symbol: GPIOA_IRQHandler
+   Definitions
+      At line 289 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 82 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 216 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+GPIOB_IRQHandler 0000001A
+
+Symbol: GPIOB_IRQHandler
+   Definitions
+      At line 290 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 83 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+
+
+
+ARM Macro Assembler    Page 10 Alphabetic symbol ordering
+Relocatable symbols
+
+      At line 217 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+HardFault_Handler 0000000A
+
+Symbol: HardFault_Handler
+   Definitions
+      At line 174 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 64 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 175 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+I2C_IRQHandler 0000001A
+
+Symbol: I2C_IRQHandler
+   Definitions
+      At line 322 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 115 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 249 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+MFLASH_IRQHandler 0000001A
+
+Symbol: MFLASH_IRQHandler
+   Definitions
+      At line 288 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 81 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 215 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+MemManage_Handler 0000000C
+
+Symbol: MemManage_Handler
+   Definitions
+      At line 179 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 65 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 180 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+NMI_Handler 00000008
+
+Symbol: NMI_Handler
+   Definitions
+      At line 169 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 63 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+
+
+
+ARM Macro Assembler    Page 11 Alphabetic symbol ordering
+Relocatable symbols
+
+921VK035.s
+      At line 170 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+PWM0_HD_IRQHandler 0000001A
+
+Symbol: PWM0_HD_IRQHandler
+   Definitions
+      At line 327 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 120 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 254 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+PWM0_IRQHandler 0000001A
+
+Symbol: PWM0_IRQHandler
+   Definitions
+      At line 326 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 119 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 253 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+PWM0_TZ_IRQHandler 0000001A
+
+Symbol: PWM0_TZ_IRQHandler
+   Definitions
+      At line 328 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 121 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 255 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+PWM1_HD_IRQHandler 0000001A
+
+Symbol: PWM1_HD_IRQHandler
+   Definitions
+      At line 330 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 123 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 257 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+PWM1_IRQHandler 0000001A
+
+Symbol: PWM1_IRQHandler
+   Definitions
+      At line 329 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+
+
+
+ARM Macro Assembler    Page 12 Alphabetic symbol ordering
+Relocatable symbols
+
+      At line 122 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 256 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+PWM1_TZ_IRQHandler 0000001A
+
+Symbol: PWM1_TZ_IRQHandler
+   Definitions
+      At line 331 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 124 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 258 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+PWM2_HD_IRQHandler 0000001A
+
+Symbol: PWM2_HD_IRQHandler
+   Definitions
+      At line 333 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 126 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 260 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+PWM2_IRQHandler 0000001A
+
+Symbol: PWM2_IRQHandler
+   Definitions
+      At line 332 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 125 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 259 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+PWM2_TZ_IRQHandler 0000001A
+
+Symbol: PWM2_TZ_IRQHandler
+   Definitions
+      At line 334 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 127 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 261 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+PendSV_Handler 00000016
+
+Symbol: PendSV_Handler
+   Definitions
+      At line 202 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+
+
+ARM Macro Assembler    Page 13 Alphabetic symbol ordering
+Relocatable symbols
+
+   Uses
+      At line 75 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 203 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+QEP_IRQHandler 0000001A
+
+Symbol: QEP_IRQHandler
+   Definitions
+      At line 335 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 128 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 262 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+RCU_IRQHandler 0000001A
+
+Symbol: RCU_IRQHandler
+   Definitions
+      At line 287 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 80 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 214 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+Reset_Handler 00000000
+
+Symbol: Reset_Handler
+   Definitions
+      At line 157 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 62 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 158 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+SPI_RO_RT_IRQHandler 0000001A
+
+Symbol: SPI_RO_RT_IRQHandler
+   Definitions
+      At line 319 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 112 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 246 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+SPI_RX_IRQHandler 0000001A
+
+Symbol: SPI_RX_IRQHandler
+   Definitions
+      At line 320 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+
+
+
+ARM Macro Assembler    Page 14 Alphabetic symbol ordering
+Relocatable symbols
+
+1921VK035.s
+   Uses
+      At line 113 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 247 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+SPI_TX_IRQHandler 0000001A
+
+Symbol: SPI_TX_IRQHandler
+   Definitions
+      At line 321 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 114 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 248 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+SVC_Handler 00000012
+
+Symbol: SVC_Handler
+   Definitions
+      At line 193 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 72 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 194 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+SysTick_Handler 00000018
+
+Symbol: SysTick_Handler
+   Definitions
+      At line 206 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 76 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 207 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+TMR0_IRQHandler 0000001A
+
+Symbol: TMR0_IRQHandler
+   Definitions
+      At line 307 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 100 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 234 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+TMR1_IRQHandler 0000001A
+
+Symbol: TMR1_IRQHandler
+   Definitions
+
+
+
+ARM Macro Assembler    Page 15 Alphabetic symbol ordering
+Relocatable symbols
+
+      At line 308 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 101 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 235 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+TMR2_IRQHandler 0000001A
+
+Symbol: TMR2_IRQHandler
+   Definitions
+      At line 309 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 102 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 236 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+TMR3_IRQHandler 0000001A
+
+Symbol: TMR3_IRQHandler
+   Definitions
+      At line 310 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 103 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 237 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+UART0_E_RT_IRQHandler 0000001A
+
+Symbol: UART0_E_RT_IRQHandler
+   Definitions
+      At line 314 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 107 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 241 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+UART0_RX_IRQHandler 0000001A
+
+Symbol: UART0_RX_IRQHandler
+   Definitions
+      At line 312 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 105 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 239 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+UART0_TD_IRQHandler 0000001A
+
+Symbol: UART0_TD_IRQHandler
+
+
+
+ARM Macro Assembler    Page 16 Alphabetic symbol ordering
+Relocatable symbols
+
+   Definitions
+      At line 311 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 104 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 238 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+UART0_TX_IRQHandler 0000001A
+
+Symbol: UART0_TX_IRQHandler
+   Definitions
+      At line 313 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 106 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 240 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+UART1_E_RT_IRQHandler 0000001A
+
+Symbol: UART1_E_RT_IRQHandler
+   Definitions
+      At line 318 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 111 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 245 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+UART1_RX_IRQHandler 0000001A
+
+Symbol: UART1_RX_IRQHandler
+   Definitions
+      At line 316 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 109 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 243 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+UART1_TD_IRQHandler 0000001A
+
+Symbol: UART1_TD_IRQHandler
+   Definitions
+      At line 315 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 108 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 242 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+UART1_TX_IRQHandler 0000001A
+
+
+
+
+ARM Macro Assembler    Page 17 Alphabetic symbol ordering
+Relocatable symbols
+
+Symbol: UART1_TX_IRQHandler
+   Definitions
+      At line 317 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 110 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+      At line 244 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+UsageFault_Handler 00000010
+
+Symbol: UsageFault_Handler
+   Definitions
+      At line 189 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 67 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 190 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+WDT_IRQHandler 0000001A
+
+Symbol: WDT_IRQHandler
+   Definitions
+      At line 286 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 79 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 213 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+__user_initial_stackheap 0000001C
+
+Symbol: __user_initial_stackheap
+   Definitions
+      At line 379 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 377 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+Comment: __user_initial_stackheap used once
+83 symbols
+
+
+
+ARM Macro Assembler    Page 1 Alphabetic symbol ordering
+Absolute symbols
+
+Heap_Size 00000200
+
+Symbol: Heap_Size
+   Definitions
+      At line 44 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+   Uses
+      At line 48 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 383 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+Stack_Size 00000400
+
+Symbol: Stack_Size
+   Definitions
+      At line 33 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+   Uses
+      At line 36 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+      At line 382 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+
+__Vectors_Size 00000158
+
+Symbol: __Vectors_Size
+   Definitions
+      At line 152 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 59 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1
+921VK035.s
+Comment: __Vectors_Size used once
+3 symbols
+
+
+
+ARM Macro Assembler    Page 1 Alphabetic symbol ordering
+External symbols
+
+SystemInit 00000000
+
+Symbol: SystemInit
+   Definitions
+      At line 160 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 161 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+Comment: SystemInit used once
+__main 00000000
+
+Symbol: __main
+   Definitions
+      At line 159 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      At line 163 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+Comment: __main used once
+__use_two_region_memory 00000000
+
+Symbol: __use_two_region_memory
+   Definitions
+      At line 376 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K
+1921VK035.s
+   Uses
+      None
+Comment: __use_two_region_memory unused
+3 symbols
+436 symbols in table

Listings/template.map

@@ -0,0 +1,1316 @@
+Component: ARM Compiler 5.06 update 7 (build 960) Tool: armlink [4d3601]
+
+==============================================================================
+
+Section Cross References
+
+    system_k1921vk035.o(i.SystemCoreClockUpdate) refers to system_k1921vk035.o(.data) for .data
+    system_k1921vk035.o(i.SystemInit) refers to system_k1921vk035.o(i.ClkInit) for ClkInit
+    system_k1921vk035.o(i.SystemInit) refers to system_k1921vk035.o(i.FPUInit) for FPUInit
+    startup_k1921vk035.o(STACK) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
+    startup_k1921vk035.o(HEAP) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
+    startup_k1921vk035.o(RESET) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
+    startup_k1921vk035.o(RESET) refers to startup_k1921vk035.o(STACK) for __initial_sp
+    startup_k1921vk035.o(RESET) refers to startup_k1921vk035.o(.text) for Reset_Handler
+    startup_k1921vk035.o(RESET) refers to vk035_it.o(i.NMI_Handler) for NMI_Handler
+    startup_k1921vk035.o(RESET) refers to vk035_it.o(i.HardFault_Handler) for HardFault_Handler
+    startup_k1921vk035.o(RESET) refers to vk035_it.o(i.MemManage_Handler) for MemManage_Handler
+    startup_k1921vk035.o(RESET) refers to vk035_it.o(i.BusFault_Handler) for BusFault_Handler
+    startup_k1921vk035.o(RESET) refers to vk035_it.o(i.UsageFault_Handler) for UsageFault_Handler
+    startup_k1921vk035.o(RESET) refers to vk035_it.o(i.SVC_Handler) for SVC_Handler
+    startup_k1921vk035.o(RESET) refers to vk035_it.o(i.DebugMon_Handler) for DebugMon_Handler
+    startup_k1921vk035.o(RESET) refers to vk035_it.o(i.PendSV_Handler) for PendSV_Handler
+    startup_k1921vk035.o(RESET) refers to vk035_it.o(i.SysTick_Handler) for SysTick_Handler
+    startup_k1921vk035.o(.text) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
+    startup_k1921vk035.o(.text) refers to system_k1921vk035.o(i.SystemInit) for SystemInit
+    startup_k1921vk035.o(.text) refers to __main.o(!!!main) for __main
+    startup_k1921vk035.o(.text) refers to startup_k1921vk035.o(HEAP) for Heap_Mem
+    startup_k1921vk035.o(.text) refers to startup_k1921vk035.o(STACK) for Stack_Mem
+    main.o(i.assert_failed) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+    main.o(i.assert_failed) refers to _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) for _printf_d
+    main.o(i.assert_failed) refers to _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) for _printf_s
+    main.o(i.assert_failed) refers to _printf_dec.o(.text) for _printf_int_dec
+    main.o(i.assert_failed) refers to _printf_str.o(.text) for _printf_str
+    main.o(i.assert_failed) refers to noretval__2printf.o(.text) for __2printf
+    main.o(i.main) refers to main.o(i.periph_init) for periph_init
+    main.o(i.periph_init) refers to _printf_pad.o(.text) for _printf_pre_padding
+    main.o(i.periph_init) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+    main.o(i.periph_init) refers to _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) for _printf_d
+    main.o(i.periph_init) refers to _printf_dec.o(.text) for _printf_int_dec
+    main.o(i.periph_init) refers to system_k1921vk035.o(i.SystemCoreClockUpdate) for SystemCoreClockUpdate
+    main.o(i.periph_init) refers to rcu.o(i.sysclk_init) for sysclk_init
+    main.o(i.periph_init) refers to gpio.o(i.gpio_init) for gpio_init
+    main.o(i.periph_init) refers to retarget_conf.o(i.retarget_init) for retarget_init
+    main.o(i.periph_init) refers to dflt_clz.o(x$fpl$dfltu) for __aeabi_ui2d
+    main.o(i.periph_init) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv
+    main.o(i.periph_init) refers to dfix.o(x$fpl$dfix) for __aeabi_d2iz
+    main.o(i.periph_init) refers to noretval__2printf.o(.text) for __2printf
+    main.o(i.periph_init) refers to system_k1921vk035.o(.data) for SystemCoreClock
+    gpio.o(i.gpio_init) refers to plib035_gpio.o(i.GPIO_DeInit) for GPIO_DeInit
+    gpio.o(i.gpio_init) refers to plib035_gpio.o(i.GPIO_Init) for GPIO_Init
+    gpio.o(i.gpio_init) refers to gpio.o(.data) for .data
+    rcu.o(i.RCU_ClkOutConfig) refers to main.o(i.assert_failed) for assert_failed
+    rcu.o(i.sysclk_init) refers to plib035_rcu.o(i.RCU_PLL_AutoConfig) for RCU_PLL_AutoConfig
+    rcu.o(i.sysclk_init) refers to main.o(i.Error_Handler) for Error_Handler
+    rcu.o(i.sysclk_init) refers to system_k1921vk035.o(i.SystemCoreClockUpdate) for SystemCoreClockUpdate
+    rcu.o(i.sysclk_init) refers to rcu.o(i.RCU_ClkOutConfig) for RCU_ClkOutConfig
+    rcu.o(i.sysclk_init) refers to rcu.o(.data) for .data
+    vk035_it.o(i.SysTick_Handler) refers to system_k1921vk035.o(.data) for uwTick
+    plib035_adc.o(i.ADC_DC_Config) refers to main.o(i.assert_failed) for assert_failed
+    plib035_adc.o(i.ADC_DC_Config) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init
+    plib035_adc.o(i.ADC_DC_Init) refers to main.o(i.assert_failed) for assert_failed
+    plib035_adc.o(i.ADC_DC_Init) refers to plib035_adc.o(i.ADC_DC_Config) for ADC_DC_Config
+    plib035_adc.o(i.ADC_DC_Init) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init
+    plib035_adc.o(i.ADC_DeInit) refers to plib035_adc.o(i.RCU_ADCRstCmd) for RCU_ADCRstCmd
+    plib035_adc.o(i.ADC_SEQ_DCEnableCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_adc.o(i.ADC_SEQ_DCEnableCmd) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init
+    plib035_adc.o(i.ADC_SEQ_Init) refers to main.o(i.assert_failed) for assert_failed
+    plib035_adc.o(i.ADC_SEQ_Init) refers to plib035_adc.o(i.ADC_SEQ_ReqConfig) for ADC_SEQ_ReqConfig
+    plib035_adc.o(i.ADC_SEQ_Init) refers to plib035_adc.o(i.ADC_SEQ_DCEnableCmd) for ADC_SEQ_DCEnableCmd
+    plib035_adc.o(i.ADC_SEQ_ReqConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_adc.o(i.ADC_SEQ_ReqConfig) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init
+    plib035_adc.o(i.RCU_ADCRstCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_dma.o(i.DMA_ChannelInit) refers to main.o(i.assert_failed) for assert_failed
+    plib035_dma.o(i.DMA_Init) refers to plib035_dma.o(i.DMA_ProtectConfig) for DMA_ProtectConfig
+    plib035_dma.o(i.DMA_Init) refers to main.o(i.assert_failed) for assert_failed
+    plib035_dma.o(i.DMA_ProtectConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_dma.o(i.DMA_ProtectConfig) refers to plib035_dma.o(i.DMA_Init) for i.DMA_Init
+    plib035_ecap.o(i.ECAP_Capture_Init) refers to main.o(i.assert_failed) for assert_failed
+    plib035_ecap.o(i.ECAP_Capture_Init) refers to plib035_ecap.o(i.ECAP_Init) for i.ECAP_Init
+    plib035_ecap.o(i.ECAP_DeInit) refers to main.o(i.assert_failed) for assert_failed
+    plib035_ecap.o(i.ECAP_DeInit) refers to plib035_ecap.o(i.RCU_APBRstCmd) for RCU_APBRstCmd
+    plib035_ecap.o(i.ECAP_Init) refers to main.o(i.assert_failed) for assert_failed
+    plib035_ecap.o(i.ECAP_PWM_Init) refers to main.o(i.assert_failed) for assert_failed
+    plib035_ecap.o(i.ECAP_PWM_Init) refers to plib035_ecap.o(i.ECAP_Init) for i.ECAP_Init
+    plib035_ecap.o(i.RCU_APBRstCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_gpio.o(i.GPIO_AltFuncCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_gpio.o(i.GPIO_AltFuncCmd) refers to plib035_gpio.o(i.GPIO_DigitalCmd) for i.GPIO_DigitalCmd
+    plib035_gpio.o(i.GPIO_DeInit) refers to main.o(i.assert_failed) for assert_failed
+    plib035_gpio.o(i.GPIO_DeInit) refers to plib035_gpio.o(i.RCU_AHBRstCmd) for RCU_AHBRstCmd
+    plib035_gpio.o(i.GPIO_DigitalCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_gpio.o(i.GPIO_DriveModeConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_gpio.o(i.GPIO_DriveModeConfig) refers to plib035_gpio.o(i.GPIO_ModeConfig) for GPIO_ModeConfig
+    plib035_gpio.o(i.GPIO_InModeConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_gpio.o(i.GPIO_InModeConfig) refers to plib035_gpio.o(i.GPIO_ModeConfig) for GPIO_ModeConfig
+    plib035_gpio.o(i.GPIO_Init) refers to plib035_gpio.o(i.GPIO_OutCmd) for GPIO_OutCmd
+    plib035_gpio.o(i.GPIO_Init) refers to plib035_gpio.o(i.GPIO_AltFuncCmd) for GPIO_AltFuncCmd
+    plib035_gpio.o(i.GPIO_Init) refers to plib035_gpio.o(i.GPIO_OutModeConfig) for GPIO_OutModeConfig
+    plib035_gpio.o(i.GPIO_Init) refers to plib035_gpio.o(i.GPIO_InModeConfig) for GPIO_InModeConfig
+    plib035_gpio.o(i.GPIO_Init) refers to plib035_gpio.o(i.GPIO_PullModeConfig) for GPIO_PullModeConfig
+    plib035_gpio.o(i.GPIO_Init) refers to plib035_gpio.o(i.GPIO_DriveModeConfig) for GPIO_DriveModeConfig
+    plib035_gpio.o(i.GPIO_Init) refers to plib035_gpio.o(i.GPIO_DigitalCmd) for GPIO_DigitalCmd
+    plib035_gpio.o(i.GPIO_OutCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_gpio.o(i.GPIO_OutCmd) refers to plib035_gpio.o(i.GPIO_DigitalCmd) for i.GPIO_DigitalCmd
+    plib035_gpio.o(i.GPIO_OutModeConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_gpio.o(i.GPIO_OutModeConfig) refers to plib035_gpio.o(i.GPIO_ModeConfig) for GPIO_ModeConfig
+    plib035_gpio.o(i.GPIO_PullModeConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_gpio.o(i.GPIO_PullModeConfig) refers to plib035_gpio.o(i.GPIO_ModeConfig) for GPIO_ModeConfig
+    plib035_gpio.o(i.RCU_AHBRstCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_i2c.o(i.I2C_FSFreqConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_i2c.o(i.I2C_HSFreqConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_i2c.o(i.I2C_HSFreqConfig) refers to plib035_i2c.o(i.I2C_FSFreqConfig) for i.I2C_FSFreqConfig
+    plib035_mflash.o(i.MFLASH_EraseFull) refers to main.o(i.assert_failed) for assert_failed
+    plib035_mflash.o(i.MFLASH_EraseFull) refers to plib035_mflash.o(i.MFLASH_SetCmd) for MFLASH_SetCmd
+    plib035_mflash.o(i.MFLASH_EraseFull) refers to plib035_mflash.o(i.MFLASH_BusyStatus) for MFLASH_BusyStatus
+    plib035_mflash.o(i.MFLASH_ErasePage) refers to main.o(i.assert_failed) for assert_failed
+    plib035_mflash.o(i.MFLASH_ErasePage) refers to plib035_mflash.o(i.MFLASH_SetCmd) for MFLASH_SetCmd
+    plib035_mflash.o(i.MFLASH_ErasePage) refers to plib035_mflash.o(i.MFLASH_BusyStatus) for MFLASH_BusyStatus
+    plib035_mflash.o(i.MFLASH_ReadData) refers to main.o(i.assert_failed) for assert_failed
+    plib035_mflash.o(i.MFLASH_ReadData) refers to plib035_mflash.o(i.MFLASH_SetCmd) for MFLASH_SetCmd
+    plib035_mflash.o(i.MFLASH_ReadData) refers to plib035_mflash.o(i.MFLASH_BusyStatus) for MFLASH_BusyStatus
+    plib035_mflash.o(i.MFLASH_WriteData) refers to main.o(i.assert_failed) for assert_failed
+    plib035_mflash.o(i.MFLASH_WriteData) refers to plib035_mflash.o(i.MFLASH_SetCmd) for MFLASH_SetCmd
+    plib035_mflash.o(i.MFLASH_WriteData) refers to plib035_mflash.o(i.MFLASH_BusyStatus) for MFLASH_BusyStatus
+    plib035_mflash.o(i.MFLASH_WriteData) refers to plib035_mflash.o(i.MFLASH_ReadData) for i.MFLASH_ReadData
+    plib035_pwm.o(i.PWM_AQ_ActionAConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_AQ_ActionBConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_AQ_Init) refers to plib035_pwm.o(i.PWM_AQ_ActionAConfig) for PWM_AQ_ActionAConfig
+    plib035_pwm.o(i.PWM_AQ_Init) refers to plib035_pwm.o(i.PWM_AQ_ActionBConfig) for PWM_AQ_ActionBConfig
+    plib035_pwm.o(i.PWM_CMP_CmpADirectLoadCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_CMP_CmpALoadEventConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_CMP_Init) refers to plib035_pwm.o(i.PWM_CMP_CmpALoadEventConfig) for PWM_CMP_CmpALoadEventConfig
+    plib035_pwm.o(i.PWM_CMP_Init) refers to plib035_pwm.o(i.PWM_CMP_CmpADirectLoadCmd) for PWM_CMP_CmpADirectLoadCmd
+    plib035_pwm.o(i.PWM_CMP_Init) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_CMP_Init) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_DB_Init) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_DB_Init) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_DeInit) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_DeInit) refers to plib035_pwm.o(i.RCU_APBRstCmd) for RCU_APBRstCmd
+    plib035_pwm.o(i.PWM_ET_Init) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_ET_Init) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_HD_Init) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_HD_Init) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_TB_ClkDivConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_TB_ClkDivConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.PWM_TB_Init) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_TB_Init) refers to plib035_pwm.o(i.PWM_TB_ClkDivConfig) for PWM_TB_ClkDivConfig
+    plib035_pwm.o(i.PWM_TZ_Init) refers to main.o(i.assert_failed) for assert_failed
+    plib035_pwm.o(i.PWM_TZ_Init) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init
+    plib035_pwm.o(i.RCU_APBRstCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_qep.o(i.QEP_CAP_Init) refers to main.o(i.assert_failed) for assert_failed
+    plib035_qep.o(i.QEP_CAP_Init) refers to plib035_qep.o(i.QEP_PC_Init) for i.QEP_PC_Init
+    plib035_qep.o(i.QEP_CMP_Init) refers to main.o(i.assert_failed) for assert_failed
+    plib035_qep.o(i.QEP_CMP_Init) refers to plib035_qep.o(i.QEP_PC_Init) for i.QEP_PC_Init
+    plib035_qep.o(i.QEP_DeInit) refers to plib035_qep.o(i.RCU_APBRstCmd) for RCU_APBRstCmd
+    plib035_qep.o(i.QEP_PC_Init) refers to main.o(i.assert_failed) for assert_failed
+    plib035_qep.o(i.RCU_APBRstCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_rcu.o(i.MFLASH_LatencyConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_rcu.o(i.RCU_GetADCClkFreq) refers to plib035_rcu.o(i.getPeriphClkFreq) for getPeriphClkFreq
+    plib035_rcu.o(i.RCU_GetClkOutFreq) refers to plib035_rcu.o(i.getSysPeriphClkFreq) for getSysPeriphClkFreq
+    plib035_rcu.o(i.RCU_GetPLLDivClkFreq) refers to plib035_rcu.o(i.RCU_GetPLLClkFreq) for RCU_GetPLLClkFreq
+    plib035_rcu.o(i.RCU_GetSPIClkFreq) refers to plib035_rcu.o(i.getPeriphClkFreq) for getPeriphClkFreq
+    plib035_rcu.o(i.RCU_GetSysClkFreq) refers to plib035_rcu.o(i.getSysClkFreq) for getSysClkFreq
+    plib035_rcu.o(i.RCU_GetTraceClkFreq) refers to plib035_rcu.o(i.getSysPeriphClkFreq) for getSysPeriphClkFreq
+    plib035_rcu.o(i.RCU_GetUARTClkFreq) refers to plib035_rcu.o(i.getPeriphClkFreq) for getPeriphClkFreq
+    plib035_rcu.o(i.RCU_GetWDTClkFreq) refers to plib035_rcu.o(i.getSysPeriphClkFreq) for getSysPeriphClkFreq
+    plib035_rcu.o(i.RCU_PLL_AutoConfig) refers to plib035_rcu.o(i.RCU_PLL_StructInit) for RCU_PLL_StructInit
+    plib035_rcu.o(i.RCU_PLL_AutoConfig) refers to plib035_rcu.o(i.RCU_PLL_Init) for RCU_PLL_Init
+    plib035_rcu.o(i.RCU_PLL_AutoConfig) refers to plib035_rcu.o(i.MFLASH_LatencyConfig) for MFLASH_LatencyConfig
+    plib035_rcu.o(i.RCU_PLL_AutoConfig) refers to plib035_rcu.o(i.RCU_SysClkChangeCmd) for RCU_SysClkChangeCmd
+    plib035_rcu.o(i.RCU_PLL_DeInit) refers to plib035_rcu.o(i.RCU_PLL_OutCmd) for RCU_PLL_OutCmd
+    plib035_rcu.o(i.RCU_PLL_Init) refers to main.o(i.assert_failed) for assert_failed
+    plib035_rcu.o(i.RCU_PLL_Init) refers to plib035_rcu.o(i.RCU_PLL_OutCmd) for RCU_PLL_OutCmd
+    plib035_rcu.o(i.RCU_PLL_OutCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_rcu.o(i.RCU_SysClkChangeCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_rcu.o(i.getPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetOSIClkFreq) for RCU_GetOSIClkFreq
+    plib035_rcu.o(i.getPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetOSEClkFreq) for RCU_GetOSEClkFreq
+    plib035_rcu.o(i.getPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetPLLClkFreq) for RCU_GetPLLClkFreq
+    plib035_rcu.o(i.getPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetPLLDivClkFreq) for RCU_GetPLLDivClkFreq
+    plib035_rcu.o(i.getSysClkFreq) refers to plib035_rcu.o(i.RCU_GetPLLDivClkFreq) for RCU_GetPLLDivClkFreq
+    plib035_rcu.o(i.getSysClkFreq) refers to plib035_rcu.o(i.RCU_GetOSIClkFreq) for RCU_GetOSIClkFreq
+    plib035_rcu.o(i.getSysClkFreq) refers to plib035_rcu.o(i.RCU_GetOSEClkFreq) for RCU_GetOSEClkFreq
+    plib035_rcu.o(i.getSysClkFreq) refers to plib035_rcu.o(i.RCU_GetPLLClkFreq) for RCU_GetPLLClkFreq
+    plib035_rcu.o(i.getSysPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetPLLDivClkFreq) for RCU_GetPLLDivClkFreq
+    plib035_rcu.o(i.getSysPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetOSEClkFreq) for RCU_GetOSEClkFreq
+    plib035_rcu.o(i.getSysPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetPLLClkFreq) for RCU_GetPLLClkFreq
+    plib035_rcu.o(i.getSysPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetOSIClkFreq) for RCU_GetOSIClkFreq
+    plib035_spi.o(i.RCU_SPIRstCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_spi.o(i.SPI_DeInit) refers to plib035_spi.o(i.RCU_SPIRstCmd) for RCU_SPIRstCmd
+    plib035_spi.o(i.SPI_Init) refers to main.o(i.assert_failed) for assert_failed
+    plib035_tmr.o(i.TMR_FreqConfig) refers to plib035_tmr.o(i.TMR_SetLoad) for TMR_SetLoad
+    plib035_tmr.o(i.TMR_PeriodConfig) refers to plib035_tmr.o(i.TMR_SetLoad) for TMR_SetLoad
+    plib035_tmr.o(i.TMR_SetLoad) refers to main.o(i.assert_failed) for assert_failed
+    plib035_uart.o(i.RCU_UARTRstCmd) refers to main.o(i.assert_failed) for assert_failed
+    plib035_uart.o(i.UART_AutoBaudConfig) refers to main.o(i.assert_failed) for assert_failed
+    plib035_uart.o(i.UART_AutoBaudConfig) refers to plib035_rcu.o(i.RCU_GetUARTClkFreq) for RCU_GetUARTClkFreq
+    plib035_uart.o(i.UART_DeInit) refers to main.o(i.assert_failed) for assert_failed
+    plib035_uart.o(i.UART_DeInit) refers to plib035_uart.o(i.RCU_UARTRstCmd) for RCU_UARTRstCmd
+    plib035_uart.o(i.UART_Init) refers to plib035_uart.o(i.UART_AutoBaudConfig) for UART_AutoBaudConfig
+    plib035_uart.o(i.UART_Init) refers to main.o(i.assert_failed) for assert_failed
+    retarget.o(.rev16_text) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi
+    retarget.o(.revsh_text) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi
+    retarget.o(.rrx_text) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi
+    retarget.o(i._sys_exit) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi
+    retarget.o(i._ttywrch) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi
+    retarget.o(i._ttywrch) refers to retarget_conf.o(i.retarget_put_char) for retarget_put_char
+    retarget.o(i.ferror) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi
+    retarget.o(i.fgetc) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi
+    retarget.o(i.fgetc) refers to retarget_conf.o(i.retarget_get_char) for retarget_get_char
+    retarget.o(i.fputc) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi
+    retarget.o(i.fputc) refers to retarget_conf.o(i.retarget_put_char) for retarget_put_char
+    retarget.o(.data) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi
+    retarget.o(.data) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi
+    retarget_conf.o(i.retarget_init) refers to system_k1921vk035.o(.data) for SystemCoreClock
+    __2printf.o(.text) refers to _printf_char_file.o(.text) for _printf_char_file
+    __2printf.o(.text) refers to retarget.o(.data) for __stdout
+    noretval__2printf.o(.text) refers to _printf_char_file.o(.text) for _printf_char_file
+    noretval__2printf.o(.text) refers to retarget.o(.data) for __stdout
+    __printf.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+    _printf_str.o(.text) refers (Special) to _printf_char.o(.text) for _printf_cs_common
+    _printf_str.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding
+    _printf_str.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding
+    _printf_dec.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common
+    __printf_flags.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+    __printf_flags.o(.text) refers to __printf_flags.o(.constdata) for .constdata
+    __printf_ss.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+    __printf_flags_ss.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+    __printf_flags_ss.o(.text) refers to __printf_flags_ss.o(.constdata) for .constdata
+    __printf_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit
+    __printf_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+    __printf_flags_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit
+    __printf_flags_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+    __printf_flags_wp.o(.text) refers to __printf_flags_wp.o(.constdata) for .constdata
+    __printf_ss_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit
+    __printf_ss_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+    __printf_flags_ss_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit
+    __printf_flags_ss_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+    __printf_flags_ss_wp.o(.text) refers to __printf_flags_ss_wp.o(.constdata) for .constdata
+    _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) refers (Weak) to _printf_char.o(.text) for _printf_string
+    _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) refers (Weak) to _printf_dec.o(.text) for _printf_int_dec
+    _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) refers (Special) to _printf_percent_end.o(.ARM.Collect$$_printf_percent$$00000017) for _printf_percent_end
+    __main.o(!!!main) refers to __rtentry.o(.ARM.Collect$$rtentry$$00000000) for __rt_entry
+    ddiv.o(x$fpl$drdiv) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    ddiv.o(x$fpl$drdiv) refers to ddiv.o(x$fpl$ddiv) for ddiv_entry
+    ddiv.o(x$fpl$ddiv) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    ddiv.o(x$fpl$ddiv) refers to dretinf.o(x$fpl$dretinf) for __fpl_dretinf
+    ddiv.o(x$fpl$ddiv) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf
+    dfix.o(x$fpl$dfix) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    dfix.o(x$fpl$dfix) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf
+    dfix.o(x$fpl$dfixr) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    dfix.o(x$fpl$dfixr) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf
+    dflt_clz.o(x$fpl$dfltu) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    dflt_clz.o(x$fpl$dflt) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    dflt_clz.o(x$fpl$dfltn) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for __rt_entry_li
+    __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for __rt_entry_main
+    __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) for __rt_entry_postli_1
+    __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000009) for __rt_entry_postsh_1
+    __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000002) for __rt_entry_presh_1
+    __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for __rt_entry_sh
+    _printf_intcommon.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding
+    _printf_intcommon.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding
+    _printf_intcommon.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding
+    _printf_char.o(.text) refers (Weak) to _printf_str.o(.text) for _printf_str
+    _printf_char_file.o(.text) refers to _printf_char_common.o(.text) for _printf_char_common
+    _printf_char_file.o(.text) refers to retarget.o(i.ferror) for ferror
+    _printf_char_file.o(.text) refers to retarget.o(i.fputc) for fputc
+    dnaninf.o(x$fpl$dnaninf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    dretinf.o(x$fpl$dretinf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+    __rtentry2.o(.ARM.Collect$$rtentry$$00000008) refers to boardinit2.o(.text) for _platform_post_stackheap_init
+    __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) refers to libinit.o(.ARM.Collect$$libinit$$00000000) for __rt_lib_init
+    __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) refers to boardinit3.o(.text) for _platform_post_lib_init
+    __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to main.o(i.main) for main
+    __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to exit.o(.text) for exit
+    __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000001) for .ARM.Collect$$rtentry$$00000001
+    __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000008) for .ARM.Collect$$rtentry$$00000008
+    __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for .ARM.Collect$$rtentry$$0000000A
+    __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) for .ARM.Collect$$rtentry$$0000000B
+    __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for .ARM.Collect$$rtentry$$0000000D
+    __rtentry4.o(.ARM.Collect$$rtentry$$00000004) refers to sys_stackheap_outer.o(.text) for __user_setup_stackheap
+    __rtentry4.o(.ARM.exidx) refers to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for .ARM.Collect$$rtentry$$00000004
+    _printf_char_common.o(.text) refers to __printf_wp.o(.text) for __printf
+    sys_stackheap_outer.o(.text) refers to libspace.o(.text) for __user_perproc_libspace
+    sys_stackheap_outer.o(.text) refers to startup_k1921vk035.o(.text) for __user_initial_stackheap
+    exit.o(.text) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for __rt_exit
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002E) for __rt_lib_init_alloca_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002C) for __rt_lib_init_argv_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001B) for __rt_lib_init_atexit_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000021) for __rt_lib_init_clock_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000032) for __rt_lib_init_cpp_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000030) for __rt_lib_init_exceptions_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000001) for __rt_lib_init_fp_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001F) for __rt_lib_init_fp_trap_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000023) for __rt_lib_init_getenv_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000A) for __rt_lib_init_heap_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000011) for __rt_lib_init_lc_collate_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000013) for __rt_lib_init_lc_ctype_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000015) for __rt_lib_init_lc_monetary_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000017) for __rt_lib_init_lc_numeric_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000019) for __rt_lib_init_lc_time_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000004) for __rt_lib_init_preinit_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000E) for __rt_lib_init_rand_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000033) for __rt_lib_init_return
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001D) for __rt_lib_init_signal_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000025) for __rt_lib_init_stdio_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000C) for __rt_lib_init_user_alloc_1
+    libspace.o(.text) refers to libspace.o(.bss) for __libspace_start
+    rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit
+    rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls
+    rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1
+    rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit
+    rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls
+    rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1
+    rtexit.o(.ARM.exidx) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for .ARM.Collect$$rtexit$$00000000
+    libinit2.o(.ARM.Collect$$libinit$$00000001) refers to fpinit.o(x$fpl$fpinit) for _fp_init
+    libinit2.o(.ARM.Collect$$libinit$$00000010) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
+    libinit2.o(.ARM.Collect$$libinit$$00000012) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
+    libinit2.o(.ARM.Collect$$libinit$$00000014) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
+    libinit2.o(.ARM.Collect$$libinit$$00000016) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
+    libinit2.o(.ARM.Collect$$libinit$$00000018) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
+    libinit2.o(.ARM.Collect$$libinit$$00000026) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer
+    libinit2.o(.ARM.Collect$$libinit$$00000027) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer
+    rtexit2.o(.ARM.Collect$$rtexit$$00000003) refers to libshutdown.o(.ARM.Collect$$libshutdown$$00000000) for __rt_lib_shutdown
+    rtexit2.o(.ARM.Collect$$rtexit$$00000004) refers to retarget.o(i._sys_exit) for _sys_exit
+    rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000001) for .ARM.Collect$$rtexit$$00000001
+    rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for .ARM.Collect$$rtexit$$00000003
+    rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for .ARM.Collect$$rtexit$$00000004
+    argv_veneer.o(.emb_text) refers to no_argv.o(.text) for __ARM_get_argv
+    _get_argv_nomalloc.o(.text) refers (Special) to hrguard.o(.text) for __heap_region$guard
+    _get_argv_nomalloc.o(.text) refers to defsig_rtmem_outer.o(.text) for __rt_SIGRTMEM
+    _get_argv_nomalloc.o(.text) refers to sys_command.o(.text) for _sys_command_string
+    libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) for __rt_lib_shutdown_cpp_1
+    libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) for __rt_lib_shutdown_fini_1
+    libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000009) for __rt_lib_shutdown_fp_trap_1
+    libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000011) for __rt_lib_shutdown_heap_1
+    libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000012) for __rt_lib_shutdown_return
+    libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) for __rt_lib_shutdown_signal_1
+    libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000006) for __rt_lib_shutdown_stdio_1
+    libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000E) for __rt_lib_shutdown_user_alloc_1
+    sys_command.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting
+    sys_command.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function
+    defsig_rtmem_outer.o(.text) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner
+    defsig_rtmem_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit
+    defsig_rtmem_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise
+    rt_raise.o(.text) refers to __raise.o(.text) for __raise
+    rt_raise.o(.text) refers to retarget.o(i._sys_exit) for _sys_exit
+    defsig_exit.o(.text) refers to retarget.o(i._sys_exit) for _sys_exit
+    defsig_rtmem_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+    __raise.o(.text) refers to defsig.o(CL$$defsig) for __default_signal_handler
+    defsig_general.o(.text) refers to retarget.o(i._ttywrch) for _ttywrch
+    defsig.o(CL$$defsig) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner
+    defsig_abrt_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+    defsig_fpe_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+    defsig_rtred_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+    defsig_stak_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+    defsig_pvfn_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+    defsig_cppl_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+    defsig_segv_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+    defsig_other.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+
+
+==============================================================================
+
+Removing Unused input sections from the image.
+
+    Removing system_k1921vk035.o(.rev16_text), (4 bytes).
+    Removing system_k1921vk035.o(.revsh_text), (4 bytes).
+    Removing system_k1921vk035.o(.rrx_text), (6 bytes).
+    Removing main.o(.rev16_text), (4 bytes).
+    Removing main.o(.revsh_text), (4 bytes).
+    Removing main.o(.rrx_text), (6 bytes).
+    Removing gpio.o(.rev16_text), (4 bytes).
+    Removing gpio.o(.revsh_text), (4 bytes).
+    Removing gpio.o(.rrx_text), (6 bytes).
+    Removing rcu.o(.rev16_text), (4 bytes).
+    Removing rcu.o(.revsh_text), (4 bytes).
+    Removing rcu.o(.rrx_text), (6 bytes).
+    Removing vk035_it.o(.rev16_text), (4 bytes).
+    Removing vk035_it.o(.revsh_text), (4 bytes).
+    Removing vk035_it.o(.rrx_text), (6 bytes).
+    Removing plib035_adc.o(.rev16_text), (4 bytes).
+    Removing plib035_adc.o(.revsh_text), (4 bytes).
+    Removing plib035_adc.o(.rrx_text), (6 bytes).
+    Removing plib035_adc.o(i.ADC_DC_Config), (116 bytes).
+    Removing plib035_adc.o(i.ADC_DC_Init), (316 bytes).
+    Removing plib035_adc.o(i.ADC_DC_StructInit), (18 bytes).
+    Removing plib035_adc.o(i.ADC_DeInit), (18 bytes).
+    Removing plib035_adc.o(i.ADC_SEQ_DCEnableCmd), (96 bytes).
+    Removing plib035_adc.o(i.ADC_SEQ_Init), (568 bytes).
+    Removing plib035_adc.o(i.ADC_SEQ_ReqConfig), (104 bytes).
+    Removing plib035_adc.o(i.ADC_SEQ_StructInit), (52 bytes).
+    Removing plib035_adc.o(i.RCU_ADCRstCmd), (80 bytes).
+    Removing plib035_can.o(.rev16_text), (4 bytes).
+    Removing plib035_can.o(.revsh_text), (4 bytes).
+    Removing plib035_can.o(.rrx_text), (6 bytes).
+    Removing plib035_dma.o(.rev16_text), (4 bytes).
+    Removing plib035_dma.o(.revsh_text), (4 bytes).
+    Removing plib035_dma.o(.rrx_text), (6 bytes).
+    Removing plib035_dma.o(i.DMA_ChannelDeInit), (10 bytes).
+    Removing plib035_dma.o(i.DMA_ChannelInit), (492 bytes).
+    Removing plib035_dma.o(i.DMA_ChannelStructInit), (40 bytes).
+    Removing plib035_dma.o(i.DMA_DeInit), (28 bytes).
+    Removing plib035_dma.o(i.DMA_Init), (292 bytes).
+    Removing plib035_dma.o(i.DMA_ProtectConfig), (100 bytes).
+    Removing plib035_dma.o(i.DMA_StructInit), (26 bytes).
+    Removing plib035_ecap.o(.rev16_text), (4 bytes).
+    Removing plib035_ecap.o(.revsh_text), (4 bytes).
+    Removing plib035_ecap.o(.rrx_text), (6 bytes).
+    Removing plib035_ecap.o(i.ECAP_Capture_Init), (632 bytes).
+    Removing plib035_ecap.o(i.ECAP_Capture_StructInit), (28 bytes).
+    Removing plib035_ecap.o(i.ECAP_DeInit), (124 bytes).
+    Removing plib035_ecap.o(i.ECAP_Init), (276 bytes).
+    Removing plib035_ecap.o(i.ECAP_PWM_Init), (144 bytes).
+    Removing plib035_ecap.o(i.ECAP_PWM_StructInit), (18 bytes).
+    Removing plib035_ecap.o(i.ECAP_StructInit), (12 bytes).
+    Removing plib035_ecap.o(i.RCU_APBRstCmd), (152 bytes).
+    Removing plib035_gpio.o(.rev16_text), (4 bytes).
+    Removing plib035_gpio.o(.revsh_text), (4 bytes).
+    Removing plib035_gpio.o(.rrx_text), (6 bytes).
+    Removing plib035_gpio.o(i.GPIO_StructInit), (24 bytes).
+    Removing plib035_i2c.o(.rev16_text), (4 bytes).
+    Removing plib035_i2c.o(.revsh_text), (4 bytes).
+    Removing plib035_i2c.o(.rrx_text), (6 bytes).
+    Removing plib035_i2c.o(i.I2C_FSFreqConfig), (104 bytes).
+    Removing plib035_i2c.o(i.I2C_HSFreqConfig), (72 bytes).
+    Removing plib035_mflash.o(.rev16_text), (4 bytes).
+    Removing plib035_mflash.o(.revsh_text), (4 bytes).
+    Removing plib035_mflash.o(.rrx_text), (6 bytes).
+    Removing plib035_mflash.o(i.MFLASH_BusyStatus), (16 bytes).
+    Removing plib035_mflash.o(i.MFLASH_EraseFull), (92 bytes).
+    Removing plib035_mflash.o(i.MFLASH_ErasePage), (132 bytes).
+    Removing plib035_mflash.o(i.MFLASH_ReadData), (212 bytes).
+    Removing plib035_mflash.o(i.MFLASH_SetCmd), (20 bytes).
+    Removing plib035_mflash.o(i.MFLASH_WriteData), (180 bytes).
+    Removing plib035_pmu.o(.rev16_text), (4 bytes).
+    Removing plib035_pmu.o(.revsh_text), (4 bytes).
+    Removing plib035_pmu.o(.rrx_text), (6 bytes).
+    Removing plib035_pwm.o(.rev16_text), (4 bytes).
+    Removing plib035_pwm.o(.revsh_text), (4 bytes).
+    Removing plib035_pwm.o(.rrx_text), (6 bytes).
+    Removing plib035_pwm.o(i.PWM_AQ_ActionAConfig), (160 bytes).
+    Removing plib035_pwm.o(i.PWM_AQ_ActionBConfig), (160 bytes).
+    Removing plib035_pwm.o(i.PWM_AQ_Init), (130 bytes).
+    Removing plib035_pwm.o(i.PWM_AQ_StructInit), (28 bytes).
+    Removing plib035_pwm.o(i.PWM_CMP_CmpADirectLoadCmd), (112 bytes).
+    Removing plib035_pwm.o(i.PWM_CMP_CmpALoadEventConfig), (120 bytes).
+    Removing plib035_pwm.o(i.PWM_CMP_Init), (168 bytes).
+    Removing plib035_pwm.o(i.PWM_CMP_StructInit), (16 bytes).
+    Removing plib035_pwm.o(i.PWM_DB_Init), (292 bytes).
+    Removing plib035_pwm.o(i.PWM_DB_StructInit), (14 bytes).
+    Removing plib035_pwm.o(i.PWM_DeInit), (116 bytes).
+    Removing plib035_pwm.o(i.PWM_ET_Init), (680 bytes).
+    Removing plib035_pwm.o(i.PWM_ET_StructInit), (30 bytes).
+    Removing plib035_pwm.o(i.PWM_HD_Init), (336 bytes).
+    Removing plib035_pwm.o(i.PWM_HD_StructInit), (16 bytes).
+    Removing plib035_pwm.o(i.PWM_TB_ClkDivConfig), (152 bytes).
+    Removing plib035_pwm.o(i.PWM_TB_Init), (532 bytes).
+    Removing plib035_pwm.o(i.PWM_TB_StructInit), (24 bytes).
+    Removing plib035_pwm.o(i.PWM_TZ_Init), (248 bytes).
+    Removing plib035_pwm.o(i.PWM_TZ_StructInit), (12 bytes).
+    Removing plib035_pwm.o(i.RCU_APBRstCmd), (152 bytes).
+    Removing plib035_qep.o(.rev16_text), (4 bytes).
+    Removing plib035_qep.o(.revsh_text), (4 bytes).
+    Removing plib035_qep.o(.rrx_text), (6 bytes).
+    Removing plib035_qep.o(i.QEP_CAP_Init), (224 bytes).
+    Removing plib035_qep.o(i.QEP_CAP_StructInit), (18 bytes).
+    Removing plib035_qep.o(i.QEP_CMP_Init), (180 bytes).
+    Removing plib035_qep.o(i.QEP_CMP_StructInit), (18 bytes).
+    Removing plib035_qep.o(i.QEP_DeInit), (26 bytes).
+    Removing plib035_qep.o(i.QEP_PC_Init), (280 bytes).
+    Removing plib035_qep.o(i.QEP_PC_StructInit), (24 bytes).
+    Removing plib035_qep.o(i.RCU_APBRstCmd), (152 bytes).
+    Removing plib035_rcu.o(.rev16_text), (4 bytes).
+    Removing plib035_rcu.o(.revsh_text), (4 bytes).
+    Removing plib035_rcu.o(.rrx_text), (6 bytes).
+    Removing plib035_rcu.o(i.RCU_GetADCClkFreq), (48 bytes).
+    Removing plib035_rcu.o(i.RCU_GetClkOutFreq), (44 bytes).
+    Removing plib035_rcu.o(i.RCU_GetOSEClkFreq), (8 bytes).
+    Removing plib035_rcu.o(i.RCU_GetOSIClkFreq), (8 bytes).
+    Removing plib035_rcu.o(i.RCU_GetPLLClkFreq), (56 bytes).
+    Removing plib035_rcu.o(i.RCU_GetPLLDivClkFreq), (28 bytes).
+    Removing plib035_rcu.o(i.RCU_GetSPIClkFreq), (48 bytes).
+    Removing plib035_rcu.o(i.RCU_GetSysClkFreq), (16 bytes).
+    Removing plib035_rcu.o(i.RCU_GetTraceClkFreq), (44 bytes).
+    Removing plib035_rcu.o(i.RCU_GetUARTClkFreq), (48 bytes).
+    Removing plib035_rcu.o(i.RCU_GetWDTClkFreq), (44 bytes).
+    Removing plib035_rcu.o(i.RCU_PLL_DeInit), (24 bytes).
+    Removing plib035_rcu.o(i.getPeriphClkFreq), (38 bytes).
+    Removing plib035_rcu.o(i.getSysClkFreq), (38 bytes).
+    Removing plib035_rcu.o(i.getSysPeriphClkFreq), (38 bytes).
+    Removing plib035_spi.o(.rev16_text), (4 bytes).
+    Removing plib035_spi.o(.revsh_text), (4 bytes).
+    Removing plib035_spi.o(.rrx_text), (6 bytes).
+    Removing plib035_spi.o(i.RCU_SPIRstCmd), (80 bytes).
+    Removing plib035_spi.o(i.SPI_DeInit), (18 bytes).
+    Removing plib035_spi.o(i.SPI_Init), (228 bytes).
+    Removing plib035_spi.o(i.SPI_StructInit), (18 bytes).
+    Removing plib035_tmr.o(.rev16_text), (4 bytes).
+    Removing plib035_tmr.o(.revsh_text), (4 bytes).
+    Removing plib035_tmr.o(.rrx_text), (6 bytes).
+    Removing plib035_tmr.o(i.TMR_FreqConfig), (8 bytes).
+    Removing plib035_tmr.o(i.TMR_PeriodConfig), (16 bytes).
+    Removing plib035_tmr.o(i.TMR_SetLoad), (100 bytes).
+    Removing plib035_uart.o(.rev16_text), (4 bytes).
+    Removing plib035_uart.o(.revsh_text), (4 bytes).
+    Removing plib035_uart.o(.rrx_text), (6 bytes).
+    Removing plib035_uart.o(i.RCU_UARTRstCmd), (84 bytes).
+    Removing plib035_uart.o(i.UART_AutoBaudConfig), (260 bytes).
+    Removing plib035_uart.o(i.UART_DeInit), (100 bytes).
+    Removing plib035_uart.o(i.UART_Init), (316 bytes).
+    Removing plib035_uart.o(i.UART_StructInit), (24 bytes).
+    Removing plib035_wdt.o(.rev16_text), (4 bytes).
+    Removing plib035_wdt.o(.revsh_text), (4 bytes).
+    Removing plib035_wdt.o(.rrx_text), (6 bytes).
+    Removing retarget.o(.rev16_text), (4 bytes).
+    Removing retarget.o(.revsh_text), (4 bytes).
+    Removing retarget.o(.rrx_text), (6 bytes).
+    Removing retarget.o(i._ttywrch), (4 bytes).
+    Removing retarget.o(i.fgetc), (4 bytes).
+    Removing retarget.o(.data), (4 bytes).
+    Removing retarget_conf.o(.rev16_text), (4 bytes).
+    Removing retarget_conf.o(.revsh_text), (4 bytes).
+    Removing retarget_conf.o(.rrx_text), (6 bytes).
+    Removing retarget_conf.o(i.retarget_get_char), (20 bytes).
+
+159 unused section(s) (total 11136 bytes) removed from the image.
+
+==============================================================================
+
+Image Symbol Table
+
+    Local Symbols
+
+    Symbol Name                              Value     Ov Type        Size  Object(Section)
+
+    RESET                                    0x00000000   Section      344  startup_k1921vk035.o(RESET)
+    ../clib/angel/boardlib.s                 0x00000000   Number         0  boardshut.o ABSOLUTE
+    ../clib/angel/boardlib.s                 0x00000000   Number         0  boardinit3.o ABSOLUTE
+    ../clib/angel/boardlib.s                 0x00000000   Number         0  boardinit2.o ABSOLUTE
+    ../clib/angel/boardlib.s                 0x00000000   Number         0  boardinit1.o ABSOLUTE
+    ../clib/angel/dczerorl2.s                0x00000000   Number         0  __dczerorl2.o ABSOLUTE
+    ../clib/angel/handlers.s                 0x00000000   Number         0  __scatter_zi.o ABSOLUTE
+    ../clib/angel/kernel.s                   0x00000000   Number         0  __rtentry.o ABSOLUTE
+    ../clib/angel/kernel.s                   0x00000000   Number         0  rtexit2.o ABSOLUTE
+    ../clib/angel/kernel.s                   0x00000000   Number         0  __rtentry2.o ABSOLUTE
+    ../clib/angel/kernel.s                   0x00000000   Number         0  rtexit.o ABSOLUTE
+    ../clib/angel/kernel.s                   0x00000000   Number         0  __rtentry4.o ABSOLUTE
+    ../clib/angel/rt.s                       0x00000000   Number         0  rt_raise.o ABSOLUTE
+    ../clib/angel/scatter.s                  0x00000000   Number         0  __scatter.o ABSOLUTE
+    ../clib/angel/startup.s                  0x00000000   Number         0  __main.o ABSOLUTE
+    ../clib/angel/sys.s                      0x00000000   Number         0  sys_stackheap_outer.o ABSOLUTE
+    ../clib/angel/sys.s                      0x00000000   Number         0  indicate_semi.o ABSOLUTE
+    ../clib/angel/sys.s                      0x00000000   Number         0  use_no_semi.o ABSOLUTE
+    ../clib/angel/sys.s                      0x00000000   Number         0  libspace.o ABSOLUTE
+    ../clib/angel/sysapp.c                   0x00000000   Number         0  sys_command.o ABSOLUTE
+    ../clib/armsys.c                         0x00000000   Number         0  argv_veneer.o ABSOLUTE
+    ../clib/armsys.c                         0x00000000   Number         0  argv_veneer.o ABSOLUTE
+    ../clib/armsys.c                         0x00000000   Number         0  _get_argv_nomalloc.o ABSOLUTE
+    ../clib/armsys.c                         0x00000000   Number         0  no_argv.o ABSOLUTE
+    ../clib/heapalloc.c                      0x00000000   Number         0  hrguard.o ABSOLUTE
+    ../clib/heapaux.c                        0x00000000   Number         0  heapauxi.o ABSOLUTE
+    ../clib/libinit.s                        0x00000000   Number         0  libshutdown.o ABSOLUTE
+    ../clib/libinit.s                        0x00000000   Number         0  libshutdown2.o ABSOLUTE
+    ../clib/libinit.s                        0x00000000   Number         0  libinit2.o ABSOLUTE
+    ../clib/libinit.s                        0x00000000   Number         0  libinit.o ABSOLUTE
+    ../clib/misc.s                           0x00000000   Number         0  printf_stubs.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  _printf_dec.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  __printf_ss.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  __printf_flags_ss.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  __printf_wp.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  __printf_flags_wp.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  __printf_flags.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  __printf_flags_ss_wp.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  __printf_nopercent.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  __printf_ss_wp.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  _printf_char_file.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  _printf_char.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  _printf_intcommon.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  _printf_char_common.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  __2printf.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  noretval__2printf.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  __printf.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  _printf_pad.o ABSOLUTE
+    ../clib/printf.c                         0x00000000   Number         0  _printf_str.o ABSOLUTE
+    ../clib/printf_percent.s                 0x00000000   Number         0  _printf_percent_end.o ABSOLUTE
+    ../clib/printf_percent.s                 0x00000000   Number         0  _printf_s.o ABSOLUTE
+    ../clib/printf_percent.s                 0x00000000   Number         0  _printf_d.o ABSOLUTE
+    ../clib/printf_percent.s                 0x00000000   Number         0  _printf_percent.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_rtred_inner.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_stak_inner.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_pvfn_inner.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_cppl_inner.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_segv_inner.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_other.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_rtmem_inner.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  __raise.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_rtmem_formal.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_rtmem_outer.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_general.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_abrt_inner.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_exit.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_fpe_inner.o ABSOLUTE
+    ../clib/signal.s                         0x00000000   Number         0  defsig.o ABSOLUTE
+    ../clib/stdlib.c                         0x00000000   Number         0  exit.o ABSOLUTE
+    ../fplib/ddiv.s                          0x00000000   Number         0  ddiv.o ABSOLUTE
+    ../fplib/dfix.s                          0x00000000   Number         0  dfix.o ABSOLUTE
+    ../fplib/dflt.s                          0x00000000   Number         0  dflt_clz.o ABSOLUTE
+    ../fplib/dnaninf.s                       0x00000000   Number         0  dnaninf.o ABSOLUTE
+    ../fplib/dretinf.s                       0x00000000   Number         0  dretinf.o ABSOLUTE
+    ../fplib/fpinit.s                        0x00000000   Number         0  fpinit.o ABSOLUTE
+    ../fplib/usenofp.s                       0x00000000   Number         0  usenofp.o ABSOLUTE
+    Core\App\gpio.c                          0x00000000   Number         0  gpio.o ABSOLUTE
+    Core\App\main.c                          0x00000000   Number         0  main.o ABSOLUTE
+    Core\App\rcu.c                           0x00000000   Number         0  rcu.o ABSOLUTE
+    Core\App\vk035_it.c                      0x00000000   Number         0  vk035_it.o ABSOLUTE
+    Core\\App\\gpio.c                        0x00000000   Number         0  gpio.o ABSOLUTE
+    Core\\App\\main.c                        0x00000000   Number         0  main.o ABSOLUTE
+    Core\\App\\rcu.c                         0x00000000   Number         0  rcu.o ABSOLUTE
+    Core\\App\\vk035_it.c                    0x00000000   Number         0  vk035_it.o ABSOLUTE
+    dc.s                                     0x00000000   Number         0  dc.o ABSOLUTE
+    platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1921VK035.s 0x00000000   Number         0  startup_k1921vk035.o ABSOLUTE
+    platform\Device\NIIET\K1921VK035\Source\system_K1921VK035.c 0x00000000   Number         0  system_k1921vk035.o ABSOLUTE
+    platform\\Device\\NIIET\\K1921VK035\\Source\\system_K1921VK035.c 0x00000000   Number         0  system_k1921vk035.o ABSOLUTE
+    platform\\plib035\\src\\plib035_adc.c    0x00000000   Number         0  plib035_adc.o ABSOLUTE
+    platform\\plib035\\src\\plib035_can.c    0x00000000   Number         0  plib035_can.o ABSOLUTE
+    platform\\plib035\\src\\plib035_dma.c    0x00000000   Number         0  plib035_dma.o ABSOLUTE
+    platform\\plib035\\src\\plib035_ecap.c   0x00000000   Number         0  plib035_ecap.o ABSOLUTE
+    platform\\plib035\\src\\plib035_gpio.c   0x00000000   Number         0  plib035_gpio.o ABSOLUTE
+    platform\\plib035\\src\\plib035_i2c.c    0x00000000   Number         0  plib035_i2c.o ABSOLUTE
+    platform\\plib035\\src\\plib035_mflash.c 0x00000000   Number         0  plib035_mflash.o ABSOLUTE
+    platform\\plib035\\src\\plib035_pmu.c    0x00000000   Number         0  plib035_pmu.o ABSOLUTE
+    platform\\plib035\\src\\plib035_pwm.c    0x00000000   Number         0  plib035_pwm.o ABSOLUTE
+    platform\\plib035\\src\\plib035_qep.c    0x00000000   Number         0  plib035_qep.o ABSOLUTE
+    platform\\plib035\\src\\plib035_rcu.c    0x00000000   Number         0  plib035_rcu.o ABSOLUTE
+    platform\\plib035\\src\\plib035_spi.c    0x00000000   Number         0  plib035_spi.o ABSOLUTE
+    platform\\plib035\\src\\plib035_tmr.c    0x00000000   Number         0  plib035_tmr.o ABSOLUTE
+    platform\\plib035\\src\\plib035_uart.c   0x00000000   Number         0  plib035_uart.o ABSOLUTE
+    platform\\plib035\\src\\plib035_wdt.c    0x00000000   Number         0  plib035_wdt.o ABSOLUTE
+    platform\\retarget\\retarget.c           0x00000000   Number         0  retarget.o ABSOLUTE
+    platform\\retarget\\retarget_conf.c      0x00000000   Number         0  retarget_conf.o ABSOLUTE
+    platform\plib035\src\plib035_adc.c       0x00000000   Number         0  plib035_adc.o ABSOLUTE
+    platform\plib035\src\plib035_can.c       0x00000000   Number         0  plib035_can.o ABSOLUTE
+    platform\plib035\src\plib035_dma.c       0x00000000   Number         0  plib035_dma.o ABSOLUTE
+    platform\plib035\src\plib035_ecap.c      0x00000000   Number         0  plib035_ecap.o ABSOLUTE
+    platform\plib035\src\plib035_gpio.c      0x00000000   Number         0  plib035_gpio.o ABSOLUTE
+    platform\plib035\src\plib035_i2c.c       0x00000000   Number         0  plib035_i2c.o ABSOLUTE
+    platform\plib035\src\plib035_mflash.c    0x00000000   Number         0  plib035_mflash.o ABSOLUTE
+    platform\plib035\src\plib035_pmu.c       0x00000000   Number         0  plib035_pmu.o ABSOLUTE
+    platform\plib035\src\plib035_pwm.c       0x00000000   Number         0  plib035_pwm.o ABSOLUTE
+    platform\plib035\src\plib035_qep.c       0x00000000   Number         0  plib035_qep.o ABSOLUTE
+    platform\plib035\src\plib035_rcu.c       0x00000000   Number         0  plib035_rcu.o ABSOLUTE
+    platform\plib035\src\plib035_spi.c       0x00000000   Number         0  plib035_spi.o ABSOLUTE
+    platform\plib035\src\plib035_tmr.c       0x00000000   Number         0  plib035_tmr.o ABSOLUTE
+    platform\plib035\src\plib035_uart.c      0x00000000   Number         0  plib035_uart.o ABSOLUTE
+    platform\plib035\src\plib035_wdt.c       0x00000000   Number         0  plib035_wdt.o ABSOLUTE
+    platform\retarget\retarget.c             0x00000000   Number         0  retarget.o ABSOLUTE
+    platform\retarget\retarget_conf.c        0x00000000   Number         0  retarget_conf.o ABSOLUTE
+    !!!main                                  0x00000158   Section        8  __main.o(!!!main)
+    !!!scatter                               0x00000160   Section       52  __scatter.o(!!!scatter)
+    !!dczerorl2                              0x00000194   Section       90  __dczerorl2.o(!!dczerorl2)
+    !!handler_zi                             0x000001f0   Section       28  __scatter_zi.o(!!handler_zi)
+    .ARM.Collect$$_printf_percent$$00000000  0x0000020c   Section        0  _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000)
+    .ARM.Collect$$_printf_percent$$00000009  0x0000020c   Section        6  _printf_d.o(.ARM.Collect$$_printf_percent$$00000009)
+    .ARM.Collect$$_printf_percent$$00000014  0x00000212   Section        6  _printf_s.o(.ARM.Collect$$_printf_percent$$00000014)
+    .ARM.Collect$$_printf_percent$$00000017  0x00000218   Section        4  _printf_percent_end.o(.ARM.Collect$$_printf_percent$$00000017)
+    .ARM.Collect$$libinit$$00000000          0x0000021c   Section        2  libinit.o(.ARM.Collect$$libinit$$00000000)
+    .ARM.Collect$$libinit$$00000001          0x0000021e   Section        4  libinit2.o(.ARM.Collect$$libinit$$00000001)
+    .ARM.Collect$$libinit$$00000004          0x00000222   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000004)
+    .ARM.Collect$$libinit$$0000000A          0x00000222   Section        0  libinit2.o(.ARM.Collect$$libinit$$0000000A)
+    .ARM.Collect$$libinit$$0000000C          0x00000222   Section        0  libinit2.o(.ARM.Collect$$libinit$$0000000C)
+    .ARM.Collect$$libinit$$0000000E          0x00000222   Section        0  libinit2.o(.ARM.Collect$$libinit$$0000000E)
+    .ARM.Collect$$libinit$$00000011          0x00000222   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000011)
+    .ARM.Collect$$libinit$$00000013          0x00000222   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000013)
+    .ARM.Collect$$libinit$$00000015          0x00000222   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000015)
+    .ARM.Collect$$libinit$$00000017          0x00000222   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000017)
+    .ARM.Collect$$libinit$$00000019          0x00000222   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000019)
+    .ARM.Collect$$libinit$$0000001B          0x00000222   Section        0  libinit2.o(.ARM.Collect$$libinit$$0000001B)
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+    CAN14_IRQHandler                         0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    CAN15_IRQHandler                         0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    CAN1_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    CAN2_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    CAN3_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    CAN4_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    CAN5_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    CAN6_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    CAN7_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    CAN8_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    CAN9_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH0_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH10_IRQHandler                      0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH11_IRQHandler                      0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH12_IRQHandler                      0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH13_IRQHandler                      0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH14_IRQHandler                      0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH15_IRQHandler                      0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH1_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH2_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH3_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH4_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH5_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH6_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH7_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH8_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    DMA_CH9_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    ECAP0_IRQHandler                         0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    ECAP1_IRQHandler                         0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    ECAP2_IRQHandler                         0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    FPU_IRQHandler                           0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    GPIOA_IRQHandler                         0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    GPIOB_IRQHandler                         0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    I2C_IRQHandler                           0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    MFLASH_IRQHandler                        0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    PWM0_HD_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    PWM0_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    PWM0_TZ_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    PWM1_HD_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    PWM1_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    PWM1_TZ_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    PWM2_HD_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    PWM2_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    PWM2_TZ_IRQHandler                       0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    QEP_IRQHandler                           0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    RCU_IRQHandler                           0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    SPI_RO_RT_IRQHandler                     0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    SPI_RX_IRQHandler                        0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    SPI_TX_IRQHandler                        0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    TMR0_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    TMR1_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    TMR2_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    TMR3_IRQHandler                          0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    UART0_E_RT_IRQHandler                    0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    UART0_RX_IRQHandler                      0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    UART0_TD_IRQHandler                      0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    UART0_TX_IRQHandler                      0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    UART1_E_RT_IRQHandler                    0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    UART1_RX_IRQHandler                      0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    UART1_TD_IRQHandler                      0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    UART1_TX_IRQHandler                      0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    WDT_IRQHandler                           0x00000263   Thumb Code     0  startup_k1921vk035.o(.text)
+    __user_initial_stackheap                 0x00000265   Thumb Code     0  startup_k1921vk035.o(.text)
+    __I$use$semihosting                      0x00000289   Thumb Code     0  use_no_semi.o(.text)
+    __use_no_semihosting_swi                 0x00000289   Thumb Code     2  use_no_semi.o(.text)
+    __2printf                                0x0000028d   Thumb Code    20  noretval__2printf.o(.text)
+    _printf_pre_padding                      0x000002a5   Thumb Code    44  _printf_pad.o(.text)
+    _printf_post_padding                     0x000002d1   Thumb Code    34  _printf_pad.o(.text)
+    _printf_str                              0x000002f3   Thumb Code    82  _printf_str.o(.text)
+    _printf_int_dec                          0x00000345   Thumb Code   104  _printf_dec.o(.text)
+    __printf                                 0x000003bd   Thumb Code   270  __printf_wp.o(.text)
+    __use_two_region_memory                  0x000004cb   Thumb Code     2  heapauxi.o(.text)
+    __rt_heap_escrow$2region                 0x000004cd   Thumb Code     2  heapauxi.o(.text)
+    __rt_heap_expand$2region                 0x000004cf   Thumb Code     2  heapauxi.o(.text)
+    _printf_int_common                       0x000004d1   Thumb Code   178  _printf_intcommon.o(.text)
+    _printf_cs_common                        0x00000583   Thumb Code    20  _printf_char.o(.text)
+    _printf_char                             0x00000597   Thumb Code    16  _printf_char.o(.text)
+    _printf_string                           0x000005a7   Thumb Code     8  _printf_char.o(.text)
+    _printf_char_file                        0x000005b1   Thumb Code    32  _printf_char_file.o(.text)
+    _printf_char_common                      0x000005df   Thumb Code    32  _printf_char_common.o(.text)
+    __user_setup_stackheap                   0x00000605   Thumb Code    74  sys_stackheap_outer.o(.text)
+    exit                                     0x0000064f   Thumb Code    18  exit.o(.text)
+    __user_libspace                          0x00000661   Thumb Code     8  libspace.o(.text)
+    __user_perproc_libspace                  0x00000661   Thumb Code     0  libspace.o(.text)
+    __user_perthread_libspace                0x00000661   Thumb Code     0  libspace.o(.text)
+    BusFault_Handler                         0x00000669   Thumb Code     2  vk035_it.o(i.BusFault_Handler)
+    ClkInit                                  0x0000066d   Thumb Code   106  system_k1921vk035.o(i.ClkInit)
+    DebugMon_Handler                         0x000006e1   Thumb Code     2  vk035_it.o(i.DebugMon_Handler)
+    Error_Handler                            0x000006e3   Thumb Code     4  main.o(i.Error_Handler)
+    FPUInit                                  0x000006e9   Thumb Code    18  system_k1921vk035.o(i.FPUInit)
+    GPIO_DeInit                              0x00000759   Thumb Code    54  plib035_gpio.o(i.GPIO_DeInit)
+    GPIO_DriveModeConfig                     0x00000839   Thumb Code    80  plib035_gpio.o(i.GPIO_DriveModeConfig)
+    GPIO_InModeConfig                        0x000008b5   Thumb Code    76  plib035_gpio.o(i.GPIO_InModeConfig)
+    GPIO_Init                                0x0000092d   Thumb Code    80  plib035_gpio.o(i.GPIO_Init)
+    GPIO_OutModeConfig                       0x00000a01   Thumb Code    76  plib035_gpio.o(i.GPIO_OutModeConfig)
+    GPIO_PullModeConfig                      0x00000a79   Thumb Code    76  plib035_gpio.o(i.GPIO_PullModeConfig)
+    HardFault_Handler                        0x00000af1   Thumb Code     2  vk035_it.o(i.HardFault_Handler)
+    MemManage_Handler                        0x00000b3d   Thumb Code     2  vk035_it.o(i.MemManage_Handler)
+    NMI_Handler                              0x00000b3f   Thumb Code     2  vk035_it.o(i.NMI_Handler)
+    PendSV_Handler                           0x00000b41   Thumb Code     2  vk035_it.o(i.PendSV_Handler)
+    RCU_PLL_AutoConfig                       0x00000c39   Thumb Code   304  plib035_rcu.o(i.RCU_PLL_AutoConfig)
+    RCU_PLL_Init                             0x00000d99   Thumb Code   212  plib035_rcu.o(i.RCU_PLL_Init)
+    RCU_PLL_StructInit                       0x00000ee9   Thumb Code    16  plib035_rcu.o(i.RCU_PLL_StructInit)
+    RCU_SysClkChangeCmd                      0x00000ef9   Thumb Code   104  plib035_rcu.o(i.RCU_SysClkChangeCmd)
+    SVC_Handler                              0x00000fb1   Thumb Code     2  vk035_it.o(i.SVC_Handler)
+    SysTick_Handler                          0x00000fb5   Thumb Code    10  vk035_it.o(i.SysTick_Handler)
+    SystemCoreClockUpdate                    0x00000fc5   Thumb Code    96  system_k1921vk035.o(i.SystemCoreClockUpdate)
+    SystemInit                               0x00001035   Thumb Code    14  system_k1921vk035.o(i.SystemInit)
+    UsageFault_Handler                       0x00001043   Thumb Code     2  vk035_it.o(i.UsageFault_Handler)
+    _is_digit                                0x00001045   Thumb Code    14  __printf_wp.o(i._is_digit)
+    _sys_exit                                0x00001053   Thumb Code     2  retarget.o(i._sys_exit)
+    assert_failed                            0x00001055   Thumb Code    12  main.o(i.assert_failed)
+    ferror                                   0x00001085   Thumb Code     6  retarget.o(i.ferror)
+    fputc                                    0x0000108b   Thumb Code     4  retarget.o(i.fputc)
+    gpio_init                                0x00001091   Thumb Code   100  gpio.o(i.gpio_init)
+    main                                     0x00001105   Thumb Code     6  main.o(i.main)
+    periph_init                              0x0000110d   Thumb Code    54  main.o(i.periph_init)
+    retarget_init                            0x0000117d   Thumb Code   166  retarget_conf.o(i.retarget_init)
+    retarget_put_char                        0x0000123d   Thumb Code    14  retarget_conf.o(i.retarget_put_char)
+    sysclk_init                              0x00001251   Thumb Code    80  rcu.o(i.sysclk_init)
+    __aeabi_ddiv                             0x000012b9   Thumb Code     0  ddiv.o(x$fpl$ddiv)
+    _ddiv                                    0x000012b9   Thumb Code   552  ddiv.o(x$fpl$ddiv)
+    __aeabi_d2iz                             0x00001569   Thumb Code     0  dfix.o(x$fpl$dfix)
+    _dfix                                    0x00001569   Thumb Code    94  dfix.o(x$fpl$dfix)
+    __aeabi_ui2d                             0x000015c7   Thumb Code     0  dflt_clz.o(x$fpl$dfltu)
+    _dfltu                                   0x000015c7   Thumb Code    38  dflt_clz.o(x$fpl$dfltu)
+    __fpl_dnaninf                            0x000015ed   Thumb Code   156  dnaninf.o(x$fpl$dnaninf)
+    __fpl_dretinf                            0x00001689   Thumb Code    12  dretinf.o(x$fpl$dretinf)
+    _fp_init                                 0x00001695   Thumb Code    10  fpinit.o(x$fpl$fpinit)
+    __fplib_config_fpu_vfp                   0x0000169d   Thumb Code     0  fpinit.o(x$fpl$fpinit)
+    __fplib_config_pureend_doubles           0x0000169d   Thumb Code     0  fpinit.o(x$fpl$fpinit)
+    __I$use$fp                               0x0000169e   Number         0  usenofp.o(x$fpl$usenofp)
+    Region$$Table$$Base                      0x000016a0   Number         0  anon$$obj.o(Region$$Table)
+    Region$$Table$$Limit                     0x000016c0   Number         0  anon$$obj.o(Region$$Table)
+    SystemCoreClock                          0x20000000   Data           4  system_k1921vk035.o(.data)
+    uwTick                                   0x20000004   Data           4  system_k1921vk035.o(.data)
+    __stdout                                 0x2000018c   Data           4  retarget.o(.data)
+    __libspace_start                         0x20000190   Data          96  libspace.o(.bss)
+    __temporary_stack_top$libspace           0x200001f0   Data           0  libspace.o(.bss)
+
+
+
+==============================================================================
+
+Memory Map of the image
+
+  Image Entry point : 0x00000249
+
+  Load Region LR_1 (Base: 0x00000000, Size: 0x00001850, Max: 0xffffffff, ABSOLUTE, COMPRESSED[0x000016e4])
+
+    Execution Region ER_RO (Exec base: 0x00000000, Load base: 0x00000000, Size: 0x000016c0, Max: 0xffffffff, ABSOLUTE)
+
+    Exec Addr    Load Addr    Size         Type   Attr      Idx    E Section Name        Object
+
+    0x00000000   0x00000000   0x00000158   Data   RO           77    RESET               startup_k1921vk035.o
+    0x00000158   0x00000158   0x00000008   Code   RO         1417  * !!!main             c_w.l(__main.o)
+    0x00000160   0x00000160   0x00000034   Code   RO         1602    !!!scatter          c_w.l(__scatter.o)
+    0x00000194   0x00000194   0x0000005a   Code   RO         1600    !!dczerorl2         c_w.l(__dczerorl2.o)
+    0x000001ee   0x000001ee   0x00000002   PAD
+    0x000001f0   0x000001f0   0x0000001c   Code   RO         1604    !!handler_zi        c_w.l(__scatter_zi.o)
+    0x0000020c   0x0000020c   0x00000000   Code   RO         1414    .ARM.Collect$$_printf_percent$$00000000  c_w.l(_printf_percent.o)
+    0x0000020c   0x0000020c   0x00000006   Code   RO         1413    .ARM.Collect$$_printf_percent$$00000009  c_w.l(_printf_d.o)
+    0x00000212   0x00000212   0x00000006   Code   RO         1412    .ARM.Collect$$_printf_percent$$00000014  c_w.l(_printf_s.o)
+    0x00000218   0x00000218   0x00000004   Code   RO         1440    .ARM.Collect$$_printf_percent$$00000017  c_w.l(_printf_percent_end.o)
+    0x0000021c   0x0000021c   0x00000002   Code   RO         1474    .ARM.Collect$$libinit$$00000000  c_w.l(libinit.o)
+    0x0000021e   0x0000021e   0x00000004   Code   RO         1480    .ARM.Collect$$libinit$$00000001  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         1483    .ARM.Collect$$libinit$$00000004  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         1486    .ARM.Collect$$libinit$$0000000A  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         1488    .ARM.Collect$$libinit$$0000000C  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         1490    .ARM.Collect$$libinit$$0000000E  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         1493    .ARM.Collect$$libinit$$00000011  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         1495    .ARM.Collect$$libinit$$00000013  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         1497    .ARM.Collect$$libinit$$00000015  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         1499    .ARM.Collect$$libinit$$00000017  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         1501    .ARM.Collect$$libinit$$00000019  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         1503    .ARM.Collect$$libinit$$0000001B  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         1505    .ARM.Collect$$libinit$$0000001D  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         1507    .ARM.Collect$$libinit$$0000001F  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         1509    .ARM.Collect$$libinit$$00000021  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         1511    .ARM.Collect$$libinit$$00000023  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         1513    .ARM.Collect$$libinit$$00000025  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         1517    .ARM.Collect$$libinit$$0000002C  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         1519    .ARM.Collect$$libinit$$0000002E  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         1521    .ARM.Collect$$libinit$$00000030  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000000   Code   RO         1523    .ARM.Collect$$libinit$$00000032  c_w.l(libinit2.o)
+    0x00000222   0x00000222   0x00000002   Code   RO         1524    .ARM.Collect$$libinit$$00000033  c_w.l(libinit2.o)
+    0x00000224   0x00000224   0x00000002   Code   RO         1542    .ARM.Collect$$libshutdown$$00000000  c_w.l(libshutdown.o)
+    0x00000226   0x00000226   0x00000000   Code   RO         1552    .ARM.Collect$$libshutdown$$00000002  c_w.l(libshutdown2.o)
+    0x00000226   0x00000226   0x00000000   Code   RO         1554    .ARM.Collect$$libshutdown$$00000004  c_w.l(libshutdown2.o)
+    0x00000226   0x00000226   0x00000000   Code   RO         1556    .ARM.Collect$$libshutdown$$00000006  c_w.l(libshutdown2.o)
+    0x00000226   0x00000226   0x00000000   Code   RO         1559    .ARM.Collect$$libshutdown$$00000009  c_w.l(libshutdown2.o)
+    0x00000226   0x00000226   0x00000000   Code   RO         1562    .ARM.Collect$$libshutdown$$0000000C  c_w.l(libshutdown2.o)
+    0x00000226   0x00000226   0x00000000   Code   RO         1564    .ARM.Collect$$libshutdown$$0000000E  c_w.l(libshutdown2.o)
+    0x00000226   0x00000226   0x00000000   Code   RO         1567    .ARM.Collect$$libshutdown$$00000011  c_w.l(libshutdown2.o)
+    0x00000226   0x00000226   0x00000002   Code   RO         1568    .ARM.Collect$$libshutdown$$00000012  c_w.l(libshutdown2.o)
+    0x00000228   0x00000228   0x00000000   Code   RO         1433    .ARM.Collect$$rtentry$$00000000  c_w.l(__rtentry.o)
+    0x00000228   0x00000228   0x00000000   Code   RO         1447    .ARM.Collect$$rtentry$$00000002  c_w.l(__rtentry2.o)
+    0x00000228   0x00000228   0x00000006   Code   RO         1459    .ARM.Collect$$rtentry$$00000004  c_w.l(__rtentry4.o)
+    0x0000022e   0x0000022e   0x00000000   Code   RO         1449    .ARM.Collect$$rtentry$$00000009  c_w.l(__rtentry2.o)
+    0x0000022e   0x0000022e   0x00000004   Code   RO         1450    .ARM.Collect$$rtentry$$0000000A  c_w.l(__rtentry2.o)
+    0x00000232   0x00000232   0x00000000   Code   RO         1452    .ARM.Collect$$rtentry$$0000000C  c_w.l(__rtentry2.o)
+    0x00000232   0x00000232   0x00000008   Code   RO         1453    .ARM.Collect$$rtentry$$0000000D  c_w.l(__rtentry2.o)
+    0x0000023a   0x0000023a   0x00000002   Code   RO         1478    .ARM.Collect$$rtexit$$00000000  c_w.l(rtexit.o)
+    0x0000023c   0x0000023c   0x00000000   Code   RO         1526    .ARM.Collect$$rtexit$$00000002  c_w.l(rtexit2.o)
+    0x0000023c   0x0000023c   0x00000004   Code   RO         1527    .ARM.Collect$$rtexit$$00000003  c_w.l(rtexit2.o)
+    0x00000240   0x00000240   0x00000006   Code   RO         1528    .ARM.Collect$$rtexit$$00000004  c_w.l(rtexit2.o)
+    0x00000246   0x00000246   0x00000002   PAD
+    0x00000248   0x00000248   0x00000040   Code   RO           78  * .text               startup_k1921vk035.o
+    0x00000288   0x00000288   0x00000002   Code   RO         1378    .text               c_w.l(use_no_semi.o)
+    0x0000028a   0x0000028a   0x00000002   PAD
+    0x0000028c   0x0000028c   0x00000018   Code   RO         1382    .text               c_w.l(noretval__2printf.o)
+    0x000002a4   0x000002a4   0x0000004e   Code   RO         1386    .text               c_w.l(_printf_pad.o)
+    0x000002f2   0x000002f2   0x00000052   Code   RO         1388    .text               c_w.l(_printf_str.o)
+    0x00000344   0x00000344   0x00000078   Code   RO         1390    .text               c_w.l(_printf_dec.o)
+    0x000003bc   0x000003bc   0x0000010e   Code   RO         1400    .text               c_w.l(__printf_wp.o)
+    0x000004ca   0x000004ca   0x00000006   Code   RO         1415    .text               c_w.l(heapauxi.o)
+    0x000004d0   0x000004d0   0x000000b2   Code   RO         1434    .text               c_w.l(_printf_intcommon.o)
+    0x00000582   0x00000582   0x0000002c   Code   RO         1436    .text               c_w.l(_printf_char.o)
+    0x000005ae   0x000005ae   0x00000002   PAD
+    0x000005b0   0x000005b0   0x00000024   Code   RO         1438    .text               c_w.l(_printf_char_file.o)
+    0x000005d4   0x000005d4   0x00000030   Code   RO         1461    .text               c_w.l(_printf_char_common.o)
+    0x00000604   0x00000604   0x0000004a   Code   RO         1463    .text               c_w.l(sys_stackheap_outer.o)
+    0x0000064e   0x0000064e   0x00000012   Code   RO         1467    .text               c_w.l(exit.o)
+    0x00000660   0x00000660   0x00000008   Code   RO         1475    .text               c_w.l(libspace.o)
+    0x00000668   0x00000668   0x00000002   Code   RO          274    i.BusFault_Handler  vk035_it.o
+    0x0000066a   0x0000066a   0x00000002   PAD
+    0x0000066c   0x0000066c   0x00000074   Code   RO            4    i.ClkInit           system_k1921vk035.o
+    0x000006e0   0x000006e0   0x00000002   Code   RO          275    i.DebugMon_Handler  vk035_it.o
+    0x000006e2   0x000006e2   0x00000004   Code   RO           85    i.Error_Handler     main.o
+    0x000006e6   0x000006e6   0x00000002   PAD
+    0x000006e8   0x000006e8   0x00000018   Code   RO            5    i.FPUInit           system_k1921vk035.o
+    0x00000700   0x00000700   0x00000058   Code   RO          571    i.GPIO_AltFuncCmd   plib035_gpio.o
+    0x00000758   0x00000758   0x00000064   Code   RO          572    i.GPIO_DeInit       plib035_gpio.o
+    0x000007bc   0x000007bc   0x0000007c   Code   RO          573    i.GPIO_DigitalCmd   plib035_gpio.o
+    0x00000838   0x00000838   0x0000007c   Code   RO          574    i.GPIO_DriveModeConfig  plib035_gpio.o
+    0x000008b4   0x000008b4   0x00000078   Code   RO          575    i.GPIO_InModeConfig  plib035_gpio.o
+    0x0000092c   0x0000092c   0x00000050   Code   RO          576    i.GPIO_Init         plib035_gpio.o
+    0x0000097c   0x0000097c   0x0000002c   Code   RO          577    i.GPIO_ModeConfig   plib035_gpio.o
+    0x000009a8   0x000009a8   0x00000058   Code   RO          578    i.GPIO_OutCmd       plib035_gpio.o
+    0x00000a00   0x00000a00   0x00000078   Code   RO          579    i.GPIO_OutModeConfig  plib035_gpio.o
+    0x00000a78   0x00000a78   0x00000078   Code   RO          580    i.GPIO_PullModeConfig  plib035_gpio.o
+    0x00000af0   0x00000af0   0x00000002   Code   RO          276    i.HardFault_Handler  vk035_it.o
+    0x00000af2   0x00000af2   0x00000002   PAD
+    0x00000af4   0x00000af4   0x00000048   Code   RO          977    i.MFLASH_LatencyConfig  plib035_rcu.o
+    0x00000b3c   0x00000b3c   0x00000002   Code   RO          277    i.MemManage_Handler  vk035_it.o
+    0x00000b3e   0x00000b3e   0x00000002   Code   RO          278    i.NMI_Handler       vk035_it.o
+    0x00000b40   0x00000b40   0x00000002   Code   RO          279    i.PendSV_Handler    vk035_it.o
+    0x00000b42   0x00000b42   0x00000002   PAD
+    0x00000b44   0x00000b44   0x0000006c   Code   RO          582    i.RCU_AHBRstCmd     plib035_gpio.o
+    0x00000bb0   0x00000bb0   0x00000088   Code   RO          236    i.RCU_ClkOutConfig  rcu.o
+    0x00000c38   0x00000c38   0x00000160   Code   RO          989    i.RCU_PLL_AutoConfig  plib035_rcu.o
+    0x00000d98   0x00000d98   0x00000100   Code   RO          991    i.RCU_PLL_Init      plib035_rcu.o
+    0x00000e98   0x00000e98   0x00000050   Code   RO          992    i.RCU_PLL_OutCmd    plib035_rcu.o
+    0x00000ee8   0x00000ee8   0x00000010   Code   RO          993    i.RCU_PLL_StructInit  plib035_rcu.o
+    0x00000ef8   0x00000ef8   0x000000b8   Code   RO          994    i.RCU_SysClkChangeCmd  plib035_rcu.o
+    0x00000fb0   0x00000fb0   0x00000002   Code   RO          280    i.SVC_Handler       vk035_it.o
+    0x00000fb2   0x00000fb2   0x00000002   PAD
+    0x00000fb4   0x00000fb4   0x00000010   Code   RO          281    i.SysTick_Handler   vk035_it.o
+    0x00000fc4   0x00000fc4   0x00000070   Code   RO            6    i.SystemCoreClockUpdate  system_k1921vk035.o
+    0x00001034   0x00001034   0x0000000e   Code   RO            7    i.SystemInit        system_k1921vk035.o
+    0x00001042   0x00001042   0x00000002   Code   RO          282    i.UsageFault_Handler  vk035_it.o
+    0x00001044   0x00001044   0x0000000e   Code   RO         1402    i._is_digit         c_w.l(__printf_wp.o)
+    0x00001052   0x00001052   0x00000002   Code   RO         1278    i._sys_exit         retarget.o
+    0x00001054   0x00001054   0x00000030   Code   RO           86    i.assert_failed     main.o
+    0x00001084   0x00001084   0x00000006   Code   RO         1280    i.ferror            retarget.o
+    0x0000108a   0x0000108a   0x00000004   Code   RO         1282    i.fputc             retarget.o
+    0x0000108e   0x0000108e   0x00000002   PAD
+    0x00001090   0x00001090   0x00000074   Code   RO          204    i.gpio_init         gpio.o
+    0x00001104   0x00001104   0x00000006   Code   RO           87    i.main              main.o
+    0x0000110a   0x0000110a   0x00000002   PAD
+    0x0000110c   0x0000110c   0x00000070   Code   RO           88    i.periph_init       main.o
+    0x0000117c   0x0000117c   0x000000c0   Code   RO         1344    i.retarget_init     retarget_conf.o
+    0x0000123c   0x0000123c   0x00000014   Code   RO         1345    i.retarget_put_char  retarget_conf.o
+    0x00001250   0x00001250   0x00000068   Code   RO          237    i.sysclk_init       rcu.o
+    0x000012b8   0x000012b8   0x000002b0   Code   RO         1420    x$fpl$ddiv          fz_wm.l(ddiv.o)
+    0x00001568   0x00001568   0x0000005e   Code   RO         1423    x$fpl$dfix          fz_wm.l(dfix.o)
+    0x000015c6   0x000015c6   0x00000026   Code   RO         1427    x$fpl$dfltu         fz_wm.l(dflt_clz.o)
+    0x000015ec   0x000015ec   0x0000009c   Code   RO         1441    x$fpl$dnaninf       fz_wm.l(dnaninf.o)
+    0x00001688   0x00001688   0x0000000c   Code   RO         1443    x$fpl$dretinf       fz_wm.l(dretinf.o)
+    0x00001694   0x00001694   0x0000000a   Code   RO         1534    x$fpl$fpinit        fz_wm.l(fpinit.o)
+    0x0000169e   0x0000169e   0x00000000   Code   RO         1445    x$fpl$usenofp       fz_wm.l(usenofp.o)
+    0x0000169e   0x0000169e   0x00000002   PAD
+    0x000016a0   0x000016a0   0x00000020   Data   RO         1598    Region$$Table       anon$$obj.o
+
+
+    Execution Region ER_RW (Exec base: 0x20000000, Load base: 0x000016c0, Size: 0x00000190, Max: 0xffffffff, ABSOLUTE, COMPRESSED[0x00000024])
+
+    Exec Addr    Load Addr    Size         Type   Attr      Idx    E Section Name        Object
+
+    0x20000000   COMPRESSED   0x00000004   Data   RW            8    .data               system_k1921vk035.o
+    0x20000004   COMPRESSED   0x00000004   Data   RW            9    .data               system_k1921vk035.o
+    0x20000008   COMPRESSED   0x00000180   Data   RW          205    .data               gpio.o
+    0x20000188   COMPRESSED   0x00000001   Data   RW          238    .data               rcu.o
+    0x20000189   COMPRESSED   0x00000003   PAD
+    0x2000018c   COMPRESSED   0x00000004   Data   RW         1283    .data               retarget.o
+
+
+    Execution Region ER_ZI (Exec base: 0x20000190, Load base: 0x000016e4, Size: 0x00000660, Max: 0xffffffff, ABSOLUTE)
+
+    Exec Addr    Load Addr    Size         Type   Attr      Idx    E Section Name        Object
+
+    0x20000190        -       0x00000060   Zero   RW         1476    .bss                c_w.l(libspace.o)
+    0x200001f0        -       0x00000200   Zero   RW           76    HEAP                startup_k1921vk035.o
+    0x200003f0        -       0x00000400   Zero   RW           75    STACK               startup_k1921vk035.o
+
+
+==============================================================================
+
+Image component sizes
+
+
+      Code (inc. data)   RO Data    RW Data    ZI Data      Debug   Object Name
+
+       116         16          0        384          0      10416   gpio.o
+       170         94          0          0          0       8505   main.o
+      1116        344          0          0          0      12904   plib035_gpio.o
+       960        262          0          0          0      15871   plib035_rcu.o
+       240         74          0          1          0      40297   rcu.o
+        12          0          0          4          0       3303   retarget.o
+       212         32          0          0          0       1204   retarget_conf.o
+        64         26        344          0       1536        892   startup_k1921vk035.o
+       266         32          0          8          0     197926   system_k1921vk035.o
+        32          6          0          0          0       3974   vk035_it.o
+
+    ----------------------------------------------------------------------
+      3202        886        376        400       1536     295292   Object Totals
+         0          0         32          0          0          0   (incl. Generated)
+        14          0          0          3          0          0   (incl. Padding)
+
+    ----------------------------------------------------------------------
+
+      Code (inc. data)   RO Data    RW Data    ZI Data      Debug   Library Member Name
+
+        90          0          0          0          0          0   __dczerorl2.o
+         8          0          0          0          0         68   __main.o
+       284          0          0          0          0        156   __printf_wp.o
+         0          0          0          0          0          0   __rtentry.o
+        12          0          0          0          0          0   __rtentry2.o
+         6          0          0          0          0          0   __rtentry4.o
+        52          8          0          0          0          0   __scatter.o
+        28          0          0          0          0          0   __scatter_zi.o
+        44          0          0          0          0        108   _printf_char.o
+        48          6          0          0          0         96   _printf_char_common.o
+        36          4          0          0          0         80   _printf_char_file.o
+         6          0          0          0          0          0   _printf_d.o
+       120         16          0          0          0         92   _printf_dec.o
+       178          0          0          0          0         88   _printf_intcommon.o
+        78          0          0          0          0        108   _printf_pad.o
+         0          0          0          0          0          0   _printf_percent.o
+         4          0          0          0          0          0   _printf_percent_end.o
+         6          0          0          0          0          0   _printf_s.o
+        82          0          0          0          0         80   _printf_str.o
+        18          0          0          0          0         80   exit.o
+         6          0          0          0          0        152   heapauxi.o
+         2          0          0          0          0          0   libinit.o
+         6          0          0          0          0          0   libinit2.o
+         2          0          0          0          0          0   libshutdown.o
+         2          0          0          0          0          0   libshutdown2.o
+         8          4          0          0         96         68   libspace.o
+        24          4          0          0          0         84   noretval__2printf.o
+         2          0          0          0          0          0   rtexit.o
+        10          0          0          0          0          0   rtexit2.o
+        74          0          0          0          0         80   sys_stackheap_outer.o
+         2          0          0          0          0         68   use_no_semi.o
+       688        140          0          0          0        256   ddiv.o
+        94          4          0          0          0        140   dfix.o
+        38          0          0          0          0        116   dflt_clz.o
+       156          4          0          0          0        140   dnaninf.o
+        12          0          0          0          0        116   dretinf.o
+        10          0          0          0          0        116   fpinit.o
+         0          0          0          0          0          0   usenofp.o
+
+    ----------------------------------------------------------------------
+      2246        190          0          0         96       2292   Library Totals
+        10          0          0          0          0          0   (incl. Padding)
+
+    ----------------------------------------------------------------------
+
+      Code (inc. data)   RO Data    RW Data    ZI Data      Debug   Library Name
+
+      1238         42          0          0         96       1408   c_w.l
+       998        148          0          0          0        884   fz_wm.l
+
+    ----------------------------------------------------------------------
+      2246        190          0          0         96       2292   Library Totals
+
+    ----------------------------------------------------------------------
+
+==============================================================================
+
+
+      Code (inc. data)   RO Data    RW Data    ZI Data      Debug   
+
+      5448       1076        376        400       1632     292960   Grand Totals
+      5448       1076        376         36       1632     292960   ELF Image Totals (compressed)
+      5448       1076        376         36          0          0   ROM Totals
+
+==============================================================================
+
+    Total RO  Size (Code + RO Data)                 5824 (   5.69kB)
+    Total RW  Size (RW Data + ZI Data)              2032 (   1.98kB)
+    Total ROM Size (Code + RO Data + RW Data)       5860 (   5.72kB)
+
+==============================================================================
+

Template.uvoptx

@@ -0,0 +1,750 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc; *.md</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp; *.cc; *.cxx</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>template</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\Listings\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>0</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>4</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>Segger\JL2CM3.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMRTXEVENTFLAGS</Key>
+          <Name>-L70 -Z18 -C0 -M0 -T1</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>JL2CM3</Key>
+          <Name>-U-O14 -O14 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN1 -FF0K1921VK035.FLM -FS00 -FL010000 -FP0($$Device:K1921VK035$Flash\K1921VK035.FLM)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0K1921VK035 -FS00 -FL010000 -FP0($$Device:K1921VK035$Flash\K1921VK035.FLM))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <WatchWindow1>
+        <Ww>
+          <count>0</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>uwTick,0x0A</ItemText>
+        </Ww>
+        <Ww>
+          <count>1</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>start,0x0A</ItemText>
+        </Ww>
+        <Ww>
+          <count>2</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>uwTick,0x0A</ItemText>
+        </Ww>
+        <Ww>
+          <count>3</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>(uwTick-start) &lt; ms</ItemText>
+        </Ww>
+        <Ww>
+          <count>4</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>ms,0x0A</ItemText>
+        </Ww>
+        <Ww>
+          <count>5</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>local_time()</ItemText>
+        </Ww>
+        <Ww>
+          <count>6</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>GPIOA</ItemText>
+        </Ww>
+      </WatchWindow1>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>Config</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
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+</ProjectOpt>

Template.uvprojx

@@ -0,0 +1,628 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>template</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060960::V5.06 update 7 (build 960)::.\ARMCC</pCCUsed>
+      <uAC6>0</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>K1921VK035</Device>
+          <Vendor>Generic</Vendor>
+          <PackID>NIIET.K1921VK035_DFP.2.0.6</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x4000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC3000 -FN2 -FF0K1921VK035 -FS00 -FL010000 -FF1K1921VK035_SRV -FS10 -FL1100000 -FP0($$Device:K1921VK035$Flash\K1921VK035.FLM) -FP1($$Device:K1921VK035$Flash\K1921VK035_SRV.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:K1921VK035$Device\Include\K1921VK035.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:K1921VK035$SVD\K1921VK035.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>Firmware</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <RvdsCdeCp>0</RvdsCdeCp>
+            <nBranchProt>0</nBranchProt>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x4000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x10000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x4000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>3</v6Lang>
+            <v6LangP>5</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>RETARGET, RETARGET_USE_UART, SYSCLK_OSE, OSECLK_VAL=24000000, CKO_NONE, USE_FULL_ASSERT</Define>
+              <Undefine></Undefine>
+              <IncludePath>.\platform\CMSIS\Core\Include;.\platform\Device\NIIET\K1921VK035\Include;.\platform\plib035\inc;.\platform\retarget;.\platform\retarget\Template\K1921VK035;.\Core\App;.\Core\Config;.\Core\ExtendedLibs;.\Core\ExtendedLibs\MyLibs\Inc;.\Core\ExtendedLibs\RTT</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <ClangAsOpt>4</ClangAsOpt>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Config</GroupName>
+          <Files>
+            <File>
+              <FileName>mylibs_config.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Core\Config\mylibs_config.h</FilePath>
+            </File>
+            <File>
+              <FileName>mylibs_include.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Core\Config\mylibs_include.h</FilePath>
+            </File>
+            <File>
+              <FileName>SEGGER_RTT_Conf.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Core\Config\SEGGER_RTT_Conf.h</FilePath>
+            </File>
+            <File>
+              <FileName>gpio.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Core\App\gpio.h</FilePath>
+            </File>
+            <File>
+              <FileName>rcu.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Core\App\rcu.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>src</GroupName>
+          <Files>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Core\App\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Core\App\gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>rcu.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Core\App\rcu.c</FilePath>
+            </File>
+            <File>
+              <FileName>vk035_it.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Core\App\vk035_it.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>MyLibs</GroupName>
+          <Files>
+            <File>
+              <FileName>bench_time.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Core\ExtendedLibs\MyLibs\Inc\bench_time.h</FilePath>
+            </File>
+            <File>
+              <FileName>bit_access.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Core\ExtendedLibs\MyLibs\Inc\bit_access.h</FilePath>
+            </File>
+            <File>
+              <FileName>gen_optimizer.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Core\ExtendedLibs\MyLibs\Inc\gen_optimizer.h</FilePath>
+            </File>
+            <File>
+              <FileName>mylibs_defs.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Core\ExtendedLibs\MyLibs\Inc\mylibs_defs.h</FilePath>
+            </File>
+            <File>
+              <FileName>trace.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Core\ExtendedLibs\MyLibs\Inc\trace.h</FilePath>
+            </File>
+            <File>
+              <FileName>trackers.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Core\ExtendedLibs\MyLibs\Inc\trackers.h</FilePath>
+            </File>
+            <File>
+              <FileName>SEGGER_RTT.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Core\ExtendedLibs\RTT\SEGGER_RTT.c</FilePath>
+            </File>
+            <File>
+              <FileName>SEGGER_RTT_printf.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Core\ExtendedLibs\RTT\SEGGER_RTT_printf.c</FilePath>
+            </File>
+            <File>
+              <FileName>filters.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Core\ExtendedLibs\MyLibs\Inc\filters.h</FilePath>
+            </File>
+            <File>
+              <FileName>filters.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Core\ExtendedLibs\MyLibs\Src\filters.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>startup</GroupName>
+          <Files>
+            <File>
+              <FileName>system_K1921VK035.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\platform\Device\NIIET\K1921VK035\Source\system_K1921VK035.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup_K1921VK035.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1921VK035.s</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>plib035</GroupName>
+          <Files>
+            <File>
+              <FileName>plib035_adc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\platform\plib035\src\plib035_adc.c</FilePath>
+            </File>
+            <File>
+              <FileName>plib035_can.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\platform\plib035\src\plib035_can.c</FilePath>
+            </File>
+            <File>
+              <FileName>plib035_dma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\platform\plib035\src\plib035_dma.c</FilePath>
+            </File>
+            <File>
+              <FileName>plib035_ecap.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\platform\plib035\src\plib035_ecap.c</FilePath>
+            </File>
+            <File>
+              <FileName>plib035_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\platform\plib035\src\plib035_gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>plib035_i2c.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\platform\plib035\src\plib035_i2c.c</FilePath>
+            </File>
+            <File>
+              <FileName>plib035_mflash.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\platform\plib035\src\plib035_mflash.c</FilePath>
+            </File>
+            <File>
+              <FileName>plib035_pmu.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\platform\plib035\src\plib035_pmu.c</FilePath>
+            </File>
+            <File>
+              <FileName>plib035_pwm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\platform\plib035\src\plib035_pwm.c</FilePath>
+            </File>
+            <File>
+              <FileName>plib035_qep.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\platform\plib035\src\plib035_qep.c</FilePath>
+            </File>
+            <File>
+              <FileName>plib035_rcu.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\platform\plib035\src\plib035_rcu.c</FilePath>
+            </File>
+            <File>
+              <FileName>plib035_spi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\platform\plib035\src\plib035_spi.c</FilePath>
+            </File>
+            <File>
+              <FileName>plib035_tmr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\platform\plib035\src\plib035_tmr.c</FilePath>
+            </File>
+            <File>
+              <FileName>plib035_uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\platform\plib035\src\plib035_uart.c</FilePath>
+            </File>
+            <File>
+              <FileName>plib035_wdt.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\platform\plib035\src\plib035_wdt.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Retarget</GroupName>
+          <Files>
+            <File>
+              <FileName>retarget.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\platform\retarget\retarget.c</FilePath>
+            </File>
+            <File>
+              <FileName>retarget_conf.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\platform\retarget\retarget_conf.c</FilePath>
+            </File>
+            <File>
+              <FileName>retarget_conf.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\platform\retarget\retarget_conf.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components/>
+    <files/>
+  </RTE>
+
+  <LayerInfo>
+    <Layers>
+      <Layer>
+        <LayName>UKSI</LayName>
+        <LayPrjMark>1</LayPrjMark>
+      </Layer>
+    </Layers>
+  </LayerInfo>
+
+</Project>

platform/CMSIS/Core/Include/cmsis_armcc.h

@@ -0,0 +1,867 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (ARM compiler V5) header file
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+  #define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+  #define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+  #define __ARM_ARCH_7EM__          1
+#endif
+
+  /* __ARM_ARCH_8M_BASE__  not applicable */
+  /* __ARM_ARCH_8M_MAIN__  not applicable */
+
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         __packed union
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+                  
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return result;
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */

platform/CMSIS/Core/Include/cmsis_armclang.h

@@ -0,0 +1,1815 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler ARMCLANG (ARM compiler V6) header file
+ * @version  V5.0.3
+ * @date     27. March 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header   /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h>    /* Compatibility header for ARM Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
+#endif                                           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+  return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR()      ((uint32_t)0U)
+#endif
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __set_FPSCR      __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x)      ((void)(x))
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF);
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF);
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF);
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV(value)   __builtin_bswap32(value)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)     __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT            __builtin_arm_rbit
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+  int32_t result;
+
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */

platform/CMSIS/Core/Include/cmsis_cmcpp.h

@@ -0,0 +1,127 @@
+/**************************************************************************//**
+ * @file     cmsis_cmcpp.h
+ * @brief    CMSIS compiler CMCPP_ARM header file
+ * @version  V5.0.2
+ * @date     13. February 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_CMCPP_H
+#define __CMSIS_CMCPP_H
+
+/* ignore some GCC warnings */
+/*#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter" */
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   static inline /*__attribute__((always_inline)) static inline*/
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            /*__attribute__((__noreturn__))*/
+#endif
+#ifndef   __USED
+  #define __USED                                 /*__attribute__((used))*/
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 /*__attribute__((weak))*/
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __packed
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         __packed union
+#endif
+
+//#ifndef   __UNALIGNED_UINT32        /* deprecated */
+/*  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif   */
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           /*__attribute__((aligned(x)))*/
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             /*__restrict*/
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+
+#endif /* __CMSISG_CMCPP_H */
+

platform/CMSIS/Core/Include/cmsis_compiler.h

@@ -0,0 +1,264 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * ARM Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * ARM Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * CMCPP-ARM Compiler
+ */
+#elif defined ( __CMCPPARM__ )
+  #include "cmsis_cmcpp.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+  
+/*
+ * TI ARM Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

platform/CMSIS/Core/Include/cmsis_gcc.h

@@ -0,0 +1,2026 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler GCC header file
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+#endif                                           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+  return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  return __builtin_arm_get_fpscr();
+#else
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#endif
+#else
+  return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  __builtin_arm_set_fpscr(fpscr);
+#else
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+  (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP()                             __ASM volatile ("nop")
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI()                             __ASM volatile ("wfi")
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE()                             __ASM volatile ("wfe")
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV()                             __ASM volatile ("sev")
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (int16_t)__builtin_bswap16(value);
+#else
+  int16_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return result;
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (__ARM_FEATURE_DSP == 1)                             /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */

platform/CMSIS/Core/Include/cmsis_iccarm.h

@@ -0,0 +1,906 @@
+/**************************************************************************//**
+ * @file     cmsis_iccarm.h
+ * @brief    CMSIS compiler ICCARM (IAR compiler) header file
+ * @version  V5.0.3
+ * @date     29. August 2017
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+  #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+  #define __ICCARM_V8 1
+#else
+  #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+  #if __ICCARM_V8
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #elif (__VER__ >= 7080000)
+    /* Needs IAR language extensions */
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #else
+    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+    #if __ARM_ARCH == 6
+      #define __ARM_ARCH_6M__ 1
+    #elif __ARM_ARCH == 7
+      #if __ARM_FEATURE_DSP
+        #define __ARM_ARCH_7EM__ 1
+      #else
+        #define __ARM_ARCH_7M__ 1
+      #endif
+    #endif /* __ARM_ARCH */
+  #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+    #define __ARM_ARCH_6M__ 1
+  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+    #define __ARM_ARCH_7M__ 1
+  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+    #define __ARM_ARCH_7EM__  1
+  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #else
+    #error "Unknown target."
+  #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+  #define __IAR_M0_FAMILY  1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+  #define __IAR_M0_FAMILY  1
+#else
+  #define __IAR_M0_FAMILY  0
+#endif
+
+
+#ifndef __ASM
+  #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+  #define __INLINE inline
+#endif
+
+#ifndef   __NO_RETURN
+  #if __ICCARM_V8
+    #define __NO_RETURN __attribute__((__noreturn__))
+  #else
+    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+  #endif
+#endif
+
+#ifndef   __PACKED
+  #if __ICCARM_V8
+    #define __PACKED __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED __packed
+  #endif
+#endif
+
+#ifndef   __PACKED_STRUCT
+  #if __ICCARM_V8
+    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_STRUCT __packed struct
+  #endif
+#endif
+
+#ifndef   __PACKED_UNION
+  #if __ICCARM_V8
+    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_UNION __packed union
+  #endif
+#endif
+
+#ifndef   __RESTRICT
+  #define __RESTRICT restrict
+#endif
+
+
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE static inline
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+  return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+  *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+  return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+  *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32   /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct  __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef   __USED
+  #if __ICCARM_V8
+    #define __USED __attribute__((used))
+  #else
+    #define __USED _Pragma("__root")
+  #endif
+#endif
+
+#ifndef   __WEAK
+  #if __ICCARM_V8
+    #define __WEAK __attribute__((weak))
+  #else
+    #define __WEAK _Pragma("__weak")
+  #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+  #define __ICCARM_INTRINSICS_VERSION__  0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+  #if defined(__CLZ)
+    #undef __CLZ
+  #endif
+  #if defined(__REVSH)
+    #undef __REVSH
+  #endif
+  #if defined(__RBIT)
+    #undef __RBIT
+  #endif
+  #if defined(__SSAT)
+    #undef __SSAT
+  #endif
+  #if defined(__USAT)
+    #undef __USAT
+  #endif
+
+  #include "iccarm_builtin.h"
+
+  #define __disable_fault_irq __iar_builtin_disable_fiq
+  #define __disable_irq       __iar_builtin_disable_interrupt
+  #define __enable_fault_irq  __iar_builtin_enable_fiq
+  #define __enable_irq        __iar_builtin_enable_interrupt
+  #define __arm_rsr           __iar_builtin_rsr
+  #define __arm_wsr           __iar_builtin_wsr
+
+
+  #define __get_APSR()                (__arm_rsr("APSR"))
+  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
+  #define __get_CONTROL()             (__arm_rsr("CONTROL"))
+  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
+
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
+    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
+  #else
+    #define __get_FPSCR()             ( 0 )
+    #define __set_FPSCR(VALUE)        ((void)VALUE)
+  #endif
+
+  #define __get_IPSR()                (__arm_rsr("IPSR"))
+  #define __get_MSP()                 (__arm_rsr("MSP"))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __get_MSPLIM()            (0U)
+  #else
+    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))
+  #endif
+  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
+  #define __get_PSP()                 (__arm_rsr("PSP"))
+  
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __get_PSPLIM()            (0U)
+  #else
+    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))
+  #endif
+  
+  #define __get_xPSR()                (__arm_rsr("xPSR"))
+
+  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
+  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
+  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
+  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
+  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
+  
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __set_MSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))
+  #endif
+  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
+  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __set_PSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))
+  #endif
+
+  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
+  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
+  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
+  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
+  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
+  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
+  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
+  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
+  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
+  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
+  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
+  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
+  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
+  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+  #define __TZ_get_PSPLIM_NS()        (__arm_rsr("PSPLIM_NS"))
+  #define __TZ_set_PSPLIM_NS(VALUE)   (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
+  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+  #define __NOP     __iar_builtin_no_operation
+
+  #define __CLZ     __iar_builtin_CLZ
+  #define __CLREX   __iar_builtin_CLREX
+
+  #define __DMB     __iar_builtin_DMB
+  #define __DSB     __iar_builtin_DSB
+  #define __ISB     __iar_builtin_ISB
+
+  #define __LDREXB  __iar_builtin_LDREXB
+  #define __LDREXH  __iar_builtin_LDREXH
+  #define __LDREXW  __iar_builtin_LDREX
+
+  #define __RBIT    __iar_builtin_RBIT
+  #define __REV     __iar_builtin_REV
+  #define __REV16   __iar_builtin_REV16
+
+  __IAR_FT int16_t __REVSH(int16_t val)
+  {
+    return (int16_t) __iar_builtin_REVSH(val);
+  }
+
+  #define __ROR     __iar_builtin_ROR
+  #define __RRX     __iar_builtin_RRX
+
+  #define __SEV     __iar_builtin_SEV
+
+  #if !__IAR_M0_FAMILY
+    #define __SSAT    __iar_builtin_SSAT
+  #endif
+
+  #define __STREXB  __iar_builtin_STREXB
+  #define __STREXH  __iar_builtin_STREXH
+  #define __STREXW  __iar_builtin_STREX
+
+  #if !__IAR_M0_FAMILY
+    #define __USAT    __iar_builtin_USAT
+  #endif
+
+  #define __WFE     __iar_builtin_WFE
+  #define __WFI     __iar_builtin_WFI
+
+  #if __ARM_MEDIA__
+    #define __SADD8   __iar_builtin_SADD8
+    #define __QADD8   __iar_builtin_QADD8
+    #define __SHADD8  __iar_builtin_SHADD8
+    #define __UADD8   __iar_builtin_UADD8
+    #define __UQADD8  __iar_builtin_UQADD8
+    #define __UHADD8  __iar_builtin_UHADD8
+    #define __SSUB8   __iar_builtin_SSUB8
+    #define __QSUB8   __iar_builtin_QSUB8
+    #define __SHSUB8  __iar_builtin_SHSUB8
+    #define __USUB8   __iar_builtin_USUB8
+    #define __UQSUB8  __iar_builtin_UQSUB8
+    #define __UHSUB8  __iar_builtin_UHSUB8
+    #define __SADD16  __iar_builtin_SADD16
+    #define __QADD16  __iar_builtin_QADD16
+    #define __SHADD16 __iar_builtin_SHADD16
+    #define __UADD16  __iar_builtin_UADD16
+    #define __UQADD16 __iar_builtin_UQADD16
+    #define __UHADD16 __iar_builtin_UHADD16
+    #define __SSUB16  __iar_builtin_SSUB16
+    #define __QSUB16  __iar_builtin_QSUB16
+    #define __SHSUB16 __iar_builtin_SHSUB16
+    #define __USUB16  __iar_builtin_USUB16
+    #define __UQSUB16 __iar_builtin_UQSUB16
+    #define __UHSUB16 __iar_builtin_UHSUB16
+    #define __SASX    __iar_builtin_SASX
+    #define __QASX    __iar_builtin_QASX
+    #define __SHASX   __iar_builtin_SHASX
+    #define __UASX    __iar_builtin_UASX
+    #define __UQASX   __iar_builtin_UQASX
+    #define __UHASX   __iar_builtin_UHASX
+    #define __SSAX    __iar_builtin_SSAX
+    #define __QSAX    __iar_builtin_QSAX
+    #define __SHSAX   __iar_builtin_SHSAX
+    #define __USAX    __iar_builtin_USAX
+    #define __UQSAX   __iar_builtin_UQSAX
+    #define __UHSAX   __iar_builtin_UHSAX
+    #define __USAD8   __iar_builtin_USAD8
+    #define __USADA8  __iar_builtin_USADA8
+    #define __SSAT16  __iar_builtin_SSAT16
+    #define __USAT16  __iar_builtin_USAT16
+    #define __UXTB16  __iar_builtin_UXTB16
+    #define __UXTAB16 __iar_builtin_UXTAB16
+    #define __SXTB16  __iar_builtin_SXTB16
+    #define __SXTAB16 __iar_builtin_SXTAB16
+    #define __SMUAD   __iar_builtin_SMUAD
+    #define __SMUADX  __iar_builtin_SMUADX
+    #define __SMMLA   __iar_builtin_SMMLA
+    #define __SMLAD   __iar_builtin_SMLAD
+    #define __SMLADX  __iar_builtin_SMLADX
+    #define __SMLALD  __iar_builtin_SMLALD
+    #define __SMLALDX __iar_builtin_SMLALDX
+    #define __SMUSD   __iar_builtin_SMUSD
+    #define __SMUSDX  __iar_builtin_SMUSDX
+    #define __SMLSD   __iar_builtin_SMLSD
+    #define __SMLSDX  __iar_builtin_SMLSDX
+    #define __SMLSLD  __iar_builtin_SMLSLD
+    #define __SMLSLDX __iar_builtin_SMLSLDX
+    #define __SEL     __iar_builtin_SEL
+    #define __QADD    __iar_builtin_QADD
+    #define __QSUB    __iar_builtin_QSUB
+    #define __PKHBT   __iar_builtin_PKHBT
+    #define __PKHTB   __iar_builtin_PKHTB
+  #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #define __CLZ  __cmsis_iar_clz_not_active
+    #define __SSAT __cmsis_iar_ssat_not_active
+    #define __USAT __cmsis_iar_usat_not_active
+    #define __RBIT __cmsis_iar_rbit_not_active
+    #define __get_APSR  __cmsis_iar_get_APSR_not_active
+  #endif
+
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+  #endif
+
+  #ifdef __INTRINSICS_INCLUDED
+  #error intrinsics.h is already included previously!
+  #endif
+
+  #include <intrinsics.h>
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #undef __CLZ
+    #undef __SSAT
+    #undef __USAT
+    #undef __RBIT
+    #undef __get_APSR
+
+    __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+    {
+      if (data == 0U) { return 32U; }
+
+      uint32_t count = 0U;
+      uint32_t mask = 0x80000000U;
+
+      while ((data & mask) == 0U)
+      {
+        count += 1U;
+        mask = mask >> 1U;
+      }
+      return count;
+    }
+
+    __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+    {
+      uint8_t sc = 31U;
+      uint32_t r = v;
+      for (v >>= 1U; v; v >>= 1U)
+      {
+        r <<= 1U;
+        r |= v & 1U;
+        sc--;
+      }
+      return (r << sc);
+    }
+
+    __STATIC_INLINE  uint32_t __get_APSR(void)
+    {
+      uint32_t res;
+      __asm("MRS      %0,APSR" : "=r" (res));
+      return res;
+    }
+
+  #endif
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #undef __get_FPSCR
+    #undef __set_FPSCR
+    #define __get_FPSCR()       (0)
+    #define __set_FPSCR(VALUE)  ((void)VALUE)
+  #endif
+
+  #pragma diag_suppress=Pe940
+  #pragma diag_suppress=Pe177
+
+  #define __enable_irq    __enable_interrupt
+  #define __disable_irq   __disable_interrupt
+  #define __NOP           __no_operation
+
+  #define __get_xPSR      __get_PSR
+
+  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+    {
+      return __LDREX((unsigned long *)ptr);
+    }
+
+    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+    {
+      return __STREX(value, (unsigned long *)ptr);
+    }
+  #endif
+
+
+  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+  #if (__CORTEX_M >= 0x03)
+
+    __IAR_FT uint32_t __RRX(uint32_t value)
+    {
+      uint32_t result;
+      __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
+      return(result);
+    }
+
+    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));
+    }
+
+
+    #define __enable_fault_irq  __enable_fiq
+    #define __disable_fault_irq __disable_fiq
+
+
+  #endif /* (__CORTEX_M >= 0x03) */
+
+  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+  {
+    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+  }
+
+  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+   __IAR_FT uint32_t __get_MSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_MSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __get_PSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_PSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
+    {
+      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_SP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,SP_NS" : "=r" (res));
+      return res;
+    }
+    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      SP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+      return res;
+    }
+    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));
+    }
+
+  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+  {
+    if ((sat >= 1U) && (sat <= 32U))
+    {
+      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+      const int32_t min = -1 - max ;
+      if (val > max)
+      {
+        return max;
+      }
+      else if (val < min)
+      {
+        return min;
+      }
+    }
+    return val;
+  }
+
+  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+  {
+    if (sat <= 31U)
+    {
+      const uint32_t max = ((1U << sat) - 1U);
+      if (val > (int32_t)max)
+      {
+        return max;
+      }
+      else if (val < 0)
+      {
+        return 0U;
+      }
+    }
+    return (uint32_t)val;
+  }
+#endif
+
+#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+  {
+    __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+  {
+    __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+  {
+    __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+  }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+
+  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+  {
+    __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+  {
+    __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+  {
+    __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+    return res;
+  }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */

platform/CMSIS/Core/Include/cmsis_version.h

@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

platform/CMSIS/Core/Include/core_cm4.h

@@ -0,0 +1,2115 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V5.0.3
+ * @date     09. August 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M4
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM4_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000U
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

platform/CMSIS/Core/Include/mpu_armv7.h

@@ -0,0 +1,204 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for ARMv7 MPU
+ * @version  V5.0.3
+ * @date     09. August 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U)
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U)
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U)
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U)
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U)
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U)
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU)
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU)
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU)
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU)
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU)
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU)
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U)
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U)
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U)
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U)
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U)
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U)
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U)
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U)
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U)
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U)
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU)
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU)
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU)
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU)
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU)
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU)
+
+#define ARM_MPU_AP_NONE 0U
+#define ARM_MPU_AP_PRIV 1U
+#define ARM_MPU_AP_URO  2U
+#define ARM_MPU_AP_FULL 3U
+#define ARM_MPU_AP_PRO  5U
+#define ARM_MPU_AP_RO   6U
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Region Attribut and Size Register Value
+*
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ((((DisableExec     ) << MPU_RASR_XN_Pos)     & MPU_RASR_XN_Msk)     | \
+   (((AccessPermission) << MPU_RASR_AP_Pos)     & MPU_RASR_AP_Msk)     | \
+   (((TypeExtField    ) << MPU_RASR_TEX_Pos)    & MPU_RASR_TEX_Msk)    | \
+   (((IsShareable     ) << MPU_RASR_S_Pos)      & MPU_RASR_S_Msk)      | \
+   (((IsCacheable     ) << MPU_RASR_C_Pos)      & MPU_RASR_C_Msk)      | \
+   (((IsBufferable    ) << MPU_RASR_B_Pos)      & MPU_RASR_B_Msk)      | \
+   (((SubRegionDisable) << MPU_RASR_SRD_Pos)    & MPU_RASR_SRD_Msk)    | \
+   (((Size            ) << MPU_RASR_SIZE_Pos)   & MPU_RASR_SIZE_Msk)   | \
+   (MPU_RASR_ENABLE_Msk))
+
+
+/**
+* Struct for a single MPU Region
+*/
+#if defined (__CMCPPARM__)
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+#else
+typedef struct _ARM_MPU_Region_t {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+#endif
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i)
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif

platform/Device/NIIET/K1921VK035/Include/system_K1921VK035.h

@@ -0,0 +1,52 @@
+/*==============================================================================
+ * Инициализация К1921ВК035
+ *------------------------------------------------------------------------------
+ * НИИЭТ, Богдан Колбов <kolbov@niiet.ru>
+ *==============================================================================
+ * ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ ПРЕДОСТАВЛЯЕТСЯ «КАК ЕСТЬ», БЕЗ КАКИХ-ЛИБО
+ * ГАРАНТИЙ, ЯВНО ВЫРАЖЕННЫХ ИЛИ ПОДРАЗУМЕВАЕМЫХ, ВКЛЮЧАЯ ГАРАНТИИ ТОВАРНОЙ
+ * ПРИГОДНОСТИ, СООТВЕТСТВИЯ ПО ЕГО КОНКРЕТНОМУ НАЗНАЧЕНИЮ И ОТСУТСТВИЯ
+ * НАРУШЕНИЙ, НО НЕ ОГРАНИЧИВАЯСЬ ИМИ. ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ
+ * ПРЕДНАЗНАЧЕНО ДЛЯ ОЗНАКОМИТЕЛЬНЫХ ЦЕЛЕЙ И НАПРАВЛЕНО ТОЛЬКО НА
+ * ПРЕДОСТАВЛЕНИЕ ДОПОЛНИТЕЛЬНОЙ ИНФОРМАЦИИ О ПРОДУКТЕ, С ЦЕЛЬЮ СОХРАНИТЬ ВРЕМЯ
+ * ПОТРЕБИТЕЛЮ. НИ В КАКОМ СЛУЧАЕ АВТОРЫ ИЛИ ПРАВООБЛАДАТЕЛИ НЕ НЕСУТ
+ * ОТВЕТСТВЕННОСТИ ПО КАКИМ-ЛИБО ИСКАМ, ЗА ПРЯМОЙ ИЛИ КОСВЕННЫЙ УЩЕРБ, ИЛИ
+ * ПО ИНЫМ ТРЕБОВАНИЯМ, ВОЗНИКШИМ ИЗ-ЗА ИСПОЛЬЗОВАНИЯ ПРОГРАММНОГО ОБЕСПЕЧЕНИЯ
+ * ИЛИ ИНЫХ ДЕЙСТВИЙ С ПРОГРАММНЫМ ОБЕСПЕЧЕНИЕМ.
+ *
+ *                              2018 АО "НИИЭТ"
+ *==============================================================================
+ */
+
+#ifndef SYSTEM_K1921VK035_H
+#define SYSTEM_K1921VK035_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//-- Includes ------------------------------------------------------------------
+#include <stdint.h>
+
+//-- Defines -------------------------------------------------------------------
+#define OSICLK_VAL 8000000
+#ifndef OSECLK_VAL 
+#define OSECLK_VAL 0
+#endif
+#define OSECLK_STARTUP_TIMEOUT 0x100000
+#define SYSCLK_SWITCH_TIMEOUT 0x100000
+
+//-- Variables -----------------------------------------------------------------
+extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock)
+extern uint32_t uwTick;
+//-- Functions -----------------------------------------------------------------
+// Initialize the System
+extern void SystemInit(void);
+// Updates the SystemCoreClock with current core Clock retrieved from registers
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // SYSTEM_K1921VK035_H

platform/Device/NIIET/K1921VK035/Source/ARM/startup_K1921VK035.s

@@ -0,0 +1,393 @@
+;******************** (C) COPYRIGHT 2018 NIIET ********************
+;* File Name          : startup_K1921VK035.s
+;* Author             : NIIET 
+;* Version            : V1.7
+;* Date               : 02.05.2018
+;* Description        : K1921VK035 vector table for MDK-ARM 
+;*                      toolchain.  
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Configure the clock system
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, NIIET SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+				DCD     WDT_IRQHandler ; Watchdog timer interrupt
+				DCD     RCU_IRQHandler ; Reset and clock unit interrupt
+				DCD     MFLASH_IRQHandler ; MFLASH interrupt
+				DCD     GPIOA_IRQHandler ; GPIO A interrupt
+				DCD     GPIOB_IRQHandler ; GPIO B interrupt
+				DCD     DMA_CH0_IRQHandler ; DMA channel 0 interrupt
+				DCD     DMA_CH1_IRQHandler ; DMA channel 1 interrupt
+				DCD     DMA_CH2_IRQHandler ; DMA channel 2 interrupt
+				DCD     DMA_CH3_IRQHandler ; DMA channel 3 interrupt
+				DCD     DMA_CH4_IRQHandler ; DMA channel 4 interrupt
+				DCD     DMA_CH5_IRQHandler ; DMA channel 5 interrupt
+				DCD     DMA_CH6_IRQHandler ; DMA channel 6 interrupt
+				DCD     DMA_CH7_IRQHandler ; DMA channel 7 interrupt
+				DCD     DMA_CH8_IRQHandler ; DMA channel 8 interrupt
+				DCD     DMA_CH9_IRQHandler ; DMA channel 9 interrupt
+				DCD     DMA_CH10_IRQHandler ; DMA channel 10 interrupt
+				DCD     DMA_CH11_IRQHandler ; DMA channel 11 interrupt
+				DCD     DMA_CH12_IRQHandler ; DMA channel 12 interrupt
+				DCD     DMA_CH13_IRQHandler ; DMA channel 13 interrupt
+				DCD     DMA_CH14_IRQHandler ; DMA channel 14 interrupt
+				DCD     DMA_CH15_IRQHandler ; DMA channel 15 interrupt
+				DCD     TMR0_IRQHandler ; Timer 0 interrupt
+				DCD     TMR1_IRQHandler ; Timer 1 interrupt
+				DCD     TMR2_IRQHandler ; Timer 2 interrupt
+				DCD     TMR3_IRQHandler ; Timer 3 interrupt
+				DCD     UART0_TD_IRQHandler ; UART0 Transmit Done interrupt
+				DCD     UART0_RX_IRQHandler ; UART0 Recieve interrupt
+				DCD     UART0_TX_IRQHandler ; UART0 Transmit interrupt
+				DCD     UART0_E_RT_IRQHandler ; UART0 Error and Receive Timeout interrupt
+				DCD     UART1_TD_IRQHandler ; UART1 Transmit Done interrupt
+				DCD     UART1_RX_IRQHandler ; UART1 Recieve interrupt
+				DCD     UART1_TX_IRQHandler ; UART1 Transmit interrupt
+				DCD     UART1_E_RT_IRQHandler ; UART1 Error and Receive Timeout interrupt
+				DCD     SPI_RO_RT_IRQHandler ; SPI RX FIFO overrun and Receive Timeout interrupt
+				DCD     SPI_RX_IRQHandler ; SPI Receive interrupt
+				DCD     SPI_TX_IRQHandler ; SPI Transmit interrupt
+				DCD     I2C_IRQHandler ; I2C interrupt
+				DCD     ECAP0_IRQHandler ; ECAP0 interrupt
+				DCD     ECAP1_IRQHandler ; ECAP1 interrupt
+				DCD     ECAP2_IRQHandler ; ECAP2 interrupt
+				DCD     PWM0_IRQHandler ; PWM0 interrupt
+				DCD     PWM0_HD_IRQHandler ; PWM0 HD interrupt
+				DCD     PWM0_TZ_IRQHandler ; PWM0 TZ interrupt
+				DCD     PWM1_IRQHandler ; PWM1 interrupt
+				DCD     PWM1_HD_IRQHandler ; PWM1 HD interrupt
+				DCD     PWM1_TZ_IRQHandler ; PWM1 TZ interrupt
+				DCD     PWM2_IRQHandler ; PWM2 interrupt
+				DCD     PWM2_HD_IRQHandler ; PWM2 HD interrupt
+				DCD     PWM2_TZ_IRQHandler ; PWM2 TZ interrupt
+				DCD     QEP_IRQHandler ; QEP interrupt
+				DCD     ADC_SEQ0_IRQHandler ; ADC Sequencer 0 interrupt
+				DCD     ADC_SEQ1_IRQHandler ; ADC Sequencer 1 interrupt
+				DCD     ADC_DC_IRQHandler ; ADC Digital Comparator interrupt
+				DCD     CAN0_IRQHandler ; CAN0 interrupt
+				DCD     CAN1_IRQHandler ; CAN1 interrupt
+				DCD     CAN2_IRQHandler ; CAN2 interrupt
+				DCD     CAN3_IRQHandler ; CAN3 interrupt
+				DCD     CAN4_IRQHandler ; CAN4 interrupt
+				DCD     CAN5_IRQHandler ; CAN5 interrupt
+				DCD     CAN6_IRQHandler ; CAN6 interrupt
+				DCD     CAN7_IRQHandler ; CAN7 interrupt
+				DCD     CAN8_IRQHandler ; CAN8 interrupt
+				DCD     CAN9_IRQHandler ; CAN9 interrupt
+				DCD     CAN10_IRQHandler ; CAN10 interrupt
+				DCD     CAN11_IRQHandler ; CAN11 interrupt
+				DCD     CAN12_IRQHandler ; CAN12 interrupt
+				DCD     CAN13_IRQHandler ; CAN13 interrupt
+				DCD     CAN14_IRQHandler ; CAN14 interrupt
+				DCD     CAN15_IRQHandler ; CAN15 interrupt
+				DCD     FPU_IRQHandler ; FPU exception interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+     IMPORT  __main
+     IMPORT  SystemInit
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT     WDT_IRQHandler           [WEAK]
+                EXPORT     RCU_IRQHandler           [WEAK]
+                EXPORT     MFLASH_IRQHandler           [WEAK]
+                EXPORT     GPIOA_IRQHandler           [WEAK]
+                EXPORT     GPIOB_IRQHandler           [WEAK]
+                EXPORT     DMA_CH0_IRQHandler           [WEAK]
+                EXPORT     DMA_CH1_IRQHandler           [WEAK]
+                EXPORT     DMA_CH2_IRQHandler           [WEAK]
+                EXPORT     DMA_CH3_IRQHandler           [WEAK]
+                EXPORT     DMA_CH4_IRQHandler           [WEAK]
+                EXPORT     DMA_CH5_IRQHandler           [WEAK]
+                EXPORT     DMA_CH6_IRQHandler           [WEAK]
+                EXPORT     DMA_CH7_IRQHandler           [WEAK]
+                EXPORT     DMA_CH8_IRQHandler           [WEAK]
+                EXPORT     DMA_CH9_IRQHandler           [WEAK]
+                EXPORT     DMA_CH10_IRQHandler           [WEAK]
+                EXPORT     DMA_CH11_IRQHandler           [WEAK]
+                EXPORT     DMA_CH12_IRQHandler           [WEAK]
+                EXPORT     DMA_CH13_IRQHandler           [WEAK]
+                EXPORT     DMA_CH14_IRQHandler           [WEAK]
+                EXPORT     DMA_CH15_IRQHandler           [WEAK]
+                EXPORT     TMR0_IRQHandler           [WEAK]
+                EXPORT     TMR1_IRQHandler           [WEAK]
+                EXPORT     TMR2_IRQHandler           [WEAK]
+                EXPORT     TMR3_IRQHandler           [WEAK]
+                EXPORT     UART0_TD_IRQHandler           [WEAK]
+                EXPORT     UART0_RX_IRQHandler           [WEAK]
+                EXPORT     UART0_TX_IRQHandler           [WEAK]
+                EXPORT     UART0_E_RT_IRQHandler           [WEAK]
+                EXPORT     UART1_TD_IRQHandler           [WEAK]
+                EXPORT     UART1_RX_IRQHandler           [WEAK]
+                EXPORT     UART1_TX_IRQHandler           [WEAK]
+                EXPORT     UART1_E_RT_IRQHandler           [WEAK]
+                EXPORT     SPI_RO_RT_IRQHandler           [WEAK]
+                EXPORT     SPI_RX_IRQHandler           [WEAK]
+                EXPORT     SPI_TX_IRQHandler           [WEAK]
+                EXPORT     I2C_IRQHandler           [WEAK]
+                EXPORT     ECAP0_IRQHandler           [WEAK]
+                EXPORT     ECAP1_IRQHandler           [WEAK]
+                EXPORT     ECAP2_IRQHandler           [WEAK]
+                EXPORT     PWM0_IRQHandler           [WEAK]
+                EXPORT     PWM0_HD_IRQHandler           [WEAK]
+                EXPORT     PWM0_TZ_IRQHandler           [WEAK]
+                EXPORT     PWM1_IRQHandler           [WEAK]
+                EXPORT     PWM1_HD_IRQHandler           [WEAK]
+                EXPORT     PWM1_TZ_IRQHandler           [WEAK]
+                EXPORT     PWM2_IRQHandler           [WEAK]
+                EXPORT     PWM2_HD_IRQHandler           [WEAK]
+                EXPORT     PWM2_TZ_IRQHandler           [WEAK]
+                EXPORT     QEP_IRQHandler           [WEAK]
+                EXPORT     ADC_SEQ0_IRQHandler           [WEAK]
+                EXPORT     ADC_SEQ1_IRQHandler           [WEAK]
+                EXPORT     ADC_DC_IRQHandler           [WEAK]
+                EXPORT     CAN0_IRQHandler           [WEAK]
+                EXPORT     CAN1_IRQHandler           [WEAK]
+                EXPORT     CAN2_IRQHandler           [WEAK]
+                EXPORT     CAN3_IRQHandler           [WEAK]
+                EXPORT     CAN4_IRQHandler           [WEAK]
+                EXPORT     CAN5_IRQHandler           [WEAK]
+                EXPORT     CAN6_IRQHandler           [WEAK]
+                EXPORT     CAN7_IRQHandler           [WEAK]
+                EXPORT     CAN8_IRQHandler           [WEAK]
+                EXPORT     CAN9_IRQHandler           [WEAK]
+                EXPORT     CAN10_IRQHandler           [WEAK]
+                EXPORT     CAN11_IRQHandler           [WEAK]
+                EXPORT     CAN12_IRQHandler           [WEAK]
+                EXPORT     CAN13_IRQHandler           [WEAK]
+                EXPORT     CAN14_IRQHandler           [WEAK]
+                EXPORT     CAN15_IRQHandler           [WEAK]
+                EXPORT     FPU_IRQHandler           [WEAK]
+
+
+
+WDT_IRQHandler         
+RCU_IRQHandler         
+MFLASH_IRQHandler         
+GPIOA_IRQHandler         
+GPIOB_IRQHandler         
+DMA_CH0_IRQHandler         
+DMA_CH1_IRQHandler         
+DMA_CH2_IRQHandler         
+DMA_CH3_IRQHandler         
+DMA_CH4_IRQHandler         
+DMA_CH5_IRQHandler         
+DMA_CH6_IRQHandler         
+DMA_CH7_IRQHandler         
+DMA_CH8_IRQHandler         
+DMA_CH9_IRQHandler         
+DMA_CH10_IRQHandler         
+DMA_CH11_IRQHandler         
+DMA_CH12_IRQHandler         
+DMA_CH13_IRQHandler         
+DMA_CH14_IRQHandler         
+DMA_CH15_IRQHandler         
+TMR0_IRQHandler         
+TMR1_IRQHandler         
+TMR2_IRQHandler         
+TMR3_IRQHandler         
+UART0_TD_IRQHandler         
+UART0_RX_IRQHandler         
+UART0_TX_IRQHandler         
+UART0_E_RT_IRQHandler         
+UART1_TD_IRQHandler         
+UART1_RX_IRQHandler         
+UART1_TX_IRQHandler         
+UART1_E_RT_IRQHandler         
+SPI_RO_RT_IRQHandler         
+SPI_RX_IRQHandler         
+SPI_TX_IRQHandler         
+I2C_IRQHandler         
+ECAP0_IRQHandler         
+ECAP1_IRQHandler         
+ECAP2_IRQHandler         
+PWM0_IRQHandler         
+PWM0_HD_IRQHandler         
+PWM0_TZ_IRQHandler         
+PWM1_IRQHandler         
+PWM1_HD_IRQHandler         
+PWM1_TZ_IRQHandler         
+PWM2_IRQHandler         
+PWM2_HD_IRQHandler         
+PWM2_TZ_IRQHandler         
+QEP_IRQHandler         
+ADC_SEQ0_IRQHandler         
+ADC_SEQ1_IRQHandler         
+ADC_DC_IRQHandler         
+CAN0_IRQHandler         
+CAN1_IRQHandler         
+CAN2_IRQHandler         
+CAN3_IRQHandler         
+CAN4_IRQHandler         
+CAN5_IRQHandler         
+CAN6_IRQHandler         
+CAN7_IRQHandler         
+CAN8_IRQHandler         
+CAN9_IRQHandler         
+CAN10_IRQHandler         
+CAN11_IRQHandler         
+CAN12_IRQHandler         
+CAN13_IRQHandler         
+CAN14_IRQHandler         
+CAN15_IRQHandler         
+FPU_IRQHandler         
+
+
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB           
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;******************* (C) COPYRIGHT 2018 NIIET *****END OF FILE*****

platform/Device/NIIET/K1921VK035/Source/system_K1921VK035.c

@@ -0,0 +1,167 @@
+/*==============================================================================
+ * Инициализация К1921ВК035
+ *------------------------------------------------------------------------------
+ * НИИЭТ, Богдан Колбов <kolbov@niiet.ru>
+ *==============================================================================
+ * ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ ПРЕДОСТАВЛЯЕТСЯ «КАК ЕСТЬ», БЕЗ КАКИХ-ЛИБО
+ * ГАРАНТИЙ, ЯВНО ВЫРАЖЕННЫХ ИЛИ ПОДРАЗУМЕВАЕМЫХ, ВКЛЮЧАЯ ГАРАНТИИ ТОВАРНОЙ
+ * ПРИГОДНОСТИ, СООТВЕТСТВИЯ ПО ЕГО КОНКРЕТНОМУ НАЗНАЧЕНИЮ И ОТСУТСТВИЯ
+ * НАРУШЕНИЙ, НО НЕ ОГРАНИЧИВАЯСЬ ИМИ. ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ
+ * ПРЕДНАЗНАЧЕНО ДЛЯ ОЗНАКОМИТЕЛЬНЫХ ЦЕЛЕЙ И НАПРАВЛЕНО ТОЛЬКО НА
+ * ПРЕДОСТАВЛЕНИЕ ДОПОЛНИТЕЛЬНОЙ ИНФОРМАЦИИ О ПРОДУКТЕ, С ЦЕЛЬЮ СОХРАНИТЬ ВРЕМЯ
+ * ПОТРЕБИТЕЛЮ. НИ В КАКОМ СЛУЧАЕ АВТОРЫ ИЛИ ПРАВООБЛАДАТЕЛИ НЕ НЕСУТ
+ * ОТВЕТСТВЕННОСТИ ПО КАКИМ-ЛИБО ИСКАМ, ЗА ПРЯМОЙ ИЛИ КОСВЕННЫЙ УЩЕРБ, ИЛИ
+ * ПО ИНЫМ ТРЕБОВАНИЯМ, ВОЗНИКШИМ ИЗ-ЗА ИСПОЛЬЗОВАНИЯ ПРОГРАММНОГО ОБЕСПЕЧЕНИЯ
+ * ИЛИ ИНЫХ ДЕЙСТВИЙ С ПРОГРАММНЫМ ОБЕСПЕЧЕНИЕМ.
+ *
+ *                              2018 АО "НИИЭТ"
+ *==============================================================================
+ */
+
+//-- Includes ------------------------------------------------------------------
+#include "system_K1921VK035.h"
+#include "K1921VK035.h"
+
+//-- Variables -----------------------------------------------------------------
+uint32_t SystemCoreClock; // System Clock Frequency (Core Clock)
+uint32_t uwTick; // Milliseconds ticks
+
+//-- Functions -----------------------------------------------------------------
+void SystemCoreClockUpdate(void)
+{
+    uint32_t current_sysclk;
+    uint32_t pll_n, pll_m, pll_od, pll_refclk, pll_div = 1;
+
+    current_sysclk = RCU->SYSCLKSTAT_bit.SYSSTAT;
+
+    switch (current_sysclk) {
+    case RCU_SYSCLKSTAT_SYSSTAT_OSICLK:
+        SystemCoreClock = OSICLK_VAL;
+        break;
+    case RCU_SYSCLKSTAT_SYSSTAT_OSECLK:
+        SystemCoreClock = OSECLK_VAL;
+        break;
+    case RCU_SYSCLKSTAT_SYSSTAT_PLLDIVCLK:
+    case RCU_SYSCLKSTAT_SYSSTAT_PLLCLK:
+        if (current_sysclk == RCU_SYSCLKSTAT_SYSSTAT_PLLDIVCLK)
+            pll_div = RCU->PLLDIV_bit.DIV + 1;
+        pll_n = RCU->PLLCFG_bit.N;
+        pll_m = RCU->PLLCFG_bit.M;
+        pll_od = RCU->PLLCFG_bit.OD;
+        if (RCU->PLLCFG_bit.REFSRC == RCU_PLLCFG_REFSRC_OSICLK)
+            pll_refclk = OSICLK_VAL;
+        else // RCU->PLLCFG_bit.REFSRC == RCU_PLLCFG_REFSRC_OSECLK
+            pll_refclk = OSECLK_VAL;
+        SystemCoreClock = (pll_refclk * pll_m) / (pll_n * (1 << pll_od) * pll_div);
+        break;
+    }
+}
+
+void ClkInit()
+{
+    uint32_t timeout_counter = 0;
+    uint32_t sysclk_source;
+
+//clockout control
+#if defined CKO_OSI
+    SIU->CLKOUTCTL = SIU_CLKOUTCTL_CLKOUTEN_Msk;
+    RCU->CLKOUTCFG = (RCU_CLKOUTCFG_CLKSEL_OSICLK << RCU_CLKOUTCFG_CLKSEL_Pos) |
+                     (RCU_CLKOUTCFG_CLKEN_Msk); //CKO = OSICLK
+#elif defined CKO_OSE && (OSECLK_VAL != 0)
+    SIU->CLKOUTCTL = SIU_CLKOUTCTL_CLKOUTEN_Msk;
+    RCU->CLKOUTCFG = (RCU_CLKOUTCFG_CLKSEL_OSECLK << RCU_CLKOUTCFG_CLKSEL_Pos) |
+                     (RCU_CLKOUTCFG_CLKEN_Msk); //CKO = OSECLK
+#elif defined CKO_PLL
+    SIU->CLKOUTCTL = SIU_CLKOUTCTL_CLKOUTEN_Msk;
+    RCU->CLKOUTCFG = (RCU_CLKOUTCFG_CLKSEL_PLLCLK << RCU_CLKOUTCFG_CLKSEL_Pos) |
+                     (1 << RCU_CLKOUTCFG_DIVN_Pos) |
+                     (RCU_CLKOUTCFG_DIVEN_Msk) |
+                     (RCU_CLKOUTCFG_CLKEN_Msk); //CKO = PLLCLK/4
+#endif
+
+//wait till external oscillator is ready
+#if defined OSECLK_VAL && (OSECLK_VAL != 0)
+    while ((!RCU->SYSCLKSTAT_bit.OSECLKOK) && (timeout_counter < OSECLK_STARTUP_TIMEOUT))
+        timeout_counter++;
+    if (timeout_counter == OSECLK_STARTUP_TIMEOUT) //OSE failed to startup
+        while (1) {
+        };
+#endif
+
+//select system clock
+#ifdef SYSCLK_PLL
+//PLLCLK = REFSRC * (M/N) * (1/(2^OD))
+#if (OSECLK_VAL == 8000000)
+    RCU->PLLCFG = (RCU_PLLCFG_REFSRC_OSECLK << RCU_PLLCFG_REFSRC_Pos) |
+                  (1 << RCU_PLLCFG_N_Pos) |
+                  (25 << RCU_PLLCFG_M_Pos);
+#elif (OSECLK_VAL == 12000000)
+    RCU->PLLCFG = (RCU_PLLCFG_REFSRC_OSECLK << RCU_PLLCFG_REFSRC_Pos) |
+                  (3 << RCU_PLLCFG_N_Pos) |
+                  (50 << RCU_PLLCFG_M_Pos);
+#elif (OSECLK_VAL == 16000000)
+    RCU->PLLCFG = (RCU_PLLCFG_REFSRC_OSECLK << RCU_PLLCFG_REFSRC_Pos) |
+                  (2 << RCU_PLLCFG_N_Pos) |
+                  (25 << RCU_PLLCFG_M_Pos);
+#elif (OSECLK_VAL == 20000000)
+    RCU->PLLCFG = (RCU_PLLCFG_REFSRC_OSECLK << RCU_PLLCFG_REFSRC_Pos) |
+                  (2 << RCU_PLLCFG_N_Pos) |
+                  (20 << RCU_PLLCFG_M_Pos);
+#elif (OSECLK_VAL == 24000000)
+    RCU->PLLCFG = (RCU_PLLCFG_REFSRC_OSECLK << RCU_PLLCFG_REFSRC_Pos) |
+                  (3 << RCU_PLLCFG_N_Pos) |
+                  (25 << RCU_PLLCFG_M_Pos);
+#elif defined OSICLK_VAL
+    RCU->PLLCFG = (RCU_PLLCFG_REFSRC_OSICLK << RCU_PLLCFG_REFSRC_Pos) |
+                  (1 << RCU_PLLCFG_N_Pos) |
+                  (25 << RCU_PLLCFG_M_Pos);
+#else
+#error "Please define OSICLK_VAL and OSECLK_VAL with correct values!"
+#endif
+    RCU->PLLCFG |= (1 << RCU_PLLCFG_OD_Pos) |
+                   (RCU_PLLCFG_OUTEN_Msk);
+    while (!RCU->PLLCFG_bit.LOCK) {
+    };
+    // additional waitstates
+    MFLASH->CTRL = (3 << MFLASH_CTRL_LAT_Pos);
+    //select PLL as source system clock
+    sysclk_source = RCU_SYSCLKCFG_SYSSEL_PLLCLK;
+#elif defined SYSCLK_OSI
+    sysclk_source = RCU_SYSCLKCFG_SYSSEL_OSICLK;
+#elif defined SYSCLK_OSE
+    sysclk_source = RCU_SYSCLKCFG_SYSSEL_OSECLK;
+#else
+#error "Please define SYSCLK source (SYSCLK_PLL | SYSCLK_OSI | SYSCLK_OSE)!"
+#endif
+
+    //switch sysclk
+    RCU->SYSCLKCFG = (sysclk_source << RCU_SYSCLKCFG_SYSSEL_Pos);
+    // Wait switching done
+    timeout_counter = 0;
+    while ((RCU->SYSCLKSTAT_bit.SYSSTAT != RCU->SYSCLKCFG_bit.SYSSEL) && (timeout_counter < SYSCLK_SWITCH_TIMEOUT))
+        timeout_counter++;
+    if (timeout_counter == SYSCLK_SWITCH_TIMEOUT) //SYSCLK failed to switch
+        while (1) {
+        };
+
+    //flush and enable cache
+    MFLASH->CTRL_bit.IFLUSH = 1;
+    while (MFLASH->ICSTAT_bit.BUSY) {
+    };
+    MFLASH->CTRL_bit.DFLUSH = 1;
+    while (MFLASH->DCSTAT_bit.BUSY) {
+    };
+    MFLASH->CTRL |= (MFLASH_CTRL_DCEN_Msk) | (MFLASH_CTRL_ICEN_Msk) | (MFLASH_CTRL_PEN_Msk);
+}
+
+void FPUInit()
+{
+    SCB->CPACR = 0x00F00000;
+    __DSB();
+    __ISB();
+}
+void SystemInit(void)
+{
+    ClkInit();
+    FPUInit();
+}

platform/plib035/inc/plib035.h

@@ -0,0 +1,145 @@
+/**
+  ******************************************************************************
+  * @file    plib035.h
+  *
+  * @brief   Низкоуровневая библиотека периферии для микроконтроллера НИИЭТ К1921ВК035
+  *          Этот файл содержит:
+  *           - Главный заголовочный файл целевого устройства, с описанием всех регистров его периферии
+  *           - Область настройки драйвера
+  *           - Макросы для доступа к регистрам периферии
+  *
+  * @author  НИИЭТ, Богдан Колбов <kolbov@niiet.ru>
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ ПРЕДОСТАВЛЯЕТСЯ «КАК ЕСТЬ», БЕЗ КАКИХ-ЛИБО
+  * ГАРАНТИЙ, ЯВНО ВЫРАЖЕННЫХ ИЛИ ПОДРАЗУМЕВАЕМЫХ, ВКЛЮЧАЯ ГАРАНТИИ ТОВАРНОЙ
+  * ПРИГОДНОСТИ, СООТВЕТСТВИЯ ПО ЕГО КОНКРЕТНОМУ НАЗНАЧЕНИЮ И ОТСУТСТВИЯ
+  * НАРУШЕНИЙ, НО НЕ ОГРАНИЧИВАЯСЬ ИМИ. ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ
+  * ПРЕДНАЗНАЧЕНО ДЛЯ ОЗНАКОМИТЕЛЬНЫХ ЦЕЛЕЙ И НАПРАВЛЕНО ТОЛЬКО НА
+  * ПРЕДОСТАВЛЕНИЕ ДОПОЛНИТЕЛЬНОЙ ИНФОРМАЦИИ О ПРОДУКТЕ, С ЦЕЛЬЮ СОХРАНИТЬ ВРЕМЯ
+  * ПОТРЕБИТЕЛЮ. НИ В КАКОМ СЛУЧАЕ АВТОРЫ ИЛИ ПРАВООБЛАДАТЕЛИ НЕ НЕСУТ
+  * ОТВЕТСТВЕННОСТИ ПО КАКИМ-ЛИБО ИСКАМ, ЗА ПРЯМОЙ ИЛИ КОСВЕННЫЙ УЩЕРБ, ИЛИ
+  * ПО ИНЫМ ТРЕБОВАНИЯМ, ВОЗНИКШИМ ИЗ-ЗА ИСПОЛЬЗОВАНИЯ ПРОГРАММНОГО ОБЕСПЕЧЕНИЯ
+  * ИЛИ ИНЫХ ДЕЙСТВИЙ С ПРОГРАММНЫМ ОБЕСПЕЧЕНИЕМ.
+  *
+  * <h2><center>&copy; 2018 ОАО "НИИЭТ"</center></h2>
+  ******************************************************************************
+  */
+
+/** @addtogroup PLib035 Библиотека периферии
+  * @{
+  */
+
+#ifndef __PLIB035_H
+#define __PLIB035_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "K1921VK035.h"
+
+/** @addtogroup Exported_macro Макросы
+  * @{
+  */
+
+#if defined(__ICCARM__)
+#define __RAMFUNC __ramfunc
+#elif defined(__CMCARM__)
+#define __RAMFUNC __ramfunc
+#elif defined(__CC_ARM)
+#define __RAMFUNC
+#elif defined(__GNUC__)
+#define __RAMFUNC __attribute__((long_call, section(".ramfunc")))
+#else
+#error "plib035.h: RAMFUNC - нет реализации под данный компилятор!"
+#endif
+
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) (((REG) & (BIT)) ? (0x1) : (0x0))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_Types Типы
+  * @{
+  */
+
+/**
+  * @brief Описывает логическое состояние периферии.
+  * Используется для операций включения/выключения периферийных блоков или их функций.
+  */
+typedef enum {
+    DISABLE = 0UL,
+    ENABLE = 1UL
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(VALUE) (((VALUE) == DISABLE) || ((VALUE) == ENABLE))
+
+/**
+  * @brief Описывает коды возврата при выполнении какой-либо операции
+  */
+typedef enum {
+    OK = 0UL,
+    ERROR = 1UL
+} OperationStatus;
+
+/**
+  * @brief Описывает возможные состояния флага или бита
+  */
+typedef enum {
+    CLEAR = 0UL,
+    SET = 1UL
+} FlagStatus,
+    BitState;
+#define IS_BIT_STATE(VALUE) (((VALUE) == CLEAR) || ((VALUE) == SET))
+
+/**
+  * @}
+  */
+
+/** @defgroup Misc Дополнительные модули
+  * @{
+  */
+
+#include "plib035_assert.h"
+#include "plib035_version.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral Периферия
+  * @{
+  */
+
+#include "plib035_conf.h"
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PLIB035_H */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2018 NIIET *****END OF FILE****/

platform/plib035/inc/plib035_adc.h

@@ -0,0 +1,1155 @@
+/**
+  ******************************************************************************
+  * @file    plib035_adc.h
+  *
+  * @brief   Файл содержит прототипы и компактные inline реализации функций для
+  *          ADC, а также сопутствующие макроопределения и перечисления
+  *
+  * @author  НИИЭТ, Богдан Колбов <kolbov@niiet.ru>
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ ПРЕДОСТАВЛЯЕТСЯ «КАК ЕСТЬ», БЕЗ КАКИХ-ЛИБО
+  * ГАРАНТИЙ, ЯВНО ВЫРАЖЕННЫХ ИЛИ ПОДРАЗУМЕВАЕМЫХ, ВКЛЮЧАЯ ГАРАНТИИ ТОВАРНОЙ
+  * ПРИГОДНОСТИ, СООТВЕТСТВИЯ ПО ЕГО КОНКРЕТНОМУ НАЗНАЧЕНИЮ И ОТСУТСТВИЯ
+  * НАРУШЕНИЙ, НО НЕ ОГРАНИЧИВАЯСЬ ИМИ. ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ
+  * ПРЕДНАЗНАЧЕНО ДЛЯ ОЗНАКОМИТЕЛЬНЫХ ЦЕЛЕЙ И НАПРАВЛЕНО ТОЛЬКО НА
+  * ПРЕДОСТАВЛЕНИЕ ДОПОЛНИТЕЛЬНОЙ ИНФОРМАЦИИ О ПРОДУКТЕ, С ЦЕЛЬЮ СОХРАНИТЬ ВРЕМЯ
+  * ПОТРЕБИТЕЛЮ. НИ В КАКОМ СЛУЧАЕ АВТОРЫ ИЛИ ПРАВООБЛАДАТЕЛИ НЕ НЕСУТ
+  * ОТВЕТСТВЕННОСТИ ПО КАКИМ-ЛИБО ИСКАМ, ЗА ПРЯМОЙ ИЛИ КОСВЕННЫЙ УЩЕРБ, ИЛИ
+  * ПО ИНЫМ ТРЕБОВАНИЯМ, ВОЗНИКШИМ ИЗ-ЗА ИСПОЛЬЗОВАНИЯ ПРОГРАММНОГО ОБЕСПЕЧЕНИЯ
+  * ИЛИ ИНЫХ ДЕЙСТВИЙ С ПРОГРАММНЫМ ОБЕСПЕЧЕНИЕМ.
+  *
+  * <h2><center>&copy; 2018 ОАО "НИИЭТ"</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PLIB035_ADC_H
+#define __PLIB035_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "plib035.h"
+
+/** @addtogroup Peripheral
+  * @{
+  */
+
+/** @defgroup ADC
+  * @brief Драйвер для работы с ADC
+  * @{
+  */
+
+/** @defgroup ADC_Exported_Defines Константы
+  * @{
+  */
+
+#define ADC_SEQ_Total 2UL
+#define ADC_SEQ_Req_Total 4UL
+#define ADC_DC_Total 4UL
+#define ADC_CH_Total 4UL
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Types Типы
+  * @{
+  */
+
+/**
+  * @brief  Номер секвенсора
+  */
+typedef enum {
+    ADC_SEQ_Num_0, /*!< Севенсор 0 */
+    ADC_SEQ_Num_1  /*!< Севенсор 1 */
+} ADC_SEQ_Num_TypeDef;
+#define IS_ADC_SEQ_NUM(VALUE) (((VALUE) == ADC_SEQ_Num_0) || \
+                               ((VALUE) == ADC_SEQ_Num_1))
+
+/**
+  * @brief  Номер запроса в очереди секвенсора
+  */
+typedef enum {
+    ADC_SEQ_ReqNum_0, /*!< Запрос 0 */
+    ADC_SEQ_ReqNum_1, /*!< Запрос 1 */
+    ADC_SEQ_ReqNum_2, /*!< Запрос 2 */
+    ADC_SEQ_ReqNum_3  /*!< Запрос 3 */
+} ADC_SEQ_ReqNum_TypeDef;
+#define IS_ADC_SEQ_REQ_NUM(VALUE) (((VALUE) == ADC_SEQ_ReqNum_0) || \
+                                   ((VALUE) == ADC_SEQ_ReqNum_1) || \
+                                   ((VALUE) == ADC_SEQ_ReqNum_2) || \
+                                   ((VALUE) == ADC_SEQ_ReqNum_3))
+
+/**
+  * @brief  События запуска секвенсоров
+  */
+typedef enum {
+    ADC_SEQ_StartEvent_SwReq = ADC_EMUX_EM0_SwReq,     /*!< Запуск по программному запросу */
+    ADC_SEQ_StartEvent_GPIOA = ADC_EMUX_EM0_GPIOA,     /*!< Сигнал от GPIOA */
+    ADC_SEQ_StartEvent_GPIOB = ADC_EMUX_EM0_GPIOB,     /*!< Сигнал от GPIOB */
+    ADC_SEQ_StartEvent_TMR0 = ADC_EMUX_EM0_TMR0,       /*!< Сигнал от таймера 0 */
+    ADC_SEQ_StartEvent_TMR1 = ADC_EMUX_EM0_TMR1,       /*!< Сигнал от таймера 1 */
+    ADC_SEQ_StartEvent_TMR2 = ADC_EMUX_EM0_TMR2,       /*!< Сигнал от таймера 2 */
+    ADC_SEQ_StartEvent_TMR3 = ADC_EMUX_EM0_TMR3,       /*!< Сигнал от таймера 3 */
+    ADC_SEQ_StartEvent_PWM012A = ADC_EMUX_EM0_PWM012A, /*!< Сигналы A от блоков ШИМ 0, 1, 2 */
+    ADC_SEQ_StartEvent_PWM012B = ADC_EMUX_EM0_PWM012B, /*!< Сигналы B от блоков ШИМ 0, 1, 2 */
+    ADC_SEQ_StartEvent_Cycle = ADC_EMUX_EM0_Cycle,     /*!< Циклическая работа сразу после запуска секвенсора */
+} ADC_SEQ_StartEvent_TypeDef;
+#define IS_ADC_SEQ_START_EVENT(VALUE) (((VALUE) == ADC_SEQ_StartEvent_SwReq) ||   \
+                                       ((VALUE) == ADC_SEQ_StartEvent_GPIOA) ||   \
+                                       ((VALUE) == ADC_SEQ_StartEvent_GPIOB) ||   \
+                                       ((VALUE) == ADC_SEQ_StartEvent_TMR0) ||    \
+                                       ((VALUE) == ADC_SEQ_StartEvent_TMR1) ||    \
+                                       ((VALUE) == ADC_SEQ_StartEvent_TMR2) ||    \
+                                       ((VALUE) == ADC_SEQ_StartEvent_TMR3) ||    \
+                                       ((VALUE) == ADC_SEQ_StartEvent_PWM012A) || \
+                                       ((VALUE) == ADC_SEQ_StartEvent_PWM012B) || \
+                                       ((VALUE) == ADC_SEQ_StartEvent_Cycle))
+
+/**
+  * @brief  Количество измерений для усреднения
+  */
+typedef enum {
+    ADC_SEQ_Average_2 = ADC_SEQ_SRQCTL_QAVGVAL_Average2,   /*!< Усреднение по 2 измерениям */
+    ADC_SEQ_Average_4 = ADC_SEQ_SRQCTL_QAVGVAL_Average4,   /*!< Усреднение по 4 измерениям */
+    ADC_SEQ_Average_8 = ADC_SEQ_SRQCTL_QAVGVAL_Average8,   /*!< Усреднение по 8 измерениям */
+    ADC_SEQ_Average_16 = ADC_SEQ_SRQCTL_QAVGVAL_Average16, /*!< Усреднение по 16 измерениям */
+    ADC_SEQ_Average_32 = ADC_SEQ_SRQCTL_QAVGVAL_Average32, /*!< Усреднение по 32 измерениям */
+    ADC_SEQ_Average_64 = ADC_SEQ_SRQCTL_QAVGVAL_Average64, /*!< Усреднение по 64 измерениям */
+} ADC_SEQ_Average_TypeDef;
+#define IS_ADC_SEQ_AVERAGE(VALUE) (((VALUE) == ADC_SEQ_Average_2) ||  \
+                                   ((VALUE) == ADC_SEQ_Average_4) ||  \
+                                   ((VALUE) == ADC_SEQ_Average_8) ||  \
+                                   ((VALUE) == ADC_SEQ_Average_16) || \
+                                   ((VALUE) == ADC_SEQ_Average_32) || \
+                                   ((VALUE) == ADC_SEQ_Average_64))
+
+/**
+  * @brief  Количество результатов измерений записанных в буфер секвенсора, по достижению которого вызывается DMA
+  */
+typedef enum {
+    ADC_SEQ_DMAFIFOLevel_1 = ADC_SEQ_SDMACTL_WMARK_Level1,   /*!< Запрос DMA после заполнения 1 ячейки в буффере */
+    ADC_SEQ_DMAFIFOLevel_2 = ADC_SEQ_SDMACTL_WMARK_Level2,   /*!< Запрос DMA после заполнения 2 ячеек в буффере */
+    ADC_SEQ_DMAFIFOLevel_4 = ADC_SEQ_SDMACTL_WMARK_Level4,   /*!< Запрос DMA после заполнения 4 ячеек в буффере */
+    ADC_SEQ_DMAFIFOLevel_8 = ADC_SEQ_SDMACTL_WMARK_Level8,   /*!< Запрос DMA после заполнения 8 ячеек в буффере */
+    ADC_SEQ_DMAFIFOLevel_16 = ADC_SEQ_SDMACTL_WMARK_Level16, /*!< Запрос DMA после заполнения 16 ячеек в буффере */
+    ADC_SEQ_DMAFIFOLevel_32 = ADC_SEQ_SDMACTL_WMARK_Level32, /*!< Запрос DMA после заполнения 32 ячеек в буффере */
+} ADC_SEQ_DMAFIFOLevel_TypeDef;
+#define IS_ADC_SEQ_DMA_FIFO_LEVEL(VALUE) (((VALUE) == ADC_SEQ_DMAFIFOLevel_1) ||  \
+                                          ((VALUE) == ADC_SEQ_DMAFIFOLevel_2) ||  \
+                                          ((VALUE) == ADC_SEQ_DMAFIFOLevel_4) ||  \
+                                          ((VALUE) == ADC_SEQ_DMAFIFOLevel_8) ||  \
+                                          ((VALUE) == ADC_SEQ_DMAFIFOLevel_16) || \
+                                          ((VALUE) == ADC_SEQ_DMAFIFOLevel_32))
+
+/**
+  * @brief Номер цифрового компаратора
+  */
+typedef enum {
+    ADC_DC_Num_0, /*!< Модуль цифрового компаратора 0 */
+    ADC_DC_Num_1, /*!< Модуль цифрового компаратора 1 */
+    ADC_DC_Num_2, /*!< Модуль цифрового компаратора 2 */
+    ADC_DC_Num_3, /*!< Модуль цифрового компаратора 3 */
+} ADC_DC_Num_TypeDef;
+#define IS_ADC_DC_NUM(VALUE) (((VALUE) == ADC_DC_Num_0) || \
+                              ((VALUE) == ADC_DC_Num_1) || \
+                              ((VALUE) == ADC_DC_Num_2) || \
+                              ((VALUE) == ADC_DC_Num_3))
+
+/**
+  * @brief  Режим срабатывания цифрового компаратора
+  */
+typedef enum {
+    ADC_DC_Mode_Multiple = ADC_DC_DCTL_CIM_Multiple,         /*!< Многократный */
+    ADC_DC_Mode_Single = ADC_DC_DCTL_CIM_Single,             /*!< Однократный */
+    ADC_DC_Mode_MultipleHyst = ADC_DC_DCTL_CIM_MultipleHyst, /*!< Многократный с гистерезисом */
+    ADC_DC_Mode_SingleHyst = ADC_DC_DCTL_CIM_SingleHyst,     /*!< Однократный с гистерезисом */
+} ADC_DC_Mode_TypeDef;
+#define IS_ADC_DC_MODE(VALUE) (((VALUE) == ADC_DC_Mode_Single) ||     \
+                               ((VALUE) == ADC_DC_Mode_Multiple) ||   \
+                               ((VALUE) == ADC_DC_Mode_SingleHyst) || \
+                               ((VALUE) == ADC_DC_Mode_MultipleHyst))
+
+/**
+  * @brief  Условие срабатывания компаратора
+  */
+typedef enum {
+    ADC_DC_Condition_Low = ADC_DC_DCTL_CIC_Low,       /*!< Результат меньше либо равен нижней границе */
+    ADC_DC_Condition_Window = ADC_DC_DCTL_CIC_Window, /*!< Результат внутри диапазона, задаваемого границами, либо равен одной из них */
+    ADC_DC_Condition_High = ADC_DC_DCTL_CIC_High,     /*!< Результат больше либо равен верхней границе */
+} ADC_DC_Condition_TypeDef;
+#define IS_ADC_DC_CONDITION(VALUE) (((VALUE) == ADC_DC_Condition_Low) ||    \
+                                    ((VALUE) == ADC_DC_Condition_Window) || \
+                                    ((VALUE) == ADC_DC_Condition_High))
+
+/**
+  * @brief  Источник данных для компаратора
+  */
+typedef enum {
+    ADC_DC_Source_EOC,  /*!< Ококнчание измерения АЦП */
+    ADC_DC_Source_FIFO, /*!< Запись результатат в FIFO */
+} ADC_DC_Source_TypeDef;
+#define IS_ADC_DC_SOURCE(VALUE) (((VALUE) == ADC_DC_Source_EOC) || \
+                                 ((VALUE) == ADC_DC_Source_FIFO))
+
+/**
+  * @brief  Номер канала
+  */
+typedef enum {
+    ADC_CH_Num_0, /*!< Канал 0 */
+    ADC_CH_Num_1, /*!< Канал 1 */
+    ADC_CH_Num_2, /*!< Канал 2 */
+    ADC_CH_Num_3, /*!< Канал 3 */
+} ADC_CH_Num_TypeDef;
+#define IS_ADC_CH_NUM(VALUE) (((VALUE) == ADC_CH_Num_0) || \
+                              ((VALUE) == ADC_CH_Num_1) || \
+                              ((VALUE) == ADC_CH_Num_2) || \
+                              ((VALUE) == ADC_CH_Num_3))
+
+/**
+  * @brief  Выбор приоритета канала
+  */
+typedef enum {
+    ADC_CH_Priority_Normal, /*!< Обычный уровень приоритета */
+    ADC_CH_Priority_High,   /*!< Высокий уровень приоритета */
+} ADC_CH_Priority_TypeDef;
+#define IS_ADC_CH_PRIORITY(VALUE) (((VALUE) == ADC_CH_Priority_Normal) || \
+                                   ((VALUE) == ADC_CH_Priority_High))
+
+/**
+  * @brief  Структура инициализации цифровых компараторов
+  */
+typedef struct
+{
+    FunctionalState DCOutput;           /*!< Разрешает работу выходному триггеру компаратора */
+    uint32_t ThresholdLow;              /*!< Нижний порог срабатывания компаратора.
+                                             Параметр может принимать любое значение из диапазона 0 - 4095. */
+    uint32_t ThresholdHigh;             /*!< Верхний порог срабатывания компаратора.
+                                             Параметр может принимать любое значение из диапазона 0 - 4095. */
+    ADC_DC_Source_TypeDef Source;       /*!< Выбирает источник получения измерения */
+    ADC_CH_Num_TypeDef Channel;         /*!< Выбирает канал, результат измерения которого будет передан на компаратор */
+    ADC_DC_Mode_TypeDef Mode;           /*!< Выбирает режим срабатывания компаратора */
+    ADC_DC_Condition_TypeDef Condition; /*!< Выбирает условие срабатывания компаратора */
+} ADC_DC_Init_TypeDef;
+
+#define IS_ADC_DC_THRESHOLD(VALUE) ((VALUE) < 0x1000)
+
+/**
+  * @brief  Структура инициализации секвенсоров
+  */
+typedef struct
+{
+    ADC_SEQ_StartEvent_TypeDef StartEvent;     /*!< Определяет cобытие запуска секвенсора */
+    FunctionalState SWStartEn;                 /*!< Разрешает секвенсору запускаться по программному запросу */
+    ADC_CH_Num_TypeDef Req[ADC_SEQ_Req_Total]; /*!< Выбор каналов для запросов секвенсора */
+    ADC_SEQ_ReqNum_TypeDef ReqMax;             /*!< Настройка глубины очереди запросов */
+    ADC_SEQ_Average_TypeDef ReqAverage;        /*!< Настройка усреднения сканированием очереди запросов */
+    FunctionalState ReqAverageEn;              /*!< Разрешение усреднения сканированием очереди запросов */
+    uint32_t RestartCount;                     /*!< Задание количества перезапусков модулей АЦП секвенсором после его запуска по событию.
+                                                         0x00 - без перезапусков, 0x01 - 1 перезапуск, 0xFF - 255 перезапусков. */
+    FunctionalState RestartAverageEn;          /*!< Разрешение усреднения по перезапускам */
+    uint32_t RestartTimer;                     /*!< Задание задержки запуска модуля АЦП.
+                                                         Параметр может принимать любое значение из диапазона 0x00000000 - 0x00FFFFFF. */
+    FunctionalState DCEn[ADC_DC_Total];        /*!< Разрешение работы цифровых компараторов секвенсором */
+    ADC_SEQ_DMAFIFOLevel_TypeDef DMAFIFOLevel; /*!< Настройка уровня заполненности буфера для генерации запросов DMA */
+    FunctionalState DMAEn;                     /*!< Разрешение генерации запросов DMA */
+} ADC_SEQ_Init_TypeDef;
+
+#define IS_ADC_SEQ_RESTART_VAL(VALUE) ((VALUE) < 0x100)
+#define IS_ADC_SEQ_RESTART_TIMER_VAL(VALUE) ((VALUE) < 0x1000000)
+#define IS_ADC_SEQ_IT_COUNT_VAL(VALUE) ((VALUE) < 0x100)
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions Функции
+  * @{
+  */
+
+void ADC_DeInit(void);
+
+/**
+  * @brief   Включение аналогового модуля АЦП
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_AM_Cmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(ADC->ACTL_bit.ADCEN, State);
+}
+
+/**
+  * @brief   Чтение статуса готовности аналогового модуля АЦП. Флаг становится активным после того,
+  *          как модуль АЦП провел внутренние процедуры иницализации.
+  * @retval  Status  Статус готовности
+  */
+__STATIC_INLINE FlagStatus ADC_AM_ReadyStatus(void)
+{
+    return (FlagStatus)READ_REG(ADC->ACTL_bit.ADCRDY);
+}
+
+/**
+  * @brief   Чтение статуса занятости аналогового модуля АЦП. Флаг становится активным при
+  *          проведении измерения.
+  * @retval  Status  Статус занятости
+  */
+__STATIC_INLINE FlagStatus ADC_AM_BusyStatus(void)
+{
+    return (FlagStatus)READ_REG(ADC->BSTAT_bit.ADCBUSY);
+}
+
+/**
+  * @brief   Настройка приоритета канала АЦП
+  * @param   Channel_Num  Выбор канала
+  * @param   Priority  Выбор приоритета
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_CH_PriorityConfig(ADC_CH_Num_TypeDef Channel_Num, ADC_CH_Priority_TypeDef Priority)
+{
+    assert_param(IS_ADC_CH_NUM(Channel_Num));
+    assert_param(IS_ADC_CH_PRIORITY(Priority));
+
+    WRITE_REG(ADC->CHCTL[Channel_Num].CHCTL_bit.PRIORITY, Priority);
+}
+
+/**
+  * @brief   Получение текущего значения коэффициента коррекции ошибки усиления
+  * @param   Channel_Num  Выбор канала
+  * @retval  Val  Значение. Диапазон значений -256…255, величина в
+                  дополнительном коде: 100h соответствует -256, 000h - 0, 0FFh - 255.
+  */
+__STATIC_INLINE uint32_t ADC_CH_GetGainTrim(ADC_CH_Num_TypeDef Channel_Num)
+{
+    assert_param(IS_ADC_CH_NUM(Channel_Num));
+
+    return READ_REG(ADC->CHCTL[Channel_Num].CHCTL_bit.GAINTRIM);
+}
+
+/**
+  * @brief   Установка значения коэффициента коррекции ошибки усиления
+  * @param   Channel_Num  Выбор канала
+  * @param   Val  Значение. Диапазон значений -256…255, величина в
+                  дополнительном коде: 100h соответствует -256, 000h - 0, 0FFh - 255.
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_CH_SetGainTrim(ADC_CH_Num_TypeDef Channel_Num, uint32_t Val)
+{
+    assert_param(IS_ADC_CH_NUM(Channel_Num));
+
+    WRITE_REG(ADC->CHCTL[Channel_Num].CHCTL_bit.GAINTRIM, Val);
+}
+
+/**
+  * @brief   Получение текущего значения коэффициента коррекции ошибки смещения нуля
+  * @param   Channel_Num  Выбор канала
+  * @retval  Val  Значение. Диапазон значений -256…255, величина в
+                  дополнительном коде: 100h соответствует -256, 000h - 0, 0FFh - 255.
+  */
+__STATIC_INLINE uint32_t ADC_CH_GetOffsetTrim(ADC_CH_Num_TypeDef Channel_Num)
+{
+    assert_param(IS_ADC_CH_NUM(Channel_Num));
+
+    return READ_REG(ADC->CHCTL[Channel_Num].CHCTL_bit.OFFTRIM);
+}
+
+/**
+  * @brief   Установка значения коэффициента коррекции ошибки смещения нуля
+  * @param   Channel_Num  Выбор канала
+  * @param   Val  Значение. Диапазон значений -256…255, величина в
+                  дополнительном коде: 100h соответствует -256, 000h - 0, 0FFh - 255.
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_CH_SetOffsetTrim(ADC_CH_Num_TypeDef Channel_Num, uint32_t Val)
+{
+    assert_param(IS_ADC_CH_NUM(Channel_Num));
+
+    WRITE_REG(ADC->CHCTL[Channel_Num].CHCTL_bit.OFFTRIM, Val);
+}
+
+/** @defgroup ADC_Exported_Functions_Init_SEQ Секвенсоры
+  * @{
+  */
+
+void ADC_SEQ_Init(ADC_SEQ_Num_TypeDef SEQ_Num, ADC_SEQ_Init_TypeDef* InitStruct);
+void ADC_SEQ_StructInit(ADC_SEQ_Init_TypeDef* InitStruct);
+
+/**
+  * @brief   Включение модуля секвенсора АЦП
+  * @param   SEQ_Num  Выбор секвенсора
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_SEQ_Cmd(ADC_SEQ_Num_TypeDef SEQ_Num, FunctionalState State)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    MODIFY_REG(ADC->SEQEN, 1 << (uint32_t)SEQ_Num, State << (uint32_t)SEQ_Num);
+}
+
+/**
+  * @brief   Включение программного запуска секвенсора АЦП
+  * @param   SEQ_Num  Выбор секвенсора
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_SEQ_SwStartEnCmd(ADC_SEQ_Num_TypeDef SEQ_Num, FunctionalState State)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    MODIFY_REG(ADC->SEQSYNC, 1 << (uint32_t)SEQ_Num, State << (uint32_t)SEQ_Num);
+}
+
+/**
+  * @brief   Генерация импульса программного запуска
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_SEQ_SwStartCmd(void)
+{
+    WRITE_REG(ADC->SEQSYNC_bit.GSYNC, 1);
+}
+
+/**
+  * @brief   Чтение статуса занятости секвенсора. Флаг становится активным при
+  *          проведении запусков/перезапусков.
+  * @param   SEQ_Num  Выбор секвенсора
+  * @retval  Status  Статус занятости
+  */
+__STATIC_INLINE FlagStatus ADC_SEQ_BusyStatus(ADC_SEQ_Num_TypeDef SEQ_Num)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+
+    return (FlagStatus)READ_BIT(ADC->BSTAT, 1 << (uint32_t)SEQ_Num);
+}
+
+/**
+  * @brief   Чтение статуса заполнения буфера секвенсора
+  * @param   SEQ_Num  Выбор секвенсора
+  * @retval  Status  Статус заполнения буфера
+  */
+__STATIC_INLINE FlagStatus ADC_SEQ_FIFOFullStatus(ADC_SEQ_Num_TypeDef SEQ_Num)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+
+    return (FlagStatus)READ_BIT(ADC->FSTAT, 1 << ((uint32_t)SEQ_Num + ADC_FSTAT_OV0_Pos));
+}
+
+/**
+  * @brief   Сброс статуса заполнения буфера секвенсора
+  * @param   SEQ_Num  Выбор секвенсора
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_SEQ_FIFOFullStatusClear(ADC_SEQ_Num_TypeDef SEQ_Num)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+
+    WRITE_REG(ADC->FSTAT, 1 << ((uint32_t)SEQ_Num + ADC_FSTAT_OV0_Pos));
+}
+
+/**
+  * @brief   Чтение статуса пустоты буфера секвенсора
+  * @param   SEQ_Num  Выбор секвенсора
+  * @retval  Status  Статус пустоты буфера
+  */
+__STATIC_INLINE FlagStatus ADC_SEQ_FIFOEmptyStatus(ADC_SEQ_Num_TypeDef SEQ_Num)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+
+    return (FlagStatus)READ_BIT(ADC->FSTAT, 1 << ((uint32_t)SEQ_Num + ADC_FSTAT_UN0_Pos));
+}
+
+/**
+  * @brief   Сброс статуса пустоты буфера секвенсора
+  * @param   SEQ_Num  Выбор секвенсора
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_SEQ_FIFOEmptyStatusClear(ADC_SEQ_Num_TypeDef SEQ_Num)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+
+    WRITE_REG(ADC->FSTAT, 1 << ((uint32_t)SEQ_Num + ADC_FSTAT_UN0_Pos));
+}
+
+/**
+  * @brief   Настройка события запуска секвенсора
+  * @param   SEQ_Num  Выбор секвенсора
+  * @param   StartEvent  Выбор события
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_SEQ_StartEventConfig(ADC_SEQ_Num_TypeDef SEQ_Num, ADC_SEQ_StartEvent_TypeDef StartEvent)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+
+    MODIFY_REG(ADC->EMUX, 0xF << ((uint32_t)SEQ_Num * 4), StartEvent << ((uint32_t)SEQ_Num * 4));
+}
+
+/**
+  * @brief   Выбор каналов для запроса секвенсора
+  * @param   SEQ_Num  Выбор секвенсора
+  * @param   ReqNum  Выбор запроса
+  * @param   Channel_Num  Выбор канала
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_SEQ_ReqConfig(ADC_SEQ_Num_TypeDef SEQ_Num, ADC_SEQ_ReqNum_TypeDef ReqNum, ADC_CH_Num_TypeDef Channel_Num)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+    assert_param(IS_ADC_SEQ_REQ_NUM(ReqNum));
+    assert_param(IS_ADC_CH_NUM(Channel_Num));
+
+    MODIFY_REG(ADC->SEQ[SEQ_Num].SRQSEL, 0x3 << ((uint32_t)ReqNum * 4), Channel_Num << ((uint32_t)ReqNum * 4));
+}
+
+/**
+  * @brief   Настройка глубины очереди запросов
+  * @param   SEQ_Num  Выбор секвенсора
+  * @param   ReqNumMax  Номер последнего запроса
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_SEQ_ReqMaxConfig(ADC_SEQ_Num_TypeDef SEQ_Num, ADC_SEQ_ReqNum_TypeDef ReqNumMax)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+    assert_param(IS_ADC_SEQ_REQ_NUM(ReqNumMax));
+
+    WRITE_REG(ADC->SEQ[SEQ_Num].SRQCTL_bit.RQMAX, ReqNumMax);
+}
+
+/**
+  * @brief   Настройка усреднения сканированием очереди запросов
+  * @param   SEQ_Num  Выбор секвенсора
+  * @param   Average  Выбор режима усреднения
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_SEQ_ReqAverageConfig(ADC_SEQ_Num_TypeDef SEQ_Num, ADC_SEQ_Average_TypeDef Average)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+    assert_param(IS_ADC_SEQ_AVERAGE(Average));
+
+    WRITE_REG(ADC->SEQ[SEQ_Num].SRQCTL_bit.QAVGVAL, Average);
+}
+
+/**
+  * @brief   Включение усреднения сканированием очереди запросов
+  * @param   SEQ_Num  Выбор секвенсора
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_SEQ_ReqAverageCmd(ADC_SEQ_Num_TypeDef SEQ_Num, FunctionalState State)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(ADC->SEQ[SEQ_Num].SRQCTL_bit.QAVGEN, State);
+}
+
+/**
+  * @brief   Получение текущего номера запроса в очереди
+  * @param   SEQ_Num  Выбор секвенсора
+  * @retval  Val  Номер запроса
+  */
+__STATIC_INLINE ADC_SEQ_ReqNum_TypeDef ADC_SEQ_GetReqCurrent(ADC_SEQ_Num_TypeDef SEQ_Num)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+
+    return (ADC_SEQ_ReqNum_TypeDef)READ_REG(ADC->SEQ[SEQ_Num].SRQSTAT_bit.RQPTR);
+}
+
+/**
+  * @brief   Чтение статуса занятости запроса секвенсора. Флаг становится активным при
+  *          выставленном запросе.
+  * @param   SEQ_Num  Выбор секвенсора
+  * @retval  Status  Статус занятости
+  */
+__STATIC_INLINE FlagStatus ADC_SEQ_ReqBusyStatus(ADC_SEQ_Num_TypeDef SEQ_Num)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+
+    return (FlagStatus)READ_REG(ADC->SEQ[SEQ_Num].SRQSTAT_bit.RQBUSY);
+}
+
+/**
+  * @brief   Настройка генерации запросов DMA
+  * @param   SEQ_Num  Выбор секвенсора
+  * @param   DMAFIFOLevel  Выбор уровня заполнения буфера для генерации запросов DMA
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_SEQ_DMAConfig(ADC_SEQ_Num_TypeDef SEQ_Num, ADC_SEQ_DMAFIFOLevel_TypeDef DMAFIFOLevel)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+    assert_param(IS_ADC_SEQ_DMA_FIFO_LEVEL(DMAFIFOLevel));
+
+    WRITE_REG(ADC->SEQ[SEQ_Num].SDMACTL_bit.WMARK, DMAFIFOLevel);
+}
+
+/**
+  * @brief   Включение генерации запросов DMA
+  * @param   SEQ_Num  Выбор секвенсора
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_SEQ_DMACmd(ADC_SEQ_Num_TypeDef SEQ_Num, FunctionalState State)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(ADC->SEQ[SEQ_Num].SDMACTL_bit.DMAEN, State);
+}
+
+/**
+  * @brief   Чтение статуса ошибки генерации запросов DMA
+  * @param   SEQ_Num  Выбор секвенсора
+  * @retval  Status  Статус ошибки
+  */
+__STATIC_INLINE FlagStatus ADC_SEQ_DMAErrorStatus(ADC_SEQ_Num_TypeDef SEQ_Num)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+
+    return (FlagStatus)READ_BIT(ADC->FSTAT, 1 << ((uint32_t)SEQ_Num + ADC_FSTAT_DOV0_Pos));
+}
+
+/**
+  * @brief   Сброс статуса ошибки генерации запросов DMA
+  * @param   SEQ_Num  Выбор секвенсора
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_SEQ_DMAErrorStatusClear(ADC_SEQ_Num_TypeDef SEQ_Num)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+
+    WRITE_REG(ADC->FSTAT, 1 << ((uint32_t)SEQ_Num + ADC_FSTAT_DOV0_Pos));
+}
+
+/**
+  * @brief   Настройка количества перезапусков очереди запросов
+  * @param   SEQ_Num  Выбор секвенсора
+  * @param   RestartVal  Количество. 0x00 - без перезапусков,
+  *                      0x01 - 1 перезапуск, 0xFF - 255 перезапусков.
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_SEQ_RestartConfig(ADC_SEQ_Num_TypeDef SEQ_Num, uint32_t RestartVal)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+    assert_param(IS_ADC_SEQ_RESTART_VAL(RestartVal));
+
+    WRITE_REG(ADC->SEQ[SEQ_Num].SCCTL_bit.RCNT, RestartVal);
+}
+
+/**
+  * @brief   Включение режима усреднения по перезапускам.
+  *          При этом количество перезапусков должно равнятся 2^p - 1 (p=1..8).
+  * @param   SEQ_Num  Выбор секвенсора
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_SEQ_RestartAverageCmd(ADC_SEQ_Num_TypeDef SEQ_Num, FunctionalState State)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(ADC->SEQ[SEQ_Num].SCCTL_bit.RAVGEN, State);
+}
+
+/**
+  * @brief   Получение текущего количества совершенных перезапусков
+  * @param   SEQ_Num  Выбор секвенсора
+  * @retval  Val  Номер запроса
+  */
+__STATIC_INLINE uint32_t ADC_SEQ_GetRestartCurrent(ADC_SEQ_Num_TypeDef SEQ_Num)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+
+    return READ_REG(ADC->SEQ[SEQ_Num].SCVAL_bit.RCNT);
+}
+
+/**
+  * @brief   Разрешение поступления данных на выбранный цифровой компаратор
+  * @param   SEQ_Num  Выбор секвенсора
+  * @param   DC_Num  Выбор компаратора
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_SEQ_DCEnableCmd(ADC_SEQ_Num_TypeDef SEQ_Num, ADC_DC_Num_TypeDef DC_Num, FunctionalState State)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+    assert_param(IS_ADC_DC_NUM(DC_Num));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    MODIFY_REG(ADC->SEQ[SEQ_Num].SDC, 1 << ((uint32_t)DC_Num), State << ((uint32_t)DC_Num));
+}
+
+/**
+  * @brief   Установка значения задержки перезапуска секвенсора в тактак ACLK
+  * @param   SEQ_Num  Выбор секвенсора
+  * @param   TimerVal  Значение. 0 - означает отсутствие задержки и немедленный перезапуск (если активен).
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_SEQ_SetRestartTimer(ADC_SEQ_Num_TypeDef SEQ_Num, uint32_t TimerVal)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+    assert_param(IS_ADC_SEQ_RESTART_TIMER_VAL(TimerVal));
+
+    WRITE_REG(ADC->SEQ[SEQ_Num].SRTMR_bit.VAL, TimerVal);
+}
+/**
+  * @brief   Получение текущего значения задержки перезапуска секвенсора в тактак ACLK
+  * @param   SEQ_Num  Выбор секвенсора
+  * @retval  Val  Значение. 0 - означает отсутствие задержки и немедленный перезапуск (если активен).
+  */
+__STATIC_INLINE uint32_t ADC_SEQ_GetRestartTimer(ADC_SEQ_Num_TypeDef SEQ_Num)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+
+    return READ_REG(ADC->SEQ[SEQ_Num].SRTMR_bit.VAL);
+}
+
+/**
+  * @brief   Разрешение обновления значения задержки по событиям перезапуска (по умолчанию, только по запускам)
+  * @param   SEQ_Num  Выбор секвенсора
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_SEQ_RestartTimerUpdateCmd(ADC_SEQ_Num_TypeDef SEQ_Num, FunctionalState State)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(ADC->SEQ[SEQ_Num].SRTMR_bit.NOWAIT, State);
+}
+
+/**
+  * @brief   Получение текущего значения количества результатов в буфере секвенсора
+  * @param   SEQ_Num  Выбор секвенсора
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t ADC_SEQ_GetFIFOLoad(ADC_SEQ_Num_TypeDef SEQ_Num)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+
+    return READ_REG(ADC->SEQ[SEQ_Num].SFLOAD_bit.VAL);
+}
+
+/**
+  * @brief   Получение результата измерения из буфера секвенсора
+  * @param   SEQ_Num  Выбор секвенсора
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t ADC_SEQ_GetFIFOData(ADC_SEQ_Num_TypeDef SEQ_Num)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+
+    return READ_REG(ADC->SEQ[SEQ_Num].SFIFO_bit.DATA);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions_Init_DC Цифровые компараторы
+  * @{
+  */
+
+void ADC_DC_Init(ADC_DC_Num_TypeDef DC_Num, ADC_DC_Init_TypeDef* InitStruct);
+void ADC_DC_StructInit(ADC_DC_Init_TypeDef* InitStruct);
+
+/**
+  * @brief   Разрешение работы цифрового компаратора
+  * @param   DC_Num  Выбор компаратора
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_DC_OutputCmd(ADC_DC_Num_TypeDef DC_Num, FunctionalState State)
+{
+    assert_param(IS_ADC_DC_NUM(DC_Num));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(ADC->DC[DC_Num].DCTL_bit.CTE, State);
+}
+
+/**
+  * @brief   Настройка источника данных цифрового компаратора
+  * @param   DC_Num  Выбор компаратора
+  * @param   Source  Выбор источника
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_DC_SourceConfig(ADC_DC_Num_TypeDef DC_Num, ADC_DC_Source_TypeDef Source)
+{
+    assert_param(IS_ADC_DC_NUM(DC_Num));
+    assert_param(IS_ADC_DC_SOURCE(Source));
+
+    WRITE_REG(ADC->DC[DC_Num].DCTL_bit.SRC, Source);
+}
+
+/**
+  * @brief   Выбор канала АЦП для получения данных цифрового компаратора
+  * @param   DC_Num  Выбор компаратора
+  * @param   Source  Выбор источника
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_DC_ChannelConfig(ADC_DC_Num_TypeDef DC_Num, ADC_CH_Num_TypeDef Channel_Num)
+{
+    assert_param(IS_ADC_DC_NUM(DC_Num));
+    assert_param(IS_ADC_CH_NUM(Channel_Num));
+
+    WRITE_REG(ADC->DC[DC_Num].DCTL_bit.CHNL, Channel_Num);
+}
+
+/**
+  * @brief   Настройка режима и условия срабатывания компаратора
+  * @param   DC_Num  Выбор компаратора
+  * @param   Mode  Выбор режима
+  * @param   Condition  Выбор условия
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_DC_Config(ADC_DC_Num_TypeDef DC_Num, ADC_DC_Mode_TypeDef Mode, ADC_DC_Condition_TypeDef Condition)
+{
+    assert_param(IS_ADC_DC_NUM(DC_Num));
+    assert_param(IS_ADC_DC_MODE(Mode));
+    assert_param(IS_ADC_DC_CONDITION(Condition));
+
+    MODIFY_REG(ADC->DC[DC_Num].DCTL, ADC_DC_DCTL_CTC_Msk | ADC_DC_DCTL_CTM_Msk,
+               ((Mode << ADC_DC_DCTL_CTM_Pos) |
+                (Condition << ADC_DC_DCTL_CTC_Pos)));
+}
+
+/**
+  * @brief   Установка значения нижней границы цифрового компаратора
+  * @param   DC_Num  Выбор компаратора
+  * @param   Val  Значение. Диапазон 0-0xFFF.
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_DC_SetThresholdLow(ADC_DC_Num_TypeDef DC_Num, uint32_t Val)
+{
+    assert_param(IS_ADC_DC_NUM(DC_Num));
+    assert_param(IS_ADC_DC_THRESHOLD(Val));
+
+    WRITE_REG(ADC->DC[DC_Num].DCMP_bit.CMPL, Val);
+}
+
+/**
+  * @brief   Получение значения нижней границы цифрового компаратора
+  * @param   DC_Num  Выбор компаратора
+  * @retval  Val  Значение. Диапазон 0-0xFFF.
+  */
+__STATIC_INLINE uint32_t ADC_DC_GetThresholdLow(ADC_DC_Num_TypeDef DC_Num)
+{
+    assert_param(IS_ADC_DC_NUM(DC_Num));
+
+    return READ_REG(ADC->DC[DC_Num].DCMP_bit.CMPL);
+}
+
+/**
+  * @brief   Установка значения верхней границы цифрового компаратора
+  * @param   DC_Num  Выбор компаратора
+  * @param   Val  Значение. Диапазон 0-0xFFF.
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_DC_SetThresholdHigh(ADC_DC_Num_TypeDef DC_Num, uint32_t Val)
+{
+    assert_param(IS_ADC_DC_NUM(DC_Num));
+    assert_param(IS_ADC_DC_THRESHOLD(Val));
+
+    WRITE_REG(ADC->DC[DC_Num].DCMP_bit.CMPH, Val);
+}
+
+/**
+  * @brief   Получение значения верхней границы цифрового компаратора
+  * @param   DC_Num  Выбор компаратора
+  * @retval  Val  Значение. Диапазон 0-0xFFF.
+  */
+__STATIC_INLINE uint32_t ADC_DC_GetThresholdHigh(ADC_DC_Num_TypeDef DC_Num)
+{
+    assert_param(IS_ADC_DC_NUM(DC_Num));
+
+    return READ_REG(ADC->DC[DC_Num].DCMP_bit.CMPH);
+}
+
+/**
+  * @brief   Чтение статуса события сравнения компаратора
+  * @param   DC_Num  Выбор компаратора
+  * @retval  Status  Статус
+  */
+__STATIC_INLINE FlagStatus ADC_DC_CmpEventStatus(ADC_DC_Num_TypeDef DC_Num)
+{
+    assert_param(IS_ADC_DC_NUM(DC_Num));
+
+    return (FlagStatus)READ_BIT(ADC->DCTRIG, 1 << ((uint32_t)DC_Num + ADC_DCTRIG_DCEV0_Pos));
+}
+
+/**
+  * @brief   Сброс статуса события сравнения компаратора
+  * @param   DC_Num  Выбор компаратора
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_DC_CmpEventStatusClear(ADC_DC_Num_TypeDef DC_Num)
+{
+    assert_param(IS_ADC_DC_NUM(DC_Num));
+
+    WRITE_REG(ADC->DCTRIG, 1 << ((uint32_t)DC_Num + ADC_DCTRIG_DCEV0_Pos));
+}
+
+/**
+  * @brief   Чтение статуса выходного триггера компаратора
+  * @param   DC_Num  Выбор компаратора
+  * @retval  Status  Статус
+  */
+__STATIC_INLINE FlagStatus ADC_DC_TrigStatus(ADC_DC_Num_TypeDef DC_Num)
+{
+    assert_param(IS_ADC_DC_NUM(DC_Num));
+
+    return (FlagStatus)READ_BIT(ADC->DCTRIG, 1 << ((uint32_t)DC_Num + ADC_DCTRIG_TOS0_Pos));
+}
+
+/**
+  * @brief   Сброс выходного триггера компаратора
+  * @param   DC_Num  Выбор компаратора
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_DC_TrigStatusClear(ADC_DC_Num_TypeDef DC_Num)
+{
+    assert_param(IS_ADC_DC_NUM(DC_Num));
+
+    WRITE_REG(ADC->DCTRIG, 1 << ((uint32_t)DC_Num + ADC_DCTRIG_TOS0_Pos));
+}
+
+/**
+  * @brief   Получение последнего значения, использованного для сравнения
+  * @param   DC_Num  Выбор компаратора
+  * @retval  Val  Значение. Диапазон 0-0xFFF.
+  */
+__STATIC_INLINE uint32_t ADC_DC_GetLastData(ADC_DC_Num_TypeDef DC_Num)
+{
+    assert_param(IS_ADC_DC_NUM(DC_Num));
+
+    return READ_REG(ADC->DC[DC_Num].DDATA);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions_Int Конфигурация прерываний
+  * @{
+  */
+
+/** @defgroup ADC_Exported_Functions_Int_DC Цифровые компараторы
+  * @{
+  */
+
+/**
+  * @brief   Включение генерации прерывания компаратора
+  * @param   DC_Num  Выбор компаратора
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_DC_ITCmd(ADC_DC_Num_TypeDef DC_Num, FunctionalState State)
+{
+    assert_param(IS_ADC_DC_NUM(DC_Num));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(ADC->DC[DC_Num].DCTL_bit.CIE, State);
+}
+
+/**
+  * @brief   Настройка условий и режима работы для генерации прерывания компаратора
+  * @param   DC_Num  Выбор компаратора
+  * @param   Mode  Выбор режима
+  * @param   Condition  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_DC_ITConfig(ADC_DC_Num_TypeDef DC_Num, ADC_DC_Mode_TypeDef Mode, ADC_DC_Condition_TypeDef Condition)
+{
+    assert_param(IS_ADC_DC_NUM(DC_Num));
+    assert_param(IS_ADC_DC_MODE(Mode));
+    assert_param(IS_ADC_DC_CONDITION(Condition));
+
+    MODIFY_REG(ADC->DC[DC_Num].DCTL, ADC_DC_DCTL_CIC_Msk | ADC_DC_DCTL_CIM_Msk,
+               ((Mode << ADC_DC_DCTL_CIM_Pos) |
+                (Condition << ADC_DC_DCTL_CIC_Pos)));
+}
+
+/**
+  * @brief   Маскирование прерывания компаратора
+  * @param   DC_Num  Выбор компаратора
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_DC_ITMaskCmd(ADC_DC_Num_TypeDef DC_Num, FunctionalState State)
+{
+    assert_param(IS_ADC_DC_NUM(DC_Num));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    MODIFY_REG(ADC->IM, 1 << ((uint32_t)DC_Num + ADC_IM_DCIM0_Pos), State << ((uint32_t)DC_Num + ADC_IM_DCIM0_Pos));
+}
+
+/**
+  * @brief   Запрос немаскированного состояния прерывания компаратора
+  * @param   DC_Num  Выбор компаратора
+  * @retval  Status  Состояние
+  */
+__STATIC_INLINE FlagStatus ADC_DC_ITRawStatus(ADC_DC_Num_TypeDef DC_Num)
+{
+    assert_param(IS_ADC_DC_NUM(DC_Num));
+
+    return (FlagStatus)READ_BIT(ADC->RIS, 1 << ((uint32_t)DC_Num + ADC_RIS_DCRIS0_Pos));
+}
+
+/**
+  * @brief   Запрос маскированного состояния прерывания компаратора
+  * @param   DC_Num  Выбор компаратора
+  * @retval  Status  Состояние
+  */
+__STATIC_INLINE FlagStatus ADC_DC_ITMaskedStatus(ADC_DC_Num_TypeDef DC_Num)
+{
+    assert_param(IS_ADC_DC_NUM(DC_Num));
+
+    return (FlagStatus)READ_BIT(ADC->MIS, 1 << ((uint32_t)DC_Num + ADC_MIS_DCMIS0_Pos));
+}
+
+/**
+  * @brief   Сброс флага прерывания компаратора
+  * @param   DC_Num  Выбор компаратора
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_DC_ITStatusClear(ADC_DC_Num_TypeDef DC_Num)
+{
+    assert_param(IS_ADC_DC_NUM(DC_Num));
+
+    WRITE_REG(ADC->IC, 1 << ((uint32_t)DC_Num + ADC_IC_DCIC0_Pos));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions_Int_SEQ Секвенсоры
+  * @{
+  */
+
+/**
+  * @brief   Маскирование прерывания секвенсора
+  * @param   SEQ_Num  Выбор секвенсора
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_SEQ_ITCmd(ADC_SEQ_Num_TypeDef SEQ_Num, FunctionalState State)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    MODIFY_REG(ADC->IM, 1 << ((uint32_t)SEQ_Num + ADC_IM_SEQIM0_Pos), State << ((uint32_t)SEQ_Num + ADC_IM_SEQIM0_Pos));
+}
+
+/**
+  * @brief   Настройка генерации прерывания секвенсора
+  * @param   SEQ_Num  Выбор секвенсора
+  * @param   ITCount  Количество запросов модуля АЦП для генерации прерывания.
+  *                   0 - по каждому запросу, 0xFF - каждые 256 запросов.
+  * @param   ITCountNoRst  Активация режима, где счетчик прерывания не будет сбрасываться по запуску секвенсора
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_SEQ_ITConfig(ADC_SEQ_Num_TypeDef SEQ_Num, uint32_t ITCount, FunctionalState ITCountNoRst)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+    assert_param(IS_ADC_SEQ_IT_COUNT_VAL(ITCount));
+    assert_param(IS_FUNCTIONAL_STATE(ITCountNoRst));
+
+    WRITE_REG(ADC->SEQ[SEQ_Num].SCCTL_bit.ICNT, ITCount);
+    MODIFY_REG(ADC->CICNT, 1 << ((uint32_t)SEQ_Num + ADC_CICNT_ICNT0_Pos), ITCountNoRst << ((uint32_t)SEQ_Num + ADC_CICNT_ICNT0_Pos));
+}
+
+/**
+  * @brief   Получение текущего состояния счетчика запросов, используемого для генерации прерываний
+  * @param   SEQ_Num  Выбор секвенсора
+  * @retval  Val  Значение. Диапазон 0-0xFF.
+  */
+__STATIC_INLINE uint32_t ADC_SEQ_GetITCountCurrent(ADC_SEQ_Num_TypeDef SEQ_Num)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+
+    return READ_REG(ADC->SEQ[SEQ_Num].SCVAL_bit.ICNT);
+}
+
+/**
+  * @brief   Сброс счетчика запросов, используемого для генерации прерываний
+  * @param   SEQ_Num  Выбор секвенсора
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_SEQ_ITCountRst(ADC_SEQ_Num_TypeDef SEQ_Num)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+
+    WRITE_REG(ADC->SEQ[SEQ_Num].SCVAL_bit.ICLR, 1);
+}
+
+/**
+  * @brief   Запрос немаскированного состояния прерывания секвенсора
+  * @param   SEQ_Num  Выбор секвенсора
+  * @retval  Status  Состояние
+  */
+__STATIC_INLINE FlagStatus ADC_SEQ_ITRawStatus(ADC_SEQ_Num_TypeDef SEQ_Num)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+
+    return (FlagStatus)READ_BIT(ADC->RIS, 1 << ((uint32_t)SEQ_Num + ADC_RIS_SEQRIS0_Pos));
+}
+
+/**
+  * @brief   Запрос маскированного состояния прерывания секвенсора
+  * @param   SEQ_Num  Выбор секвенсора
+  * @retval  Status  Состояние
+  */
+__STATIC_INLINE FlagStatus ADC_SEQ_ITMaskedStatus(ADC_SEQ_Num_TypeDef SEQ_Num)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+
+    return (FlagStatus)READ_BIT(ADC->MIS, 1 << ((uint32_t)SEQ_Num + ADC_MIS_SEQMIS0_Pos));
+}
+
+/**
+  * @brief   Сброс флага прерывания секвенсора
+  * @param   SEQ_Num  Выбор секвенсора
+  * @retval  void
+  */
+__STATIC_INLINE void ADC_SEQ_ITStatusClear(ADC_SEQ_Num_TypeDef SEQ_Num)
+{
+    assert_param(IS_ADC_SEQ_NUM(SEQ_Num));
+
+    WRITE_REG(ADC->IC, 1 << ((uint32_t)SEQ_Num + ADC_IC_SEQIC0_Pos));
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PLIB035_ADC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2018 NIIET *****END OF FILE****/

platform/plib035/inc/plib035_assert.h

@@ -0,0 +1,57 @@
+/**
+  ******************************************************************************
+  * @file    plib035_assert.h
+  *
+  * @brief   Файл управления assert'ами
+  *
+  * @author  НИИЭТ, Богдан Колбов <kolbov@niiet.ru>
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ ПРЕДОСТАВЛЯЕТСЯ «КАК ЕСТЬ», БЕЗ КАКИХ-ЛИБО
+  * ГАРАНТИЙ, ЯВНО ВЫРАЖЕННЫХ ИЛИ ПОДРАЗУМЕВАЕМЫХ, ВКЛЮЧАЯ ГАРАНТИИ ТОВАРНОЙ
+  * ПРИГОДНОСТИ, СООТВЕТСТВИЯ ПО ЕГО КОНКРЕТНОМУ НАЗНАЧЕНИЮ И ОТСУТСТВИЯ
+  * НАРУШЕНИЙ, НО НЕ ОГРАНИЧИВАЯСЬ ИМИ. ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ
+  * ПРЕДНАЗНАЧЕНО ДЛЯ ОЗНАКОМИТЕЛЬНЫХ ЦЕЛЕЙ И НАПРАВЛЕНО ТОЛЬКО НА
+  * ПРЕДОСТАВЛЕНИЕ ДОПОЛНИТЕЛЬНОЙ ИНФОРМАЦИИ О ПРОДУКТЕ, С ЦЕЛЬЮ СОХРАНИТЬ ВРЕМЯ
+  * ПОТРЕБИТЕЛЮ. НИ В КАКОМ СЛУЧАЕ АВТОРЫ ИЛИ ПРАВООБЛАДАТЕЛИ НЕ НЕСУТ
+  * ОТВЕТСТВЕННОСТИ ПО КАКИМ-ЛИБО ИСКАМ, ЗА ПРЯМОЙ ИЛИ КОСВЕННЫЙ УЩЕРБ, ИЛИ
+  * ПО ИНЫМ ТРЕБОВАНИЯМ, ВОЗНИКШИМ ИЗ-ЗА ИСПОЛЬЗОВАНИЯ ПРОГРАММНОГО ОБЕСПЕЧЕНИЯ
+  * ИЛИ ИНЫХ ДЕЙСТВИЙ С ПРОГРАММНЫМ ОБЕСПЕЧЕНИЕМ.
+  *
+  * <h2><center>&copy; 2018 ОАО "НИИЭТ"</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PLIB035_ASSERT_H
+#define __PLIB035_ASSERT_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Раскомментируйте строку ниже для включения макроса "assert_param" в коде библиотеки */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+
+/**
+  * @brief  Данный макрос используется для проверки параметров, передаваемых функции.
+  * @param  expr Если равен FALSE, то вызывается функция assert_failed, которая
+  *         показывает имя файла и номер строки, где произошел вызов. Если равен TRUE,
+  *         то возвращаемое значение отсутсвует.
+  * @retval Нет
+  */
+#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t*)__FILE__, __LINE__))
+
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t* file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __PLIB035_ASSERT_H */
+
+/******************* (C) COPYRIGHT 2018 NIIET *****END OF FILE****/

platform/plib035/inc/plib035_can.h

@@ -0,0 +1,86 @@
+/**
+  ******************************************************************************
+  * @file    plib035_can.h
+  *
+  * @brief   Файл содержит прототипы и компактные inline реализации функций для
+  *          CAN, а также сопутствующие макроопределения и перечисления
+  *
+  * @author  НИИЭТ, Богдан Колбов <kolbov@niiet.ru>
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ ПРЕДОСТАВЛЯЕТСЯ «КАК ЕСТЬ», БЕЗ КАКИХ-ЛИБО
+  * ГАРАНТИЙ, ЯВНО ВЫРАЖЕННЫХ ИЛИ ПОДРАЗУМЕВАЕМЫХ, ВКЛЮЧАЯ ГАРАНТИИ ТОВАРНОЙ
+  * ПРИГОДНОСТИ, СООТВЕТСТВИЯ ПО ЕГО КОНКРЕТНОМУ НАЗНАЧЕНИЮ И ОТСУТСТВИЯ
+  * НАРУШЕНИЙ, НО НЕ ОГРАНИЧИВАЯСЬ ИМИ. ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ
+  * ПРЕДНАЗНАЧЕНО ДЛЯ ОЗНАКОМИТЕЛЬНЫХ ЦЕЛЕЙ И НАПРАВЛЕНО ТОЛЬКО НА
+  * ПРЕДОСТАВЛЕНИЕ ДОПОЛНИТЕЛЬНОЙ ИНФОРМАЦИИ О ПРОДУКТЕ, С ЦЕЛЬЮ СОХРАНИТЬ ВРЕМЯ
+  * ПОТРЕБИТЕЛЮ. НИ В КАКОМ СЛУЧАЕ АВТОРЫ ИЛИ ПРАВООБЛАДАТЕЛИ НЕ НЕСУТ
+  * ОТВЕТСТВЕННОСТИ ПО КАКИМ-ЛИБО ИСКАМ, ЗА ПРЯМОЙ ИЛИ КОСВЕННЫЙ УЩЕРБ, ИЛИ
+  * ПО ИНЫМ ТРЕБОВАНИЯМ, ВОЗНИКШИМ ИЗ-ЗА ИСПОЛЬЗОВАНИЯ ПРОГРАММНОГО ОБЕСПЕЧЕНИЯ
+  * ИЛИ ИНЫХ ДЕЙСТВИЙ С ПРОГРАММНЫМ ОБЕСПЕЧЕНИЕМ.
+  *
+  * <h2><center>&copy; 2018 ОАО "НИИЭТ"</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PLIB035_CAN_H
+#define __PLIB035_CAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "plib035.h"
+
+/** @addtogroup Peripheral
+  * @{
+  */
+
+/** @defgroup CAN
+  * @brief Драйвер для работы с CAN
+  * @{
+  */
+
+/** @defgroup CAN_Exported_Defines Константы
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Exported_Types Типы
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Exported_Functions Функции
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PLIB035_CAN_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2018 NIIET *****END OF FILE****/

platform/plib035/inc/plib035_conf.h

@@ -0,0 +1,49 @@
+/**
+  ******************************************************************************
+  * @file    plib035_conf.h
+  *
+  * @brief   Файл конфигурации библиотеки
+  *
+  * @author  НИИЭТ, Богдан Колбов <kolbov@niiet.ru>
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ ПРЕДОСТАВЛЯЕТСЯ «КАК ЕСТЬ», БЕЗ КАКИХ-ЛИБО
+  * ГАРАНТИЙ, ЯВНО ВЫРАЖЕННЫХ ИЛИ ПОДРАЗУМЕВАЕМЫХ, ВКЛЮЧАЯ ГАРАНТИИ ТОВАРНОЙ
+  * ПРИГОДНОСТИ, СООТВЕТСТВИЯ ПО ЕГО КОНКРЕТНОМУ НАЗНАЧЕНИЮ И ОТСУТСТВИЯ
+  * НАРУШЕНИЙ, НО НЕ ОГРАНИЧИВАЯСЬ ИМИ. ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ
+  * ПРЕДНАЗНАЧЕНО ДЛЯ ОЗНАКОМИТЕЛЬНЫХ ЦЕЛЕЙ И НАПРАВЛЕНО ТОЛЬКО НА
+  * ПРЕДОСТАВЛЕНИЕ ДОПОЛНИТЕЛЬНОЙ ИНФОРМАЦИИ О ПРОДУКТЕ, С ЦЕЛЬЮ СОХРАНИТЬ ВРЕМЯ
+  * ПОТРЕБИТЕЛЮ. НИ В КАКОМ СЛУЧАЕ АВТОРЫ ИЛИ ПРАВООБЛАДАТЕЛИ НЕ НЕСУТ
+  * ОТВЕТСТВЕННОСТИ ПО КАКИМ-ЛИБО ИСКАМ, ЗА ПРЯМОЙ ИЛИ КОСВЕННЫЙ УЩЕРБ, ИЛИ
+  * ПО ИНЫМ ТРЕБОВАНИЯМ, ВОЗНИКШИМ ИЗ-ЗА ИСПОЛЬЗОВАНИЯ ПРОГРАММНОГО ОБЕСПЕЧЕНИЯ
+  * ИЛИ ИНЫХ ДЕЙСТВИЙ С ПРОГРАММНЫМ ОБЕСПЕЧЕНИЕМ.
+  *
+  * <h2><center>&copy; 2018 ОАО "НИИЭТ"</center></h2>
+  ******************************************************************************
+  */
+
+#ifndef __PLIB035_CONF_H
+#define __PLIB035_CONF_H
+
+/* Раскомментируйте/закоментируйте, чтобы включить/отключить заголовочный файл периферии */
+#include "plib035_adc.h"
+#include "plib035_can.h"
+#include "plib035_dma.h"
+#include "plib035_ecap.h"
+#include "plib035_gpio.h"
+#include "plib035_i2c.h"
+#include "plib035_mflash.h"
+#include "plib035_pmu.h"
+#include "plib035_pwm.h"
+#include "plib035_qep.h"
+#include "plib035_rcu.h"
+#include "plib035_spi.h"
+#include "plib035_tmr.h"
+#include "plib035_uart.h"
+#include "plib035_wdt.h"
+
+#endif /* __PLIB035_CONF_H */
+
+/******************* (C) COPYRIGHT 2018 NIIET *****END OF FILE****/

platform/plib035/inc/plib035_dma.h

@@ -0,0 +1,631 @@
+/**
+  ******************************************************************************
+  * @file    plib035_dma.h
+  *
+  * @brief   Файл содержит прототипы и компактные inline реализации функций для
+  *          DMA, а также сопутствующие макроопределения и перечисления
+  *
+  * @author  НИИЭТ, Богдан Колбов <kolbov@niiet.ru>
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ ПРЕДОСТАВЛЯЕТСЯ «КАК ЕСТЬ», БЕЗ КАКИХ-ЛИБО
+  * ГАРАНТИЙ, ЯВНО ВЫРАЖЕННЫХ ИЛИ ПОДРАЗУМЕВАЕМЫХ, ВКЛЮЧАЯ ГАРАНТИИ ТОВАРНОЙ
+  * ПРИГОДНОСТИ, СООТВЕТСТВИЯ ПО ЕГО КОНКРЕТНОМУ НАЗНАЧЕНИЮ И ОТСУТСТВИЯ
+  * НАРУШЕНИЙ, НО НЕ ОГРАНИЧИВАЯСЬ ИМИ. ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ
+  * ПРЕДНАЗНАЧЕНО ДЛЯ ОЗНАКОМИТЕЛЬНЫХ ЦЕЛЕЙ И НАПРАВЛЕНО ТОЛЬКО НА
+  * ПРЕДОСТАВЛЕНИЕ ДОПОЛНИТЕЛЬНОЙ ИНФОРМАЦИИ О ПРОДУКТЕ, С ЦЕЛЬЮ СОХРАНИТЬ ВРЕМЯ
+  * ПОТРЕБИТЕЛЮ. НИ В КАКОМ СЛУЧАЕ АВТОРЫ ИЛИ ПРАВООБЛАДАТЕЛИ НЕ НЕСУТ
+  * ОТВЕТСТВЕННОСТИ ПО КАКИМ-ЛИБО ИСКАМ, ЗА ПРЯМОЙ ИЛИ КОСВЕННЫЙ УЩЕРБ, ИЛИ
+  * ПО ИНЫМ ТРЕБОВАНИЯМ, ВОЗНИКШИМ ИЗ-ЗА ИСПОЛЬЗОВАНИЯ ПРОГРАММНОГО ОБЕСПЕЧЕНИЯ
+  * ИЛИ ИНЫХ ДЕЙСТВИЙ С ПРОГРАММНЫМ ОБЕСПЕЧЕНИЕМ.
+  *
+  * <h2><center>&copy; 2018 ОАО "НИИЭТ"</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PLIB035_DMA_H
+#define __PLIB035_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "plib035.h"
+
+/** @addtogroup Peripheral
+  * @{
+  */
+
+/** @defgroup DMA
+  * @brief Драйвер для работы с DMA
+  * @{
+  */
+
+/** @defgroup DMA_Exported_Defines Константы
+  * @{
+  */
+
+/** @defgroup DMA_ChannelMux_Define Мультиплексируемые каналы
+  * @{
+  */
+
+#define DMA_ChannelMux_8 SIU_DMAMUX_SRCSEL8_Msk   /*!< Выбор мультиплексора канала DMA 8 */
+#define DMA_ChannelMux_9 SIU_DMAMUX_SRCSEL9_Msk   /*!< Выбор мультиплексора канала DMA 9 */
+#define DMA_ChannelMux_10 SIU_DMAMUX_SRCSEL10_Msk /*!< Выбор мультиплексора канала DMA 10 */
+#define DMA_ChannelMux_11 SIU_DMAMUX_SRCSEL11_Msk /*!< Выбор мультиплексора канала DMA 11 */
+#define DMA_ChannelMux_12 SIU_DMAMUX_SRCSEL12_Msk /*!< Выбор мультиплексора канала DMA 12 */
+#define DMA_ChannelMux_13 SIU_DMAMUX_SRCSEL13_Msk /*!< Выбор мультиплексора канала DMA 13 */
+#define DMA_ChannelMux_14 SIU_DMAMUX_SRCSEL14_Msk /*!< Выбор мультиплексора канала DMA 14 */
+#define DMA_ChannelMux_15 SIU_DMAMUX_SRCSEL15_Msk /*!< Выбор мультиплексора канала DMA 15 */
+#define DMA_ChannelMux_All (DMA_ChannelMux_8 |  \
+                            DMA_ChannelMux_9 |  \
+                            DMA_ChannelMux_10 | \
+                            DMA_ChannelMux_11 | \
+                            DMA_ChannelMux_12 | \
+                            DMA_ChannelMux_13 | \
+                            DMA_ChannelMux_14 | \
+                            DMA_ChannelMux_15) /*!< Выбор всех мультиплексоров каналов DMA */
+
+#define IS_DMA_CHANNEL_MUX_NUM(VALUE) (((VALUE) != 0) && (((VALUE) & (~DMA_ChannelMux_All)) == 0))
+
+/**
+   * @}
+   */
+
+/** @defgroup DMA_ChannelMux_Sel_Define Выбор источников мультиплексируемых каналов
+  * @{
+  */
+
+#define DMA_ChannelMux_8_QEP (SIU_DMAMUX_SRCSEL8_QEP << SIU_DMAMUX_SRCSEL8_Pos)        /*!< Выбор QEP в качестве источника запросов канала DMA 8 */
+#define DMA_ChannelMux_8_GPIOA (SIU_DMAMUX_SRCSEL8_GPIOA << SIU_DMAMUX_SRCSEL8_Pos)    /*!< Выбор GPIOA в качестве источника запросов канала DMA 8 */
+#define DMA_ChannelMux_9_TMR0 (SIU_DMAMUX_SRCSEL9_TMR0 << SIU_DMAMUX_SRCSEL9_Pos)      /*!< Выбор TMR0 в качестве источника запросов канала DMA 9 */
+#define DMA_ChannelMux_9_GPIOB (SIU_DMAMUX_SRCSEL9_GPIOB << SIU_DMAMUX_SRCSEL9_Pos)    /*!< Выбор GPIOB в качестве источника запросов канала DMA 9 */
+#define DMA_ChannelMux_10_TMR1 (SIU_DMAMUX_SRCSEL10_TMR1 << SIU_DMAMUX_SRCSEL10_Pos)   /*!< Выбор TMR1 в качестве источника запросов канала DMA 10 */
+#define DMA_ChannelMux_10_PWM2B (SIU_DMAMUX_SRCSEL10_PWM0B << SIU_DMAMUX_SRCSEL10_Pos) /*!< Выбор PWM2 B в качестве источника запросов канала DMA 10 */
+#define DMA_ChannelMux_11_TMR2 (SIU_DMAMUX_SRCSEL11_TMR2 << SIU_DMAMUX_SRCSEL11_Pos)   /*!< Выбор TMR2 в качестве источника запросов канала DMA 11 */
+#define DMA_ChannelMux_11_PWM1B (SIU_DMAMUX_SRCSEL11_PWM1B << SIU_DMAMUX_SRCSEL11_Pos) /*!< Выбор PWM1 B в качестве источника запросов канала DMA 11 */
+#define DMA_ChannelMux_12_TMR3 (SIU_DMAMUX_SRCSEL12_TMR3 << SIU_DMAMUX_SRCSEL12_Pos)   /*!< Выбор TMR3 в качестве источника запросов канала DMA 12 */
+#define DMA_ChannelMux_12_PWM0B (SIU_DMAMUX_SRCSEL12_PWM2B << SIU_DMAMUX_SRCSEL12_Pos) /*!< Выбор PWM0 B в качестве источника запросов канала DMA 12 */
+#define DMA_ChannelMux_13_PWM0A (SIU_DMAMUX_SRCSEL13_PWM0A << SIU_DMAMUX_SRCSEL13_Pos) /*!< Выбор PWM0 A в качестве источника запросов канала DMA 13 */
+#define DMA_ChannelMux_14_PWM1A (SIU_DMAMUX_SRCSEL14_PWM1A << SIU_DMAMUX_SRCSEL14_Pos) /*!< Выбор PWM1 A в качестве источника запросов канала DMA 14 */
+#define DMA_ChannelMux_15_PWM2A (SIU_DMAMUX_SRCSEL15_PWM2A << SIU_DMAMUX_SRCSEL15_Pos) /*!< Выбор PWM2 A в качестве источника запросов канала DMA 15 */
+
+/**
+   * @}
+   */
+
+/** @defgroup DMA_Channel_Define Маски каналов DMA
+   * @{
+   */
+
+/** @defgroup DMA_Channel_Num_Define Маски каналов по номеру
+  * @{
+  */
+
+#define DMA_Channel_0 0x00000001UL   /*!< Канал DMA 0 */
+#define DMA_Channel_1 0x00000002UL   /*!< Канал DMA 1 */
+#define DMA_Channel_2 0x00000004UL   /*!< Канал DMA 2 */
+#define DMA_Channel_3 0x00000008UL   /*!< Канал DMA 3 */
+#define DMA_Channel_4 0x00000010UL   /*!< Канал DMA 4 */
+#define DMA_Channel_5 0x00000020UL   /*!< Канал DMA 5 */
+#define DMA_Channel_6 0x00000040UL   /*!< Канал DMA 6 */
+#define DMA_Channel_7 0x00000080UL   /*!< Канал DMA 7 */
+#define DMA_Channel_8 0x00000100UL   /*!< Канал DMA 8 */
+#define DMA_Channel_9 0x00000200UL   /*!< Канал DMA 9 */
+#define DMA_Channel_10 0x00000400UL  /*!< Канал DMA 10 */
+#define DMA_Channel_11 0x00000800UL  /*!< Канал DMA 11 */
+#define DMA_Channel_12 0x00001000UL  /*!< Канал DMA 12 */
+#define DMA_Channel_13 0x00002000UL  /*!< Канал DMA 13 */
+#define DMA_Channel_14 0x00004000UL  /*!< Канал DMA 14 */
+#define DMA_Channel_15 0x00008000UL  /*!< Канал DMA 15 */
+#define DMA_Channel_16 0x00010000UL  /*!< Канал DMA 16 */
+#define DMA_Channel_All 0x0000FFFFUL /*!< Все каналы DMA */
+
+/**
+   * @}
+   */
+
+/** @defgroup DMA_Channel_Periph_Define Маски каналов по имени
+  * @{
+  */
+
+#define DMA_Channel_UART0_TX DMA_Channel_0 /*!< Канал DMA по передаче от UART0 */
+#define DMA_Channel_UART1_TX DMA_Channel_1 /*!< Канал DMA по передаче от UART1 */
+#define DMA_Channel_UART0_RX DMA_Channel_2 /*!< Канал DMA по приему от UART0 */
+#define DMA_Channel_UART1_RX DMA_Channel_3 /*!< Канал DMA по приему от UART1 */
+#define DMA_Channel_ADC_SEQ0 DMA_Channel_4 /*!< Канал DMA секвенсора 0 АЦП */
+#define DMA_Channel_ADC_SEQ1 DMA_Channel_5 /*!< Канал DMA секвенсора 1 АЦП */
+#define DMA_Channel_SPI_TX DMA_Channel_6   /*!< Канал DMA по передаче от SPI */
+#define DMA_Channel_SPI_RX DMA_Channel_7   /*!< Канал DMA по приему от SPI */
+#define DMA_Channel_PWM0_A DMA_Channel_13  /*!< Канал PWM0 A */
+#define DMA_Channel_PWM1_A DMA_Channel_14  /*!< Канал PWM1 A */
+#define DMA_Channel_PWM2_A DMA_Channel_15  /*!< Канал PWM2 A */
+#define DMA_Channel_PWM2_B DMA_Channel_12  /*!< Канал PWM2 B */
+#define DMA_Channel_PWM1_B DMA_Channel_11  /*!< Канал PWM1 B */
+#define DMA_Channel_PWM0_B DMA_Channel_10  /*!< Канал PWM0 B */
+#define DMA_Channel_TMR0 DMA_Channel_9     /*!< Канал TMR0 */
+#define DMA_Channel_TMR1 DMA_Channel_10    /*!< Канал TMR1 */
+#define DMA_Channel_TMR2 DMA_Channel_11    /*!< Канал TMR2 */
+#define DMA_Channel_TMR3 DMA_Channel_12    /*!< Канал TMR3 */
+#define DMA_Channel_QEP DMA_Channel_8      /*!< Канал QEP */
+#define DMA_Channel_GPIOA DMA_Channel_8    /*!< Канал GPIOA */
+#define DMA_Channel_GPIOB DMA_Channel_9    /*!< Канал GPIOB */
+
+/**
+  * @}
+  */
+
+#define IS_DMA_CHANNEL(VALUE) (((VALUE) != 0) && (((VALUE)&0xFFFF0000) == 0))
+
+#define IS_GET_DMA_CHANNEL(VALUE) (((VALUE) == (DMA_Channel_0)) ||  \
+                                   ((VALUE) == (DMA_Channel_1)) ||  \
+                                   ((VALUE) == (DMA_Channel_2)) ||  \
+                                   ((VALUE) == (DMA_Channel_3)) ||  \
+                                   ((VALUE) == (DMA_Channel_4)) ||  \
+                                   ((VALUE) == (DMA_Channel_5)) ||  \
+                                   ((VALUE) == (DMA_Channel_6)) ||  \
+                                   ((VALUE) == (DMA_Channel_7)) ||  \
+                                   ((VALUE) == (DMA_Channel_8)) ||  \
+                                   ((VALUE) == (DMA_Channel_9)) ||  \
+                                   ((VALUE) == (DMA_Channel_10)) || \
+                                   ((VALUE) == (DMA_Channel_11)) || \
+                                   ((VALUE) == (DMA_Channel_12)) || \
+                                   ((VALUE) == (DMA_Channel_13)) || \
+                                   ((VALUE) == (DMA_Channel_14)) || \
+                                   ((VALUE) == (DMA_Channel_15)))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Types Типы
+  * @{
+  */
+
+/**
+  * @brief Выбор режима работы DMA
+  */
+
+typedef enum {
+    DMA_Mode_Disable = DMA_CHANNEL_CFG_CYCLE_CTRL_Stop,                         /*!< Неактивное состояние */
+    DMA_Mode_Basic = DMA_CHANNEL_CFG_CYCLE_CTRL_Basic,                          /*!< Основной режим передачи */
+    DMA_Mode_AutoReq = DMA_CHANNEL_CFG_CYCLE_CTRL_AutoReq,                      /*!< Режим передачи с авто-запросом */
+    DMA_Mode_PingPong = DMA_CHANNEL_CFG_CYCLE_CTRL_PingPong,                    /*!< Режим передачи "пинг-понг" */
+    DMA_Mode_PrmMemScatGath = DMA_CHANNEL_CFG_CYCLE_CTRL_MemScatGathPrim,       /*!< Работа с памятью в режиме "разборка-сборка" с использованием первичной управляющей структуры */
+    DMA_Mode_AltMemScatGath = DMA_CHANNEL_CFG_CYCLE_CTRL_MemScatGathAlt,        /*!< Работа с памятью в режиме "разборка-сборка" с использованием альтернативной управляющей структуры */
+    DMA_Mode_PrmPeriphScatGath = DMA_CHANNEL_CFG_CYCLE_CTRL_PeriphScatGathPrim, /*!< Работа с периферией в режиме "разборка-сборка" с использованием первичной управляющей структуры */
+    DMA_Mode_AltPeriphScatGath = DMA_CHANNEL_CFG_CYCLE_CTRL_PeriphScatGathAlt   /*!< Работа с периферией в режиме "разборка-сборка" с использованием альтернативной управляющей структуры */
+} DMA_Mode_TypeDef;
+#define IS_DMA_MODE(VALUE) (((VALUE) == DMA_Mode_Disable) ||           \
+                            ((VALUE) == DMA_Mode_Basic) ||             \
+                            ((VALUE) == DMA_Mode_AutoReq) ||           \
+                            ((VALUE) == DMA_Mode_PingPong) ||          \
+                            ((VALUE) == DMA_Mode_PrmMemScatGath) ||    \
+                            ((VALUE) == DMA_Mode_AltMemScatGath) ||    \
+                            ((VALUE) == DMA_Mode_PrmPeriphScatGath) || \
+                            ((VALUE) == DMA_Mode_AltPeriphScatGath))
+
+/**
+   * @brief Выбор количества передач до выполнения переарбитрации
+   */
+typedef enum {
+    DMA_ArbitrationRate_1,   /*!< Переарбитрация каждую передачу DMA */
+    DMA_ArbitrationRate_2,   /*!< Переарбитрация каждые 2 передачи DMA */
+    DMA_ArbitrationRate_4,   /*!< Переарбитрация каждые 4 передачи DMA */
+    DMA_ArbitrationRate_8,   /*!< Переарбитрация каждые 8 передач DMA */
+    DMA_ArbitrationRate_16,  /*!< Переарбитрация каждые 16 передач DMA */
+    DMA_ArbitrationRate_32,  /*!< Переарбитрация каждые 32 передачи DMA */
+    DMA_ArbitrationRate_64,  /*!< Переарбитрация каждые 64 передачи DMA */
+    DMA_ArbitrationRate_128, /*!< Переарбитрация каждые 128 передач DMA */
+    DMA_ArbitrationRate_256, /*!< Переарбитрация каждые 256 передач DMA */
+    DMA_ArbitrationRate_512, /*!< Переарбитрация каждые 512 передач DMA */
+    DMA_ArbitrationRate_1024 /*!< Переарбитрация каждые 1024 передачи DMA */
+} DMA_ArbitrationRate_TypeDef;
+#define IS_DMA_ARBITRATION_RATE(VALUE) (((VALUE) == DMA_ArbitrationRate_1) ||   \
+                                        ((VALUE) == DMA_ArbitrationRate_2) ||   \
+                                        ((VALUE) == DMA_ArbitrationRate_4) ||   \
+                                        ((VALUE) == DMA_ArbitrationRate_8) ||   \
+                                        ((VALUE) == DMA_ArbitrationRate_16) ||  \
+                                        ((VALUE) == DMA_ArbitrationRate_32) ||  \
+                                        ((VALUE) == DMA_ArbitrationRate_64) ||  \
+                                        ((VALUE) == DMA_ArbitrationRate_128) || \
+                                        ((VALUE) == DMA_ArbitrationRate_256) || \
+                                        ((VALUE) == DMA_ArbitrationRate_512) || \
+                                        ((VALUE) == DMA_ArbitrationRate_1024))
+
+/**
+  * @brief  Разрядность данных источника или приемника
+  */
+typedef enum {
+    DMA_DataSize_8 = DMA_CHANNEL_CFG_SRC_SIZE_Byte,      /*!< Разрядность данных 8 бит */
+    DMA_DataSize_16 = DMA_CHANNEL_CFG_SRC_SIZE_Halfword, /*!< Разрядность данных 16 бит */
+    DMA_DataSize_32 = DMA_CHANNEL_CFG_SRC_SIZE_Word      /*!< Разрядность данных 32 бит */
+} DMA_DataSize_TypeDef;
+#define IS_DMA_DATA_SIZE(VALUE) (((VALUE) == DMA_DataSize_8) ||  \
+                                 ((VALUE) == DMA_DataSize_16) || \
+                                 ((VALUE) == DMA_DataSize_32))
+
+/**
+  * @brief  Шаг инкремента адреса источника при чтении или приемника при записи
+  */
+typedef enum {
+    DMA_DataInc_8 = DMA_CHANNEL_CFG_SRC_INC_Byte,      /*!< Инкремент данных 8 бит */
+    DMA_DataInc_16 = DMA_CHANNEL_CFG_SRC_INC_Halfword, /*!< Инкремент данных 16 бит */
+    DMA_DataInc_32 = DMA_CHANNEL_CFG_SRC_INC_Word,     /*!< Инкремент данных 32 бит */
+    DMA_DataInc_Disable = DMA_CHANNEL_CFG_SRC_INC_None /*!< Инкремент отсутствует */
+} DMA_DataInc_TypeDef;
+#define IS_DMA_DATA_INC(VALUE) (((VALUE) == DMA_DataInc_8) ||  \
+                                ((VALUE) == DMA_DataInc_16) || \
+                                ((VALUE) == DMA_DataInc_32) || \
+                                ((VALUE) == DMA_DataInc_Disable))
+
+/**
+  * @brief  Возможные состояния конечного автомата управления контроллером DMA
+  */
+typedef enum {
+    DMA_State_Free = DMA_STATUS_STATE_Free,                           /*!< В покое */
+    DMA_State_ReadConfigData = DMA_STATUS_STATE_ReadConfigData,       /*!< Чтение управляющих данных канала */
+    DMA_State_ReadSrcDataEndPtr = DMA_STATUS_STATE_ReadSrcDataEndPtr, /*!< Чтение указателя конца данных источника */
+    DMA_State_ReadDstDataEndPtr = DMA_STATUS_STATE_ReadDstDataEndPtr, /*!< Чтение указателя конца данных приемника */
+    DMA_State_ReadSrcData = DMA_STATUS_STATE_ReadSrcData,             /*!< Чтение данных источника */
+    DMA_State_WriteDstData = DMA_STATUS_STATE_WrireDstData,           /*!< Запись данных в приемник */
+    DMA_State_WaitReq = DMA_STATUS_STATE_WaitReq,                     /*!< Ожидание запроса на выполнение прямого доступа */
+    DMA_State_WriteConfigData = DMA_STATUS_STATE_WriteConfigData,     /*!< Запись управляющих данных канала */
+    DMA_State_Pause = DMA_STATUS_STATE_Pause,                         /*!< Приостановлен */
+    DMA_State_Done = DMA_STATUS_STATE_Done,                           /*!< Выполнен */
+    DMA_State_PeriphScatGath = DMA_STATUS_STATE_PeriphScatGath        /*!< Работа с периферией в режиме "разборка-сборка" */
+} DMA_State_TypeDef;
+#define IS_DMA_STATE(VALUE) (((VALUE) == DMA_State_Free) ||              \
+                             ((VALUE) == DMA_State_ReadConfigData) ||    \
+                             ((VALUE) == DMA_State_ReadSrcDataEndPtr) || \
+                             ((VALUE) == DMA_State_ReadDstDataEndPtr) || \
+                             ((VALUE) == DMA_State_ReadSrcData) ||       \
+                             ((VALUE) == DMA_State_WriteDstData) ||      \
+                             ((VALUE) == DMA_State_WaitReq) ||           \
+                             ((VALUE) == DMA_State_Pause) ||             \
+                             ((VALUE) == DMA_State_Done) ||              \
+                             ((VALUE) == DMA_State_PeriphScatGath))
+
+/**
+  * @brief  Защита шины при чтении из источника или записи в приемник через DMA
+  */
+typedef struct
+{
+    FunctionalState Priveleged; /*!< Управление привелегированным доступом */
+    FunctionalState Bufferable; /*!< Управление буфферизацией доступа */
+    FunctionalState Cacheable;  /*!< Управление кэшированием доступа */
+} DMA_Protect_TypeDef;
+
+/**
+  * @brief  Структура инициализации канала DMA
+  */
+typedef struct
+{
+    void* SrcDataEndPtr;                         /*!< Указатель конца данных источника */
+    void* DstDataEndPtr;                         /*!< Указатель конца данных приемника */
+    DMA_Mode_TypeDef Mode;                       /*!< Выбор режима работы DMA. */
+    FunctionalState NextUseburst;                /*!< Контроль установки соответсвующего каналу бита в регистре NT_DMA->CHNL_USEBURST_SET */
+    uint32_t TransfersTotal;                     /*!< Общее количество передач DMA.
+                                                      Параметр может принимать любое значение из диапазона 1-1024 */
+    DMA_ArbitrationRate_TypeDef ArbitrationRate; /*!< Выбор количества передач до выполнения переарбитрации */
+    DMA_Protect_TypeDef SrcProtect;              /*!< Защита шины при чтении из источника через DMA */
+    DMA_Protect_TypeDef DstProtect;              /*!< Защита шины при записи в приемник через DMA */
+    DMA_DataSize_TypeDef SrcDataSize;            /*!< Разрядность данных источника */
+    DMA_DataSize_TypeDef DstDataSize;            /*!< Разрядность данных приемника */
+    DMA_DataInc_TypeDef SrcDataInc;              /*!< Шаг инкремента адреса источника при чтении */
+    DMA_DataInc_TypeDef DstDataInc;              /*!< Шаг инкремента адреса приемника при записи */
+} DMA_ChannelInit_TypeDef;
+#define IS_DMA_TRANSFERS_TOTAL(VALUE) (((VALUE) <= 1024) && ((VALUE) >= 1))
+
+/**
+  * @brief  Структура инициализации контроллера DMA
+  */
+typedef struct
+{
+    uint32_t Channel;                /*!< Определяет каналы, которые будут настроены.
+                                          Параметр может принимать значение любой комбинации масок DMA_Channel_x из @ref DMA_Channel_Define. */
+    DMA_Protect_TypeDef CtrlProtect; /*!< Управление защитой шины при обращении DMA к управляющим данным */
+    FunctionalState UseBurst;        /*!< Установка пакетного обмена каналов DMA */
+    FunctionalState ReqMask;         /*!< Маскирование (игнорирование) запросов от периферии на обслуживание каналов DMA */
+    FunctionalState AltCtrl;         /*!< Установка альтернативной управляющей структуры каналов DMA */
+    FunctionalState HighPriority;    /*!< Установка высокого приоритета каналов DMA */
+    FunctionalState ChannelEnable;   /*!< Разрешение работы каналов DMA */
+} DMA_Init_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Functions Функции
+  * @{
+  */
+
+/**
+  * @brief   Настройка запросов периферии для мультиплексируемых каналов 8-15
+  * @param   MuxNum  Номера каналов. Любое сочетание значений DMA_ChannelMux_N (@ref DMA_ChannelMux_Define)
+  * @param   MuxSel  Выбор источников. Любое сочетание значений из DMA_ChannelMux_N_x (@ref DMA_ChannelMux_Sel_Define)
+  * @retval  void
+  */
+__STATIC_INLINE void DMA_ChannelMuxConfig(uint32_t MuxNum, uint32_t MuxSel)
+{
+    assert_param(IS_DMA_CHANNEL_MUX_NUM(MuxNum));
+
+    MODIFY_REG(SIU->DMAMUX, MuxNum, MuxSel);
+}
+
+/** @defgroup DMA_Exported_Functions_Init_Channel Инициализация каналов DMA
+  * @{
+  */
+
+void DMA_ChannelDeInit(DMA_Channel_TypeDef* ChannelStruct);
+void DMA_ChannelInit(DMA_Channel_TypeDef* ChannelStruct, DMA_ChannelInit_TypeDef* ChannelInitStruct);
+void DMA_ChannelStructInit(DMA_ChannelInit_TypeDef* ChannelInitStruct);
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Functions_Init Инициализация контроллера DMA
+  * @{
+  */
+
+void DMA_DeInit(void);
+void DMA_Init(DMA_Init_TypeDef* InitStruct);
+void DMA_StructInit(DMA_Init_TypeDef* InitStruct);
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Functions_Config Конфигурация контроллера DMA
+  * @{
+  */
+
+/**
+  * @brief   Установка базового адреса управляющих каналов
+  * @param   BasePtr  Значение базового адреса
+  * @retval  void
+  */
+__STATIC_INLINE void DMA_BasePtrConfig(uint32_t BasePtr)
+{
+    WRITE_REG(DMA->BASEPTR, BasePtr);
+}
+
+/**
+  * @brief   Управление защитой шины при обращении контроллера DMA к управляющим данным
+  * @param   CtrlProtect  Структура, содержащая конфигурацию защиты
+  * @retval  void
+  */
+__STATIC_INLINE void DMA_ProtectConfig(DMA_Protect_TypeDef* CtrlProtect)
+{
+    assert_param(IS_FUNCTIONAL_STATE(CtrlProtect->Bufferable));
+    assert_param(IS_FUNCTIONAL_STATE(CtrlProtect->Cacheable));
+    assert_param(IS_FUNCTIONAL_STATE(CtrlProtect->Priveleged));
+
+    MODIFY_REG(DMA->CFG, DMA_CFG_CHPROT_Msk, ((CtrlProtect->Priveleged << (DMA_CFG_CHPROT_Pos + 0)) |
+                                              (CtrlProtect->Bufferable << (DMA_CFG_CHPROT_Pos + 1)) |
+                                              (CtrlProtect->Cacheable << (DMA_CFG_CHPROT_Pos + 2))));
+}
+
+/**
+  * @brief      Разрешения работы контроллера DMA
+  * @attention  Прежде чем включать DMA, необходимо проинициализоровать каналы
+  *             с помощью @ref DMA_ChannelInit и сконфигурировать контроллер DMA через функцию
+  *             инициализации @ref DMA_Init или вручную - @ref DMA_Exported_Functions_Config.
+  * @param      State  Выбор состояния
+  * @retval     void
+  */
+__STATIC_INLINE void DMA_MasterEnableCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(DMA->CFG_bit.MASTEREN, State);
+}
+
+/**
+  * @brief   Программный запрос на осуществление передач DMA по выбранным каналам
+  * @param   Channel  Выбор канала.
+  *                   Параметр принимает любую комбинацию масок DMA_Channel_x из @ref DMA_Channel_Define.
+  * @retval  void
+  */
+__STATIC_INLINE void DMA_SwRequestCmd(uint32_t Channel)
+{
+    assert_param(IS_DMA_CHANNEL(Channel));
+
+    WRITE_REG(DMA->SWREQ, Channel);
+}
+
+/**
+  * @brief   Установка пакетного обмена каналов DMA
+  * @param   Channel  Выбор канала.
+  *                   Параметр принимает любую комбинацию масок DMA_Channel_x из @ref DMA_Channel_Define.
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void DMA_UseBurstCmd(uint32_t Channel, FunctionalState State)
+{
+    assert_param(IS_DMA_CHANNEL(Channel));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    if (State == ENABLE)
+        WRITE_REG(DMA->USEBURSTSET, Channel);
+    else
+        WRITE_REG(DMA->USEBURSTCLR, Channel);
+}
+
+/**
+  * @brief      Маскирование каналов DMA
+  * @attention  По маскированным каналам игнорируются запросы на передачи
+  * @param      Channel  Выбор канала
+  *                      Параметр принимает любую комбинацию масок DMA_Channel_x из @ref DMA_Channel_Define.
+  * @param      State  Выбор состояния
+  * @retval     void
+  */
+__STATIC_INLINE void DMA_ReqMaskCmd(uint32_t Channel, FunctionalState State)
+{
+    assert_param(IS_DMA_CHANNEL(Channel));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    if (State == ENABLE)
+        WRITE_REG(DMA->REQMASKSET, Channel);
+    else
+        WRITE_REG(DMA->REQMASKCLR, Channel);
+}
+
+/**
+  * @brief   Активация каналов DMA
+  * @param   Channel  Выбор канала
+  *                   Параметр принимает любую комбинацию масок DMA_Channel_x из @ref DMA_Channel_Define.
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void DMA_ChannelEnableCmd(uint32_t Channel, FunctionalState State)
+{
+    assert_param(IS_DMA_CHANNEL(Channel));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    if (State == ENABLE)
+        WRITE_REG(DMA->ENSET, Channel);
+    else
+        WRITE_REG(DMA->ENCLR, Channel);
+}
+
+/**
+  * @brief   Установка альтернативной управляющей структуры каналов DMA
+  * @param   Channel  Выбор канала.
+  *                   Параметр принимает любую комбинацию масок DMA_Channel_x из @ref DMA_Channel_Define.
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void DMA_AltCtrlCmd(uint32_t Channel, FunctionalState State)
+{
+    assert_param(IS_DMA_CHANNEL(Channel));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    if (State == ENABLE)
+        WRITE_REG(DMA->PRIALTSET, Channel);
+    else
+        WRITE_REG(DMA->PRIALTCLR, Channel);
+}
+
+/**
+  * @brief   Установка высокого приоритета каналов DMA
+  * @param   Channel  Выбор канала.
+  *                   Параметр принимает любую комбинацию масок DMA_Channel_x из @ref DMA_Channel_Define.
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void DMA_HighPriorityCmd(uint32_t Channel, FunctionalState State)
+{
+    assert_param(IS_DMA_CHANNEL(Channel));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    if (State == ENABLE)
+        WRITE_REG(DMA->PRIORITYSET, Channel);
+    else
+        WRITE_REG(DMA->PRIORITYCLR, Channel);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Functions_Status Статусная информация
+  * @{
+  */
+
+/**
+  * @brief   Доступ к текущему конечного автомата контроллера DMA
+  * @retval  State  Текущее состояние конечного автомата
+  */
+__STATIC_INLINE DMA_State_TypeDef DMA_StateStatus(void)
+{
+    return (DMA_State_TypeDef)READ_REG(DMA->STATUS_bit.STATE);
+}
+
+/**
+  * @brief   Состояние контроллера DMA
+  * @retval  State  Текущее состояние контроллера DMA
+  */
+__STATIC_INLINE FunctionalState DMA_MasterEnableStatus(void)
+{
+    return (FunctionalState)READ_BIT(DMA->STATUS, DMA_STATUS_MASTEREN_Msk);
+}
+
+/**
+  * @brief   Состояние канала DMA
+  * @param   Channel  Выбор канала
+  * @retval  State  Текущее состояние контроллера DMA
+  */
+__STATIC_INLINE FunctionalState DMA_ChannelEnableStatus(uint32_t Channel)
+{
+    assert_param(IS_GET_DMA_CHANNEL(Channel));
+
+    return (FunctionalState)READ_BIT(DMA->ENSET, Channel);
+}
+
+/**
+  * @brief   Показывает поддерживает ли канал одиночные SREQ запросы
+  * @param   Channel  Выбор канала
+  * @retval  State  Одно из значений @ref FunctionalState:
+  *                 - ENABLE - поддерживаются SREQ (как и блочные BREQ);
+  *                 - DISABLE - поддерживаются только блочные запросы BREQ.
+  */
+__STATIC_INLINE FunctionalState DMA_WaitOnReqStatus(uint32_t Channel)
+{
+    assert_param(IS_GET_DMA_CHANNEL(Channel));
+
+    return (FunctionalState)READ_BIT(DMA->WAITONREQ, Channel);
+}
+
+/**
+  * @brief   Показывает наличие ошибки на шине
+  * @retval  Status  Одно из значений @ref OperationStatus:
+  *                  - OK - ошибок не было;
+  *                  - ERROR - произошла ошибка.
+  */
+__STATIC_INLINE OperationStatus DMA_ErrorStatus(void)
+{
+    return (OperationStatus)READ_BIT(DMA->ERRCLR, DMA_ERRCLR_VAL_Msk);
+}
+
+/**
+  * @brief   Сброс флага ошибки на шине
+  * @retval  void
+  */
+__STATIC_INLINE void DMA_ClearErrorStatus(void)
+{
+    WRITE_REG(DMA->ERRCLR, DMA_ERRCLR_VAL_Msk);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PLIB035_DMA_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2018 NIIET *****END OF FILE****/

platform/plib035/inc/plib035_ecap.h

@@ -0,0 +1,910 @@
+/**
+  ******************************************************************************
+  * @file    plib035_ecap.h
+  *
+  * @brief   Файл содержит прототипы и компактные inline реализации функций для
+  *          ECAP, а также сопутствующие макроопределения и перечисления
+  *
+  * @author  НИИЭТ, Богдан Колбов <kolbov@niiet.ru>
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ ПРЕДОСТАВЛЯЕТСЯ «КАК ЕСТЬ», БЕЗ КАКИХ-ЛИБО
+  * ГАРАНТИЙ, ЯВНО ВЫРАЖЕННЫХ ИЛИ ПОДРАЗУМЕВАЕМЫХ, ВКЛЮЧАЯ ГАРАНТИИ ТОВАРНОЙ
+  * ПРИГОДНОСТИ, СООТВЕТСТВИЯ ПО ЕГО КОНКРЕТНОМУ НАЗНАЧЕНИЮ И ОТСУТСТВИЯ
+  * НАРУШЕНИЙ, НО НЕ ОГРАНИЧИВАЯСЬ ИМИ. ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ
+  * ПРЕДНАЗНАЧЕНО ДЛЯ ОЗНАКОМИТЕЛЬНЫХ ЦЕЛЕЙ И НАПРАВЛЕНО ТОЛЬКО НА
+  * ПРЕДОСТАВЛЕНИЕ ДОПОЛНИТЕЛЬНОЙ ИНФОРМАЦИИ О ПРОДУКТЕ, С ЦЕЛЬЮ СОХРАНИТЬ ВРЕМЯ
+  * ПОТРЕБИТЕЛЮ. НИ В КАКОМ СЛУЧАЕ АВТОРЫ ИЛИ ПРАВООБЛАДАТЕЛИ НЕ НЕСУТ
+  * ОТВЕТСТВЕННОСТИ ПО КАКИМ-ЛИБО ИСКАМ, ЗА ПРЯМОЙ ИЛИ КОСВЕННЫЙ УЩЕРБ, ИЛИ
+  * ПО ИНЫМ ТРЕБОВАНИЯМ, ВОЗНИКШИМ ИЗ-ЗА ИСПОЛЬЗОВАНИЯ ПРОГРАММНОГО ОБЕСПЕЧЕНИЯ
+  * ИЛИ ИНЫХ ДЕЙСТВИЙ С ПРОГРАММНЫМ ОБЕСПЕЧЕНИЕМ.
+  *
+  * <h2><center>&copy; 2018 ОАО "НИИЭТ"</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PLIB035_ECAP_H
+#define __PLIB035_ECAP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "plib035.h"
+
+/** @addtogroup Peripheral
+  * @{
+  */
+
+/** @defgroup ECAP
+  * @brief Драйвер для работы с ECAP
+  * @{
+  */
+
+/** @defgroup ECAP_Exported_Defines Константы
+  * @{
+  */
+
+/** @defgroup ECAP_ITStatus_Define Флаги прерываний
+  * @{
+  */
+
+#define ECAP_ITStatus_GeneralInt ECAP_ECFLG_INT_Msk        /*!< Общее прерывание */
+#define ECAP_ITStatus_CapEvt0 ECAP_ECFLG_CEVT0_Msk         /*!< Событие захвата 0 */
+#define ECAP_ITStatus_CapEvt1 ECAP_ECFLG_CEVT1_Msk         /*!< Событие захвата 1 */
+#define ECAP_ITStatus_CapEvt2 ECAP_ECFLG_CEVT2_Msk         /*!< Событие захвата 2 */
+#define ECAP_ITStatus_CapEvt3 ECAP_ECFLG_CEVT3_Msk         /*!< Событие захвата 3 */
+#define ECAP_ITStatus_TimerOvf ECAP_ECFLG_CTROVF_Msk       /*!< Переполнение счетчика таймера */
+#define ECAP_ITStatus_TimerEqPeriod ECAP_ECFLG_CTRPRD_Msk  /*!< Счетчик таймера равен периоду (в режиме ШИМ) */
+#define ECAP_ITStatus_TimerEqCompare ECAP_ECFLG_CTRCMP_Msk /*!< Счетчик таймера равен значению сравнения (в режиме ШИМ) */
+#define ECAP_ITStatus_All (ECAP_ITStatus_GeneralInt |    \
+                           ECAP_ITStatus_CapEvt0 |       \
+                           ECAP_ITStatus_CapEvt1 |       \
+                           ECAP_ITStatus_CapEvt2 |       \
+                           ECAP_ITStatus_CapEvt3 |       \
+                           ECAP_ITStatus_TimerOvf |      \
+                           ECAP_ITStatus_TimerEqPeriod | \
+                           ECAP_ITStatus_TimerEqCompare) /*!< Все флаги выбраны */
+
+#define IS_ECAP_IT_STATUS(VALUE) (((VALUE) & ~ECAP_ITStatus_All) == 0)
+
+/**
+  * @}
+  */
+
+/** @defgroup ECAP_ITSource_Define Маски источников прерываний
+  * @{
+  */
+
+#define ECAP_ITSource_CapEvt0 ECAP_ECEINT_CEVT0_Msk         /*!< Событие захвата 0 */
+#define ECAP_ITSource_CapEvt1 ECAP_ECEINT_CEVT1_Msk         /*!< Событие захвата 1 */
+#define ECAP_ITSource_CapEvt2 ECAP_ECEINT_CEVT2_Msk         /*!< Событие захвата 2 */
+#define ECAP_ITSource_CapEvt3 ECAP_ECEINT_CEVT3_Msk         /*!< Событие захвата 3 */
+#define ECAP_ITSource_TimerOvf ECAP_ECEINT_CTROVF_Msk       /*!< Переполнение счетчика таймера */
+#define ECAP_ITSource_TimerEqPeriod ECAP_ECEINT_CTRPRD_Msk  /*!< Счетчик таймера равен периоду (в режиме ШИМ) */
+#define ECAP_ITSource_TimerEqCompare ECAP_ECEINT_CTRCMP_Msk /*!< Счетчик таймера равен значению сравнения (в режиме ШИМ) */
+#define ECAP_ITSource_All (ECAP_ITSource_CapEvt0 |       \
+                           ECAP_ITSource_CapEvt1 |       \
+                           ECAP_ITSource_CapEvt2 |       \
+                           ECAP_ITSource_CapEvt3 |       \
+                           ECAP_ITSource_TimerOvf |      \
+                           ECAP_ITSource_TimerEqPeriod | \
+                           ECAP_ITSource_TimerEqCompare) /*!< Все источники выбраны */
+
+#define IS_ECAP_IT_SOURCE(VALUE) (((VALUE) & ~ECAP_ITSource_All) == 0)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ECAP_Exported_Types Типы
+  * @{
+  */
+
+/**
+  * @brief  Выбор фронта захвата
+  */
+typedef enum {
+    ECAP_Capture_Polarity_PosEdge, /*!< Захват по переднему фронту */
+    ECAP_Capture_Polarity_NegEdge  /*!< Захват по заднему фронту */
+} ECAP_Capture_Polarity_TypeDef;
+#define IS_ECAP_CAPTURE_POLARITY(VALUE) (((VALUE) == ECAP_Capture_Polarity_PosEdge) || \
+                                         ((VALUE) == ECAP_Capture_Polarity_NegEdge))
+
+/**
+  * @brief  Выбор режима остановки таймера при отладке
+  */
+typedef enum {
+    ECAP_Halt_Stop = ECAP_ECCTL0_FREESOFT_Stop,             /*!< Мгновенная остановка таймера при отладке */
+    ECAP_Halt_StopOnZero = ECAP_ECCTL0_FREESOFT_StopAtZero, /*!< Остановка таймера при переполнении или сбросе (событие достижения 0) */
+    ECAP_Halt_Free = ECAP_ECCTL0_FREESOFT_Free              /*!< Нормальный режим */
+} ECAP_Halt_TypeDef;
+#define IS_ECAP_HALT(VALUE) (((VALUE) == ECAP_Halt_Stop) ||       \
+                             ((VALUE) == ECAP_Halt_StopOnZero) || \
+                             ((VALUE) == ECAP_Halt_Free))
+
+/**
+  * @brief  Выбор источника выходного сигнала синхронизации
+  */
+typedef enum {
+    ECAP_SyncOut_Bypass = ECAP_ECCTL1_SYNCOSEL_Bypass,          /*!< Пропуск синхросигнала со входа на выход */
+    ECAP_SyncOut_TimerEqPeriod = ECAP_ECCTL1_SYNCOSEL_CTREqPrd, /*!< Передача события равенства таймера и значения периода в качестве выходного сигнала синхронизации */
+    ECAP_SyncOut_Disable = ECAP_ECCTL1_SYNCOSEL_Disable         /*!< Выходной сигнал синхронизации запрещен */
+} ECAP_SyncOut_TypeDef;
+#define IS_ECAP_SYNC_OUT(VALUE) (((VALUE) == ECAP_SyncOut_Bypass) ||        \
+                                 ((VALUE) == ECAP_SyncOut_TimerEqPeriod) || \
+                                 ((VALUE) == ECAP_SyncOut_Disable))
+
+/**
+  * @brief  Выбор режима работы захвата
+  */
+typedef enum {
+    ECAP_Capture_Mode_Cycle, /*!< Цикличный захват */
+    ECAP_Capture_Mode_Single /*!< Однократный захват */
+} ECAP_Capture_Mode_TypeDef;
+#define IS_ECAP_CAPTURE_MODE(VALUE) (((VALUE) == ECAP_Capture_Mode_Single) || \
+                                     ((VALUE) == ECAP_Capture_Mode_Cycle))
+
+/**
+  * @brief  Выбор активного уровня в режиме ШИМ
+  */
+typedef enum {
+    ECAP_PWM_Polarity_Pos, /*!< Высокий уровень является активным */
+    ECAP_PWM_Polarity_Neg  /*!< Низкий уровень является активным */
+} ECAP_PWM_Polarity_TypeDef;
+#define IS_ECAP_PWM_POLARITY(VALUE) (((VALUE) == ECAP_PWM_Polarity_Pos) || \
+                                     ((VALUE) == ECAP_PWM_Polarity_Neg))
+
+/**
+  * @brief  Выбор режима работы блока захвата
+  */
+typedef enum {
+    ECAP_Mode_Capture, /*!< Режим захвата */
+    ECAP_Mode_PWM      /*!< Режим ШИМ */
+} ECAP_Mode_TypeDef;
+#define IS_ECAP_MODE(VALUE) (((VALUE) == ECAP_Mode_Capture) || \
+                             ((VALUE) == ECAP_Mode_PWM))
+
+/**
+  * @brief  Структура инициализации блока захвата в целом
+  */
+typedef struct
+{
+    ECAP_Halt_TypeDef Halt;       /*!< Выбор режима остановки таймера при отладке */
+    FunctionalState SyncEn;       /*!< Определеяет возможность синхронизации */
+    ECAP_SyncOut_TypeDef SyncOut; /*!< Выбор источника выходного сигнала синхронизации */
+    ECAP_Mode_TypeDef Mode;       /*!< Выбор режима работы блока захвата */
+} ECAP_Init_TypeDef;
+
+/**
+  * @brief  Структура инициализации режима захвата
+  */
+typedef struct
+{
+    uint32_t Prescale;                          /*!< Предварительный делитель событий.
+                                                     Параметр может принимать любое значение из диапазона 0-63. 0 - делитель выключен. */
+    ECAP_Capture_Mode_TypeDef Mode;             /*!< Определеяет режим работы захвата */
+    uint32_t StopVal;                           /*!< Значение счетчика событий для остановки одиночного режима захвата.
+                                                     Параметр может принимать любое значение из диапазона 0-3. */
+    FunctionalState RstEvt0;                    /*!< Определеяет сброс таймера после события захвата 0 */
+    FunctionalState RstEvt1;                    /*!< Определеяет сброс таймера после события захвата 1 */
+    FunctionalState RstEvt2;                    /*!< Определеяет сброс таймера после события захвата 2 */
+    FunctionalState RstEvt3;                    /*!< Определеяет сброс таймера после события захвата 3 */
+    ECAP_Capture_Polarity_TypeDef PolarityEvt0; /*!< Определеяет фронт события захвата 0 */
+    ECAP_Capture_Polarity_TypeDef PolarityEvt1; /*!< Определеяет фронт события захвата 1 */
+    ECAP_Capture_Polarity_TypeDef PolarityEvt2; /*!< Определеяет фронт события захвата 2 */
+    ECAP_Capture_Polarity_TypeDef PolarityEvt3; /*!< Определеяет фронт события захвата 3 */
+} ECAP_Capture_Init_TypeDef;
+#define IS_ECAP_CAPTURE_PRESCALE(VALUE) ((VALUE) < 0x40)
+#define IS_ECAP_CAPTURE_STOP(VALUE) ((VALUE) < 0x4)
+
+/**
+  * @brief  Структура инициализации режима ШИМ
+  */
+typedef struct
+{
+    uint32_t Period;                    /*!< Значение периода ШИМ.
+                                             Параметр может принимать любое значение из диапазона 0x00000000-0xFFFFFFFF. */
+    uint32_t Compare;                   /*!< Значение сравнения ШИМ.
+                                             Параметр может принимать любое значение из диапазона 0x00000000-0xFFFFFFFF. */
+    ECAP_PWM_Polarity_TypeDef Polarity; /*!< Выбор полярности ШИМ сигнала */
+} ECAP_PWM_Init_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup ECAP_Exported_Functions Функции
+  * @{
+  */
+
+/** @defgroup CAP_Config Конфигурация
+  * @{
+  */
+
+void ECAP_DeInit(ECAP_TypeDef* ECAPx);
+void ECAP_Init(ECAP_TypeDef* ECAPx, ECAP_Init_TypeDef* InitStruct);
+void ECAP_StructInit(ECAP_Init_TypeDef* InitStruct);
+
+/**
+  * @brief   Разрешение работы вывода блока захвата
+  * @param   ECAPx  Выбор модуля ECAP, где x лежит в диапазоне 0-2
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_RemapCmd(ECAP_TypeDef* ECAPx, FunctionalState State)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    if (ECAPx == ECAP0)
+        WRITE_REG(SIU->REMAPAF_bit.ECAP0EN, State);
+    else if (ECAPx == ECAP1)
+        WRITE_REG(SIU->REMAPAF_bit.ECAP1EN, State);
+    else /* (ECAPx == ECAP2) */
+        WRITE_REG(SIU->REMAPAF_bit.ECAP2EN, State);
+}
+
+/**
+  * @brief   Настройка режима остановки таймера при отладке
+  * @param   ECAPx  Выбор модуля ECAP, где x лежит в диапазоне 0-2
+  * @param   Halt  Выбор режима
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_HaltConfig(ECAP_TypeDef* ECAPx, ECAP_Halt_TypeDef Halt)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+    assert_param(IS_ECAP_HALT(Halt));
+
+    WRITE_REG(ECAPx->ECCTL0_bit.FREESOFT, Halt);
+}
+
+/**
+  * @brief   Настройка режима работы блока захвата
+  * @param   ECAPx  Выбор модуля ECAP, где x лежит в диапазоне 0-2
+  * @param   Mode  Выбор режима
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_ModeConfig(ECAP_TypeDef* ECAPx, ECAP_Mode_TypeDef Mode)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+    assert_param(IS_ECAP_MODE(Mode));
+
+    WRITE_REG(ECAPx->ECCTL1_bit.CAPAPWM, Mode);
+}
+
+/**
+  * @brief   Разрешение работы таймера, выбранного блока захвата
+  * @param   ECAPx  Выбор модуля ECAP, где x лежит в диапазоне 0-2
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_TimerCmd(ECAP_TypeDef* ECAPx, FunctionalState State)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(ECAPx->ECCTL1_bit.TSCTRSTOP, State);
+}
+
+/**
+  * @brief   Установка текущего значения счетчика напрямую
+  * @param   ECAPx  Выбор модуля ECAP, где x лежит в диапазоне 0-2
+  * @param   TimerVal  Значение таймера
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_SetTimer(ECAP_TypeDef* ECAPx, uint32_t TimerVal)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+
+    WRITE_REG(ECAPx->TSCTR, TimerVal);
+}
+
+/**
+  * @brief   Установка теневого значения таймера для отложенной записи
+  * @param   ECAPx  Выбор модуля ECAP, где x лежит в диапазоне 0-2
+  * @param   TimerVal  Значение таймера
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_SetShadowTimer(ECAP_TypeDef* ECAPx, uint32_t TimerVal)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+
+    WRITE_REG(ECAPx->CTRPHS, TimerVal);
+}
+
+/**
+  * @brief   Получение текущего значения таймера
+  * @param   ECAPx  Выбор ECAP, где x лежит в диапазоне 0-2
+  * @retval  Val  Значение таймера
+  */
+__STATIC_INLINE uint32_t ECAP_GetTimer(ECAP_TypeDef* ECAPx)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+
+    return READ_REG(ECAPx->TSCTR);
+}
+
+/**
+  * @brief   Получение отложенного значения таймера
+  * @param   ECAPx  Выбор ECAP, где x лежит в диапазоне 0-2
+  * @retval  Val  Значение таймера
+  */
+__STATIC_INLINE uint32_t ECAP_GetShadowTimer(ECAP_TypeDef* ECAPx)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+
+    return READ_REG(ECAPx->CTRPHS);
+}
+
+/**
+  * @brief   Настройка источника выходного сигнала синхронизации
+  * @param   ECAPx  Выбор модуля ECAP, где x лежит в диапазоне 0-2
+  * @param   SyncOut  Выбор режима
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_SyncOutConfig(ECAP_TypeDef* ECAPx, ECAP_SyncOut_TypeDef SyncOut)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+    assert_param(IS_ECAP_SYNC_OUT(SyncOut));
+
+    WRITE_REG(ECAPx->ECCTL1_bit.SYNCOSEL, SyncOut);
+}
+
+/**
+  * @brief   Разрешение синхронизации
+  * @param   ECAPx  Выбор модуля CAP, где x лежит в диапазоне 0-2
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_SyncCmd(ECAP_TypeDef* ECAPx, FunctionalState State)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(ECAPx->ECCTL1_bit.SYNCIEN, State);
+}
+
+/**
+  * @brief   Проведение программной синхронизации
+  * @param   ECAPx  Выбор модуля ECAP, где x лежит в диапазоне 0-2
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_SwSync(ECAP_TypeDef* ECAPx)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+
+    WRITE_REG(ECAPx->ECCTL1_bit.SWSYNC, 1);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CAP_Config_PWM_Mode Режим ШИМ
+  * @{
+  */
+
+void ECAP_PWM_Init(ECAP_TypeDef* ECAPx, ECAP_PWM_Init_TypeDef* InitStruct);
+void ECAP_PWM_StructInit(ECAP_PWM_Init_TypeDef* InitStruct);
+
+/**
+  * @brief   Настройка полярности ШИМ сигнала
+  * @param   ECAPx  Выбор модуля ECAP, где x лежит в диапазоне 0-2
+  * @param   Polarity  Выбор режима
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_PWM_PolarityConfig(ECAP_TypeDef* ECAPx, ECAP_PWM_Polarity_TypeDef Polarity)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+    assert_param(IS_ECAP_PWM_POLARITY(Polarity));
+
+    WRITE_REG(ECAPx->ECCTL1_bit.APWMPOL, Polarity);
+}
+
+/**
+  * @brief   Установка значения периода ШИМ
+  * @param   ECAPx  Выбор ECAP, где x лежит в диапазоне 0-2
+  * @param   PeriodVal  Значение периода
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_PWM_SetPeriod(ECAP_TypeDef* ECAPx, uint32_t PeriodVal)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+
+    WRITE_REG(ECAPx->PRD, PeriodVal);
+}
+
+/**
+  * @brief   Установка значения сравнения ШИМ.
+  * @param   ECAPx  Выбор ECAP, где x лежит в диапазоне 0-2
+  * @param   CompareVal  Значение сравнения.
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_PWM_SetCompare(ECAP_TypeDef* ECAPx, uint32_t CompareVal)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+
+    WRITE_REG(ECAPx->CMP, CompareVal);
+}
+
+/**
+  * @brief   Установка значения периода ШИМ для отложенной записи
+  * @param   ECAPx  Выбор ECAP, где x лежит в диапазоне 0-2
+  * @param   PeriodVal  Значение периода
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_PWM_SetShadowPeriod(ECAP_TypeDef* ECAPx, uint32_t PeriodVal)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+
+    WRITE_REG(ECAPx->PRDSHDW, PeriodVal);
+}
+
+/**
+  * @brief   Установка значения сравнения ШИМ для отложенной записи
+  * @param   ECAPx  Выбор ECAP, где x лежит в диапазоне 0-2
+  * @param   CompareVal  Значение сравнения
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_PWM_SetShadowCompare(ECAP_TypeDef* ECAPx, uint32_t CompareVal)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+
+    WRITE_REG(ECAPx->CMPSHDW, CompareVal);
+}
+
+/**
+  * @brief   Получение текущего периода ШИМ
+  * @param   ECAPx  Выбор ECAP, где x лежит в диапазоне 0-2
+  * @retval  Val  Значение периода
+  */
+__STATIC_INLINE uint32_t ECAP_PWM_GetPeriod(ECAP_TypeDef* ECAPx)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+
+    return READ_REG(ECAPx->PRD);
+}
+
+/**
+  * @brief   Получение текущего значения сравнения ШИМ
+  * @param   ECAPx  Выбор ECAP, где x лежит в диапазоне 0-2
+  * @retval  Val  Значение сравнения
+  */
+__STATIC_INLINE uint32_t ECAP_PWM_GetCompare(ECAP_TypeDef* ECAPx)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+
+    return READ_REG(ECAPx->CMP);
+}
+
+/**
+  * @brief   Получение отложенного значения периода ШИМ
+  * @param   ECAPx  Выбор ECAP, где x лежит в диапазоне 0-2
+  * @retval  Val  Значение периода
+  */
+__STATIC_INLINE uint32_t ECAP_PWM_GetShadowPeriod(ECAP_TypeDef* ECAPx)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+
+    return READ_REG(ECAPx->PRDSHDW);
+}
+
+/**
+  * @brief   Получение отложенного значения сравнения ШИМ
+  * @param   ECAPx  Выбор ECAP, где x лежит в диапазоне 0-2
+  * @retval  Val  Значение сравнения
+  */
+__STATIC_INLINE uint32_t ECAP_PWM_GetShadowCompare(ECAP_TypeDef* ECAPx)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+
+    return READ_REG(ECAPx->CMPSHDW);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CAP_Config_CAP_Mode Режим захвата
+  * @{
+  */
+
+void ECAP_Capture_Init(ECAP_TypeDef* ECAPx, ECAP_Capture_Init_TypeDef* InitStruct);
+void ECAP_Capture_StructInit(ECAP_Capture_Init_TypeDef* InitStruct);
+
+/**
+  * @brief   Настройка режима захвата
+  * @param   ECAPx  Выбор модуля ECAP, где x лежит в диапазоне 0-2
+  * @param   Mode  Выбор режима
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_Capture_ModeConfig(ECAP_TypeDef* ECAPx, ECAP_Capture_Mode_TypeDef Mode)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+    assert_param(IS_ECAP_CAPTURE_MODE(Mode));
+
+    WRITE_REG(ECAPx->ECCTL1_bit.CONTOST, Mode);
+}
+
+/**
+  * @brief   Настройка счетчика событий для остановки одиночного режима захвата
+  * @param   ECAPx  Выбор модуля ECAP, где x лежит в диапазоне 0-2
+  * @param   StopVal  Значение
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_Capture_StopConfig(ECAP_TypeDef* ECAPx, uint32_t StopVal)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+    assert_param(IS_ECAP_CAPTURE_STOP(StopVal));
+
+    WRITE_REG(ECAPx->ECCTL1_bit.STOPWRAP, StopVal);
+}
+
+/**
+  * @brief   Настройка предварительного делителя событий
+  * @param   ECAPx  Выбор модуля ECAP, где x лежит в диапазоне 0-2
+  * @param   PrescaleVal  Значение
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_Capture_PrescaleConfig(ECAP_TypeDef* ECAPx, uint32_t PrescaleVal)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+    assert_param(IS_ECAP_CAPTURE_PRESCALE(PrescaleVal));
+
+    WRITE_REG(ECAPx->ECCTL0_bit.PRESCALE, PrescaleVal);
+}
+
+/**
+  * @brief   Настройка фронта события захвата 0
+  * @param   ECAPx  Выбор модуля ECAP, где x лежит в диапазоне 0-2
+  * @param   Polarity  Значение режима
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_Capture_PolarityEvt0Config(ECAP_TypeDef* ECAPx, ECAP_Capture_Polarity_TypeDef Polarity)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+    assert_param(IS_ECAP_CAPTURE_POLARITY(Polarity));
+
+    WRITE_REG(ECAPx->ECCTL0_bit.CAP0POL, Polarity);
+}
+
+/**
+  * @brief   Настройка фронта события захвата 1
+  * @param   ECAPx  Выбор модуля ECAP, где x лежит в диапазоне 0-2
+  * @param   Polarity  Значение режима
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_Capture_PolarityEvt1Config(ECAP_TypeDef* ECAPx, ECAP_Capture_Polarity_TypeDef Polarity)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+    assert_param(IS_ECAP_CAPTURE_POLARITY(Polarity));
+
+    WRITE_REG(ECAPx->ECCTL0_bit.CAP1POL, Polarity);
+}
+
+/**
+  * @brief   Настройка фронта события захвата 2
+  * @param   ECAPx  Выбор модуля ECAP, где x лежит в диапазоне 0-2
+  * @param   Polarity  Значение режима
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_Capture_PolarityEvt2Config(ECAP_TypeDef* ECAPx, ECAP_Capture_Polarity_TypeDef Polarity)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+    assert_param(IS_ECAP_CAPTURE_POLARITY(Polarity));
+
+    WRITE_REG(ECAPx->ECCTL0_bit.CAP2POL, Polarity);
+}
+
+/**
+  * @brief   Настройка фронта события захвата 3
+  * @param   ECAPx  Выбор модуля ECAP, где x лежит в диапазоне 0-2
+  * @param   Polarity  Значение режима
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_Capture_PolarityEvt3Config(ECAP_TypeDef* ECAPx, ECAP_Capture_Polarity_TypeDef Polarity)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+    assert_param(IS_ECAP_CAPTURE_POLARITY(Polarity));
+
+    WRITE_REG(ECAPx->ECCTL0_bit.CAP3POL, Polarity);
+}
+
+/**
+  * @brief   Разрешение сброса таймера после события захвата 0
+  * @param   ECAPx  Выбор модуля ECAP, где x лежит в диапазоне 0-2
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_Capture_RstEvt0Cmd(ECAP_TypeDef* ECAPx, FunctionalState State)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(ECAPx->ECCTL0_bit.CTRRST0, State);
+}
+
+/**
+  * @brief   Разрешение сброса таймера после события захвата 1
+  * @param   ECAPx  Выбор модуля ECAP, где x лежит в диапазоне 0-2
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_Capture_RstEvt1Cmd(ECAP_TypeDef* ECAPx, FunctionalState State)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(ECAPx->ECCTL0_bit.CTRRST1, State);
+}
+
+/**
+  * @brief   Разрешение сброса таймера после события захвата 2
+  * @param   ECAPx  Выбор модуля ECAP, где x лежит в диапазоне 0-2
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_Capture_RstEvt2Cmd(ECAP_TypeDef* ECAPx, FunctionalState State)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(ECAPx->ECCTL0_bit.CTRRST2, State);
+}
+
+/**
+  * @brief   Разрешение сброса таймера после события захвата 3
+  * @param   ECAPx  Выбор модуля ECAP, где x лежит в диапазоне 0-2
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_Capture_RstEvt3Cmd(ECAP_TypeDef* ECAPx, FunctionalState State)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(ECAPx->ECCTL0_bit.CTRRST3, State);
+}
+
+/**
+  * @brief   Разрешение захвата для выбранного блока захвата
+  * @param   ECAPx  Выбор модуля ECAP, где x лежит в диапазоне 0-2
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_Capture_Cmd(ECAP_TypeDef* ECAPx, FunctionalState State)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(ECAPx->ECCTL1_bit.REARM, State);
+    WRITE_REG(ECAPx->ECCTL0_bit.CAPLDEN, State);
+}
+
+/**
+  * @brief   Установка значения регистра захвата 0
+  * @param   ECAPx  Выбор таймера, где x лежит в диапазоне 0-2
+  * @param   Value  Значение
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_Capture_SetCap0(ECAP_TypeDef* ECAPx, uint32_t Value)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+
+    WRITE_REG(ECAPx->CAP0, Value);
+}
+
+/**
+  * @brief   Установка значения регистра захвата 1
+  * @param   ECAPx  Выбор таймера, где x лежит в диапазоне 0-2
+  * @param   Value  Значение
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_Capture_SetCap1(ECAP_TypeDef* ECAPx, uint32_t Value)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+
+    WRITE_REG(ECAPx->CAP1, Value);
+}
+
+/**
+  * @brief   Установка значения регистра захвата 2
+  * @param   ECAPx  Выбор таймера, где x лежит в диапазоне 0-2
+  * @param   Value  Значение
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_Capture_SetCap2(ECAP_TypeDef* ECAPx, uint32_t Value)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+
+    WRITE_REG(ECAPx->CAP2, Value);
+}
+
+/**
+  * @brief   Установка значения регистра захвата 3
+  * @param   ECAPx  Выбор таймера, где x лежит в диапазоне 0-2
+  * @param   Value  Значение
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_Capture_SetCap3(ECAP_TypeDef* ECAPx, uint32_t Value)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+
+    WRITE_REG(ECAPx->CAP3, Value);
+}
+
+/**
+  * @brief   Получение текущего значения из регистра захвата 0
+  * @param   ECAPx  Выбор ECAP, где x лежит в диапазоне 0-2
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t ECAP_Capture_GetCap0(ECAP_TypeDef* ECAPx)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+
+    return READ_REG(ECAPx->CAP0);
+}
+
+/**
+  * @brief   Получение текущего значения из регистра захвата 1
+  * @param   ECAPx  Выбор ECAP, где x лежит в диапазоне 0-2
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t ECAP_Capture_GetCap1(ECAP_TypeDef* ECAPx)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+
+    return READ_REG(ECAPx->CAP1);
+}
+
+/**
+  * @brief   Получение текущего значения из регистра захвата 2
+  * @param   ECAPx  Выбор ECAP, где x лежит в диапазоне 0-2
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t ECAP_Capture_GetCap2(ECAP_TypeDef* ECAPx)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+
+    return READ_REG(ECAPx->CAP2);
+}
+
+/**
+  * @brief   Получение текущего значения из регистра захвата 3
+  * @param   ECAPx  Выбор ECAP, где x лежит в диапазоне 0-2
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t ECAP_Capture_GetCap3(ECAP_TypeDef* ECAPx)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+
+    return READ_REG(ECAPx->CAP3);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CAP_IT Прерывания
+  * @{
+  */
+
+/**
+  * @brief   Разрешение генерации прерываний
+  * @param   ECAPx  Выбор ECAP, где x лежит в диапазоне 0-2
+  * @param   ITSource  Выбор источников прерывания
+  *                    Параметр принимает любою совокупность значений ECAP_ITSource_x из @ref ECAP_ITSource_define.
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_ITCmd(ECAP_TypeDef* ECAPx, uint32_t ITSource, FunctionalState State)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+    assert_param(IS_ECAP_IT_SOURCE(ITSource));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    MODIFY_REG(ECAPx->ECEINT, ITSource, State ? (uint32_t)ITSource : 0);
+}
+
+/**
+  * @brief   Принудительный вызов прерывания выбранного блока захвата
+  * @param   ECAPx  Выбор ECAP, где x лежит в диапазоне 0-2
+  * @param   ITSource  Выбор источников прерывания
+  *                    Параметр принимает любою совокупность значений ECAP_ITSource_x из @ref ECAP_ITSource_define.
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_ITForceCmd(ECAP_TypeDef* ECAPx, uint32_t ITSource)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+    assert_param(IS_ECAP_IT_SOURCE(ITSource));
+
+    WRITE_REG(ECAPx->ECFRC, ITSource);
+}
+
+/**
+  * @brief   Чтение статуса прерывания выбранного блока захвата
+  * @param   ECAPx  Выбор ECAP, где x лежит в диапазоне 0-2
+  * @param   ITStatus  Выбор флага прерывания.
+  *                    Параметр принимает любою совокупность значений ECAP_ITStatus_x из @ref ECAP_ITStatus_define.
+  * @retval  Status  Статус прерывания. Если выбрано несколько прерываний,
+  *                  то результат соответсвует логическому ИЛИ их состояний.
+  */
+__STATIC_INLINE FlagStatus ECAP_ITStatus(ECAP_TypeDef* ECAPx, uint32_t ITStatus)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+    assert_param(IS_ECAP_IT_STATUS(ITStatus));
+
+    return (FlagStatus)READ_BIT(ECAPx->ECFLG, ITStatus);
+}
+
+/**
+  * @brief   Сброс статуса прерывания выбранного блока захвата
+  * @param   ECAPx  Выбор ECAP, где x лежит в диапазоне 0-2
+  * @param   ITStatus  Выбор флага прерывания.
+  *                    Параметр принимает любою совокупность значений ECAP_ITStatus_x из @ref ECAP_ITStatus_define.
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_ITStatusClear(ECAP_TypeDef* ECAPx, uint32_t ITStatus)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+    assert_param(IS_ECAP_IT_STATUS(ITStatus));
+
+    WRITE_REG(ECAPx->ECCLR, ITStatus);
+}
+
+/**
+  * @brief   Чтение активного статуса прерывания выбранного блока захвата
+  * @param   ECAPx  Выбор ECAP, где x лежит в диапазоне 0-2
+  * @retval  Status  Статус прерывания
+  */
+__STATIC_INLINE FlagStatus ECAP_ITPendStatus(ECAP_TypeDef* ECAPx)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+
+    return (FlagStatus)READ_BIT(ECAPx->PEINT, ECAP_PEINT_PEINT_Msk);
+}
+
+/**
+  * @brief   Сброс активности прерывания выбранного блока захвата.
+  * @param   CAPx  Выбор CAP, где x лежит в диапазоне 0-2
+  * @retval  void
+  */
+__STATIC_INLINE void ECAP_ITPendStatusClear(ECAP_TypeDef* ECAPx)
+{
+    assert_param(IS_ECAP_PERIPH(ECAPx));
+
+    WRITE_REG(ECAPx->PEINT, ECAP_PEINT_PEINT_Msk);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PLIB035_ECAP_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2018 NIIET *****END OF FILE****/

platform/plib035/inc/plib035_gpio.h

@@ -0,0 +1,832 @@
+/**
+  ******************************************************************************
+  * @file    plib035_gpio.h
+  *
+  * @brief   Файл содержит прототипы и компактные inline реализации функций для
+  *          GPIO, а также сопутствующие макроопределения и перечисления
+  *
+  * @author  НИИЭТ, Богдан Колбов <kolbov@niiet.ru>
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ ПРЕДОСТАВЛЯЕТСЯ «КАК ЕСТЬ», БЕЗ КАКИХ-ЛИБО
+  * ГАРАНТИЙ, ЯВНО ВЫРАЖЕННЫХ ИЛИ ПОДРАЗУМЕВАЕМЫХ, ВКЛЮЧАЯ ГАРАНТИИ ТОВАРНОЙ
+  * ПРИГОДНОСТИ, СООТВЕТСТВИЯ ПО ЕГО КОНКРЕТНОМУ НАЗНАЧЕНИЮ И ОТСУТСТВИЯ
+  * НАРУШЕНИЙ, НО НЕ ОГРАНИЧИВАЯСЬ ИМИ. ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ
+  * ПРЕДНАЗНАЧЕНО ДЛЯ ОЗНАКОМИТЕЛЬНЫХ ЦЕЛЕЙ И НАПРАВЛЕНО ТОЛЬКО НА
+  * ПРЕДОСТАВЛЕНИЕ ДОПОЛНИТЕЛЬНОЙ ИНФОРМАЦИИ О ПРОДУКТЕ, С ЦЕЛЬЮ СОХРАНИТЬ ВРЕМЯ
+  * ПОТРЕБИТЕЛЮ. НИ В КАКОМ СЛУЧАЕ АВТОРЫ ИЛИ ПРАВООБЛАДАТЕЛИ НЕ НЕСУТ
+  * ОТВЕТСТВЕННОСТИ ПО КАКИМ-ЛИБО ИСКАМ, ЗА ПРЯМОЙ ИЛИ КОСВЕННЫЙ УЩЕРБ, ИЛИ
+  * ПО ИНЫМ ТРЕБОВАНИЯМ, ВОЗНИКШИМ ИЗ-ЗА ИСПОЛЬЗОВАНИЯ ПРОГРАММНОГО ОБЕСПЕЧЕНИЯ
+  * ИЛИ ИНЫХ ДЕЙСТВИЙ С ПРОГРАММНЫМ ОБЕСПЕЧЕНИЕМ.
+  *
+  * <h2><center>&copy; 2018 ОАО "НИИЭТ"</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PLIB035_GPIO_H
+#define __PLIB035_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "plib035.h"
+
+/** @addtogroup Peripheral
+  * @{
+  */
+
+/** @defgroup GPIO
+  * @brief Драйвер для работы с GPIO
+  * @{
+  */
+
+/** @defgroup GPIO_Exported_Defines Константы
+  * @{
+  */
+
+/** @defgroup GPIO_Pin_Define Маски пинов
+  * @{
+  */
+
+#define GPIO_Pin_0 0x0001UL           /*!< Пин 0 выбран */
+#define GPIO_Pin_1 0x0002UL           /*!< Пин 1 выбран */
+#define GPIO_Pin_2 0x0004UL           /*!< Пин 2 выбран */
+#define GPIO_Pin_3 0x0008UL           /*!< Пин 3 выбран */
+#define GPIO_Pin_4 0x0010UL           /*!< Пин 4 выбран */
+#define GPIO_Pin_5 0x0020UL           /*!< Пин 5 выбран */
+#define GPIO_Pin_6 0x0040UL           /*!< Пин 6 выбран */
+#define GPIO_Pin_7 0x0080UL           /*!< Пин 7 выбран */
+#define GPIO_Pin_8 0x0100UL           /*!< Пин 8 выбран */
+#define GPIO_Pin_9 0x0200UL           /*!< Пин 9 выбран */
+#define GPIO_Pin_10 0x0400UL          /*!< Пин 10 выбран */
+#define GPIO_Pin_11 0x0800UL          /*!< Пин 11 выбран */
+#define GPIO_Pin_12 0x1000UL          /*!< Пин 12 выбран */
+#define GPIO_Pin_13 0x2000UL          /*!< Пин 13 выбран */
+#define GPIO_Pin_14 0x4000UL          /*!< Пин 14 выбран */
+#define GPIO_Pin_15 0x8000UL          /*!< Пин 15 выбран */
+#define GPIO_Pin_0_3 0x000FUL         /*!< Пины 0-3 выбраны */
+#define GPIO_Pin_3_0 GPIO_Pin_0_3     /*!< Пины 3-0 выбраны */
+#define GPIO_Pin_4_7 0x00F0UL         /*!< Пины 4-7 выбраны */
+#define GPIO_Pin_7_4 GPIO_Pin_4_7     /*!< Пины 7-4 выбраны */
+#define GPIO_Pin_8_11 0x0F00UL        /*!< Пины 8-11 выбраны */
+#define GPIO_Pin_11_8 GPIO_Pin_8_11   /*!< Пины 11-8 выбраны */
+#define GPIO_Pin_12_15 0xF000UL       /*!< Пины 12-15 выбраны */
+#define GPIO_Pin_15_12 GPIO_Pin_12_15 /*!< Пины 15-12 выбраны */
+#define GPIO_Pin_0_7 0x00FFUL         /*!< Пины 0-7 выбраны */
+#define GPIO_Pin_7_0 GPIO_Pin_0_7     /*!< Пины 7-0 выбраны */
+#define GPIO_Pin_8_15 0xFF00UL        /*!< Пины 8-15 выбраны */
+#define GPIO_Pin_15_8 GPIO_Pin_8_15   /*!< Пины 15-8 выбраны */
+#define GPIO_Pin_All 0xFFFFUL         /*!< Все пины выбраны */
+
+#define IS_GPIO_PIN(VALUE) (((VALUE) != 0) && (((VALUE)&0xFFFF0000) == 0))
+
+#define IS_GET_GPIO_PIN(VALUE) (((VALUE) == GPIO_Pin_0) ||  \
+                                ((VALUE) == GPIO_Pin_1) ||  \
+                                ((VALUE) == GPIO_Pin_2) ||  \
+                                ((VALUE) == GPIO_Pin_3) ||  \
+                                ((VALUE) == GPIO_Pin_4) ||  \
+                                ((VALUE) == GPIO_Pin_5) ||  \
+                                ((VALUE) == GPIO_Pin_6) ||  \
+                                ((VALUE) == GPIO_Pin_7) ||  \
+                                ((VALUE) == GPIO_Pin_8) ||  \
+                                ((VALUE) == GPIO_Pin_9) ||  \
+                                ((VALUE) == GPIO_Pin_10) || \
+                                ((VALUE) == GPIO_Pin_11) || \
+                                ((VALUE) == GPIO_Pin_12) || \
+                                ((VALUE) == GPIO_Pin_13) || \
+                                ((VALUE) == GPIO_Pin_14) || \
+                                ((VALUE) == GPIO_Pin_15))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Exported_Types Типы
+  * @{
+  */
+
+/**
+  * @brief  Выбор режима работы пина
+  */
+typedef enum {
+    GPIO_Mode_IO,     /*!< Пин в режиме ввода-вывода */
+    GPIO_Mode_AltFunc /*!< Пин в режиме альтернативной функции */
+} GPIO_Mode_TypeDef;
+#define IS_GPIO_MODE(VALUE) (((VALUE) == GPIO_Mode_IO) || \
+                             ((VALUE) == GPIO_Mode_AltFunc))
+
+/**
+  * @brief  Выбор события для возникновения прерывания
+  */
+typedef enum {
+    GPIO_IntType_Level, /*!< Прерывание по уровню */
+    GPIO_IntType_Edge   /*!< Прерывание по перепаду */
+} GPIO_IntType_TypeDef;
+#define IS_GPIO_INT_TYPE(VALUE) (((VALUE) == GPIO_IntType_Level) || \
+                                 ((VALUE) == GPIO_IntType_Edge))
+
+/**
+  * @brief  Выбор полярности события для возникновения прерывания
+  */
+typedef enum {
+    GPIO_IntPol_Negative, /*!< Прерывание по низкому уровню или отрицательному фронту */
+    GPIO_IntPol_Positive  /*!< Прерывание по высокому уровню или положительному фронту */
+} GPIO_IntPol_TypeDef;
+#define IS_GPIO_INT_POL(VALUE) (((VALUE) == GPIO_IntPol_Negative) || \
+                                ((VALUE) == GPIO_IntPol_Positive))
+
+/**
+  * @brief  Выбор количества фронтов, ипользуемых в генерации прерывания по фронту
+  */
+typedef enum {
+    GPIO_IntEdge_Polarity, /*!< Прерывание согласно выбранной полярности фронта */
+    GPIO_IntEdge_Any       /*!< Прерывание по обоим фронтам */
+} GPIO_IntEdge_TypeDef;
+#define IS_GPIO_INT_EDGE(VALUE) (((VALUE) == GPIO_IntEdge_Polarity) || \
+                                 ((VALUE) == GPIO_IntEdge_Any))
+
+/**
+  * @brief  Выбор режима работы выходных каскадов
+  */
+typedef enum {
+    GPIO_OutMode_PP = GPIO_OUTMODE_PIN0_PP, /*!< Режим push-pull */
+    GPIO_OutMode_OD = GPIO_OUTMODE_PIN0_OD, /*!< Режим open-drain */
+    GPIO_OutMode_OS = GPIO_OUTMODE_PIN0_OS  /*!< Режим open-source */
+} GPIO_OutMode_TypeDef;
+#define IS_GPIO_OUT_MODE(VALUE) (((VALUE) == GPIO_OutMode_PP) || \
+                                 ((VALUE) == GPIO_OutMode_OD) || \
+                                 ((VALUE) == GPIO_OutMode_OS))
+
+/**
+  * @brief  Выбор режима работы входа
+  */
+typedef enum {
+    GPIO_InMode_Schmitt = GPIO_INMODE_PIN0_Schmitt, /*!< Режим push-pull */
+    GPIO_InMode_CMOS = GPIO_INMODE_PIN0_CMOS,       /*!< Режим open-drain */
+    GPIO_InMode_Disable = GPIO_INMODE_PIN0_Disable  /*!< Режим open-source */
+} GPIO_InMode_TypeDef;
+#define IS_GPIO_IN_MODE(VALUE) (((VALUE) == GPIO_InMode_Schmitt) || \
+                                ((VALUE) == GPIO_InMode_CMOS) ||    \
+                                ((VALUE) == GPIO_InMode_Disable))
+
+/**
+  * @brief  Выбор режима работы подтяжки
+  */
+typedef enum {
+    GPIO_PullMode_Disable = GPIO_PULLMODE_PIN0_Disable, /*!< Внутренняя подтяжка выключена */
+    GPIO_PullMode_PU = GPIO_PULLMODE_PIN0_PU,           /*!< Внутренняя подтяжка к питанию включена */
+    GPIO_PullMode_PD = GPIO_PULLMODE_PIN0_PD            /*!< Внутренняя подтяжка к земле включена */
+} GPIO_PullMode_TypeDef;
+#define IS_GPIO_PULL_MODE(VALUE) (((VALUE) == GPIO_PullMode_Disable) || \
+                                  ((VALUE) == GPIO_PullMode_PU) ||      \
+                                  ((VALUE) == GPIO_PullMode_PD))
+
+/**
+  * @brief  Выбор нагрузочной способности и скорости переключения пина
+  */
+typedef enum {
+    GPIO_DriveMode_HighFast = GPIO_DRIVEMODE_PIN0_HF, /*!< Высокая нагрузочная способность и высокая скорость переключения */
+    GPIO_DriveMode_HighSlow = GPIO_DRIVEMODE_PIN0_HS, /*!< Высокая нагрузочная способность и низкая скорость переключения */
+    GPIO_DriveMode_LowFast = GPIO_DRIVEMODE_PIN0_LF,  /*!< Низкая нагрузочная способность и высокая скорость переключения */
+    GPIO_DriveMode_LowSlow = GPIO_DRIVEMODE_PIN0_LS   /*!< Низкая нагрузочная способность и низкая скорость переключения */
+} GPIO_DriveMode_TypeDef;
+#define IS_GPIO_DRIVE_MODE(VALUE) (((VALUE) == GPIO_DriveMode_HighFast) || \
+                                   ((VALUE) == GPIO_DriveMode_HighSlow) || \
+                                   ((VALUE) == GPIO_DriveMode_LowFast) ||  \
+                                   ((VALUE) == GPIO_DriveMode_LowSlow))
+
+/**
+  * @brief  Выбор режима работы входного фильтра пина
+  */
+typedef enum {
+    GPIO_QualMode_3Sample, /*!< Используется 3 отсчета для фильтрации */
+    GPIO_QualMode_6Sample  /*!< Используется 6 отсчетов для фильтрации */
+} GPIO_QualMode_TypeDef;
+#define IS_GPIO_QUAL_MODE(VALUE) (((VALUE) == GPIO_QualMode_3Sample) || \
+                                  ((VALUE) == GPIO_QualMode_6Sample))
+
+#define IS_GPIO_QUAL_PERIOD(VALUE) (((VALUE)&0xFFFFFF00) == 0)
+#define IS_GPIO_MASK(VALUE) (((VALUE)&0xFFFFFF00) == 0)
+#define IS_GPIO_VAL(VALUE) (((VALUE)&0xFFFF0000) == 0)
+
+/**
+  * @brief  Структура инициализации GPIO
+  */
+typedef struct
+{
+    uint32_t Pin;                     /*!< Определяет пины, которые будут настроены.
+                                           Параметр может принимать любое значение из @ref GPIO_Pin_Define. */
+    FunctionalState Out;              /*!< Определяет включение выхода выбранных пинов */
+    FunctionalState AltFunc;          /*!< Определяет режим работы периферийной функции пинов */
+    FunctionalState Digital;          /*!< Определяет включение цифровой функции порта */
+    GPIO_OutMode_TypeDef OutMode;     /*!< Определяет режим работы выходных каскадов выбранных пинов */
+    GPIO_InMode_TypeDef InMode;       /*!< Определяет режим работы входов выбранных пинов */
+    GPIO_PullMode_TypeDef PullMode;   /*!< Определяет режим работы подтяжки выбранных пинов */
+    GPIO_DriveMode_TypeDef DriveMode; /*!< Определяет нагрузочную способность и скорость переключения выбранных пинов */
+} GPIO_Init_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Exported_Functions Функции
+  * @{
+  */
+
+/** @defgroup GPIO_Init_Deinit Инициализация и деинициализация
+  * @{
+  */
+
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_Init_TypeDef* InitStruct);
+void GPIO_StructInit(GPIO_Init_TypeDef* InitStruct);
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Config Конфигурация
+  * @{
+  */
+
+/**
+  * @brief   Включение цифровой работы (вход или выход) выбранных пинов
+  * @param   GPIOx  выбор порта, где x=A|B
+  * @param   Pin  Выбор пинов. Любая совокупность значений GPIO_Pin_x (@ref GPIO_Pin_Define).
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void GPIO_DigitalCmd(GPIO_TypeDef* GPIOx, uint32_t Pin, FunctionalState State)
+{
+    assert_param(IS_GPIO_PERIPH(GPIOx));
+    assert_param(IS_GPIO_PIN(Pin));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    if (State == ENABLE)
+        WRITE_REG(GPIOx->DENSET, Pin);
+    else
+        WRITE_REG(GPIOx->DENCLR, Pin);
+}
+
+/**
+  * @brief   Включение выхода выбранных пинов
+  * @param   GPIOx  выбор порта, где x=A|B
+  * @param   Pin  Выбор пинов. Любая совокупность значений значений GPIO_Pin_x (@ref GPIO_Pin_Define).
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void GPIO_OutCmd(GPIO_TypeDef* GPIOx, uint32_t Pin, FunctionalState State)
+{
+    assert_param(IS_GPIO_PERIPH(GPIOx));
+    assert_param(IS_GPIO_PIN(Pin));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    if (State == ENABLE)
+        WRITE_REG(GPIOx->OUTENSET, Pin);
+    else
+        WRITE_REG(GPIOx->OUTENCLR, Pin);
+}
+
+/**
+  * @brief   Включение периферийной функции выбранных пинов
+  * @param   GPIOx  выбор порта, где x=A|B
+  * @param   Pin  Выбор пинов. Любая совокупность значений значений GPIO_Pin_x (@ref GPIO_Pin_Define).
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void GPIO_AltFuncCmd(GPIO_TypeDef* GPIOx, uint32_t Pin, FunctionalState State)
+{
+    assert_param(IS_GPIO_PERIPH(GPIOx));
+    assert_param(IS_GPIO_PIN(Pin));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    if (State == ENABLE)
+        WRITE_REG(GPIOx->ALTFUNCSET, Pin);
+    else
+        WRITE_REG(GPIOx->ALTFUNCCLR, Pin);
+}
+
+void GPIO_OutModeConfig(GPIO_TypeDef* GPIOx, uint32_t Pin, GPIO_OutMode_TypeDef OutMode);
+void GPIO_InModeConfig(GPIO_TypeDef* GPIOx, uint32_t Pin, GPIO_InMode_TypeDef InMode);
+void GPIO_PullModeConfig(GPIO_TypeDef* GPIOx, uint32_t Pin, GPIO_PullMode_TypeDef PullMode);
+void GPIO_DriveModeConfig(GPIO_TypeDef* GPIOx, uint32_t Pin, GPIO_DriveMode_TypeDef DriveMode);
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Read_Write Чтение и запись
+  * @{
+  */
+
+/** @defgroup GPIO_Read Чтение
+  * @{
+  */
+
+/**
+  * @brief   Чтение состояния выбранного пина
+  * @param   GPIOx  Выбор порта, где x=A|B
+  * @param   Pin  Выбор пина
+  * @retval  State  Состояние Если выбрано несколько пинов, то результат соответсвует логическому ИЛИ их состояний.
+  */
+__STATIC_INLINE BitState GPIO_ReadBit(GPIO_TypeDef* GPIOx, uint32_t Pin)
+{
+    assert_param(IS_GPIO_PERIPH(GPIOx));
+    assert_param(IS_GET_GPIO_PIN(Pin));
+
+    return (BitState)READ_BIT(GPIOx->DATA, (uint32_t)Pin);
+}
+
+/**
+  * @brief   Чтение состояния выбранного порта
+  * @param   GPIOx  Выбор порта, где x=A|B
+  * @retval  Val  Состояние
+  */
+__STATIC_INLINE uint32_t GPIO_ReadPort(GPIO_TypeDef* GPIOx)
+{
+    assert_param(IS_GPIO_PERIPH(GPIOx));
+
+    return READ_REG(GPIOx->DATA);
+}
+
+/**
+  * @brief   Чтение состояния младшего байта порта c использованием маски
+  * @param   GPIOx  Выбор порта, где x=A|B
+  * @param   MaskVal  Значение маски чтения
+  * @retval  Val  Состояние находится в битах 7:0
+  */
+__STATIC_INLINE uint32_t GPIO_ReadLowMask(GPIO_TypeDef* GPIOx, uint32_t MaskVal)
+{
+    assert_param(IS_GPIO_PERIPH(GPIOx));
+    assert_param(IS_GPIO_MASK(MaskVal));
+
+    return READ_REG(GPIOx->MASKLB[MaskVal].MASKLB);
+}
+
+/**
+  * @brief   Чтение состояния старшего байта порта c использованием маски
+  * @param   GPIOx  Выбор порта, где x=A|B
+  * @param   MaskVal  Значение маски чтения
+  * @retval  Val  Состояние находится в битах 15:8
+  */
+__STATIC_INLINE uint32_t GPIO_ReadHighMask(GPIO_TypeDef* GPIOx, uint32_t MaskVal)
+{
+    assert_param(IS_GPIO_PERIPH(GPIOx));
+    assert_param(IS_GPIO_MASK(MaskVal));
+
+    return READ_REG(GPIOx->MASKHB[MaskVal].MASKHB);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Write Запись
+  * @{
+  */
+
+/**
+  * @brief   Запись выбранного пина
+  * @param   GPIOx  Выбор порта, где x=A|B
+  * @param   Pin  Выбор пина
+  * @retval  void
+  */
+__STATIC_INLINE void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint32_t Pin, BitState State)
+{
+    assert_param(IS_GPIO_PERIPH(GPIOx));
+    assert_param(IS_GET_GPIO_PIN(Pin));
+    assert_param(IS_BIT_STATE(State));
+
+    MODIFY_REG(GPIOx->DATAOUT, Pin, State ? (uint32_t)Pin : 0);
+}
+
+/**
+  * @brief   Запись выбранного порта
+  * @param   GPIOx  Выбор порта, где x=A|B
+  * @param   PortVal  Значение которое будет записано
+  * @retval  void
+  */
+__STATIC_INLINE void GPIO_WritePort(GPIO_TypeDef* GPIOx, uint32_t PortVal)
+{
+    assert_param(IS_GPIO_PERIPH(GPIOx));
+    assert_param(IS_GPIO_VAL(PortVal));
+
+    WRITE_REG(GPIOx->DATAOUT, PortVal);
+}
+
+/**
+  * @brief   Запись младшего байта порта c использованием маски
+  * @param   GPIOx  Выбор порта, где x=A|B
+  * @param   MaskVal  Значение маски
+  * @param   PortVal  Значение которое будет записано (биты 7:0)
+  * @retval  void
+  */
+__STATIC_INLINE void GPIO_WriteLowMask(GPIO_TypeDef* GPIOx, uint32_t MaskVal, uint32_t PortVal)
+{
+    assert_param(IS_GPIO_PERIPH(GPIOx));
+    assert_param(IS_GPIO_VAL(PortVal));
+    assert_param(IS_GPIO_MASK(MaskVal));
+
+    WRITE_REG(GPIOx->MASKLB[MaskVal].MASKLB, PortVal);
+}
+
+/**
+  * @brief   Запись старшего байта порта c использованием маски
+  * @param   GPIOx  Выбор порта, где x=A|B
+  * @param   MaskVal  Значение маски
+  * @param   PortVal  Значение которое будет записано (биты 15:8)
+  * @retval  void
+  */
+__STATIC_INLINE void GPIO_WriteHighMask(GPIO_TypeDef* GPIOx, uint32_t MaskVal, uint32_t PortVal)
+{
+    assert_param(IS_GPIO_PERIPH(GPIOx));
+    assert_param(IS_GPIO_VAL(PortVal));
+    assert_param(IS_GPIO_MASK(MaskVal));
+
+    WRITE_REG(GPIOx->MASKHB[MaskVal].MASKHB, PortVal);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Bit_Operations Битовые операции
+  * @{
+  */
+
+/**
+  * @brief   Установка пинов порта
+  * @param   GPIOx  Выбор порта, где x=A|B
+  * @param   Pin  Выбор пина
+  * @retval  void
+  */
+__STATIC_INLINE void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint32_t Pin)
+{
+    assert_param(IS_GPIO_PERIPH(GPIOx));
+    assert_param(IS_GET_GPIO_PIN(Pin));
+
+    WRITE_REG(GPIOx->DATAOUTSET, Pin);
+}
+
+/**
+  * @brief   Сброс пинов порта
+  * @param   GPIOx  Выбор порта, где x=A|B
+  * @param   Pin  Выбор пина
+  * @retval  void
+  */
+__STATIC_INLINE void GPIO_ClearBits(GPIO_TypeDef* GPIOx, uint32_t Pin)
+{
+    assert_param(IS_GPIO_PERIPH(GPIOx));
+    assert_param(IS_GET_GPIO_PIN(Pin));
+
+    WRITE_REG(GPIOx->DATAOUTCLR, Pin);
+}
+
+/**
+  * @brief   Переключение пинов порта в противоположное состояние
+  * @param   GPIOx  Выбор порта, где x=A|B
+  * @param   Pin  Выбор пина
+  * @retval  void
+  */
+__STATIC_INLINE void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint32_t Pin)
+{
+    assert_param(IS_GPIO_PERIPH(GPIOx));
+    assert_param(IS_GET_GPIO_PIN(Pin));
+
+    WRITE_REG(GPIOx->DATAOUTTGL, Pin);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Qualifier Фильтрация
+  * @{
+  */
+
+/**
+  * @brief   Настройка режима входного фильтра пина
+  * @param   GPIOx  выбор порта, где x=A|B
+  * @param   Pin  Выбор пинов. Любая совокупность значений значений GPIO_Pin_x (@ref GPIO_Pin_Define).
+  * @param   Mode  Выбор режима
+  * @retval  void
+  */
+__STATIC_INLINE void GPIO_QualModeConfig(GPIO_TypeDef* GPIOx, uint32_t Pin, GPIO_QualMode_TypeDef Mode)
+{
+    assert_param(IS_GPIO_PERIPH(GPIOx));
+    assert_param(IS_GPIO_PIN(Pin));
+    assert_param(IS_GPIO_QUAL_MODE(Mode));
+
+    if (Mode == GPIO_QualMode_6Sample)
+        WRITE_REG(GPIOx->QUALMODESET, Pin);
+    else
+        WRITE_REG(GPIOx->QUALMODECLR, Pin);
+}
+
+/**
+  * @brief   Настройка времени сэмплирования
+  * @param   GPIOx  Выбор порта, где x=A|B
+  * @param   SamplePerod  Количество тактов системной частоты между отсчетами фильтра
+  * @retval  void
+  */
+__STATIC_INLINE void GPIO_QualSampleConfig(GPIO_TypeDef* GPIOx, uint32_t SamplePerod)
+{
+    assert_param(IS_GPIO_PERIPH(GPIOx));
+    assert_param(IS_GPIO_QUAL_PERIOD(SamplePerod));
+
+    WRITE_REG(GPIOx->QUALSAMPLE, SamplePerod);
+}
+
+/**
+  * @brief   Включение входных фильтров пинов
+  * @param   GPIOx  выбор порта, где x=A|B
+  * @param   Pin  Выбор пинов. Любая совокупность значений значений GPIO_Pin_x (@ref GPIO_Pin_Define).
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void GPIO_QualCmd(GPIO_TypeDef* GPIOx, uint32_t Pin, FunctionalState State)
+{
+    assert_param(IS_GPIO_PERIPH(GPIOx));
+    assert_param(IS_GPIO_PIN(Pin));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    if (State == ENABLE)
+        WRITE_REG(GPIOx->QUALSET, Pin);
+    else
+        WRITE_REG(GPIOx->QUALCLR, Pin);
+}
+
+/**
+  * @brief   Включение пересинхронизации входов через 2 триггера
+  * @param   GPIOx  выбор порта, где x=A|B.
+  * @param   Pin  Выбор пинов. Любая совокупность значений значений GPIO_Pin_x (@ref GPIO_Pin_Define).
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void GPIO_SyncCmd(GPIO_TypeDef* GPIOx, uint32_t Pin, FunctionalState State)
+{
+    assert_param(IS_GPIO_PERIPH(GPIOx));
+    assert_param(IS_GPIO_PIN(Pin));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    if (State == ENABLE)
+        WRITE_REG(GPIOx->SYNCSET, Pin);
+    else
+        WRITE_REG(GPIOx->SYNCCLR, Pin);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Interrupts Прерывания
+  * @{
+  */
+
+/**
+  * @brief   Настройка режима генерации сигналов прерываний и внешних сигналов запросов
+  * @param   GPIOx  выбор порта, где x=A|B
+  * @param   Pin  Выбор пинов. Любая совокупность значений значений GPIO_Pin_x (@ref GPIO_Pin_Define).
+  * @param   IntType  Выбор режима генерации
+  * @retval  void
+  */
+__STATIC_INLINE void GPIO_ITTypeConfig(GPIO_TypeDef* GPIOx, uint32_t Pin, GPIO_IntType_TypeDef IntType)
+{
+    assert_param(IS_GPIO_PERIPH(GPIOx));
+    assert_param(IS_GPIO_PIN(Pin));
+    assert_param(IS_GPIO_INT_TYPE(IntType));
+
+    if (IntType == GPIO_IntType_Edge)
+        WRITE_REG(GPIOx->INTTYPESET, Pin);
+    else
+        WRITE_REG(GPIOx->INTTYPECLR, Pin);
+}
+
+/**
+  * @brief   Настройка полярности генерации прерываний
+  * @param   GPIOx  выбор порта, где x=A|B
+  * @param   Pin  Выбор пинов. Любая совокупность значений значений GPIO_Pin_x (@ref GPIO_Pin_Define).
+  * @param   IntPol  Выбор полярности
+  * @retval  void
+  */
+__STATIC_INLINE void GPIO_ITPolConfig(GPIO_TypeDef* GPIOx, uint32_t Pin, GPIO_IntPol_TypeDef IntPol)
+{
+    assert_param(IS_GPIO_PERIPH(GPIOx));
+    assert_param(IS_GPIO_PIN(Pin));
+    assert_param(IS_GPIO_INT_POL(IntPol));
+
+    if (IntPol == GPIO_IntPol_Positive)
+        WRITE_REG(GPIOx->INTPOLSET, Pin);
+    else
+        WRITE_REG(GPIOx->INTPOLCLR, Pin);
+}
+
+/**
+  * @brief   Настройка режима прерываний по перепадам
+  * @param   GPIOx  выбор порта, где x=A|B
+  * @param   Pin  Выбор пинов. Любая совокупность значений значений GPIO_Pin_x (@ref GPIO_Pin_Define).
+  * @param   IntEdge  Выбор режима
+  * @retval  void
+  */
+__STATIC_INLINE void GPIO_ITEdgeConfig(GPIO_TypeDef* GPIOx, uint32_t Pin, GPIO_IntEdge_TypeDef IntEdge)
+{
+    assert_param(IS_GPIO_PERIPH(GPIOx));
+    assert_param(IS_GPIO_PIN(Pin));
+    assert_param(IS_GPIO_INT_EDGE(IntEdge));
+
+    if (IntEdge == GPIO_IntEdge_Any)
+        WRITE_REG(GPIOx->INTEDGESET, Pin);
+    else
+        WRITE_REG(GPIOx->INTEDGECLR, Pin);
+}
+
+/**
+  * @brief   Разрешение генерации прерываний
+  * @param   GPIOx  выбор порта, где x=A|B
+  * @param   Pin  Выбор пинов. Любая совокупность значений значений GPIO_Pin_x (@ref GPIO_Pin_Define).
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void GPIO_ITCmd(GPIO_TypeDef* GPIOx, uint32_t Pin, FunctionalState State)
+{
+    assert_param(IS_GPIO_PERIPH(GPIOx));
+    assert_param(IS_GPIO_PIN(Pin));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    if (State == ENABLE)
+        WRITE_REG(GPIOx->INTENSET, Pin);
+    else
+        WRITE_REG(GPIOx->INTENCLR, Pin);
+}
+
+/**
+  * @brief   Получение статуса выбранного пина
+  * @param   Pin  Выбор пинов. Любая совокупность значений значений GPIO_Pin_x (@ref GPIO_Pin_Define).
+  * @retval  Status  Если выбрано несколько пинов, то результат соответсвует логическому ИЛИ их состояний.
+  */
+__STATIC_INLINE FlagStatus GPIO_ITStatus(GPIO_TypeDef* GPIOx, uint32_t Pin)
+{
+    assert_param(IS_GPIO_PERIPH(GPIOx));
+    assert_param(IS_GPIO_PIN(Pin));
+
+    return (FlagStatus)READ_BIT(GPIOx->INTSTATUS, Pin);
+}
+
+/**
+  * @brief   Сброс статуса выбранного флага прерывания
+  * @param   Pin  Выбор пинов
+  * @retval  void
+  */
+__STATIC_INLINE void GPIO_ITStatusClear(GPIO_TypeDef* GPIOx, uint32_t Pin)
+{
+    assert_param(IS_GPIO_PIN(Pin));
+
+    WRITE_REG(GPIOx->INTSTATUS, Pin);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_ExternalRequests Генерация внешних запросов
+  * @{
+  */
+
+/**
+  * @brief   Разрешение генерации запросов к DMA
+  * @param   GPIOx  выбор порта, где x=A|B
+  * @param   Pin  Выбор пинов. Любая совокупность значений значений GPIO_Pin_x (@ref GPIO_Pin_Define).
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void GPIO_DMAReqCmd(GPIO_TypeDef* GPIOx, uint32_t Pin, FunctionalState State)
+{
+    assert_param(IS_GPIO_PERIPH(GPIOx));
+    assert_param(IS_GPIO_PIN(Pin));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    if (State == ENABLE)
+        WRITE_REG(GPIOx->DMAREQSET, Pin);
+    else
+        WRITE_REG(GPIOx->DMAREQCLR, Pin);
+}
+
+/**
+  * @brief   Разрешение генерации сигналов запуска АЦП
+  * @param   GPIOx  выбор порта, где x=A|B
+  * @param   Pin  Выбор пинов. Любая совокупность значений значений GPIO_Pin_x (@ref GPIO_Pin_Define).
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void GPIO_ADCSOCCmd(GPIO_TypeDef* GPIOx, uint32_t Pin, FunctionalState State)
+{
+    assert_param(IS_GPIO_PERIPH(GPIOx));
+    assert_param(IS_GPIO_PIN(Pin));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    if (State == ENABLE)
+        WRITE_REG(GPIOx->ADCSOCSET, Pin);
+    else
+        WRITE_REG(GPIOx->ADCSOCCLR, Pin);
+}
+
+/**
+  * @brief   Разрешение генерации события RXEV
+  * @param   GPIOx  выбор порта, где x=A|B
+  * @param   Pin  Выбор пинов. Любая совокупность значений значений GPIO_Pin_x (@ref GPIO_Pin_Define).
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void GPIO_RXEVCmd(GPIO_TypeDef* GPIOx, uint32_t Pin, FunctionalState State)
+{
+    assert_param(IS_GPIO_PERIPH(GPIOx));
+    assert_param(IS_GPIO_PIN(Pin));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    if (State == ENABLE)
+        WRITE_REG(GPIOx->RXEVSET, Pin);
+    else
+        WRITE_REG(GPIOx->RXEVCLR, Pin);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Lock Механизм защиты конфигурации
+  * @{
+  */
+/**
+  * @brief   Разрешение изменения состояния защиты пинов. Разрешение применяется спустя несколько тактов.
+  * @param   GPIOx  выбор порта, где x=A|B
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void GPIO_LockKeyCmd(GPIO_TypeDef* GPIOx, FunctionalState State)
+{
+    assert_param(IS_GPIO_PERIPH(GPIOx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    if (State == ENABLE)
+        WRITE_REG(GPIOx->LOCKKEY, (uint32_t)GPIO_LOCKKEY_VAL_UNLOCK);
+    else
+        WRITE_REG(GPIOx->LOCKKEY, (uint32_t)GPIO_LOCKKEY_VAL_LOCK);
+}
+
+/**
+  * @brief      Управление защитой конфигурации пина от изменений.
+  * @attention  По умолчанию, регистры используемые в функции находятся врежиме "только чтение".
+  *             Чтобы разрешить их запись, необходимо воспользоваться функцией @ref GPIO_LockKeyCmd и подождать несколько тактов.
+  * @param      GPIOx  выбор порта, где x=A|B
+  * @param      Pin  Выбор пинов. Любая совокупность значений значений GPIO_Pin_x (@ref GPIO_Pin_Define).
+  * @param      State  Выбор состояния
+  * @retval     void
+  */
+__STATIC_INLINE void GPIO_LockCmd(GPIO_TypeDef* GPIOx, uint32_t Pin, FunctionalState State)
+{
+    assert_param(IS_GPIO_PERIPH(GPIOx));
+    assert_param(IS_GPIO_PIN(Pin));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    if (State == ENABLE)
+        WRITE_REG(GPIOx->LOCKSET, Pin);
+    else
+        WRITE_REG(GPIOx->LOCKCLR, Pin);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PLIB035_GPIO_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2018 NIIET *****END OF FILE****/

platform/plib035/inc/plib035_i2c.h

@@ -0,0 +1,548 @@
+/**
+  ******************************************************************************
+  * @file    plib035_i2c.h
+  *
+  * @brief   Файл содержит прототипы и компактные inline реализации функций для
+  *          I2C, а также сопутствующие макроопределения и перечисления
+  *
+  * @author  НИИЭТ, Богдан Колбов <kolbov@niiet.ru>
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ ПРЕДОСТАВЛЯЕТСЯ «КАК ЕСТЬ», БЕЗ КАКИХ-ЛИБО
+  * ГАРАНТИЙ, ЯВНО ВЫРАЖЕННЫХ ИЛИ ПОДРАЗУМЕВАЕМЫХ, ВКЛЮЧАЯ ГАРАНТИИ ТОВАРНОЙ
+  * ПРИГОДНОСТИ, СООТВЕТСТВИЯ ПО ЕГО КОНКРЕТНОМУ НАЗНАЧЕНИЮ И ОТСУТСТВИЯ
+  * НАРУШЕНИЙ, НО НЕ ОГРАНИЧИВАЯСЬ ИМИ. ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ
+  * ПРЕДНАЗНАЧЕНО ДЛЯ ОЗНАКОМИТЕЛЬНЫХ ЦЕЛЕЙ И НАПРАВЛЕНО ТОЛЬКО НА
+  * ПРЕДОСТАВЛЕНИЕ ДОПОЛНИТЕЛЬНОЙ ИНФОРМАЦИИ О ПРОДУКТЕ, С ЦЕЛЬЮ СОХРАНИТЬ ВРЕМЯ
+  * ПОТРЕБИТЕЛЮ. НИ В КАКОМ СЛУЧАЕ АВТОРЫ ИЛИ ПРАВООБЛАДАТЕЛИ НЕ НЕСУТ
+  * ОТВЕТСТВЕННОСТИ ПО КАКИМ-ЛИБО ИСКАМ, ЗА ПРЯМОЙ ИЛИ КОСВЕННЫЙ УЩЕРБ, ИЛИ
+  * ПО ИНЫМ ТРЕБОВАНИЯМ, ВОЗНИКШИМ ИЗ-ЗА ИСПОЛЬЗОВАНИЯ ПРОГРАММНОГО ОБЕСПЕЧЕНИЯ
+  * ИЛИ ИНЫХ ДЕЙСТВИЙ С ПРОГРАММНЫМ ОБЕСПЕЧЕНИЕМ.
+  *
+  * <h2><center>&copy; 2018 ОАО "НИИЭТ"</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PLIB035_I2C_H
+#define __PLIB035_I2C_H
+
+#ifdef __cplusplus
+//extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "plib035.h"
+
+/** @addtogroup Peripheral
+  * @{
+  */
+
+/** @defgroup I2C
+  * @brief Драйвер для работы с I2C
+  * @{
+  */
+
+/** @defgroup I2C_Exported_Defines Константы
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Types Типы
+  * @{
+  */
+
+/**
+  * @brief  Коды состояния I2C
+  */
+typedef enum {
+    I2C_State_IDLE = I2C_ST_MODE_IDLE,       /*!< Общий - Idle, нет доступной статусной информации */
+    I2C_State_STDONE = I2C_ST_MODE_STDONE,   /*!< FS мастер - Сформировано состояние СТАРТа */
+    I2C_State_RSDONE = I2C_ST_MODE_RSDONE,   /*!< FS мастер - Сформировано состояние повторного СТАРТа */
+    I2C_State_IDLARL = I2C_ST_MODE_IDLARL,   /*!< FS мастер - Потеря арбитража, переход в режим безадресного ведомого */
+    I2C_State_MTADPA = I2C_ST_MODE_MTADPA,   /*!< FS мастер передача - Отправлен адрес ведомого, ACK */
+    I2C_State_MTADNA = I2C_ST_MODE_MTADNA,   /*!< FS мастер передача - Отправлен адрес ведомого, NACK */
+    I2C_State_MTDAPA = I2C_ST_MODE_MTDAPA,   /*!< FS мастер передача - Отправлен байт данных, ACK */
+    I2C_State_MTDANA = I2C_ST_MODE_MTDANA,   /*!< FS мастер передача - Отправлен байт данных, NACK */
+    I2C_State_MRADPA = I2C_ST_MODE_MRADPA,   /*!< FS мастер приём - Отправлен адрес ведомого, ACK */
+    I2C_State_MRADNA = I2C_ST_MODE_MRADNA,   /*!< FS мастер приём - Отправлен адрес ведомого, NACK */
+    I2C_State_MRDAPA = I2C_ST_MODE_MRDAPA,   /*!< FS мастер приём - Принят байт данных, ACK */
+    I2C_State_MRDANA = I2C_ST_MODE_MRDANA,   /*!< FS мастер приём - Принят байт данных, NACK */
+    I2C_State_MTMCER = I2C_ST_MODE_MTMCER,   /*!< FS мастер - Отправлен код мастера, обнаружена ошибка, ACK */
+    I2C_State_SRADPA = I2C_ST_MODE_SRADPA,   /*!< FS ведомый приём - Принят адрес ведомого, ACK */
+    I2C_State_SRAAPA = I2C_ST_MODE_SRAAPA,   /*!< FS ведомый приём - Принят адрес ведомого после потери арбитража, ACK */
+    I2C_State_SRDAPA = I2C_ST_MODE_SRDAPA,   /*!< FS ведомый приём - Принят байт данных, ACK */
+    I2C_State_SRDANA = I2C_ST_MODE_SRDANA,   /*!< FS ведомый приём - Принят байт данных, NACK */
+    I2C_State_STADPA = I2C_ST_MODE_STADPA,   /*!< FS ведомый передача - Принят адрес ведомого, ACK */
+    I2C_State_STAAPA = I2C_ST_MODE_STAAPA,   /*!< FS ведомый передача - Принят адрес ведомого, NACK */
+    I2C_State_STDAPA = I2C_ST_MODE_STDAPA,   /*!< FS ведомый передача - Отправлен байт данных, ACK */
+    I2C_State_STDANA = I2C_ST_MODE_STDANA,   /*!< FS ведомый передача - Отправлен байт данных, NACK */
+    I2C_State_SATADP = I2C_ST_MODE_SATADP,   /*!< FS ведомый передача отклика на тревогу - Принят адрес отклика на тревогу, ACK */
+    I2C_State_SATAAP = I2C_ST_MODE_SATAAP,   /*!< FS ведомый передача отклика на тревогу - Принят адрес отклика на тревогу после потери арбитража, ACK */
+    I2C_State_SATDAP = I2C_ST_MODE_SATDAP,   /*!< FS ведомый передача отклика на тревогу - Отправлен байт данных отклика на тревогу, ACK */
+    I2C_State_SATDAN = I2C_ST_MODE_SATDAN,   /*!< FS ведомый передача отклика на тревогу - Отправлен байт данных отклика на тревогу, NACK */
+    I2C_State_SSTOP = I2C_ST_MODE_SSTOP,     /*!< FS ведомый - Обнаружено состояние СТОП ведомого */
+    I2C_State_SGADPA = I2C_ST_MODE_SGADPA,   /*!< FS ведомый - Принят адрес общего вызова, ACK */
+    I2C_State_SDAAPA = I2C_ST_MODE_SDAAPA,   /*!< FS ведомый - Принят адрес общего вызова после потери арбитража, ACK */
+    I2C_State_BERROR = I2C_ST_MODE_BERROR,   /*!< Общий - Обнаружена ошибка шины (некорректный СТАРТ или СТОП) */
+    I2C_State_HMTMCOK = I2C_ST_MODE_HMTMCOK, /*!< HS мастер - Код мастера передан успешно - переход в режим HS */
+    I2C_State_HRSDONE = I2C_ST_MODE_HRSDONE, /*!< HS мастер - Сформировано состояние повторного СТАРТа */
+    I2C_State_HIDLARL = I2C_ST_MODE_HIDLARL, /*!< HS мастер - Потеря арбитража, переход в режим HS безадресного ведомого  */
+    I2C_State_HMTADPA = I2C_ST_MODE_HMTADPA, /*!< HS мастер передача - Отправлен адрес ведомого, ACK */
+    I2C_State_HMTADNA = I2C_ST_MODE_HMTADNA, /*!< HS мастер передача - Отправлен адрес ведомого, NACK */
+    I2C_State_HMTDAPA = I2C_ST_MODE_HMTDAPA, /*!< HS мастер передача - Отправлен байт данных, ACK */
+    I2C_State_HMTDANA = I2C_ST_MODE_HMTDANA, /*!< HS мастер передача - Отправлен байт данных, NACK */
+    I2C_State_HMRADPA = I2C_ST_MODE_HMRADPA, /*!< HS мастер приём - Отправлен адрес ведомого, ACK */
+    I2C_State_HMRADNA = I2C_ST_MODE_HMRADNA, /*!< HS мастер приём - Отправлен адрес ведомого, NACK */
+    I2C_State_HMRDAPA = I2C_ST_MODE_HMRDAPA, /*!< HS мастер приём - Принят байт данных, ACK */
+    I2C_State_HMRDANA = I2C_ST_MODE_HMRDANA, /*!< HS мастер приём - Принят байт данных, NACK */
+    I2C_State_HSRADPA = I2C_ST_MODE_HSRADPA, /*!< HS ведомый приём - Принят адрес ведомого, ACK */
+    I2C_State_HSRDAPA = I2C_ST_MODE_HSRDAPA, /*!< HS ведомый приём - Принят байт данных, ACK */
+    I2C_State_HSRDANA = I2C_ST_MODE_HSRDANA, /*!< HS ведомый приём - Принят байт данных, NACK */
+    I2C_State_HSTADPA = I2C_ST_MODE_HSTADPA, /*!< HS ведомый передача - Принят адрес ведомого, ACK */
+    I2C_State_HSTDAPA = I2C_ST_MODE_HSTDAPA, /*!< HS ведомый передача - Отправлен байт данных, ACK */
+    I2C_State_HSTDANA = I2C_ST_MODE_HSTDANA, /*!< HS ведомый передача - Отправлен байт данных, NACK */
+} I2C_State_TypeDef;
+
+/**
+  * @brief  Выбор предделителя тактовой частоты для счетчика простоя линии SCL
+  */
+typedef enum {
+    I2C_TimeoutClkDiv_Disable = I2C_CST_TOCDIV_Disable, /*!< Выключен, не тактируется */
+    I2C_TimeoutClkDiv_Div4 = I2C_CST_TOCDIV_Div4,       /*!< Деление на 4 */
+    I2C_TimeoutClkDiv_Div8 = I2C_CST_TOCDIV_Div8,       /*!< Деление на 8 */
+    I2C_TimeoutClkDiv_Div16 = I2C_CST_TOCDIV_Div16      /*!< Деление на 16 */
+} I2C_TimeoutClkDiv_TypeDef;
+#define IS_I2C_TIMEOUT_CLK_DIV(VALUE) (((VALUE) == I2C_TimeoutClkDiv_Disable) || \
+                                       ((VALUE) == I2C_TimeoutClkDiv_Div4) ||    \
+                                       ((VALUE) == I2C_TimeoutClkDiv_Div8) ||    \
+                                       ((VALUE) == I2C_TimeoutClkDiv_Div16))
+
+#define IS_I2C_TIMEOUT_LOAD_VAL(VALUE) ((VALUE) < 0x100)
+#define IS_I2C_DATA_VAL(VALUE) ((VALUE) < 0x100)
+#define IS_I2C_FS_DIV_LOW_VAL(VALUE) (((VALUE) < 0x80) && ((VALUE) > 0x3))
+#define IS_I2C_FS_DIV_HIGH_VAL(VALUE) ((VALUE) < 0x100)
+#define IS_I2C_HS_DIV_LOW_VAL(VALUE) (((VALUE) < 0x10) && ((VALUE) > 0x1))
+#define IS_I2C_HS_DIV_HIGH_VAL(VALUE) ((VALUE) < 0x100)
+#define IS_I2C_SLAVE_ADDR_VAL(VALUE) ((VALUE) < 0x80)
+#define IS_I2C_SLAVE_10_ADDR_VAL(VALUE) ((VALUE) < 0x8)
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Functions Функции
+  * @{
+  */
+
+/** @defgroup I2C_Exported_Functions_Clk Настройка тактирования
+  * @{
+  */
+
+void I2C_FSFreqConfig(uint32_t FSFreq, uint32_t I2CFreq);
+void I2C_HSFreqConfig(uint32_t HSFreq, uint32_t I2CFreq);
+
+/**
+  * @brief      Установка младшей части делителя частоты в режиме FS мастера.
+  * @attention  Можно записать любое значение в диапазоне от 4 до 127. При попытке
+  *             записи любого значения меньше 4, оно будет записано со смещением 4.
+  *             Например, при записи числа 2, к нему будет аппаратно добавлено
+  *             смещение 4 и, в итоге, в регистре окажется значение 6.
+  * @param      DivVal  Значение (биты [6:0])
+  * @retval     void
+  */
+__STATIC_INLINE void I2C_FSDivLowConfig(uint32_t DivVal)
+{
+    assert_param(IS_I2C_FS_DIV_LOW_VAL(DivVal));
+
+    WRITE_REG(I2C->CTL1_bit.SCLFRQ, DivVal);
+}
+
+/**
+  * @brief   Установка старшей части делителя частоты в режиме FS мастера
+  * @param   DivVal  Значение (биты [7:0])
+  * @retval  void
+  */
+__STATIC_INLINE void I2C_FSDivHighConfig(uint32_t DivVal)
+{
+    assert_param(IS_I2C_FS_DIV_HIGH_VAL(DivVal));
+
+    WRITE_REG(I2C->CTL3_bit.SCLFRQ, DivVal);
+}
+
+/**
+  * @brief      Установка младшей части делителя частоты в режиме HS мастера.
+  * @attention  Можно записать любое значение в диапазоне от 2 до 15. При попытке
+  *             записи любого значения меньше 2, оно будет записано со смещением 2.
+  *             Например, при записи числа 1, к нему будет аппаратно добавлено
+  *             смещение 2 и, в итоге, в регистре окажется значение 3.
+  * @param      DivVal  Значение (биты [3:0])
+  * @retval     void
+  */
+__STATIC_INLINE void I2C_HSDivLowConfig(uint32_t DivVal)
+{
+    assert_param(IS_I2C_HS_DIV_LOW_VAL(DivVal));
+
+    WRITE_REG(I2C->CTL2_bit.HSDIV, DivVal);
+}
+
+/**
+  * @brief   Установка старшей части делителя частоты в режиме HS мастера
+  * @param   DivVal  Значение (биты [7:0])
+  * @retval  void
+  */
+__STATIC_INLINE void I2C_HSDivHighConfig(uint32_t DivVal)
+{
+    assert_param(IS_I2C_HS_DIV_HIGH_VAL(DivVal));
+
+    WRITE_REG(I2C->CTL4_bit.HSDIV, DivVal);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Functions_CtrlStatus Общее управление и статусная информация
+  * @{
+  */
+
+/**
+  * @brief   Включение модуля I2C
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void I2C_Cmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(I2C->CTL1_bit.ENABLE, State);
+}
+
+/**
+  * @brief   Получение состояния внутренней машины состояний I2C
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE I2C_State_TypeDef I2C_GetState(void)
+{
+    return (I2C_State_TypeDef)READ_REG(I2C->ST_bit.MODE);
+}
+
+/**
+  * @brief   Установка байта данных I2C
+  * @param   DataVal  Значение
+  * @retval  void
+  */
+__STATIC_INLINE void I2C_SetData(uint32_t DataVal)
+{
+    assert_param(IS_I2C_DATA_VAL(DataVal));
+
+    WRITE_REG(I2C->SDA, DataVal);
+}
+
+/**
+  * @brief   Получение байта данных I2C
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t I2C_GetData(void)
+{
+    return READ_REG(I2C->SDA);
+}
+
+/**
+  * @brief   Чтение статуса флага занятости шины
+  * @retval  Status  Статус
+  */
+__STATIC_INLINE FlagStatus I2C_BusBusyStatus(void)
+{
+    return (FlagStatus)READ_BIT(I2C->CST, I2C_CST_BB_Msk);
+}
+
+/**
+  * @brief   Чтение статуса флага ошибки сравнения контрольной суммы
+  * @retval  Status  Статус
+  */
+__STATIC_INLINE FlagStatus I2C_PECFailStatus(void)
+{
+    return (FlagStatus)READ_BIT(I2C->CST, I2C_CST_PECFAULT_Msk);
+}
+
+/**
+  * @brief   Чтение текущего состояния линии SDA
+  * @retval  Status  Статус
+  */
+__STATIC_INLINE FlagStatus I2C_SDAStatus(void)
+{
+    return (FlagStatus)READ_BIT(I2C->CST, I2C_CST_TSDA_Msk);
+}
+
+/**
+  * @brief   Включение режима распознавания адреса отклика на тревогу
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void I2C_AlertResponseMatchCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(I2C->CTL0_bit.SMBARE, State);
+}
+
+/**
+  * @brief   Включение режима распознавания адреса общего вызова
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void I2C_GlobalCallMatchCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(I2C->CTL0_bit.GCMEN, State);
+}
+
+/**
+  * @brief   Следующий переданный/принятый байт будет байтом контрольной суммы
+  * @retval  void
+  */
+__STATIC_INLINE void I2C_PECCmd(void)
+{
+    WRITE_REG(I2C->CST_bit.PECNEXT, 1);
+}
+
+/**
+  * @brief   Принудительное переключение сигнала SCL на один такт, когда на SDA низкий уровень
+  * @retval  void
+  */
+__STATIC_INLINE void I2C_ToggleSCL(void)
+{
+    WRITE_REG(I2C->CST_bit.TGSCL, 1);
+}
+
+/**
+  * @brief   Формирование состояния СТАРТ
+  * @retval  void
+  */
+__STATIC_INLINE void I2C_StartCmd(void)
+{
+    WRITE_REG(I2C->CTL0_bit.START, 1);
+}
+
+/**
+  * @brief   Формирование состояния СТОП
+  * @retval  void
+  */
+__STATIC_INLINE void I2C_StopCmd(void)
+{
+    WRITE_REG(I2C->CTL0_bit.STOP, 1);
+}
+
+/**
+  * @brief   Передача значения NACK в ответе на запрос передатчика
+  * @retval  void
+  */
+__STATIC_INLINE void I2C_NACKCmd(void)
+{
+    WRITE_REG(I2C->CTL0_bit.ACK, 1);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Functions_SlaveMode Управление режимом ведомого
+  * @{
+  */
+
+/**
+  * @brief   Включение режима распознавания принятого адреса (режим ведомого)
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void I2C_SlaveCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(I2C->ADDR_bit.SAEN, State);
+}
+
+/**
+  * @brief   Задание собственного адреса ведомого
+  * @param   AddrVal  Значение адреса (биты [6:0])
+  * @retval  void
+  */
+__STATIC_INLINE void I2C_SetSlaveAddr(uint32_t AddrVal)
+{
+    assert_param(IS_I2C_SLAVE_ADDR_VAL(AddrVal));
+
+    WRITE_REG(I2C->ADDR_bit.ADDR, AddrVal);
+}
+
+/**
+  * @brief   Получение собственного адреса ведомого
+  * @retval  Val  Значение адреса (биты [6:0])
+  */
+__STATIC_INLINE uint32_t I2C_GetSlaveAddr(void)
+{
+    return READ_REG(I2C->ADDR_bit.ADDR);
+}
+
+/**
+  * @brief   Включение режима 10-битной адресации ведомого
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void I2C_Slave10AddrCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(I2C->CTL2_bit.S10EN, State);
+}
+
+/**
+  * @brief   Задание старшей части 10-битного адреса ведомого.
+  *          Два байта адреса формируются следующим образом:
+  *          [11110b, S10ADDR[2:1]] и [S10ADDR[0], ADDR[6:0]].
+  * @param   AddrVal  Значение адреса (биты [2:0])
+  * @retval  void
+  */
+__STATIC_INLINE void I2C_SetSlave10Addr(uint32_t Addr10Val)
+{
+    assert_param(IS_I2C_SLAVE_10_ADDR_VAL(Addr10Val));
+
+    WRITE_REG(I2C->CTL2_bit.S10ADR, Addr10Val);
+}
+
+/**
+  * @brief   Получение старшей части 10-битного адреса ведомого
+  * @retval  Val  Значение адреса (биты [2:0])
+  */
+__STATIC_INLINE uint32_t I2C_GetSlave10Addr(void)
+{
+    return READ_REG(I2C->CTL2_bit.S10ADR);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Functions_Timeout Контроль простоя шины
+  * @{
+  */
+
+/**
+  * @brief   Устанавливает коэффициент деления тактового сигнала,
+  *          подаваемого на предделитель времени простоя линии SCL
+  * @param   TimeoutClkDiv  Выбор делителя
+  * @retval  void
+  */
+__STATIC_INLINE void I2C_TimeoutClkDivConfig(I2C_TimeoutClkDiv_TypeDef TimeoutClkDiv)
+{
+    assert_param(IS_I2C_TIMEOUT_CLK_DIV(TimeoutClkDiv));
+
+    WRITE_REG(I2C->CST_bit.TOCDIV, TimeoutClkDiv);
+}
+
+/**
+  * @brief   Установка значения загрузки счетчика времени простоя
+  * @param   LoadVal  Значение
+  * @retval  void
+  */
+__STATIC_INLINE void I2C_SetTimeoutCounterLoad(uint32_t LoadVal)
+{
+    assert_param(IS_I2C_TIMEOUT_LOAD_VAL(LoadVal));
+
+    WRITE_REG(I2C->TOPR, LoadVal);
+}
+
+/**
+  * @brief   Получение значения загрузки счетчика времени простоя
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t I2C_GetTimeoutCounterLoad(void)
+{
+    return READ_REG(I2C->TOPR);
+}
+
+/**
+  * @brief   Чтение статуса флага ошибки простоя I2C
+  * @retval  Status  Статус
+  */
+__STATIC_INLINE FlagStatus I2C_TimeoutStatus(void)
+{
+    return (FlagStatus)READ_BIT(I2C->CST, I2C_CST_TOERR_Msk);
+}
+
+/**
+  * @brief   Сброс флага ошибки простоя I2C
+  * @retval  void
+  */
+__STATIC_INLINE void I2C_TimeoutStatusClear(void)
+{
+    WRITE_REG(I2C->CTL0_bit.CLRST, 1);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Functions_IT Прерывания
+  * @{
+  */
+
+/**
+  * @brief   Включение генерации прерывания I2C
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void I2C_ITCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(I2C->CTL0_bit.INTEN, State);
+}
+
+/**
+  * @brief   Чтение статуса флага прерывания I2C
+  * @retval  Status  Статус
+  */
+__STATIC_INLINE FlagStatus I2C_ITStatus(void)
+{
+    return (FlagStatus)READ_BIT(I2C->ST, I2C_ST_INT_Msk);
+}
+
+/**
+  * @brief   Сброс флага прерывания I2C
+  * @retval  void
+  */
+__STATIC_INLINE void I2C_ITStatusClear(void)
+{
+    WRITE_REG(I2C->CTL0_bit.CLRST, 1);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PLIB035_I2C_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2018 NIIET *****END OF FILE****/

platform/plib035/inc/plib035_mflash.h

@@ -0,0 +1,327 @@
+/**
+  ******************************************************************************
+  * @file    plib035_mflash.h
+  *
+  * @brief   Файл содержит прототипы и компактные inline реализации функций для
+  *          MFLASH, а также сопутствующие макроопределения и перечисления
+  *
+  * @author  НИИЭТ, Богдан Колбов <kolbov@niiet.ru>
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ ПРЕДОСТАВЛЯЕТСЯ «КАК ЕСТЬ», БЕЗ КАКИХ-ЛИБО
+  * ГАРАНТИЙ, ЯВНО ВЫРАЖЕННЫХ ИЛИ ПОДРАЗУМЕВАЕМЫХ, ВКЛЮЧАЯ ГАРАНТИИ ТОВАРНОЙ
+  * ПРИГОДНОСТИ, СООТВЕТСТВИЯ ПО ЕГО КОНКРЕТНОМУ НАЗНАЧЕНИЮ И ОТСУТСТВИЯ
+  * НАРУШЕНИЙ, НО НЕ ОГРАНИЧИВАЯСЬ ИМИ. ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ
+  * ПРЕДНАЗНАЧЕНО ДЛЯ ОЗНАКОМИТЕЛЬНЫХ ЦЕЛЕЙ И НАПРАВЛЕНО ТОЛЬКО НА
+  * ПРЕДОСТАВЛЕНИЕ ДОПОЛНИТЕЛЬНОЙ ИНФОРМАЦИИ О ПРОДУКТЕ, С ЦЕЛЬЮ СОХРАНИТЬ ВРЕМЯ
+  * ПОТРЕБИТЕЛЮ. НИ В КАКОМ СЛУЧАЕ АВТОРЫ ИЛИ ПРАВООБЛАДАТЕЛИ НЕ НЕСУТ
+  * ОТВЕТСТВЕННОСТИ ПО КАКИМ-ЛИБО ИСКАМ, ЗА ПРЯМОЙ ИЛИ КОСВЕННЫЙ УЩЕРБ, ИЛИ
+  * ПО ИНЫМ ТРЕБОВАНИЯМ, ВОЗНИКШИМ ИЗ-ЗА ИСПОЛЬЗОВАНИЯ ПРОГРАММНОГО ОБЕСПЕЧЕНИЯ
+  * ИЛИ ИНЫХ ДЕЙСТВИЙ С ПРОГРАММНЫМ ОБЕСПЕЧЕНИЕМ.
+  *
+  * <h2><center>&copy; 2018 ОАО "НИИЭТ"</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PLIB035_MFLASH_H
+#define __PLIB035_MFLASH_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "plib035.h"
+
+/** @addtogroup Peripheral
+  * @{
+  */
+
+/** @defgroup MFLASH
+  * @brief Драйвер для работы с MFLASH
+  * @{
+  */
+
+/** @defgroup MFLASH_Exported_Defines Константы
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MFLASH_Exported_Types Типы
+  * @{
+  */
+
+/**
+  * @brief  Команды контроллера флеш-памяти
+  */
+typedef enum {
+    MFLASH_Cmd_Read = MFLASH_CMD_RD_Msk,         /*!< Команда чтения */
+    MFLASH_Cmd_Write = MFLASH_CMD_WR_Msk,        /*!< Команда записи */
+    MFLASH_Cmd_EraseFull = MFLASH_CMD_ERALL_Msk, /*!< Команда стирания всей памяти */
+    MFLASH_Cmd_ErasePage = MFLASH_CMD_ERSEC_Msk, /*!< Команда стирания страницы */
+} MFLASH_Cmd_TypeDef;
+#define IS_MFLASH_CMD(VALUE) (((VALUE) == MFLASH_Cmd_Read) ||      \
+                              ((VALUE) == MFLASH_Cmd_Write) ||     \
+                              ((VALUE) == MFLASH_Cmd_EraseFull) || \
+                              ((VALUE) == MFLASH_Cmd_ErasePage))
+
+/**
+  * @brief  Выбор региона флеш-памяти для исполнения команд
+  */
+typedef enum {
+    MFLASH_Region_Main = 0UL,                 /*!< Основная область */
+    MFLASH_Region_NVR = MFLASH_CMD_NVRON_Msk, /*!< NVR область (загрузочная) */
+} MFLASH_Region_TypeDef;
+#define IS_MFLASH_REGION(VALUE) (((VALUE) == MFLASH_Region_Main) || \
+                                 ((VALUE) == MFLASH_Region_NVR))
+
+#define IS_MFLASH_MAIN_ADDR(MAIN_ADDR) (MAIN_ADDR < MEM_MFLASH_SIZE)
+#define IS_MFLASH_MAIN_PAGE_NUM(MAIN_PAGE_NUM) (MAIN_PAGE_NUM < MEM_MFLASH_PAGE_TOTAL)
+#define IS_MFLASH_NVR_ADDR(NVR_ADDR) (NVR_ADDR < MEM_MFLASH_NVR_SIZE)
+#define IS_MFLASH_NVR_PAGE_NUM(NVR_PAGE_NUM) (NVR_PAGE_NUM < MEM_MFLASH_NVR_PAGE_TOTAL)
+#define IS_MFLASH_DATA_NUM(DATA_NUM) (DATA_NUM < MEM_MFLASH_BUS_WIDTH_WORDS)
+#define IS_MFLASH_LATENCY(LATENCY) (LATENCY < 15)
+
+/**
+  * @}
+  */
+
+/** @defgroup MFLASH_Exported_Functions Функции
+  * @{
+  */
+
+/** @defgroup MFLASH_Cmd Управление контроллером флеш-памяти
+  * @{
+  */
+
+/**
+  * @brief   Установка значения адреса
+  * @param   AddrVal  Значение адреса
+  * @retval  void
+  */
+__STATIC_INLINE void MFLASH_SetAddr(uint32_t AddrVal)
+{
+    WRITE_REG(MFLASH->ADDR, AddrVal);
+}
+
+/**
+  * @brief   Установка выбранного слова данных
+  * @param   DataNum  Номер слова данных
+  * @param   DataVal  Значение слова данных
+  * @retval  void
+  */
+__STATIC_INLINE void MFLASH_SetData(uint32_t DataNum, uint32_t DataVal)
+{
+    assert_param(IS_MFLASH_DATA_NUM(DataNum));
+
+    WRITE_REG(MFLASH->DATA[DataNum].DATA, DataVal);
+}
+
+/**
+  * @brief   Получение выбранного слова данных
+  * @param   DataNum  Номер слова данных
+  * @retval  Val  Значение слова данных
+  */
+__STATIC_INLINE uint32_t MFLASH_GetData(uint32_t DataNum)
+{
+    assert_param(IS_MFLASH_DATA_NUM(DataNum));
+
+    return READ_REG(MFLASH->DATA[DataNum].DATA);
+}
+
+/**
+  * @brief   Передача команды контроллеру флеш-памяти
+  * @param   Cmd  Команда
+  * @param   Region  Область
+  * @retval  void
+  */
+__STATIC_INLINE void MFLASH_SetCmd(MFLASH_Cmd_TypeDef Cmd, MFLASH_Region_TypeDef Region)
+{
+    WRITE_REG(MFLASH->CMD, ((uint32_t)MFLASH_CMD_KEY_Access << MFLASH_CMD_KEY_Pos) | (uint32_t)Region | (uint32_t)Cmd);
+}
+
+/**
+  * @brief   Получение статуса занятости контроллера флеш-памяти
+  * @retval  Status
+  */
+__STATIC_INLINE FlagStatus MFLASH_BusyStatus(void)
+{
+    return (FlagStatus)READ_BIT(MFLASH->STAT, MFLASH_STAT_BUSY_Msk);
+}
+
+void MFLASH_ReadData(uint32_t AddrVal, uint32_t* DataArr, MFLASH_Region_TypeDef Region);
+void MFLASH_WriteData(uint32_t AddrVal, uint32_t* DataArr, MFLASH_Region_TypeDef Region);
+void MFLASH_ErasePage(uint32_t AddrVal, MFLASH_Region_TypeDef Region);
+void MFLASH_EraseFull(MFLASH_Region_TypeDef Region);
+
+/**
+  * @}
+  */
+
+/** @defgroup MFLASH_ExecCtrl Настройка исполнения программ
+  * @{
+  */
+
+/**
+  * @brief   Настройка количества тактов ожидания чтения из флеш
+  * @param   LatencyVal  Значение
+  * @retval  void
+  */
+__STATIC_INLINE void MFLASH_LatencyConfig(uint32_t LatencyVal)
+{
+    assert_param(IS_MFLASH_LATENCY(LatencyVal));
+
+    WRITE_REG(MFLASH->CTRL_bit.LAT, LatencyVal);
+}
+
+/**
+  * @brief   Разрешение работы кэша инструкций
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void MFLASH_ICacheCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(MFLASH->CTRL_bit.ICEN, State);
+}
+
+/**
+  * @brief   Очистка кэша инструкций
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void MFLASH_ICacheFlushCmd(void)
+{
+    WRITE_REG(MFLASH->CTRL_bit.IFLUSH, 1);
+}
+
+/**
+  * @brief   Получение статуса занятости очистки кэша инструкций
+  * @retval  Status
+  */
+__STATIC_INLINE FlagStatus MFLASH_ICacheBusyStatus(void)
+{
+    return (FlagStatus)READ_BIT(MFLASH->ICSTAT, MFLASH_ICSTAT_BUSY_Msk);
+}
+
+/**
+  * @brief   Разрешение работы кэша данных
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void MFLASH_DCacheCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(MFLASH->CTRL_bit.DCEN, State);
+}
+
+/**
+  * @brief   Очистка кэша данных
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void MFLASH_DCacheFlushCmd(void)
+{
+    WRITE_REG(MFLASH->CTRL_bit.DFLUSH, 1);
+}
+
+/**
+  * @brief   Получение статуса занятости очистки кэша данных
+  * @retval  Status
+  */
+__STATIC_INLINE FlagStatus MFLASH_DCacheBusyStatus(void)
+{
+    return (FlagStatus)READ_BIT(MFLASH->DCSTAT, MFLASH_DCSTAT_BUSY_Msk);
+}
+
+/**
+  * @brief   Разрешение работы предвыборки
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void MFLASH_PrefetchCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(MFLASH->CTRL_bit.PEN, State);
+}
+
+/**
+  * @brief   Отключение старта из загрузчоной памяти после следующего программного сброса.
+  *          Оказывает влияние только если в CFGWORD активирован старт из загрузочной области.
+  * @retval  void
+  */
+__STATIC_INLINE void MFLASH_BootDisableCmd(void)
+{
+    WRITE_REG(MFLASH->BDIS, MFLASH_BDIS_BMDIS_Msk);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup MFLASH_IRQ Прерывания
+  * @{
+  */
+
+/**
+  * @brief   Разрешение работы прерывания MFLASH
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void MFLASH_ITCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(MFLASH->CTRL_bit.IRQEN, State);
+}
+
+/**
+  * @brief   Получение статуса прерывания
+  * @retval  Status
+  */
+__STATIC_INLINE FlagStatus MFLASH_ITStatus(void)
+{
+    return (FlagStatus)READ_BIT(MFLASH->STAT, MFLASH_STAT_IRQF_Msk);
+}
+
+/**
+  * @brief   Сброс статуса прерывания
+  * @retval  void
+  */
+__STATIC_INLINE void MFLASH_ITStatusClear(void)
+{
+    WRITE_REG(MFLASH->STAT, MFLASH_STAT_IRQF_Msk);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PLIB035_MFLASH_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2018 NIIET *****END OF FILE****/

platform/plib035/inc/plib035_pmu.h

@@ -0,0 +1,162 @@
+/**
+  ******************************************************************************
+  * @file    plib035_pmu.h
+  *
+  * @brief   Файл содержит прототипы и компактные inline реализации функций для
+  *          PMU, а также сопутствующие макроопределения и перечисления
+  *
+  * @author  НИИЭТ, Богдан Колбов <kolbov@niiet.ru>
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ ПРЕДОСТАВЛЯЕТСЯ «КАК ЕСТЬ», БЕЗ КАКИХ-ЛИБО
+  * ГАРАНТИЙ, ЯВНО ВЫРАЖЕННЫХ ИЛИ ПОДРАЗУМЕВАЕМЫХ, ВКЛЮЧАЯ ГАРАНТИИ ТОВАРНОЙ
+  * ПРИГОДНОСТИ, СООТВЕТСТВИЯ ПО ЕГО КОНКРЕТНОМУ НАЗНАЧЕНИЮ И ОТСУТСТВИЯ
+  * НАРУШЕНИЙ, НО НЕ ОГРАНИЧИВАЯСЬ ИМИ. ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ
+  * ПРЕДНАЗНАЧЕНО ДЛЯ ОЗНАКОМИТЕЛЬНЫХ ЦЕЛЕЙ И НАПРАВЛЕНО ТОЛЬКО НА
+  * ПРЕДОСТАВЛЕНИЕ ДОПОЛНИТЕЛЬНОЙ ИНФОРМАЦИИ О ПРОДУКТЕ, С ЦЕЛЬЮ СОХРАНИТЬ ВРЕМЯ
+  * ПОТРЕБИТЕЛЮ. НИ В КАКОМ СЛУЧАЕ АВТОРЫ ИЛИ ПРАВООБЛАДАТЕЛИ НЕ НЕСУТ
+  * ОТВЕТСТВЕННОСТИ ПО КАКИМ-ЛИБО ИСКАМ, ЗА ПРЯМОЙ ИЛИ КОСВЕННЫЙ УЩЕРБ, ИЛИ
+  * ПО ИНЫМ ТРЕБОВАНИЯМ, ВОЗНИКШИМ ИЗ-ЗА ИСПОЛЬЗОВАНИЯ ПРОГРАММНОГО ОБЕСПЕЧЕНИЯ
+  * ИЛИ ИНЫХ ДЕЙСТВИЙ С ПРОГРАММНЫМ ОБЕСПЕЧЕНИЕМ.
+  *
+  * <h2><center>&copy; 2018 ОАО "НИИЭТ"</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PLIB035_PMU_H
+#define __PLIB035_PMU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "plib035.h"
+
+/** @addtogroup Peripheral
+  * @{
+  */
+
+/** @defgroup PMU
+  * @brief Драйвер для работы с PMU
+  * @{
+  */
+
+/** @defgroup PMU_Exported_Defines Константы
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PMU_Exported_Types Типы
+  * @{
+  */
+
+/**
+  * @brief  Управление режимом powerdown выбранного блока периферии
+  */
+typedef enum {
+    PMU_PeriphPD_PLL = PMU_PDEN_PLLPD_Msk,       /*!< Управление режимом powerdown PLL */
+    PMU_PeriphPD_MFLASH = PMU_PDEN_MFLASHPD_Msk, /*!< Управление режимом powerdown MFLASH */
+    PMU_PeriphPD_OSE = PMU_PDEN_OSEPD_Msk        /*!< Управление режимом powerdown OSE */
+} PMU_PeriphPD_TypeDef;
+#define IS_PMU_PERIPH_PD(VALUE) (((VALUE) == PMU_PeriphPD_PLL) ||    \
+                                 ((VALUE) == PMU_PeriphPD_MFLASH) || \
+                                 ((VALUE) == PMU_PeriphPD_OSE))
+
+/**
+  * @brief  Управление разрешением получения событий RXEV от портов
+  */
+typedef enum {
+    PMU_RXEV_GPIOA = PMU_RXEVEN_GPIOAEV_Msk, /*!< Управление разрешением получения событий RXEV от GPIOA */
+    PMU_RXEV_GPIOB = PMU_RXEVEN_GPIOBEV_Msk, /*!< Управление разрешением получения событий RXEV от GPIOB */
+} PMU_RXEV_TypeDef;
+#define IS_PMU_RXEV(VALUE) (((VALUE) == PMU_RXEV_GPIOA) || \
+                            ((VALUE) == PMU_RXEV_GPIOB))
+
+#define IS_PMU_POWERUP_DELAY(VALUE) (((VALUE)&0xFFFF0000) == 0)
+
+/**
+  * @}
+  */
+
+/** @defgroup PMU_Exported_Functions Функции
+  * @{
+  */
+
+/**
+  * @brief   Разрешение работы PMU - необходимо для перехода в режим Deepsleep
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void PMU_Cmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(PMU->CFG_bit.EN, State);
+}
+
+/**
+  * @brief   Настройка задержки выхода из сна в тактах OSI
+  * @param   DelayVal  Величина хадержки
+  * @retval  void
+  */
+__STATIC_INLINE void PMU_PowerUpDelayConfig(uint32_t DelayVal)
+{
+    assert_param(IS_PMU_POWERUP_DELAY(DelayVal));
+
+    WRITE_REG(PMU->PUDEL, DelayVal);
+}
+
+/**
+  * @brief   Управление режимом powerdown выбранного блока периферии
+  * @param   PeriphPD  Выбор периферии
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void PMU_PeriphPDCmd(PMU_PeriphPD_TypeDef PeriphPD, FunctionalState State)
+{
+    assert_param(IS_PMU_PERIPH_PD(PeriphPD));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    MODIFY_REG(PMU->PDEN, PeriphPD, State ? (uint32_t)PeriphPD : 0);
+}
+
+/**
+  * @brief   Управление разрешением получения событий RXEV от портов
+  * @param   RXEV  Выбор порта
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void PMU_RXEVCmd(PMU_RXEV_TypeDef RXEV, FunctionalState State)
+{
+    assert_param(IS_PMU_RXEV(RXEV));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    MODIFY_REG(PMU->RXEVEN, RXEV, State ? (uint32_t)RXEV : 0);
+}
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PLIB035_PMU_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2018 NIIET *****END OF FILE****/

platform/plib035/inc/plib035_pwm.h

@@ -0,0 +1,2038 @@
+/**
+  ******************************************************************************
+  * @file    plib035_pwm.h
+  *
+  * @brief   Файл содержит прототипы и компактные inline реализации функций для
+  *          PWM, а также сопутствующие макроопределения и перечисления
+  *
+  * @author  НИИЭТ, Богдан Колбов <kolbov@niiet.ru>
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ ПРЕДОСТАВЛЯЕТСЯ «КАК ЕСТЬ», БЕЗ КАКИХ-ЛИБО
+  * ГАРАНТИЙ, ЯВНО ВЫРАЖЕННЫХ ИЛИ ПОДРАЗУМЕВАЕМЫХ, ВКЛЮЧАЯ ГАРАНТИИ ТОВАРНОЙ
+  * ПРИГОДНОСТИ, СООТВЕТСТВИЯ ПО ЕГО КОНКРЕТНОМУ НАЗНАЧЕНИЮ И ОТСУТСТВИЯ
+  * НАРУШЕНИЙ, НО НЕ ОГРАНИЧИВАЯСЬ ИМИ. ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ
+  * ПРЕДНАЗНАЧЕНО ДЛЯ ОЗНАКОМИТЕЛЬНЫХ ЦЕЛЕЙ И НАПРАВЛЕНО ТОЛЬКО НА
+  * ПРЕДОСТАВЛЕНИЕ ДОПОЛНИТЕЛЬНОЙ ИНФОРМАЦИИ О ПРОДУКТЕ, С ЦЕЛЬЮ СОХРАНИТЬ ВРЕМЯ
+  * ПОТРЕБИТЕЛЮ. НИ В КАКОМ СЛУЧАЕ АВТОРЫ ИЛИ ПРАВООБЛАДАТЕЛИ НЕ НЕСУТ
+  * ОТВЕТСТВЕННОСТИ ПО КАКИМ-ЛИБО ИСКАМ, ЗА ПРЯМОЙ ИЛИ КОСВЕННЫЙ УЩЕРБ, ИЛИ
+  * ПО ИНЫМ ТРЕБОВАНИЯМ, ВОЗНИКШИМ ИЗ-ЗА ИСПОЛЬЗОВАНИЯ ПРОГРАММНОГО ОБЕСПЕЧЕНИЯ
+  * ИЛИ ИНЫХ ДЕЙСТВИЙ С ПРОГРАММНЫМ ОБЕСПЕЧЕНИЕМ.
+  *
+  * <h2><center>&copy; 2018 ОАО "НИИЭТ"</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PLIB035_PWM_H
+#define __PLIB035_PWM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "plib035.h"
+
+/** @addtogroup Peripheral
+  * @{
+  */
+
+/** @defgroup PWM
+  * @brief Драйвер для работы с PWM
+  * @{
+  */
+
+/** @defgroup PWM_Exported_Defines Константы
+  * @{
+  */
+
+/** @defgroup PWM_TB_Status_Define Статусы счетчика
+  * @{
+  */
+
+#define PWM_TB_Status_CountDir PWM_TBSTS_CTRDIR_Msk /*!< Направление счета */
+#define PWM_TB_Status_SyncIn PWM_TBSTS_SYNCI_Msk    /*!< Произошло событие синхронизации */
+#define PWM_TB_Status_CountMax PWM_TBSTS_CTRMAX_Msk /*!< Таймер достиг максимального значения 0xFFFF */
+#define PWM_TB_Status_All (PWM_TB_Status_CountDir | \
+                           PWM_TB_Status_SyncIn |   \
+                           PWM_TB_Status_CountMax) /*!< Все статусы выбраны */
+
+#define IS_PWM_TB_STATUS(VALUE) (((VALUE) & ~PWM_TB_Status_All) == 0)
+
+/**
+  * @}
+  */
+
+/** @defgroup PWM_CMP_Status_Define Статусы компаратора
+  * @{
+  */
+
+#define PWM_CMP_Status_ShadowLoadedA PWM_CMPCTL_SHDWAFULL_Msk /*!< Произошла теневая загрузка в CMPA */
+#define PWM_CMP_Status_ShadowLoadedB PWM_CMPCTL_SHDWBFULL_Msk /*!< Произошла теневая загрузка в CMPB */
+#define PWM_CMP_Status_All (PWM_CMP_Status_ShadowLoadedA | \
+                            PWM_CMP_Status_ShadowLoadedB) /*!< Все статусы выбраны */
+
+#define IS_PWM_CMP_STATUS(VALUE) (((VALUE) & ~PWM_CMP_Status_All) == 0)
+
+/**
+  * @}
+  */
+
+/** @defgroup PWM_Presc_Define Управление предделителями таймеров блоков ШИМ
+  * @{
+  */
+
+#define PWM_TB_Presc_0 (0x1UL << SIU_PWMSYNC_PRESCRST_Pos) /*!< Предделитель блока ШИМ0 */
+#define PWM_TB_Presc_1 (0x2UL << SIU_PWMSYNC_PRESCRST_Pos) /*!< Предделитель блока ШИМ1 */
+#define PWM_TB_Presc_2 (0x4UL << SIU_PWMSYNC_PRESCRST_Pos) /*!< Предделитель блока ШИМ2 */
+#define PWM_TB_Presc_All (PWM_TB_Presc_0 | \
+                          PWM_TB_Presc_1 | \
+                          PWM_TB_Presc_2) /*!< Все блоки выбраны */
+
+#define IS_PWM_TB_PRESC(VALUE) (((VALUE) & ~PWM_TB_Presc_All) == 0)
+
+/**
+  * @}
+  */
+
+/** @defgroup PWM_TZ_ITSource_Define Источники прерываний блока сигналов аварий ШИМ
+  * @{
+  */
+
+#define PWM_TZ_ITSource_Cycle PWM_TZEINT_CBC_Msk   /*!< Циклический обработчик сигнала аварии */
+#define PWM_TZ_ITSource_OneShot PWM_TZEINT_OST_Msk /*!< Однократный обработчик сигнала аварии */
+#define PWM_TZ_ITSource_All (PWM_TZ_ITSource_Cycle | \
+                             PWM_TZ_ITSource_OneShot) /*!< Все источники выбраны */
+
+#define IS_PWM_TZ_IT_SOURCE(IT_SOURCE) (((IT_SOURCE) & ~PWM_TZ_ITSource_All) == 0)
+
+/**
+  * @}
+  */
+
+/** @defgroup PWM_TZ_ITStatus_Define Флаги прерываний блока сигналов аварий ШИМ
+  * @{
+  */
+
+#define PWM_TZ_ITStatus_Int PWM_TZFLG_INT_Msk     /*!< Флаг прерывания NVIC */
+#define PWM_TZ_ITStatus_Cycle PWM_TZFLG_CBC_Msk   /*!< Циклический обработчик сигнала аварии */
+#define PWM_TZ_ITStatus_OneShot PWM_TZFLG_OST_Msk /*!< Однократный обработчик сигнала аварии */
+#define PWM_TZ_ITStatus_All (PWM_TZ_ITStatus_Int |   \
+                             PWM_TZ_ITStatus_Cycle | \
+                             PWM_TZ_ITStatus_OneShot) /*!< Все флаги выбраны */
+
+#define IS_PWM_TZ_IT_STATUS(VALUE) (((VALUE) & ~PWM_TZ_ITStatus_All) == 0)
+
+/**
+  * @}
+  */
+
+/** @defgroup PWM_ET_Status_Define Флаги генерации событий запуска АЦП и DMA обработчиком событий
+  * @{
+  */
+
+#define PWM_ET_Status_SOCA PWM_ETFLG_SOCA_Msk /*!< Флаг генерации запуска АЦП от канала А */
+#define PWM_ET_Status_SOCB PWM_ETFLG_SOCB_Msk /*!< Флаг генерации запуска АЦП от канала B */
+#define PWM_ET_Status_DRQA PWM_ETFLG_DRQA_Msk /*!< Флаг генерации запроса DMA от канала А */
+#define PWM_ET_Status_DRQB PWM_ETFLG_DRQB_Msk /*!< Флаг генерации запроса DMA от канала B */
+#define PWM_ET_Status_All (PWM_ET_Status_SOCA | \
+                           PWM_ET_Status_SOCB | \
+                           PWM_ET_Status_DRQA | \
+                           PWM_ET_Status_DRQB) /*!< Все флаги выбраны */
+
+#define IS_PWM_ET_STATUS(VALUE) (((VALUE) & ~PWM_ET_Status_All) == 0)
+
+/**
+  * @}
+  */
+
+/** @defgroup PWM_HD_Source_Define Выбор источника события удержания
+  * @{
+  */
+
+#define PWM_HD_Source_ADCDC0 PWM_HDSEL_ADCDC0_Msk /*!< Сигнал от цифрового компаратора 0 АЦП */
+#define PWM_HD_Source_ADCDC1 PWM_HDSEL_ADCDC1_Msk /*!< Сигнал от цифрового компаратора 1 АЦП */
+#define PWM_HD_Source_ADCDC2 PWM_HDSEL_ADCDC2_Msk /*!< Сигнал от цифрового компаратора 2 АЦП */
+#define PWM_HD_Source_ADCDC3 PWM_HDSEL_ADCDC3_Msk /*!< Сигнал от цифрового компаратора 3 АЦП */
+#define PWM_HD_Source_All (PWM_HD_Source_ADCDC0 | \
+                           PWM_HD_Source_ADCDC1 | \
+                           PWM_HD_Source_ADCDC2 | \
+                           PWM_HD_Source_ADCDC3) /*!< Все источники выбраны */
+
+#define IS_PWM_HD_SOURCE(VALUE) (((VALUE) & ~PWM_HD_Source_All) == 0)
+
+/**
+  * @}
+  */
+
+/** @defgroup PWM_HD_ITSource_Define Источники прерываний блока cобытий удержания
+  * @{
+  */
+
+#define PWM_HD_ITSource_Cycle PWM_HDEINT_CBC_Msk   /*!< Циклический обработчик cобытия удержания */
+#define PWM_HD_ITSource_OneShot PWM_HDEINT_OST_Msk /*!< Однократный обработчик cобытия удержания */
+#define PWM_HD_ITSource_All (PWM_HD_ITSource_Cycle | \
+                             PWM_HD_ITSource_OneShot) /*!< Все источники выбраны */
+
+#define IS_PWM_HD_IT_SOURCE(VALUE) (((VALUE) & ~PWM_HD_ITSource_All) == 0)
+
+/**
+  * @}
+  */
+
+/** @defgroup PWM_HD_ITStatus_Define Флаги прерываний блока cобытий удержания
+  * @{
+  */
+
+#define PWM_HD_ITStatus_Int PWM_HDFLG_INT_Msk     /*!< Флаг прерывания NVIC */
+#define PWM_HD_ITStatus_Cycle PWM_HDFLG_CBC_Msk   /*!< Циклический обработчик cобытия удержания */
+#define PWM_HD_ITStatus_OneShot PWM_HDFLG_OST_Msk /*!< Однократный обработчик cобытия удержания */
+#define PWM_HD_ITStatus_All (PWM_HD_ITStatus_Int |   \
+                             PWM_HD_ITStatus_Cycle | \
+                             PWM_HD_ITStatus_OneShot) /*!< Все флаги выбраны */
+
+#define IS_PWM_HD_IT_STATUS(VALUE) (((VALUE) & ~PWM_HD_ITStatus_All) == 0)
+
+/**
+  * @}
+  */
+
+#define IS_PWM_IT_PERIOD(VALUE) ((VALUE) < 0x4)
+#define IS_PWM_FILTER(VALUE) ((VALUE) < 0x100)
+#define IS_PWM_PC_DUTY(VALUE) ((VALUE) < 0x7)
+#define IS_PWM_PC_FREQ_DIV(VALUE) ((VALUE) < 0x8)
+#define IS_PWM_PC_FIRST_WIDTH(VALUE) ((VALUE) < 0x10)
+
+/**
+  * @}
+  */
+
+/** @defgroup PWM_Exported_Types Типы
+  * @{
+  */
+
+/**
+  * @brief  Выбор режима остановки таймера при отладке
+  */
+typedef enum {
+    PWM_TB_Halt_StopOnTBCLK = PWM_TBCTL_FREESOFT_StopAtTBCLK,   /*!< Остановка таймера при отладке со следующего такта TBCLK */
+    PWM_TB_Halt_StopOnPeriod = PWM_TBCTL_FREESOFT_StopAtPeriod, /*!< Остановка таймера при отладке в конце периода */
+    PWM_TB_Halt_Free = PWM_TBCTL_FREESOFT_FreeRun               /*!< Без остановки */
+} PWM_TB_Halt_TypeDef;
+#define IS_PWM_TB_HALT(VALUE) (((VALUE) == PWM_TB_Halt_StopOnTBCLK) || \
+                               ((VALUE) == PWM_TB_Halt_StopOnPeriod))
+
+/**
+  * @brief  Коэффициент базового деления частоты
+  */
+typedef enum {
+    PWM_TB_ClkDiv_1 = PWM_TBCTL_CLKDIV_Div1,    /*!< Без деления тактовой частоты */
+    PWM_TB_ClkDiv_2 = PWM_TBCTL_CLKDIV_Div2,    /*!< Деление тактовой частоты на 2 */
+    PWM_TB_ClkDiv_4 = PWM_TBCTL_CLKDIV_Div4,    /*!< Деление тактовой частоты на 4 */
+    PWM_TB_ClkDiv_8 = PWM_TBCTL_CLKDIV_Div8,    /*!< Деление тактовой частоты на 8 */
+    PWM_TB_ClkDiv_16 = PWM_TBCTL_CLKDIV_Div16,  /*!< Деление тактовой частоты на 16 */
+    PWM_TB_ClkDiv_32 = PWM_TBCTL_CLKDIV_Div32,  /*!< Деление тактовой частоты на 32 */
+    PWM_TB_ClkDiv_64 = PWM_TBCTL_CLKDIV_Div64,  /*!< Деление тактовой частоты на 64 */
+    PWM_TB_ClkDiv_128 = PWM_TBCTL_CLKDIV_Div128 /*!< Деление тактовой частоты на 128 */
+} PWM_TB_ClkDiv_TypeDef;
+#define IS_PWM_TB_CLK_DIV(VALUE) (((VALUE) == PWM_TB_ClkDiv_1) ||  \
+                                  ((VALUE) == PWM_TB_ClkDiv_2) ||  \
+                                  ((VALUE) == PWM_TB_ClkDiv_4) ||  \
+                                  ((VALUE) == PWM_TB_ClkDiv_8) ||  \
+                                  ((VALUE) == PWM_TB_ClkDiv_16) || \
+                                  ((VALUE) == PWM_TB_ClkDiv_32) || \
+                                  ((VALUE) == PWM_TB_ClkDiv_64) || \
+                                  ((VALUE) == PWM_TB_ClkDiv_128))
+
+/**
+  * @brief  Коэффициент дополнительного деления частоты
+  */
+typedef enum {
+    PWM_TB_ClkDivExtra_1 = PWM_TBCTL_HSPCLKDIV_Div1,   /*!< Без дополнительного деления тактовой частоты */
+    PWM_TB_ClkDivExtra_2 = PWM_TBCTL_HSPCLKDIV_Div2,   /*!< Дополнительное деление тактовой частоты на 2 */
+    PWM_TB_ClkDivExtra_4 = PWM_TBCTL_HSPCLKDIV_Div4,   /*!< Дополнительное деление тактовой частоты на 4 */
+    PWM_TB_ClkDivExtra_6 = PWM_TBCTL_HSPCLKDIV_Div6,   /*!< Дополнительное деление тактовой частоты на 6 */
+    PWM_TB_ClkDivExtra_8 = PWM_TBCTL_HSPCLKDIV_Div8,   /*!< Дополнительное деление тактовой частоты на 8 */
+    PWM_TB_ClkDivExtra_10 = PWM_TBCTL_HSPCLKDIV_Div10, /*!< Дополнительное деление тактовой частоты на 10 */
+    PWM_TB_ClkDivExtra_12 = PWM_TBCTL_HSPCLKDIV_Div12, /*!< Дополнительное деление тактовой частоты на 12 */
+    PWM_TB_ClkDivExtra_14 = PWM_TBCTL_HSPCLKDIV_Div14, /*!< Дополнительное деление тактовой частоты на 14 */
+} PWM_TB_ClkDivExtra_TypeDef;
+#define IS_PWM_TB_CLK_DIV_EXTRA(VALUE) (((VALUE) == PWM_TB_ClkDivExtra_1) ||  \
+                                        ((VALUE) == PWM_TB_ClkDivExtra_2) ||  \
+                                        ((VALUE) == PWM_TB_ClkDivExtra_4) ||  \
+                                        ((VALUE) == PWM_TB_ClkDivExtra_6) ||  \
+                                        ((VALUE) == PWM_TB_ClkDivExtra_8) ||  \
+                                        ((VALUE) == PWM_TB_ClkDivExtra_10) || \
+                                        ((VALUE) == PWM_TB_ClkDivExtra_12) || \
+                                        ((VALUE) == PWM_TB_ClkDivExtra_14))
+
+/**
+  * @brief  Направление счета
+  */
+typedef enum {
+    PWM_TB_Dir_Down, /*!< Счет вниз */
+    PWM_TB_Dir_Up    /*!< Счет вверх */
+} PWM_TB_Dir_TypeDef;
+#define IS_PWM_TB_DIR(VALUE) (((VALUE) == PWM_TB_Dir_Down) || \
+                              ((VALUE) == PWM_TB_Dir_Up))
+
+/**
+  * @brief  Источник для выходного сигнала синхронизации SYNCO
+  */
+typedef enum {
+    PWM_TB_SyncOut_SyncIn = PWM_TBCTL_SYNCOSEL_SYNCI,        /*!< Входной сигнал SYNCI */
+    PWM_TB_SyncOut_CTREqZero = PWM_TBCTL_SYNCOSEL_CTREqZero, /*!< Значение таймера равно нулю */
+    PWM_TB_SyncOut_CTREqCMPB = PWM_TBCTL_SYNCOSEL_CTREqCMPB, /*!< Значение таймера равно регистру CMPB */
+    PWM_TB_SyncOut_Disable = PWM_TBCTL_SYNCOSEL_Disable      /*!< Выдача синхроимпульса запрещена */
+} PWM_TB_SyncOut_TypeDef;
+#define IS_PWM_TB_SYNC_OUT(VALUE) (((VALUE) == PWM_TB_SyncOut_SyncIn) ||    \
+                                   ((VALUE) == PWM_TB_SyncOut_CTREqZero) || \
+                                   ((VALUE) == PWM_TB_SyncOut_CTREqCMPB) || \
+                                   ((VALUE) == PWM_TB_SyncOut_Disable))
+
+/**
+  * @brief Направление счета
+  */
+typedef enum {
+    PWM_TB_Mode_Up = PWM_TBCTL_CTRMODE_Up,         /*!< Счет вверх */
+    PWM_TB_Mode_Down = PWM_TBCTL_CTRMODE_Down,     /*!< Счет вниз */
+    PWM_TB_Mode_UpDown = PWM_TBCTL_CTRMODE_UpDown, /*!< Счет вверх-вниз */
+    PWM_TB_Mode_Disable = PWM_TBCTL_CTRMODE_Stop   /*!< Счетчик остановлен */
+} PWM_TB_Mode_TypeDef;
+#define IS_PWM_TB_MODE(VALUE) (((VALUE) == PWM_TB_Mode_Up) ||     \
+                               ((VALUE) == PWM_TB_Mode_Down) ||   \
+                               ((VALUE) == PWM_TB_Mode_UpDown) || \
+                               ((VALUE) == PWM_TB_Mode_Disable))
+
+/**
+  * @brief  Событие для загрузки значения сравнения в теневом режиме
+  */
+typedef enum {
+    PWM_CMP_LoadEvent_CTREqZero = PWM_CMPCTL_LOADAMODE_CTREqZero,            /*!< Загрузка отложенного значения при условии, что значение таймера равно нулю */
+    PWM_CMP_LoadEvent_CTREqPeriod = PWM_CMPCTL_LOADAMODE_CTREqPRD,           /*!< Загрузка отложенного значения при условии, что значение таймера равно периоду */
+    PWM_CMP_LoadEvent_CTREqZeroOrPeriod = PWM_CMPCTL_LOADAMODE_CTREqZeroPRD, /*!< Загрузка отложенного значения при условии, что значение таймера равно нулю или периоду */
+    PWM_CMP_LoadEvent_Disable = PWM_CMPCTL_LOADAMODE_Disable                 /*!< Загрузка отложенного значения запрещена */
+} PWM_CMP_LoadEvent_TypeDef;
+#define IS_PWM_CMP_LOAD_EVENT(VALUE) (((VALUE) == PWM_CMP_LoadEvent_CTREqZero) ||         \
+                                      ((VALUE) == PWM_CMP_LoadEvent_CTREqPeriod) ||       \
+                                      ((VALUE) == PWM_CMP_LoadEvent_CTREqZeroOrPeriod) || \
+                                      ((VALUE) == PWM_CMP_LoadEvent_Disable))
+
+/**
+  * @brief Выбор действия на выводе ШИМ
+  */
+typedef enum {
+    PWM_AQ_Action_None = PWM_AQCTLA_ZRO_NoAction, /*!< Нет реакции */
+    PWM_AQ_Action_ToZero = PWM_AQCTLA_PRD_Clear,  /*!< Переключение в ноль */
+    PWM_AQ_Action_ToOne = PWM_AQCTLA_CAU_Set,     /*!< Переключение в единицу */
+    PWM_AQ_Action_Inv = PWM_AQCTLA_CAD_Toggle     /*!< Инверсия текущего состояния */
+} PWM_AQ_Action_TypeDef;
+#define IS_PWM_AQ_ACTION(VALUE) (((VALUE) == PWM_AQ_Action_None) ||   \
+                                 ((VALUE) == PWM_AQ_Action_ToZero) || \
+                                 ((VALUE) == PWM_AQ_Action_ToOne) ||  \
+                                 ((VALUE) == PWM_AQ_Action_Inv))
+
+/**
+  * @brief  Возможные события для генерации внешних сигналов/запросов
+  */
+typedef enum {
+    PWM_AQ_Event_CTREqZero = PWM_AQCTLA_ZRO_Pos,     /*!< Значение таймера равно нулю */
+    PWM_AQ_Event_CTREqPeriod = PWM_AQCTLA_PRD_Pos,   /*!< Значение таймера равно периоду */
+    PWM_AQ_Event_CTREqCMPAUp = PWM_AQCTLA_CAU_Pos,   /*!< Значение таймера равно регистру CMPA при счете вверх */
+    PWM_AQ_Event_CTREqCMPADown = PWM_AQCTLA_CAD_Pos, /*!< Значение таймера равно регистру CMPA при счете вниз */
+    PWM_AQ_Event_CTREqCMPBUp = PWM_AQCTLA_CBU_Pos,   /*!< Значение таймера равно регистру CMPB при счете вверх */
+    PWM_AQ_Event_CTREqCMPBDown = PWM_AQCTLA_CBD_Pos  /*!< Значение таймера равно регистру CMPB при счете вниз */
+} PWM_AQ_Event_TypeDef;
+#define IS_PWM_AQ_EVENT(VALUE) (((VALUE) == PWM_AQ_Event_CTREqZero) ||     \
+                                ((VALUE) == PWM_AQ_Event_CTREqPeriod) ||   \
+                                ((VALUE) == PWM_AQ_Event_CTREqCMPAUp) ||   \
+                                ((VALUE) == PWM_AQ_Event_CTREqCMPADown) || \
+                                ((VALUE) == PWM_AQ_Event_CTREqCMPBUp) ||   \
+                                ((VALUE) == PWM_AQ_Event_CTREqCMPBDown))
+
+/**
+  * @brief  Cобытия для применения настроек однократного или цилического программного воздействия на вывода
+  */
+typedef enum {
+    PWM_AQ_ForceShadowEvent_CTREqZero = PWM_AQSFRC_RLDCSF_CTREqZero,          /*!< Значение таймера равно нулю */
+    PWM_AQ_ForceShadowEvent_CTREqPeriod = PWM_AQSFRC_RLDCSF_CTREqPRD,         /*!< Значение таймера равно периоду */
+    PWM_AQ_ForceShadowEvent_CTREqPeriodZero = PWM_AQSFRC_RLDCSF_CTREqZeroPRD, /*!< Значение таймера равно периоду или нулю */
+    PWM_AQ_ForceShadowEvent_None = PWM_AQSFRC_RLDCSF_NoShadow,                /*!< Прямая запись */
+} PWM_AQ_ForceShadowEvent_TypeDef;
+#define IS_PWM_AQ_FORCE_SHADOW_EVENT(VALUE) (((VALUE) == PWM_AQ_ForceShadowEvent_CTREqZero) ||       \
+                                             ((VALUE) == PWM_AQ_ForceShadowEvent_CTREqPeriod) ||     \
+                                             ((VALUE) == PWM_AQ_ForceShadowEvent_CTREqPeriodZero) || \
+                                             ((VALUE) == PWM_AQ_ForceShadowEvent_None))
+
+/**
+  * @brief Выбор источников для формирования задержки
+  */
+typedef enum {
+    PWM_DB_In_A = PWM_DBCTL_INMODE_APosNeg,            /*!< Входной сигнал А задержан по обоим фронтам */
+    PWM_DB_In_AFallBRise = PWM_DBCTL_INMODE_ANeg_BPos, /*!< Входной сигнал A задержан заднему фронту, B - по переднему  */
+    PWM_DB_In_ARiseBFall = PWM_DBCTL_INMODE_APos_BNeg, /*!< Входной сигнал A задержан переднему фронту, B - по заднему  */
+    PWM_DB_In_B = PWM_DBCTL_INMODE_BPosNeg             /*!< Входной сигнал B задержан по обоим фронтам */
+} PWM_DB_In_TypeDef;
+#define IS_PWM_DB_IN(VALUE) (((VALUE) == PWM_DB_In_A) ||          \
+                             ((VALUE) == PWM_DB_In_ARiseBFall) || \
+                             ((VALUE) == PWM_DB_In_AFallBRise) || \
+                             ((VALUE) == PWM_DB_In_B))
+
+/**
+  * @brief Выбор полярности задержанных сигналов
+  */
+typedef enum {
+    PWM_DB_Polarity_ActiveHigh = PWM_DBCTL_POLSEL_InvDisable, /*!< Нет инверсии */
+    PWM_DB_Polarity_ActiveLowCompl = PWM_DBCTL_POLSEL_InvA,   /*!< Инвертируется сигнал, задержанный по переднему фронту  */
+    PWM_DB_Polarity_ActiveHighCompl = PWM_DBCTL_POLSEL_InvB,  /*!< Инвертируется сигнал, задержанный по заднему фронту  */
+    PWM_DB_Polarity_ActiveLow = PWM_DBCTL_POLSEL_InvAB        /*!< Инвертируются оба сигнала */
+} PWM_DB_Polarity_TypeDef;
+#define IS_PWM_DB_POLARITY(VALUE) (((VALUE) == PWM_DB_Polarity_ActiveHigh) ||      \
+                                   ((VALUE) == PWM_DB_Polarity_ActiveLowCompl) ||  \
+                                   ((VALUE) == PWM_DB_Polarity_ActiveHighCompl) || \
+                                   ((VALUE) == PWM_DB_Polarity_ActiveLow))
+
+/**
+  * @brief Выбор выходных сигналов блока задержки
+  */
+typedef enum {
+    PWM_DB_Out_BypassAB = PWM_DBCTL_OUTMODE_NoSpec,  /*!< Нет задержки. Входные сигналы A и B подключены напрямую к выходу модуля задержки. */
+    PWM_DB_Out_BypassA = PWM_DBCTL_OUTMODE_BNeg,     /*!< Входной сигнал A подключен напрямую к выходу A модуля задержки. Задержанный по заднему фронту сигнал подключен к выходу B.  */
+    PWM_DB_Out_BypassB = PWM_DBCTL_OUTMODE_APos,     /*!< Входной сигнал B подключен напрямую к выходу B модуля задержки. Задержанный по переднему фронту сигнал подключен к выходу A.  */
+    PWM_DB_Out_DelayAB = PWM_DBCTL_OUTMODE_Apos_BNeg /*!< Задержанный по переднему фронту сигнал подключен к выходу A, по заднему - к выходу B. */
+} PWM_DB_Out_TypeDef;
+#define IS_PWM_DB_OUT(VALUE) (((VALUE) == PWM_DB_Out_BypassAB) || \
+                              ((VALUE) == PWM_DB_Out_BypassA) ||  \
+                              ((VALUE) == PWM_DB_Out_BypassB) ||  \
+                              ((VALUE) == PWM_DB_Out_DelayAB))
+
+/**
+  * @brief  Возможные события для генерации внешних сигналов/запросов
+  */
+typedef enum {
+    PWM_ET_Event_CTREqZero = PWM_ETSEL_SOCASEL_CTREqZero,             /*!< Значение таймера равно нулю */
+    PWM_ET_Event_CTREqPeriod = PWM_ETSEL_SOCASEL_CTREqPRD,            /*!< Значение таймера равно периоду */
+    PWM_ET_Event_CTREqCMPA_Up = PWM_ETSEL_SOCASEL_CTREqCMPA_OnUp,     /*!< Значение таймера равно регистру CMPA при счете вверх */
+    PWM_ET_Event_CTREqCMPA_Down = PWM_ETSEL_SOCASEL_CTREqCMPA_OnDown, /*!< Значение таймера равно регистру CMPA при счете вниз */
+    PWM_ET_Event_CTREqCMPB_Up = PWM_ETSEL_SOCASEL_CTREqCMPB_OnUp,     /*!< Значение таймера равно регистру CMPB при счете вверх */
+    PWM_ET_Event_CTREqCMPB_Down = PWM_ETSEL_SOCASEL_CTREqCMPB_OnDown  /*!< Значение таймера равно регистру CMPB при счете вниз */
+} PWM_ET_Event_TypeDef;
+#define IS_PWM_ET_EVENT(VALUE) (((VALUE) == PWM_ET_Event_CTREqZero) ||      \
+                                ((VALUE) == PWM_ET_Event_CTREqPeriod) ||    \
+                                ((VALUE) == PWM_ET_Event_CTREqCMPA_Up) ||   \
+                                ((VALUE) == PWM_ET_Event_CTREqCMPA_Down) || \
+                                ((VALUE) == PWM_ET_Event_CTREqCMPB_Up) ||   \
+                                ((VALUE) == PWM_ET_Event_CTREqCMPB_Down))
+
+/**
+  * @brief Выбор поведения вывода в случае наступления сигнала аварии
+  */
+typedef enum {
+    PWM_TZ_Action_ToZ = PWM_TZCTL_TZA_Z,        /*!< Переключение вывода в третье состояние */
+    PWM_TZ_Action_ToOne = PWM_TZCTL_TZA_Set,    /*!< Переключение в единицу */
+    PWM_TZ_Action_ToZero = PWM_TZCTL_TZA_Clear, /*!< Переключение в ноль  */
+    PWM_TZ_Action_None = PWM_TZCTL_TZA_NoAction /*!< Нет действий */
+} PWM_TZ_Action_TypeDef;
+#define IS_PWM_TZ_ACTION(VALUE) (((VALUE) == PWM_TZ_Action_ToZ) ||    \
+                                 ((VALUE) == PWM_TZ_Action_ToOne) ||  \
+                                 ((VALUE) == PWM_TZ_Action_ToZero) || \
+                                 ((VALUE) == PWM_TZ_Action_None))
+
+/**
+  * @brief Выбор поведения вывода в случае наступления события удержания.
+  */
+
+typedef enum {
+    PWM_HD_Action_ToOne = PWM_HDCTL_HDA_Set,    /*!< Переключение в единицу*/
+    PWM_HD_Action_ToZero = PWM_HDCTL_HDA_Clear, /*!< Переключение в ноль  */
+    PWM_HD_Action_None = PWM_HDCTL_HDA_NoAction /*!< Нет действий */
+} PWM_HD_Action_TypeDef;
+#define IS_PWM_HD_ACTION(VALUE) (((VALUE) == PWM_HD_Action_ToOne) ||  \
+                                 ((VALUE) == PWM_HD_Action_ToZero) || \
+                                 ((VALUE) == PWM_HD_Action_None))
+
+/**
+  * @brief  Структура инициализации таймера-счетчика блока ШИМ
+  */
+typedef struct
+{
+    PWM_TB_Halt_TypeDef Halt;               /*!< Выбор режима остановки таймера при отладке */
+    PWM_TB_ClkDiv_TypeDef ClkDiv;           /*!< Коэффициент базового деления частоты */
+    PWM_TB_ClkDivExtra_TypeDef ClkDivExtra; /*!< Коэффициент дополнительного деления частоты.
+                                                 Результирующий коэффциент = ClkDiv * ClkDivExtra */
+    PWM_TB_SyncOut_TypeDef SyncOut;         /*!< Источник для выходного сигнала синхронизации SYNCO */
+    FunctionalState PhaseSync;              /*!< Разрешает загрузку счетчика значением регистра фазы при получении события синхронизации */
+    PWM_TB_Dir_TypeDef PhaseSyncDir;        /*!< Задание направления счета после синхронизации фазы */
+    uint32_t Phase;                         /*!< Значение фазы ШИМ при получении события синхронизации.
+                                                 Параметр может принимать любое значение из диапазона: 0x0000-0xFFFF. */
+    PWM_TB_Mode_TypeDef Mode;               /*!< Задание направления счета */
+    FunctionalState PeriodDirectLoad;       /*!< Разрешает только прямую загрузку в регистр периода (теневая отключена) */
+    uint32_t Period;                        /*!< Значение периода таймера ШИМ.
+                                                 Параметр может принимать любое значение из диапазона: 0x0000-0xFFFF. */
+} PWM_TB_Init_TypeDef;
+#define IS_PWM_TB_PHASE_VAL(VALUE) ((VALUE) < 0x10000)
+#define IS_PWM_TB_PERIOD_VAL(VALUE) ((VALUE) < 0x10000)
+#define IS_PWM_TB_COUNTER_VAL(VALUE) ((VALUE) < 0x10000)
+
+typedef struct
+{
+    PWM_AQ_Action_TypeDef ActionA_CTREqZero;     /*!< Действие в канале А, при наступлении события равенства счетчика таймера нулю */
+    PWM_AQ_Action_TypeDef ActionA_CTREqPeriod;   /*!< Действие в канале А, при наступлении события равенства счетчика значению периода */
+    PWM_AQ_Action_TypeDef ActionA_CTREqCMPAUp;   /*!< Действие в канале А, при наступлении события равенства счетчика таймера значению сравнения A при счете вверх */
+    PWM_AQ_Action_TypeDef ActionA_CTREqCMPADown; /*!< Действие в канале A, при наступлении события равенства счетчика таймера значению сравнения A при счете вниз */
+    PWM_AQ_Action_TypeDef ActionA_CTREqCMPBUp;   /*!< Действие в канале А, при наступлении события равенства счетчика таймера значению сравнения B при счете вверх */
+    PWM_AQ_Action_TypeDef ActionA_CTREqCMPBDown; /*!< Действие в канале A, при наступлении события равенства счетчика таймера значению сравнения B при счете вниз */
+    PWM_AQ_Action_TypeDef ActionB_CTREqZero;     /*!< Действие в канале B, при наступлении события равенства счетчика таймера нулю */
+    PWM_AQ_Action_TypeDef ActionB_CTREqPeriod;   /*!< Действие в канале B, при наступлении события равенства счетчика значению периода */
+    PWM_AQ_Action_TypeDef ActionB_CTREqCMPAUp;   /*!< Действие в канале B, при наступлении события равенства счетчика таймера значению сравнения A при счете вверх */
+    PWM_AQ_Action_TypeDef ActionB_CTREqCMPADown; /*!< Действие в канале B, при наступлении события равенства счетчика таймера значению сравнения A при счете вниз */
+    PWM_AQ_Action_TypeDef ActionB_CTREqCMPBUp;   /*!< Действие в канале B, при наступлении события равенства счетчика таймера значению сравнения B при счете вверх */
+    PWM_AQ_Action_TypeDef ActionB_CTREqCMPBDown; /*!< Действие в канале B, при наступлении события равенства счетчика таймера значению сравнения B при счете вниз */
+} PWM_AQ_Init_TypeDef;
+
+/**
+   * @brief  Структура инициализации компараторов блока ШИМ
+   */
+typedef struct
+{
+    FunctionalState CmpADirectLoad;          /*!< Разрешает только прямую загрузку в регистр CMPA (теневая отключена) */
+    PWM_CMP_LoadEvent_TypeDef LoadEventCmpA; /*!< Событие для теневой загрузки в регистр сравнения CMPA */
+    uint32_t CmpA;                           /*!< Значение порога срабатывания канала А, которое сравнивается со значением счетчика таймера.
+                                                  Параметр может принимать любое значение из диапазона: 0x0000-0xFFFF. */
+    FunctionalState CmpBDirectLoad;          /*!< Разрешает только прямую загрузку в регистр CMPB (теневая отключена) */
+    PWM_CMP_LoadEvent_TypeDef LoadEventCmpB; /*!< Событие для теневой загрузки в регистр сравнения CMPB */
+    uint32_t CmpB;                           /*!< Значение порога срабатывания канала B, которое сравнивается со значением счетчика таймера.
+                                                  Параметр может принимать любое значение из диапазона: 0x0000-0xFFFF. */
+} PWM_CMP_Init_TypeDef;
+#define IS_PWM_CMP_VAL(VALUE) ((VALUE) < 0x10000)
+
+/**
+   * @brief  Структура инициализации порогового выключателя блока ШИМ
+   */
+typedef struct
+{
+    PWM_HD_Action_TypeDef ActionA; /*!< Настройка поведения канала A при поступлении события удержания */
+    PWM_HD_Action_TypeDef ActionB; /*!< Настройка поведения канала B при поступлении события удержания */
+    uint32_t Source;               /*!< Выбор источников для генерации события удержания.
+                                        Параметр принимает любую совокупность значений из @ref PWM_HD_Source_Define */
+    FunctionalState Cycle;         /*!< Включение циклической обработки сигнала удержания */
+    FunctionalState OneShot;       /*!< Включение однократной обработки сигнала удержания */
+} PWM_HD_Init_TypeDef;
+
+/**
+   * @brief  Структура инициализации задержки сигналов ШИМ ("мертвое время").
+   */
+typedef struct
+{
+    PWM_DB_In_TypeDef In;             /*!< Выбор источников для формирования задержки */
+    PWM_DB_Polarity_TypeDef Polarity; /*!< Выбор полярности задержанных сигналов */
+    PWM_DB_Out_TypeDef Out;           /*!< Выбор выходных сигналов блока задержки */
+    uint32_t RiseDelay;               /*!< Величина задержки переднего фронта.
+                                           Параметр может принимать любое значение из диапазона: 0x000-0x3FF. */
+    uint32_t FallDelay;               /*!< Величина задержки заднего фронта.
+                                           Параметр может принимать любое значение из диапазона: 0x000-0x3FF. */
+} PWM_DB_Init_TypeDef;
+#define IS_PWM_DB_DELAY_VAL(VALUE) ((VALUE) < 0x400)
+
+/**
+   * @brief  Структура инициализации обработчика сигнала аварии блока ШИМ
+   */
+typedef struct
+{
+    PWM_TZ_Action_TypeDef ActionA; /*!< Настройка поведения канала A при поступлении сигнала аварии */
+    PWM_TZ_Action_TypeDef ActionB; /*!< Настройка поведения канала B при поступлении сигнала аварии */
+    FunctionalState Cycle;         /*!< Включение циклической обработки сигнала аварии */
+    FunctionalState OneShot;       /*!< Включение однократной обработки сигнала аварии */
+} PWM_TZ_Init_TypeDef;
+
+/**
+  * @brief  Структура инициализации блока "триггера событий" для генерации внешних сигналов/запросов
+  */
+typedef struct
+{
+    FunctionalState SOCA;           /*!< Канал А: разрешает формирование строба запуска АЦП */
+    PWM_ET_Event_TypeDef EventSOCA; /*!< Канал А: выбор события для формирования строба запуска АЦП */
+    uint32_t PeriodSOCA;            /*!< Канал А: выбор количества событий для возникновения строба АЦП.
+                                         Параметр принимает любое значение из диапазона 0-3,
+                                         где 0 - соответсвует каждому событию, 1 - каждому второму и т.д. */
+    FunctionalState SOCB;           /*!< Канал B: разрешает формирование строба запуска АЦП */
+    PWM_ET_Event_TypeDef EventSOCB; /*!< Канал B: выбор события для формирования строба запуска АЦП */
+    uint32_t PeriodSOCB;            /*!< Канал B: выбор количества событий для возникновения строба запуска АЦП.
+                                         Параметр принимает любое значение из диапазона 0-3,
+                                         где 0 - соответсвует каждому событию, 1 - каждому второму и т.д. */
+    FunctionalState DRQA;           /*!< Канал А: разрешает формирование запроса DMA */
+    PWM_ET_Event_TypeDef EventDRQA; /*!< Канал А: выбор события для формирования запроса DMA */
+    uint32_t PeriodDRQA;            /*!< Канал А: выбор количества событий для возникновения запроса DMA.
+                                         Параметр принимает любое значение из диапазона 0-3,
+                                         где 0 - соответсвует каждому событию, 1 - каждому второму и т.д. */
+    FunctionalState DRQB;           /*!< Канал B: разрешает формирование запроса DMA */
+    PWM_ET_Event_TypeDef EventDRQB; /*!< Канал B: выбор события для формирования запроса DMA */
+    uint32_t PeriodDRQB;            /*!< Канал B: выбор количества событий для возникновения запроса DMA.
+                                         Параметр принимает любое значение из диапазона 0-3,
+                                         где 0 - соответсвует каждому событию, 1 - каждому второму и т.д. */
+} PWM_ET_Init_TypeDef;
+#define IS_PWM_ET_PERIOD(VALUE) ((VALUE) < 0x4)
+
+/**
+  * @}
+  */
+
+/** @defgroup PWM_Exported_Functions Функции
+  * @{
+  */
+
+void PWM_DeInit(PWM_TypeDef* PWMx);
+
+/**
+  * @brief   Установка ширины фильтрации коротких импульсов
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   FilterVal  Значение.
+  *                     Параметр принимает любое значение из диапазона 0x00-0xFF,
+  *                     где 0 - фильтр выключен, а 0xFF - 25.6 мкс (шаг установки 0.1 мкс).
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_FilterConfig(PWM_TypeDef* PWMx, uint32_t FilterVal)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_FILTER(FilterVal));
+
+    WRITE_REG(PWMx->FWDTH, FilterVal);
+}
+
+/**
+  * @brief   Разрешение всех теневых загрузок регистров PWM
+  * @param   PWMx  Выбор блока PWM, где x лежит в диапазоне 0-2.
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_TB_GlobalShadowLoadCmd(PWM_TypeDef* PWMx, FunctionalState State)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(PWMx->TBCTL_bit.SHDWGLOB, State);
+}
+
+/** @defgroup PWM_Exported_Functions_TimeBase Счетчик
+  * @{
+  */
+
+void PWM_TB_Init(PWM_TypeDef* PWMx, PWM_TB_Init_TypeDef* InitStruct);
+void PWM_TB_StructInit(PWM_TB_Init_TypeDef* InitStruct);
+
+/**
+  * @brief   Управление предделителями тактирования таймеров блоков PWM
+  * @param   Presc  Выбор предделителей блоков.
+  *                 Параметр принимает любою совокупность значений из @ref PWM_Presc_Define.
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_TB_PrescCmd(uint32_t Presc, FunctionalState State)
+{
+    assert_param(IS_PWM_TB_PRESC(Presc));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    MODIFY_REG(SIU->PWMSYNC, Presc, State ? Presc : 0);
+}
+
+/**
+  * @brief   Настройка коэффициента деления частоты для получения счетного тактового сигнала TBCLK.
+  *          Результирующий коэффциент = ClkDiv * ClkDivExtra
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   ClkDiv  Выбор делителя
+  * @param   ClkDivExtra  Выбор делителя
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_TB_ClkDivConfig(PWM_TypeDef* PWMx, PWM_TB_ClkDiv_TypeDef ClkDiv, PWM_TB_ClkDivExtra_TypeDef ClkDivExtra)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_TB_CLK_DIV(ClkDiv));
+    assert_param(IS_PWM_TB_CLK_DIV_EXTRA(ClkDivExtra));
+
+    MODIFY_REG(PWMx->TBCTL, PWM_TBCTL_CLKDIV_Msk | PWM_TBCTL_HSPCLKDIV_Msk,
+               ((ClkDiv << PWM_TBCTL_CLKDIV_Pos) |
+                (ClkDivExtra << PWM_TBCTL_HSPCLKDIV_Pos)));
+}
+
+/**
+  * @brief   Чтение статуса флага состояния таймера PWM
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   Status  Выбор флагов.
+  *                  Параметр принимает любою совокупность значений из @ref PWM_TB_Status_Define.
+  * @retval  Status  Статус прерывания. Если выбрано несколько флагов,
+  *                  то результат соответсвует логическому ИЛИ их состояний.
+  */
+__STATIC_INLINE FlagStatus PWM_TB_Status(PWM_TypeDef* PWMx, uint32_t Status)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_TB_STATUS(Status));
+
+    return (FlagStatus)READ_BIT(PWMx->TBSTS, Status);
+}
+
+/**
+  * @brief   Сброс флагов статусов таймера PWM
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   Status  Выбор флагов.
+  *                  Параметр принимает любою совокупность значений из @ref PWM_TB_Status_Define.
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_TB_StatusClear(PWM_TypeDef* PWMx, uint32_t Status)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_TB_STATUS(Status));
+
+    WRITE_REG(PWMx->TBSTS, Status);
+}
+
+/**
+  * @brief   Установка значения счетчика PWM
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   CounterVal  Значение счетчика
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_TB_SetCounter(PWM_TypeDef* PWMx, uint32_t CounterVal)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_TB_COUNTER_VAL(CounterVal));
+
+    WRITE_REG(PWMx->TBCTR, CounterVal);
+}
+
+/**
+  * @brief   Установка значения периода PWM
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   PeriodVal  Значение периода
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_TB_SetPeriod(PWM_TypeDef* PWMx, uint32_t PeriodVal)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_TB_PERIOD_VAL(PeriodVal));
+
+    WRITE_REG(PWMx->TBPRD, PeriodVal);
+}
+
+/**
+  * @brief   Установка значения фазы PWM
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   PhaseVal  Значение фазы
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_TB_SetPhase(PWM_TypeDef* PWMx, uint32_t PhaseVal)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_TB_PHASE_VAL(PhaseVal));
+
+    WRITE_REG(PWMx->TBPHS, PhaseVal);
+}
+
+/**
+  * @brief   Получение текущего значения счетчика PWM
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @retval  Val  Значение счетчика
+  */
+__STATIC_INLINE uint32_t PWM_TB_GetCounter(PWM_TypeDef* PWMx)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+
+    return READ_REG(PWMx->TBCTR);
+}
+
+/**
+  * @brief   Получение текущего значения периода PWM
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @retval  Val  Значение периода
+  */
+__STATIC_INLINE uint32_t PWM_TB_GetPeriod(PWM_TypeDef* PWMx)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+
+    return READ_REG(PWMx->TBPRD);
+}
+
+/**
+  * @brief   Получение текущего значения фазы PWM
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @retval  Val  Значение фазы
+  */
+__STATIC_INLINE uint32_t PWM_TB_GetPhase(PWM_TypeDef* PWMx)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+
+    return READ_REG(PWMx->TBPHS);
+}
+
+/**
+  * @brief   Программный запуск входного синхроимпульса SYNCI
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_TB_SwSyncInCmd(PWM_TypeDef* PWMx)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+
+    WRITE_REG(PWMx->TBCTL_bit.SWFSYNC, 1);
+}
+
+/**
+  * @brief   Настройка режима остановки таймера PWM при отладке
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   Halt  Выбор режима
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_TB_HaltConfig(PWM_TypeDef* PWMx, PWM_TB_Halt_TypeDef Halt)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_TB_HALT(Halt));
+
+    WRITE_REG(PWMx->TBCTL_bit.FREESOFT, Halt);
+}
+
+/**
+  * @brief   Настройка источника выходного сигнала синхронизации SYNCO
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   SyncOut  Выбор режима
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_TB_SyncOutConfig(PWM_TypeDef* PWMx, PWM_TB_SyncOut_TypeDef SyncOut)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_TB_SYNC_OUT(SyncOut));
+
+    WRITE_REG(PWMx->TBCTL_bit.SYNCOSEL, SyncOut);
+}
+
+/**
+  * @brief   Разрешает загрузку счетчика значением регистра фазы при получении события синхронизации
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_TB_PhaseSyncCmd(PWM_TypeDef* PWMx, FunctionalState State)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(PWMx->TBCTL_bit.PHSEN, State);
+}
+
+/**
+  * @brief   Задание направления счета после синхронизации фазы
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   PhaseSyncDir  Выбор режима
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_TB_PhaseSyncDirConfig(PWM_TypeDef* PWMx, PWM_TB_Dir_TypeDef PhaseSyncDir)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_TB_DIR(PhaseSyncDir));
+
+    WRITE_REG(PWMx->TBCTL_bit.PHSDIR, PhaseSyncDir);
+}
+
+/**
+  * @brief   Задание направления счета PWM
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   Mode  Выбор режима
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_TB_ModeConfig(PWM_TypeDef* PWMx, PWM_TB_Mode_TypeDef Mode)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_TB_MODE(Mode));
+
+    WRITE_REG(PWMx->TBCTL_bit.CTRMODE, Mode);
+}
+
+/**
+  * @brief   Разрешает прямую загрузку в регистр периода (теневая отключена)
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_TB_PeriodDirectLoadCmd(PWM_TypeDef* PWMx, FunctionalState State)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(PWMx->TBCTL_bit.PRDLD, State);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWM_Exported_Functions_ActionQualifier Управление поведением выводов
+  * @{
+  */
+
+void PWM_AQ_Init(PWM_TypeDef* PWMx, PWM_AQ_Init_TypeDef* InitStruct);
+void PWM_AQ_StructInit(PWM_AQ_Init_TypeDef* InitStruct);
+
+/**
+  * @brief   Задание действия на выходе PWM A по выбранному событию
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   Event  Выбор события
+  * @param   Action  Выбор действия
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_AQ_ActionAConfig(PWM_TypeDef* PWMx, PWM_AQ_Event_TypeDef Event, PWM_AQ_Action_TypeDef Action)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_AQ_EVENT(Event));
+    assert_param(IS_PWM_AQ_ACTION(Action));
+
+    MODIFY_REG(PWMx->AQCTLA, 3 << (uint32_t)Event, Action << (uint32_t)Event);
+}
+
+/**
+  * @brief   Программное задание продолжительного воздействия на канал PWM A
+  * @param   PWMx  Выбор ШИМ, где x лежит в диапазоне 0-2
+  * @param   Action  Выбор действия
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_AQ_ForceContACmd(PWM_TypeDef* PWMx, PWM_AQ_Action_TypeDef Action)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_AQ_ACTION(Action));
+
+    WRITE_REG(PWMx->AQCSFRC_bit.CSFA, Action);
+}
+
+/**
+  * @brief   Настройка типа однократного программного воздействия на канал PWM A
+  * @param   PWMx  Выбор ШИМ, где x лежит в диапазоне 0-2
+  * @param   Action  Выбор действия
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_AQ_ForceAConfig(PWM_TypeDef* PWMx, PWM_AQ_Action_TypeDef Action)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_AQ_ACTION(Action));
+
+    WRITE_REG(PWMx->AQSFRC_bit.ACTSFA, Action);
+}
+
+/**
+  * @brief   Применение выбранного однократного программного воздействия на канал PWM A
+  * @param   PWMx  Выбор ШИМ, где x лежит в диапазоне 0-2
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_AQ_ForceACmd(PWM_TypeDef* PWMx)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+
+    WRITE_REG(PWMx->AQSFRC_bit.OTSFA, 1);
+}
+
+/**
+  * @brief   Задание действия на выходе PWM B по выбранному событию
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   Event  Выбор события
+  * @param   Action  Выбор действия
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_AQ_ActionBConfig(PWM_TypeDef* PWMx, PWM_AQ_Event_TypeDef Event, PWM_AQ_Action_TypeDef Action)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_AQ_EVENT(Event));
+    assert_param(IS_PWM_AQ_ACTION(Action));
+
+    MODIFY_REG(PWMx->AQCTLB, 3 << (uint32_t)Event, Action << (uint32_t)Event);
+}
+
+/**
+  * @brief   Программное задание продолжительного воздействия на канал PWM B
+  * @param   PWMx  Выбор ШИМ, где x лежит в диапазоне 0-2
+  * @param   Action  Выбор действия
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_AQ_ForceContBCmd(PWM_TypeDef* PWMx, PWM_AQ_Action_TypeDef Action)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_AQ_ACTION(Action));
+
+    WRITE_REG(PWMx->AQCSFRC_bit.CSFB, Action);
+}
+
+/**
+  * @brief   Настройка типа однократного программного воздействия на канал PWM B
+  * @param   PWMx  Выбор ШИМ, где x лежит в диапазоне 0-2
+  * @param   Action  Выбор действия
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_AQ_ForceBConfig(PWM_TypeDef* PWMx, PWM_AQ_Action_TypeDef Action)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_AQ_ACTION(Action));
+
+    WRITE_REG(PWMx->AQSFRC_bit.ACTSFB, Action);
+}
+
+/**
+  * @brief   Применение выбранного однократного программного воздействия на канал PWM B
+  * @param   PWMx  Выбор ШИМ, где x лежит в диапазоне 0-2
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_AQ_ForceBCmd(PWM_TypeDef* PWMx)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+
+    WRITE_REG(PWMx->AQSFRC_bit.OTSFB, 1);
+}
+
+/**
+  * @brief   Задание события для применения настроек однократного или цилического программного воздействия на вывода
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   Event  Выбор события
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_AQ_ForceShadowConfig(PWM_TypeDef* PWMx, PWM_AQ_ForceShadowEvent_TypeDef ForceShadowEvent)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_AQ_FORCE_SHADOW_EVENT(ForceShadowEvent));
+
+    WRITE_REG(PWMx->AQSFRC_bit.RLDCSF, (uint32_t)ForceShadowEvent);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWM_Exported_Functions_Compare Компараторы
+  * @{
+  */
+
+void PWM_CMP_Init(PWM_TypeDef* PWMx, PWM_CMP_Init_TypeDef* InitStruct);
+void PWM_CMP_StructInit(PWM_CMP_Init_TypeDef* InitStruct);
+
+/**
+  * @brief   Настройка cобытия для теневой загрузки в регистр сравнения CMPA
+  * @param   PWMx  Выбор ШИМ, где x лежит в диапазоне 0-2
+  * @param   LoadEvent  Выбор события
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_CMP_CmpALoadEventConfig(PWM_TypeDef* PWMx, PWM_CMP_LoadEvent_TypeDef LoadEvent)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_CMP_LOAD_EVENT(LoadEvent));
+
+    WRITE_REG(PWMx->CMPCTL_bit.LOADAMODE, LoadEvent);
+}
+
+/**
+  * @brief   Разрешает прямую загрузку в регистр CMPA (теневая отключена)
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_CMP_CmpADirectLoadCmd(PWM_TypeDef* PWMx, FunctionalState State)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(PWMx->CMPCTL_bit.SHDWAMODE, State);
+}
+
+/**
+  * @brief   Установка значения сравнения A PWM
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   CMPAVal  Значение сравнения
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_CMP_SetCmpA(PWM_TypeDef* PWMx, uint32_t CMPAVal)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_CMP_VAL(CMPAVal));
+
+    WRITE_REG(PWMx->CMPA_bit.CMPA, CMPAVal);
+}
+
+/**
+  * @brief   Получение текущего значения сравнения A PWM
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @retval  Val  Значение сравнения
+  */
+__STATIC_INLINE uint32_t PWM_CMP_GetCmpA(PWM_TypeDef* PWMx)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+
+    return READ_REG(PWMx->CMPA_bit.CMPA);
+}
+
+/**
+  * @brief   Настройка cобытия для теневой загрузки в регистр сравнения CMPB
+  * @param   PWMx  Выбор ШИМ, где x лежит в диапазоне 0-2
+  * @param   LoadEvent  Выбор события
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_CMP_CmpBLoadEventConfig(PWM_TypeDef* PWMx, PWM_CMP_LoadEvent_TypeDef LoadEvent)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_CMP_LOAD_EVENT(LoadEvent));
+
+    WRITE_REG(PWMx->CMPCTL_bit.LOADBMODE, LoadEvent);
+}
+
+/**
+  * @brief   Разрешает прямую загрузку в регистр CMPB (теневая отключена)
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_CMP_CmpBDirectLoadCmd(PWM_TypeDef* PWMx, FunctionalState State)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(PWMx->CMPCTL_bit.SHDWBMODE, State);
+}
+
+/**
+  * @brief   Установка значения сравнения B PWM
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   CMPBVal  Значение сравнения
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_CMP_SetCmpB(PWM_TypeDef* PWMx, uint32_t CMPBVal)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_CMP_VAL(CMPBVal));
+
+    WRITE_REG(PWMx->CMPB_bit.CMPB, CMPBVal);
+}
+
+/**
+  * @brief   Получение текущего значения сравнения B PWM
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @retval  Val  Значение сравнения
+  */
+__STATIC_INLINE uint32_t PWM_CMP_GetCmpB(PWM_TypeDef* PWMx)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+
+    return READ_REG(PWMx->CMPB_bit.CMPB);
+}
+
+/**
+  * @brief   Чтение статуса флага состояния компараторов PWM.
+  *          Флаги установлены, если произошла запись в активный регистр значения сравнения из теневого.
+  *          Сбрасываются флаги автоматически при каждой записи в теневой регистр.
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   Status  Выбор флагов.
+  *                  Параметр принимает любою совокупность значений из @ref PWM_CMP_Status_Define.
+  * @retval  Status  Статус флагов. Если выбрано несколько флагов,
+  *                  то результат соответсвует логическому ИЛИ их состояний.
+  */
+__STATIC_INLINE FlagStatus PWM_CMP_Status(PWM_TypeDef* PWMx, uint32_t Status)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_CMP_STATUS(Status));
+
+    return (FlagStatus)READ_BIT(PWMx->CMPCTL, Status);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWM_Exported_Functions_HoldDetector Блок порогового выключателя
+  * @{
+  */
+
+void PWM_HD_Init(PWM_TypeDef* PWMx, PWM_HD_Init_TypeDef* InitStruct);
+void PWM_HD_StructInit(PWM_HD_Init_TypeDef* InitStruct);
+
+/**
+  * @brief   Настройка поведения канала A при поступлении события удержания
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   Action  Выбор действия
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_HD_ActionAConfig(PWM_TypeDef* PWMx, PWM_HD_Action_TypeDef Action)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_HD_ACTION(Action));
+
+    WRITE_REG(PWMx->HDCTL_bit.HDA, Action);
+}
+
+/**
+  * @brief   Настройка поведения канала B при поступлении события удержания
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   Action  Выбор действия
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_HD_ActionBConfig(PWM_TypeDef* PWMx, PWM_HD_Action_TypeDef Action)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_HD_ACTION(Action));
+
+    WRITE_REG(PWMx->HDCTL_bit.HDB, Action);
+}
+
+/**
+  * @brief   Выбор источников для генерации события удержания
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   Source  Выбор источника
+  *                  Параметр принимает любую совокупность значений из @ref PWM_HD_Source_Define
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_HD_SourceCmd(PWM_TypeDef* PWMx, uint32_t Source, FunctionalState State)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_HD_SOURCE(Source));
+
+    MODIFY_REG(PWMx->HDSEL, Source, State ? Source : 0);
+}
+
+/**
+  * @brief   Включение циклической обработки сигнала удержания
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_HD_CycleCmd(PWM_TypeDef* PWMx, FunctionalState State)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(PWMx->HDSEL_bit.CBC, State);
+}
+
+/**
+  * @brief   Включение однократной обработки сигнала удержания
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_HD_OneShotCmd(PWM_TypeDef* PWMx, FunctionalState State)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(PWMx->HDSEL_bit.OST, State);
+}
+
+/**
+  * @brief   Включение прерывания по событию удержания
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   ITSource  Выбор источника прерывания
+  *                    Параметр принимает любую совокупность значений из @ref PWM_HD_ITSource_Define.
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_HD_ITCmd(PWM_TypeDef* PWMx, uint32_t ITSource, FunctionalState State)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_HD_IT_SOURCE(ITSource));
+
+    MODIFY_REG(PWMx->HDEINT, ITSource, State ? ITSource : 0);
+}
+
+/**
+  * @brief   Программный вызов прерывания от обработчика событий удержания выбранного блока ШИМ
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   ITSource  Выбор источника прерывания
+  *                    Параметр принимает любую совокупность значений из @ref PWM_HD_ITSource_Define
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_HD_ITForceCmd(PWM_TypeDef* PWMx, uint32_t ITSource)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_HD_IT_SOURCE(ITSource));
+
+    WRITE_REG(PWMx->HDFRC, ITSource);
+}
+
+/**
+  * @brief   Чтение статуса флага прерывания от обработчика событий удержания выбранного блока ШИМ
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   ITStatus  Выбор флагов.
+  *                    Параметр принимает любую совокупность значений из @ref PWM_HD_ITSource_Define.
+  * @retval  Status  Статус прерывания. Если выбрано несколько флагов,
+  *                  то результат соответсвует логическому ИЛИ их состояний.
+  */
+__STATIC_INLINE FlagStatus PWM_HD_ITStatus(PWM_TypeDef* PWMx, uint32_t ITStatus)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_HD_IT_STATUS(ITStatus));
+
+    return (FlagStatus)READ_BIT(PWMx->HDFLG, ITStatus);
+}
+
+/**
+  * @brief   Сброс флага прерывания от обработчика событий удержания выбранного блока ШИМ
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   ITStatus  Выбор флагов.
+  *                    Параметр принимает любую совокупность значений из @ref PWM_HD_ITSource_Define.
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_HD_ITStatusClear(PWM_TypeDef* PWMx, uint32_t ITStatus)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_HD_IT_STATUS(ITStatus));
+
+    WRITE_REG(PWMx->HDCLR, ITStatus);
+}
+
+/**
+  * @brief   Чтение статуса активного запроса прерывания от обработчика событий удержания выбранного блока ШИМ
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @retval  Status  Статус запроса прерывания
+  */
+__STATIC_INLINE FlagStatus PWM_HD_ITPendStatus(PWM_TypeDef* PWMx)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+
+    return (FlagStatus)READ_BIT(PWMx->HDINTCLR, PWM_HDINTCLR_INT_Msk);
+}
+
+/**
+  * @brief  Сброс активного запроса прерывания от обработчика событий удержания выбранного блока ШИМ
+  * @param  PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @retval Нет
+  */
+__STATIC_INLINE void PWM_HD_ITPendStatusClear(PWM_TypeDef* PWMx)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+
+    WRITE_REG(PWMx->HDINTCLR_bit.INT, 1);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWM_Exported_Functions_DeadBand Блок "мертвого времени"
+  * @{
+  */
+
+void PWM_DB_Init(PWM_TypeDef* PWMx, PWM_DB_Init_TypeDef* InitStruct);
+void PWM_DB_StructInit(PWM_DB_Init_TypeDef* InitStruct);
+
+/**
+  * @brief   Выбор источников для формирования задержки
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   In  Выбор источника
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_DB_InConfig(PWM_TypeDef* PWMx, PWM_DB_In_TypeDef In)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_DB_IN(In));
+
+    WRITE_REG(PWMx->DBCTL_bit.INMODE, In);
+}
+
+/**
+  * @brief   Выбор выходных сигналов блока задержки
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   Out  Выбор сигнала
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_DB_OutConfig(PWM_TypeDef* PWMx, PWM_DB_Out_TypeDef Out)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_DB_OUT(Out));
+
+    WRITE_REG(PWMx->DBCTL_bit.OUTMODE, Out);
+}
+
+/**
+  * @brief   Выбор полярности задержанных сигналов
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   Polarity  Выбор полярности
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_DB_PolarityConfig(PWM_TypeDef* PWMx, PWM_DB_Polarity_TypeDef Polarity)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_DB_POLARITY(Polarity));
+
+    WRITE_REG(PWMx->DBCTL_bit.POLSEL, Polarity);
+}
+
+/**
+  * @brief   Установка значения величины задержки по переднему фронту
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   RiseDelayVal  Значение
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_DB_SetRiseDelay(PWM_TypeDef* PWMx, uint32_t RiseDelayVal)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_DB_DELAY_VAL(RiseDelayVal));
+
+    WRITE_REG(PWMx->DBRED, RiseDelayVal);
+}
+
+/**
+  * @brief   Установка значения величины задержки по заднему фронту
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   FallDelayVal  Значение
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_DB_SetFallDelay(PWM_TypeDef* PWMx, uint32_t FallDelayVal)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_DB_DELAY_VAL(FallDelayVal));
+
+    WRITE_REG(PWMx->DBFED, FallDelayVal);
+}
+
+/**
+  * @brief   Получение текущего значения величины задержки по переднему фронту
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t PWM_DB_GetRiseDelay(PWM_TypeDef* PWMx)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+
+    return READ_REG(PWMx->DBRED);
+}
+
+/**
+  * @brief   Получение текущего значения величины задержки по заднему фронту
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t PWM_DB_GetFallDelay(PWM_TypeDef* PWMx)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+
+    return READ_REG(PWMx->DBFED);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWM_Exported_Functions_PWM_Chopper Блок модуляции
+  * @{
+  */
+
+/**
+  * @brief   Настройка модулятора сигналов ШИМ
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   DutyVal  Значение скважности второго и последующего импульсов.
+  *                   Параметр принимает любое значение из диапазона 0x0-0x6,
+  *                   где 0x0 - скважность 1/8, а 0x6 - 7/8.
+  * @param   FreqDivVal  Значение делителя частоты второго и последующего импульсов.
+  *                      Параметр принимает любое значение из диапазона 0x0-0x7,
+  *                      где 0x0 - без деления, 0x1 - с коэф. 1/2, а 0x7 - 1/8.
+  * @param   FirstWidthVal  Значение ширины первого импульса в тактах SysClk/8.
+  *                         Параметр принимает любое значение из диапазона 0x0-0xF,
+  *                         где 0x0 - 1 такт, а 0xF - 16 тактов.
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_PC_Config(PWM_TypeDef* PWMx, uint32_t DutyVal, uint32_t FreqDivVal, uint32_t FirstWidthVal)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_PC_DUTY(DutyVal));
+    assert_param(IS_PWM_PC_FREQ_DIV(FreqDivVal));
+    assert_param(IS_PWM_PC_FIRST_WIDTH(FirstWidthVal));
+
+    MODIFY_REG(PWMx->PCCTL, PWM_PCCTL_CHPDUTY_Msk | PWM_PCCTL_CHPFREQ_Msk | PWM_PCCTL_OSTWTH_Msk,
+               ((DutyVal << PWM_PCCTL_CHPDUTY_Pos) |
+                (FreqDivVal << PWM_PCCTL_CHPFREQ_Pos) |
+                (FirstWidthVal << PWM_PCCTL_OSTWTH_Pos)));
+}
+
+/**
+  * @brief   Включение модулятора блока ШИМ
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_PC_Cmd(PWM_TypeDef* PWMx, FunctionalState State)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(PWMx->PCCTL_bit.CHPEN, State);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWM_Exported_Functions_TripZone Блок обработки сигналов аварии
+  * @{
+  */
+
+void PWM_TZ_Init(PWM_TypeDef* PWMx, PWM_TZ_Init_TypeDef* InitStruct);
+void PWM_TZ_StructInit(PWM_TZ_Init_TypeDef* InitStruct);
+
+/**
+  * @brief   Настройка поведения канала A при поступлении сигнала аварии
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   Action  Выбор действия
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_TZ_ActionAConfig(PWM_TypeDef* PWMx, PWM_TZ_Action_TypeDef Action)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_TZ_ACTION(Action));
+
+    WRITE_REG(PWMx->TZCTL_bit.TZA, Action);
+}
+
+/**
+  * @brief   Настройка поведения канала B при поступлении сигнала аварии
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   Action  Выбор действия
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_TZ_ActionBConfig(PWM_TypeDef* PWMx, PWM_TZ_Action_TypeDef Action)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_TZ_ACTION(Action));
+
+    WRITE_REG(PWMx->TZCTL_bit.TZB, Action);
+}
+
+/**
+  * @brief   Включение циклической обработки сигнала аварии
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_TZ_CycleCmd(PWM_TypeDef* PWMx, FunctionalState State)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(PWMx->TZSEL_bit.CBC, State);
+}
+
+/**
+  * @brief   Включение однократной обработки сигнала аварии
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_TZ_OneShotCmd(PWM_TypeDef* PWMx, FunctionalState State)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(PWMx->TZSEL_bit.OST, State);
+}
+
+/**
+  * @brief   Включение прерывания по сигналу аварии
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   ITSource  Выбор источника прерывания
+  *                    Параметр принимает любую совокупность значений из @ref PWM_TZ_ITSource_Define.
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_TZ_ITCmd(PWM_TypeDef* PWMx, uint32_t ITSource, FunctionalState State)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_TZ_IT_SOURCE(ITSource));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    MODIFY_REG(PWMx->TZEINT, ITSource, State ? ITSource : 0);
+}
+
+/**
+  * @brief   Чтение статуса флага прерывания от обработчика сигналов аварии выбранного блока ШИМ
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   ITStatus  Выбор флагов.
+  *                    Параметр принимает любую совокупность значений из @ref PWM_TZ_ITSource_Define.
+  * @retval  Status  Статус прерывания. Если выбрано несколько флагов,
+  *                  то результат соответсвует логическому ИЛИ их состояний.
+  */
+__STATIC_INLINE FlagStatus PWM_TZ_ITStatus(PWM_TypeDef* PWMx, uint32_t ITStatus)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_TZ_IT_STATUS(ITStatus));
+
+    return (FlagStatus)READ_BIT(PWMx->TZFLG, ITStatus);
+}
+
+/**
+  * @brief   Сброс флага прерывания от обработчика сигналов аварии выбранного блока ШИМ
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   ITStatus  Выбор флагов.
+  *                    Параметр принимает любую совокупность значений из @ref PWM_TZ_ITSource_Define.
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_TZ_ITStatusClear(PWM_TypeDef* PWMx, uint32_t ITStatus)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_TZ_IT_STATUS(ITStatus));
+
+    WRITE_REG(PWMx->TZCLR, ITStatus);
+}
+
+/**
+  * @brief   Чтение статуса активного запроса прерывания от обработчика сигналов аварии выбранного блока ШИМ
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @retval  Status  Статус запроса прерывания
+  */
+__STATIC_INLINE FlagStatus PWM_TZ_ITPendStatus(PWM_TypeDef* PWMx)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+
+    return (FlagStatus)READ_BIT(PWMx->TZINTCLR, PWM_TZINTCLR_INT_Msk);
+}
+
+/**
+  * @brief  Сброс активного запроса прерывания от обработчика сигналов аварии выбранного блока ШИМ
+  * @param  PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @retval Нет
+  */
+__STATIC_INLINE void PWM_TZ_ITPendStatusClear(PWM_TypeDef* PWMx)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+
+    WRITE_REG(PWMx->TZINTCLR_bit.INT, 1);
+}
+
+/**
+  * @brief   Программный вызов прерывания от обработчика сигналов аварии выбранного блока ШИМ
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   ITSource  Выбор источника прерывания
+  *                    Параметр принимает любую совокупность значений из @ref PWM_TZ_ITSource_Define
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_TZ_ITForceCmd(PWM_TypeDef* PWMx, uint32_t ITSource)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_TZ_IT_SOURCE(ITSource));
+
+    WRITE_REG(PWMx->TZFRC, ITSource);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWM_Exported_Functions_EventTrigger Генерация внешних сигналов
+  * @{
+  */
+
+void PWM_ET_Init(PWM_TypeDef* PWMx, PWM_ET_Init_TypeDef* InitStruct);
+void PWM_ET_StructInit(PWM_ET_Init_TypeDef* InitStruct);
+
+/**
+  * @brief   Включение генерации строба запуска АЦП по событию канала A
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_ET_SOCACmd(PWM_TypeDef* PWMx, FunctionalState State)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(PWMx->ETSEL_bit.SOCAEN, State);
+}
+
+/**
+  * @brief   Настройка события канала A для генерации строба запуска АЦП
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   Event  Выбор события
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_ET_SOCAEventConfig(PWM_TypeDef* PWMx, PWM_ET_Event_TypeDef Event)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_ET_EVENT(Event));
+
+    WRITE_REG(PWMx->ETSEL_bit.SOCASEL, Event);
+}
+
+/**
+  * @brief   Настройка количества событий канала A для генерации строба запуска АЦП
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   PeriodVal  Выбор количества событий для возникновения строба АЦП.
+                        Параметр принимает любое значение из диапазона 0-3,
+                        где 0 - соответсвует каждому событию, 1 - каждому второму и т.д.
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_ET_SOCAPeriodConfig(PWM_TypeDef* PWMx, uint32_t PeriodVal)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_ET_PERIOD(PeriodVal));
+
+    WRITE_REG(PWMx->ETPS_bit.SOCAPRD, PeriodVal);
+}
+
+/**
+  * @brief   Получение текущего значения счетчика событий, приводящих к генерации события запуска АЦП
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t PWM_ET_GetEventCountSOCA(PWM_TypeDef* PWMx)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+
+    return READ_REG(PWMx->ETPS_bit.SOCACNT);
+}
+
+/**
+  * @brief   Включение генерации строба запуска АЦП по событию канала B
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_ET_SOCBCmd(PWM_TypeDef* PWMx, FunctionalState State)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(PWMx->ETSEL_bit.SOCBEN, State);
+}
+
+/**
+  * @brief   Настройка события канала B для генерации строба запуска АЦП
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   Event  Выбор события
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_ET_SOCBEventConfig(PWM_TypeDef* PWMx, PWM_ET_Event_TypeDef Event)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_ET_EVENT(Event));
+
+    WRITE_REG(PWMx->ETSEL_bit.SOCBSEL, Event);
+}
+
+/**
+  * @brief   Настройка количества событий канала B для генерации строба запуска АЦП
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   PeriodVal  Выбор количества событий для возникновения строба АЦП.
+                        Параметр принимает любое значение из диапазона 0-3,
+                        где 0 - соответсвует каждому событию, 1 - каждому второму и т.д.
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_ET_SOCBPeriodConfig(PWM_TypeDef* PWMx, uint32_t PeriodVal)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_ET_PERIOD(PeriodVal));
+
+    WRITE_REG(PWMx->ETPS_bit.SOCBPRD, PeriodVal);
+}
+
+/**
+  * @brief   Получение текущего значения счетчика событий, приводящих к генерации события запуска АЦП
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t PWM_ET_GetEventCountSOCB(PWM_TypeDef* PWMx)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+
+    return READ_REG(PWMx->ETPS_bit.SOCBCNT);
+}
+
+/**
+  * @brief   Включение генерации запроса DMA по событию канала A
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_ET_DRQACmd(PWM_TypeDef* PWMx, FunctionalState State)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(PWMx->ETSEL_bit.DRQAEN, State);
+}
+
+/**
+  * @brief   Настройка события канала A для генерации запроса DMA
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   Event  Выбор события
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_ET_DRQAEventConfig(PWM_TypeDef* PWMx, PWM_ET_Event_TypeDef Event)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_ET_EVENT(Event));
+
+    WRITE_REG(PWMx->ETSEL_bit.DRQASEL, Event);
+}
+
+/**
+  * @brief   Настройка количества событий канала A для генерации запроса DMA
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   PeriodVal  Выбор количества событий для возникновения запроса DMA.
+                        Параметр принимает любое значение из диапазона 0-3,
+                        где 0 - соответсвует каждому событию, 1 - каждому второму и т.д.
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_ET_DRQAPeriodConfig(PWM_TypeDef* PWMx, uint32_t PeriodVal)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_ET_PERIOD(PeriodVal));
+
+    WRITE_REG(PWMx->ETPS_bit.DRQAPRD, PeriodVal);
+}
+
+/**
+  * @brief   Получение текущего значения счетчика событий, приводящих к генерации запроса DMA
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t PWM_ET_GetEventCountDRQA(PWM_TypeDef* PWMx)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+
+    return READ_REG(PWMx->ETPS_bit.DRQACNT);
+}
+
+/**
+  * @brief   Включение генерации запроса DMA по событию канала B
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_ET_DRQBCmd(PWM_TypeDef* PWMx, FunctionalState State)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(PWMx->ETSEL_bit.DRQBEN, State);
+}
+
+/**
+  * @brief   Настройка события канала B для генерации запроса DMA
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   Event  Выбор события
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_ET_DRQBEventConfig(PWM_TypeDef* PWMx, PWM_ET_Event_TypeDef Event)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_ET_EVENT(Event));
+
+    WRITE_REG(PWMx->ETSEL_bit.DRQBSEL, Event);
+}
+
+/**
+  * @brief   Настройка количества событий канала B для генерации запроса DMA
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   PeriodVal  Выбор количества событий для возникновения запроса DMA.
+                        Параметр принимает любое значение из диапазона 0-3,
+                        где 0 - соответсвует каждому событию, 1 - каждому второму и т.д.
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_ET_DRQBPeriodConfig(PWM_TypeDef* PWMx, uint32_t PeriodVal)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_ET_PERIOD(PeriodVal));
+
+    WRITE_REG(PWMx->ETPS_bit.DRQBPRD, PeriodVal);
+}
+
+/**
+  * @brief   Получение текущего значения счетчика событий, приводящих к генерации запроса DMA
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t PWM_ET_GetEventCountDRQB(PWM_TypeDef* PWMx)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+
+    return READ_REG(PWMx->ETPS_bit.DRQBCNT);
+}
+
+/**
+  * @brief   Чтение статусов флагов генерации внешних сигналов/запросов выбранным блоком ШИМ
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   Status  Выбор флагов.
+  *                  Параметр принимает любую совокупность значений из @ref PWM_ET_Status_Define.
+  * @retval  Status  Статус. Если выбрано несколько флагов,
+  *                  то результат соответсвует логическому ИЛИ их состояний.
+  */
+__STATIC_INLINE FlagStatus PWM_ET_Status(PWM_TypeDef* PWMx, uint32_t Status)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_ET_STATUS(Status));
+
+    return (FlagStatus)READ_BIT(PWMx->ETFLG, Status);
+}
+
+/**
+  * @brief   Сброс флагов генерации внешних сигналов/запросов выбранным блоком ШИМ
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   Status  Выбор флагов.
+  *                  Параметр принимает любую совокупность значений из @ref PWM_ET_Status_Define.
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_ET_StatusClear(PWM_TypeDef* PWMx, uint32_t Status)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_ET_STATUS(Status));
+
+    WRITE_REG(PWMx->ETCLR, Status);
+}
+
+/**
+  * @brief   Программный вызов генерации внешних сигналов/запросов выбранным блоком ШИМ
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   Status  Выбор источника.
+  *                  Параметр принимает любую совокупность значений из @ref PWM_ET_Status_Define
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_ET_ForceCmd(PWM_TypeDef* PWMx, uint32_t Status)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_ET_STATUS(Status));
+
+    WRITE_REG(PWMx->ETFRC, Status);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWM_Exported_Functions_IT Прерывание счетчика ШИМ
+  * @{
+  */
+
+/**
+  * @brief   Настройка события канала для генерации прерывания
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   Event  Выбор события
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_ITEventConfig(PWM_TypeDef* PWMx, PWM_ET_Event_TypeDef Event)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_ET_EVENT(Event));
+
+    WRITE_REG(PWMx->ETSEL_bit.INTSEL, Event);
+}
+
+/**
+  * @brief   Настройка количества событий для генерации прерывания
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   PeriodVal  Выбор количества событий для возникновения прерывания
+                        Параметр принимает любое значение из диапазона 0-3,
+                        где 0 - соответсвует каждому событию, 1 - каждому второму и т.д.
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_ITPeriodConfig(PWM_TypeDef* PWMx, uint32_t PeriodVal)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_PWM_ET_PERIOD(PeriodVal));
+
+    WRITE_REG(PWMx->ETPS_bit.INTPRD, PeriodVal);
+}
+
+/**
+  * @brief   Включение генерации прерывания ШИМ
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_ITCmd(PWM_TypeDef* PWMx, FunctionalState State)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(PWMx->ETSEL_bit.INTEN, State);
+}
+
+/**
+  * @brief   Получение текущего значения счетчика событий, приводящих к генерации прерывания
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t PWM_GetITEventCount(PWM_TypeDef* PWMx)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+
+    return READ_REG(PWMx->ETPS_bit.INTCNT);
+}
+
+/**
+  * @brief   Чтение статуса флага прерывания выбранного блока ШИМ
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @retval  Status  Статус
+  */
+__STATIC_INLINE FlagStatus PWM_ITStatus(PWM_TypeDef* PWMx)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+
+    return (FlagStatus)READ_BIT(PWMx->ETFLG, PWM_ETFRC_INT_Msk);
+}
+
+/**
+  * @brief   Сброс флагов прерывания выбранного блока ШИМ
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_ITStatusClear(PWM_TypeDef* PWMx)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+
+    WRITE_REG(PWMx->ETCLR, PWM_ETCLR_INT_Msk);
+}
+
+/**
+  * @brief   Чтение статуса флага активного прерывания выбранного блока ШИМ
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @retval  Status  Статус
+  */
+__STATIC_INLINE FlagStatus PWM_ITPendStatus(PWM_TypeDef* PWMx)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+
+    return (FlagStatus)READ_BIT(PWMx->INTCLR, PWM_INTCLR_INT_Msk);
+}
+
+/**
+  * @brief   Сброс флагов активного прерывания выбранного блока ШИМ
+  * @param   PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @retval  void
+  */
+__STATIC_INLINE void PWM_ITPendStatusClear(PWM_TypeDef* PWMx)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+
+    WRITE_REG(PWMx->INTCLR, PWM_INTCLR_INT_Msk);
+}
+
+/**
+  * @brief  Программный вызов прерывания выбранного блока ШИМ
+  * @param  PWMx  Выбор PWM, где x лежит в диапазоне 0-2
+  * @retval Нет
+  */
+__STATIC_INLINE void PWM_ITForceCmd(PWM_TypeDef* PWMx)
+{
+    assert_param(IS_PWM_PERIPH(PWMx));
+
+    WRITE_REG(PWMx->ETFRC, PWM_ETFRC_INT_Msk);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PLIB035_PWM_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2018 NIIET *****END OF FILE****/

platform/plib035/inc/plib035_qep.h

@@ -0,0 +1,1246 @@
+/**
+  ******************************************************************************
+  * @file    plib035_qep.h
+  *
+  * @brief   Файл содержит прототипы и компактные inline реализации функций для
+  *          QEP, а также сопутствующие макроопределения и перечисления
+  *
+  * @author  НИИЭТ, Богдан Колбов <kolbov@niiet.ru>
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ ПРЕДОСТАВЛЯЕТСЯ «КАК ЕСТЬ», БЕЗ КАКИХ-ЛИБО
+  * ГАРАНТИЙ, ЯВНО ВЫРАЖЕННЫХ ИЛИ ПОДРАЗУМЕВАЕМЫХ, ВКЛЮЧАЯ ГАРАНТИИ ТОВАРНОЙ
+  * ПРИГОДНОСТИ, СООТВЕТСТВИЯ ПО ЕГО КОНКРЕТНОМУ НАЗНАЧЕНИЮ И ОТСУТСТВИЯ
+  * НАРУШЕНИЙ, НО НЕ ОГРАНИЧИВАЯСЬ ИМИ. ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ
+  * ПРЕДНАЗНАЧЕНО ДЛЯ ОЗНАКОМИТЕЛЬНЫХ ЦЕЛЕЙ И НАПРАВЛЕНО ТОЛЬКО НА
+  * ПРЕДОСТАВЛЕНИЕ ДОПОЛНИТЕЛЬНОЙ ИНФОРМАЦИИ О ПРОДУКТЕ, С ЦЕЛЬЮ СОХРАНИТЬ ВРЕМЯ
+  * ПОТРЕБИТЕЛЮ. НИ В КАКОМ СЛУЧАЕ АВТОРЫ ИЛИ ПРАВООБЛАДАТЕЛИ НЕ НЕСУТ
+  * ОТВЕТСТВЕННОСТИ ПО КАКИМ-ЛИБО ИСКАМ, ЗА ПРЯМОЙ ИЛИ КОСВЕННЫЙ УЩЕРБ, ИЛИ
+  * ПО ИНЫМ ТРЕБОВАНИЯМ, ВОЗНИКШИМ ИЗ-ЗА ИСПОЛЬЗОВАНИЯ ПРОГРАММНОГО ОБЕСПЕЧЕНИЯ
+  * ИЛИ ИНЫХ ДЕЙСТВИЙ С ПРОГРАММНЫМ ОБЕСПЕЧЕНИЕМ.
+  *
+  * <h2><center>&copy; 2018 ОАО "НИИЭТ"</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PLIB035_QEP_H
+#define __PLIB035_QEP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "plib035.h"
+
+/** @addtogroup Peripheral
+  * @{
+  */
+
+/** @defgroup QEP
+  * @brief Драйвер для работы с QEP
+  * @{
+  */
+
+/** @defgroup QEP_Exported_Defines Константы
+  * @{
+  */
+
+/** @defgroup QEP_Flag_Define Флаги работы QEP
+  * @{
+  */
+
+#define QEP_Flag_PCError QEP_QEPSTS_PCEF_Msk             /*!< Флаг ошибки счетчика позиции. Обновляется  по каждому сигналу индексации. */
+#define QEP_Flag_FirstIndex QEP_QEPSTS_FIMF_Msk          /*!< Флаг приема первого импульса сигнала индексации */
+#define QEP_Flag_CAPDirectionError QEP_QEPSTS_CDEF_Msk   /*!< Флаг ошибки изменения направления вращения вала ротора между двумя событиями захвата */
+#define QEP_Flag_CAPCountOverflow QEP_QEPSTS_COEF_Msk    /*!< Флаг переполнения счетчика модуля захвата */
+#define QEP_Flag_QuadDirectionI QEP_QEPSTS_QDLF_Msk      /*!< Флаг направления вращения. Обновляется по каждому сигналу индексации. */
+#define QEP_Flag_QuadDirection QEP_QEPSTS_QDF_Msk        /*!< Флаг направления вращения. Обновляется по каждому событию на входах квадратур. */
+#define QEP_Flag_FirstIndexDirection QEP_QEPSTS_FIDF_Msk /*!< Индикатор направления вращения по событию первого импульса индексации. */
+#define QEP_Flag_CAPEvent QEP_QEPSTS_UPEVNT_Msk          /*!< Флаг события захвата */
+#define QEP_Flag_DirectionChange QEP_QEPSTS_DCF_Msk      /*!< Флаг изменения направления вращения вала ротора */
+#define QEP_Flag_All (QEP_Flag_PCError |             \
+                      QEP_Flag_FirstIndex |          \
+                      QEP_Flag_CAPDirectionError |   \
+                      QEP_Flag_CAPCountOverflow |    \
+                      QEP_Flag_QuadDirectionI |      \
+                      QEP_Flag_QuadDirection |       \
+                      QEP_Flag_FirstIndexDirection | \
+                      QEP_Flag_CAPEvent |            \
+                      QEP_Flag_DirectionChange) /*!< Все флаги выбраны */
+
+#define IS_QEP_FLAG(VALUE) (((VALUE) & ~QEP_Flag_All) == 0)
+
+/**
+  * @}
+  */
+
+/** @defgroup QEP_ITStatus_Define Флаги прерываний
+  * @{
+  */
+
+#define QEP_ITStatus_GeneralInt QEP_QFLG_INT_Msk      /*!< Флаг общего сигнала прерывания */
+#define QEP_ITStatus_PCError QEP_QFLG_PCE_Msk         /*!< Флаг прерывания по ошибке счетчика позиции */
+#define QEP_ITStatus_QuadPhaseError QEP_QFLG_QPE_Msk  /*!< Флаг прерывания по ошибке фазы на квадратурном входе */
+#define QEP_ITStatus_DirectionChange QEP_QFLG_QDC_Msk /*!< Флаг прерывания по смене направления вращения */
+#define QEP_ITStatus_Watchdog QEP_QFLG_WTO_Msk        /*!< Флаг прерывания по срабатыванию сторожевого таймера */
+#define QEP_ITStatus_PCOverflow QEP_QFLG_PCO_Msk      /*!< Флаг прерывания по переполнению счетчика позиции (переход через максимальное значение) */
+#define QEP_ITStatus_PCUnderflow QEP_QFLG_PCU_Msk     /*!< Флаг прерывания по недозаполнению счетчика позиции (переход через минимальное значение) */
+#define QEP_ITStatus_CMPShadowReady QEP_QFLG_PCR_Msk  /*!< Флаг прерывания по готовности компаратора к загрузке значения сравнения из отложенного регистра */
+#define QEP_ITStatus_CMP QEP_QFLG_PCM_Msk             /*!< Флаг прерывания по срабатыванию компаратора */
+#define QEP_ITStatus_Strobe QEP_QFLG_SEL_Msk          /*!< Флаг прерывания по событию стробирования */
+#define QEP_ITStatus_Index QEP_QFLG_IEL_Msk           /*!< Флаг прерывания по событию индексации */
+#define QEP_ITStatus_TMR QEP_QFLG_UTO_Msk             /*!< Флаг прерывания по таймера временных отсчетов */
+#define QEP_ITStatus_All (QEP_ITStatus_GeneralInt |      \
+                          QEP_ITStatus_PCError |         \
+                          QEP_ITStatus_QuadPhaseError |  \
+                          QEP_ITStatus_DirectionChange | \
+                          QEP_ITStatus_Watchdog |        \
+                          QEP_ITStatus_PCOverflow |      \
+                          QEP_ITStatus_PCUnderflow |     \
+                          QEP_ITStatus_CMPShadowReady |  \
+                          QEP_ITStatus_CMP |             \
+                          QEP_ITStatus_Strobe |          \
+                          QEP_ITStatus_Index |           \
+                          QEP_ITStatus_TMR) /*!< Все флаги выбраны */
+
+#define IS_QEP_IT_STATUS(VALUE) (((VALUE) & ~QEP_ITStatus_All) == 0)
+
+/**
+  * @}
+  */
+
+/** @defgroup QEP_ITSource_Define Источники прерываний
+  * @{
+  */
+
+#define QEP_ITSource_PCError QEP_QEINT_PCE_Msk         /*!< Прерывание по ошибке счетчика позиции */
+#define QEP_ITSource_QuadPhaseError QEP_QEINT_QPE_Msk  /*!< Прерывание по ошибке фазы на квадратурном входе */
+#define QEP_ITSource_DirectionChange QEP_QEINT_QDC_Msk /*!< Прерывание по смене направления вращения */
+#define QEP_ITSource_Watchdog QEP_QEINT_WTO_Msk        /*!< Прерывание по срабатыванию сторожевого таймера */
+#define QEP_ITSource_PCOverflow QEP_QEINT_PCO_Msk      /*!< Прерывание по переполнению счетчика позиции (переход через максимальное значение) */
+#define QEP_ITSource_PCUnderflow QEP_QEINT_PCU_Msk     /*!< Прерывание по недозаполнению счетчика позиции (переход через минимальное значение) */
+#define QEP_ITSource_CMPShadowReady QEP_QEINT_PCR_Msk  /*!< Прерывание по готовности компаратора к загрузке значения сравнения из отложенного регистра */
+#define QEP_ITSource_CMP QEP_QEINT_PCM_Msk             /*!< Прерывание по срабатыванию компаратора */
+#define QEP_ITSource_Strobe QEP_QEINT_SEL_Msk          /*!< Прерывание по событию стробирования */
+#define QEP_ITSource_Index QEP_QEINT_IEL_Msk           /*!< Прерывание по событию индексации */
+#define QEP_ITSource_TMR QEP_QEINT_UTO_Msk             /*!< Прерывание по таймера временных отсчетов */
+#define QEP_ITSource_All (QEP_ITSource_PCError |         \
+                          QEP_ITSource_QuadPhaseError |  \
+                          QEP_ITSource_DirectionChange | \
+                          QEP_ITSource_Watchdog |        \
+                          QEP_ITSource_PCOverflow |      \
+                          QEP_ITSource_PCUnderflow |     \
+                          QEP_ITSource_CMPShadowReady |  \
+                          QEP_ITSource_CMP |             \
+                          QEP_ITSource_Strobe |          \
+                          QEP_ITSource_Index |           \
+                          QEP_ITSource_TMR) /*!< Все источники выбраны */
+
+#define IS_QEP_IT_SOURCE(VALUE) (((VALUE) & ~QEP_ITSource_All) == 0)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup QEP_Exported_Types Типы
+  * @{
+  */
+
+/**
+  * @brief  Выбор режима остановки таймеров QEP при отладке
+  */
+typedef enum {
+    QEP_Halt_Stop = QEP_QEPCTL_FREESOFT_Stop,                /*!< Принудительная остановка */
+    QEP_Halt_StopOnOverflow = QEP_QEPCTL_FREESOFT_StopAtOvf, /*!< Остановка после переполнения */
+    QEP_Halt_Free = QEP_QEPCTL_FREESOFT_Free                 /*!< Без остановки */
+} QEP_Halt_TypeDef;
+#define IS_QEP_HALT(VALUE) (((VALUE) == QEP_Halt_Stop) ||           \
+                            ((VALUE) == QEP_Halt_StopOnOverflow) || \
+                            ((VALUE) == QEP_Halt_Free))
+
+/**
+  * @brief  Режим счёта
+  */
+typedef enum {
+    QEP_PC_Mode_Quad = QEP_QDECCTL_QSRC_Quad,         /*!< Квадратурный режим счета */
+    QEP_PC_Mode_CountDir = QEP_QDECCTL_QSRC_CountDir, /*!< Режим счета-направления */
+    QEP_PC_Mode_CountUp = QEP_QDECCTL_QSRC_Up,        /*!< Счет вверх */
+    QEP_PC_Mode_CountDown = QEP_QDECCTL_QSRC_Down     /*!< Счет вниз */
+} QEP_PC_Mode_TypeDef;
+#define IS_QEP_PC_MODE(VALUE) (((VALUE) == QEP_PC_Mode_Quad) ||     \
+                               ((VALUE) == QEP_PC_Mode_CountDir) || \
+                               ((VALUE) == QEP_PC_Mode_CountUp) ||  \
+                               ((VALUE) == QEP_PC_Mode_CountDown))
+
+/**
+  * @brief  Выбор скорости счета для режимов счета вверх или вниз
+  */
+typedef enum {
+    QEP_PC_CountRate_Single, /*!< Счет по переднему фронту */
+    QEP_PC_CountRate_Double  /*!< Счет по обоим перепадам */
+} QEP_PC_CountRate_TypeDef;
+#define IS_QEP_PC_COUNT_RATE(VALUE) (((VALUE) == QEP_PC_CountRate_Single) || \
+                                     ((VALUE) == QEP_PC_CountRate_Double))
+
+/**
+  * @brief  Выбор события для сброса счетчика позиции
+  */
+typedef enum {
+    QEP_PC_ResetEvent_Index = QEP_QEPCTL_PCRM_Ind,           /*!< Событие индексации */
+    QEP_PC_ResetEvent_CountMax = QEP_QEPCTL_PCRM_PosMax,     /*!< Достижение счетчиком максимального значения */
+    QEP_PC_ResetEvent_FirstIndex = QEP_QEPCTL_PCRM_FirstInd, /*!< Первое событие индексации */
+    QEP_PC_ResetEvent_TMR = QEP_QEPCTL_PCRM_Time             /*!< Окончание временного отсчета */
+} QEP_PC_ResetEvent_TypeDef;
+#define IS_QEP_PC_RESET_EVENT(VALUE) (((VALUE) == QEP_PC_ResetEvent_Index) ||      \
+                                      ((VALUE) == QEP_PC_ResetEvent_CountMax) ||   \
+                                      ((VALUE) == QEP_PC_ResetEvent_FirstIndex) || \
+                                      ((VALUE) == QEP_PC_ResetEvent_TMR))
+
+/**
+  * @brief  Выбор события стробирования для инициализации счетчика позиции
+  */
+typedef enum {
+    QEP_PC_InitEventS_None = QEP_QEPCTL_SEI_NoInit,            /*!< Без инициализации */
+    QEP_PC_InitEventS_Rise = QEP_QEPCTL_SEI_QEPSPos,           /*!< По переднему фронту S */
+    QEP_PC_InitEventS_UpRiseDownFall = QEP_QEPCTL_SEI_QEPSDir, /*!< По переднему фронту S при счете вверх (вращение по часовой, вперед)
+                                                                    и по заднему фронту S при счете вниз (вращение против часовой, назад) */
+} QEP_PC_InitEventS_TypeDef;
+#define IS_QEP_PC_INIT_EVENT_S(VALUE) (((VALUE) == QEP_PC_InitEventS_None) || \
+                                       ((VALUE) == QEP_PC_InitEventS_Rise) || \
+                                       ((VALUE) == QEP_PC_InitEventS_UpRiseDownFall))
+
+/**
+  * @brief  Выбор события индексации для инициализации счетчика позиции
+  */
+typedef enum {
+    QEP_PC_InitEventI_None = QEP_QEPCTL_IEI_NoInit,  /*!< Без инициализации */
+    QEP_PC_InitEventI_Rise = QEP_QEPCTL_IEI_QEPIPos, /*!< По переднему фронту I */
+    QEP_PC_InitEventI_Fall = QEP_QEPCTL_IEI_QEPINeg, /*!< По заднему фронту I */
+} QEP_PC_InitEventI_TypeDef;
+#define IS_QEP_PC_INIT_EVENT_I(VALUE) (((VALUE) == QEP_PC_InitEventI_None) || \
+                                       ((VALUE) == QEP_PC_InitEventI_Rise) || \
+                                       ((VALUE) == QEP_PC_InitEventI_Fall))
+
+/**
+  * @brief  Выбор события стробирования для сохранения значения счетчика позиции
+  */
+typedef enum {
+    QEP_PC_LatchEventS_Rise,           /*!< По переднему фронту S */
+    QEP_PC_LatchEventS_UpRiseDownFall, /*!< По переднему фронту S при счете вверх (вращение по часовой, вперед)
+                                           и по заднему фронту S при счете вниз (вращение против часовой, назад) */
+} QEP_PC_LatchEventS_TypeDef;
+#define IS_QEP_PC_LATCH_EVENT_S(VALUE) (((VALUE) == QEP_PC_LatchEventS_Rise) || \
+                                        ((VALUE) == QEP_PC_LatchEventS_UpRiseDownFall))
+
+/**
+  * @brief  Выбор события индексации для сохранения значения счетчика позиции
+  */
+typedef enum {
+    QEP_PC_LatchEventI_None = QEP_QEPCTL_IEL_NoLatch,  /*!< Без сохранения */
+    QEP_PC_LatchEventI_Rise = QEP_QEPCTL_IEL_IndPos,   /*!< По переднему фронту I */
+    QEP_PC_LatchEventI_Fall = QEP_QEPCTL_IEL_IndNeg,   /*!< По заднему фронту I */
+    QEP_PC_LatchEventI_Marker = QEP_QEPCTL_IEL_IndMark /*!< По маркеру индексации */
+} QEP_PC_LatchEventI_TypeDef;
+#define IS_QEP_PC_LATCH_EVENT_I(VALUE) (((VALUE) == QEP_PC_LatchEventI_None) || \
+                                        ((VALUE) == QEP_PC_LatchEventI_Rise) || \
+                                        ((VALUE) == QEP_PC_LatchEventI_Fall) || \
+                                        ((VALUE) == QEP_PC_LatchEventI_Marker))
+
+/**
+  * @brief  Выбор события загрузки для отложенной записи значения сравнения счетчика позиции
+  */
+typedef enum {
+    QEP_CMP_LoadEvent_PCCountEqZero, /*!< Загрузка по равенству счетчика позиции нулю */
+    QEP_CMP_LoadEvent_PCCountEqComp  /*!< Загрузка по равенству счетчика позиции значению сравнения */
+} QEP_CMP_LoadEvent_TypeDef;
+#define IS_QEP_CMP_LOAD_EVENT(VALUE) (((VALUE) == QEP_CMP_LoadEvent_PCCountEqZero) || \
+                                      ((VALUE) == QEP_CMP_LoadEvent_PCCountEqComp))
+
+/**
+  * @brief  Выбор вывода для выдачи выходного сигнала компаратора
+  */
+typedef enum {
+    QEP_CMP_Out_S, /*!< Вывод сигнала строба */
+    QEP_CMP_Out_I  /*!< Вывод сигнала индекса */
+} QEP_CMP_Out_TypeDef;
+#define IS_QEP_CMP_OUT(VALUE) (((VALUE) == QEP_CMP_Out_S) || \
+                               ((VALUE) == QEP_CMP_Out_I))
+
+/**
+  * @brief  Выбор полярности выходного сигнала компаратора счетчика позиции
+  */
+typedef enum {
+    QEP_CMP_OutPolarity_ActiveHigh, /*!< Активная единица */
+    QEP_CMP_OutPolarity_ActiveLow,  /*!< Активный ноль */
+} QEP_CMP_OutPolarity_TypeDef;
+#define IS_QEP_CMP_OUT_POLARITY(VALUE) (((VALUE) == QEP_CMP_OutPolarity_ActiveHigh) || \
+                                        ((VALUE) == QEP_CMP_OutPolarity_ActiveLow))
+
+/**
+  * @brief  Выбор события для сброса таймера захвата
+  */
+typedef enum {
+    QEP_CAP_ResetEvent_QCLKDiv, /*!< Деленное квадратурное событие */
+    QEP_CAP_ResetEvent_CMPOut   /*!< Выходной сигнал компаратора счетчика позиции */
+} QEP_CAP_ResetEvent_TypeDef;
+#define IS_QEP_CAP_RESET_EVENT(VALUE) (((VALUE) == QEP_CAP_ResetEvent_QCLKDiv) || \
+                                       ((VALUE) == QEP_CAP_ResetEvent_CMPOut))
+
+/**
+  * @brief  Коэффициент деления тактового сигнала PCLK для таймера захвата
+  */
+typedef enum {
+    QEP_CAP_PCLKDiv_1 = QEP_QCAPCTL_CCPS_Disable, /*!< Без деления тактовой частоты */
+    QEP_CAP_PCLKDiv_2 = QEP_QCAPCTL_CCPS_Div2,    /*!< Деление тактовой частоты на 2 */
+    QEP_CAP_PCLKDiv_4 = QEP_QCAPCTL_CCPS_Div4,    /*!< Деление тактовой частоты на 4 */
+    QEP_CAP_PCLKDiv_8 = QEP_QCAPCTL_CCPS_Div8,    /*!< Деление тактовой частоты на 8 */
+    QEP_CAP_PCLKDiv_16 = QEP_QCAPCTL_CCPS_Div16,  /*!< Деление тактовой частоты на 16 */
+    QEP_CAP_PCLKDiv_32 = QEP_QCAPCTL_CCPS_Div32,  /*!< Деление тактовой частоты на 32 */
+    QEP_CAP_PCLKDiv_64 = QEP_QCAPCTL_CCPS_Div64,  /*!< Деление тактовой частоты на 64 */
+    QEP_CAP_PCLKDiv_128 = QEP_QCAPCTL_CCPS_Div128 /*!< Деление тактовой частоты на 128 */
+} QEP_CAP_PCLKDiv_TypeDef;
+#define IS_QEP_CAP_PCLK_DIV(VALUE) (((VALUE) == QEP_CAP_PCLKDiv_1) ||  \
+                                    ((VALUE) == QEP_CAP_PCLKDiv_2) ||  \
+                                    ((VALUE) == QEP_CAP_PCLKDiv_4) ||  \
+                                    ((VALUE) == QEP_CAP_PCLKDiv_8) ||  \
+                                    ((VALUE) == QEP_CAP_PCLKDiv_16) || \
+                                    ((VALUE) == QEP_CAP_PCLKDiv_32) || \
+                                    ((VALUE) == QEP_CAP_PCLKDiv_64) || \
+                                    ((VALUE) == QEP_CAP_PCLKDiv_128))
+
+/**
+  * @brief  Коэффициент деления квадратурных событий
+  */
+typedef enum {
+    QEP_CAP_QCLKDiv_1 = QEP_QCAPCTL_UPPS_Disable,    /*!< Без деления квадратурных событий */
+    QEP_CAP_QCLKDiv_2 = QEP_QCAPCTL_UPPS_Div2,       /*!< Деление квадратурных событий на 2 */
+    QEP_CAP_QCLKDiv_4 = QEP_QCAPCTL_UPPS_Div4,       /*!< Деление квадратурных событий на 4 */
+    QEP_CAP_QCLKDiv_8 = QEP_QCAPCTL_UPPS_Div8,       /*!< Деление квадратурных событий на 8 */
+    QEP_CAP_QCLKDiv_16 = QEP_QCAPCTL_UPPS_Div16,     /*!< Деление квадратурных событий на 16 */
+    QEP_CAP_QCLKDiv_32 = QEP_QCAPCTL_UPPS_Div32,     /*!< Деление квадратурных событий на 32 */
+    QEP_CAP_QCLKDiv_64 = QEP_QCAPCTL_UPPS_Div64,     /*!< Деление квадратурных событий на 64 */
+    QEP_CAP_QCLKDiv_128 = QEP_QCAPCTL_UPPS_Div128,   /*!< Деление квадратурных событий на 128 */
+    QEP_CAP_QCLKDiv_256 = QEP_QCAPCTL_UPPS_Div256,   /*!< Деление квадратурных событий на 64 */
+    QEP_CAP_QCLKDiv_512 = QEP_QCAPCTL_UPPS_Div512,   /*!< Деление квадратурных событий на 128 */
+    QEP_CAP_QCLKDiv_1024 = QEP_QCAPCTL_UPPS_Div1024, /*!< Деление квадратурных событий на 64 */
+    QEP_CAP_QCLKDiv_2048 = QEP_QCAPCTL_UPPS_Div2048, /*!< Деление квадратурных событий на 128 */
+} QEP_CAP_QCLKDiv_TypeDef;
+#define IS_QEP_CAP_QCLK_DIV(VALUE) (((VALUE) == QEP_CAP_QCLKDiv_1) ||    \
+                                    ((VALUE) == QEP_CAP_QCLKDiv_2) ||    \
+                                    ((VALUE) == QEP_CAP_QCLKDiv_4) ||    \
+                                    ((VALUE) == QEP_CAP_QCLKDiv_8) ||    \
+                                    ((VALUE) == QEP_CAP_QCLKDiv_16) ||   \
+                                    ((VALUE) == QEP_CAP_QCLKDiv_32) ||   \
+                                    ((VALUE) == QEP_CAP_QCLKDiv_64) ||   \
+                                    ((VALUE) == QEP_CAP_QCLKDiv_128) ||  \
+                                    ((VALUE) == QEP_CAP_QCLKDiv_256) ||  \
+                                    ((VALUE) == QEP_CAP_QCLKDiv_512) ||  \
+                                    ((VALUE) == QEP_CAP_QCLKDiv_1024) || \
+                                    ((VALUE) == QEP_CAP_QCLKDiv_2048))
+
+/**
+  * @brief  Выбор события для сохранения значения регистров модуля захвата
+  */
+typedef enum {
+    QEP_CAP_LatchEvent_ReadPCCount,     /*!< Чтение счетного регистра счетчика позиции */
+    QEP_CAP_LatchEvent_TMRCountEqPeriod /*!< Равенство счетного регистра таймера периоду */
+} QEP_CAP_LatchEvent_TypeDef;
+#define IS_QEP_CAP_LATCH_EVENT(VALUE) (((VALUE) == QEP_CAP_LatchEvent_ReadPCCount) || \
+                                       ((VALUE) == QEP_CAP_LatchEvent_TMRCountEqPeriod))
+
+/**
+  * @brief  Структура инициализации счётчика позиции
+  */
+typedef struct
+{
+    QEP_PC_Mode_TypeDef Mode;
+    QEP_PC_CountRate_TypeDef CountRate;
+    QEP_PC_ResetEvent_TypeDef ResetEvent;
+    QEP_PC_InitEventS_TypeDef InitEventS;
+    QEP_PC_InitEventI_TypeDef InitEventI;
+    QEP_PC_LatchEventS_TypeDef LatchEventS;
+    QEP_PC_LatchEventI_TypeDef LatchEventI;
+    uint32_t Count;
+    uint32_t CountInit;
+    uint32_t CountMax;
+} QEP_PC_Init_TypeDef;
+
+/**
+  * @brief  Структура инициализации компаратора счётчика позиции
+  */
+typedef struct
+{
+    FunctionalState ShadowLoad;
+    QEP_CMP_LoadEvent_TypeDef LoadEvent;
+    QEP_CMP_Out_TypeDef Out;
+    FunctionalState OutEn;
+    QEP_CMP_OutPolarity_TypeDef OutPolarity;
+    uint32_t OutWidth;
+    uint32_t Comp;
+} QEP_CMP_Init_TypeDef;
+#define IS_QEP_CMP_OUT_WIDTH_VAL(VALUE) ((VALUE) < 0x1000)
+
+/**
+  * @brief  Структура инициализации модуля захвата времени
+  */
+typedef struct
+{
+    FunctionalState DivShadowLoad;
+    QEP_CAP_ResetEvent_TypeDef ResetEvent;
+    QEP_CAP_PCLKDiv_TypeDef PCLKDiv;
+    QEP_CAP_QCLKDiv_TypeDef QCLKDiv;
+    QEP_CAP_LatchEvent_TypeDef LatchEvent;
+    uint32_t Count;
+    uint32_t Period;
+} QEP_CAP_Init_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup QEP_Exported_Functions Функции
+  * @{
+  */
+
+void QEP_DeInit(void);
+
+/**
+  * @brief   Разрешение работы выводов QEP
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_RemapCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(SIU->REMAPAF_bit.QEPEN, State);
+}
+
+/**
+  * @brief   Запрос состояния выбранного флага
+  * @param   Flag  Выбор флагов.
+  *                Параметр принимает любую совокупность значений QEP_Flag_x из @ref QEP_Flag_Define.
+  * @retval  Status  Состояние флага. Если выбрано несколько флагов,
+  *                  то результат соответсвует логическому ИЛИ их состояний.
+  */
+__STATIC_INLINE FlagStatus QEP_FlagStatus(uint32_t Flag)
+{
+    assert_param(IS_QEP_FLAG(Flag));
+
+    return (FlagStatus)READ_BIT(QEP->QEPSTS, Flag);
+}
+
+/**
+  * @brief   Сброс флагов
+  * @param   Status  Выбор флагов.
+  *                  Параметр принимает любою совокупность значений из @ref QEP_Flag_Define.
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_FlagStatusClear(uint32_t Flag)
+{
+    assert_param(IS_QEP_FLAG(Flag));
+
+    WRITE_REG(QEP->QEPSTS, Flag);
+}
+
+/**
+  * @brief   Настройка режима остановки всех счетчиков таймеров QEP
+  * @param   Halt  Выбор режима
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_HaltConfig(QEP_Halt_TypeDef Halt)
+{
+    assert_param(IS_QEP_HALT(Halt));
+
+    WRITE_REG(QEP->QEPCTL_bit.FREESOFT, Halt);
+}
+
+/** @defgroup QEP_Exported_Functions_IO Управление входами
+  * @{
+  */
+
+/**
+  * @brief   Включение обмена входов A и B местами
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_IO_SwapABCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(QEP->QDECCTL_bit.SWAP, State);
+}
+
+/**
+  * @brief   Включение стробирования сигнала индекса
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_IO_GateICmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(QEP->QDECCTL_bit.IGATE, State);
+}
+
+/**
+  * @brief   Включение инверсии входа A
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_IO_InvACmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(QEP->QDECCTL_bit.QAP, State);
+}
+
+/**
+  * @brief   Включение инверсии входа B
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_IO_InvBCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(QEP->QDECCTL_bit.QBP, State);
+}
+
+/**
+  * @brief   Включение инверсии входа I (индекса)
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_IO_InvICmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(QEP->QDECCTL_bit.QIP, State);
+}
+
+/**
+  * @brief   Включение инверсии входа S (строба)
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_IO_InvSCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(QEP->QDECCTL_bit.QSP, State);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup QEP_Exported_Functions_PositionCounter Счётчик позиции
+  * @{
+  */
+
+void QEP_PC_Init(QEP_PC_Init_TypeDef* InitStruct);
+void QEP_PC_StructInit(QEP_PC_Init_TypeDef* InitStruct);
+
+/**
+  * @brief   Включение счётчика позиции
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_PC_Cmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(QEP->QEPCTL_bit.QPEN, State);
+}
+
+/**
+  * @brief   Настройка режима счета
+  * @param   Mode  Выбор режима
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_PC_ModeConfig(QEP_PC_Mode_TypeDef Mode)
+{
+    assert_param(IS_QEP_PC_MODE(Mode));
+
+    WRITE_REG(QEP->QDECCTL_bit.QSRC, Mode);
+}
+
+/**
+  * @brief   Настройка скорости счета для режимов счета вверх или вниз
+  * @param   CountRate  Выбор режима
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_PC_CountRateConfig(QEP_PC_CountRate_TypeDef CountRate)
+{
+    assert_param(IS_QEP_PC_COUNT_RATE(CountRate));
+
+    WRITE_REG(QEP->QDECCTL_bit.XCR, CountRate);
+}
+
+/**
+  * @brief   Настройка события для сброса счетчика позиции
+  * @param   ResetEvent  Выбор события
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_PC_ResetEventConfig(QEP_PC_ResetEvent_TypeDef ResetEvent)
+{
+    assert_param(IS_QEP_PC_RESET_EVENT(ResetEvent));
+
+    WRITE_REG(QEP->QEPCTL_bit.PCRM, ResetEvent);
+}
+
+/**
+  * @brief   Настройка события стробирования для инициализации счетчика позиции
+  * @param   InitEvent  Выбор события
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_PC_InitEventSConfig(QEP_PC_InitEventS_TypeDef InitEvent)
+{
+    assert_param(IS_QEP_PC_INIT_EVENT_S(InitEvent));
+
+    WRITE_REG(QEP->QEPCTL_bit.SEI, InitEvent);
+}
+
+/**
+  * @brief   Настройка события индексации для инициализации счетчика позиции
+  * @param   InitEvent  Выбор события
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_PC_InitEventIConfig(QEP_PC_InitEventI_TypeDef InitEvent)
+{
+    assert_param(IS_QEP_PC_INIT_EVENT_I(InitEvent));
+
+    WRITE_REG(QEP->QEPCTL_bit.IEI, InitEvent);
+}
+
+/**
+  * @brief   Выполнение программной инициализации счетчика позиции
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_PC_SwInitCmd(void)
+{
+    WRITE_REG(QEP->QEPCTL_bit.SWI, 1);
+}
+
+/**
+  * @brief   Настройка события стробирования для сохранения счетчика позиции
+  * @param   InitEvent  Выбор события
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_PC_LatchEventSConfig(QEP_PC_LatchEventS_TypeDef LatchEvent)
+{
+    assert_param(IS_QEP_PC_LATCH_EVENT_S(LatchEvent));
+
+    WRITE_REG(QEP->QEPCTL_bit.SEL, LatchEvent);
+}
+
+/**
+  * @brief   Настройка события индексации для сохранения счетчика позиции
+  * @param   InitEvent  Выбор события
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_PC_LatchEventIConfig(QEP_PC_LatchEventI_TypeDef LatchEvent)
+{
+    assert_param(IS_QEP_PC_LATCH_EVENT_I(LatchEvent));
+
+    WRITE_REG(QEP->QEPCTL_bit.IEL, LatchEvent);
+}
+
+/**
+  * @brief   Установка значения счетчика позиции
+  * @param   Val  Значение
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_PC_SetCount(uint32_t Val)
+{
+    WRITE_REG(QEP->QPOSCNT, Val);
+}
+
+/**
+  * @brief   Получение текущего значения счетчика позиции
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t QEP_PC_GetCount(void)
+{
+    return READ_REG(QEP->QPOSCNT);
+}
+
+/**
+  * @brief   Установка значения инициализации счетчика позиции
+  * @param   Val  Значение
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_PC_SetCountInit(uint32_t Val)
+{
+    WRITE_REG(QEP->QPOSINIT, Val);
+}
+
+/**
+  * @brief   Получение текущего значения инициализации счетчика позиции
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t QEP_PC_GetCountInit(void)
+{
+    return READ_REG(QEP->QPOSINIT);
+}
+
+/**
+  * @brief   Установка максимального значения счетчика позиции
+  * @param   Val  Значение
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_PC_SetCountMax(uint32_t Val)
+{
+    WRITE_REG(QEP->QPOSMAX, Val);
+}
+
+/**
+  * @brief   Получение текущего максимального значения счетчика позиции
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t QEP_PC_GetCountMax(void)
+{
+    return READ_REG(QEP->QPOSMAX);
+}
+
+/**
+  * @brief   Получение сохраненного значения счетчика позиции по стробу
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t QEP_PC_GetCountLatchS(void)
+{
+    return READ_REG(QEP->QPOSSLAT);
+}
+
+/**
+  * @brief   Получение сохраненного значения счетчика позиции по индексу
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t QEP_PC_GetCountLatchI(void)
+{
+    return READ_REG(QEP->QPOSILAT);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup QEP_Exported_Functions_PositionCompare Компаратор
+  * @{
+  */
+
+void QEP_CMP_Init(QEP_CMP_Init_TypeDef* InitStruct);
+void QEP_CMP_StructInit(QEP_CMP_Init_TypeDef* InitStruct);
+
+/**
+  * @brief   Включение компаратора счётчика позиции
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_CMP_Cmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(QEP->QPOSCTL_bit.PCE, State);
+}
+
+/**
+  * @brief   Включение отложенной загрузки компаратора счётчика позиции
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_CMP_ShadowLoadCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(QEP->QPOSCTL_bit.PCSHDW, State);
+}
+
+/**
+  * @brief   Настройка события для отложенной загрузки компаратора счётчика позиции
+  * @param   LoadEvent  Выбор события
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_CMP_LoadEventConfig(QEP_CMP_LoadEvent_TypeDef LoadEvent)
+{
+    assert_param(IS_QEP_CMP_LOAD_EVENT(LoadEvent));
+
+    WRITE_REG(QEP->QPOSCTL_bit.PCLOAD, LoadEvent);
+}
+
+/**
+  * @brief   Настройка вывода для выдачи выходного сигнала компаратора счётчика позиции
+  * @param   Out  Выбор вывода
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_CMP_OutConfig(QEP_CMP_Out_TypeDef Out)
+{
+    assert_param(IS_QEP_CMP_OUT(Out));
+
+    WRITE_REG(QEP->QDECCTL_bit.SPSEL, Out);
+}
+
+/**
+  * @brief   Разрешение выходного сигнала компаратора счётчика позиции
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_CMP_OutCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(QEP->QDECCTL_bit.SOEN, State);
+}
+
+/**
+  * @brief   Настройка полярности выходного сигнала компаратора счетчика позиции
+  * @param   OutPolarity  Выбор режима
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_CMP_OutPolarityConfig(QEP_CMP_OutPolarity_TypeDef OutPolarity)
+{
+    assert_param(IS_QEP_CMP_OUT_POLARITY(OutPolarity));
+
+    WRITE_REG(QEP->QPOSCTL_bit.PCPOL, OutPolarity);
+}
+
+/**
+  * @brief   Настройка ширигы импульса выходного сигнала компаратора счетчика позиции
+  * @param   OutPolarity  Выбор режима
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_CMP_SetOutWidth(uint32_t OutWidth)
+{
+    assert_param(IS_QEP_CMP_OUT_WIDTH_VAL(OutWidth));
+
+    WRITE_REG(QEP->QPOSCTL_bit.PCSPW, OutWidth);
+}
+
+/**
+  * @brief   Установка значения компаратора счетчика позиции
+  * @param   Val  Значение
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_CMP_SetComp(uint32_t Val)
+{
+    WRITE_REG(QEP->QPOSCMP, Val);
+}
+
+/**
+  * @brief   Получение текущего значения компаратора счетчика позиции
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t QEP_CMP_GetComp(void)
+{
+    return READ_REG(QEP->QPOSCMP);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup QEP_Exported_Functions_CaptureTime Модуль захвата времени
+  * @{
+  */
+
+void QEP_CAP_Init(QEP_CAP_Init_TypeDef* InitStruct);
+void QEP_CAP_StructInit(QEP_CAP_Init_TypeDef* InitStruct);
+
+/**
+  * @brief   Включение модуля захвата времени
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_CAP_Cmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(QEP->QCAPCTL_bit.CEN, State);
+}
+
+/**
+  * @brief   Включение теневой загрузки делителей модуля захвата времени
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_CAP_DivShadowLoadCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(QEP->QCAPCTL_bit.EPSLD, State);
+}
+
+/**
+  * @brief   Настройка события сброса счетчика модуля захвата времени
+  * @param   ResetEvent  Выбор события
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_CAP_ResetEventConfig(QEP_CAP_ResetEvent_TypeDef ResetEvent)
+{
+    assert_param(IS_QEP_CAP_RESET_EVENT(ResetEvent));
+
+    WRITE_REG(QEP->QCAPCTL_bit.SELEVENT, ResetEvent);
+}
+
+/**
+  * @brief   Настройка делителей для модуля захвата времени
+  * @param   PCLKDiv  Выбор делителя PCLK
+  * @param   QCLKDiv  Выбор делителя QCLK
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_CAP_DivConfig(QEP_CAP_PCLKDiv_TypeDef PCLKDiv, QEP_CAP_QCLKDiv_TypeDef QCLKDiv)
+{
+    assert_param(IS_QEP_CAP_PCLK_DIV(PCLKDiv));
+    assert_param(IS_QEP_CAP_QCLK_DIV(QCLKDiv));
+
+    MODIFY_REG(QEP->QCAPCTL, QEP_QCAPCTL_CCPS_Msk | QEP_QCAPCTL_UPPS_Msk,
+               ((PCLKDiv << QEP_QCAPCTL_CCPS_Pos) | (QCLKDiv << QEP_QCAPCTL_UPPS_Pos)));
+}
+
+/**
+  * @brief   Настройка делителя PCLK для модуля захвата времени
+  * @param   PCLKDiv  Выбор делителя
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_CAP_PCLKDivConfig(QEP_CAP_PCLKDiv_TypeDef PCLKDiv)
+{
+    assert_param(IS_QEP_CAP_PCLK_DIV(PCLKDiv));
+
+    WRITE_REG(QEP->QCAPCTL_bit.CCPS, PCLKDiv);
+}
+
+/**
+  * @brief   Настройка делителя QCLK для модуля захвата времени
+  * @param   QCLKDiv  Выбор делителя
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_CAP_QCLKDivConfig(QEP_CAP_QCLKDiv_TypeDef QCLKDiv)
+{
+    assert_param(IS_QEP_CAP_QCLK_DIV(QCLKDiv));
+
+    WRITE_REG(QEP->QCAPCTL_bit.UPPS, QCLKDiv);
+}
+
+/**
+  * @brief   Настройка события сохранения значения регистров модуля захвата
+  * @param   LatchEvent  Выбор события
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_CAP_LatchEventConfig(QEP_CAP_LatchEvent_TypeDef LatchEvent)
+{
+    assert_param(IS_QEP_CAP_LATCH_EVENT(LatchEvent));
+
+    WRITE_REG(QEP->QEPCTL_bit.QCLM, LatchEvent);
+}
+
+/**
+  * @brief   Установка значения счетчика модуля захвата
+  * @param   Val  Значение
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_CAP_SetCount(uint32_t Val)
+{
+    WRITE_REG(QEP->QCTMR, Val);
+}
+
+/**
+  * @brief   Получение текущего значения счетчика модуля захвата
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t QEP_CAP_GetCount(void)
+{
+    return READ_REG(QEP->QCTMR);
+}
+
+/**
+  * @brief   Установка значения периода модуля захвата
+  * @param   Val  Значение
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_CAP_SetPeriod(uint32_t Val)
+{
+    WRITE_REG(QEP->QCPRD, Val);
+}
+
+/**
+  * @brief   Получение текущего значения периода модуля захвата
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t QEP_CAP_GetPeriod(void)
+{
+    return READ_REG(QEP->QCPRD);
+}
+
+/**
+  * @brief   Получение сохраненного значения счетчика модуля захвата
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t QEP_PC_GetCountLatch(void)
+{
+    return READ_REG(QEP->QCTMRLAT);
+}
+
+/**
+  * @brief   Получение сохраненного значения периода модуля захвата
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t QEP_PC_GetPeriodLatch(void)
+{
+    return READ_REG(QEP->QCPRDLAT);
+}
+
+/**
+  * @brief   Включение генерации запроса DMA событию захвата
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_CAP_DMACmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(QEP->DMAREQ_bit.DMAEN, State);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup QEP_Exported_Functions_UnitTimer Таймер временных отсчетов
+  * @{
+  */
+
+/**
+  * @brief   Включение таймера временных отсчетов
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_TMR_Cmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(QEP->QEPCTL_bit.UTE, State);
+}
+
+/**
+  * @brief   Установка значения счетчика таймера временных отсчетов
+  * @param   Val  Значение
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_TMR_SetCount(uint32_t Val)
+{
+    WRITE_REG(QEP->QUTMR, Val);
+}
+
+/**
+  * @brief   Получение значения счетчика таймера временных отсчетов
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t QEP_TMR_GetCount(void)
+{
+    return READ_REG(QEP->QUTMR);
+}
+
+/**
+  * @brief   Установка значения периода таймера временных отсчетов
+  * @param   Val  Значение
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_TMR_SetPeriod(uint32_t Val)
+{
+    WRITE_REG(QEP->QUPRD, Val);
+}
+
+/**
+  * @brief   Получение значения периода таймера временных отсчетов
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t QEP_TMR_GetPeriod(void)
+{
+    return READ_REG(QEP->QUPRD);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup QEP_Exported_Functions_Watchdog Сторожевой таймер
+  * @{
+  */
+
+/**
+  * @brief   Включение сторожевого таймера
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_WDT_Cmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(QEP->QEPCTL_bit.WDE, State);
+}
+
+/**
+  * @brief   Установка значения счетчика сторожевого таймера
+  * @param   Val  Значение
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_WDT_SetCount(uint32_t Val)
+{
+    WRITE_REG(QEP->QWDTMR, Val);
+}
+
+/**
+  * @brief   Получение значения счетчика сторожевого таймера
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t QEP_WDT_GetCount(void)
+{
+    return READ_REG(QEP->QWDTMR);
+}
+
+/**
+  * @brief   Установка значения периода сторожевого таймера
+  * @param   Val  Значение
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_WDT_SetPeriod(uint32_t Val)
+{
+    WRITE_REG(QEP->QWDPRD, Val);
+}
+
+/**
+  * @brief   Получение значения периода сторожевого таймера
+  * @retval  Val  Значение
+  */
+__STATIC_INLINE uint32_t QEP_WDT_GetPeriod(void)
+{
+    return READ_REG(QEP->QWDPRD);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup QEP_Exported_Functions_IT Прерывания
+  * @{
+  */
+
+/**
+  * @brief   Разрешение генерации прерываний
+  * @param   ITSource  Выбор источников прерывания
+  *                    Параметр принимает любою совокупность значений QEP_ITSource_x из @ref QEP_ITSource_define.
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_ITCmd(uint32_t ITSource, FunctionalState State)
+{
+    assert_param(IS_QEP_IT_SOURCE(ITSource));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    MODIFY_REG(QEP->QEINT, ITSource, State ? (uint32_t)ITSource : 0);
+}
+
+/**
+  * @brief   Принудительный вызов прерывания
+  * @param   ITSource  Выбор источников прерывания
+  *                    Параметр принимает любою совокупность значений QEP_ITSource_x из @ref QEP_ITSource_define.
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_ITForceCmd(uint32_t ITSource)
+{
+    assert_param(IS_QEP_IT_SOURCE(ITSource));
+
+    WRITE_REG(QEP->QFRC, ITSource);
+}
+
+/**
+  * @brief   Чтение статуса прерывания
+  * @param   ITStatus  Выбор флага прерывания.
+  *                    Параметр принимает любою совокупность значений QEP_ITStatus_x из @ref QEP_ITStatus_define.
+  * @retval  Status  Статус прерывания. Если выбрано несколько прерываний,
+  *                  то результат соответсвует логическому ИЛИ их состояний.
+  */
+__STATIC_INLINE FlagStatus QEP_ITStatus(uint32_t ITStatus)
+{
+    assert_param(IS_QEP_IT_STATUS(ITStatus));
+
+    return (FlagStatus)READ_BIT(QEP->QFLG, ITStatus);
+}
+
+/**
+  * @brief   Чтение сохраненного статуса прерывания (сохранение каждый раз при чтении счетчика позиции)
+  * @param   ITStatus  Выбор флага прерывания.
+  *                    Параметр принимает любою совокупность значений QEP_ITStatus_x из @ref QEP_ITStatus_define.
+  * @retval  Status  Статус прерывания. Если выбрано несколько прерываний,
+  *                  то результат соответсвует логическому ИЛИ их состояний.
+  */
+__STATIC_INLINE FlagStatus QEP_ITStatusLatch(uint32_t ITStatus)
+{
+    assert_param(IS_QEP_IT_STATUS(ITStatus));
+
+    return (FlagStatus)READ_BIT(QEP->QFLG, ITStatus << QEP_QFLG_QFLGLAT_Pos);
+}
+
+/**
+  * @brief   Сброс статуса прерывания
+  * @param   ITStatus  Выбор флага прерывания.
+  *                    Параметр принимает любою совокупность значений QEP_ITStatus_x из @ref QEP_ITStatus_define.
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_ITStatusClear(uint32_t ITStatus)
+{
+    assert_param(IS_QEP_IT_STATUS(ITStatus));
+
+    WRITE_REG(QEP->QCLR, ITStatus);
+}
+
+/**
+  * @brief   Чтение активного статуса прерывания
+  * @retval  Status  Статус прерывания
+  */
+__STATIC_INLINE FlagStatus QEP_ITPendStatus(void)
+{
+    return (FlagStatus)READ_BIT(QEP->INTCLR, QEP_INTCLR_INT_Msk);
+}
+
+/**
+  * @brief   Сброс активности прерывания
+  * @retval  void
+  */
+__STATIC_INLINE void QEP_ITPendStatusClear(void)
+{
+    WRITE_REG(QEP->INTCLR, QEP_INTCLR_INT_Msk);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PLIB035_QEP_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2018 NIIET *****END OF FILE****/

platform/plib035/inc/plib035_rcu.h

@@ -0,0 +1,955 @@
+/**
+  ******************************************************************************
+  * @file    plib035_rcu.h
+  *
+  * @brief   Файл содержит прототипы и компактные inline реализации функций для
+  *          RCU (Reset & Clock control Unit), а также сопутствующие
+  *          макроопределения и перечисления
+  *
+  * @author  НИИЭТ, Богдан Колбов <kolbov@niiet.ru>
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ ПРЕДОСТАВЛЯЕТСЯ «КАК ЕСТЬ», БЕЗ КАКИХ-ЛИБО
+  * ГАРАНТИЙ, ЯВНО ВЫРАЖЕННЫХ ИЛИ ПОДРАЗУМЕВАЕМЫХ, ВКЛЮЧАЯ ГАРАНТИИ ТОВАРНОЙ
+  * ПРИГОДНОСТИ, СООТВЕТСТВИЯ ПО ЕГО КОНКРЕТНОМУ НАЗНАЧЕНИЮ И ОТСУТСТВИЯ
+  * НАРУШЕНИЙ, НО НЕ ОГРАНИЧИВАЯСЬ ИМИ. ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ
+  * ПРЕДНАЗНАЧЕНО ДЛЯ ОЗНАКОМИТЕЛЬНЫХ ЦЕЛЕЙ И НАПРАВЛЕНО ТОЛЬКО НА
+  * ПРЕДОСТАВЛЕНИЕ ДОПОЛНИТЕЛЬНОЙ ИНФОРМАЦИИ О ПРОДУКТЕ, С ЦЕЛЬЮ СОХРАНИТЬ ВРЕМЯ
+  * ПОТРЕБИТЕЛЮ. НИ В КАКОМ СЛУЧАЕ АВТОРЫ ИЛИ ПРАВООБЛАДАТЕЛИ НЕ НЕСУТ
+  * ОТВЕТСТВЕННОСТИ ПО КАКИМ-ЛИБО ИСКАМ, ЗА ПРЯМОЙ ИЛИ КОСВЕННЫЙ УЩЕРБ, ИЛИ
+  * ПО ИНЫМ ТРЕБОВАНИЯМ, ВОЗНИКШИМ ИЗ-ЗА ИСПОЛЬЗОВАНИЯ ПРОГРАММНОГО ОБЕСПЕЧЕНИЯ
+  * ИЛИ ИНЫХ ДЕЙСТВИЙ С ПРОГРАММНЫМ ОБЕСПЕЧЕНИЕМ.
+  *
+  * <h2><center>&copy; 2018 ОАО "НИИЭТ"</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PLIB035_RCU_H
+#define __PLIB035_RCU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "plib035.h"
+
+/** @addtogroup Peripheral
+  * @{
+  */
+
+/** @defgroup RCU
+  * @brief Драйвер для работы с тактированием и сбросом периферийных блоков
+  * @{
+  */
+
+/** @defgroup RCU_Exported_Defines Константы
+  * @{
+  */
+
+/** @defgroup RCU_ClkStatus_Define Cтатусы источников тактового сигнала
+  * @{
+  */
+
+#define RCU_ClkStatus_SysClkFail RCU_SYSCLKSTAT_SYSFAIL_Msk          /*!< Ошибка текущей системной частоты */
+#define RCU_ClkStatus_OSEClkFail RCU_SYSCLKSTAT_OSECLKERR_Msk       /*!< Ошибка сигнала внешнего осциллятора */
+#define RCU_ClkStatus_PLLClkFail RCU_SYSCLKSTAT_PLLCLKERR_Msk       /*!< Ошибка сигнала с PLL */
+#define RCU_ClkStatus_PLLDivClkFail RCU_SYSCLKSTAT_PLLDIVCLKERR_Msk /*!< Ошибка сигнала с деленного выхода PLL */
+#define RCU_ClkStatus_OSEClkGood RCU_SYSCLKSTAT_OSECLKOK_Msk       /*!< Нормальная работа сигнала внешнего осциллятора */
+#define RCU_ClkStatus_PLLClkGood RCU_SYSCLKSTAT_PLLCLKOK_Msk       /*!< Нормальная работа сигнала с PLL */
+#define RCU_ClkStatus_PLLDivClkGood RCU_SYSCLKSTAT_PLLDIVCLKOK_Msk /*!< Нормальная работа сигнала с деленного выхода PLL */
+
+#define IS_RCU_CLK_STATUS(VALUE) (((VALUE) == RCU_ClkStatus_SysClkFail) ||    \
+                                  ((VALUE) == RCU_ClkStatus_OSEClkFail) ||    \
+                                  ((VALUE) == RCU_ClkStatus_PLLClkFail) ||    \
+                                  ((VALUE) == RCU_ClkStatus_PLLDivClkFail) || \
+                                  ((VALUE) == RCU_ClkStatus_OSEClkGood) ||    \
+                                  ((VALUE) == RCU_ClkStatus_PLLClkGood) ||    \
+                                  ((VALUE) == RCU_ClkStatus_PLLDivClkGood))
+/**
+  * @}
+  */
+
+/** @defgroup RCU_RstStatus_Define Источник, вызвавший последний сброс системы
+  * @{
+  */
+
+#define RCU_RstStatus_POR RCU_SYSRSTSTAT_POR_Msk       /*!< Сброс от блока POR */
+#define RCU_RstStatus_WDT RCU_SYSRSTSTAT_WDOG_Msk      /*!< Сброс от сторожевого таймера */
+#define RCU_RstStatus_Sys RCU_SYSRSTSTAT_SYSRST_Msk    /*!< Системный сброс */
+#define RCU_RstStatus_LockUp RCU_SYSRSTSTAT_LOCKUP_Msk /*!< Сброс по состоянию LockUp ядра */
+
+#define IS_RCU_RST_STATUS(VALUE) (((VALUE) == RCU_RstStatus_POR) || \
+                                  ((VALUE) == RCU_RstStatus_WDT) || \
+                                  ((VALUE) == RCU_RstStatus_Sys) || \
+                                  ((VALUE) == RCU_RstStatus_LockUp))
+/**
+  * @}
+  */
+
+/** @defgroup RCU_ITSource_Define Источники прерываний
+  * @{
+  */
+
+#define RCU_ITSource_OSEClkFail RCU_INTEN_OSECLKERR_Msk       /*!< Произошла ошибка сигнала внешнего осциллятора */
+#define RCU_ITSource_PLLClkFail RCU_INTEN_PLLCLKERR_Msk       /*!< Произошла ошибка сигнала с PLL */
+#define RCU_ITSource_PLLDivClkFail RCU_INTEN_PLLDIVCLKERR_Msk /*!< Произошла ошибка сигнала с деленного выхода PLL */
+#define RCU_ITSource_OSEClkGood RCU_INTEN_OSECLKOK_Msk        /*!< Произошел переход к нормальной работе сигнала внешнего осциллятора */
+#define RCU_ITSource_PLLClkGood RCU_INTEN_PLLCLKOK_Msk        /*!< Произошел переход к нормальной работе сигнала с PLL */
+#define RCU_ITSource_PLLDivClkGood RCU_INTEN_PLLDIVCLKOK_Msk  /*!< Произошел переход к нормальной работе сигнала с деленного выхода PLL */
+#define RCU_ITSource_PLLLock RCU_INTEN_PLLLOCK_Msk            /*!< Произошел захват частоты PLL */
+
+#define IS_RCU_IT_SOURCE(VALUE) (((VALUE) == RCU_ITSource_OSEClkFail) ||    \
+                                 ((VALUE) == RCU_ITSource_PLLClkFail) ||    \
+                                 ((VALUE) == RCU_ITSource_PLLDivClkFail) || \
+                                 ((VALUE) == RCU_ITSource_OSEClkGood) ||    \
+                                 ((VALUE) == RCU_ITSource_PLLClkGood) ||    \
+                                 ((VALUE) == RCU_ITSource_PLLDivClkGood) || \
+                                 ((VALUE) == RCU_ITSource_PLLLock))
+
+/**
+  * @}
+  */
+
+/** @defgroup RCU_ITStatus_Define Статусы прерываний
+  * @{
+  */
+
+#define RCU_ITStatus_OSEClkFail RCU_INTSTAT_OSECLKERR_Msk       /*!< Флаг ошибки сигнала внешнего осциллятора */
+#define RCU_ITStatus_PLLClkFail RCU_INTSTAT_PLLCLKERR_Msk       /*!< Флаг ошибки сигнала с PLL */
+#define RCU_ITStatus_PLLDivClkFail RCU_INTSTAT_PLLDIVCLKERR_Msk /*!< Флаг ошибки сигнала с деленного выхода PLL */
+#define RCU_ITStatus_OSEClkGood RCU_INTSTAT_OSECLKOK_Msk       /*!< Флаг перехода к нормальной работе сигнала внешнего осциллятора */
+#define RCU_ITStatus_PLLClkGood RCU_INTSTAT_PLLCLKOK_Msk       /*!< Флаг перехода к нормальной работе сигнала с PLL */
+#define RCU_ITStatus_PLLDivClkGood RCU_INTSTAT_PLLDIVCLKOK_Msk /*!< Флаг перехода к нормальной работе сигнала с деленного выхода PLL */
+#define RCU_ITStatus_PLLLock RCU_INTSTAT_PLLLOCK_Msk             /*!< Флаг захвата частоты PLL */
+#define RCU_ITStatus_SysFail RCU_INTSTAT_SYSFAIL_Msk             /*!< Флаг сбоя системной частоты */
+
+#define IS_RCU_IT_STATUS(VALUE) (((VALUE) == RCU_ITStatus_OSEClkFail) ||    \
+                                 ((VALUE) == RCU_ITStatus_PLLClkFail) ||    \
+                                 ((VALUE) == RCU_ITStatus_PLLDivClkFail) || \
+                                 ((VALUE) == RCU_ITStatus_OSEClkGood) ||    \
+                                 ((VALUE) == RCU_ITStatus_PLLClkGood) ||    \
+                                 ((VALUE) == RCU_ITStatus_PLLDivClkGood) || \
+                                 ((VALUE) == RCU_ITStatus_PLLLock) ||       \
+                                 ((VALUE) == RCU_ITStatus_SysFail))
+
+/**
+  * @}
+  */
+
+/** @defgroup RCU_APBClk_Define Управление тактированием периферийных блоков APB
+  * @{
+  */
+
+#define RCU_APBClk_TMR0 RCU_PCLKCFG_TMR0EN_Msk   /*!< Управление тактированием блока TMR 0 */
+#define RCU_APBClk_TMR1 RCU_PCLKCFG_TMR1EN_Msk   /*!< Управление тактированием блока TMR 1 */
+#define RCU_APBClk_TMR2 RCU_PCLKCFG_TMR2EN_Msk   /*!< Управление тактированием блока TMR 2 */
+#define RCU_APBClk_TMR3 RCU_PCLKCFG_TMR3EN_Msk   /*!< Управление тактированием блока TMR 3 */
+#define RCU_APBClk_PWM0 RCU_PCLKCFG_PWM0EN_Msk   /*!< Управление тактированием блока PWM 0 */
+#define RCU_APBClk_PWM1 RCU_PCLKCFG_PWM1EN_Msk   /*!< Управление тактированием блока PWM 1 */
+#define RCU_APBClk_PWM2 RCU_PCLKCFG_PWM2EN_Msk   /*!< Управление тактированием блока PWM 2 */
+#define RCU_APBClk_I2C RCU_PCLKCFG_I2CEN_Msk     /*!< Управление тактированием блока I2C */
+#define RCU_APBClk_QEP RCU_PCLKCFG_QEPEN_Msk     /*!< Управление тактированием блока QEP */
+#define RCU_APBClk_ECAP0 RCU_PCLKCFG_ECAP0EN_Msk /*!< Управление тактированием блока ECAP 0 */
+#define RCU_APBClk_ECAP1 RCU_PCLKCFG_ECAP1EN_Msk /*!< Управление тактированием блока ECAP 1 */
+#define RCU_APBClk_ECAP2 RCU_PCLKCFG_ECAP2EN_Msk /*!< Управление тактированием блока ECAP 2 */
+
+#define IS_RCU_APB_CLK(VALUE) (((VALUE) == RCU_APBClk_TMR0) ||  \
+                               ((VALUE) == RCU_APBClk_TMR1) ||  \
+                               ((VALUE) == RCU_APBClk_TMR2) ||  \
+                               ((VALUE) == RCU_APBClk_TMR3) ||  \
+                               ((VALUE) == RCU_APBClk_PWM0) ||  \
+                               ((VALUE) == RCU_APBClk_PWM1) ||  \
+                               ((VALUE) == RCU_APBClk_PWM2) ||  \
+                               ((VALUE) == RCU_APBClk_I2C) ||   \
+                               ((VALUE) == RCU_APBClk_QEP) ||   \
+                               ((VALUE) == RCU_APBClk_ECAP0) || \
+                               ((VALUE) == RCU_APBClk_ECAP1) || \
+                               ((VALUE) == RCU_APBClk_ECAP2))
+
+/**
+  * @}
+  */
+
+/** @defgroup RCU_AHBClk_Define Управление тактированием периферийных блоков AHB
+  * @{
+  */
+
+#define RCU_AHBClk_GPIOA RCU_HCLKCFG_GPIOAEN_Msk /*!< Управление тактированием блока GPIOA */
+#define RCU_AHBClk_GPIOB RCU_HCLKCFG_GPIOBEN_Msk /*!< Управление тактированием блока GPIOB */
+#define RCU_AHBClk_CAN RCU_HCLKCFG_CANEN_Msk     /*!< Управление тактированием блока CAN */
+#define IS_RCU_AHB_CLK(VALUE) (((VALUE) == RCU_AHBClk_GPIOA) || \
+                               ((VALUE) == RCU_AHBClk_GPIOB) || \
+                               ((VALUE) == RCU_AHBClk_CAN))
+
+/**
+  * @}
+  */
+
+/** @defgroup RCU_APBRst_Define Управление сбросом периферийных блоков APB
+  * @{
+  */
+
+#define RCU_APBRst_TMR0 RCU_PRSTCFG_TMR0EN_Msk   /*!< Управление сбросом блока TMR 0 */
+#define RCU_APBRst_TMR1 RCU_PRSTCFG_TMR1EN_Msk   /*!< Управление сбросом блока TMR 1 */
+#define RCU_APBRst_TMR2 RCU_PRSTCFG_TMR2EN_Msk   /*!< Управление сбросом блока TMR 2 */
+#define RCU_APBRst_TMR3 RCU_PRSTCFG_TMR3EN_Msk   /*!< Управление сбросом блока TMR 3 */
+#define RCU_APBRst_PWM0 RCU_PRSTCFG_PWM0EN_Msk   /*!< Управление сбросом блока PWM 0 */
+#define RCU_APBRst_PWM1 RCU_PRSTCFG_PWM1EN_Msk   /*!< Управление сбросом блока PWM 1 */
+#define RCU_APBRst_PWM2 RCU_PRSTCFG_PWM2EN_Msk   /*!< Управление сбросом блока PWM 2 */
+#define RCU_APBRst_I2C RCU_PRSTCFG_I2CEN_Msk     /*!< Управление сбросом блока I2C */
+#define RCU_APBRst_QEP RCU_PRSTCFG_QEPEN_Msk     /*!< Управление сбросом блока QEP */
+#define RCU_APBRst_ECAP0 RCU_PRSTCFG_ECAP0EN_Msk /*!< Управление сбросом блока ECAP 0 */
+#define RCU_APBRst_ECAP1 RCU_PRSTCFG_ECAP1EN_Msk /*!< Управление сбросом блока ECAP 1 */
+#define RCU_APBRst_ECAP2 RCU_PRSTCFG_ECAP2EN_Msk /*!< Управление сбросом блока ECAP 2 */
+
+#define IS_RCU_APB_RST(VALUE) (((VALUE) == RCU_APBRst_TMR0) ||  \
+                               ((VALUE) == RCU_APBRst_TMR1) ||  \
+                               ((VALUE) == RCU_APBRst_TMR2) ||  \
+                               ((VALUE) == RCU_APBRst_TMR3) ||  \
+                               ((VALUE) == RCU_APBRst_PWM0) ||  \
+                               ((VALUE) == RCU_APBRst_PWM1) ||  \
+                               ((VALUE) == RCU_APBRst_PWM2) ||  \
+                               ((VALUE) == RCU_APBRst_I2C) ||   \
+                               ((VALUE) == RCU_APBRst_QEP) ||   \
+                               ((VALUE) == RCU_APBRst_ECAP0) || \
+                               ((VALUE) == RCU_APBRst_ECAP1) || \
+                               ((VALUE) == RCU_APBRst_ECAP2))
+
+/**
+  * @}
+  */
+
+/** @defgroup RCU_AHBRst_Define Управление сбросом периферийных блоков AHB
+  * @{
+  */
+
+#define RCU_AHBRst_GPIOA RCU_HRSTCFG_GPIOAEN_Msk /*!< Управление сбросом блока GPIOA */
+#define RCU_AHBRst_GPIOB RCU_HRSTCFG_GPIOBEN_Msk /*!< Управление сбросом блока GPIOB */
+#define RCU_AHBRst_CAN RCU_HRSTCFG_CANEN_Msk     /*!< Управление сбросом блока CAN */
+
+#define IS_RCU_AHB_RST(VALUE) (((VALUE) == RCU_AHBRst_GPIOA) || \
+                               ((VALUE) == RCU_AHBRst_GPIOB) || \
+                               ((VALUE) == RCU_AHBRst_CAN))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCU_Exported_Types Типы
+  * @{
+  */
+
+/**
+  * @brief  Выбор источника опорного сигнала PLL.
+  */
+typedef enum {
+    RCU_PLL_Ref_OSEClk = RCU_PLLCFG_REFSRC_OSECLK, /*!< Сигнал внешнего осциллятора */
+    RCU_PLL_Ref_OSIClk = RCU_PLLCFG_REFSRC_OSICLK  /*!< Сигнал внтуреннего осциллятора */
+} RCU_PLL_Ref_TypeDef;
+#define IS_RCU_PLL_REF(VALUE) (((VALUE) == RCU_PLL_Ref_OSEClk) || \
+                               ((VALUE) == RCU_PLL_Ref_OSIClk))
+
+/**
+  * @brief  Выходной делитель OD
+  */
+typedef enum {
+    RCU_PLL_OD_Disable = RCU_PLLCFG_OD_Disable, /*!< Делитель OD выключен */
+    RCU_PLL_OD_Div2 = RCU_PLLCFG_OD_Div2,       /*!< Коэффициент деления OD равен 2 */
+    RCU_PLL_OD_Div4 = RCU_PLLCFG_OD_Div4,       /*!< Коэффициент деления OD равен 4 */
+    RCU_PLL_OD_Div8 = RCU_PLLCFG_OD_Div8        /*!< Коэффициент деления OD равен 8 */
+} RCU_PLL_OD_TypeDef;
+#define IS_RCU_PLL_OD(VALUE) (((VALUE) == RCU_PLL_OD_Disable) || \
+                              ((VALUE) == RCU_PLL_OD_Div2) ||    \
+                              ((VALUE) == RCU_PLL_OD_Div4) ||    \
+                              ((VALUE) == RCU_PLL_OD_Div8))
+
+/**
+  * @brief  Выбор источника тактирования для периферийного блока c несколькими тактовыми доменами - ADC, UART, SPI
+  */
+typedef enum {
+    RCU_PeriphClk_OSEClk = RCU_SPICFG_CLKSEL_OSECLK,       /*!< Сигнал внешнего осциллятора */
+    RCU_PeriphClk_PLLClk = RCU_SPICFG_CLKSEL_PLLCLK,       /*!< Сигнал с PLL */
+    RCU_PeriphClk_PLLDivClk = RCU_SPICFG_CLKSEL_PLLDIVCLK, /*!< Сигнал с деленного выхода PLL */
+    RCU_PeriphClk_OSIClk = RCU_SPICFG_CLKSEL_OSICLK        /*!< Сигнал внтуреннего осциллятора */
+} RCU_PeriphClk_TypeDef;
+#define IS_RCU_PERIPH_CLK(VALUE) (((VALUE) == RCU_PeriphClk_OSEClk) ||    \
+                                  ((VALUE) == RCU_PeriphClk_PLLClk) ||    \
+                                  ((VALUE) == RCU_PeriphClk_PLLDivClk) || \
+                                  ((VALUE) == RCU_PeriphClk_OSIClk))
+
+/**
+  * @brief  Выбор источника тактирования для CLKOUT, TRACE, WDT.
+  */
+typedef enum {
+    RCU_SysPeriphClk_OSEClk = RCU_CLKOUTCFG_CLKSEL_OSECLK,       /*!< Сигнал внешнего осциллятора */
+    RCU_SysPeriphClk_PLLClk = RCU_CLKOUTCFG_CLKSEL_PLLCLK,       /*!< Сигнал с PLL */
+    RCU_SysPeriphClk_PLLDivClk = RCU_CLKOUTCFG_CLKSEL_PLLDIVCLK, /*!< Сигнал с деленного выхода PLL */
+    RCU_SysPeriphClk_OSIClk = RCU_CLKOUTCFG_CLKSEL_OSICLK        /*!< Сигнал внтуреннего осциллятора */
+} RCU_SysPeriphClk_TypeDef;
+#define IS_RCU_SYS_PERIPH_CLK(VALUE) (((VALUE) == RCU_SysPeriphClk_OSEClk) ||    \
+                                      ((VALUE) == RCU_SysPeriphClk_PLLClk) ||    \
+                                      ((VALUE) == RCU_SysPeriphClk_PLLDivClk) || \
+                                      ((VALUE) == RCU_SysPeriphClk_OSIClk))
+
+/**
+  * @brief  Выбор источника системной частоты.
+  */
+typedef enum {
+    RCU_SysClk_OSIClk = RCU_SYSCLKCFG_SYSSEL_OSICLK,      /*!< Сигнал внтуреннего осциллятора */
+    RCU_SysClk_OSEClk = RCU_SYSCLKCFG_SYSSEL_OSECLK,      /*!< Сигнал внешнего осциллятора */
+    RCU_SysClk_PLLClk = RCU_SYSCLKCFG_SYSSEL_PLLCLK,      /*!< Сигнал с PLL */
+    RCU_SysClk_PLLDivClk = RCU_SYSCLKCFG_SYSSEL_PLLDIVCLK /*!< Сигнал с деленного выхода PLL */
+} RCU_SysClk_TypeDef;
+#define IS_RCU_SYS_CLK(VALUE) (((VALUE) == RCU_SysClk_OSIClk) || \
+                               ((VALUE) == RCU_SysClk_OSEClk) || \
+                               ((VALUE) == RCU_SysClk_PLLClk) || \
+                               ((VALUE) == RCU_SysClk_PLLDivClk))
+
+/**
+  * @brief  Структура инициализации PLL
+  *
+  */
+typedef struct
+{
+    uint32_t DivVal;         /*!< Значение делителя сигнала на выходе блока PLL (итоговое значение 2*(Div+1)).
+                                   Параметр может принимать любое значение из диапазона 0-63. */
+    FunctionalState DivEn;   /*!< Активация делителя PLL*/
+    RCU_PLL_Ref_TypeDef Ref; /*!< Источник опорного сигнала PLL */
+    RCU_PLL_OD_TypeDef OD;   /*!< Выходной делитель OD */
+    uint32_t M;              /*!< Множитель M.
+                                   Параметр может принимать любое значение из диапазона 2-63. */
+    uint32_t N;              /*!< Делитель N.
+                                   Параметр может принимать любое значение из диапазона 1-63. */
+} RCU_PLL_Init_TypeDef;
+#define IS_RCU_PLL_DIV(VALUE) (((VALUE)&0xFFFFFFC0) == 0)
+#define IS_RCU_PLL_M(VALUE) (((VALUE) <= 63) && ((VALUE) >= 2))
+#define IS_RCU_PLL_N(VALUE) (((VALUE) <= 63) && ((VALUE) >= 1))
+#define IS_RCU_PLL_REF_FREQ(VALUE) (((VALUE) <= 64000000) && ((VALUE) >= 4000000))
+#define IS_RCU_PLL_CMP_FREQ(VALUE) (((VALUE) <= 20000000) && ((VALUE) >= 4000000))
+#define IS_RCU_PLL_VCO_FREQ(VALUE) (((VALUE) <= 200000000) && ((VALUE) >= 120000000))
+
+#define IS_RCU_SYSCLK_FREQ(VALUE) (((VALUE) <= 100000000) && ((VALUE) >= 1000000))
+#define IS_RCU_SECPRD(VALUE) (((VALUE)&0xFFFFFF00) == 0)
+#define IS_RCU_OSI_CALIB(VALUE) (((VALUE)&0xFFFFFC00) == 0)
+#define IS_RCU_PERIPH_DIV(VALUE) (((VALUE)&0xFFFFFFC0) == 0)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCU_Exported_Functions Функции
+  * @{
+  */
+
+/**
+  * @brief   Включение тактирования выбранного APB блока периферии
+  * @param   APBClk  Выбор периферии. Любая совокупность значений значений RCU_APBClk_x (@ref RCU_APBClk_Define).
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_APBClkCmd(uint32_t APBClk, FunctionalState State)
+{
+    assert_param(IS_RCU_APB_CLK(APBClk));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    MODIFY_REG(RCU->PCLKCFG, APBClk, State ? APBClk : 0);
+}
+
+/**
+  * @brief   Включение тактирования выбранного AHB блока периферии
+  * @param   AHBClk  Выбор периферии. Любая совокупность значений значений RCU_AHBClk_x (@ref RCU_AHBClk_Define).
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_AHBClkCmd(uint32_t AHBClk, FunctionalState State)
+{
+    assert_param(IS_RCU_AHB_CLK(AHBClk));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    MODIFY_REG(RCU->HCLKCFG, AHBClk, State ? AHBClk : 0);
+}
+
+/**
+  * @brief   Вывод из состояния сброса периферийных блоков APB
+  * @param   APBRst  Выбор периферийного модуля. Любая совокупность значений значений RCU_APBRst_x (@ref RCU_APBRst_Define).
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_APBRstCmd(uint32_t APBRst, FunctionalState State)
+{
+    assert_param(IS_RCU_APB_RST(APBRst));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    MODIFY_REG(RCU->PRSTCFG, APBRst, State ? APBRst : 0);
+}
+
+/**
+  * @brief   Вывод из состояния сброса периферийных блоков APB
+  * @param   AHBRst  Выбор периферийного модуля. Любая совокупность значений значений RCU_AHBRst_x (@ref RCU_AHBRst_Define).
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_AHBRstCmd(uint32_t AHBRst, FunctionalState State)
+{
+    assert_param(IS_RCU_AHB_RST(AHBRst));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    MODIFY_REG(RCU->HRSTCFG, AHBRst, State ? AHBRst : 0);
+}
+
+/**
+  * @brief   Установка опорного тактового сигнала для системной частоты
+  * @param   SysClk  Выбор тактового сигнала
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_SysClkConfig(RCU_SysClk_TypeDef SysClk)
+{
+    assert_param(IS_RCU_SYS_CLK(SysClk));
+
+    WRITE_REG(RCU->SYSCLKCFG_bit.SYSSEL, SysClk);
+}
+
+/**
+  * @brief   Получение текущего опорного тактового сигнала для системной частоты
+  * @retval  Val  Выбранный сигнал
+  */
+__STATIC_INLINE RCU_SysClk_TypeDef RCU_SysClkStatus(void)
+{
+    return (RCU_SysClk_TypeDef)READ_REG(RCU->SYSCLKSTAT_bit.SYSSTAT);
+}
+
+/**
+  * @brief   Получение статуса занятости менеджера тактовых сигналов
+  * @retval  Status  Статус
+  */
+__STATIC_INLINE FlagStatus RCU_BusyStatus(void)
+{
+    return (FlagStatus)READ_BIT(RCU->SYSCLKSTAT, RCU_SYSCLKSTAT_BUSY_Msk);
+}
+
+/**
+  * @brief   Получение статуса выбранного тактового сигнала
+  * @param   ClkStatus  Выбор тактового сигнала. Любая совокупность значений значений RCU_ClkStatus_x (@ref RCU_ClkStatus_Define).
+  * @retval  Status  Статус
+  */
+__STATIC_INLINE FlagStatus RCU_ClkStatus(uint32_t ClkStatus)
+{
+    return (FlagStatus)READ_BIT(RCU->SYSCLKSTAT, ClkStatus);
+}
+
+uint32_t RCU_GetOSIClkFreq(void);
+uint32_t RCU_GetOSEClkFreq(void);
+uint32_t RCU_GetPLLClkFreq(void);
+uint32_t RCU_GetPLLDivClkFreq(void);
+uint32_t RCU_GetSysClkFreq(void);
+
+/**
+  * @brief   Включение системы слежения за системным тактовым сигналом
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_SecurityCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(RCU->SYSCLKCFG_bit.SECEN, State);
+}
+
+/**
+  * @brief   Настройка периода срабатывания системы слежения
+  * @param   OSEPrd  Максимальное значение счетчика слежения за сигналом OSECLK
+  * @param   PLLPrd  Максимальное значение счетчика слежения за сигналом PLLCLK
+  * @param   PLLDivPrd  Максимальное значение счетчика слежения за сигналом PLLDIVCLK
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_SecurityConfig(uint32_t OSEPrd, uint32_t PLLPrd, uint32_t PLLDivPrd)
+{
+    assert_param(IS_RCU_SECPRD(OSEPrd));
+    assert_param(IS_RCU_SECPRD(PLLPrd));
+    assert_param(IS_RCU_SECPRD(PLLDivPrd));
+
+    MODIFY_REG(RCU->SECPRD, (RCU_SECPRD_OSECLK_Msk | RCU_SECPRD_PLLCLK_Msk | RCU_SECPRD_PLLDIVCLK_Msk),
+               ((OSEPrd << RCU_SECPRD_OSECLK_Pos) | (PLLPrd << RCU_SECPRD_PLLCLK_Pos) | (PLLDivPrd << RCU_SECPRD_PLLDIVCLK_Pos)));
+}
+
+/**
+  * @brief   Получение статуса выбранного типа сброса
+  * @param   RstStatus  Выбранный тип сброса. Любая совокупность значений значений RCU_RstStatus_x (@ref RCU_RstStatus_Define).
+  * @retval  Status  Статус активности
+  */
+__STATIC_INLINE FlagStatus RCU_RstStatus(uint32_t RstStatus)
+{
+    return (FlagStatus)READ_BIT(RCU->SYSRSTSTAT, RstStatus);
+}
+
+/**
+  * @brief   Очистка статуса выбранного типа сброса
+  * @param   RstStatus  Выбранный тип сброса. Любая совокупность значений значений RCU_RstStatus_x (@ref RCU_RstStatus_Define).
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_RstStatusClear(uint32_t RstStatus)
+{
+    assert_param(IS_RCU_RST_STATUS(RstStatus));
+
+    WRITE_REG(RCU->SYSRSTSTAT, RstStatus);
+}
+
+/**
+  * @brief   Включение сброса ядра по переходу в состояние LockUp
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_LockUpRstCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(RCU->SYSRSTCFG_bit.LOCKUPEN, State);
+}
+
+/**
+  * @brief   Установка калибровочного значения для внутреннего осциллятора
+  * @param   CalibVal  Значение калибровки
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_OSIConfig(uint32_t CalibVal)
+{
+    assert_param(IS_RCU_OSI_CALIB(CalibVal));
+
+    WRITE_REG(RCU->OSICFG_bit.CAL, CalibVal);
+}
+
+/**
+  * @brief   Разрешение работы внешнего осциллятора
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_OSECmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    MODIFY_REG(RCU->OSECFG, (RCU_OSECFG_EN_Msk | RCU_OSECFG_XOEN_Msk),
+               ((State << RCU_OSECFG_EN_Pos) | (State << RCU_OSECFG_XOEN_Pos)));
+}
+
+OperationStatus RCU_SysClkChangeCmd(RCU_SysClk_TypeDef SysClk);
+
+/** @defgroup RCU_Init_Deinit Конфигурация PLL
+  * @{
+  */
+
+OperationStatus RCU_PLL_AutoConfig(uint32_t SysClkFreq, RCU_PLL_Ref_TypeDef Ref);
+OperationStatus RCU_PLL_Init(RCU_PLL_Init_TypeDef* InitStruct);
+void RCU_PLL_DeInit(void);
+void RCU_PLL_StructInit(RCU_PLL_Init_TypeDef* InitStruct);
+
+/**
+  * @brief   Разрешение работы выхода PLL
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_PLL_OutCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(RCU->PLLCFG_bit.OUTEN, State);
+}
+
+/**
+  * @brief   Включение режима bypass PLL
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_PLL_BypassCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(RCU->PLLCFG_bit.BYPASS, State);
+}
+
+/**
+  * @brief   Настройка внешнего делителя PLL
+  * @param   Val  Выбор значения делителя. Тактовый сигнал делится на Val+1.
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_PLL_DivConfig(uint32_t Val, FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+    assert_param(IS_RCU_PLL_DIV(Val));
+
+    MODIFY_REG(RCU->PLLDIV, RCU_PLLDIV_DIV_Msk | RCU_PLLDIV_DIVEN_Msk,
+               (Val << RCU_PLLDIV_DIV_Pos |
+                State << RCU_PLLDIV_DIVEN_Pos));
+}
+
+/**
+  * @brief   Получение статуса захвата частоты PLL
+  * @retval  Status  Статус захвата
+  */
+__STATIC_INLINE FlagStatus RCU_PLL_LockStatus(void)
+{
+    return (FlagStatus)READ_BIT(RCU->PLLCFG, RCU_PLLCFG_LOCK_Msk);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCU_CLK_Config_ClkOut Настройка выдачи тактового сигнала CLKOUT
+  * @{
+  */
+
+uint32_t RCU_GetClkOutFreq(void);
+
+/**
+  * @brief   Настройка тактирования ClkOut
+  * @param   ClkOut  Источник тактового сигнала
+  * @param   DivVal  Значение делителя (деление на 2*(DivVal+1))
+  * @param   DivState  Разрешение работы делителя
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_ClkOutConfig(RCU_SysPeriphClk_TypeDef ClkOut, uint32_t DivVal, FunctionalState DivState)
+{
+    assert_param(IS_RCU_SYS_PERIPH_CLK(ClkOut));
+    assert_param(IS_RCU_PERIPH_DIV(DivVal));
+    assert_param(IS_FUNCTIONAL_STATE(DivState));
+
+    MODIFY_REG(RCU->CLKOUTCFG, (RCU_CLKOUTCFG_CLKSEL_Msk | RCU_CLKOUTCFG_DIVN_Msk | RCU_CLKOUTCFG_DIVEN_Msk),
+               ((ClkOut << RCU_CLKOUTCFG_CLKSEL_Pos) | (DivVal << RCU_CLKOUTCFG_DIVN_Pos) | (DivState << RCU_CLKOUTCFG_DIVEN_Pos)));
+}
+
+/**
+  * @brief   Включение тактирования ClkOut
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_ClkOutCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(RCU->CLKOUTCFG_bit.CLKEN, State);
+    WRITE_REG(SIU->CLKOUTCTL_bit.CLKOUTEN, State);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCU_CLK_Config_Trace Тактирование модуля трассировки
+  * @{
+  */
+
+uint32_t RCU_GetTraceClkFreq(void);
+
+/**
+  * @brief   Настройка тактирования блока трассировки
+  * @param   TraceClk  Источник тактового сигнала
+  * @param   DivVal  Значение делителя (деление на 2*(DivVal+1))
+  * @param   DivState  Разрешение работы делителя
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_TraceClkConfig(RCU_SysPeriphClk_TypeDef TraceClk, uint32_t DivVal, FunctionalState DivState)
+{
+    assert_param(IS_RCU_SYS_PERIPH_CLK(TraceClk));
+    assert_param(IS_RCU_PERIPH_DIV(DivVal));
+    assert_param(IS_FUNCTIONAL_STATE(DivState));
+
+    MODIFY_REG(RCU->TRACECFG, (RCU_TRACECFG_CLKSEL_Msk | RCU_TRACECFG_DIVN_Msk | RCU_TRACECFG_DIVEN_Msk),
+               ((TraceClk << RCU_TRACECFG_CLKSEL_Pos) | (DivVal << RCU_TRACECFG_DIVN_Pos) | (DivState << RCU_TRACECFG_DIVEN_Pos)));
+}
+
+/**
+  * @brief   Включение тактирования трассировки
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_TraceClkCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(RCU->TRACECFG_bit.CLKEN, State);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCU_CLK_RST_Config_UART Тактирование и сброс UART
+  * @{
+  */
+
+uint32_t RCU_GetUARTClkFreq(UART_Num_TypeDef UARTx_Num);
+
+/**
+  * @brief   Настройка тактирования UART
+  * @param   UARTx_Num  Порядковый номер блока UART
+  * @param   UARTClk  Источник тактового сигнала
+  * @param   DivVal  Значение делителя (деление на 2*(DivVal+1))
+  * @param   DivState  Разрешение работы делителя
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_UARTClkConfig(UART_Num_TypeDef UARTx_Num, RCU_PeriphClk_TypeDef UARTClk, uint32_t DivVal, FunctionalState DivState)
+{
+    assert_param(IS_RCU_PERIPH_CLK(UARTClk));
+    assert_param(IS_RCU_PERIPH_DIV(DivVal));
+    assert_param(IS_FUNCTIONAL_STATE(DivState));
+
+    MODIFY_REG(RCU->UARTCFG[UARTx_Num].UARTCFG, (RCU_UARTCFG_UARTCFG_CLKSEL_Msk | RCU_UARTCFG_UARTCFG_DIVN_Msk | RCU_UARTCFG_UARTCFG_DIVEN_Msk),
+               ((UARTClk << RCU_UARTCFG_UARTCFG_CLKSEL_Pos) | (DivVal << RCU_UARTCFG_UARTCFG_DIVN_Pos) | (DivState << RCU_UARTCFG_UARTCFG_DIVEN_Pos)));
+}
+
+/**
+  * @brief   Включение тактирования UART
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_UARTClkCmd(UART_Num_TypeDef UARTx_Num, FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(RCU->UARTCFG[UARTx_Num].UARTCFG_bit.CLKEN, State);
+}
+
+/**
+  * @brief   Cнятие сброса UART
+  * @param   UARTx_Num  Порядковый номер блока UART
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_UARTRstCmd(UART_Num_TypeDef UARTx_Num, FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(RCU->UARTCFG[UARTx_Num].UARTCFG_bit.RSTDIS, State);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCU_CLK_RST_Config_SPI Тактирование и сброс SPI
+  * @{
+  */
+
+uint32_t RCU_GetSPIClkFreq(void);
+
+/**
+  * @brief   Настройка тактирования SPI
+  * @param   SPIClk  Источник тактового сигнала
+  * @param   DivVal  Значение делителя (деление на 2*(DivVal+1))
+  * @param   DivState  Разрешение работы делителя
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_SPIClkConfig(RCU_PeriphClk_TypeDef SPIClk, uint32_t DivVal, FunctionalState DivState)
+{
+    assert_param(IS_RCU_PERIPH_CLK(SPIClk));
+    assert_param(IS_RCU_PERIPH_DIV(DivVal));
+    assert_param(IS_FUNCTIONAL_STATE(DivState));
+
+    MODIFY_REG(RCU->SPICFG, (RCU_SPICFG_CLKSEL_Msk | RCU_SPICFG_DIVN_Msk | RCU_SPICFG_DIVEN_Msk),
+               ((SPIClk << RCU_SPICFG_CLKSEL_Pos) | (DivVal << RCU_SPICFG_DIVN_Pos) | (DivState << RCU_SPICFG_DIVEN_Pos)));
+}
+
+/**
+  * @brief   Включение тактирования SPI
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_SPIClkCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(RCU->SPICFG_bit.CLKEN, State);
+}
+
+/**
+  * @brief   Cнятие сброса SPI
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_SPIRstCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(RCU->SPICFG_bit.RSTDIS, State);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCU_CLK_RST_Config_WDT Тактирование и сброс WDT
+  * @{
+  */
+
+uint32_t RCU_GetWDTClkFreq(void);
+
+/**
+  * @brief   Настройка тактирования сторожевого таймера
+  * @param   WDTClk  Источник тактового сигнала
+  * @param   DivVal  Значение делителя (деление на 2*(DivVal+1))
+  * @param   DivState  Разрешение работы делителя
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_WDTClkConfig(RCU_SysPeriphClk_TypeDef WDTClk, uint32_t DivVal, FunctionalState DivState)
+{
+    assert_param(IS_RCU_SYS_PERIPH_CLK(WDTClk));
+    assert_param(IS_RCU_PERIPH_DIV(DivVal));
+    assert_param(IS_FUNCTIONAL_STATE(DivState));
+
+    MODIFY_REG(RCU->WDTCFG, (RCU_WDTCFG_CLKSEL_Msk | RCU_WDTCFG_DIVN_Msk | RCU_WDTCFG_DIVEN_Msk),
+               ((WDTClk << RCU_WDTCFG_CLKSEL_Pos) | (DivVal << RCU_WDTCFG_DIVN_Pos) | (DivState << RCU_WDTCFG_DIVEN_Pos)));
+}
+
+/**
+  * @brief   Включение тактирования сторожевого таймера
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_WDTClkCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(RCU->WDTCFG_bit.CLKEN, State);
+}
+
+/**
+  * @brief   Cнятие сброса сторожевого таймера
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_WDTRstCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(RCU->WDTCFG_bit.RSTDIS, State);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCU_CLK_RST_Config_ADC Тактирование и сброс ADC
+  * @{
+  */
+
+uint32_t RCU_GetADCClkFreq(void);
+
+/**
+  * @brief   Настройка тактирования АЦП
+  * @param   ADCClk  Источник тактового сигнала
+  * @param   DivVal  Значение делителя (деление на 2*(DivVal+1))
+  * @param   DivState  Разрешение работы делителя
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_ADCClkConfig(RCU_PeriphClk_TypeDef ADCClk, uint32_t DivVal, FunctionalState DivState)
+{
+    assert_param(IS_RCU_PERIPH_CLK(ADCClk));
+    assert_param(IS_RCU_PERIPH_DIV(DivVal));
+    assert_param(IS_FUNCTIONAL_STATE(DivState));
+
+    MODIFY_REG(RCU->ADCCFG, (RCU_ADCCFG_CLKSEL_Msk | RCU_ADCCFG_DIVN_Msk | RCU_ADCCFG_DIVEN_Msk),
+               ((ADCClk << RCU_ADCCFG_CLKSEL_Pos) | (DivVal << RCU_ADCCFG_DIVN_Pos) | (DivState << RCU_ADCCFG_DIVEN_Pos)));
+}
+
+/**
+  * @brief   Включение тактирования АЦП
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_ADCClkCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(RCU->ADCCFG_bit.CLKEN, State);
+}
+
+/**
+  * @brief   Cнятие сброса АЦП
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_ADCRstCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(RCU->ADCCFG_bit.RSTDIS, State);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCU_IT Прерывания
+  * @{
+  */
+
+/**
+  * @brief   Разрешение работы прерывания RCU
+  * @param   ITSource  Выбор источника прерывания. Любая совокупность значений значений RCU_ITSource_x (@ref RCU_ITSource_Define).
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_ITCmd(uint32_t ITSource, FunctionalState State)
+{
+    assert_param(IS_RCU_IT_SOURCE(ITSource));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    MODIFY_REG(RCU->INTEN, ITSource, State ? (uint32_t)ITSource : 0);
+}
+
+/**
+  * @brief   Получение статуса выбранного флага прерывания
+  * @param   ITStatus  Выбранный флаг. Любая совокупность значений значений RCU_ITStatus_x (@ref RCU_ITStatus_Define).
+  * @retval  Status  Статус
+  */
+__STATIC_INLINE FlagStatus RCU_ITStatus(uint32_t ITStatus)
+{
+    assert_param(IS_RCU_IT_STATUS(ITStatus));
+
+    return (FlagStatus)READ_BIT(RCU->INTSTAT, ITStatus);
+}
+
+/**
+  * @brief   Сброс статуса выбранного флага прерывания
+  * @param   ITStatus  Выбранный флаг. Любая совокупность значений значений RCU_ITStatus_x (@ref RCU_ITStatus_Define).
+  * @retval  void
+  */
+__STATIC_INLINE void RCU_ITStatusClear(uint32_t ITStatus)
+{
+    assert_param(IS_RCU_IT_STATUS(ITStatus));
+
+    WRITE_REG(RCU->INTSTAT, ITStatus);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PLIB035_RCU_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2018 NIIET *****END OF FILE****/

platform/plib035/inc/plib035_spi.h

@@ -0,0 +1,491 @@
+/**
+  ******************************************************************************
+  * @file    plib035_spi.h
+  *
+  * @brief   Файл содержит прототипы и компактные inline реализации функций для
+  *          SPI, а также сопутствующие макроопределения и перечисления
+  *
+  * @author  НИИЭТ, Богдан Колбов <kolbov@niiet.ru>
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ ПРЕДОСТАВЛЯЕТСЯ «КАК ЕСТЬ», БЕЗ КАКИХ-ЛИБО
+  * ГАРАНТИЙ, ЯВНО ВЫРАЖЕННЫХ ИЛИ ПОДРАЗУМЕВАЕМЫХ, ВКЛЮЧАЯ ГАРАНТИИ ТОВАРНОЙ
+  * ПРИГОДНОСТИ, СООТВЕТСТВИЯ ПО ЕГО КОНКРЕТНОМУ НАЗНАЧЕНИЮ И ОТСУТСТВИЯ
+  * НАРУШЕНИЙ, НО НЕ ОГРАНИЧИВАЯСЬ ИМИ. ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ
+  * ПРЕДНАЗНАЧЕНО ДЛЯ ОЗНАКОМИТЕЛЬНЫХ ЦЕЛЕЙ И НАПРАВЛЕНО ТОЛЬКО НА
+  * ПРЕДОСТАВЛЕНИЕ ДОПОЛНИТЕЛЬНОЙ ИНФОРМАЦИИ О ПРОДУКТЕ, С ЦЕЛЬЮ СОХРАНИТЬ ВРЕМЯ
+  * ПОТРЕБИТЕЛЮ. НИ В КАКОМ СЛУЧАЕ АВТОРЫ ИЛИ ПРАВООБЛАДАТЕЛИ НЕ НЕСУТ
+  * ОТВЕТСТВЕННОСТИ ПО КАКИМ-ЛИБО ИСКАМ, ЗА ПРЯМОЙ ИЛИ КОСВЕННЫЙ УЩЕРБ, ИЛИ
+  * ПО ИНЫМ ТРЕБОВАНИЯМ, ВОЗНИКШИМ ИЗ-ЗА ИСПОЛЬЗОВАНИЯ ПРОГРАММНОГО ОБЕСПЕЧЕНИЯ
+  * ИЛИ ИНЫХ ДЕЙСТВИЙ С ПРОГРАММНЫМ ОБЕСПЕЧЕНИЕМ.
+  *
+  * <h2><center>&copy; 2018 ОАО "НИИЭТ"</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PLIB035_SPI_H
+#define __PLIB035_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "plib035.h"
+
+/** @addtogroup Peripheral
+  * @{
+  */
+
+/** @defgroup SPI
+  * @brief Драйвер для работы с SPI
+  * @{
+  */
+
+/** @defgroup SPI_Exported_Defines Константы
+  * @{
+  */
+
+/** @defgroup SPI_ITSource_Define Источники прерываний SPI
+  * @{
+  */
+
+#define SPI_ITSource_RecieveTimeout SPI_IMSC_RTIM_Msk  /*!< Таймаут приема данных */
+#define SPI_ITSource_RecieveOverrun SPI_IMSC_RORIM_Msk /*!< Переполнение буфера приемника */
+#define SPI_ITSource_RxFIFOLevel SPI_IMSC_RXIM_Msk     /*!< Порог переполнения буфера приемника */
+#define SPI_ITSource_TxFIFOLevel SPI_IMSC_TXIM_Msk     /*!< Порог опустошения буфера передатчика */
+#define SPI_ITSource_All (SPI_IMSC_RTIM_Msk |  \
+                          SPI_IMSC_RORIM_Msk | \
+                          SPI_IMSC_RXIM_Msk |  \
+                          SPI_IMSC_TXIM_Msk) /*!< Все источники выбраны */
+
+#define IS_SPI_IT_SOURCE(VALUE) (((VALUE) & ~SPI_ITSource_All) == 0)
+
+/**
+   * @}
+   */
+
+/** @defgroup SPI_Flag_Define Флаги работы SPI
+  * @{
+  */
+
+#define SPI_Flag_Busy SPI_SR_BSY_Msk           /*!< Флаг занятости блока SPI */
+#define SPI_Flag_RxFIFONotEmpty SPI_SR_RNE_Msk /*!< Флаг наличия данных в буффере приемника данных */
+#define SPI_Flag_RxFIFOFull SPI_SR_RFF_Msk     /*!< Флаг заполнения буффера приемника */
+#define SPI_Flag_TxFIFONotFull SPI_SR_TNF_Msk  /*!< Флаг наличия свободного места в буффере передатчика */
+#define SPI_Flag_TxFIFOEmpty SPI_SR_TFE_Msk    /*!< Флаг пустоты буффера передатчика */
+#define SPI_Flag_All (SPI_SR_BSY_Msk | \
+                      SPI_SR_RNE_Msk | \
+                      SPI_SR_RFF_Msk | \
+                      SPI_SR_TNF_Msk | \
+                      SPI_SR_TFE_Msk) /*!< Все флаги выбраны */
+
+#define IS_SPI_FLAG(VALUE) (((VALUE) & ~SPI_Flag_All) == 0)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Exported_Types Типы
+  * @{
+  */
+
+/**
+  * @brief  Выбор фазы сигнала SCK (только режим SPI)
+  */
+typedef enum {
+    SPI_SCKPhase_CaptureRise, /*!< Захват данных по переднему фронту SCK, установка по заднему */
+    SPI_SCKPhase_CaptureFall  /*!< Захват данных по заднему фронту SCK, установка по переднему */
+} SPI_SCKPhase_TypeDef;
+#define IS_SPI_SCK_PHASE(VALUE) (((VALUE) == SPI_SCKPhase_CaptureRise) || \
+                                 ((VALUE) == SPI_SCKPhase_CaptureFall))
+
+/**
+  * @brief  Выбор полярности сигнала SCK (только режим SPI)
+  */
+typedef enum {
+    SPI_SCKPolarity_SteadyLow, /*!< В режиме ожидания SCK удерживается в состоянии нуля */
+    SPI_SCKPolarity_SteadyHigh /*!< В режиме ожидания SCK удерживается в состоянии единицы */
+} SPI_SCKPolarity_TypeDef;
+#define IS_SPI_SCK_POLARITY(VALUE) (((VALUE) == SPI_SCKPolarity_SteadyLow) || \
+                                    ((VALUE) == SPI_SCKPolarity_SteadyHigh))
+
+/**
+  * @brief  Выбор формата кадра
+  */
+typedef enum {
+    SPI_FrameFormat_SPI = SPI_CR0_FRF_SPI,             /*!< Режим SPI от Motorola */
+    SPI_FrameFormat_SSI = SPI_CR0_FRF_SSI,             /*!< Режим SSI от Texas Instruments */
+    SPI_FrameFormat_Microwire = SPI_CR0_FRF_Microwire, /*!< Режим Microwire от National Semiconductor */
+} SPI_FrameFormat_TypeDef;
+#define IS_SPI_FRAME_FORMAT(VALUE) (((VALUE) == SPI_FrameFormat_SPI) || \
+                                    ((VALUE) == SPI_FrameFormat_SSI) || \
+                                    ((VALUE) == SPI_FrameFormat_Microwire))
+
+/**
+  * @brief  Размер слова данных
+  */
+typedef enum {
+    SPI_DataWidth_4 = SPI_CR0_DSS_4bit,   /*!< Длина информационного слова 4 бит */
+    SPI_DataWidth_5 = SPI_CR0_DSS_5bit,   /*!< Длина информационного слова 5 бит */
+    SPI_DataWidth_6 = SPI_CR0_DSS_6bit,   /*!< Длина информационного слова 6 бит */
+    SPI_DataWidth_7 = SPI_CR0_DSS_7bit,   /*!< Длина информационного слова 7 бит */
+    SPI_DataWidth_8 = SPI_CR0_DSS_8bit,   /*!< Длина информационного слова 8 бит */
+    SPI_DataWidth_9 = SPI_CR0_DSS_9bit,   /*!< Длина информационного слова 9 бит */
+    SPI_DataWidth_10 = SPI_CR0_DSS_10bit, /*!< Длина информационного слова 10 бит */
+    SPI_DataWidth_11 = SPI_CR0_DSS_11bit, /*!< Длина информационного слова 11 бит */
+    SPI_DataWidth_12 = SPI_CR0_DSS_12bit, /*!< Длина информационного слова 12 бит */
+    SPI_DataWidth_13 = SPI_CR0_DSS_13bit, /*!< Длина информационного слова 13 бит */
+    SPI_DataWidth_14 = SPI_CR0_DSS_14bit, /*!< Длина информационного слова 14 бит */
+    SPI_DataWidth_15 = SPI_CR0_DSS_15bit, /*!< Длина информационного слова 15 бит */
+    SPI_DataWidth_16 = SPI_CR0_DSS_16bit, /*!< Длина информационного слова 16 бит */
+} SPI_DataWidth_TypeDef;
+#define IS_SPI_DATA_WIDTH(VALUE) (((VALUE) == SPI_DataWidth_4) ||  \
+                                  ((VALUE) == SPI_DataWidth_5) ||  \
+                                  ((VALUE) == SPI_DataWidth_6) ||  \
+                                  ((VALUE) == SPI_DataWidth_7) ||  \
+                                  ((VALUE) == SPI_DataWidth_8) ||  \
+                                  ((VALUE) == SPI_DataWidth_9) ||  \
+                                  ((VALUE) == SPI_DataWidth_10) || \
+                                  ((VALUE) == SPI_DataWidth_11) || \
+                                  ((VALUE) == SPI_DataWidth_12) || \
+                                  ((VALUE) == SPI_DataWidth_13) || \
+                                  ((VALUE) == SPI_DataWidth_14) || \
+                                  ((VALUE) == SPI_DataWidth_15) || \
+                                  ((VALUE) == SPI_DataWidth_16))
+
+/**
+  * @brief  Выбор режима работы
+  */
+typedef enum {
+    SPI_Mode_Master, /*!< Мастер */
+    SPI_Mode_Slave   /*!< Ведомый */
+} SPI_Mode_TypeDef;
+#define IS_SPI_MODE(VALUE) (((VALUE) == SPI_Mode_Master) || \
+                            ((VALUE) == SPI_Mode_Slave))
+
+/**
+  * @brief  Структура инициализации SPI
+  */
+typedef struct
+{
+    SPI_Mode_TypeDef Mode;               /*!< Выбор режима работы */
+    SPI_FrameFormat_TypeDef FrameFormat; /*!< Выбор формата кадра */
+    SPI_DataWidth_TypeDef DataWidth;     /*!< Количество передаваемых/принимаемых информационных бит */
+    uint32_t SCKDiv;                     /*!< Коэффициент базового деления частоты.
+                                              Параметр может принимать любое значение из диапазона: 0-255. */
+    uint32_t SCKDivExtra;                /*!< Коэффициент дополнительного деления частоты.
+                                              Параметр может принимать любые четные значения из диапазона: 2-254.
+                                              Результирующий коэффциент = SCKDivExtra * (1 + SCKDiv). */
+} SPI_Init_TypeDef;
+
+#define IS_SPI_SCK_DIV(VALUE) (((VALUE) > 0) && ((VALUE) < 0x100))
+#define IS_SPI_SCK_DIV_EXTRA(VALUE) (((VALUE) > 1) && ((VALUE) < 0xFF))
+#define IS_SPI_DATA(VALUE) ((VALUE) < 0x10000)
+#define IS_SPI_FIFO_LEVEL(VALUE) ((VALUE) < 9)
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Exported_Functions Функции
+  * @{
+  */
+
+/**
+  * @brief   Разрешение работы приемопередатчика SPI
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void SPI_Cmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(SPI->CR1_bit.SSE, State);
+}
+
+/**
+  * @brief   Отключение выхода данных в режиме ведомого
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void SPI_SlaveOutputDisCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(SPI->CR1_bit.SOD, State);
+}
+
+/**
+  * @brief   Настройка полярности и фазы SCK в режиме SPI Motorola
+  * @param   SCKPhase  Режим фазы
+  * @param   SCKPhase  Режим полярности
+  * @retval  void
+  */
+__STATIC_INLINE void SPI_SCKConfig(SPI_SCKPhase_TypeDef SCKPhase, SPI_SCKPolarity_TypeDef SCKPolarity)
+{
+    assert_param(IS_SPI_SCK_PHASE(SCKPhase));
+    assert_param(IS_SPI_SCK_POLARITY(SCKPolarity));
+
+    MODIFY_REG(SPI->CR0, SPI_CR0_SPH_Msk | SPI_CR0_SPO_Msk,
+               ((SCKPhase << SPI_CR0_SPH_Pos) |
+                (SCKPolarity << SPI_CR0_SPO_Pos)));
+}
+
+/**
+  * @brief   Настройка ширины слова данных
+  * @param   DataWidth  Значение разрядности слова
+  * @retval  void
+  */
+__STATIC_INLINE void SPI_DataWidthConfig(SPI_DataWidth_TypeDef DataWidth)
+{
+    assert_param(IS_SPI_DATA_WIDTH(DataWidth));
+
+    WRITE_REG(SPI->CR0_bit.DSS, DataWidth);
+}
+
+/**
+  * @brief   Настройка режима работы SPI
+  * @param   Mode  Выбор режима
+  * @retval  void
+  */
+__STATIC_INLINE void SPI_ModeConfig(SPI_Mode_TypeDef Mode)
+{
+    assert_param(IS_SPI_MODE(Mode));
+
+    WRITE_REG(SPI->CR1_bit.MS, Mode);
+}
+
+/**
+  * @brief   Настройка режима формата кадра
+  * @param   FrameFormat  Выбор формата
+  * @retval  void
+  */
+__STATIC_INLINE void SPI_FrameFormatConfig(SPI_FrameFormat_TypeDef FrameFormat)
+{
+    assert_param(IS_SPI_FRAME_FORMAT(FrameFormat));
+
+    WRITE_REG(SPI->CR0_bit.FRF, FrameFormat);
+}
+
+/**
+  * @brief   Настройка делителя для получение нужной частоты SCK.
+  *          Результирующий коэффциент деления = SCKDivExtra * (1 + SCKDiv).
+  * @param   SCKDiv  Основной делитель.
+  *                  Параметр принимает любое значение из диапазона 0-255.
+  * @param   SCKDivExtra  Дополнительный делитель.
+                          Параметр может принимать любые четные значения из диапазона: 2-254.
+
+  * @retval  void
+  */
+__STATIC_INLINE void SPI_SCKDivConfig(uint32_t SCKDiv, uint32_t SCKDivExtra)
+{
+    assert_param(IS_SPI_SCK_DIV(SCKDiv));
+    assert_param(IS_SPI_SCK_DIV_EXTRA(SCKDivExtra));
+
+    WRITE_REG(SPI->CR0_bit.SCR, SCKDiv);
+    WRITE_REG(SPI->CPSR, SCKDivExtra);
+}
+
+/** @defgroup SPI_Init_Deinit Инициализация и деинициализация
+  * @{
+  */
+
+void SPI_DeInit(void);
+void SPI_Init(SPI_Init_TypeDef* InitStruct);
+void SPI_StructInit(SPI_Init_TypeDef* InitStruct);
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_SendRecieve Прием и передача
+  * @{
+  */
+
+/**
+  * @brief   Передача слова данных
+  * @param   Data   Слово данных
+  * @retval  void
+  */
+__STATIC_INLINE void SPI_SendData(uint32_t Data)
+{
+    assert_param(IS_SPI_DATA(Data));
+
+    WRITE_REG(SPI->DR, Data);
+}
+
+/**
+  * @brief   Прием слова данных
+  * @retval  Val  Слово данных
+  */
+__STATIC_INLINE uint32_t SPI_RecieveData()
+{
+    return READ_REG(SPI->DR);
+}
+
+/**
+  * @brief   Запрос состояния выбранного флага
+  * @param   Flag  Выбор флагов.
+  *                Параметр принимает любую совокупность значений SPI_Flag_x из @ref SPI_Flag_Define.
+  * @retval  Status  Состояние флага. Если выбрано несколько флагов,
+  *                  то результат соответсвует логическому ИЛИ их состояний.
+  */
+__STATIC_INLINE FlagStatus SPI_FlagStatus(uint32_t Flag)
+{
+    assert_param(IS_SPI_FLAG(Flag));
+
+    return (FlagStatus)READ_BIT(SPI->SR, Flag);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_IT Прерывания
+  * @{
+  */
+
+/**
+  * @brief   Настройка порога заполнения FIFO при приёме для генерации прерывания
+  * @param   FIFOLevelRx  Порог.
+  *                       Параметр принимает любое значение из диапазона 0-8.
+  * @retval  void
+  */
+__STATIC_INLINE void SPI_ITFIFOLevelRxConfig(uint32_t FIFOLevelRx)
+{
+    assert_param(IS_SPI_FIFO_LEVEL(FIFOLevelRx));
+
+    WRITE_REG(SPI->CR1_bit.RXIFLSEL, FIFOLevelRx);
+}
+
+/**
+  * @brief   Настройка порога опустошения FIFO при передаче для генерации прерывания
+  * @param   FIFOLevelTx  Порог.
+  *                       Параметр принимает любое значение из диапазона 0-8.
+  * @retval  void
+  */
+__STATIC_INLINE void SPI_ITFIFOLevelTxConfig(uint32_t FIFOLevelTx)
+{
+    assert_param(IS_SPI_FIFO_LEVEL(FIFOLevelTx));
+
+    WRITE_REG(SPI->CR1_bit.TXIFLSEL, FIFOLevelTx);
+}
+
+/**
+  * @brief   Маскирование выбранных прерываний
+  * @param   ITSource  Выбор прерываний.
+  *                    Параметр принимает любую совокупность значений SPI_ITSource_x из @ref SPI_ITSource_Define.
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void SPI_ITCmd(uint32_t ITSource, FunctionalState State)
+{
+    assert_param(IS_SPI_IT_SOURCE(ITSource));
+
+    MODIFY_REG(SPI->IMSC, ITSource, State ? ITSource : 0);
+}
+
+/**
+  * @brief   Запрос немаскированного состояния прерывания
+  * @param   ITSource  Выбор прерываний.
+  *                    Параметр принимает любую совокупность значений SPI_ITSource_x из @ref SPI_ITSource_Define.
+  * @retval  Status  Состояние флага. Если выбрано несколько прерываний,
+  *                  то результат соответсвует логическому ИЛИ их состояний.
+  */
+__STATIC_INLINE FlagStatus SPI_ITRawStatus(uint32_t ITSource)
+{
+    assert_param(IS_SPI_IT_SOURCE(ITSource));
+
+    return (FlagStatus)READ_BIT(SPI->RIS, ITSource);
+}
+
+/**
+  * @brief   Запрос маскированного состояния прерывания
+  * @param   ITSource  Выбор прерываний.
+  *                    Параметр принимает любую совокупность значений SPI_ITSource_x из @ref SPI_ITSource_Define.
+  * @retval  Status  Состояние флага. Если выбрано несколько прерываний,
+  *                  то результат соответсвует логическому ИЛИ их состояний.
+  */
+__STATIC_INLINE FlagStatus SPI_ITMaskedStatus(uint32_t ITSource)
+{
+    assert_param(IS_SPI_IT_SOURCE(ITSource));
+
+    return (FlagStatus)READ_BIT(SPI->MIS, ITSource);
+}
+
+/**
+  * @brief   Сброс флагов состояния выбранных прерываний
+  * @param   ITSource  Выбор прерываний.
+  *                    Параметр принимает любую совокупность значений SPI_ITSource_x из @ref SPI_ITSource_Define.
+  * @retval  void
+  */
+__STATIC_INLINE void SPI_ITStatusClear(uint32_t ITSource)
+{
+    assert_param(IS_SPI_IT_SOURCE(ITSource));
+
+    WRITE_REG(SPI->ICR, ITSource);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_DMA Настройка DMA
+  * @{
+  */
+
+/**
+  * @brief   Разрешение формирования запросов DMA для обслуживания буфера приемника
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void SPI_DMARxCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(SPI->DMACR_bit.RXDMAE, State);
+}
+
+/**
+  * @brief   Разрешение формирования запросов DMA для обслуживания буфера передатчика
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void SPI_DMATxCmd(FunctionalState State)
+{
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(SPI->DMACR_bit.TXDMAE, State);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PLIB035_SPI_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2018 NIIET *****END OF FILE****/

platform/plib035/inc/plib035_tmr.h

@@ -0,0 +1,245 @@
+/**
+  ******************************************************************************
+  * @file    plib035_tmr.h
+  *
+  * @brief   Файл содержит прототипы и компактные inline реализации функций для
+  *          TMR, а также сопутствующие макроопределения и перечисления
+  *
+  * @author  НИИЭТ, Богдан Колбов <kolbov@niiet.ru>
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ ПРЕДОСТАВЛЯЕТСЯ «КАК ЕСТЬ», БЕЗ КАКИХ-ЛИБО
+  * ГАРАНТИЙ, ЯВНО ВЫРАЖЕННЫХ ИЛИ ПОДРАЗУМЕВАЕМЫХ, ВКЛЮЧАЯ ГАРАНТИИ ТОВАРНОЙ
+  * ПРИГОДНОСТИ, СООТВЕТСТВИЯ ПО ЕГО КОНКРЕТНОМУ НАЗНАЧЕНИЮ И ОТСУТСТВИЯ
+  * НАРУШЕНИЙ, НО НЕ ОГРАНИЧИВАЯСЬ ИМИ. ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ
+  * ПРЕДНАЗНАЧЕНО ДЛЯ ОЗНАКОМИТЕЛЬНЫХ ЦЕЛЕЙ И НАПРАВЛЕНО ТОЛЬКО НА
+  * ПРЕДОСТАВЛЕНИЕ ДОПОЛНИТЕЛЬНОЙ ИНФОРМАЦИИ О ПРОДУКТЕ, С ЦЕЛЬЮ СОХРАНИТЬ ВРЕМЯ
+  * ПОТРЕБИТЕЛЮ. НИ В КАКОМ СЛУЧАЕ АВТОРЫ ИЛИ ПРАВООБЛАДАТЕЛИ НЕ НЕСУТ
+  * ОТВЕТСТВЕННОСТИ ПО КАКИМ-ЛИБО ИСКАМ, ЗА ПРЯМОЙ ИЛИ КОСВЕННЫЙ УЩЕРБ, ИЛИ
+  * ПО ИНЫМ ТРЕБОВАНИЯМ, ВОЗНИКШИМ ИЗ-ЗА ИСПОЛЬЗОВАНИЯ ПРОГРАММНОГО ОБЕСПЕЧЕНИЯ
+  * ИЛИ ИНЫХ ДЕЙСТВИЙ С ПРОГРАММНЫМ ОБЕСПЕЧЕНИЕМ.
+  *
+  * <h2><center>&copy; 2018 ОАО "НИИЭТ"</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PLIB035_TMR_H
+#define __PLIB035_TMR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "plib035.h"
+
+/** @addtogroup Peripheral
+  * @{
+  */
+
+/** @defgroup TMR
+  * @brief Драйвер для работы с TMR
+  * @{
+  */
+
+/** @defgroup TMR_Exported_Defines Константы
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TMR_Exported_Types Типы
+  * @{
+  */
+
+/**
+  * @brief  Настройка внешнего тактирования таймера
+  */
+typedef enum {
+    TMR_ExtInput_Disable = 0x0UL,                                         /*!< Внешнее тактирование не используется */
+    TMR_ExtInput_CountClk = TMR_CTRL_EXTINEN_Msk | TMR_CTRL_EXTINCLK_Msk, /*!< Таймер считает по внешнему тактовому сигналу */
+    TMR_ExtInput_CountEn = TMR_CTRL_EXTINEN_Msk                           /*!< Таймер считает по внутреннему тактовому сигналу и только тогда, когда на выводе "1" */
+} TMR_ExtInput_TypeDef;
+#define IS_TMR_EXT_INPUT(VALUE) (((VALUE) == TMR_ExtInput_Disable) ||  \
+                                 ((VALUE) == TMR_ExtInput_CountClk) || \
+                                 ((VALUE) == TMR_ExtInput_CountEn))
+/**
+  * @}
+  */
+
+/** @defgroup TMR_Exported_Functions Функции
+  * @{
+  */
+
+/**
+  * @brief   Разрешение работы выбранного таймера
+  * @param   TMRx  Выбор таймера, где x лежит в диапазоне 0-3
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void TMR_Cmd(TMR_TypeDef* TMRx, FunctionalState State)
+{
+    assert_param(IS_TMR_PERIPH(TMRx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(TMRx->CTRL_bit.ON, State);
+}
+
+/**
+  * @brief   Установка значения перезагрузки
+  * @param   TMRx  Выбор таймера, где x лежит в диапазоне 0-3
+  * @param   LoadVal  Значение перезагрузки
+  * @retval  void
+  */
+__STATIC_INLINE void TMR_SetLoad(TMR_TypeDef* TMRx, uint32_t LoadVal)
+{
+    assert_param(IS_TMR_PERIPH(TMRx));
+
+    WRITE_REG(TMRx->LOAD, LoadVal);
+}
+
+/**
+  * @brief   Получение текущего значения перезагрузки
+  * @param   TMRx  Выбор таймера, где x лежит в диапазоне 0-3
+  * @retval  Val  Значение перезагрузки
+  */
+__STATIC_INLINE uint32_t TMR_GetLoad(TMR_TypeDef* TMRx)
+{
+    assert_param(IS_TMR_PERIPH(TMRx));
+
+    return READ_REG(TMRx->LOAD);
+}
+
+/**
+  * @brief   Установка значения счетчика
+  * @param   TMRx  Выбор таймера, где x лежит в диапазоне 0-3
+  * @param   CounterVal  Значение счетчика
+  * @retval  void
+  */
+__STATIC_INLINE void TMR_SetCounter(TMR_TypeDef* TMRx, uint32_t CounterVal)
+{
+    assert_param(IS_TMR_PERIPH(TMRx));
+
+    WRITE_REG(TMRx->VALUE, CounterVal);
+}
+
+/**
+  * @brief   Получение текущего значения счетчика.
+  * @param   TMRx  Выбор таймера, где x лежит в диапазоне 0-3
+  * @retval  Val  Значение счетчика
+  */
+__STATIC_INLINE uint32_t TMR_GetCounter(TMR_TypeDef* TMRx)
+{
+    assert_param(IS_TMR_PERIPH(TMRx));
+
+    return READ_REG(TMRx->VALUE);
+}
+
+/**
+  * @brief   Выбор режима работы входа внешнего тактирования.
+  * @param   TMRx  Выбор таймера, где x лежит в диапазоне 0-3
+  * @param   TMR_ExtInput  Выбор режима работы
+  * @retval  void
+  */
+
+__STATIC_INLINE void TMR_ExtInputConfig(TMR_TypeDef* TMRx, TMR_ExtInput_TypeDef ExtInput)
+{
+    assert_param(IS_TMR_PERIPH(TMRx));
+    assert_param(IS_TMR_EXT_INPUT(ExtInput));
+
+    MODIFY_REG(TMRx->CTRL, TMR_CTRL_EXTINEN_Msk | TMR_CTRL_EXTINCLK_Msk, ExtInput);
+}
+
+/**
+  * @brief   Разрешение работы прерывания выбранного таймера
+  * @param   TMRx  Выбор таймера, где x лежит в диапазоне 0-3
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void TMR_ITCmd(TMR_TypeDef* TMRx, FunctionalState State)
+{
+    assert_param(IS_TMR_PERIPH(TMRx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(TMRx->CTRL_bit.INTEN, State);
+}
+
+/**
+  * @brief   Чтение статуса прерывания выбранного таймера
+  * @param   TMRx  Выбор таймера, где x лежит в диапазоне 0-3
+  * @retval  Status  Статус прерывания
+  */
+__STATIC_INLINE FlagStatus TMR_ITStatus(TMR_TypeDef* TMRx)
+{
+    assert_param(IS_TMR_PERIPH(TMRx));
+
+    return (FlagStatus)READ_BIT(TMRx->INTSTATUS, TMR_INTSTATUS_INT_Msk);
+}
+
+/**
+  * @brief   Очищение статусного бита прерывания выбранного таймера.
+  * @param   TMRx  Выбор таймера, где x лежит в диапазоне 0-3.
+  * @retval  void
+  */
+__STATIC_INLINE void TMR_ITStatusClear(TMR_TypeDef* TMRx)
+{
+    assert_param(IS_TMR_PERIPH(TMRx));
+
+    WRITE_REG(TMRx->INTSTATUS, TMR_INTSTATUS_INT_Msk);
+}
+
+void TMR_PeriodConfig(TMR_TypeDef* TMRx, uint32_t TimerClkFreq, uint32_t TimerPeriod);
+void TMR_FreqConfig(TMR_TypeDef* TMRx, uint32_t TimerClkFreq, uint32_t TimerFreq);
+
+/**
+  * @brief   Разрешение генерации запросов к DMA
+  * @param   TMRx  Выбор таймера, где x лежит в диапазоне 0-3
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void TMR_DMAReqCmd(TMR_TypeDef* TMRx, FunctionalState State)
+{
+    assert_param(IS_TMR_PERIPH(TMRx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(TMRx->DMAREQ_bit.EN, State);
+}
+
+/**
+  * @brief   Разрешение генерации сигналов запуска АЦП
+  * @param   TMRx  Выбор таймера, где x лежит в диапазоне 0-3
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void TMR_ADCSOCCmd(TMR_TypeDef* TMRx, FunctionalState State)
+{
+    assert_param(IS_TMR_PERIPH(TMRx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(TMRx->ADCSOC_bit.EN, State);
+}
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PLIB035_TMR_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2018 NIIET *****END OF FILE****/

platform/plib035/inc/plib035_uart.h

@@ -0,0 +1,606 @@
+/**
+  ******************************************************************************
+  * @file    plib035_uart.h
+  *
+  * @brief   Файл содержит прототипы и компактные inline реализации функций для
+  *          UART, а также сопутствующие макроопределения и перечисления
+  *
+  * @author  НИИЭТ, Богдан Колбов <kolbov@niiet.ru>
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ ПРЕДОСТАВЛЯЕТСЯ «КАК ЕСТЬ», БЕЗ КАКИХ-ЛИБО
+  * ГАРАНТИЙ, ЯВНО ВЫРАЖЕННЫХ ИЛИ ПОДРАЗУМЕВАЕМЫХ, ВКЛЮЧАЯ ГАРАНТИИ ТОВАРНОЙ
+  * ПРИГОДНОСТИ, СООТВЕТСТВИЯ ПО ЕГО КОНКРЕТНОМУ НАЗНАЧЕНИЮ И ОТСУТСТВИЯ
+  * НАРУШЕНИЙ, НО НЕ ОГРАНИЧИВАЯСЬ ИМИ. ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ
+  * ПРЕДНАЗНАЧЕНО ДЛЯ ОЗНАКОМИТЕЛЬНЫХ ЦЕЛЕЙ И НАПРАВЛЕНО ТОЛЬКО НА
+  * ПРЕДОСТАВЛЕНИЕ ДОПОЛНИТЕЛЬНОЙ ИНФОРМАЦИИ О ПРОДУКТЕ, С ЦЕЛЬЮ СОХРАНИТЬ ВРЕМЯ
+  * ПОТРЕБИТЕЛЮ. НИ В КАКОМ СЛУЧАЕ АВТОРЫ ИЛИ ПРАВООБЛАДАТЕЛИ НЕ НЕСУТ
+  * ОТВЕТСТВЕННОСТИ ПО КАКИМ-ЛИБО ИСКАМ, ЗА ПРЯМОЙ ИЛИ КОСВЕННЫЙ УЩЕРБ, ИЛИ
+  * ПО ИНЫМ ТРЕБОВАНИЯМ, ВОЗНИКШИМ ИЗ-ЗА ИСПОЛЬЗОВАНИЯ ПРОГРАММНОГО ОБЕСПЕЧЕНИЯ
+  * ИЛИ ИНЫХ ДЕЙСТВИЙ С ПРОГРАММНЫМ ОБЕСПЕЧЕНИЕМ.
+  *
+  * <h2><center>&copy; 2018 ОАО "НИИЭТ"</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PLIB035_UART_H
+#define __PLIB035_UART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "plib035.h"
+
+/** @addtogroup Peripheral
+  * @{
+  */
+
+/** @defgroup UART
+  * @brief Драйвер для работы с UART
+  * @{
+  */
+
+/** @defgroup UART_Exported_Defines Константы
+  * @{
+  */
+
+/** @defgroup UART_ITSource_Define Источники прерываний UART
+  * @{
+  */
+
+#define UART_ITSource_RxFIFOLevel UART_IMSC_RXIM_Msk    /*!< Порог переполнения буфера приемника */
+#define UART_ITSource_TxFIFOLevel UART_IMSC_TXIM_Msk    /*!< Порог опустошения буфера передатчика */
+#define UART_ITSource_RecieveTimeout UART_IMSC_RTIM_Msk /*!< Таймаут приема данных */
+#define UART_ITSource_ErrorFrame UART_IMSC_FERIM_Msk    /*!< Ошибка в структуре кадра */
+#define UART_ITSource_ErrorParity UART_IMSC_PERIM_Msk   /*!< Ошибка контроля четности */
+#define UART_ITSource_ErrorBreak UART_IMSC_BERIM_Msk    /*!< Разрыв линии */
+#define UART_ITSource_ErrorOverflow UART_IMSC_OERIM_Msk /*!< Переполнение буффера приемника */
+#define UART_ITSource_TransmitDone UART_IMSC_TDIM_Msk   /*!< Окончание передачи в линии */
+#define UART_ITSource_All (UART_IMSC_RXIM_Msk |  \
+                           UART_IMSC_TXIM_Msk |  \
+                           UART_IMSC_RTIM_Msk |  \
+                           UART_IMSC_FEIM_Msk | \
+                           UART_IMSC_PEIM_Msk | \
+                           UART_IMSC_BEIM_Msk | \
+                           UART_IMSC_OEIM_Msk | \
+                           UART_IMSC_TDIM_Msk) /*!< Все источники выбраны */
+
+#define IS_UART_IT_SOURCE(VALUE) (((VALUE) & ~UART_ITSource_All) == 0)
+
+/**
+   * @}
+   */
+
+/** @defgroup UART_Flag_Define Флаги работы UART
+  * @{
+  */
+
+#define UART_Flag_Busy UART_FR_BUSY_Msk        /*!< Флаг занятости блока UART */
+#define UART_Flag_RxFIFOEmpty UART_FR_RXFE_Msk /*!< Флаг пустоты буффера приемника */
+#define UART_Flag_TxFIFOFull UART_FR_TXFF_Msk  /*!< Флаг заполнения буффера передатчика */
+#define UART_Flag_RxFIFOFull UART_FR_RXFF_Msk  /*!< Флаг заполнения буффера приемника */
+#define UART_Flag_TxFIFOEmpty UART_FR_TXFE_Msk /*!< Флаг пустоты буффера передатчика */
+#define UART_Flag_All (UART_FR_BUSY_Msk | \
+                       UART_FR_RXFE_Msk | \
+                       UART_FR_TXFF_Msk | \
+                       UART_FR_RXFF_Msk | \
+                       UART_FR_TXFE_Msk) /*!< Все флаги выбраны */
+
+#define IS_UART_FLAG(VALUE) (((VALUE) & ~UART_Flag_All) == 0)
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Error_Define Ошибки приемника UART
+   * @{
+   */
+
+#define UART_Error_Frame UART_RSR_FE_Msk    /*!< Флаг ошибки в структуре кадра */
+#define UART_Error_Parity UART_RSR_PE_Msk   /*!< Флаг ошибки контроля четности */
+#define UART_Error_Break UART_RSR_BE_Msk    /*!< Флаг разрыва линии */
+#define UART_Error_Overflow UART_RSR_OE_Msk /*!< Флаг переполнения буффера приемника */
+#define UART_Error_All (UART_RSR_FE_Msk | \
+                        UART_RSR_PE_Msk | \
+                        UART_RSR_BE_Msk | \
+                        UART_RSR_OE_Msk) /*!< Все флаги ошибок выбраны */
+
+#define IS_UART_ERROR(VALUE) (((VALUE) & ~UART_Error_All) == 0)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Exported_Types Типы
+  * @{
+  */
+
+#define IS_UART_INT_DIV(VALUE) (((VALUE) > 0) && ((VALUE) < 0x10000))
+#define IS_UART_FRAC_DIV(VALUE) ((VALUE) < 0x40)
+#define IS_UART_DATA(VALUE) ((VALUE) < 0x100)
+
+/**
+  * @brief  Выбор режима передачи стопового бита
+  */
+typedef enum {
+    UART_StopBit_1, /*!< Один стоповый бит */
+    UART_StopBit_2  /*!< Два стоповых бита */
+} UART_StopBit_TypeDef;
+#define IS_UART_STOP_BIT(VALUE) (((VALUE) == UART_StopBit_1) || \
+                                 ((VALUE) == UART_StopBit_2))
+
+/**
+  * @brief  Выбор режима бита четности
+  */
+typedef enum {
+    UART_ParityBit_Disable = 0,                                                    /*!< Не передается, не проверяется */
+    UART_ParityBit_Odd = UART_LCRH_PEN_Msk,                                        /*!< Проверка нечетности данных */
+    UART_ParityBit_Even = UART_LCRH_PEN_Msk | UART_LCRH_EPS_Msk,                   /*!< Проверка четности данных */
+    UART_ParityBit_High = UART_LCRH_PEN_Msk | UART_LCRH_SPS_Msk,                   /*!< Бит четности постоянно равен единице */
+    UART_ParityBit_Low = UART_LCRH_PEN_Msk | UART_LCRH_SPS_Msk | UART_LCRH_EPS_Msk /*!< Бит четности постоянно равен нулю */
+} UART_ParityBit_TypeDef;
+#define IS_UART_PARITY_BIT(VALUE) (((VALUE) == UART_ParityBit_Disable) || \
+                                   ((VALUE) == UART_ParityBit_Odd) ||     \
+                                   ((VALUE) == UART_ParityBit_Even) ||    \
+                                   ((VALUE) == UART_ParityBit_High) ||    \
+                                   ((VALUE) == UART_ParityBit_Low))
+
+/**
+  * @brief  Количество передаваемых/принимаемых информационных бит
+  */
+typedef enum {
+    UART_DataWidth_5 = UART_LCRH_WLEN_5bit, /*!< Длина информационного слова 5 бит */
+    UART_DataWidth_6 = UART_LCRH_WLEN_6bit, /*!< Длина информационного слова 6 бит */
+    UART_DataWidth_7 = UART_LCRH_WLEN_7bit, /*!< Длина информационного слова 7 бит */
+    UART_DataWidth_8 = UART_LCRH_WLEN_8bit  /*!< Длина информационного слова 8 бит */
+} UART_DataWidth_TypeDef;
+#define IS_UART_DATA_WIDTH(VALUE) (((VALUE) == UART_DataWidth_5) || \
+                                   ((VALUE) == UART_DataWidth_6) || \
+                                   ((VALUE) == UART_DataWidth_7) || \
+                                   ((VALUE) == UART_DataWidth_8))
+
+/**
+  * @brief  Порог заполнения/опустошения буфера приемника/передатчика, по достижению которого
+  *   будет генерироваться прерывание
+  */
+typedef enum {
+    UART_FIFOLevel_1_8 = UART_IFLS_TXIFLSEL_Lvl18, /*!< Заполнение/опустошение FIFO на 1/8 */
+    UART_FIFOLevel_1_4 = UART_IFLS_TXIFLSEL_Lvl14, /*!< Заполнение/опустошение FIFO на 1/4 */
+    UART_FIFOLevel_1_2 = UART_IFLS_TXIFLSEL_Lvl12, /*!< Заполнение/опустошение FIFO на 1/2 */
+    UART_FIFOLevel_3_4 = UART_IFLS_TXIFLSEL_Lvl34, /*!< Заполнение/опустошение FIFO на 3/4 */
+    UART_FIFOLevel_7_8 = UART_IFLS_TXIFLSEL_Lvl78  /*!< Заполнение/опустошение FIFO на 7/8 */
+} UART_FIFOLevel_TypeDef;
+#define IS_UART_FIFO_LEVEL(VALUE) (((VALUE) == UART_FIFOLevel_1_8) || \
+                                   ((VALUE) == UART_FIFOLevel_1_4) || \
+                                   ((VALUE) == UART_FIFOLevel_1_2) || \
+                                   ((VALUE) == UART_FIFOLevel_3_4) || \
+                                   ((VALUE) == UART_FIFOLevel_7_8))
+
+/**
+  * @brief  Структура инициализации UART
+  */
+
+typedef struct
+{
+    UART_StopBit_TypeDef StopBit;     /*!< Выбор режима передачи стопового бита */
+    UART_ParityBit_TypeDef ParityBit; /*!< Выбор режима бита четности */
+    UART_DataWidth_TypeDef DataWidth; /*!< Количество передаваемых/принимаемых информационных бит */
+    uint32_t BaudRate;                /*!< Желаемая скорость передачи данных в бит/с */
+    FunctionalState FIFO;             /*!< Разрешение режима FIFO буфера приемника и передатчика */
+    FunctionalState Rx;               /*!< Разрешение приема */
+    FunctionalState Tx;               /*!< Разрешение передачи */
+} UART_Init_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions Функции
+  * @{
+  */
+
+void UART_AutoBaudConfig(UART_TypeDef* UARTx, uint32_t BaudRate);
+
+/**
+  * @brief   Разрешение работы выбранного UART
+  * @param   UARTx  Выбор модуля UART, где x=0|1
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void UART_Cmd(UART_TypeDef* UARTx, FunctionalState State)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(UARTx->CR_bit.UARTEN, State);
+}
+
+/**
+  * @brief   Настройка ширины слова данных
+  * @param   UARTx  Выбор модуля UART, где x=0|1
+  * @param   DataWidth  Значение разрядности слова
+  * @retval  void
+  */
+__STATIC_INLINE void UART_DataWidthConfig(UART_TypeDef* UARTx, UART_DataWidth_TypeDef DataWidth)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_DATA_WIDTH(DataWidth));
+
+    WRITE_REG(UARTx->LCRH_bit.WLEN, DataWidth);
+}
+
+/**
+  * @brief   Настройка количества стоп-бит
+  * @param   UARTx  Выбор модуля UART, где x=0|1
+  * @param   StopBit  Количество стоп-бит
+  * @retval  void
+  */
+__STATIC_INLINE void UART_StopBitConfig(UART_TypeDef* UARTx, UART_StopBit_TypeDef StopBit)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_STOP_BIT(StopBit));
+
+    WRITE_REG(UARTx->LCRH_bit.STP2, StopBit);
+}
+
+/**
+  * @brief   Настройка режима бита четности
+  * @param   UARTx  Выбор модуля UART, где x=0|1
+  * @param   ParityBit  Режим
+  * @retval  void
+  */
+__STATIC_INLINE void UART_ParityBitConfig(UART_TypeDef* UARTx, UART_ParityBit_TypeDef ParityBit)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_PARITY_BIT(ParityBit));
+
+    MODIFY_REG(UARTx->LCRH, UART_LCRH_PEN_Msk | UART_LCRH_SPS_Msk | UART_LCRH_EPS_Msk, ParityBit);
+}
+
+/**
+  * @brief   Ручная настройка делителя для реализации необходимой скорости передачи
+  * @param   UARTx  Выбор модуля UART, где x=0|1
+  * @param   IntDiv  Целая часть делителя.
+  *                  Параметр принимает любое значение из диапазона 1-65535.
+  * @param   FracDiv  Дробная часть делителя.
+  *                   Параметр принимает любое значение из диапазона 0-63. В случае, если IntDiv
+  *                   равен 65535, значение FracDiv может быть только 0.
+  * @retval  void
+  */
+__STATIC_INLINE void UART_BaudDivConfig(UART_TypeDef* UARTx, uint32_t IntDiv, uint32_t FracDiv)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_INT_DIV(IntDiv));
+    assert_param(IS_UART_FRAC_DIV(FracDiv));
+
+    WRITE_REG(UARTx->IBRD, IntDiv);
+    WRITE_REG(UARTx->FBRD, FracDiv);
+}
+
+/**
+  * @brief   Включение разрыва линии
+  * @param   UARTx  Выбор модуля UART, где x=0|1
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void UART_BreakCmd(UART_TypeDef* UARTx, FunctionalState State)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(UARTx->LCRH_bit.BRK, State);
+}
+
+/**
+  * @brief   Включение FIFO
+  * @param   UARTx  Выбор модуля UART, где x=0|1
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void UART_FIFOCmd(UART_TypeDef* UARTx, FunctionalState State)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(UARTx->LCRH_bit.FEN, State);
+}
+
+/**
+  * @brief   Разрешение приема
+  * @param   UARTx  Выбор модуля UART, где x=0|1
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void UART_RxCmd(UART_TypeDef* UARTx, FunctionalState State)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(UARTx->CR_bit.RXE, State);
+}
+
+/**
+  * @brief   Разрешение передачи
+  * @param   UARTx  Выбор модуля UART, где x=0|1
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void UART_TxCmd(UART_TypeDef* UARTx, FunctionalState State)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(UARTx->CR_bit.TXE, State);
+}
+
+/** @defgroup UART_Init_Deinit Инициализация и деинициализация
+  * @{
+  */
+
+void UART_DeInit(UART_TypeDef* UARTx);
+void UART_Init(UART_TypeDef* UARTx, UART_Init_TypeDef* InitStruct);
+void UART_StructInit(UART_Init_TypeDef* InitStruct);
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_SendRecieve Прием и передача
+  * @{
+  */
+
+/**
+  * @brief   Передача слова данных
+  * @param   UARTx  Выбор модуля UART, где x=0|1
+  * @param   Data   Слово данных (биты 7-0)
+  * @retval  void
+  */
+__STATIC_INLINE void UART_SendData(UART_TypeDef* UARTx, uint32_t Data)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_DATA(Data));
+
+    WRITE_REG(UARTx->DR, Data);
+}
+
+/**
+  * @brief   Прием слова данных
+  * @param   UARTx  Выбор модуля UART, где x=0|1
+  * @retval  Val  Слово данных
+  */
+__STATIC_INLINE uint32_t UART_RecieveData(UART_TypeDef* UARTx)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    return READ_REG(UARTx->DR_bit.DATA);
+}
+
+/**
+  * @brief   Запрос состояния выбранного флага
+  * @param   UARTx  Выбор модуля UART, где x=0|1
+  * @param   Flag  Выбор флагов.
+  *                Параметр принимает любую совокупность значений UART_Flag_x из @ref UART_Flag_Define.
+  * @retval  Status  Состояние флага. Если выбрано несколько флагов,
+  *                  то результат соответсвует логическому ИЛИ их состояний.
+  */
+__STATIC_INLINE FlagStatus UART_FlagStatus(UART_TypeDef* UARTx, uint32_t Flag)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_FLAG(Flag));
+
+    return (FlagStatus)READ_BIT(UARTx->FR, Flag);
+}
+
+/**
+  * @brief   Запрос состояния выбранного флага ошибки
+  * @param   UARTx  Выбор модуля UART, где x=0|1
+  * @param   Error  Выбор флагов ошибки.
+  *                 Параметр принимает любую совокупность значений UART_Error_x из @ref UART_Error_Define.
+  * @retval  Status  Состояние флага. Если выбрано несколько флагов,
+  *                  то результат соответсвует логическому ИЛИ их состояний.
+  */
+__STATIC_INLINE FlagStatus UART_ErrorStatus(UART_TypeDef* UARTx, uint32_t Error)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_ERROR(Error));
+
+    return (FlagStatus)READ_BIT(UARTx->RSR, Error);
+}
+
+/**
+  * @brief   Очистка флагов ошибки
+  * @param   UARTx  Выбор модуля UART, где x=0|1
+  * @param   Error  Выбор флагов ошибки.
+  *                 Параметр принимает любую совокупность значений UART_Error_x из @ref UART_Error_Define.
+  * @retval  void
+  */
+__STATIC_INLINE void UART_ErrorStatusClear(UART_TypeDef* UARTx, uint32_t Error)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_ERROR(Error));
+
+    WRITE_REG(UARTx->RSR, Error);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_IT Прерывания
+  * @{
+  */
+
+/**
+  * @brief   Настройка порога заполнения FIFO при приёме для генерации прерывания
+  * @param   UARTx  Выбор модуля UART, где x=0|1
+  * @param   FIFOLevelRx  Порог
+  * @retval  void
+  */
+__STATIC_INLINE void UART_ITFIFOLevelRxConfig(UART_TypeDef* UARTx, UART_FIFOLevel_TypeDef FIFOLevelRx)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_FIFO_LEVEL(FIFOLevelRx));
+
+    WRITE_REG(UARTx->IFLS_bit.RXIFLSEL, FIFOLevelRx);
+}
+
+/**
+  * @brief   Настройка порога опустошения FIFO при передаче для генерации прерывания
+  * @param   UARTx  Выбор модуля UART, где x=0|1
+  * @param   FIFOLevelTx  Порог
+  * @retval  void
+  */
+__STATIC_INLINE void UART_ITFIFOLevelTxConfig(UART_TypeDef* UARTx, UART_FIFOLevel_TypeDef FIFOLevelTx)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_FIFO_LEVEL(FIFOLevelTx));
+
+    WRITE_REG(UARTx->IFLS_bit.TXIFLSEL, FIFOLevelTx);
+}
+
+/**
+  * @brief   Маскирование выбранных прерываний
+  * @param   UARTx  Выбор модуля UART, где x=0|1
+  * @param   ITSource  Выбор прерываний.
+  *                    Параметр принимает любую совокупность значений UART_ITSource_x из @ref UART_ITSource_Define.
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void UART_ITCmd(UART_TypeDef* UARTx, uint32_t ITSource, FunctionalState State)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_IT_SOURCE(ITSource));
+
+    MODIFY_REG(UARTx->IMSC, ITSource, State ? ITSource : 0);
+}
+
+/**
+  * @brief   Запрос немаскированного состояния прерывания
+  * @param   UARTx  Выбор модуля UART, где x=0|1
+  * @param   ITSource  Выбор прерываний.
+  *                    Параметр принимает любую совокупность значений UART_ITSource_x из @ref UART_ITSource_Define.
+  * @retval  Status  Состояние флага. Если выбрано несколько прерываний,
+  *                  то результат соответсвует логическому ИЛИ их состояний.
+  */
+__STATIC_INLINE FlagStatus UART_ITRawStatus(UART_TypeDef* UARTx, uint32_t ITSource)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_IT_SOURCE(ITSource));
+
+    return (FlagStatus)READ_BIT(UARTx->RIS, ITSource);
+}
+
+/**
+  * @brief   Запрос маскированного состояния прерывания
+  * @param   UARTx  Выбор модуля UART, где x=0|1
+  * @param   ITSource  Выбор прерываний.
+  *                    Параметр принимает любую совокупность значений UART_ITSource_x из @ref UART_ITSource_Define.
+  * @retval  Status  Состояние флага. Если выбрано несколько прерываний,
+  *                  то результат соответсвует логическому ИЛИ их состояний.
+  */
+__STATIC_INLINE FlagStatus UART_ITMaskedStatus(UART_TypeDef* UARTx, uint32_t ITSource)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_IT_SOURCE(ITSource));
+
+    return (FlagStatus)READ_BIT(UARTx->MIS, ITSource);
+}
+
+/**
+  * @brief   Сброс флагов состояния выбранных прерываний
+  * @param   UARTx  Выбор модуля UART, где x=0|1
+  * @param   ITSource  Выбор прерываний.
+  *                    Параметр принимает любую совокупность значений UART_ITSource_x из @ref UART_ITSource_Define.
+  * @retval  void
+  */
+__STATIC_INLINE void UART_ITStatusClear(UART_TypeDef* UARTx, uint32_t ITSource)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_IT_SOURCE(ITSource));
+
+    WRITE_REG(UARTx->ICR, ITSource);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_DMA Настройка DMA
+  * @{
+  */
+
+/**
+  * @brief   Управление блокированием запросов DMA от приемника в случае возникновения
+  *          прерывания по ошибке
+  * @param   UARTx  Выбор модуля UART, где x=0|1
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void UART_DMABlkOnErrCmd(UART_TypeDef* UARTx, FunctionalState State)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(UARTx->DMACR_bit.DMAONERR, State);
+}
+
+/**
+  * @brief   Разрешение формирования запросов DMA для обслуживания буфера приемника
+  * @param   UARTx  Выбор модуля UART, где x=0|1
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void UART_DMARxCmd(UART_TypeDef* UARTx, FunctionalState State)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(UARTx->DMACR_bit.RXDMAE, State);
+}
+
+/**
+  * @brief   Разрешение формирования запросов DMA для обслуживания буфера передатчика
+  * @param   UARTx  Выбор модуля UART, где x=0|1
+  * @param   State  Выбор состояния
+  * @retval  void
+  */
+__STATIC_INLINE void UART_DMATxCmd(UART_TypeDef* UARTx, FunctionalState State)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_FUNCTIONAL_STATE(State));
+
+    WRITE_REG(UARTx->DMACR_bit.TXDMAE, State);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PLIB035_UART_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2018 NIIET *****END OF FILE****/

platform/plib035/inc/plib035_version.h

@@ -0,0 +1,44 @@
+/**
+  ******************************************************************************
+  * @file    plib035_version.h
+  *
+  * @brief   Версия библиотеки
+  *
+  * @author  НИИЭТ, Богдан Колбов <kolbov@niiet.ru>
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ ПРЕДОСТАВЛЯЕТСЯ «КАК ЕСТЬ», БЕЗ КАКИХ-ЛИБО
+  * ГАРАНТИЙ, ЯВНО ВЫРАЖЕННЫХ ИЛИ ПОДРАЗУМЕВАЕМЫХ, ВКЛЮЧАЯ ГАРАНТИИ ТОВАРНОЙ
+  * ПРИГОДНОСТИ, СООТВЕТСТВИЯ ПО ЕГО КОНКРЕТНОМУ НАЗНАЧЕНИЮ И ОТСУТСТВИЯ
+  * НАРУШЕНИЙ, НО НЕ ОГРАНИЧИВАЯСЬ ИМИ. ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ
+  * ПРЕДНАЗНАЧЕНО ДЛЯ ОЗНАКОМИТЕЛЬНЫХ ЦЕЛЕЙ И НАПРАВЛЕНО ТОЛЬКО НА
+  * ПРЕДОСТАВЛЕНИЕ ДОПОЛНИТЕЛЬНОЙ ИНФОРМАЦИИ О ПРОДУКТЕ, С ЦЕЛЬЮ СОХРАНИТЬ ВРЕМЯ
+  * ПОТРЕБИТЕЛЮ. НИ В КАКОМ СЛУЧАЕ АВТОРЫ ИЛИ ПРАВООБЛАДАТЕЛИ НЕ НЕСУТ
+  * ОТВЕТСТВЕННОСТИ ПО КАКИМ-ЛИБО ИСКАМ, ЗА ПРЯМОЙ ИЛИ КОСВЕННЫЙ УЩЕРБ, ИЛИ
+  * ПО ИНЫМ ТРЕБОВАНИЯМ, ВОЗНИКШИМ ИЗ-ЗА ИСПОЛЬЗОВАНИЯ ПРОГРАММНОГО ОБЕСПЕЧЕНИЯ
+  * ИЛИ ИНЫХ ДЕЙСТВИЙ С ПРОГРАММНЫМ ОБЕСПЕЧЕНИЕМ.
+  *
+  * <h2><center>&copy; 2018 ОАО "НИИЭТ"</center></h2>
+  ******************************************************************************
+  */
+
+#ifndef __PLIB035_VERSION_H
+#define __PLIB035_VERSION_H
+
+/* Полный номер версии библиотеки */
+#define PLIB035_VERSION 1.1.4
+
+/* Основная версия библиотеки - увеличивается когда вносятся объемные глобальные изменения, ломающие обратную совместимость */
+#define PLIB035_VERSION_MAJOR 1
+
+/* Минорная версия библиотеки - увеличивается когда добавляется функционал */
+#define PLIB035_VERSION_MINOR 1
+
+/* Номер патча библиотеки - увеличивается когда правятся баги */
+#define PLIB035_VERSION_PATCH 4
+
+#endif /* __PLIB035_VERSION_H */
+
+/******************* (C) COPYRIGHT 2018 NIIET *****END OF FILE****/