From c6e1dc049fdab59dc6f63be95e29db616921426c Mon Sep 17 00:00:00 2001 From: Razvalyaev Date: Thu, 25 Dec 2025 10:36:35 +0300 Subject: [PATCH] =?UTF-8?q?=D0=A8=D0=B0=D0=B1=D0=BB=D0=BE=D0=BD=20=D0=BF?= =?UTF-8?q?=D1=80=D0=BE=D0=B5=D0=BA=D1=82=D0=B0=20=D1=81=20=D0=BC=D0=BE?= =?UTF-8?q?=D0=B5=D0=B9=20=D1=80=D0=B0=D1=81=D1=88=D0=B8=D1=80=D0=B5=D0=BD?= =?UTF-8?q?=D0=BD=D0=BE=D0=B9=20=D0=B1=D0=B8=D0=B1=D0=BB=D0=B8=D0=BE=D1=82?= =?UTF-8?q?=D0=B5=D0=BA=D0=BE=D0=B9=20MyLibs?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .gitignore | 49 + .gitmodules | 4 + Core/App/gpio.c | 68 + Core/App/gpio.h | 149 + Core/App/main.c | 68 + Core/App/main.h | 35 + Core/App/rcu.c | 31 + Core/App/rcu.h | 22 + Core/App/vk035_it.c | 106 + Core/Config/SEGGER_RTT_Conf.h | 429 + Core/Config/mylibs_config.h | 132 + Core/Config/mylibs_include.h | 141 + Core/ExtendedLibs | 1 + Listings/Firmware.map | 1953 +++ Listings/startup_k1921vk035.lst | 1961 +++ Listings/template.map | 1316 ++ Template.uvoptx | 750 ++ Template.uvprojx | 628 + platform/CMSIS/Core/Include/cmsis_armcc.h | 867 ++ platform/CMSIS/Core/Include/cmsis_armclang.h | 1815 +++ platform/CMSIS/Core/Include/cmsis_cmcpp.h | 127 + platform/CMSIS/Core/Include/cmsis_compiler.h | 264 + platform/CMSIS/Core/Include/cmsis_gcc.h | 2026 +++ platform/CMSIS/Core/Include/cmsis_iccarm.h | 906 ++ platform/CMSIS/Core/Include/cmsis_version.h | 39 + platform/CMSIS/Core/Include/core_cm4.h | 2115 ++++ platform/CMSIS/Core/Include/mpu_armv7.h | 204 + .../NIIET/K1921VK035/Include/K1921VK035.h | 10223 ++++++++++++++++ .../K1921VK035/Include/system_K1921VK035.h | 52 + .../Source/ARM/startup_K1921VK035.s | 393 + .../K1921VK035/Source/system_K1921VK035.c | 167 + .../K1921VK035/РП_1921ВК035_201219.pdf | Bin 0 -> 7685928 bytes platform/plib035/inc/plib035.h | 145 + platform/plib035/inc/plib035_adc.h | 1155 ++ platform/plib035/inc/plib035_assert.h | 57 + platform/plib035/inc/plib035_can.h | 86 + platform/plib035/inc/plib035_conf.h | 49 + platform/plib035/inc/plib035_dma.h | 631 + platform/plib035/inc/plib035_ecap.h | 910 ++ platform/plib035/inc/plib035_gpio.h | 832 ++ platform/plib035/inc/plib035_i2c.h | 548 + platform/plib035/inc/plib035_mflash.h | 327 + platform/plib035/inc/plib035_pmu.h | 162 + platform/plib035/inc/plib035_pwm.h | 2038 +++ platform/plib035/inc/plib035_qep.h | 1246 ++ platform/plib035/inc/plib035_rcu.h | 955 ++ platform/plib035/inc/plib035_spi.h | 491 + platform/plib035/inc/plib035_tmr.h | 245 + platform/plib035/inc/plib035_uart.h | 606 + platform/plib035/inc/plib035_version.h | 44 + platform/plib035/inc/plib035_wdt.h | 191 + platform/plib035/src/plib035_adc.c | 167 + platform/plib035/src/plib035_can.c | 70 + platform/plib035/src/plib035_dma.c | 209 + platform/plib035/src/plib035_ecap.c | 191 + platform/plib035/src/plib035_gpio.c | 212 + platform/plib035/src/plib035_i2c.c | 98 + platform/plib035/src/plib035_mflash.c | 163 + platform/plib035/src/plib035_pmu.c | 70 + platform/plib035/src/plib035_pwm.c | 346 + platform/plib035/src/plib035_qep.c | 187 + platform/plib035/src/plib035_rcu.c | 523 + platform/plib035/src/plib035_spi.c | 110 + platform/plib035/src/plib035_tmr.c | 100 + platform/plib035/src/plib035_uart.c | 151 + platform/plib035/src/plib035_wdt.c | 70 + platform/retarget/retarget.c | 179 + platform/retarget/retarget_conf.c | 108 + platform/retarget/retarget_conf.h | 69 + 69 files changed, 40782 insertions(+) create mode 100644 .gitignore create mode 100644 .gitmodules create mode 100644 Core/App/gpio.c create mode 100644 Core/App/gpio.h create mode 100644 Core/App/main.c create mode 100644 Core/App/main.h create mode 100644 Core/App/rcu.c create mode 100644 Core/App/rcu.h create mode 100644 Core/App/vk035_it.c create mode 100644 Core/Config/SEGGER_RTT_Conf.h create mode 100644 Core/Config/mylibs_config.h create mode 100644 Core/Config/mylibs_include.h create mode 160000 Core/ExtendedLibs create mode 100644 Listings/Firmware.map create mode 100644 Listings/startup_k1921vk035.lst create mode 100644 Listings/template.map create mode 100644 Template.uvoptx create mode 100644 Template.uvprojx create mode 100644 platform/CMSIS/Core/Include/cmsis_armcc.h create mode 100644 platform/CMSIS/Core/Include/cmsis_armclang.h create mode 100644 platform/CMSIS/Core/Include/cmsis_cmcpp.h create mode 100644 platform/CMSIS/Core/Include/cmsis_compiler.h create mode 100644 platform/CMSIS/Core/Include/cmsis_gcc.h create mode 100644 platform/CMSIS/Core/Include/cmsis_iccarm.h create mode 100644 platform/CMSIS/Core/Include/cmsis_version.h create mode 100644 platform/CMSIS/Core/Include/core_cm4.h create mode 100644 platform/CMSIS/Core/Include/mpu_armv7.h create mode 100644 platform/Device/NIIET/K1921VK035/Include/K1921VK035.h create mode 100644 platform/Device/NIIET/K1921VK035/Include/system_K1921VK035.h create mode 100644 platform/Device/NIIET/K1921VK035/Source/ARM/startup_K1921VK035.s create mode 100644 platform/Device/NIIET/K1921VK035/Source/system_K1921VK035.c create mode 100644 platform/Device/NIIET/K1921VK035/РП_1921ВК035_201219.pdf create mode 100644 platform/plib035/inc/plib035.h create mode 100644 platform/plib035/inc/plib035_adc.h create mode 100644 platform/plib035/inc/plib035_assert.h create mode 100644 platform/plib035/inc/plib035_can.h create mode 100644 platform/plib035/inc/plib035_conf.h create mode 100644 platform/plib035/inc/plib035_dma.h create mode 100644 platform/plib035/inc/plib035_ecap.h create mode 100644 platform/plib035/inc/plib035_gpio.h create mode 100644 platform/plib035/inc/plib035_i2c.h create mode 100644 platform/plib035/inc/plib035_mflash.h create mode 100644 platform/plib035/inc/plib035_pmu.h create mode 100644 platform/plib035/inc/plib035_pwm.h create mode 100644 platform/plib035/inc/plib035_qep.h create mode 100644 platform/plib035/inc/plib035_rcu.h create mode 100644 platform/plib035/inc/plib035_spi.h create mode 100644 platform/plib035/inc/plib035_tmr.h create mode 100644 platform/plib035/inc/plib035_uart.h create mode 100644 platform/plib035/inc/plib035_version.h create mode 100644 platform/plib035/inc/plib035_wdt.h create mode 100644 platform/plib035/src/plib035_adc.c create mode 100644 platform/plib035/src/plib035_can.c create mode 100644 platform/plib035/src/plib035_dma.c create mode 100644 platform/plib035/src/plib035_ecap.c create mode 100644 platform/plib035/src/plib035_gpio.c create mode 100644 platform/plib035/src/plib035_i2c.c create mode 100644 platform/plib035/src/plib035_mflash.c create mode 100644 platform/plib035/src/plib035_pmu.c create mode 100644 platform/plib035/src/plib035_pwm.c create mode 100644 platform/plib035/src/plib035_qep.c create mode 100644 platform/plib035/src/plib035_rcu.c create mode 100644 platform/plib035/src/plib035_spi.c create mode 100644 platform/plib035/src/plib035_tmr.c create mode 100644 platform/plib035/src/plib035_uart.c create mode 100644 platform/plib035/src/plib035_wdt.c create mode 100644 platform/retarget/retarget.c create mode 100644 platform/retarget/retarget_conf.c create mode 100644 platform/retarget/retarget_conf.h diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..8e895dc --- /dev/null +++ b/.gitignore @@ -0,0 +1,49 @@ +# ---> uVision +# git ignore file for Keil µVision Project + +# Project User Settings +*.uvguix.* + +# Listing Files +*.i +*.lst +*.m51 +*.m66 +*.map + +# Object Files +*.axf +*.b[0-2][0-9] +*.b3[0-1] +*.bak +*.build_log.htm +*.crf +*.d +*.dep +*.elf +*.htm +*.iex +*.lnp +*.o +*.obj +*.sbr + +# Firmware Files +*.bin +*.h86 +*.hex + +# Build Files +*.bat + +# Debugger Files +*.ini +*.scvd + +# JLink Files +JLinkLog.txt +JLinkSettings.ini + +# Other Files + +/Objects/ diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..759cc25 --- /dev/null +++ b/.gitmodules @@ -0,0 +1,4 @@ +[submodule "Core/ExtendedLibs"] + path = Core/ExtendedLibs + url = https://git.arktika.cyou/Razvalyaev/STM32_ExtendedLibs.git + branch = release diff --git a/Core/App/gpio.c b/Core/App/gpio.c new file mode 100644 index 0000000..8c8f454 --- /dev/null +++ b/Core/App/gpio.c @@ -0,0 +1,68 @@ +/*============================================================================== + * Инициализация портов с использованием бибилотеки PLIB035 + *------------------------------------------------------------------------------ + * ЦНИИ СЭТ, Разваляев Алексей + *============================================================================== + * Конфигурация портов настраивается в gpio.h + * ЦНИИ СЭТ + *============================================================================== + */ + +//-- Includes ------------------------------------------------------------------ +#include "gpio.h" + +//-- Defines ------------------------------------------------------------------- + +//-- Peripheral init functions ------------------------------------------------- +void gpio_init(void) +{ + RCU_AHBClkCmd(RCU_AHBClk_GPIOA, ENABLE); + RCU_AHBRstCmd(RCU_AHBRst_GPIOA, ENABLE); + + /* Сброс пинов */ + GPIO_DeInit(GPIOA); + GPIO_DeInit(GPIOB); + + // Инициализируем порт A + for (int i = 0; i < sizeof(gpioa_config) / sizeof(gpioa_config[0]); i++) + { + GPIO_Init(GPIOA, &gpioa_config[i]); + } + + // Инициализируем порт B + for (int i = 0; i < sizeof(gpiob_config) / sizeof(gpiob_config[0]); i++) + { + GPIO_Init(GPIOB, &gpiob_config[i]); + } + + + + + + + + + +// GPIO_StructInit(&gpio_init); +// gpio_init.Digital = ENABLE; +// GPIO_Init(GPIOA, &gpio_init); +// GPIO_Init(GPIOB, &gpio_init); +// +// /* Инициализация выходных пинов Пуш-Пулл */ +// gpio_init.Out = ENABLE; +// gpio_init.OutMode = GPIO_OutMode_PP; +// +// gpio_init.Pin = GPIO_OUT_PP_PA_PINS; +// GPIO_Init(GPIOA, &gpio_init); +// gpio_init.Pin = GPIO_OUT_PP_PB_PINS; +// GPIO_Init(GPIOB, &gpio_init); +// +// /* Инициализация выходных пинов Открытый сток */ +// gpio_init.Out = ENABLE; +// gpio_init.OutMode = GPIO_OutMode_OD; +// +// gpio_init.Pin = GPIO_OUT_OD_PA_PINS; +// GPIO_Init(GPIOA, &gpio_init); +// gpio_init.Pin = GPIO_OUT_OD_PB_PINS; +// GPIO_Init(GPIOB, &gpio_init); +} diff --git a/Core/App/gpio.h b/Core/App/gpio.h new file mode 100644 index 0000000..bdc99fc --- /dev/null +++ b/Core/App/gpio.h @@ -0,0 +1,149 @@ +/*============================================================================== + * Конфигурация портов с использованием бибилотеки PLIB035 + *------------------------------------------------------------------------------ + * ЦНИИ СЭТ, Разваляев Алексей + *============================================================================== + * Реализация функций инициализации портов находится в gpio.c + * ЦНИИ СЭТ + *============================================================================== + */ +#ifndef __GPIO_H +#define __GPIO_H +//-- Includes ------------------------------------------------------------------ +#include "main.h" + +//-- Defines ------------------------------------------------------------------- +// Дефайны для режима пина OutEnable, AltFuncEnable, DigitalEnable +#define GPIO_PinMode_Unused DISABLE, DISABLE, DISABLE +#define GPIO_PinMode_Input DISABLE, DISABLE, ENABLE +#define GPIO_PinMode_Output ENABLE, DISABLE, ENABLE +#define GPIO_PinMode_AltFunc DISABLE, ENABLE, ENABLE +//#define GPIO_PinMode_Analog DISABLE, DISABLE, DISABLE + + + + +static GPIO_Init_TypeDef gpioa_config[] = { + // Пин, Режим, Выходной режим, Входной режим, Подтяжка, Нагрузка/Скорость + { GPIO_Pin_0, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_1, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_2, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_3, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_4, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_5, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_6, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_7, GPIO_PinMode_Output, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_8, GPIO_PinMode_Output, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_9, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_10, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_11, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_12, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_13, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_14, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_15, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, +}; + +static GPIO_Init_TypeDef gpiob_config[] = { + { GPIO_Pin_0, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_1, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_2, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_3, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_4, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_5, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_6, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_7, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_8, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_9, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_10, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_11, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_12, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_13, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_14, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, + { GPIO_Pin_15, GPIO_PinMode_Unused, GPIO_OutMode_PP, GPIO_InMode_Schmitt, GPIO_PullMode_Disable, GPIO_DriveMode_HighFast }, +}; + + + + + + + + +// Другой вариант +//#define GPIO_OUT_PP_PA_PINS /* GPIO_Pin_0 | */ \ +// /* GPIO_Pin_1 | */ \ +// /* GPIO_Pin_2 | */ \ +// /* GPIO_Pin_3 | */ \ +// /* GPIO_Pin_4 | */ \ +// /* GPIO_Pin_5 | */ \ +// /* GPIO_Pin_6 | */ \ +// GPIO_Pin_7 | \ +// GPIO_Pin_8 | \ +// /* GPIO_Pin_9 | */ \ +// /* GPIO_Pin_10 | */ \ +// /* GPIO_Pin_11 | */ \ +// /* GPIO_Pin_12 | */ \ +// /* GPIO_Pin_13 | */ \ +// /* GPIO_Pin_14 | */ \ +// /* GPIO_Pin_15 | */ \ +// 0 + +//#define GPIO_OUT_PP_PB_PINS /* GPIO_Pin_0 | */ \ +// /* GPIO_Pin_1 | */ \ +// /* GPIO_Pin_2 | */ \ +// /* GPIO_Pin_3 | */ \ +// /* GPIO_Pin_4 | */ \ +// /* GPIO_Pin_5 | */ \ +// /* GPIO_Pin_6 | */ \ +// /* GPIO_Pin_7 | */ \ +// /* GPIO_Pin_8 | */ \ +// /* GPIO_Pin_9 | */ \ +// /* GPIO_Pin_10 | */ \ +// /* GPIO_Pin_11 | */ \ +// /* GPIO_Pin_12 | */ \ +// /* GPIO_Pin_13 | */ \ +// /* GPIO_Pin_14 | */ \ +// /* GPIO_Pin_15 | */ \ +// 0 +// +// +//#define GPIO_OUT_OD_PA_PINS /* GPIO_Pin_0 | */ \ +// /* GPIO_Pin_1 | */ \ +// /* GPIO_Pin_2 | */ \ +// /* GPIO_Pin_3 | */ \ +// /* GPIO_Pin_4 | */ \ +// /* GPIO_Pin_5 | */ \ +// /* GPIO_Pin_6 | */ \ +// /* GPIO_Pin_7 | */ \ +// /* GPIO_Pin_8 | */ \ +// /* GPIO_Pin_9 | */ \ +// /* GPIO_Pin_10 | */ \ +// /* GPIO_Pin_11 | */ \ +// /* GPIO_Pin_12 | */ \ +// /* GPIO_Pin_13 | */ \ +// /* GPIO_Pin_14 | */ \ +// /* GPIO_Pin_15 | */ \ +// 0 +// +//#define GPIO_OUT_OD_PB_PINS /* GPIO_Pin_0 | */ \ +// /* GPIO_Pin_1 | */ \ +// /* GPIO_Pin_2 | */ \ +// /* GPIO_Pin_3 | */ \ +// /* GPIO_Pin_4 | */ \ +// /* GPIO_Pin_5 | */ \ +// /* GPIO_Pin_6 | */ \ +// /* GPIO_Pin_7 | */ \ +// /* GPIO_Pin_8 | */ \ +// /* GPIO_Pin_9 | */ \ +// /* GPIO_Pin_10 | */ \ +// /* GPIO_Pin_11 | */ \ +// /* GPIO_Pin_12 | */ \ +// /* GPIO_Pin_13 | */ \ +// /* GPIO_Pin_14 | */ \ +// /* GPIO_Pin_15 | */ \ +// 0 + +//-- Exported functions prototypes --------------------------------------------- +void gpio_init(void); + +#endif /*__GPIO_H*/ diff --git a/Core/App/main.c b/Core/App/main.c new file mode 100644 index 0000000..5849db3 --- /dev/null +++ b/Core/App/main.c @@ -0,0 +1,68 @@ +/*============================================================================== + * Шаблон проекта для К1921ВК035 с использованием бибилотеки PLIB035 + *------------------------------------------------------------------------------ + * НИИЭТ, Богдан Колбов + *============================================================================== + * ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ ПРЕДОСТАВЛЯЕТСЯ «КАК ЕСТЬ», БЕЗ КАКИХ-ЛИБО + * ГАРАНТИЙ, ЯВНО ВЫРАЖЕННЫХ ИЛИ ПОДРАЗУМЕВАЕМЫХ, ВКЛЮЧАЯ ГАРАНТИИ ТОВАРНОЙ + * ПРИГОДНОСТИ, СООТВЕТСТВИЯ ПО ЕГО КОНКРЕТНОМУ НАЗНАЧЕНИЮ И ОТСУТСТВИЯ + * НАРУШЕНИЙ, НО НЕ ОГРАНИЧИВАЯСЬ ИМИ. ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ + * ПРЕДНАЗНАЧЕНО ДЛЯ ОЗНАКОМИТЕЛЬНЫХ ЦЕЛЕЙ И НАПРАВЛЕНО ТОЛЬКО НА + * ПРЕДОСТАВЛЕНИЕ ДОПОЛНИТЕЛЬНОЙ ИНФОРМАЦИИ О ПРОДУКТЕ, С ЦЕЛЬЮ СОХРАНИТЬ ВРЕМЯ + * ПОТРЕБИТЕЛЮ. НИ В КАКОМ СЛУЧАЕ АВТОРЫ ИЛИ ПРАВООБЛАДАТЕЛИ НЕ НЕСУТ + * ОТВЕТСТВЕННОСТИ ПО КАКИМ-ЛИБО ИСКАМ, ЗА ПРЯМОЙ ИЛИ КОСВЕННЫЙ УЩЕРБ, ИЛИ + * ПО ИНЫМ ТРЕБОВАНИЯМ, ВОЗНИКШИМ ИЗ-ЗА ИСПОЛЬЗОВАНИЯ ПРОГРАММНОГО ОБЕСПЕЧЕНИЯ + * ИЛИ ИНЫХ ДЕЙСТВИЙ С ПРОГРАММНЫМ ОБЕСПЕЧЕНИЕМ. + * + * 2018 АО "НИИЭТ" + *============================================================================== + */ + +//-- Includes ------------------------------------------------------------------ +#include "main.h" +#include "rcu.h" +#include "gpio.h" + +//-- Defines ------------------------------------------------------------------- + +//-- Peripheral init functions ------------------------------------------------- +void periph_init() +{ + SystemCoreClockUpdate(); + sysclk_init(); + gpio_init(); + retarget_init(); + printf("\nAll peripherals inited, SYSCLK = %3d MHz\n", (int)(SystemCoreClock / 1E6)); +} + +//-- Main ---------------------------------------------------------------------- +int main() +{ + periph_init(); + + while (1) { + + }; + //return 0; +} + + + + +//-- Assert -------------------------------------------------------------------- +void Error_Handler(void) +{ + __disable_irq(); + while (1) + { + } +} + +#if defined USE_FULL_ASSERT +void assert_failed(uint8_t* file, uint32_t line) +{ + printf("Assert failed: file %s on line %d\n", file, (int)line); + while (1) { + }; +} +#endif /* USE_FULL_ASSERT */ diff --git a/Core/App/main.h b/Core/App/main.h new file mode 100644 index 0000000..0962252 --- /dev/null +++ b/Core/App/main.h @@ -0,0 +1,35 @@ +/*============================================================================== + * Шаблон проекта для К1921ВК035 с использованием бибилотеки PLIB035 + *------------------------------------------------------------------------------ + * НИИЭТ, Богдан Колбов + *============================================================================== + * ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ ПРЕДОСТАВЛЯЕТСЯ «КАК ЕСТЬ», БЕЗ КАКИХ-ЛИБО + * ГАРАНТИЙ, ЯВНО ВЫРАЖЕННЫХ ИЛИ ПОДРАЗУМЕВАЕМЫХ, ВКЛЮЧАЯ ГАРАНТИИ ТОВАРНОЙ + * ПРИГОДНОСТИ, СООТВЕТСТВИЯ ПО ЕГО КОНКРЕТНОМУ НАЗНАЧЕНИЮ И ОТСУТСТВИЯ + * НАРУШЕНИЙ, НО НЕ ОГРАНИЧИВАЯСЬ ИМИ. ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ + * ПРЕДНАЗНАЧЕНО ДЛЯ ОЗНАКОМИТЕЛЬНЫХ ЦЕЛЕЙ И НАПРАВЛЕНО ТОЛЬКО НА + * ПРЕДОСТАВЛЕНИЕ ДОПОЛНИТЕЛЬНОЙ ИНФОРМАЦИИ О ПРОДУКТЕ, С ЦЕЛЬЮ СОХРАНИТЬ ВРЕМЯ + * ПОТРЕБИТЕЛЮ. НИ В КАКОМ СЛУЧАЕ АВТОРЫ ИЛИ ПРАВООБЛАДАТЕЛИ НЕ НЕСУТ + * ОТВЕТСТВЕННОСТИ ПО КАКИМ-ЛИБО ИСКАМ, ЗА ПРЯМОЙ ИЛИ КОСВЕННЫЙ УЩЕРБ, ИЛИ + * ПО ИНЫМ ТРЕБОВАНИЯМ, ВОЗНИКШИМ ИЗ-ЗА ИСПОЛЬЗОВАНИЯ ПРОГРАММНОГО ОБЕСПЕЧЕНИЯ + * ИЛИ ИНЫХ ДЕЙСТВИЙ С ПРОГРАММНЫМ ОБЕСПЕЧЕНИЕМ. + * + * 2018 АО "НИИЭТ" + *============================================================================== + */ +#ifndef __MAIN_H +#define __MAIN_H + +//-- Includes ------------------------------------------------------------------ +#include "plib035.h" +#include "retarget_conf.h" +#include "mylibs_include.h" + +//-- Defines ------------------------------------------------------------------- + +//-- Exported variables -------------------------------------------------------- + +//-- Exported functions prototypes --------------------------------------------- +void Error_Handler(void); + +#endif /* __MAIN_H */ diff --git a/Core/App/rcu.c b/Core/App/rcu.c new file mode 100644 index 0000000..6001675 --- /dev/null +++ b/Core/App/rcu.c @@ -0,0 +1,31 @@ +/*============================================================================== + * Инициализация тактирования с использованием бибилотеки PLIB035 + *------------------------------------------------------------------------------ + * ЦНИИ СЭТ, Разваляев Алексей + *============================================================================== + * ЦНИИ СЭТ + *============================================================================== + */ + +//-- Includes ------------------------------------------------------------------ +#include "rcu.h" + +//-- Defines ------------------------------------------------------------------- + +//-- Peripheral init functions ------------------------------------------------- +void sysclk_init(void) +{ + OperationStatus status; + status = RCU_PLL_AutoConfig(MCU_CLOCK_MHZ*__MHZ, OS_Type); + if (status == ERROR) + { + Error_Handler(); + } + SystemCoreClockUpdate(); + RCU_ClkOutConfig(RCU_SysPeriphClk_PLLClk, 1, ENABLE); + RCU_ClkOutCmd(ENABLE); + + /* Прерывание должно быть каждую миллисекунду: + Для тактирования N Гц это каждый N / 1000 тик */ + SysTick_Config(MCU_CLOCK_MHZ*__MHZ/1000); +} diff --git a/Core/App/rcu.h b/Core/App/rcu.h new file mode 100644 index 0000000..4143ba9 --- /dev/null +++ b/Core/App/rcu.h @@ -0,0 +1,22 @@ +/*============================================================================== + * Инициализация тактирования с использованием бибилотеки PLIB035 + *------------------------------------------------------------------------------ + * ЦНИИ СЭТ, Разваляев Алексей + *============================================================================== + * ЦНИИ СЭТ + *============================================================================== + */ +#ifndef __RCU_H +#define __RCU_H +//-- Includes ------------------------------------------------------------------ +#include "main.h" + +//-- Defines ------------------------------------------------------------------- +static RCU_PLL_Ref_TypeDef OS_Type = RCU_PLL_Ref_OSEClk; +#define MCU_CLOCK_MHZ 100 +#define __MHZ 1000000 + +//-- Exported functions prototypes --------------------------------------------- +void sysclk_init(void); + +#endif /*__RCU_H*/ diff --git a/Core/App/vk035_it.c b/Core/App/vk035_it.c new file mode 100644 index 0000000..e756930 --- /dev/null +++ b/Core/App/vk035_it.c @@ -0,0 +1,106 @@ +/*============================================================================== + * Прерывания микроконтроллера 1921ВК035 + *------------------------------------------------------------------------------ + * ЦНИИ СЭТ, Разваляев Алексей + *============================================================================== + * ЦНИИ СЭТ + *============================================================================== + */ + +//-- Includes ------------------------------------------------------------------ +#include "main.h" +#include "plib035.h" +#include "retarget_conf.h" + + +/******************************************************************************/ +/* STM32G4xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32g4xx.s). */ +/******************************************************************************/ + + + + +/******************************************************************************/ +/* Cortex-M4 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + while (1) + { + } +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + while (1) + { + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + while (1) + { + } +} + +/** + * @brief This function handles Prefetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + while (1) + { + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + while (1) + { + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + uwTick++; +} diff --git a/Core/Config/SEGGER_RTT_Conf.h b/Core/Config/SEGGER_RTT_Conf.h new file mode 100644 index 0000000..e386e8b --- /dev/null +++ b/Core/Config/SEGGER_RTT_Conf.h @@ -0,0 +1,429 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 1995 - 2021 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER RTT * Real Time Transfer for embedded targets * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* SEGGER strongly recommends to not make any changes * +* to or modify the source code of this software in order to stay * +* compatible with the RTT protocol and J-Link. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* o Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +* * +* RTT version: 8.10g * +* * +********************************************************************** + +---------------------------END-OF-HEADER------------------------------ +File : SEGGER_RTT_Conf.h +Purpose : Implementation of SEGGER real-time transfer (RTT) which + allows real-time communication on targets which support + debugger memory accesses while the CPU is running. +Revision: $Rev: 24316 $ + +*/ + +#ifndef SEGGER_RTT_CONF_H +#define SEGGER_RTT_CONF_H + +#ifdef __IAR_SYSTEMS_ICC__ + #include +#endif + +/********************************************************************* +* +* Defines, configurable +* +********************************************************************** +*/ + +// +// Take in and set to correct values for Cortex-A systems with CPU cache +// +//#define SEGGER_RTT_CPU_CACHE_LINE_SIZE (32) // Largest cache line size (in bytes) in the current system +//#define SEGGER_RTT_UNCACHED_OFF (0xFB000000) // Address alias where RTT CB and buffers can be accessed uncached +// +// Most common case: +// Up-channel 0: RTT +// Up-channel 1: SystemView +// +#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS + #define SEGGER_RTT_MAX_NUM_UP_BUFFERS (3) // Max. number of up-buffers (T->H) available on this target (Default: 3) +#endif +// +// Most common case: +// Down-channel 0: RTT +// Down-channel 1: SystemView +// +#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS + #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (3) // Max. number of down-buffers (H->T) available on this target (Default: 3) +#endif + +#ifndef BUFFER_SIZE_UP + #define BUFFER_SIZE_UP (4096) // Size of the buffer for terminal output of target, up to host (Default: 1k) +#endif + +#ifndef BUFFER_SIZE_DOWN + #define BUFFER_SIZE_DOWN (16) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16) +#endif + +#ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE + #define SEGGER_RTT_PRINTF_BUFFER_SIZE (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64) +#endif + +#ifndef SEGGER_RTT_MODE_DEFAULT + #define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_TRIM // Mode for pre-initialized terminal channel (buffer 0) +#endif + +/********************************************************************* +* +* RTT memcpy configuration +* +* memcpy() is good for large amounts of data, +* but the overhead is big for small amounts, which are usually stored via RTT. +* With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead. +* +* SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions. +* This is may be required with memory access restrictions, +* such as on Cortex-A devices with MMU. +*/ +#ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP + #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 // 0: Use memcpy/SEGGER_RTT_MEMCPY, 1: Use a simple byte-loop +#endif +// +// Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets +// +//#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__)) +// #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) SEGGER_memcpy((pDest), (pSrc), (NumBytes)) +//#endif + +// +// Target is not allowed to perform other RTT operations while string still has not been stored completely. +// Otherwise we would probably end up with a mixed string in the buffer. +// If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here. +// +// SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4. +// Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches. +// When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly. +// (Higher priority = lower priority number) +// Default value for embOS: 128u +// Default configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +// In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are implemented in NVIC +// or define SEGGER_RTT_LOCK() to completely disable interrupts. +// +#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20) +#endif + +/********************************************************************* +* +* RTT lock configuration for SEGGER Embedded Studio, +* Rowley CrossStudio and GCC +*/ +#if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || defined(__clang__)) && !defined (__CC_ARM) && !defined(WIN32)) + #if (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs %0, primask \n\t" \ + "movs r1, #1 \n\t" \ + "msr primask, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("msr primask, %0 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : \ + ); \ + } + #elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs %0, basepri \n\t" \ + "mov r1, %1 \n\t" \ + "msr basepri, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("msr basepri, %0 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : \ + ); \ + } + + #elif (defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7R__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs r1, CPSR \n\t" \ + "mov %0, r1 \n\t" \ + "orr r1, r1, #0xC0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ + "mrs r1, CPSR \n\t" \ + "bic r1, r1, #0xC0 \n\t" \ + "and r0, r0, #0xC0 \n\t" \ + "orr r1, r1, r0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : "r0", "r1", "cc" \ + ); \ + } + #elif defined(__riscv) || defined(__riscv_xlen) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("csrr %0, mstatus \n\t" \ + "csrci mstatus, 8 \n\t" \ + "andi %0, %0, 8 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("csrr a1, mstatus \n\t" \ + "or %0, %0, a1 \n\t" \ + "csrs mstatus, %0 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : "a1" \ + ); \ + } + #else + #define SEGGER_RTT_LOCK() + #define SEGGER_RTT_UNLOCK() + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration for IAR EWARM +*/ +#ifdef __ICCARM__ + #if (defined (__ARM6M__) && (__CORE__ == __ARM6M__)) || \ + (defined (__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_PRIMASK(); \ + __set_PRIMASK(1); + + #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ + } + #elif (defined (__ARM7EM__) && (__CORE__ == __ARM7EM__)) || \ + (defined (__ARM7M__) && (__CORE__ == __ARM7M__)) || \ + (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) || \ + (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_BASEPRI(); \ + __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); + + #define SEGGER_RTT_UNLOCK() __set_BASEPRI(_SEGGER_RTT__LockState); \ + } + #elif (defined (__ARM7A__) && (__CORE__ == __ARM7A__)) || \ + (defined (__ARM7R__) && (__CORE__ == __ARM7R__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs r1, CPSR \n\t" \ + "mov %0, r1 \n\t" \ + "orr r1, r1, #0xC0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ + "mrs r1, CPSR \n\t" \ + "bic r1, r1, #0xC0 \n\t" \ + "and r0, r0, #0xC0 \n\t" \ + "orr r1, r1, r0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : "r0", "r1", "cc" \ + ); \ + } + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration for IAR RX +*/ +#ifdef __ICCRX__ + #define SEGGER_RTT_LOCK() { \ + unsigned long _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_interrupt_state(); \ + __disable_interrupt(); + + #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ + } +#endif + +/********************************************************************* +* +* RTT lock configuration for IAR RL78 +*/ +#ifdef __ICCRL78__ + #define SEGGER_RTT_LOCK() { \ + __istate_t _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_interrupt_state(); \ + __disable_interrupt(); + + #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ + } +#endif + +/********************************************************************* +* +* RTT lock configuration for KEIL ARM +*/ +#ifdef __CC_ARM + #if (defined __TARGET_ARCH_6S_M) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + register unsigned char _SEGGER_RTT__PRIMASK __asm( "primask"); \ + _SEGGER_RTT__LockState = _SEGGER_RTT__PRIMASK; \ + _SEGGER_RTT__PRIMASK = 1u; \ + __schedule_barrier(); + + #define SEGGER_RTT_UNLOCK() _SEGGER_RTT__PRIMASK = _SEGGER_RTT__LockState; \ + __schedule_barrier(); \ + } + #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + register unsigned char BASEPRI __asm( "basepri"); \ + _SEGGER_RTT__LockState = BASEPRI; \ + BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \ + __schedule_barrier(); + + #define SEGGER_RTT_UNLOCK() BASEPRI = _SEGGER_RTT__LockState; \ + __schedule_barrier(); \ + } + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration for TI ARM +*/ +#ifdef __TI_ARM__ + #if defined (__TI_ARM_V6M0__) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_PRIMASK(); \ + __set_PRIMASK(1); + + #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ + } + #elif (defined (__TI_ARM_V7M3__) || defined (__TI_ARM_V7M4__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); + + #define SEGGER_RTT_UNLOCK() _set_interrupt_priority(_SEGGER_RTT__LockState); \ + } + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration for CCRX +*/ +#ifdef __RX + #include + #define SEGGER_RTT_LOCK() { \ + unsigned long _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = get_psw() & 0x010000; \ + clrpsw_i(); + + #define SEGGER_RTT_UNLOCK() set_psw(get_psw() | _SEGGER_RTT__LockState); \ + } +#endif + +/********************************************************************* +* +* RTT lock configuration for embOS Simulation on Windows +* (Can also be used for generic RTT locking with embOS) +*/ +#if defined(WIN32) || defined(SEGGER_RTT_LOCK_EMBOS) + +void OS_SIM_EnterCriticalSection(void); +void OS_SIM_LeaveCriticalSection(void); + +#define SEGGER_RTT_LOCK() { \ + OS_SIM_EnterCriticalSection(); + +#define SEGGER_RTT_UNLOCK() OS_SIM_LeaveCriticalSection(); \ + } +#endif + +/********************************************************************* +* +* RTT lock configuration fallback +*/ +#ifndef SEGGER_RTT_LOCK + #define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts) +#endif + +#ifndef SEGGER_RTT_UNLOCK + #define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state) +#endif + +#endif +/*************************** End of file ****************************/ diff --git a/Core/Config/mylibs_config.h b/Core/Config/mylibs_config.h new file mode 100644 index 0000000..37c6392 --- /dev/null +++ b/Core/Config/mylibs_config.h @@ -0,0 +1,132 @@ +/** +************************************************************************** +* @file mylibs_config.h +* @brief Конфигурации для библиотек MyLibs +************************************************************************** +* @defgroup MYLIBS_CONFIG Configs +* @ingroup MYLIBS_ALL +* @brief Конфигурации для библиотек MyLibs +* @{ +*************************************************************************/ +#ifndef __MYLIBS_CONFIG_H_ +#define __MYLIBS_CONFIG_H_ +#include "plib035.h" +#include "retarget_conf.h" + +// user includes + +/** + * @addtogroup TRACE_CONFIG Trace configs + * @ingroup MYLIBS_CONFIG + * @brief Конфигурация трекеров и трассировки + * @{ + */ + +#define TRACKERS_ENABLE ///< Включить трекеры +#define SERIAL_TRACE_ENABLE ///< Включить serial трассировку +#define RTT_TRACE_ENABLE ///< Включить serial трассировку через RTT +#define SWO_TRACE_ENABLE ///< Включить serial трассировку через SWO +/** + * @brief Уровень log serial трассировки @ref log_printf + * - LOG_LEVEL == 0 - логирование отключено (макрос пустой) + * - LOG_LEVEL == 1 - выводится время и TAG + * - LOG_LEVEL >= 2 - выводится время, TAG, имя файла и номер строки + */ +#define LOG_LEVEL 1 + +#define RTT_FLASH_BUFFER_SIZE 1024 ///< Размер буфера RTT в Flash +#define RTT_FLASH_SECTOR FLASH_SECTOR_11 ///< Сектор FLASH куда положится RTT буфер +#define RTT_FLASH_SECTOR_START 0x080E0000 ///< Начало сектора RTT_FLASH_SECTOR +#define RTT_FLASH_SECTOR_END 0x080FFFFF ///< Конец сектора RTT_FLASH_SECTOR + + +#define HARDFAULT_SERIAL_TRACE ///< Включить обработку и serial трассировку Hardfault +#define HF_RTT_TAG_BASE 0xDEAD0000 ///< базовый тег для HardFault +#define HF_RTT_TAIL_SIZE RTT_FLASH_BUFFER_SIZE ///< Размер буфера RTT, который сохранится при Hardfault +#define HF_STACK_DUMP_WORDS 32 ///< Сколько слов стека будет проанализировано во время Hardfault +#define HF_FLASH_ADDR ((uint32_t)0x080FF000) ///< Адрес FLASH куда положится RTT буфер +#define HF_RAM_END 0x20030000 ///< Конец RAM памяти (чтобы во время анализа стека не выйти за пределы) + +#define GPIO_TRACE_ENABLE ///< Включить GPIO трассировку + +/** TRACE_CONFIG + * @} + */ + + +/** + * @addtogroup FILTER_CONFIG Filter configs + * @ingroup MYLIBS_CONFIG + * @brief Конфигурация фильтров + * @{ + */ + + +#define FILTERS_ENABLE ///< Включить библиотеку фильтров +//#define FILTER_MEDIAN_MAX_SIZE ///< Максимальный размер окна медианного фильтра (по умолчанию 5) +//#define FILTER_AVERAGE_MAX_SIZE ///< Максимальный размер окна усредняющего фильтра (по умолчанию 8) +//#define FILTER_POLY_MAX_ORDER ///< Максимальный порядок полинома (по умолчанию 4) +#define FILTERS_DISABLE_MOVING_AVERAGE +/** GEN_CONFIG + * @} + */ + + +/** + * @addtogroup GEN_CONFIG Genetic configs + * @ingroup MYLIBS_CONFIG + * @brief Конфигурация генетического алгоритма обучения + * @{ + */ + +#define GEN_OPTIMIZATION_ENABLE ///< Включить оптимизацию параметров +#define GEN_MAX_PARAMS 20 ///< Максимальное количество параметров +#define GEN_MAX_CANDIDATES 100 ///< Максимальное количество кандидатов для обучения + +/** GEN_CONFIG + * @} + */ + + +/** + * @addtogroup GEN_CONFIG Genetic configs + * @ingroup MYLIBS_CONFIG + * @brief Конфигурация генетического алгоритма обучения + * @{ + */ + + +#define BENCH_TIME_ENABLE ///< Включить бенч времени +#define BENCH_TIME_MAX_CHANNELS 16 ///< Максимальное количество каналов измерения + +/** GEN_CONFIG + * @} + */ + + + +/** + * @addtogroup LIBS_CONFIG Libraries configs + * @ingroup MYLIBS_CONFIG + * @brief Подключение различных модулей библиотеки + * @{ + */ +extern uint32_t uwTick; +#define local_time() (uwTick) ///< Локальное время + +#define INCLUDE_FILTERS ///< Подключить библиотеку с фильтрами +#define INCLUDE_GEN_OPTIMIZER ///< Подключить библиотеку для оптимизации параметров +#define INCLUDE_BIT_ACCESS_LIB ///< Подключить библиотеку с typedef с битовыми полями +#define INCLUDE_TRACKERS_LIB ///< Подключить библиотеку с трекерами +#define INCLUDE_TRACE_LIB ///< Подключить библиотеку с трейсами +#define INCLUDE_BENCH_TIME ///< Подключить библиотеку с бенчмарком времени +//#define FREERTOS_DELAY ///< Использовать FreeRTOS задержку, вместо HAL + +/** LIBS_CONFIG + * @} + */ + +/** MYLIBS_CONFIG + * @} + */ +#endif //__MYLIBS_CONFIG_H_ diff --git a/Core/Config/mylibs_include.h b/Core/Config/mylibs_include.h new file mode 100644 index 0000000..a0e9ced --- /dev/null +++ b/Core/Config/mylibs_include.h @@ -0,0 +1,141 @@ +/** +************************************************************************** +* @file mylibs_include.h +* @brief Заголочный файл для всех библиотек +************************************************************************** +* @details +Здесь нужно собрать библиотеки и дефайны, которые должны быть видны во всем проекте, +чтобы не подключать 100 инклюдов в каждом ".c" файле +************************************************************************** +* @defgroup MYLIBS_ALL My Libs +* @brief Все используемые MyLibs библиотеки +* @details +Для подключения библиотеки необходимо: +- Сконфигурировать mylibs_config.h: + - Подключить заголовочный файл HAL библиотеки конкретного МК (напр. stm32f4xx_hal.h) + - Подключить другие заголовочные файлы которые общие для всего проекта и должны быть видны + - Подключить mylibs_include.h туда, где необходим доступ к библиотекам. + +*************************************************************************/ +#ifndef __MYLIBS_INCLUDE_H_ +#define __MYLIBS_INCLUDE_H_ + +#include "mylibs_defs.h" + + +#ifdef ARM_MATH_CM4 + #include "arm_math.h" +#else + #include "math.h" +#endif + + +#ifdef INCLUDE_BIT_ACCESS_LIB +#include "bit_access.h" +#endif + +#ifdef INCLUDE_TRACKERS_LIB +#include "trackers.h" +#else + #define TrackerTypeDef(num_user_vars) void * + #define num_of_usercnts(_user_) 0 + #define assert_tracecnt(_cntstruct_, _uservarnumb_) 0 + #define if_assert_usertracker(_cntstruct_, _uservarnumb_) if(0) + #define tern_assert_usertracker(_cntstruct_, _uservarnumb_) 0 + #define TrackerGet_Ok(_cntstruct_) dummy + #define TrackerGet_Err(_cntstruct_) dummy + #define TrackerGet_Warn(_cntstruct_) dummy + #define TrackerGet_User(_cntstruct_, _uservarnumb_) dummy + #define TrackerCnt_Ok(_cntstruct_) + #define TrackerCnt_Err(_cntstruct_) + #define TrackerCnt_Warn(_cntstruct_) + #define TrackerCnt_User(_cntstruct_, _uservarnumb_) + #define TrackerWrite_User(_cntstruct_, _uservarnumb_, _val_) + #define TrackerClear_All(_cntstruct_) + #define TrackerClear_Ok(_cntstruct_) + #define TrackerClear_Err(_cntstruct_) + #define TrackerClear_Warn(_cntstruct_) + #define TrackerClear_User(_cntstruct_) + #define TrackerClear_UserAll(_cntstruct_) +#endif + +#ifdef INCLUDE_TRACE_LIB +#include "trace.h" +#else +#define my_printf(...) +#define log_printf(TAG, fmt, ...) +#define TRACE_GPIO_SET(_gpio_,_pin_) +#define TRACE_GPIO_RESET(_gpio_,_pin_) +#define RTT_FlashPrepare(...) +#define RTT_EraseFlash(...) 0 +#define RTT_SaveToFlash(...) 0 +#define RTT_ReadFromFlash(...) 0 +#define HF_CheckRecovered(...) 0 +#define HF_HandleFault(...) +#endif + +#ifdef INCLUDE_GEN_OPTIMIZER +#include "gen_optimizer.h" +#else +typedef struct { + uint16_t n_params; + uint16_t n_cand; + uint16_t n_best; + uint16_t iq_mutation; + int32_t loss[0]; + int32_t candidates[0][0]; +} GenOptimizer_t; +#define GenOptimizer_Init(opt, n_params, n_cand, n_best, iq_mutation, start_params) +#define GenOptimizer_Step(opt, params, LossFunc) +#define PARAM_SCALE_Q16(x, min_val, max_val) (x) +#define PARAM_UNSCALE_Q16(q16_val, min_val, max_val) (q16_val) +#endif + + + +#ifdef INCLUDE_BENCH_TIME +#include "bench_time.h" +#else //BENCH_TIME_ENABLE +#define BenchTime_Init() +#define BenchTime_Start(channel, ticks, tick_period) 0 +#define BenchTime_End(channel, ticks) 0 +#define BenchTime_GetMin(channel) 0 +#define BenchTime_GetMax(channel) 0 +#define BenchTime_GetAverage(channel) 0 +#define BenchTime_GetCount(channel) 0 +#define BenchTime_GetLast(channel) 0 +#define BenchTime_ResetStats(channel) +#endif //BENCH_TIME_ENABLE + +#ifdef INCLUDE_FILTERS +#include "filters.h" +#else //INCLUDE_FILTERS +#endif //INCLUDE_FILTERS + +#ifdef INCLUDE_GENERAL_PERIPH_LIBS + +#include "__general_flash.h" +#include "general_gpio.h" +#ifdef HAL_SPI_MODULE_ENABLED +#include "general_spi.h" +#endif +#ifdef HAL_UART_MODULE_ENABLED +#include "general_uart.h" +#endif +#ifdef HAL_TIM_MODULE_ENABLED +#include "general_tim.h" +#endif + +#endif //INCLUDE_GENERAL_PERIPH_LIBS + + + + +/////////////////////////---USER SETTINGS---///////////////////////// +// user includes + +// user settings +/////////////////////////---USER SETTINGS---///////////////////////// + + +#endif // __MYLIBS_INCLUDE_H_ diff --git a/Core/ExtendedLibs b/Core/ExtendedLibs new file mode 160000 index 0000000..0031156 --- /dev/null +++ b/Core/ExtendedLibs @@ -0,0 +1 @@ +Subproject commit 0031156d5c898acb87ab3909260e82c95e1eb21a diff --git a/Listings/Firmware.map b/Listings/Firmware.map new file mode 100644 index 0000000..42cbdde --- /dev/null +++ b/Listings/Firmware.map @@ -0,0 +1,1953 @@ +Component: ARM Compiler 5.06 update 7 (build 960) Tool: armlink [4d3601] + +============================================================================== + +Section Cross References + + main.o(i.GenOptimizer_Init) refers to rand.o(.text) for srand + main.o(i.GenOptimizer_Init) refers to rand.o(.emb_text) for rand + main.o(i.GenOptimizer_Init) refers to system_k1921vk035.o(.data) for uwTick + main.o(i.GenOptimizer_Step) refers to qsortnoex.o(.text) for qsort + main.o(i.GenOptimizer_Step) refers to rand.o(.emb_text) for rand + main.o(i.GenOptimizer_Step) refers to main.o(.data) for g_sort_opt + main.o(i.GenOptimizer_Step) refers to main.o(i.cmp_idx) for cmp_idx + main.o(i.assert_failed) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + main.o(i.assert_failed) refers to _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) for _printf_d + main.o(i.assert_failed) refers to _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) for _printf_s + main.o(i.assert_failed) refers to _printf_dec.o(.text) for _printf_int_dec + main.o(i.assert_failed) refers to _printf_str.o(.text) for _printf_str + main.o(i.assert_failed) refers to noretval__2printf.o(.text) for __2printf + main.o(i.cmp_idx) refers to main.o(.data) for g_sort_opt + main.o(i.main) refers to main.o(i.periph_init) for periph_init + main.o(i.periph_init) refers to _printf_pad.o(.text) for _printf_pre_padding + main.o(i.periph_init) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + main.o(i.periph_init) refers to _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) for _printf_d + main.o(i.periph_init) refers to _printf_dec.o(.text) for _printf_int_dec + main.o(i.periph_init) refers to system_k1921vk035.o(i.SystemCoreClockUpdate) for SystemCoreClockUpdate + main.o(i.periph_init) refers to rcu.o(i.sysclk_init) for sysclk_init + main.o(i.periph_init) refers to gpio.o(i.gpio_init) for gpio_init + main.o(i.periph_init) refers to retarget_conf.o(i.retarget_init) for retarget_init + main.o(i.periph_init) refers to dflt_clz.o(x$fpl$dfltu) for __aeabi_ui2d + main.o(i.periph_init) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv + main.o(i.periph_init) refers to dfix.o(x$fpl$dfix) for __aeabi_d2iz + main.o(i.periph_init) refers to noretval__2printf.o(.text) for __2printf + main.o(i.periph_init) refers to system_k1921vk035.o(.data) for SystemCoreClock + gpio.o(i.GenOptimizer_Init) refers to rand.o(.text) for srand + gpio.o(i.GenOptimizer_Init) refers to rand.o(.emb_text) for rand + gpio.o(i.GenOptimizer_Init) refers to system_k1921vk035.o(.data) for uwTick + gpio.o(i.GenOptimizer_Step) refers to qsortnoex.o(.text) for qsort + gpio.o(i.GenOptimizer_Step) refers to rand.o(.emb_text) for rand + gpio.o(i.GenOptimizer_Step) refers to gpio.o(.data) for g_sort_opt + gpio.o(i.GenOptimizer_Step) refers to gpio.o(i.cmp_idx) for cmp_idx + gpio.o(i.RCU_AHBClkCmd) refers to main.o(i.assert_failed) for assert_failed + gpio.o(i.RCU_AHBRstCmd) refers to main.o(i.assert_failed) for assert_failed + gpio.o(i.RCU_AHBRstCmd) refers to gpio.o(i.RCU_AHBClkCmd) for i.RCU_AHBClkCmd + gpio.o(i.cmp_idx) refers to gpio.o(.data) for g_sort_opt + gpio.o(i.gpio_init) refers to gpio.o(i.RCU_AHBClkCmd) for RCU_AHBClkCmd + gpio.o(i.gpio_init) refers to gpio.o(i.RCU_AHBRstCmd) for RCU_AHBRstCmd + gpio.o(i.gpio_init) refers to plib035_gpio.o(i.GPIO_DeInit) for GPIO_DeInit + gpio.o(i.gpio_init) refers to plib035_gpio.o(i.GPIO_Init) for GPIO_Init + gpio.o(i.gpio_init) refers to gpio.o(.data) for gpioa_config + rcu.o(i.GenOptimizer_Init) refers to rand.o(.text) for srand + rcu.o(i.GenOptimizer_Init) refers to rand.o(.emb_text) for rand + rcu.o(i.GenOptimizer_Init) refers to system_k1921vk035.o(.data) for uwTick + rcu.o(i.GenOptimizer_Step) refers to qsortnoex.o(.text) for qsort + rcu.o(i.GenOptimizer_Step) refers to rand.o(.emb_text) for rand + rcu.o(i.GenOptimizer_Step) refers to rcu.o(.data) for g_sort_opt + rcu.o(i.GenOptimizer_Step) refers to rcu.o(i.cmp_idx) for cmp_idx + rcu.o(i.RCU_ClkOutConfig) refers to main.o(i.assert_failed) for assert_failed + rcu.o(i.RCU_ClkOutConfig) refers to rcu.o(i.sysclk_init) for i.sysclk_init + rcu.o(i.cmp_idx) refers to rcu.o(.data) for g_sort_opt + rcu.o(i.sysclk_init) refers to plib035_rcu.o(i.RCU_PLL_AutoConfig) for RCU_PLL_AutoConfig + rcu.o(i.sysclk_init) refers to main.o(i.Error_Handler) for Error_Handler + rcu.o(i.sysclk_init) refers to system_k1921vk035.o(i.SystemCoreClockUpdate) for SystemCoreClockUpdate + rcu.o(i.sysclk_init) refers to rcu.o(i.RCU_ClkOutConfig) for RCU_ClkOutConfig + rcu.o(i.sysclk_init) refers to main.o(i.assert_failed) for assert_failed + rcu.o(i.sysclk_init) refers to rcu.o(.data) for OS_Type + vk035_it.o(i.GenOptimizer_Init) refers to rand.o(.text) for srand + vk035_it.o(i.GenOptimizer_Init) refers to rand.o(.emb_text) for rand + vk035_it.o(i.GenOptimizer_Init) refers to system_k1921vk035.o(.data) for uwTick + vk035_it.o(i.GenOptimizer_Step) refers to qsortnoex.o(.text) for qsort + vk035_it.o(i.GenOptimizer_Step) refers to rand.o(.emb_text) for rand + vk035_it.o(i.GenOptimizer_Step) refers to vk035_it.o(.data) for g_sort_opt + vk035_it.o(i.GenOptimizer_Step) refers to vk035_it.o(i.cmp_idx) for cmp_idx + vk035_it.o(i.SysTick_Handler) refers to system_k1921vk035.o(.data) for uwTick + vk035_it.o(i.cmp_idx) refers to vk035_it.o(.data) for g_sort_opt + segger_rtt.o(i.SEGGER_RTT_AllocDownBuffer) refers to segger_rtt.o(i._DoInit) for _DoInit + segger_rtt.o(i.SEGGER_RTT_AllocDownBuffer) refers to segger_rtt.o(.bss) for _SEGGER_RTT + segger_rtt.o(i.SEGGER_RTT_AllocUpBuffer) refers to segger_rtt.o(i._DoInit) for _DoInit + segger_rtt.o(i.SEGGER_RTT_AllocUpBuffer) refers to segger_rtt.o(.bss) for _SEGGER_RTT + segger_rtt.o(i.SEGGER_RTT_ConfigDownBuffer) refers to segger_rtt.o(i._DoInit) for _DoInit + segger_rtt.o(i.SEGGER_RTT_ConfigDownBuffer) refers to segger_rtt.o(.bss) for _SEGGER_RTT + segger_rtt.o(i.SEGGER_RTT_ConfigUpBuffer) refers to segger_rtt.o(i._DoInit) for _DoInit + segger_rtt.o(i.SEGGER_RTT_ConfigUpBuffer) refers to segger_rtt.o(.bss) for _SEGGER_RTT + segger_rtt.o(i.SEGGER_RTT_GetAvailWriteSpace) refers to segger_rtt.o(i._GetAvailWriteSpace) for _GetAvailWriteSpace + segger_rtt.o(i.SEGGER_RTT_GetAvailWriteSpace) refers to segger_rtt.o(.bss) for _SEGGER_RTT + segger_rtt.o(i.SEGGER_RTT_GetBytesInBuffer) refers to segger_rtt.o(.bss) for _SEGGER_RTT + segger_rtt.o(i.SEGGER_RTT_GetKey) refers to segger_rtt.o(i.SEGGER_RTT_Read) for SEGGER_RTT_Read + segger_rtt.o(i.SEGGER_RTT_HasData) refers to segger_rtt.o(.bss) for _SEGGER_RTT + segger_rtt.o(i.SEGGER_RTT_HasDataUp) refers to segger_rtt.o(.bss) for _SEGGER_RTT + segger_rtt.o(i.SEGGER_RTT_HasKey) refers to segger_rtt.o(i._DoInit) for _DoInit + segger_rtt.o(i.SEGGER_RTT_HasKey) refers to segger_rtt.o(.bss) for _SEGGER_RTT + segger_rtt.o(i.SEGGER_RTT_Init) refers to segger_rtt.o(i._DoInit) for _DoInit + segger_rtt.o(i.SEGGER_RTT_PutChar) refers to segger_rtt.o(i._DoInit) for _DoInit + segger_rtt.o(i.SEGGER_RTT_PutChar) refers to segger_rtt.o(.bss) for _SEGGER_RTT + segger_rtt.o(i.SEGGER_RTT_PutCharSkip) refers to segger_rtt.o(i._DoInit) for _DoInit + segger_rtt.o(i.SEGGER_RTT_PutCharSkip) refers to segger_rtt.o(.bss) for _SEGGER_RTT + segger_rtt.o(i.SEGGER_RTT_PutCharSkipNoLock) refers to segger_rtt.o(.bss) for _SEGGER_RTT + segger_rtt.o(i.SEGGER_RTT_Read) refers to segger_rtt.o(i.SEGGER_RTT_ReadNoLock) for SEGGER_RTT_ReadNoLock + segger_rtt.o(i.SEGGER_RTT_ReadNoLock) refers to segger_rtt.o(i._DoInit) for _DoInit + segger_rtt.o(i.SEGGER_RTT_ReadNoLock) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy + segger_rtt.o(i.SEGGER_RTT_ReadNoLock) refers to segger_rtt.o(.bss) for _SEGGER_RTT + segger_rtt.o(i.SEGGER_RTT_ReadUpBuffer) refers to segger_rtt.o(i.SEGGER_RTT_ReadUpBufferNoLock) for SEGGER_RTT_ReadUpBufferNoLock + segger_rtt.o(i.SEGGER_RTT_ReadUpBufferNoLock) refers to segger_rtt.o(i._DoInit) for _DoInit + segger_rtt.o(i.SEGGER_RTT_ReadUpBufferNoLock) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy + segger_rtt.o(i.SEGGER_RTT_ReadUpBufferNoLock) refers to segger_rtt.o(.bss) for _SEGGER_RTT + segger_rtt.o(i.SEGGER_RTT_SetFlagsDownBuffer) refers to segger_rtt.o(i._DoInit) for _DoInit + segger_rtt.o(i.SEGGER_RTT_SetFlagsDownBuffer) refers to segger_rtt.o(.bss) for _SEGGER_RTT + segger_rtt.o(i.SEGGER_RTT_SetFlagsUpBuffer) refers to segger_rtt.o(i._DoInit) for _DoInit + segger_rtt.o(i.SEGGER_RTT_SetFlagsUpBuffer) refers to segger_rtt.o(.bss) for _SEGGER_RTT + segger_rtt.o(i.SEGGER_RTT_SetNameDownBuffer) refers to segger_rtt.o(i._DoInit) for _DoInit + segger_rtt.o(i.SEGGER_RTT_SetNameDownBuffer) refers to segger_rtt.o(.bss) for _SEGGER_RTT + segger_rtt.o(i.SEGGER_RTT_SetNameUpBuffer) refers to segger_rtt.o(i._DoInit) for _DoInit + segger_rtt.o(i.SEGGER_RTT_SetNameUpBuffer) refers to segger_rtt.o(.bss) for _SEGGER_RTT + segger_rtt.o(i.SEGGER_RTT_SetTerminal) refers to segger_rtt.o(i._DoInit) for _DoInit + segger_rtt.o(i.SEGGER_RTT_SetTerminal) refers to segger_rtt.o(i._WriteBlocking) for _WriteBlocking + segger_rtt.o(i.SEGGER_RTT_SetTerminal) refers to segger_rtt.o(i._GetAvailWriteSpace) for _GetAvailWriteSpace + segger_rtt.o(i.SEGGER_RTT_SetTerminal) refers to segger_rtt.o(i._WriteNoCheck) for _WriteNoCheck + segger_rtt.o(i.SEGGER_RTT_SetTerminal) refers to segger_rtt.o(.bss) for _SEGGER_RTT + segger_rtt.o(i.SEGGER_RTT_SetTerminal) refers to segger_rtt.o(.constdata) for _aTerminalId + segger_rtt.o(i.SEGGER_RTT_SetTerminal) refers to segger_rtt.o(.data) for _ActiveTerminal + segger_rtt.o(i.SEGGER_RTT_TerminalOut) refers to segger_rtt.o(i._DoInit) for _DoInit + segger_rtt.o(i.SEGGER_RTT_TerminalOut) refers to strlen.o(.text) for strlen + segger_rtt.o(i.SEGGER_RTT_TerminalOut) refers to segger_rtt.o(i._GetAvailWriteSpace) for _GetAvailWriteSpace + segger_rtt.o(i.SEGGER_RTT_TerminalOut) refers to segger_rtt.o(i._PostTerminalSwitch) for _PostTerminalSwitch + segger_rtt.o(i.SEGGER_RTT_TerminalOut) refers to segger_rtt.o(i._WriteBlocking) for _WriteBlocking + segger_rtt.o(i.SEGGER_RTT_TerminalOut) refers to segger_rtt.o(.bss) for _SEGGER_RTT + segger_rtt.o(i.SEGGER_RTT_TerminalOut) refers to segger_rtt.o(.data) for _ActiveTerminal + segger_rtt.o(i.SEGGER_RTT_WaitKey) refers to segger_rtt.o(i.SEGGER_RTT_GetKey) for SEGGER_RTT_GetKey + segger_rtt.o(i.SEGGER_RTT_Write) refers to segger_rtt.o(i._DoInit) for _DoInit + segger_rtt.o(i.SEGGER_RTT_Write) refers to segger_rtt.o(i.SEGGER_RTT_WriteNoLock) for SEGGER_RTT_WriteNoLock + segger_rtt.o(i.SEGGER_RTT_Write) refers to segger_rtt.o(.bss) for _SEGGER_RTT + segger_rtt.o(i.SEGGER_RTT_WriteDownBuffer) refers to segger_rtt.o(i._DoInit) for _DoInit + segger_rtt.o(i.SEGGER_RTT_WriteDownBuffer) refers to segger_rtt.o(i.SEGGER_RTT_WriteDownBufferNoLock) for SEGGER_RTT_WriteDownBufferNoLock + segger_rtt.o(i.SEGGER_RTT_WriteDownBuffer) refers to segger_rtt.o(.bss) for _SEGGER_RTT + segger_rtt.o(i.SEGGER_RTT_WriteDownBufferNoLock) refers to segger_rtt.o(i._GetAvailWriteSpace) for _GetAvailWriteSpace + segger_rtt.o(i.SEGGER_RTT_WriteDownBufferNoLock) refers to segger_rtt.o(i._WriteNoCheck) for _WriteNoCheck + segger_rtt.o(i.SEGGER_RTT_WriteDownBufferNoLock) refers to segger_rtt.o(i._WriteBlocking) for _WriteBlocking + segger_rtt.o(i.SEGGER_RTT_WriteDownBufferNoLock) refers to segger_rtt.o(.bss) for _SEGGER_RTT + segger_rtt.o(i.SEGGER_RTT_WriteNoLock) refers to segger_rtt.o(i._GetAvailWriteSpace) for _GetAvailWriteSpace + segger_rtt.o(i.SEGGER_RTT_WriteNoLock) refers to segger_rtt.o(i._WriteNoCheck) for _WriteNoCheck + segger_rtt.o(i.SEGGER_RTT_WriteNoLock) refers to segger_rtt.o(i._WriteBlocking) for _WriteBlocking + segger_rtt.o(i.SEGGER_RTT_WriteNoLock) refers to segger_rtt.o(.bss) for _SEGGER_RTT + segger_rtt.o(i.SEGGER_RTT_WriteSkipNoLock) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy + segger_rtt.o(i.SEGGER_RTT_WriteSkipNoLock) refers to segger_rtt.o(.bss) for _SEGGER_RTT + segger_rtt.o(i.SEGGER_RTT_WriteString) refers to strlen.o(.text) for strlen + segger_rtt.o(i.SEGGER_RTT_WriteString) refers to segger_rtt.o(i.SEGGER_RTT_Write) for SEGGER_RTT_Write + segger_rtt.o(i.SEGGER_RTT_WriteWithOverwriteNoLock) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy + segger_rtt.o(i.SEGGER_RTT_WriteWithOverwriteNoLock) refers to segger_rtt.o(.bss) for _SEGGER_RTT + segger_rtt.o(i._DoInit) refers to rt_memclr_w.o(.text) for __aeabi_memclr4 + segger_rtt.o(i._DoInit) refers to segger_rtt.o(.bss) for _SEGGER_RTT + segger_rtt.o(i._DoInit) refers to segger_rtt.o(.constdata) for _aInitStr + segger_rtt.o(i._PostTerminalSwitch) refers to segger_rtt.o(i._WriteBlocking) for _WriteBlocking + segger_rtt.o(i._PostTerminalSwitch) refers to segger_rtt.o(.constdata) for _aTerminalId + segger_rtt.o(i._WriteBlocking) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy + segger_rtt.o(i._WriteNoCheck) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy + segger_rtt_printf.o(i.SEGGER_RTT_printf) refers to segger_rtt_printf.o(i.SEGGER_RTT_vprintf) for SEGGER_RTT_vprintf + segger_rtt_printf.o(i.SEGGER_RTT_vprintf) refers to segger_rtt_printf.o(i._StoreChar) for _StoreChar + segger_rtt_printf.o(i.SEGGER_RTT_vprintf) refers to segger_rtt_printf.o(i._PrintInt) for _PrintInt + segger_rtt_printf.o(i.SEGGER_RTT_vprintf) refers to segger_rtt_printf.o(i._PrintUnsigned) for _PrintUnsigned + segger_rtt_printf.o(i.SEGGER_RTT_vprintf) refers to segger_rtt.o(i.SEGGER_RTT_Write) for SEGGER_RTT_Write + segger_rtt_printf.o(i._PrintInt) refers to segger_rtt_printf.o(i._StoreChar) for _StoreChar + segger_rtt_printf.o(i._PrintInt) refers to segger_rtt_printf.o(i._PrintUnsigned) for _PrintUnsigned + segger_rtt_printf.o(i._PrintUnsigned) refers to segger_rtt_printf.o(i._StoreChar) for _StoreChar + segger_rtt_printf.o(i._PrintUnsigned) refers to segger_rtt_printf.o(.constdata) for _aV2C + segger_rtt_printf.o(i._StoreChar) refers to segger_rtt.o(i.SEGGER_RTT_Write) for SEGGER_RTT_Write + filters.o(i.FilterAverageInt_Init) refers to filters.o(i.FilterAverageInt_Process) for FilterAverageInt_Process + filters.o(i.FilterAverageInt_Process) refers to llsdiv.o(.text) for __aeabi_ldivmod + filters.o(i.FilterAverage_Init) refers to filters.o(i.FilterAverage_Process) for FilterAverage_Process + filters.o(i.FilterBandPassDerivative_Init) refers to sinf.o(i.__hardfp_sinf) for __hardfp_sinf + filters.o(i.FilterBandPassDerivative_Init) refers to cosf.o(i.__hardfp_cosf) for __hardfp_cosf + filters.o(i.FilterBandPassDerivative_Init) refers to filters.o(i.FilterBandPassDerivative_Process) for FilterBandPassDerivative_Process + filters.o(i.FilterExpInt_Init) refers to filters.o(i.FilterExpInt_Process) for FilterExpInt_Process + filters.o(i.FilterExpInt_Process) refers to llsdiv.o(.text) for __aeabi_ldivmod + filters.o(i.FilterExp_Init) refers to filters.o(i.FilterExp_Process) for FilterExp_Process + filters.o(i.FilterLUTInt_Init) refers to filters.o(i.FilterLUTInt_Process) for FilterLUTInt_Process + filters.o(i.FilterLUTInt_Process) refers to llsdiv.o(.text) for __aeabi_ldivmod + filters.o(i.FilterLUT_Init) refers to filters.o(i.FilterLUT_Process) for FilterLUT_Process + filters.o(i.FilterMedianInt_Init) refers to filters.o(i.FilterMedianInt_Process) for FilterMedianInt_Process + filters.o(i.FilterMedian_Init) refers to filters.o(i.FilterMedian_Process) for FilterMedian_Process + filters.o(i.FilterMedian_Process) refers to rt_memcpy_w.o(.text) for __aeabi_memcpy4 + filters.o(i.FilterMedian_Process) refers to qsortnoex.o(.text) for qsort + filters.o(i.FilterMedian_Process) refers to filters.o(i.Filter_float_compare) for Filter_float_compare + filters.o(i.FilterPolyInt_Init) refers to rt_memcpy_w.o(.text) for __aeabi_memcpy4 + filters.o(i.FilterPolyInt_Init) refers to filters.o(i.FilterPolyInt_Process) for FilterPolyInt_Process + filters.o(i.FilterPolyInt_Process) refers to llsdiv.o(.text) for __aeabi_ldivmod + filters.o(i.FilterPoly_Init) refers to rt_memcpy_w.o(.text) for __aeabi_memcpy4 + filters.o(i.FilterPoly_Init) refers to filters.o(i.FilterPoly_Process) for FilterPoly_Process + filters.o(i.FilterRMSInt_Init) refers to rt_memclr_w.o(.text) for __aeabi_memclr4 + filters.o(i.FilterRMSInt_Init) refers to filters.o(i.FilterRMSInt_Process) for FilterRMSInt_Process + filters.o(i.FilterRMSInt_Process) refers to llsdiv.o(.text) for __aeabi_ldivmod + filters.o(i.FilterRMSInt_Process) refers to ffltll_clz.o(x$fpl$ffltll) for __aeabi_l2f + filters.o(i.FilterRMS_Init) refers to rt_memclr_w.o(.text) for __aeabi_memclr4 + filters.o(i.FilterRMS_Init) refers to filters.o(i.FilterRMS_Process) for FilterRMS_Process + system_k1921vk035.o(i.SystemCoreClockUpdate) refers to system_k1921vk035.o(.data) for SystemCoreClock + system_k1921vk035.o(i.SystemInit) refers to system_k1921vk035.o(i.ClkInit) for ClkInit + system_k1921vk035.o(i.SystemInit) refers to system_k1921vk035.o(i.FPUInit) for FPUInit + startup_k1921vk035.o(STACK) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_k1921vk035.o(HEAP) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_k1921vk035.o(RESET) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_k1921vk035.o(RESET) refers to startup_k1921vk035.o(STACK) for __initial_sp + startup_k1921vk035.o(RESET) refers to startup_k1921vk035.o(.text) for Reset_Handler + startup_k1921vk035.o(RESET) refers to vk035_it.o(i.NMI_Handler) for NMI_Handler + startup_k1921vk035.o(RESET) refers to vk035_it.o(i.HardFault_Handler) for HardFault_Handler + startup_k1921vk035.o(RESET) refers to vk035_it.o(i.MemManage_Handler) for MemManage_Handler + startup_k1921vk035.o(RESET) refers to vk035_it.o(i.BusFault_Handler) for BusFault_Handler + startup_k1921vk035.o(RESET) refers to vk035_it.o(i.UsageFault_Handler) for UsageFault_Handler + startup_k1921vk035.o(RESET) refers to vk035_it.o(i.SVC_Handler) for SVC_Handler + startup_k1921vk035.o(RESET) refers to vk035_it.o(i.DebugMon_Handler) for DebugMon_Handler + startup_k1921vk035.o(RESET) refers to vk035_it.o(i.PendSV_Handler) for PendSV_Handler + startup_k1921vk035.o(RESET) refers to vk035_it.o(i.SysTick_Handler) for SysTick_Handler + startup_k1921vk035.o(.text) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_k1921vk035.o(.text) refers to system_k1921vk035.o(i.SystemInit) for SystemInit + startup_k1921vk035.o(.text) refers to __main.o(!!!main) for __main + startup_k1921vk035.o(.text) refers to startup_k1921vk035.o(HEAP) for Heap_Mem + startup_k1921vk035.o(.text) refers to startup_k1921vk035.o(STACK) for Stack_Mem + plib035_adc.o(i.ADC_DC_ChannelConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_adc.o(i.ADC_DC_ChannelConfig) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init + plib035_adc.o(i.ADC_DC_Config) refers to main.o(i.assert_failed) for assert_failed + plib035_adc.o(i.ADC_DC_Config) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init + plib035_adc.o(i.ADC_DC_Init) refers to plib035_adc.o(i.ADC_DC_OutputCmd) for ADC_DC_OutputCmd + plib035_adc.o(i.ADC_DC_Init) refers to plib035_adc.o(i.ADC_DC_SetThresholdLow) for ADC_DC_SetThresholdLow + plib035_adc.o(i.ADC_DC_Init) refers to plib035_adc.o(i.ADC_DC_SetThresholdHigh) for ADC_DC_SetThresholdHigh + plib035_adc.o(i.ADC_DC_Init) refers to plib035_adc.o(i.ADC_DC_SourceConfig) for ADC_DC_SourceConfig + plib035_adc.o(i.ADC_DC_Init) refers to plib035_adc.o(i.ADC_DC_ChannelConfig) for ADC_DC_ChannelConfig + plib035_adc.o(i.ADC_DC_Init) refers to plib035_adc.o(i.ADC_DC_Config) for ADC_DC_Config + plib035_adc.o(i.ADC_DC_OutputCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_adc.o(i.ADC_DC_OutputCmd) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init + plib035_adc.o(i.ADC_DC_SetThresholdHigh) refers to main.o(i.assert_failed) for assert_failed + plib035_adc.o(i.ADC_DC_SetThresholdHigh) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init + plib035_adc.o(i.ADC_DC_SetThresholdLow) refers to main.o(i.assert_failed) for assert_failed + plib035_adc.o(i.ADC_DC_SetThresholdLow) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init + plib035_adc.o(i.ADC_DC_SourceConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_adc.o(i.ADC_DC_SourceConfig) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init + plib035_adc.o(i.ADC_DeInit) refers to plib035_adc.o(i.RCU_ADCRstCmd) for RCU_ADCRstCmd + plib035_adc.o(i.ADC_SEQ_DCEnableCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_adc.o(i.ADC_SEQ_DCEnableCmd) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init + plib035_adc.o(i.ADC_SEQ_DMACmd) refers to main.o(i.assert_failed) for assert_failed + plib035_adc.o(i.ADC_SEQ_DMACmd) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init + plib035_adc.o(i.ADC_SEQ_DMAConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_adc.o(i.ADC_SEQ_DMAConfig) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init + plib035_adc.o(i.ADC_SEQ_Init) refers to main.o(i.assert_failed) for assert_failed + plib035_adc.o(i.ADC_SEQ_Init) refers to plib035_adc.o(i.ADC_SEQ_SwStartEnCmd) for ADC_SEQ_SwStartEnCmd + plib035_adc.o(i.ADC_SEQ_Init) refers to plib035_adc.o(i.ADC_SEQ_ReqConfig) for ADC_SEQ_ReqConfig + plib035_adc.o(i.ADC_SEQ_Init) refers to plib035_adc.o(i.ADC_SEQ_ReqMaxConfig) for ADC_SEQ_ReqMaxConfig + plib035_adc.o(i.ADC_SEQ_Init) refers to plib035_adc.o(i.ADC_SEQ_ReqAverageConfig) for ADC_SEQ_ReqAverageConfig + plib035_adc.o(i.ADC_SEQ_Init) refers to plib035_adc.o(i.ADC_SEQ_ReqAverageCmd) for ADC_SEQ_ReqAverageCmd + plib035_adc.o(i.ADC_SEQ_Init) refers to plib035_adc.o(i.ADC_SEQ_RestartConfig) for ADC_SEQ_RestartConfig + plib035_adc.o(i.ADC_SEQ_Init) refers to plib035_adc.o(i.ADC_SEQ_RestartAverageCmd) for ADC_SEQ_RestartAverageCmd + plib035_adc.o(i.ADC_SEQ_Init) refers to plib035_adc.o(i.ADC_SEQ_SetRestartTimer) for ADC_SEQ_SetRestartTimer + plib035_adc.o(i.ADC_SEQ_Init) refers to plib035_adc.o(i.ADC_SEQ_DCEnableCmd) for ADC_SEQ_DCEnableCmd + plib035_adc.o(i.ADC_SEQ_Init) refers to plib035_adc.o(i.ADC_SEQ_DMAConfig) for ADC_SEQ_DMAConfig + plib035_adc.o(i.ADC_SEQ_Init) refers to plib035_adc.o(i.ADC_SEQ_DMACmd) for ADC_SEQ_DMACmd + plib035_adc.o(i.ADC_SEQ_ReqAverageCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_adc.o(i.ADC_SEQ_ReqAverageCmd) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init + plib035_adc.o(i.ADC_SEQ_ReqAverageConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_adc.o(i.ADC_SEQ_ReqAverageConfig) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init + plib035_adc.o(i.ADC_SEQ_ReqConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_adc.o(i.ADC_SEQ_ReqConfig) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init + plib035_adc.o(i.ADC_SEQ_ReqMaxConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_adc.o(i.ADC_SEQ_ReqMaxConfig) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init + plib035_adc.o(i.ADC_SEQ_RestartAverageCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_adc.o(i.ADC_SEQ_RestartAverageCmd) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init + plib035_adc.o(i.ADC_SEQ_RestartConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_adc.o(i.ADC_SEQ_RestartConfig) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init + plib035_adc.o(i.ADC_SEQ_SetRestartTimer) refers to main.o(i.assert_failed) for assert_failed + plib035_adc.o(i.ADC_SEQ_SetRestartTimer) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init + plib035_adc.o(i.ADC_SEQ_SwStartEnCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_adc.o(i.ADC_SEQ_SwStartEnCmd) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init + plib035_adc.o(i.RCU_ADCRstCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_dma.o(i.DMA_AltCtrlCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_dma.o(i.DMA_AltCtrlCmd) refers to plib035_dma.o(i.DMA_ProtectConfig) for i.DMA_ProtectConfig + plib035_dma.o(i.DMA_ChannelEnableCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_dma.o(i.DMA_ChannelEnableCmd) refers to plib035_dma.o(i.DMA_ProtectConfig) for i.DMA_ProtectConfig + plib035_dma.o(i.DMA_ChannelInit) refers to main.o(i.assert_failed) for assert_failed + plib035_dma.o(i.DMA_HighPriorityCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_dma.o(i.DMA_HighPriorityCmd) refers to plib035_dma.o(i.DMA_ProtectConfig) for i.DMA_ProtectConfig + plib035_dma.o(i.DMA_Init) refers to plib035_dma.o(i.DMA_ProtectConfig) for DMA_ProtectConfig + plib035_dma.o(i.DMA_Init) refers to plib035_dma.o(i.DMA_UseBurstCmd) for DMA_UseBurstCmd + plib035_dma.o(i.DMA_Init) refers to plib035_dma.o(i.DMA_AltCtrlCmd) for DMA_AltCtrlCmd + plib035_dma.o(i.DMA_Init) refers to plib035_dma.o(i.DMA_HighPriorityCmd) for DMA_HighPriorityCmd + plib035_dma.o(i.DMA_Init) refers to plib035_dma.o(i.DMA_ReqMaskCmd) for DMA_ReqMaskCmd + plib035_dma.o(i.DMA_Init) refers to plib035_dma.o(i.DMA_ChannelEnableCmd) for DMA_ChannelEnableCmd + plib035_dma.o(i.DMA_ProtectConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_dma.o(i.DMA_ReqMaskCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_dma.o(i.DMA_ReqMaskCmd) refers to plib035_dma.o(i.DMA_ProtectConfig) for i.DMA_ProtectConfig + plib035_dma.o(i.DMA_UseBurstCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_dma.o(i.DMA_UseBurstCmd) refers to plib035_dma.o(i.DMA_ProtectConfig) for i.DMA_ProtectConfig + plib035_ecap.o(i.ECAP_Capture_Init) refers to plib035_ecap.o(i.ECAP_Capture_ModeConfig) for ECAP_Capture_ModeConfig + plib035_ecap.o(i.ECAP_Capture_Init) refers to plib035_ecap.o(i.ECAP_Capture_StopConfig) for ECAP_Capture_StopConfig + plib035_ecap.o(i.ECAP_Capture_Init) refers to plib035_ecap.o(i.ECAP_Capture_PrescaleConfig) for ECAP_Capture_PrescaleConfig + plib035_ecap.o(i.ECAP_Capture_Init) refers to plib035_ecap.o(i.ECAP_Capture_PolarityEvt0Config) for ECAP_Capture_PolarityEvt0Config + plib035_ecap.o(i.ECAP_Capture_Init) refers to plib035_ecap.o(i.ECAP_Capture_PolarityEvt1Config) for ECAP_Capture_PolarityEvt1Config + plib035_ecap.o(i.ECAP_Capture_Init) refers to plib035_ecap.o(i.ECAP_Capture_PolarityEvt2Config) for ECAP_Capture_PolarityEvt2Config + plib035_ecap.o(i.ECAP_Capture_Init) refers to plib035_ecap.o(i.ECAP_Capture_PolarityEvt3Config) for ECAP_Capture_PolarityEvt3Config + plib035_ecap.o(i.ECAP_Capture_Init) refers to plib035_ecap.o(i.ECAP_Capture_RstEvt0Cmd) for ECAP_Capture_RstEvt0Cmd + plib035_ecap.o(i.ECAP_Capture_Init) refers to plib035_ecap.o(i.ECAP_Capture_RstEvt1Cmd) for ECAP_Capture_RstEvt1Cmd + plib035_ecap.o(i.ECAP_Capture_Init) refers to plib035_ecap.o(i.ECAP_Capture_RstEvt2Cmd) for ECAP_Capture_RstEvt2Cmd + plib035_ecap.o(i.ECAP_Capture_Init) refers to plib035_ecap.o(i.ECAP_Capture_RstEvt3Cmd) for ECAP_Capture_RstEvt3Cmd + plib035_ecap.o(i.ECAP_Capture_ModeConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_ecap.o(i.ECAP_Capture_ModeConfig) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init + plib035_ecap.o(i.ECAP_Capture_PolarityEvt0Config) refers to main.o(i.assert_failed) for assert_failed + plib035_ecap.o(i.ECAP_Capture_PolarityEvt0Config) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init + plib035_ecap.o(i.ECAP_Capture_PolarityEvt1Config) refers to main.o(i.assert_failed) for assert_failed + plib035_ecap.o(i.ECAP_Capture_PolarityEvt1Config) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init + plib035_ecap.o(i.ECAP_Capture_PolarityEvt2Config) refers to main.o(i.assert_failed) for assert_failed + plib035_ecap.o(i.ECAP_Capture_PolarityEvt2Config) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init + plib035_ecap.o(i.ECAP_Capture_PolarityEvt3Config) refers to main.o(i.assert_failed) for assert_failed + plib035_ecap.o(i.ECAP_Capture_PolarityEvt3Config) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init + plib035_ecap.o(i.ECAP_Capture_PrescaleConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_ecap.o(i.ECAP_Capture_PrescaleConfig) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init + plib035_ecap.o(i.ECAP_Capture_RstEvt0Cmd) refers to main.o(i.assert_failed) for assert_failed + plib035_ecap.o(i.ECAP_Capture_RstEvt0Cmd) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init + plib035_ecap.o(i.ECAP_Capture_RstEvt1Cmd) refers to main.o(i.assert_failed) for assert_failed + plib035_ecap.o(i.ECAP_Capture_RstEvt1Cmd) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init + plib035_ecap.o(i.ECAP_Capture_RstEvt2Cmd) refers to main.o(i.assert_failed) for assert_failed + plib035_ecap.o(i.ECAP_Capture_RstEvt2Cmd) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init + plib035_ecap.o(i.ECAP_Capture_RstEvt3Cmd) refers to main.o(i.assert_failed) for assert_failed + plib035_ecap.o(i.ECAP_Capture_RstEvt3Cmd) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init + plib035_ecap.o(i.ECAP_Capture_StopConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_ecap.o(i.ECAP_Capture_StopConfig) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init + plib035_ecap.o(i.ECAP_DeInit) refers to main.o(i.assert_failed) for assert_failed + plib035_ecap.o(i.ECAP_DeInit) refers to plib035_ecap.o(i.RCU_APBRstCmd) for RCU_APBRstCmd + plib035_ecap.o(i.ECAP_HaltConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_ecap.o(i.ECAP_HaltConfig) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init + plib035_ecap.o(i.ECAP_Init) refers to plib035_ecap.o(i.ECAP_HaltConfig) for ECAP_HaltConfig + plib035_ecap.o(i.ECAP_Init) refers to plib035_ecap.o(i.ECAP_SyncOutConfig) for ECAP_SyncOutConfig + plib035_ecap.o(i.ECAP_Init) refers to plib035_ecap.o(i.ECAP_SyncCmd) for ECAP_SyncCmd + plib035_ecap.o(i.ECAP_Init) refers to plib035_ecap.o(i.ECAP_ModeConfig) for ECAP_ModeConfig + plib035_ecap.o(i.ECAP_ModeConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_ecap.o(i.ECAP_ModeConfig) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init + plib035_ecap.o(i.ECAP_PWM_Init) refers to main.o(i.assert_failed) for assert_failed + plib035_ecap.o(i.ECAP_PWM_Init) refers to plib035_ecap.o(i.ECAP_PWM_PolarityConfig) for ECAP_PWM_PolarityConfig + plib035_ecap.o(i.ECAP_PWM_PolarityConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_ecap.o(i.ECAP_PWM_PolarityConfig) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init + plib035_ecap.o(i.ECAP_SyncCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_ecap.o(i.ECAP_SyncCmd) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init + plib035_ecap.o(i.ECAP_SyncOutConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_ecap.o(i.ECAP_SyncOutConfig) refers to plib035_ecap.o(i.ECAP_PWM_Init) for i.ECAP_PWM_Init + plib035_ecap.o(i.RCU_APBRstCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_gpio.o(i.GPIO_AltFuncCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_gpio.o(i.GPIO_AltFuncCmd) refers to plib035_gpio.o(i.GPIO_DigitalCmd) for i.GPIO_DigitalCmd + plib035_gpio.o(i.GPIO_DeInit) refers to main.o(i.assert_failed) for assert_failed + plib035_gpio.o(i.GPIO_DeInit) refers to plib035_gpio.o(i.RCU_AHBRstCmd) for RCU_AHBRstCmd + plib035_gpio.o(i.GPIO_DigitalCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_gpio.o(i.GPIO_DriveModeConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_gpio.o(i.GPIO_DriveModeConfig) refers to plib035_gpio.o(i.GPIO_ModeConfig) for GPIO_ModeConfig + plib035_gpio.o(i.GPIO_InModeConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_gpio.o(i.GPIO_InModeConfig) refers to plib035_gpio.o(i.GPIO_ModeConfig) for GPIO_ModeConfig + plib035_gpio.o(i.GPIO_Init) refers to plib035_gpio.o(i.GPIO_OutCmd) for GPIO_OutCmd + plib035_gpio.o(i.GPIO_Init) refers to plib035_gpio.o(i.GPIO_AltFuncCmd) for GPIO_AltFuncCmd + plib035_gpio.o(i.GPIO_Init) refers to plib035_gpio.o(i.GPIO_OutModeConfig) for GPIO_OutModeConfig + plib035_gpio.o(i.GPIO_Init) refers to plib035_gpio.o(i.GPIO_InModeConfig) for GPIO_InModeConfig + plib035_gpio.o(i.GPIO_Init) refers to plib035_gpio.o(i.GPIO_PullModeConfig) for GPIO_PullModeConfig + plib035_gpio.o(i.GPIO_Init) refers to plib035_gpio.o(i.GPIO_DriveModeConfig) for GPIO_DriveModeConfig + plib035_gpio.o(i.GPIO_Init) refers to plib035_gpio.o(i.GPIO_DigitalCmd) for GPIO_DigitalCmd + plib035_gpio.o(i.GPIO_OutCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_gpio.o(i.GPIO_OutCmd) refers to plib035_gpio.o(i.GPIO_DigitalCmd) for i.GPIO_DigitalCmd + plib035_gpio.o(i.GPIO_OutModeConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_gpio.o(i.GPIO_OutModeConfig) refers to plib035_gpio.o(i.GPIO_ModeConfig) for GPIO_ModeConfig + plib035_gpio.o(i.GPIO_PullModeConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_gpio.o(i.GPIO_PullModeConfig) refers to plib035_gpio.o(i.GPIO_ModeConfig) for GPIO_ModeConfig + plib035_gpio.o(i.RCU_AHBRstCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_i2c.o(i.I2C_FSFreqConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_i2c.o(i.I2C_HSFreqConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_i2c.o(i.I2C_HSFreqConfig) refers to plib035_i2c.o(i.I2C_FSFreqConfig) for i.I2C_FSFreqConfig + plib035_mflash.o(i.MFLASH_EraseFull) refers to main.o(i.assert_failed) for assert_failed + plib035_mflash.o(i.MFLASH_EraseFull) refers to plib035_mflash.o(i.MFLASH_SetCmd) for MFLASH_SetCmd + plib035_mflash.o(i.MFLASH_EraseFull) refers to plib035_mflash.o(i.MFLASH_BusyStatus) for MFLASH_BusyStatus + plib035_mflash.o(i.MFLASH_ErasePage) refers to main.o(i.assert_failed) for assert_failed + plib035_mflash.o(i.MFLASH_ErasePage) refers to plib035_mflash.o(i.MFLASH_SetAddr) for MFLASH_SetAddr + plib035_mflash.o(i.MFLASH_ErasePage) refers to plib035_mflash.o(i.MFLASH_SetCmd) for MFLASH_SetCmd + plib035_mflash.o(i.MFLASH_ErasePage) refers to plib035_mflash.o(i.MFLASH_BusyStatus) for MFLASH_BusyStatus + plib035_mflash.o(i.MFLASH_ReadData) refers to main.o(i.assert_failed) for assert_failed + plib035_mflash.o(i.MFLASH_ReadData) refers to plib035_mflash.o(i.MFLASH_SetAddr) for MFLASH_SetAddr + plib035_mflash.o(i.MFLASH_ReadData) refers to plib035_mflash.o(i.MFLASH_SetCmd) for MFLASH_SetCmd + plib035_mflash.o(i.MFLASH_ReadData) refers to plib035_mflash.o(i.MFLASH_BusyStatus) for MFLASH_BusyStatus + plib035_mflash.o(i.MFLASH_WriteData) refers to main.o(i.assert_failed) for assert_failed + plib035_mflash.o(i.MFLASH_WriteData) refers to plib035_mflash.o(i.MFLASH_SetAddr) for MFLASH_SetAddr + plib035_mflash.o(i.MFLASH_WriteData) refers to plib035_mflash.o(i.MFLASH_SetCmd) for MFLASH_SetCmd + plib035_mflash.o(i.MFLASH_WriteData) refers to plib035_mflash.o(i.MFLASH_BusyStatus) for MFLASH_BusyStatus + plib035_mflash.o(i.MFLASH_WriteData) refers to plib035_mflash.o(i.MFLASH_ReadData) for i.MFLASH_ReadData + plib035_pwm.o(i.PWM_AQ_ActionAConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_AQ_ActionBConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_AQ_Init) refers to plib035_pwm.o(i.PWM_AQ_ActionAConfig) for PWM_AQ_ActionAConfig + plib035_pwm.o(i.PWM_AQ_Init) refers to plib035_pwm.o(i.PWM_AQ_ActionBConfig) for PWM_AQ_ActionBConfig + plib035_pwm.o(i.PWM_CMP_CmpADirectLoadCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_CMP_CmpALoadEventConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_CMP_Init) refers to plib035_pwm.o(i.PWM_CMP_CmpALoadEventConfig) for PWM_CMP_CmpALoadEventConfig + plib035_pwm.o(i.PWM_CMP_Init) refers to plib035_pwm.o(i.PWM_CMP_CmpADirectLoadCmd) for PWM_CMP_CmpADirectLoadCmd + plib035_pwm.o(i.PWM_CMP_Init) refers to plib035_pwm.o(i.PWM_CMP_SetCmpA) for PWM_CMP_SetCmpA + plib035_pwm.o(i.PWM_CMP_Init) refers to plib035_pwm.o(i.PWM_CMP_SetCmpB) for PWM_CMP_SetCmpB + plib035_pwm.o(i.PWM_CMP_SetCmpA) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_CMP_SetCmpA) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_CMP_SetCmpB) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_CMP_SetCmpB) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_DB_InConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_DB_InConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_DB_Init) refers to plib035_pwm.o(i.PWM_DB_InConfig) for PWM_DB_InConfig + plib035_pwm.o(i.PWM_DB_Init) refers to plib035_pwm.o(i.PWM_DB_OutConfig) for PWM_DB_OutConfig + plib035_pwm.o(i.PWM_DB_Init) refers to plib035_pwm.o(i.PWM_DB_PolarityConfig) for PWM_DB_PolarityConfig + plib035_pwm.o(i.PWM_DB_Init) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_DB_Init) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_DB_OutConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_DB_OutConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_DB_PolarityConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_DB_PolarityConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_DeInit) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_DeInit) refers to plib035_pwm.o(i.RCU_APBRstCmd) for RCU_APBRstCmd + plib035_pwm.o(i.PWM_ET_DRQACmd) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_ET_DRQACmd) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_ET_DRQAEventConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_ET_DRQAEventConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_ET_DRQAPeriodConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_ET_DRQAPeriodConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_ET_DRQBCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_ET_DRQBCmd) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_ET_DRQBEventConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_ET_DRQBEventConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_ET_DRQBPeriodConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_ET_DRQBPeriodConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_ET_Init) refers to plib035_pwm.o(i.PWM_ET_SOCAEventConfig) for PWM_ET_SOCAEventConfig + plib035_pwm.o(i.PWM_ET_Init) refers to plib035_pwm.o(i.PWM_ET_SOCAPeriodConfig) for PWM_ET_SOCAPeriodConfig + plib035_pwm.o(i.PWM_ET_Init) refers to plib035_pwm.o(i.PWM_ET_SOCACmd) for PWM_ET_SOCACmd + plib035_pwm.o(i.PWM_ET_Init) refers to plib035_pwm.o(i.PWM_ET_SOCBEventConfig) for PWM_ET_SOCBEventConfig + plib035_pwm.o(i.PWM_ET_Init) refers to plib035_pwm.o(i.PWM_ET_SOCBPeriodConfig) for PWM_ET_SOCBPeriodConfig + plib035_pwm.o(i.PWM_ET_Init) refers to plib035_pwm.o(i.PWM_ET_SOCBCmd) for PWM_ET_SOCBCmd + plib035_pwm.o(i.PWM_ET_Init) refers to plib035_pwm.o(i.PWM_ET_DRQAEventConfig) for PWM_ET_DRQAEventConfig + plib035_pwm.o(i.PWM_ET_Init) refers to plib035_pwm.o(i.PWM_ET_DRQAPeriodConfig) for PWM_ET_DRQAPeriodConfig + plib035_pwm.o(i.PWM_ET_Init) refers to plib035_pwm.o(i.PWM_ET_DRQACmd) for PWM_ET_DRQACmd + plib035_pwm.o(i.PWM_ET_Init) refers to plib035_pwm.o(i.PWM_ET_DRQBEventConfig) for PWM_ET_DRQBEventConfig + plib035_pwm.o(i.PWM_ET_Init) refers to plib035_pwm.o(i.PWM_ET_DRQBPeriodConfig) for PWM_ET_DRQBPeriodConfig + plib035_pwm.o(i.PWM_ET_Init) refers to plib035_pwm.o(i.PWM_ET_DRQBCmd) for PWM_ET_DRQBCmd + plib035_pwm.o(i.PWM_ET_SOCACmd) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_ET_SOCACmd) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_ET_SOCAEventConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_ET_SOCAEventConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_ET_SOCAPeriodConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_ET_SOCAPeriodConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_ET_SOCBCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_ET_SOCBCmd) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_ET_SOCBEventConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_ET_SOCBEventConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_ET_SOCBPeriodConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_ET_SOCBPeriodConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_HD_ActionAConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_HD_ActionAConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_HD_ActionBConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_HD_ActionBConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_HD_CycleCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_HD_CycleCmd) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_HD_Init) refers to plib035_pwm.o(i.PWM_HD_ActionAConfig) for PWM_HD_ActionAConfig + plib035_pwm.o(i.PWM_HD_Init) refers to plib035_pwm.o(i.PWM_HD_ActionBConfig) for PWM_HD_ActionBConfig + plib035_pwm.o(i.PWM_HD_Init) refers to plib035_pwm.o(i.PWM_HD_SourceCmd) for PWM_HD_SourceCmd + plib035_pwm.o(i.PWM_HD_Init) refers to plib035_pwm.o(i.PWM_HD_CycleCmd) for PWM_HD_CycleCmd + plib035_pwm.o(i.PWM_HD_Init) refers to plib035_pwm.o(i.PWM_HD_OneShotCmd) for PWM_HD_OneShotCmd + plib035_pwm.o(i.PWM_HD_OneShotCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_HD_OneShotCmd) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_HD_SourceCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_HD_SourceCmd) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_TB_ClkDivConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_TB_HaltConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_TB_HaltConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_TB_Init) refers to plib035_pwm.o(i.PWM_TB_HaltConfig) for PWM_TB_HaltConfig + plib035_pwm.o(i.PWM_TB_Init) refers to plib035_pwm.o(i.PWM_TB_PhaseSyncCmd) for PWM_TB_PhaseSyncCmd + plib035_pwm.o(i.PWM_TB_Init) refers to plib035_pwm.o(i.PWM_TB_PhaseSyncDirConfig) for PWM_TB_PhaseSyncDirConfig + plib035_pwm.o(i.PWM_TB_Init) refers to plib035_pwm.o(i.PWM_TB_ClkDivConfig) for PWM_TB_ClkDivConfig + plib035_pwm.o(i.PWM_TB_Init) refers to plib035_pwm.o(i.PWM_TB_SyncOutConfig) for PWM_TB_SyncOutConfig + plib035_pwm.o(i.PWM_TB_Init) refers to plib035_pwm.o(i.PWM_TB_PeriodDirectLoadCmd) for PWM_TB_PeriodDirectLoadCmd + plib035_pwm.o(i.PWM_TB_Init) refers to plib035_pwm.o(i.PWM_TB_ModeConfig) for PWM_TB_ModeConfig + plib035_pwm.o(i.PWM_TB_Init) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_TB_ModeConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_TB_ModeConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_TB_PeriodDirectLoadCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_TB_PeriodDirectLoadCmd) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_TB_PhaseSyncCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_TB_PhaseSyncCmd) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_TB_PhaseSyncDirConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_TB_PhaseSyncDirConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_TB_SyncOutConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_TB_SyncOutConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_TZ_ActionAConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_TZ_ActionAConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_TZ_ActionBConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_TZ_ActionBConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_TZ_CycleCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_TZ_CycleCmd) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_TZ_Init) refers to plib035_pwm.o(i.PWM_TZ_ActionAConfig) for PWM_TZ_ActionAConfig + plib035_pwm.o(i.PWM_TZ_Init) refers to plib035_pwm.o(i.PWM_TZ_ActionBConfig) for PWM_TZ_ActionBConfig + plib035_pwm.o(i.PWM_TZ_Init) refers to plib035_pwm.o(i.PWM_TZ_CycleCmd) for PWM_TZ_CycleCmd + plib035_pwm.o(i.PWM_TZ_Init) refers to plib035_pwm.o(i.PWM_TZ_OneShotCmd) for PWM_TZ_OneShotCmd + plib035_pwm.o(i.PWM_TZ_OneShotCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_TZ_OneShotCmd) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.RCU_APBRstCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_qep.o(i.QEP_CAP_DivConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_qep.o(i.QEP_CAP_DivConfig) refers to plib035_qep.o(i.QEP_PC_Init) for i.QEP_PC_Init + plib035_qep.o(i.QEP_CAP_Init) refers to main.o(i.assert_failed) for assert_failed + plib035_qep.o(i.QEP_CAP_Init) refers to plib035_qep.o(i.QEP_CAP_DivConfig) for QEP_CAP_DivConfig + plib035_qep.o(i.QEP_CAP_Init) refers to plib035_qep.o(i.QEP_PC_Init) for i.QEP_PC_Init + plib035_qep.o(i.QEP_CMP_Init) refers to main.o(i.assert_failed) for assert_failed + plib035_qep.o(i.QEP_CMP_Init) refers to plib035_qep.o(i.QEP_PC_Init) for i.QEP_PC_Init + plib035_qep.o(i.QEP_DeInit) refers to plib035_qep.o(i.RCU_APBRstCmd) for RCU_APBRstCmd + plib035_qep.o(i.QEP_PC_Init) refers to main.o(i.assert_failed) for assert_failed + plib035_qep.o(i.RCU_APBRstCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_rcu.o(i.MFLASH_LatencyConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_rcu.o(i.RCU_GetADCClkFreq) refers to plib035_rcu.o(i.getPeriphClkFreq) for getPeriphClkFreq + plib035_rcu.o(i.RCU_GetClkOutFreq) refers to plib035_rcu.o(i.getSysPeriphClkFreq) for getSysPeriphClkFreq + plib035_rcu.o(i.RCU_GetPLLDivClkFreq) refers to plib035_rcu.o(i.RCU_GetPLLClkFreq) for RCU_GetPLLClkFreq + plib035_rcu.o(i.RCU_GetSPIClkFreq) refers to plib035_rcu.o(i.getPeriphClkFreq) for getPeriphClkFreq + plib035_rcu.o(i.RCU_GetSysClkFreq) refers to plib035_rcu.o(i.getSysClkFreq) for getSysClkFreq + plib035_rcu.o(i.RCU_GetTraceClkFreq) refers to plib035_rcu.o(i.getSysPeriphClkFreq) for getSysPeriphClkFreq + plib035_rcu.o(i.RCU_GetUARTClkFreq) refers to plib035_rcu.o(i.getPeriphClkFreq) for getPeriphClkFreq + plib035_rcu.o(i.RCU_GetWDTClkFreq) refers to plib035_rcu.o(i.getSysPeriphClkFreq) for getSysPeriphClkFreq + plib035_rcu.o(i.RCU_PLL_AutoConfig) refers to plib035_rcu.o(i.RCU_PLL_StructInit) for RCU_PLL_StructInit + plib035_rcu.o(i.RCU_PLL_AutoConfig) refers to plib035_rcu.o(i.RCU_PLL_Init) for RCU_PLL_Init + plib035_rcu.o(i.RCU_PLL_AutoConfig) refers to plib035_rcu.o(i.MFLASH_LatencyConfig) for MFLASH_LatencyConfig + plib035_rcu.o(i.RCU_PLL_AutoConfig) refers to plib035_rcu.o(i.RCU_SysClkChangeCmd) for RCU_SysClkChangeCmd + plib035_rcu.o(i.RCU_PLL_DeInit) refers to plib035_rcu.o(i.RCU_PLL_OutCmd) for RCU_PLL_OutCmd + plib035_rcu.o(i.RCU_PLL_Init) refers to main.o(i.assert_failed) for assert_failed + plib035_rcu.o(i.RCU_PLL_Init) refers to plib035_rcu.o(i.RCU_PLL_OutCmd) for RCU_PLL_OutCmd + plib035_rcu.o(i.RCU_PLL_OutCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_rcu.o(i.RCU_SysClkChangeCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_rcu.o(i.getPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetOSEClkFreq) for RCU_GetOSEClkFreq + plib035_rcu.o(i.getPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetPLLClkFreq) for RCU_GetPLLClkFreq + plib035_rcu.o(i.getPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetPLLDivClkFreq) for RCU_GetPLLDivClkFreq + plib035_rcu.o(i.getPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetOSIClkFreq) for RCU_GetOSIClkFreq + plib035_rcu.o(i.getSysClkFreq) refers to plib035_rcu.o(i.RCU_GetOSIClkFreq) for RCU_GetOSIClkFreq + plib035_rcu.o(i.getSysClkFreq) refers to plib035_rcu.o(i.RCU_GetOSEClkFreq) for RCU_GetOSEClkFreq + plib035_rcu.o(i.getSysClkFreq) refers to plib035_rcu.o(i.RCU_GetPLLClkFreq) for RCU_GetPLLClkFreq + plib035_rcu.o(i.getSysClkFreq) refers to plib035_rcu.o(i.RCU_GetPLLDivClkFreq) for RCU_GetPLLDivClkFreq + plib035_rcu.o(i.getSysPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetOSEClkFreq) for RCU_GetOSEClkFreq + plib035_rcu.o(i.getSysPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetPLLClkFreq) for RCU_GetPLLClkFreq + plib035_rcu.o(i.getSysPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetPLLDivClkFreq) for RCU_GetPLLDivClkFreq + plib035_rcu.o(i.getSysPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetOSIClkFreq) for RCU_GetOSIClkFreq + plib035_spi.o(i.RCU_SPIRstCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_spi.o(i.SPI_DataWidthConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_spi.o(i.SPI_DataWidthConfig) refers to plib035_spi.o(i.SPI_Init) for i.SPI_Init + plib035_spi.o(i.SPI_DeInit) refers to plib035_spi.o(i.RCU_SPIRstCmd) for RCU_SPIRstCmd + plib035_spi.o(i.SPI_Init) refers to plib035_spi.o(i.SPI_SCKDivConfig) for SPI_SCKDivConfig + plib035_spi.o(i.SPI_Init) refers to plib035_spi.o(i.SPI_DataWidthConfig) for SPI_DataWidthConfig + plib035_spi.o(i.SPI_Init) refers to main.o(i.assert_failed) for assert_failed + plib035_spi.o(i.SPI_SCKDivConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_spi.o(i.SPI_SCKDivConfig) refers to plib035_spi.o(i.SPI_Init) for i.SPI_Init + plib035_tmr.o(i.TMR_FreqConfig) refers to plib035_tmr.o(i.TMR_SetLoad) for TMR_SetLoad + plib035_tmr.o(i.TMR_PeriodConfig) refers to plib035_tmr.o(i.TMR_SetLoad) for TMR_SetLoad + plib035_tmr.o(i.TMR_SetLoad) refers to main.o(i.assert_failed) for assert_failed + plib035_uart.o(i.RCU_UARTRstCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_uart.o(i.UART_AutoBaudConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_uart.o(i.UART_AutoBaudConfig) refers to plib035_rcu.o(i.RCU_GetUARTClkFreq) for RCU_GetUARTClkFreq + plib035_uart.o(i.UART_AutoBaudConfig) refers to plib035_uart.o(i.UART_BaudDivConfig) for UART_BaudDivConfig + plib035_uart.o(i.UART_BaudDivConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_uart.o(i.UART_BaudDivConfig) refers to plib035_uart.o(i.UART_DataWidthConfig) for i.UART_DataWidthConfig + plib035_uart.o(i.UART_DataWidthConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_uart.o(i.UART_DeInit) refers to main.o(i.assert_failed) for assert_failed + plib035_uart.o(i.UART_DeInit) refers to plib035_uart.o(i.RCU_UARTRstCmd) for RCU_UARTRstCmd + plib035_uart.o(i.UART_FIFOCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_uart.o(i.UART_FIFOCmd) refers to plib035_uart.o(i.UART_DataWidthConfig) for i.UART_DataWidthConfig + plib035_uart.o(i.UART_Init) refers to plib035_uart.o(i.UART_AutoBaudConfig) for UART_AutoBaudConfig + plib035_uart.o(i.UART_Init) refers to plib035_uart.o(i.UART_DataWidthConfig) for UART_DataWidthConfig + plib035_uart.o(i.UART_Init) refers to plib035_uart.o(i.UART_StopBitConfig) for UART_StopBitConfig + plib035_uart.o(i.UART_Init) refers to plib035_uart.o(i.UART_ParityBitConfig) for UART_ParityBitConfig + plib035_uart.o(i.UART_Init) refers to plib035_uart.o(i.UART_FIFOCmd) for UART_FIFOCmd + plib035_uart.o(i.UART_Init) refers to plib035_uart.o(i.UART_TxCmd) for UART_TxCmd + plib035_uart.o(i.UART_Init) refers to plib035_uart.o(i.UART_RxCmd) for UART_RxCmd + plib035_uart.o(i.UART_ParityBitConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_uart.o(i.UART_ParityBitConfig) refers to plib035_uart.o(i.UART_DataWidthConfig) for i.UART_DataWidthConfig + plib035_uart.o(i.UART_RxCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_uart.o(i.UART_RxCmd) refers to plib035_uart.o(i.UART_DataWidthConfig) for i.UART_DataWidthConfig + plib035_uart.o(i.UART_StopBitConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_uart.o(i.UART_StopBitConfig) refers to plib035_uart.o(i.UART_DataWidthConfig) for i.UART_DataWidthConfig + plib035_uart.o(i.UART_TxCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_uart.o(i.UART_TxCmd) refers to plib035_uart.o(i.UART_DataWidthConfig) for i.UART_DataWidthConfig + retarget.o(.rev16_text) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi + retarget.o(.revsh_text) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi + retarget.o(.rrx_text) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi + retarget.o(i._sys_exit) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi + retarget.o(i._ttywrch) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi + retarget.o(i._ttywrch) refers to retarget_conf.o(i.retarget_put_char) for retarget_put_char + retarget.o(i.ferror) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi + retarget.o(i.fgetc) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi + retarget.o(i.fgetc) refers to retarget_conf.o(i.retarget_get_char) for retarget_get_char + retarget.o(i.fputc) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi + retarget.o(i.fputc) refers to retarget_conf.o(i.retarget_put_char) for retarget_put_char + retarget.o(.data) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi + retarget_conf.o(i.retarget_init) refers to system_k1921vk035.o(.data) for SystemCoreClock + llsdiv.o(.text) refers to lludivv7m.o(.text) for __aeabi_uldivmod + __2printf.o(.text) refers to _printf_char_file.o(.text) for _printf_char_file + __2printf.o(.text) refers to retarget.o(.data) for __stdout + noretval__2printf.o(.text) refers to _printf_char_file.o(.text) for _printf_char_file + noretval__2printf.o(.text) refers to retarget.o(.data) for __stdout + __printf.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + _printf_str.o(.text) refers (Special) to _printf_char.o(.text) for _printf_cs_common + _printf_str.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_str.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding + _printf_dec.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + __printf_flags.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags.o(.text) refers to __printf_flags.o(.constdata) for .constdata + __printf_ss.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_ss.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_ss.o(.text) refers to __printf_flags_ss.o(.constdata) for .constdata + __printf_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit + __printf_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit + __printf_flags_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_wp.o(.text) refers to __printf_flags_wp.o(.constdata) for .constdata + __printf_ss_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit + __printf_ss_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_ss_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit + __printf_flags_ss_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_ss_wp.o(.text) refers to __printf_flags_ss_wp.o(.constdata) for .constdata + _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) refers (Weak) to _printf_char.o(.text) for _printf_string + _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) refers (Weak) to _printf_dec.o(.text) for _printf_int_dec + _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) refers (Special) to _printf_percent_end.o(.ARM.Collect$$_printf_percent$$00000017) for _printf_percent_end + rand.o(.emb_text) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000D) for __rt_lib_init_rand_2 + rand.o(.emb_text) refers to rand.o(.text) for _rand_init + rand.o(.emb_text) refers to rand.o(.bss) for _random_number_data + rand.o(.text) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000D) for __rt_lib_init_rand_2 + rand.o(.text) refers to rand.o(.bss) for .bss + rand.o(.bss) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000D) for __rt_lib_init_rand_2 + rt_memcpy_v6.o(.text) refers to rt_memcpy_w.o(.text) for __aeabi_memcpy4 + __main.o(!!!main) refers to __rtentry.o(.ARM.Collect$$rtentry$$00000000) for __rt_entry + ddiv.o(x$fpl$drdiv) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + ddiv.o(x$fpl$drdiv) refers to ddiv.o(x$fpl$ddiv) for ddiv_entry + ddiv.o(x$fpl$ddiv) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + ddiv.o(x$fpl$ddiv) refers to dretinf.o(x$fpl$dretinf) for __fpl_dretinf + ddiv.o(x$fpl$ddiv) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + dfix.o(x$fpl$dfix) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dfix.o(x$fpl$dfix) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + dfix.o(x$fpl$dfixr) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dfix.o(x$fpl$dfixr) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + dflt_clz.o(x$fpl$dfltu) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dflt_clz.o(x$fpl$dflt) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dflt_clz.o(x$fpl$dfltn) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + ffltll_clz.o(x$fpl$ffltll) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + cosf.o(i.__hardfp_cosf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + cosf.o(i.__hardfp_cosf) refers to rredf.o(i.__mathlib_rredf2) for __mathlib_rredf2 + cosf.o(i.__hardfp_cosf) refers to _rserrno.o(.text) for __set_errno + cosf.o(i.__hardfp_cosf) refers to funder.o(i.__mathlib_flt_invalid) for __mathlib_flt_invalid + cosf.o(i.__hardfp_cosf) refers to funder.o(i.__mathlib_flt_infnan) for __mathlib_flt_infnan + cosf.o(i.__softfp_cosf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + cosf.o(i.__softfp_cosf) refers to cosf.o(i.__hardfp_cosf) for __hardfp_cosf + cosf.o(i.cosf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + cosf.o(i.cosf) refers to cosf.o(i.__hardfp_cosf) for __hardfp_cosf + cosf_x.o(i.____hardfp_cosf$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + cosf_x.o(i.____hardfp_cosf$lsc) refers to rredf.o(i.__mathlib_rredf2) for __mathlib_rredf2 + cosf_x.o(i.____hardfp_cosf$lsc) refers to _rserrno.o(.text) for __set_errno + cosf_x.o(i.____hardfp_cosf$lsc) refers to funder.o(i.__mathlib_flt_infnan) for __mathlib_flt_infnan + cosf_x.o(i.____softfp_cosf$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + cosf_x.o(i.____softfp_cosf$lsc) refers to cosf_x.o(i.____hardfp_cosf$lsc) for ____hardfp_cosf$lsc + cosf_x.o(i.__cosf$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + cosf_x.o(i.__cosf$lsc) refers to cosf_x.o(i.____hardfp_cosf$lsc) for ____hardfp_cosf$lsc + sinf.o(i.__hardfp_sinf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sinf.o(i.__hardfp_sinf) refers to rredf.o(i.__mathlib_rredf2) for __mathlib_rredf2 + sinf.o(i.__hardfp_sinf) refers to fpclassifyf.o(i.__ARM_fpclassifyf) for __ARM_fpclassifyf + sinf.o(i.__hardfp_sinf) refers to funder.o(i.__mathlib_flt_underflow) for __mathlib_flt_underflow + sinf.o(i.__hardfp_sinf) refers to _rserrno.o(.text) for __set_errno + sinf.o(i.__hardfp_sinf) refers to funder.o(i.__mathlib_flt_invalid) for __mathlib_flt_invalid + sinf.o(i.__hardfp_sinf) refers to funder.o(i.__mathlib_flt_infnan) for __mathlib_flt_infnan + sinf.o(i.__softfp_sinf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sinf.o(i.__softfp_sinf) refers to sinf.o(i.__hardfp_sinf) for __hardfp_sinf + sinf.o(i.sinf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sinf.o(i.sinf) refers to sinf.o(i.__hardfp_sinf) for __hardfp_sinf + sinf_x.o(i.____hardfp_sinf$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sinf_x.o(i.____hardfp_sinf$lsc) refers to rredf.o(i.__mathlib_rredf2) for __mathlib_rredf2 + sinf_x.o(i.____hardfp_sinf$lsc) refers to _rserrno.o(.text) for __set_errno + sinf_x.o(i.____hardfp_sinf$lsc) refers to funder.o(i.__mathlib_flt_infnan) for __mathlib_flt_infnan + sinf_x.o(i.____softfp_sinf$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sinf_x.o(i.____softfp_sinf$lsc) refers to sinf_x.o(i.____hardfp_sinf$lsc) for ____hardfp_sinf$lsc + sinf_x.o(i.__sinf$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sinf_x.o(i.__sinf$lsc) refers to sinf_x.o(i.____hardfp_sinf$lsc) for ____hardfp_sinf$lsc + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for __rt_entry_li + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for __rt_entry_main + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) for __rt_entry_postli_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000009) for __rt_entry_postsh_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000002) for __rt_entry_presh_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for __rt_entry_sh + _rserrno.o(.text) refers to rt_errno_addr_intlibspace.o(.text) for __aeabi_errno_addr + _printf_intcommon.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_intcommon.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_intcommon.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding + _printf_char.o(.text) refers (Weak) to _printf_str.o(.text) for _printf_str + _printf_char_file.o(.text) refers to _printf_char_common.o(.text) for _printf_char_common + _printf_char_file.o(.text) refers to retarget.o(i.ferror) for ferror + _printf_char_file.o(.text) refers to retarget.o(i.fputc) for fputc + libinit2.o(.ARM.Collect$$libinit$$00000001) refers to fpinit.o(x$fpl$fpinit) for _fp_init + libinit2.o(.ARM.Collect$$libinit$$0000000D) refers (Weak) to rand.o(.text) for _rand_init + libinit2.o(.ARM.Collect$$libinit$$00000010) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000012) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000014) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000016) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000018) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000026) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer + libinit2.o(.ARM.Collect$$libinit$$00000027) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer + dnaninf.o(x$fpl$dnaninf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dretinf.o(x$fpl$dretinf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + fpclassifyf.o(i.__ARM_fpclassifyf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + rredf.o(i.__mathlib_rredf2) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + rredf.o(i.__mathlib_rredf2) refers to rredf.o(.constdata) for .constdata + rredf.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + __rtentry2.o(.ARM.Collect$$rtentry$$00000008) refers to boardinit2.o(.text) for _platform_post_stackheap_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) refers to libinit.o(.ARM.Collect$$libinit$$00000000) for __rt_lib_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) refers to boardinit3.o(.text) for _platform_post_lib_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to main.o(i.main) for main + __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to exit.o(.text) for exit + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000001) for .ARM.Collect$$rtentry$$00000001 + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000008) for .ARM.Collect$$rtentry$$00000008 + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for .ARM.Collect$$rtentry$$0000000A + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) for .ARM.Collect$$rtentry$$0000000B + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for .ARM.Collect$$rtentry$$0000000D + __rtentry4.o(.ARM.Collect$$rtentry$$00000004) refers to sys_stackheap_outer.o(.text) for __user_setup_stackheap + __rtentry4.o(.ARM.exidx) refers to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for .ARM.Collect$$rtentry$$00000004 + aeabi_ldiv0_sigfpe.o(.text) refers to rt_div0.o(.text) for __rt_div0 + rt_errno_addr.o(.text) refers to rt_errno_addr.o(.bss) for __aeabi_errno_addr_data + rt_errno_addr_intlibspace.o(.text) refers to libspace.o(.bss) for __libspace_start + _printf_char_common.o(.text) refers to __printf_wp.o(.text) for __printf + argv_veneer.o(.emb_text) refers to no_argv.o(.text) for __ARM_get_argv + libspace.o(.text) refers to libspace.o(.bss) for __libspace_start + sys_stackheap_outer.o(.text) refers to libspace.o(.text) for __user_perproc_libspace + sys_stackheap_outer.o(.text) refers to startup_k1921vk035.o(.text) for __user_initial_stackheap + rt_div0.o(.text) refers to defsig_fpe_outer.o(.text) for __rt_SIGFPE + exit.o(.text) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for __rt_exit + _get_argv_nomalloc.o(.text) refers (Special) to hrguard.o(.text) for __heap_region$guard + _get_argv_nomalloc.o(.text) refers to defsig_rtmem_outer.o(.text) for __rt_SIGRTMEM + _get_argv_nomalloc.o(.text) refers to sys_command.o(.text) for _sys_command_string + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002E) for __rt_lib_init_alloca_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002C) for __rt_lib_init_argv_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001B) for __rt_lib_init_atexit_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000021) for __rt_lib_init_clock_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000032) for __rt_lib_init_cpp_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000030) for __rt_lib_init_exceptions_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000001) for __rt_lib_init_fp_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001F) for __rt_lib_init_fp_trap_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000023) for __rt_lib_init_getenv_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000A) for __rt_lib_init_heap_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000011) for __rt_lib_init_lc_collate_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000013) for __rt_lib_init_lc_ctype_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000015) for __rt_lib_init_lc_monetary_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000017) for __rt_lib_init_lc_numeric_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000019) for __rt_lib_init_lc_time_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000004) for __rt_lib_init_preinit_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000E) for __rt_lib_init_rand_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000033) for __rt_lib_init_return + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001D) for __rt_lib_init_signal_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000025) for __rt_lib_init_stdio_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000C) for __rt_lib_init_user_alloc_1 + sys_command.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_command.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 + rtexit.o(.ARM.exidx) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for .ARM.Collect$$rtexit$$00000000 + defsig_fpe_outer.o(.text) refers to defsig_fpe_inner.o(.text) for __rt_SIGFPE_inner + defsig_fpe_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit + defsig_fpe_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise + defsig_rtmem_outer.o(.text) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner + defsig_rtmem_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit + defsig_rtmem_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise + rtexit2.o(.ARM.Collect$$rtexit$$00000003) refers to libshutdown.o(.ARM.Collect$$libshutdown$$00000000) for __rt_lib_shutdown + rtexit2.o(.ARM.Collect$$rtexit$$00000004) refers to retarget.o(i._sys_exit) for _sys_exit + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000001) for .ARM.Collect$$rtexit$$00000001 + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for .ARM.Collect$$rtexit$$00000003 + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for .ARM.Collect$$rtexit$$00000004 + rt_raise.o(.text) refers to __raise.o(.text) for __raise + rt_raise.o(.text) refers to retarget.o(i._sys_exit) for _sys_exit + defsig_exit.o(.text) refers to retarget.o(i._sys_exit) for _sys_exit + defsig_fpe_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtmem_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + __raise.o(.text) refers to defsig.o(CL$$defsig) for __default_signal_handler + defsig_general.o(.text) refers to retarget.o(i._ttywrch) for _ttywrch + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) for __rt_lib_shutdown_cpp_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) for __rt_lib_shutdown_fini_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000009) for __rt_lib_shutdown_fp_trap_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000011) for __rt_lib_shutdown_heap_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000012) for __rt_lib_shutdown_return + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) for __rt_lib_shutdown_signal_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000006) for __rt_lib_shutdown_stdio_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000E) for __rt_lib_shutdown_user_alloc_1 + defsig.o(CL$$defsig) refers to defsig_fpe_inner.o(.text) for __rt_SIGFPE_inner + defsig.o(CL$$defsig) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner + defsig_abrt_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtred_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_stak_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_pvfn_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_cppl_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_segv_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_other.o(.text) refers to defsig_general.o(.text) for __default_signal_display + + +============================================================================== + +Removing Unused input sections from the image. + + Removing main.o(.rev16_text), (4 bytes). + Removing main.o(.revsh_text), (4 bytes). + Removing main.o(.rrx_text), (6 bytes). + Removing main.o(i.GenOptimizer_Init), (416 bytes). + Removing main.o(i.GenOptimizer_Step), (980 bytes). + Removing main.o(i.cmp_idx), (104 bytes). + Removing main.o(.bss), (512 bytes). + Removing main.o(.data), (396 bytes). + Removing gpio.o(.rev16_text), (4 bytes). + Removing gpio.o(.revsh_text), (4 bytes). + Removing gpio.o(.rrx_text), (6 bytes). + Removing gpio.o(i.GenOptimizer_Init), (416 bytes). + Removing gpio.o(i.GenOptimizer_Step), (980 bytes). + Removing gpio.o(i.cmp_idx), (104 bytes). + Removing gpio.o(.bss), (512 bytes). + Removing rcu.o(.rev16_text), (4 bytes). + Removing rcu.o(.revsh_text), (4 bytes). + Removing rcu.o(.rrx_text), (6 bytes). + Removing rcu.o(i.GenOptimizer_Init), (416 bytes). + Removing rcu.o(i.GenOptimizer_Step), (980 bytes). + Removing rcu.o(i.cmp_idx), (104 bytes). + Removing rcu.o(.bss), (512 bytes). + Removing vk035_it.o(.rev16_text), (4 bytes). + Removing vk035_it.o(.revsh_text), (4 bytes). + Removing vk035_it.o(.rrx_text), (6 bytes). + Removing vk035_it.o(i.GenOptimizer_Init), (416 bytes). + Removing vk035_it.o(i.GenOptimizer_Step), (980 bytes). + Removing vk035_it.o(i.cmp_idx), (104 bytes). + Removing vk035_it.o(.bss), (512 bytes). + Removing vk035_it.o(.data), (8 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_AllocDownBuffer), (200 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_AllocUpBuffer), (200 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_ConfigDownBuffer), (120 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_ConfigUpBuffer), (120 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_GetAvailWriteSpace), (28 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_GetBytesInBuffer), (68 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_GetKey), (32 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_HasData), (28 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_HasDataUp), (28 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_HasKey), (48 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_Init), (8 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_PutChar), (128 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_PutCharSkip), (116 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_PutCharSkipNoLock), (56 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_Read), (56 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_ReadNoLock), (172 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_ReadUpBuffer), (56 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_ReadUpBufferNoLock), (172 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_SetFlagsDownBuffer), (96 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_SetFlagsUpBuffer), (96 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_SetNameDownBuffer), (96 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_SetNameUpBuffer), (96 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_SetTerminal), (160 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_TerminalOut), (260 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_WaitKey), (14 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_Write), (76 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_WriteDownBuffer), (76 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_WriteDownBufferNoLock), (132 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_WriteNoLock), (132 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_WriteSkipNoLock), (160 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_WriteString), (26 bytes). + Removing segger_rtt.o(i.SEGGER_RTT_WriteWithOverwriteNoLock), (180 bytes). + Removing segger_rtt.o(i._DoInit), (116 bytes). + Removing segger_rtt.o(i._GetAvailWriteSpace), (28 bytes). + Removing segger_rtt.o(i._PostTerminalSwitch), (36 bytes). + Removing segger_rtt.o(i._WriteBlocking), (118 bytes). + Removing segger_rtt.o(i._WriteNoCheck), (88 bytes). + Removing segger_rtt.o(.bss), (4280 bytes). + Removing segger_rtt.o(.constdata), (33 bytes). + Removing segger_rtt.o(.data), (1 bytes). + Removing segger_rtt_printf.o(i.SEGGER_RTT_printf), (34 bytes). + Removing segger_rtt_printf.o(i.SEGGER_RTT_vprintf), (544 bytes). + Removing segger_rtt_printf.o(i._PrintInt), (236 bytes). + Removing segger_rtt_printf.o(i._PrintUnsigned), (236 bytes). + Removing segger_rtt_printf.o(i._StoreChar), (68 bytes). + Removing segger_rtt_printf.o(.constdata), (16 bytes). + Removing filters.o(.rev16_text), (4 bytes). + Removing filters.o(.revsh_text), (4 bytes). + Removing filters.o(.rrx_text), (6 bytes). + Removing filters.o(i.FilterAverageInt_Init), (72 bytes). + Removing filters.o(i.FilterAverageInt_Process), (94 bytes). + Removing filters.o(i.FilterAverage_Init), (76 bytes). + Removing filters.o(i.FilterAverage_Process), (104 bytes). + Removing filters.o(i.FilterBandPassDerivative_Init), (308 bytes). + Removing filters.o(i.FilterBandPassDerivative_Process), (126 bytes). + Removing filters.o(i.FilterExpInt_Init), (48 bytes). + Removing filters.o(i.FilterExpInt_Process), (88 bytes). + Removing filters.o(i.FilterExp_Init), (60 bytes). + Removing filters.o(i.FilterExp_Process), (78 bytes). + Removing filters.o(i.FilterLUTInt_Init), (64 bytes). + Removing filters.o(i.FilterLUTInt_Process), (318 bytes). + Removing filters.o(i.FilterLUT_Init), (64 bytes). + Removing filters.o(i.FilterLUT_Process), (248 bytes). + Removing filters.o(i.FilterMedianInt_Init), (88 bytes). + Removing filters.o(i.FilterMedianInt_Process), (218 bytes). + Removing filters.o(i.FilterMedian_Init), (84 bytes). + Removing filters.o(i.FilterMedian_Process), (124 bytes). + Removing filters.o(i.FilterPolyInt_Init), (80 bytes). + Removing filters.o(i.FilterPolyInt_Process), (160 bytes). + Removing filters.o(i.FilterPoly_Init), (72 bytes). + Removing filters.o(i.FilterPoly_Process), (84 bytes). + Removing filters.o(i.FilterRMSInt_Init), (96 bytes). + Removing filters.o(i.FilterRMSInt_Process), (286 bytes). + Removing filters.o(i.FilterRMS_Init), (104 bytes). + Removing filters.o(i.FilterRMS_Process), (224 bytes). + Removing filters.o(i.Filter_float_compare), (52 bytes). + Removing filters.o(.data), (4 bytes). + Removing system_k1921vk035.o(.rev16_text), (4 bytes). + Removing system_k1921vk035.o(.revsh_text), (4 bytes). + Removing system_k1921vk035.o(.rrx_text), (6 bytes). + Removing plib035_adc.o(.rev16_text), (4 bytes). + Removing plib035_adc.o(.revsh_text), (4 bytes). + Removing plib035_adc.o(.rrx_text), (6 bytes). + Removing plib035_adc.o(i.ADC_DC_ChannelConfig), (92 bytes). + Removing plib035_adc.o(i.ADC_DC_Config), (124 bytes). + Removing plib035_adc.o(i.ADC_DC_Init), (58 bytes). + Removing plib035_adc.o(i.ADC_DC_OutputCmd), (84 bytes). + Removing plib035_adc.o(i.ADC_DC_SetThresholdHigh), (88 bytes). + Removing plib035_adc.o(i.ADC_DC_SetThresholdLow), (88 bytes). + Removing plib035_adc.o(i.ADC_DC_SourceConfig), (84 bytes). + Removing plib035_adc.o(i.ADC_DC_StructInit), (18 bytes). + Removing plib035_adc.o(i.ADC_DeInit), (16 bytes). + Removing plib035_adc.o(i.ADC_SEQ_DCEnableCmd), (124 bytes). + Removing plib035_adc.o(i.ADC_SEQ_DMACmd), (88 bytes). + Removing plib035_adc.o(i.ADC_SEQ_DMAConfig), (108 bytes). + Removing plib035_adc.o(i.ADC_SEQ_Init), (224 bytes). + Removing plib035_adc.o(i.ADC_SEQ_ReqAverageCmd), (88 bytes). + Removing plib035_adc.o(i.ADC_SEQ_ReqAverageConfig), (108 bytes). + Removing plib035_adc.o(i.ADC_SEQ_ReqConfig), (132 bytes). + Removing plib035_adc.o(i.ADC_SEQ_ReqMaxConfig), (96 bytes). + Removing plib035_adc.o(i.ADC_SEQ_RestartAverageCmd), (88 bytes). + Removing plib035_adc.o(i.ADC_SEQ_RestartConfig), (88 bytes). + Removing plib035_adc.o(i.ADC_SEQ_SetRestartTimer), (88 bytes). + Removing plib035_adc.o(i.ADC_SEQ_StructInit), (68 bytes). + Removing plib035_adc.o(i.ADC_SEQ_SwStartEnCmd), (72 bytes). + Removing plib035_adc.o(i.RCU_ADCRstCmd), (84 bytes). + Removing plib035_can.o(.rev16_text), (4 bytes). + Removing plib035_can.o(.revsh_text), (4 bytes). + Removing plib035_can.o(.rrx_text), (6 bytes). + Removing plib035_dma.o(.rev16_text), (4 bytes). + Removing plib035_dma.o(.revsh_text), (4 bytes). + Removing plib035_dma.o(.rrx_text), (6 bytes). + Removing plib035_dma.o(i.DMA_AltCtrlCmd), (68 bytes). + Removing plib035_dma.o(i.DMA_ChannelDeInit), (10 bytes). + Removing plib035_dma.o(i.DMA_ChannelEnableCmd), (68 bytes). + Removing plib035_dma.o(i.DMA_ChannelInit), (584 bytes). + Removing plib035_dma.o(i.DMA_ChannelStructInit), (50 bytes). + Removing plib035_dma.o(i.DMA_DeInit), (28 bytes). + Removing plib035_dma.o(i.DMA_HighPriorityCmd), (68 bytes). + Removing plib035_dma.o(i.DMA_Init), (52 bytes). + Removing plib035_dma.o(i.DMA_ProtectConfig), (148 bytes). + Removing plib035_dma.o(i.DMA_ReqMaskCmd), (68 bytes). + Removing plib035_dma.o(i.DMA_StructInit), (28 bytes). + Removing plib035_dma.o(i.DMA_UseBurstCmd), (68 bytes). + Removing plib035_ecap.o(.rev16_text), (4 bytes). + Removing plib035_ecap.o(.revsh_text), (4 bytes). + Removing plib035_ecap.o(.rrx_text), (6 bytes). + Removing plib035_ecap.o(i.ECAP_Capture_Init), (96 bytes). + Removing plib035_ecap.o(i.ECAP_Capture_ModeConfig), (80 bytes). + Removing plib035_ecap.o(i.ECAP_Capture_PolarityEvt0Config), (80 bytes). + Removing plib035_ecap.o(i.ECAP_Capture_PolarityEvt1Config), (80 bytes). + Removing plib035_ecap.o(i.ECAP_Capture_PolarityEvt2Config), (80 bytes). + Removing plib035_ecap.o(i.ECAP_Capture_PolarityEvt3Config), (80 bytes). + Removing plib035_ecap.o(i.ECAP_Capture_PrescaleConfig), (80 bytes). + Removing plib035_ecap.o(i.ECAP_Capture_RstEvt0Cmd), (80 bytes). + Removing plib035_ecap.o(i.ECAP_Capture_RstEvt1Cmd), (80 bytes). + Removing plib035_ecap.o(i.ECAP_Capture_RstEvt2Cmd), (80 bytes). + Removing plib035_ecap.o(i.ECAP_Capture_RstEvt3Cmd), (80 bytes). + Removing plib035_ecap.o(i.ECAP_Capture_StopConfig), (80 bytes). + Removing plib035_ecap.o(i.ECAP_Capture_StructInit), (28 bytes). + Removing plib035_ecap.o(i.ECAP_DeInit), (124 bytes). + Removing plib035_ecap.o(i.ECAP_HaltConfig), (84 bytes). + Removing plib035_ecap.o(i.ECAP_Init), (40 bytes). + Removing plib035_ecap.o(i.ECAP_ModeConfig), (80 bytes). + Removing plib035_ecap.o(i.ECAP_PWM_Init), (148 bytes). + Removing plib035_ecap.o(i.ECAP_PWM_PolarityConfig), (80 bytes). + Removing plib035_ecap.o(i.ECAP_PWM_StructInit), (18 bytes). + Removing plib035_ecap.o(i.ECAP_StructInit), (12 bytes). + Removing plib035_ecap.o(i.ECAP_SyncCmd), (80 bytes). + Removing plib035_ecap.o(i.ECAP_SyncOutConfig), (84 bytes). + Removing plib035_ecap.o(i.RCU_APBRstCmd), (160 bytes). + Removing plib035_gpio.o(.rev16_text), (4 bytes). + Removing plib035_gpio.o(.revsh_text), (4 bytes). + Removing plib035_gpio.o(.rrx_text), (6 bytes). + Removing plib035_gpio.o(i.GPIO_StructInit), (24 bytes). + Removing plib035_i2c.o(.rev16_text), (4 bytes). + Removing plib035_i2c.o(.revsh_text), (4 bytes). + Removing plib035_i2c.o(.rrx_text), (6 bytes). + Removing plib035_i2c.o(i.I2C_FSFreqConfig), (128 bytes). + Removing plib035_i2c.o(i.I2C_HSFreqConfig), (96 bytes). + Removing plib035_mflash.o(.rev16_text), (4 bytes). + Removing plib035_mflash.o(.revsh_text), (4 bytes). + Removing plib035_mflash.o(.rrx_text), (6 bytes). + Removing plib035_mflash.o(i.MFLASH_BusyStatus), (16 bytes). + Removing plib035_mflash.o(i.MFLASH_EraseFull), (92 bytes). + Removing plib035_mflash.o(i.MFLASH_ErasePage), (136 bytes). + Removing plib035_mflash.o(i.MFLASH_ReadData), (224 bytes). + Removing plib035_mflash.o(i.MFLASH_SetAddr), (12 bytes). + Removing plib035_mflash.o(i.MFLASH_SetCmd), (20 bytes). + Removing plib035_mflash.o(i.MFLASH_WriteData), (188 bytes). + Removing plib035_pmu.o(.rev16_text), (4 bytes). + Removing plib035_pmu.o(.revsh_text), (4 bytes). + Removing plib035_pmu.o(.rrx_text), (6 bytes). + Removing plib035_pwm.o(.rev16_text), (4 bytes). + Removing plib035_pwm.o(.revsh_text), (4 bytes). + Removing plib035_pwm.o(.rrx_text), (6 bytes). + Removing plib035_pwm.o(i.PWM_AQ_ActionAConfig), (168 bytes). + Removing plib035_pwm.o(i.PWM_AQ_ActionBConfig), (168 bytes). + Removing plib035_pwm.o(i.PWM_AQ_Init), (128 bytes). + Removing plib035_pwm.o(i.PWM_AQ_StructInit), (28 bytes). + Removing plib035_pwm.o(i.PWM_CMP_CmpADirectLoadCmd), (116 bytes). + Removing plib035_pwm.o(i.PWM_CMP_CmpALoadEventConfig), (124 bytes). + Removing plib035_pwm.o(i.PWM_CMP_Init), (56 bytes). + Removing plib035_pwm.o(i.PWM_CMP_SetCmpA), (80 bytes). + Removing plib035_pwm.o(i.PWM_CMP_SetCmpB), (80 bytes). + Removing plib035_pwm.o(i.PWM_CMP_StructInit), (16 bytes). + Removing plib035_pwm.o(i.PWM_DB_InConfig), (88 bytes). + Removing plib035_pwm.o(i.PWM_DB_Init), (164 bytes). + Removing plib035_pwm.o(i.PWM_DB_OutConfig), (88 bytes). + Removing plib035_pwm.o(i.PWM_DB_PolarityConfig), (88 bytes). + Removing plib035_pwm.o(i.PWM_DB_StructInit), (14 bytes). + Removing plib035_pwm.o(i.PWM_DeInit), (120 bytes). + Removing plib035_pwm.o(i.PWM_ET_DRQACmd), (80 bytes). + Removing plib035_pwm.o(i.PWM_ET_DRQAEventConfig), (100 bytes). + Removing plib035_pwm.o(i.PWM_ET_DRQAPeriodConfig), (80 bytes). + Removing plib035_pwm.o(i.PWM_ET_DRQBCmd), (80 bytes). + Removing plib035_pwm.o(i.PWM_ET_DRQBEventConfig), (100 bytes). + Removing plib035_pwm.o(i.PWM_ET_DRQBPeriodConfig), (80 bytes). + Removing plib035_pwm.o(i.PWM_ET_Init), (104 bytes). + Removing plib035_pwm.o(i.PWM_ET_SOCACmd), (80 bytes). + Removing plib035_pwm.o(i.PWM_ET_SOCAEventConfig), (100 bytes). + Removing plib035_pwm.o(i.PWM_ET_SOCAPeriodConfig), (80 bytes). + Removing plib035_pwm.o(i.PWM_ET_SOCBCmd), (80 bytes). + Removing plib035_pwm.o(i.PWM_ET_SOCBEventConfig), (100 bytes). + Removing plib035_pwm.o(i.PWM_ET_SOCBPeriodConfig), (80 bytes). + Removing plib035_pwm.o(i.PWM_ET_StructInit), (42 bytes). + Removing plib035_pwm.o(i.PWM_HD_ActionAConfig), (92 bytes). + Removing plib035_pwm.o(i.PWM_HD_ActionBConfig), (92 bytes). + Removing plib035_pwm.o(i.PWM_HD_CycleCmd), (84 bytes). + Removing plib035_pwm.o(i.PWM_HD_Init), (50 bytes). + Removing plib035_pwm.o(i.PWM_HD_OneShotCmd), (84 bytes). + Removing plib035_pwm.o(i.PWM_HD_SourceCmd), (96 bytes). + Removing plib035_pwm.o(i.PWM_HD_StructInit), (16 bytes). + Removing plib035_pwm.o(i.PWM_TB_ClkDivConfig), (192 bytes). + Removing plib035_pwm.o(i.PWM_TB_HaltConfig), (80 bytes). + Removing plib035_pwm.o(i.PWM_TB_Init), (236 bytes). + Removing plib035_pwm.o(i.PWM_TB_ModeConfig), (88 bytes). + Removing plib035_pwm.o(i.PWM_TB_PeriodDirectLoadCmd), (80 bytes). + Removing plib035_pwm.o(i.PWM_TB_PhaseSyncCmd), (80 bytes). + Removing plib035_pwm.o(i.PWM_TB_PhaseSyncDirConfig), (80 bytes). + Removing plib035_pwm.o(i.PWM_TB_StructInit), (24 bytes). + Removing plib035_pwm.o(i.PWM_TB_SyncOutConfig), (88 bytes). + Removing plib035_pwm.o(i.PWM_TZ_ActionAConfig), (88 bytes). + Removing plib035_pwm.o(i.PWM_TZ_ActionBConfig), (88 bytes). + Removing plib035_pwm.o(i.PWM_TZ_CycleCmd), (80 bytes). + Removing plib035_pwm.o(i.PWM_TZ_Init), (40 bytes). + Removing plib035_pwm.o(i.PWM_TZ_OneShotCmd), (80 bytes). + Removing plib035_pwm.o(i.PWM_TZ_StructInit), (12 bytes). + Removing plib035_pwm.o(i.RCU_APBRstCmd), (160 bytes). + Removing plib035_qep.o(.rev16_text), (4 bytes). + Removing plib035_qep.o(.revsh_text), (4 bytes). + Removing plib035_qep.o(.rrx_text), (6 bytes). + Removing plib035_qep.o(i.QEP_CAP_DivConfig), (136 bytes). + Removing plib035_qep.o(i.QEP_CAP_Init), (136 bytes). + Removing plib035_qep.o(i.QEP_CAP_StructInit), (18 bytes). + Removing plib035_qep.o(i.QEP_CMP_Init), (224 bytes). + Removing plib035_qep.o(i.QEP_CMP_StructInit), (18 bytes). + Removing plib035_qep.o(i.QEP_DeInit), (22 bytes). + Removing plib035_qep.o(i.QEP_PC_Init), (340 bytes). + Removing plib035_qep.o(i.QEP_PC_StructInit), (24 bytes). + Removing plib035_qep.o(i.RCU_APBRstCmd), (160 bytes). + Removing plib035_rcu.o(.rev16_text), (4 bytes). + Removing plib035_rcu.o(.revsh_text), (4 bytes). + Removing plib035_rcu.o(.rrx_text), (6 bytes). + Removing plib035_rcu.o(i.RCU_GetADCClkFreq), (56 bytes). + Removing plib035_rcu.o(i.RCU_GetClkOutFreq), (52 bytes). + Removing plib035_rcu.o(i.RCU_GetOSEClkFreq), (8 bytes). + Removing plib035_rcu.o(i.RCU_GetOSIClkFreq), (8 bytes). + Removing plib035_rcu.o(i.RCU_GetPLLClkFreq), (72 bytes). + Removing plib035_rcu.o(i.RCU_GetPLLDivClkFreq), (28 bytes). + Removing plib035_rcu.o(i.RCU_GetSPIClkFreq), (56 bytes). + Removing plib035_rcu.o(i.RCU_GetSysClkFreq), (28 bytes). + Removing plib035_rcu.o(i.RCU_GetTraceClkFreq), (52 bytes). + Removing plib035_rcu.o(i.RCU_GetUARTClkFreq), (60 bytes). + Removing plib035_rcu.o(i.RCU_GetWDTClkFreq), (52 bytes). + Removing plib035_rcu.o(i.RCU_PLL_DeInit), (24 bytes). + Removing plib035_rcu.o(i.getPeriphClkFreq), (60 bytes). + Removing plib035_rcu.o(i.getSysClkFreq), (60 bytes). + Removing plib035_rcu.o(i.getSysPeriphClkFreq), (60 bytes). + Removing plib035_spi.o(.rev16_text), (4 bytes). + Removing plib035_spi.o(.revsh_text), (4 bytes). + Removing plib035_spi.o(.rrx_text), (6 bytes). + Removing plib035_spi.o(i.RCU_SPIRstCmd), (84 bytes). + Removing plib035_spi.o(i.SPI_DataWidthConfig), (88 bytes). + Removing plib035_spi.o(i.SPI_DeInit), (16 bytes). + Removing plib035_spi.o(i.SPI_Init), (136 bytes). + Removing plib035_spi.o(i.SPI_SCKDivConfig), (72 bytes). + Removing plib035_spi.o(i.SPI_StructInit), (20 bytes). + Removing plib035_tmr.o(.rev16_text), (4 bytes). + Removing plib035_tmr.o(.revsh_text), (4 bytes). + Removing plib035_tmr.o(.rrx_text), (6 bytes). + Removing plib035_tmr.o(i.TMR_FreqConfig), (26 bytes). + Removing plib035_tmr.o(i.TMR_PeriodConfig), (36 bytes). + Removing plib035_tmr.o(i.TMR_SetLoad), (100 bytes). + Removing plib035_uart.o(.rev16_text), (4 bytes). + Removing plib035_uart.o(.revsh_text), (4 bytes). + Removing plib035_uart.o(.rrx_text), (6 bytes). + Removing plib035_uart.o(i.RCU_UARTRstCmd), (88 bytes). + Removing plib035_uart.o(i.UART_AutoBaudConfig), (184 bytes). + Removing plib035_uart.o(i.UART_BaudDivConfig), (88 bytes). + Removing plib035_uart.o(i.UART_DataWidthConfig), (112 bytes). + Removing plib035_uart.o(i.UART_DeInit), (100 bytes). + Removing plib035_uart.o(i.UART_FIFOCmd), (72 bytes). + Removing plib035_uart.o(i.UART_Init), (64 bytes). + Removing plib035_uart.o(i.UART_ParityBitConfig), (84 bytes). + Removing plib035_uart.o(i.UART_RxCmd), (72 bytes). + Removing plib035_uart.o(i.UART_StopBitConfig), (68 bytes). + Removing plib035_uart.o(i.UART_StructInit), (24 bytes). + Removing plib035_uart.o(i.UART_TxCmd), (72 bytes). + Removing plib035_wdt.o(.rev16_text), (4 bytes). + Removing plib035_wdt.o(.revsh_text), (4 bytes). + Removing plib035_wdt.o(.rrx_text), (6 bytes). + Removing retarget.o(.rev16_text), (4 bytes). + Removing retarget.o(.revsh_text), (4 bytes). + Removing retarget.o(.rrx_text), (6 bytes). + Removing retarget.o(i._ttywrch), (12 bytes). + Removing retarget.o(i.fgetc), (10 bytes). + Removing retarget_conf.o(.rev16_text), (4 bytes). + Removing retarget_conf.o(.revsh_text), (4 bytes). + Removing retarget_conf.o(.rrx_text), (6 bytes). + Removing retarget_conf.o(i.retarget_get_char), (28 bytes). + +331 unused section(s) (total 35598 bytes) removed from the image. + +============================================================================== + +Image Symbol Table + + Local Symbols + + Symbol Name Value Ov Type Size Object(Section) + + RESET 0x00000000 Section 344 startup_k1921vk035.o(RESET) + ../clib/angel/boardlib.s 0x00000000 Number 0 boardshut.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit1.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit2.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit3.o ABSOLUTE + ../clib/angel/dczerorl2.s 0x00000000 Number 0 __dczerorl2.o ABSOLUTE + ../clib/angel/handlers.s 0x00000000 Number 0 __scatter_zi.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry4.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 rtexit.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry2.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 rtexit2.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_div0.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_raise.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 aeabi_ldiv0.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 aeabi_ldiv0_sigfpe.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_errno_addr.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_errno_addr_intlibspace.o ABSOLUTE + ../clib/angel/scatter.s 0x00000000 Number 0 __scatter.o ABSOLUTE + ../clib/angel/startup.s 0x00000000 Number 0 __main.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 libspace.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 use_no_semi.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 sys_stackheap_outer.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 indicate_semi.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_command.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 no_argv.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 _get_argv_nomalloc.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 argv_veneer.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 argv_veneer.o ABSOLUTE + ../clib/fenv.c 0x00000000 Number 0 _rserrno.o ABSOLUTE + ../clib/heapalloc.c 0x00000000 Number 0 hrguard.o ABSOLUTE + ../clib/heapaux.c 0x00000000 Number 0 heapauxi.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libshutdown.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libshutdown2.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libinit.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libinit2.o ABSOLUTE + ../clib/longlong.s 0x00000000 Number 0 llsdiv.o ABSOLUTE + ../clib/longlong.s 0x00000000 Number 0 lludivv7m.o ABSOLUTE + ../clib/memcpset.s 0x00000000 Number 0 rt_memclr_w.o ABSOLUTE + ../clib/memcpset.s 0x00000000 Number 0 rt_memcpy_w.o ABSOLUTE + ../clib/memcpset.s 0x00000000 Number 0 rt_memcpy_v6.o ABSOLUTE + ../clib/misc.s 0x00000000 Number 0 printf_stubs.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_char_file.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_char.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_flags.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_ss.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_flags_ss.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_wp.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_dec.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_str.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_flags_wp.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_ss_wp.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_flags_ss_wp.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 noretval__2printf.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __2printf.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_pad.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_char_common.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_nopercent.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_intcommon.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_s.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_percent.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_percent_end.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_d.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_fpe_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_exit.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_formal.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_fpe_formal.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_fpe_outer.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_general.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_other.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_segv_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_cppl_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_pvfn_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_stak_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtred_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_abrt_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 __raise.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_outer.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_inner.o ABSOLUTE + ../clib/signal.s 0x00000000 Number 0 defsig.o ABSOLUTE + ../clib/stdlib.c 0x00000000 Number 0 exit.o ABSOLUTE + ../clib/stdlib.c 0x00000000 Number 0 qsortnoex.o ABSOLUTE + ../clib/stdlib.c 0x00000000 Number 0 rand.o ABSOLUTE + ../clib/stdlib.c 0x00000000 Number 0 rand.o ABSOLUTE + ../clib/string.c 0x00000000 Number 0 strlen.o ABSOLUTE + ../fplib/ddiv.s 0x00000000 Number 0 ddiv.o ABSOLUTE + ../fplib/dfix.s 0x00000000 Number 0 dfix.o ABSOLUTE + ../fplib/dflt.s 0x00000000 Number 0 dflt_clz.o ABSOLUTE + ../fplib/dnaninf.s 0x00000000 Number 0 dnaninf.o ABSOLUTE + ../fplib/dretinf.s 0x00000000 Number 0 dretinf.o ABSOLUTE + ../fplib/ffltll.s 0x00000000 Number 0 ffltll_clz.o ABSOLUTE + ../fplib/fpinit.s 0x00000000 Number 0 fpinit.o ABSOLUTE + ../fplib/usenofp.s 0x00000000 Number 0 usenofp.o ABSOLUTE + ../mathlib/cosf.c 0x00000000 Number 0 cosf.o ABSOLUTE + ../mathlib/cosf.c 0x00000000 Number 0 cosf_x.o ABSOLUTE + ../mathlib/fpclassifyf.c 0x00000000 Number 0 fpclassifyf.o ABSOLUTE + ../mathlib/funder.c 0x00000000 Number 0 funder.o ABSOLUTE + ../mathlib/rredf.c 0x00000000 Number 0 rredf.o ABSOLUTE + ../mathlib/sinf.c 0x00000000 Number 0 sinf_x.o ABSOLUTE + ../mathlib/sinf.c 0x00000000 Number 0 sinf.o ABSOLUTE + Core\App\gpio.c 0x00000000 Number 0 gpio.o ABSOLUTE + Core\App\main.c 0x00000000 Number 0 main.o ABSOLUTE + Core\App\rcu.c 0x00000000 Number 0 rcu.o ABSOLUTE + Core\App\vk035_it.c 0x00000000 Number 0 vk035_it.o ABSOLUTE + Core\ExtendedLibs\MyLibs\Src\filters.c 0x00000000 Number 0 filters.o ABSOLUTE + Core\ExtendedLibs\RTT\SEGGER_RTT.c 0x00000000 Number 0 segger_rtt.o ABSOLUTE + Core\ExtendedLibs\RTT\SEGGER_RTT_printf.c 0x00000000 Number 0 segger_rtt_printf.o ABSOLUTE + Core\\App\\gpio.c 0x00000000 Number 0 gpio.o ABSOLUTE + Core\\App\\main.c 0x00000000 Number 0 main.o ABSOLUTE + Core\\App\\rcu.c 0x00000000 Number 0 rcu.o ABSOLUTE + Core\\App\\vk035_it.c 0x00000000 Number 0 vk035_it.o ABSOLUTE + Core\\ExtendedLibs\\MyLibs\\Src\\filters.c 0x00000000 Number 0 filters.o ABSOLUTE + dc.s 0x00000000 Number 0 dc.o ABSOLUTE + platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1921VK035.s 0x00000000 Number 0 startup_k1921vk035.o ABSOLUTE + platform\Device\NIIET\K1921VK035\Source\system_K1921VK035.c 0x00000000 Number 0 system_k1921vk035.o ABSOLUTE + platform\\Device\\NIIET\\K1921VK035\\Source\\system_K1921VK035.c 0x00000000 Number 0 system_k1921vk035.o ABSOLUTE + platform\\plib035\\src\\plib035_adc.c 0x00000000 Number 0 plib035_adc.o ABSOLUTE + platform\\plib035\\src\\plib035_can.c 0x00000000 Number 0 plib035_can.o ABSOLUTE + platform\\plib035\\src\\plib035_dma.c 0x00000000 Number 0 plib035_dma.o ABSOLUTE + platform\\plib035\\src\\plib035_ecap.c 0x00000000 Number 0 plib035_ecap.o ABSOLUTE + platform\\plib035\\src\\plib035_gpio.c 0x00000000 Number 0 plib035_gpio.o ABSOLUTE + platform\\plib035\\src\\plib035_i2c.c 0x00000000 Number 0 plib035_i2c.o ABSOLUTE + platform\\plib035\\src\\plib035_mflash.c 0x00000000 Number 0 plib035_mflash.o ABSOLUTE + platform\\plib035\\src\\plib035_pmu.c 0x00000000 Number 0 plib035_pmu.o ABSOLUTE + platform\\plib035\\src\\plib035_pwm.c 0x00000000 Number 0 plib035_pwm.o ABSOLUTE + platform\\plib035\\src\\plib035_qep.c 0x00000000 Number 0 plib035_qep.o ABSOLUTE + platform\\plib035\\src\\plib035_rcu.c 0x00000000 Number 0 plib035_rcu.o ABSOLUTE + platform\\plib035\\src\\plib035_spi.c 0x00000000 Number 0 plib035_spi.o ABSOLUTE + platform\\plib035\\src\\plib035_tmr.c 0x00000000 Number 0 plib035_tmr.o ABSOLUTE + platform\\plib035\\src\\plib035_uart.c 0x00000000 Number 0 plib035_uart.o ABSOLUTE + platform\\plib035\\src\\plib035_wdt.c 0x00000000 Number 0 plib035_wdt.o ABSOLUTE + platform\\retarget\\retarget.c 0x00000000 Number 0 retarget.o ABSOLUTE + platform\\retarget\\retarget_conf.c 0x00000000 Number 0 retarget_conf.o ABSOLUTE + platform\plib035\src\plib035_adc.c 0x00000000 Number 0 plib035_adc.o ABSOLUTE + platform\plib035\src\plib035_can.c 0x00000000 Number 0 plib035_can.o ABSOLUTE + platform\plib035\src\plib035_dma.c 0x00000000 Number 0 plib035_dma.o ABSOLUTE + platform\plib035\src\plib035_ecap.c 0x00000000 Number 0 plib035_ecap.o ABSOLUTE + platform\plib035\src\plib035_gpio.c 0x00000000 Number 0 plib035_gpio.o ABSOLUTE + platform\plib035\src\plib035_i2c.c 0x00000000 Number 0 plib035_i2c.o ABSOLUTE + platform\plib035\src\plib035_mflash.c 0x00000000 Number 0 plib035_mflash.o ABSOLUTE + platform\plib035\src\plib035_pmu.c 0x00000000 Number 0 plib035_pmu.o ABSOLUTE + platform\plib035\src\plib035_pwm.c 0x00000000 Number 0 plib035_pwm.o ABSOLUTE + platform\plib035\src\plib035_qep.c 0x00000000 Number 0 plib035_qep.o ABSOLUTE + platform\plib035\src\plib035_rcu.c 0x00000000 Number 0 plib035_rcu.o ABSOLUTE + platform\plib035\src\plib035_spi.c 0x00000000 Number 0 plib035_spi.o ABSOLUTE + platform\plib035\src\plib035_tmr.c 0x00000000 Number 0 plib035_tmr.o ABSOLUTE + platform\plib035\src\plib035_uart.c 0x00000000 Number 0 plib035_uart.o ABSOLUTE + platform\plib035\src\plib035_wdt.c 0x00000000 Number 0 plib035_wdt.o ABSOLUTE + platform\retarget\retarget.c 0x00000000 Number 0 retarget.o ABSOLUTE + platform\retarget\retarget_conf.c 0x00000000 Number 0 retarget_conf.o ABSOLUTE + !!!main 0x00000158 Section 8 __main.o(!!!main) + !!!scatter 0x00000160 Section 52 __scatter.o(!!!scatter) + !!dczerorl2 0x00000194 Section 90 __dczerorl2.o(!!dczerorl2) + !!handler_zi 0x000001f0 Section 28 __scatter_zi.o(!!handler_zi) + .ARM.Collect$$_printf_percent$$00000000 0x0000020c Section 0 _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) + .ARM.Collect$$_printf_percent$$00000009 0x0000020c Section 6 _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) + .ARM.Collect$$_printf_percent$$00000014 0x00000212 Section 6 _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) + .ARM.Collect$$_printf_percent$$00000017 0x00000218 Section 4 _printf_percent_end.o(.ARM.Collect$$_printf_percent$$00000017) + .ARM.Collect$$libinit$$00000000 0x0000021c Section 2 libinit.o(.ARM.Collect$$libinit$$00000000) + .ARM.Collect$$libinit$$00000001 0x0000021e Section 4 libinit2.o(.ARM.Collect$$libinit$$00000001) + .ARM.Collect$$libinit$$00000004 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000004) + .ARM.Collect$$libinit$$0000000A 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000A) + .ARM.Collect$$libinit$$0000000C 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000C) + .ARM.Collect$$libinit$$0000000E 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000E) + .ARM.Collect$$libinit$$00000011 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000011) + .ARM.Collect$$libinit$$00000013 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000013) + .ARM.Collect$$libinit$$00000015 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000015) + .ARM.Collect$$libinit$$00000017 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000017) + .ARM.Collect$$libinit$$00000019 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000019) + .ARM.Collect$$libinit$$0000001B 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001B) + .ARM.Collect$$libinit$$0000001D 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001D) + .ARM.Collect$$libinit$$0000001F 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001F) + .ARM.Collect$$libinit$$00000021 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000021) + .ARM.Collect$$libinit$$00000023 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000023) + .ARM.Collect$$libinit$$00000025 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000025) + .ARM.Collect$$libinit$$0000002C 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000002C) + .ARM.Collect$$libinit$$0000002E 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000002E) + .ARM.Collect$$libinit$$00000030 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000030) + .ARM.Collect$$libinit$$00000032 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000032) + .ARM.Collect$$libinit$$00000033 0x00000222 Section 2 libinit2.o(.ARM.Collect$$libinit$$00000033) + .ARM.Collect$$libshutdown$$00000000 0x00000224 Section 2 libshutdown.o(.ARM.Collect$$libshutdown$$00000000) + .ARM.Collect$$libshutdown$$00000002 0x00000226 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) + .ARM.Collect$$libshutdown$$00000004 0x00000226 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) + .ARM.Collect$$libshutdown$$00000006 0x00000226 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000006) + .ARM.Collect$$libshutdown$$00000009 0x00000226 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000009) + .ARM.Collect$$libshutdown$$0000000C 0x00000226 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) + .ARM.Collect$$libshutdown$$0000000E 0x00000226 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000E) + .ARM.Collect$$libshutdown$$00000011 0x00000226 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000011) + .ARM.Collect$$libshutdown$$00000012 0x00000226 Section 2 libshutdown2.o(.ARM.Collect$$libshutdown$$00000012) + .ARM.Collect$$rtentry$$00000000 0x00000228 Section 0 __rtentry.o(.ARM.Collect$$rtentry$$00000000) + .ARM.Collect$$rtentry$$00000002 0x00000228 Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000002) + .ARM.Collect$$rtentry$$00000004 0x00000228 Section 6 __rtentry4.o(.ARM.Collect$$rtentry$$00000004) + .ARM.Collect$$rtentry$$00000009 0x0000022e Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000009) + .ARM.Collect$$rtentry$$0000000A 0x0000022e Section 4 __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) + .ARM.Collect$$rtentry$$0000000C 0x00000232 Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) + .ARM.Collect$$rtentry$$0000000D 0x00000232 Section 8 __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) + .ARM.Collect$$rtexit$$00000000 0x0000023a Section 2 rtexit.o(.ARM.Collect$$rtexit$$00000000) + .ARM.Collect$$rtexit$$00000002 0x0000023c Section 0 rtexit2.o(.ARM.Collect$$rtexit$$00000002) + .ARM.Collect$$rtexit$$00000003 0x0000023c Section 4 rtexit2.o(.ARM.Collect$$rtexit$$00000003) + .ARM.Collect$$rtexit$$00000004 0x00000240 Section 6 rtexit2.o(.ARM.Collect$$rtexit$$00000004) + .text 0x00000248 Section 64 startup_k1921vk035.o(.text) + $v0 0x00000248 Number 0 startup_k1921vk035.o(.text) + .text 0x00000288 Section 2 use_no_semi.o(.text) + .text 0x0000028c Section 0 noretval__2printf.o(.text) + .text 0x000002a4 Section 0 _printf_pad.o(.text) + .text 0x000002f2 Section 0 _printf_str.o(.text) + .text 0x00000344 Section 0 _printf_dec.o(.text) + .text 0x000003bc Section 0 __printf_wp.o(.text) + .text 0x000004ca Section 0 heapauxi.o(.text) + .text 0x000004d0 Section 0 _printf_intcommon.o(.text) + .text 0x00000582 Section 0 _printf_char.o(.text) + .text 0x000005b0 Section 0 _printf_char_file.o(.text) + .text 0x000005d4 Section 0 _printf_char_common.o(.text) + _printf_input_char 0x000005d5 Thumb Code 10 _printf_char_common.o(.text) + .text 0x00000604 Section 8 libspace.o(.text) + .text 0x0000060c Section 74 sys_stackheap_outer.o(.text) + .text 0x00000656 Section 0 exit.o(.text) + i.BusFault_Handler 0x00000668 Section 0 vk035_it.o(i.BusFault_Handler) + i.ClkInit 0x0000066c Section 0 system_k1921vk035.o(i.ClkInit) + i.DebugMon_Handler 0x00000710 Section 0 vk035_it.o(i.DebugMon_Handler) + i.Error_Handler 0x00000712 Section 0 main.o(i.Error_Handler) + i.FPUInit 0x00000718 Section 0 system_k1921vk035.o(i.FPUInit) + i.GPIO_AltFuncCmd 0x00000748 Section 0 plib035_gpio.o(i.GPIO_AltFuncCmd) + GPIO_AltFuncCmd 0x00000749 Thumb Code 82 plib035_gpio.o(i.GPIO_AltFuncCmd) + i.GPIO_DeInit 0x000007a8 Section 0 plib035_gpio.o(i.GPIO_DeInit) + i.GPIO_DigitalCmd 0x0000080c Section 0 plib035_gpio.o(i.GPIO_DigitalCmd) + GPIO_DigitalCmd 0x0000080d Thumb Code 82 plib035_gpio.o(i.GPIO_DigitalCmd) + i.GPIO_DriveModeConfig 0x00000890 Section 0 plib035_gpio.o(i.GPIO_DriveModeConfig) + i.GPIO_InModeConfig 0x00000914 Section 0 plib035_gpio.o(i.GPIO_InModeConfig) + i.GPIO_Init 0x00000994 Section 0 plib035_gpio.o(i.GPIO_Init) + i.GPIO_ModeConfig 0x000009e2 Section 0 plib035_gpio.o(i.GPIO_ModeConfig) + GPIO_ModeConfig 0x000009e3 Thumb Code 46 plib035_gpio.o(i.GPIO_ModeConfig) + i.GPIO_OutCmd 0x00000a10 Section 0 plib035_gpio.o(i.GPIO_OutCmd) + GPIO_OutCmd 0x00000a11 Thumb Code 82 plib035_gpio.o(i.GPIO_OutCmd) + i.GPIO_OutModeConfig 0x00000a70 Section 0 plib035_gpio.o(i.GPIO_OutModeConfig) + i.GPIO_PullModeConfig 0x00000af0 Section 0 plib035_gpio.o(i.GPIO_PullModeConfig) + i.HardFault_Handler 0x00000b70 Section 0 vk035_it.o(i.HardFault_Handler) + i.MFLASH_LatencyConfig 0x00000b74 Section 0 plib035_rcu.o(i.MFLASH_LatencyConfig) + MFLASH_LatencyConfig 0x00000b75 Thumb Code 32 plib035_rcu.o(i.MFLASH_LatencyConfig) + i.MemManage_Handler 0x00000bc0 Section 0 vk035_it.o(i.MemManage_Handler) + i.NMI_Handler 0x00000bc4 Section 0 vk035_it.o(i.NMI_Handler) + i.PendSV_Handler 0x00000bc8 Section 0 vk035_it.o(i.PendSV_Handler) + i.RCU_AHBClkCmd 0x00000bcc Section 0 gpio.o(i.RCU_AHBClkCmd) + RCU_AHBClkCmd 0x00000bcd Thumb Code 70 gpio.o(i.RCU_AHBClkCmd) + i.RCU_AHBRstCmd 0x00000c40 Section 0 gpio.o(i.RCU_AHBRstCmd) + RCU_AHBRstCmd 0x00000c41 Thumb Code 70 gpio.o(i.RCU_AHBRstCmd) + i.RCU_AHBRstCmd 0x00000c90 Section 0 plib035_gpio.o(i.RCU_AHBRstCmd) + RCU_AHBRstCmd 0x00000c91 Thumb Code 70 plib035_gpio.o(i.RCU_AHBRstCmd) + i.RCU_ClkOutConfig 0x00000d04 Section 0 rcu.o(i.RCU_ClkOutConfig) + RCU_ClkOutConfig 0x00000d05 Thumb Code 96 rcu.o(i.RCU_ClkOutConfig) + i.RCU_PLL_AutoConfig 0x00000d70 Section 0 plib035_rcu.o(i.RCU_PLL_AutoConfig) + i.RCU_PLL_Init 0x00000f18 Section 0 plib035_rcu.o(i.RCU_PLL_Init) + i.RCU_PLL_OutCmd 0x00001040 Section 0 plib035_rcu.o(i.RCU_PLL_OutCmd) + RCU_PLL_OutCmd 0x00001041 Thumb Code 36 plib035_rcu.o(i.RCU_PLL_OutCmd) + i.RCU_PLL_StructInit 0x00001090 Section 0 plib035_rcu.o(i.RCU_PLL_StructInit) + i.RCU_SysClkChangeCmd 0x000010a0 Section 0 plib035_rcu.o(i.RCU_SysClkChangeCmd) + i.SVC_Handler 0x00001174 Section 0 vk035_it.o(i.SVC_Handler) + i.SysTick_Handler 0x00001178 Section 0 vk035_it.o(i.SysTick_Handler) + i.SystemCoreClockUpdate 0x00001188 Section 0 system_k1921vk035.o(i.SystemCoreClockUpdate) + i.SystemInit 0x00001218 Section 0 system_k1921vk035.o(i.SystemInit) + i.UsageFault_Handler 0x00001224 Section 0 vk035_it.o(i.UsageFault_Handler) + i._is_digit 0x00001228 Section 0 __printf_wp.o(i._is_digit) + i._sys_exit 0x00001236 Section 0 retarget.o(i._sys_exit) + i.assert_failed 0x0000123c Section 0 main.o(i.assert_failed) + i.ferror 0x00001274 Section 0 retarget.o(i.ferror) + i.fputc 0x0000127c Section 0 retarget.o(i.fputc) + i.gpio_init 0x0000128c Section 0 gpio.o(i.gpio_init) + i.main 0x000012f0 Section 0 main.o(i.main) + i.periph_init 0x000012f8 Section 0 main.o(i.periph_init) + i.retarget_init 0x00001378 Section 0 retarget_conf.o(i.retarget_init) + i.retarget_put_char 0x0000145c Section 0 retarget_conf.o(i.retarget_put_char) + i.sysclk_init 0x00001478 Section 0 rcu.o(i.sysclk_init) + x$fpl$ddiv 0x00001554 Section 688 ddiv.o(x$fpl$ddiv) + $v0 0x00001554 Number 0 ddiv.o(x$fpl$ddiv) + ddiv_entry 0x0000155b Thumb Code 0 ddiv.o(x$fpl$ddiv) + x$fpl$dfix 0x00001804 Section 94 dfix.o(x$fpl$dfix) + $v0 0x00001804 Number 0 dfix.o(x$fpl$dfix) + x$fpl$dfltu 0x00001862 Section 38 dflt_clz.o(x$fpl$dfltu) + $v0 0x00001862 Number 0 dflt_clz.o(x$fpl$dfltu) + x$fpl$dnaninf 0x00001888 Section 156 dnaninf.o(x$fpl$dnaninf) + $v0 0x00001888 Number 0 dnaninf.o(x$fpl$dnaninf) + x$fpl$dretinf 0x00001924 Section 12 dretinf.o(x$fpl$dretinf) + $v0 0x00001924 Number 0 dretinf.o(x$fpl$dretinf) + x$fpl$fpinit 0x00001930 Section 10 fpinit.o(x$fpl$fpinit) + $v0 0x00001930 Number 0 fpinit.o(x$fpl$fpinit) + x$fpl$usenofp 0x0000193a Section 0 usenofp.o(x$fpl$usenofp) + .data 0x20000000 Section 392 gpio.o(.data) + dummy 0x20000000 Data 4 gpio.o(.data) + g_sort_opt 0x20000004 Data 4 gpio.o(.data) + gpioa_config 0x20000008 Data 192 gpio.o(.data) + gpiob_config 0x200000c8 Data 192 gpio.o(.data) + .data 0x20000188 Section 9 rcu.o(.data) + dummy 0x20000188 Data 4 rcu.o(.data) + g_sort_opt 0x2000018c Data 4 rcu.o(.data) + OS_Type 0x20000190 Data 1 rcu.o(.data) + .data 0x20000194 Section 8 system_k1921vk035.o(.data) + .data 0x2000019c Section 8 retarget.o(.data) + .bss 0x200001a4 Section 96 libspace.o(.bss) + HEAP 0x20000208 Section 512 startup_k1921vk035.o(HEAP) + Heap_Mem 0x20000208 Data 512 startup_k1921vk035.o(HEAP) + STACK 0x20000408 Section 1024 startup_k1921vk035.o(STACK) + Stack_Mem 0x20000408 Data 1024 startup_k1921vk035.o(STACK) + __initial_sp 0x20000808 Data 0 startup_k1921vk035.o(STACK) + + Global Symbols + + Symbol Name Value Ov Type Size Object(Section) + + BuildAttributes$$THM_ISAv4$E$P$D$K$B$S$7EM$VFPi3$EXTD16$VFPS$VFMA$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OTIME$ROPI$IEEEX$EBA8$UX$STANDARDLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE + __ARM_use_no_argv 0x00000000 Number 0 main.o ABSOLUTE + __Vectors 0x00000000 Data 4 startup_k1921vk035.o(RESET) + _printf_flags 0x00000000 Number 0 printf_stubs.o ABSOLUTE + _printf_return_value 0x00000000 Number 0 printf_stubs.o ABSOLUTE + _printf_sizespec 0x00000000 Number 0 printf_stubs.o ABSOLUTE + _printf_widthprec 0x00000000 Number 0 printf_stubs.o ABSOLUTE + __ARM_exceptions_init - Undefined Weak Reference + __alloca_initialize - Undefined Weak Reference + __arm_fini_ - Undefined Weak Reference + __arm_preinit_ - Undefined Weak Reference + __cpp_initialize__aeabi_ - Undefined Weak Reference + __cxa_finalize - Undefined Weak Reference + __rt_locale - Undefined Weak Reference + __sigvec_lookup - Undefined Weak Reference + _atexit_init - Undefined Weak Reference + _call_atexit_fns - Undefined Weak Reference + _clock_init - Undefined Weak Reference + _fp_trap_init - Undefined Weak Reference + _fp_trap_shutdown - Undefined Weak Reference + _get_lc_collate - Undefined Weak Reference + _get_lc_ctype - Undefined Weak Reference + _get_lc_monetary - Undefined Weak Reference + _get_lc_numeric - Undefined Weak Reference + _get_lc_time - Undefined Weak Reference + _getenv_init - Undefined Weak Reference + _handle_redirection - Undefined Weak Reference + _init_alloc - Undefined Weak Reference + _init_user_alloc - Undefined Weak Reference + _initio - Undefined Weak Reference + _printf_mbtowc - Undefined Weak Reference + _printf_truncate_signed - Undefined Weak Reference + _printf_truncate_unsigned - Undefined Weak Reference + _signal_finish - Undefined Weak Reference + _signal_init - Undefined Weak Reference + _terminate_alloc - Undefined Weak Reference + _terminate_user_alloc - Undefined Weak Reference + _terminateio - Undefined Weak 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libinit2.o(.ARM.Collect$$libinit$$00000025) + __rt_lib_init_user_alloc_1 0x00000223 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000C) + __rt_lib_shutdown 0x00000225 Thumb Code 0 libshutdown.o(.ARM.Collect$$libshutdown$$00000000) + __rt_lib_shutdown_cpp_1 0x00000227 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) + __rt_lib_shutdown_fini_1 0x00000227 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) + __rt_lib_shutdown_fp_trap_1 0x00000227 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000009) + __rt_lib_shutdown_heap_1 0x00000227 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000011) + __rt_lib_shutdown_return 0x00000227 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000012) + __rt_lib_shutdown_signal_1 0x00000227 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) + __rt_lib_shutdown_stdio_1 0x00000227 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000006) + __rt_lib_shutdown_user_alloc_1 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rtexit2.o(.ARM.Collect$$rtexit$$00000004) + Reset_Handler 0x00000249 Thumb Code 8 startup_k1921vk035.o(.text) + ADC_DC_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + ADC_SEQ0_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + ADC_SEQ1_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + CAN0_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + CAN10_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + CAN11_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + CAN12_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + CAN13_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + CAN14_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + CAN15_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + CAN1_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + CAN2_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + CAN3_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + CAN4_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + CAN5_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + CAN6_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + CAN7_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + CAN8_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + CAN9_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH0_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH10_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH11_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH12_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH13_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH14_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH15_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH1_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH2_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH3_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH4_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH5_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH6_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH7_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH8_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH9_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + ECAP0_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + ECAP1_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + ECAP2_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + FPU_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + GPIOA_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + GPIOB_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + I2C_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + MFLASH_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + PWM0_HD_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + PWM0_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + PWM0_TZ_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + PWM1_HD_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + PWM1_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + PWM1_TZ_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + PWM2_HD_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + PWM2_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + PWM2_TZ_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + QEP_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + RCU_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + SPI_RO_RT_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + SPI_RX_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + SPI_TX_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + TMR0_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + TMR1_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + TMR2_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + TMR3_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + UART0_E_RT_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + UART0_RX_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + UART0_TD_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + UART0_TX_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + UART1_E_RT_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + UART1_RX_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + UART1_TD_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + UART1_TX_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + WDT_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + __user_initial_stackheap 0x00000265 Thumb Code 0 startup_k1921vk035.o(.text) + __I$use$semihosting 0x00000289 Thumb Code 0 use_no_semi.o(.text) + __use_no_semihosting_swi 0x00000289 Thumb Code 2 use_no_semi.o(.text) + __2printf 0x0000028d Thumb Code 20 noretval__2printf.o(.text) + _printf_pre_padding 0x000002a5 Thumb Code 44 _printf_pad.o(.text) + _printf_post_padding 0x000002d1 Thumb Code 34 _printf_pad.o(.text) + _printf_str 0x000002f3 Thumb Code 82 _printf_str.o(.text) + _printf_int_dec 0x00000345 Thumb Code 104 _printf_dec.o(.text) + __printf 0x000003bd Thumb Code 270 __printf_wp.o(.text) + __use_two_region_memory 0x000004cb Thumb Code 2 heapauxi.o(.text) + __rt_heap_escrow$2region 0x000004cd Thumb Code 2 heapauxi.o(.text) + __rt_heap_expand$2region 0x000004cf Thumb Code 2 heapauxi.o(.text) + _printf_int_common 0x000004d1 Thumb Code 178 _printf_intcommon.o(.text) + _printf_cs_common 0x00000583 Thumb Code 20 _printf_char.o(.text) + _printf_char 0x00000597 Thumb Code 16 _printf_char.o(.text) + _printf_string 0x000005a7 Thumb Code 8 _printf_char.o(.text) + _printf_char_file 0x000005b1 Thumb Code 32 _printf_char_file.o(.text) + _printf_char_common 0x000005df Thumb Code 32 _printf_char_common.o(.text) + __user_libspace 0x00000605 Thumb Code 8 libspace.o(.text) + __user_perproc_libspace 0x00000605 Thumb Code 0 libspace.o(.text) + __user_perthread_libspace 0x00000605 Thumb Code 0 libspace.o(.text) + __user_setup_stackheap 0x0000060d Thumb Code 74 sys_stackheap_outer.o(.text) + exit 0x00000657 Thumb Code 18 exit.o(.text) + BusFault_Handler 0x00000669 Thumb Code 4 vk035_it.o(i.BusFault_Handler) + ClkInit 0x0000066d Thumb Code 154 system_k1921vk035.o(i.ClkInit) + DebugMon_Handler 0x00000711 Thumb Code 2 vk035_it.o(i.DebugMon_Handler) + Error_Handler 0x00000713 Thumb Code 6 main.o(i.Error_Handler) + FPUInit 0x00000719 Thumb Code 42 system_k1921vk035.o(i.FPUInit) + GPIO_DeInit 0x000007a9 Thumb Code 56 plib035_gpio.o(i.GPIO_DeInit) + GPIO_DriveModeConfig 0x00000891 Thumb Code 86 plib035_gpio.o(i.GPIO_DriveModeConfig) + GPIO_InModeConfig 0x00000915 Thumb Code 82 plib035_gpio.o(i.GPIO_InModeConfig) + GPIO_Init 0x00000995 Thumb Code 78 plib035_gpio.o(i.GPIO_Init) + GPIO_OutModeConfig 0x00000a71 Thumb Code 82 plib035_gpio.o(i.GPIO_OutModeConfig) + GPIO_PullModeConfig 0x00000af1 Thumb Code 82 plib035_gpio.o(i.GPIO_PullModeConfig) + HardFault_Handler 0x00000b71 Thumb Code 4 vk035_it.o(i.HardFault_Handler) + MemManage_Handler 0x00000bc1 Thumb Code 4 vk035_it.o(i.MemManage_Handler) + NMI_Handler 0x00000bc5 Thumb Code 4 vk035_it.o(i.NMI_Handler) + PendSV_Handler 0x00000bc9 Thumb Code 2 vk035_it.o(i.PendSV_Handler) + RCU_PLL_AutoConfig 0x00000d71 Thumb Code 374 plib035_rcu.o(i.RCU_PLL_AutoConfig) + RCU_PLL_Init 0x00000f19 Thumb Code 250 plib035_rcu.o(i.RCU_PLL_Init) + RCU_PLL_StructInit 0x00001091 Thumb Code 16 plib035_rcu.o(i.RCU_PLL_StructInit) + RCU_SysClkChangeCmd 0x000010a1 Thumb Code 130 plib035_rcu.o(i.RCU_SysClkChangeCmd) + SVC_Handler 0x00001175 Thumb Code 2 vk035_it.o(i.SVC_Handler) + SysTick_Handler 0x00001179 Thumb Code 12 vk035_it.o(i.SysTick_Handler) + SystemCoreClockUpdate 0x00001189 Thumb Code 126 system_k1921vk035.o(i.SystemCoreClockUpdate) + SystemInit 0x00001219 Thumb Code 12 system_k1921vk035.o(i.SystemInit) + UsageFault_Handler 0x00001225 Thumb Code 4 vk035_it.o(i.UsageFault_Handler) + _is_digit 0x00001229 Thumb Code 14 __printf_wp.o(i._is_digit) + _sys_exit 0x00001237 Thumb Code 4 retarget.o(i._sys_exit) + assert_failed 0x0000123d Thumb Code 18 main.o(i.assert_failed) + ferror 0x00001275 Thumb Code 8 retarget.o(i.ferror) + fputc 0x0000127d Thumb Code 14 retarget.o(i.fputc) + gpio_init 0x0000128d Thumb Code 84 gpio.o(i.gpio_init) + main 0x000012f1 Thumb Code 8 main.o(i.main) + periph_init 0x000012f9 Thumb Code 70 main.o(i.periph_init) + retarget_init 0x00001379 Thumb Code 198 retarget_conf.o(i.retarget_init) + retarget_put_char 0x0000145d Thumb Code 24 retarget_conf.o(i.retarget_put_char) + sysclk_init 0x00001479 Thumb Code 152 rcu.o(i.sysclk_init) + __aeabi_ddiv 0x00001555 Thumb Code 0 ddiv.o(x$fpl$ddiv) + _ddiv 0x00001555 Thumb Code 552 ddiv.o(x$fpl$ddiv) + __aeabi_d2iz 0x00001805 Thumb Code 0 dfix.o(x$fpl$dfix) + _dfix 0x00001805 Thumb Code 94 dfix.o(x$fpl$dfix) + __aeabi_ui2d 0x00001863 Thumb Code 0 dflt_clz.o(x$fpl$dfltu) + _dfltu 0x00001863 Thumb Code 38 dflt_clz.o(x$fpl$dfltu) + __fpl_dnaninf 0x00001889 Thumb Code 156 dnaninf.o(x$fpl$dnaninf) + __fpl_dretinf 0x00001925 Thumb Code 12 dretinf.o(x$fpl$dretinf) + _fp_init 0x00001931 Thumb Code 10 fpinit.o(x$fpl$fpinit) + __fplib_config_fpu_vfp 0x00001939 Thumb Code 0 fpinit.o(x$fpl$fpinit) + __fplib_config_pureend_doubles 0x00001939 Thumb Code 0 fpinit.o(x$fpl$fpinit) + __I$use$fp 0x0000193a Number 0 usenofp.o(x$fpl$usenofp) + Region$$Table$$Base 0x0000193c Number 0 anon$$obj.o(Region$$Table) + Region$$Table$$Limit 0x0000195c Number 0 anon$$obj.o(Region$$Table) + SystemCoreClock 0x20000194 Data 4 system_k1921vk035.o(.data) + uwTick 0x20000198 Data 4 system_k1921vk035.o(.data) + __stdout 0x2000019c Data 4 retarget.o(.data) + __stdin 0x200001a0 Data 4 retarget.o(.data) + __libspace_start 0x200001a4 Data 96 libspace.o(.bss) + __temporary_stack_top$libspace 0x20000204 Data 0 libspace.o(.bss) + + + +============================================================================== + +Memory Map of the image + + Image Entry point : 0x00000249 + + Load Region LR_1 (Base: 0x00000000, Size: 0x00001b00, Max: 0xffffffff, ABSOLUTE, COMPRESSED[0x00001980]) + + Execution Region ER_RO (Exec base: 0x00000000, Load base: 0x00000000, Size: 0x0000195c, Max: 0xffffffff, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x00000000 0x00000000 0x00000158 Data RO 926 RESET startup_k1921vk035.o + 0x00000158 0x00000158 0x00000008 Code RO 2411 * !!!main c_w.l(__main.o) + 0x00000160 0x00000160 0x00000034 Code RO 2660 !!!scatter c_w.l(__scatter.o) + 0x00000194 0x00000194 0x0000005a Code RO 2658 !!dczerorl2 c_w.l(__dczerorl2.o) + 0x000001ee 0x000001ee 0x00000002 PAD + 0x000001f0 0x000001f0 0x0000001c Code RO 2662 !!handler_zi c_w.l(__scatter_zi.o) + 0x0000020c 0x0000020c 0x00000000 Code RO 2393 .ARM.Collect$$_printf_percent$$00000000 c_w.l(_printf_percent.o) + 0x0000020c 0x0000020c 0x00000006 Code RO 2392 .ARM.Collect$$_printf_percent$$00000009 c_w.l(_printf_d.o) + 0x00000212 0x00000212 0x00000006 Code RO 2391 .ARM.Collect$$_printf_percent$$00000014 c_w.l(_printf_s.o) + 0x00000218 0x00000218 0x00000004 Code RO 2464 .ARM.Collect$$_printf_percent$$00000017 c_w.l(_printf_percent_end.o) + 0x0000021c 0x0000021c 0x00000002 Code RO 2584 .ARM.Collect$$libinit$$00000000 c_w.l(libinit.o) + 0x0000021e 0x0000021e 0x00000004 Code RO 2465 .ARM.Collect$$libinit$$00000001 c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 2468 .ARM.Collect$$libinit$$00000004 c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 2471 .ARM.Collect$$libinit$$0000000A c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 2473 .ARM.Collect$$libinit$$0000000C c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 2475 .ARM.Collect$$libinit$$0000000E c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 2478 .ARM.Collect$$libinit$$00000011 c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 2480 .ARM.Collect$$libinit$$00000013 c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 2482 .ARM.Collect$$libinit$$00000015 c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 2484 .ARM.Collect$$libinit$$00000017 c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 2486 .ARM.Collect$$libinit$$00000019 c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 2488 .ARM.Collect$$libinit$$0000001B c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 2490 .ARM.Collect$$libinit$$0000001D c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 2492 .ARM.Collect$$libinit$$0000001F c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 2494 .ARM.Collect$$libinit$$00000021 c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 2496 .ARM.Collect$$libinit$$00000023 c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 2498 .ARM.Collect$$libinit$$00000025 c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 2502 .ARM.Collect$$libinit$$0000002C c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 2504 .ARM.Collect$$libinit$$0000002E c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 2506 .ARM.Collect$$libinit$$00000030 c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 2508 .ARM.Collect$$libinit$$00000032 c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000002 Code RO 2509 .ARM.Collect$$libinit$$00000033 c_w.l(libinit2.o) + 0x00000224 0x00000224 0x00000002 Code RO 2621 .ARM.Collect$$libshutdown$$00000000 c_w.l(libshutdown.o) + 0x00000226 0x00000226 0x00000000 Code RO 2625 .ARM.Collect$$libshutdown$$00000002 c_w.l(libshutdown2.o) + 0x00000226 0x00000226 0x00000000 Code RO 2627 .ARM.Collect$$libshutdown$$00000004 c_w.l(libshutdown2.o) + 0x00000226 0x00000226 0x00000000 Code RO 2629 .ARM.Collect$$libshutdown$$00000006 c_w.l(libshutdown2.o) + 0x00000226 0x00000226 0x00000000 Code RO 2632 .ARM.Collect$$libshutdown$$00000009 c_w.l(libshutdown2.o) + 0x00000226 0x00000226 0x00000000 Code RO 2635 .ARM.Collect$$libshutdown$$0000000C c_w.l(libshutdown2.o) + 0x00000226 0x00000226 0x00000000 Code RO 2637 .ARM.Collect$$libshutdown$$0000000E c_w.l(libshutdown2.o) + 0x00000226 0x00000226 0x00000000 Code RO 2640 .ARM.Collect$$libshutdown$$00000011 c_w.l(libshutdown2.o) + 0x00000226 0x00000226 0x00000002 Code RO 2641 .ARM.Collect$$libshutdown$$00000012 c_w.l(libshutdown2.o) + 0x00000228 0x00000228 0x00000000 Code RO 2453 .ARM.Collect$$rtentry$$00000000 c_w.l(__rtentry.o) + 0x00000228 0x00000228 0x00000000 Code RO 2535 .ARM.Collect$$rtentry$$00000002 c_w.l(__rtentry2.o) + 0x00000228 0x00000228 0x00000006 Code RO 2547 .ARM.Collect$$rtentry$$00000004 c_w.l(__rtentry4.o) + 0x0000022e 0x0000022e 0x00000000 Code RO 2537 .ARM.Collect$$rtentry$$00000009 c_w.l(__rtentry2.o) + 0x0000022e 0x0000022e 0x00000004 Code RO 2538 .ARM.Collect$$rtentry$$0000000A c_w.l(__rtentry2.o) + 0x00000232 0x00000232 0x00000000 Code RO 2540 .ARM.Collect$$rtentry$$0000000C c_w.l(__rtentry2.o) + 0x00000232 0x00000232 0x00000008 Code RO 2541 .ARM.Collect$$rtentry$$0000000D c_w.l(__rtentry2.o) + 0x0000023a 0x0000023a 0x00000002 Code RO 2587 .ARM.Collect$$rtexit$$00000000 c_w.l(rtexit.o) + 0x0000023c 0x0000023c 0x00000000 Code RO 2601 .ARM.Collect$$rtexit$$00000002 c_w.l(rtexit2.o) + 0x0000023c 0x0000023c 0x00000004 Code RO 2602 .ARM.Collect$$rtexit$$00000003 c_w.l(rtexit2.o) + 0x00000240 0x00000240 0x00000006 Code RO 2603 .ARM.Collect$$rtexit$$00000004 c_w.l(rtexit2.o) + 0x00000246 0x00000246 0x00000002 PAD + 0x00000248 0x00000248 0x00000040 Code RO 927 * .text startup_k1921vk035.o + 0x00000288 0x00000288 0x00000002 Code RO 2355 .text c_w.l(use_no_semi.o) + 0x0000028a 0x0000028a 0x00000002 PAD + 0x0000028c 0x0000028c 0x00000018 Code RO 2361 .text c_w.l(noretval__2printf.o) + 0x000002a4 0x000002a4 0x0000004e Code RO 2365 .text c_w.l(_printf_pad.o) + 0x000002f2 0x000002f2 0x00000052 Code RO 2367 .text c_w.l(_printf_str.o) + 0x00000344 0x00000344 0x00000078 Code RO 2369 .text c_w.l(_printf_dec.o) + 0x000003bc 0x000003bc 0x0000010e Code RO 2379 .text c_w.l(__printf_wp.o) + 0x000004ca 0x000004ca 0x00000006 Code RO 2409 .text c_w.l(heapauxi.o) + 0x000004d0 0x000004d0 0x000000b2 Code RO 2458 .text c_w.l(_printf_intcommon.o) + 0x00000582 0x00000582 0x0000002c Code RO 2460 .text c_w.l(_printf_char.o) + 0x000005ae 0x000005ae 0x00000002 PAD + 0x000005b0 0x000005b0 0x00000024 Code RO 2462 .text c_w.l(_printf_char_file.o) + 0x000005d4 0x000005d4 0x00000030 Code RO 2558 .text c_w.l(_printf_char_common.o) + 0x00000604 0x00000604 0x00000008 Code RO 2564 .text c_w.l(libspace.o) + 0x0000060c 0x0000060c 0x0000004a Code RO 2567 .text c_w.l(sys_stackheap_outer.o) + 0x00000656 0x00000656 0x00000012 Code RO 2573 .text c_w.l(exit.o) + 0x00000668 0x00000668 0x00000004 Code RO 322 i.BusFault_Handler vk035_it.o + 0x0000066c 0x0000066c 0x000000a4 Code RO 879 i.ClkInit system_k1921vk035.o + 0x00000710 0x00000710 0x00000002 Code RO 323 i.DebugMon_Handler vk035_it.o + 0x00000712 0x00000712 0x00000006 Code RO 4 i.Error_Handler main.o + 0x00000718 0x00000718 0x00000030 Code RO 880 i.FPUInit system_k1921vk035.o + 0x00000748 0x00000748 0x00000060 Code RO 1334 i.GPIO_AltFuncCmd plib035_gpio.o + 0x000007a8 0x000007a8 0x00000064 Code RO 1335 i.GPIO_DeInit plib035_gpio.o + 0x0000080c 0x0000080c 0x00000084 Code RO 1336 i.GPIO_DigitalCmd plib035_gpio.o + 0x00000890 0x00000890 0x00000084 Code RO 1337 i.GPIO_DriveModeConfig plib035_gpio.o + 0x00000914 0x00000914 0x00000080 Code RO 1338 i.GPIO_InModeConfig plib035_gpio.o + 0x00000994 0x00000994 0x0000004e Code RO 1339 i.GPIO_Init plib035_gpio.o + 0x000009e2 0x000009e2 0x0000002e Code RO 1340 i.GPIO_ModeConfig plib035_gpio.o + 0x00000a10 0x00000a10 0x00000060 Code RO 1341 i.GPIO_OutCmd plib035_gpio.o + 0x00000a70 0x00000a70 0x00000080 Code RO 1342 i.GPIO_OutModeConfig plib035_gpio.o + 0x00000af0 0x00000af0 0x00000080 Code RO 1343 i.GPIO_PullModeConfig plib035_gpio.o + 0x00000b70 0x00000b70 0x00000004 Code RO 326 i.HardFault_Handler vk035_it.o + 0x00000b74 0x00000b74 0x0000004c Code RO 1910 i.MFLASH_LatencyConfig plib035_rcu.o + 0x00000bc0 0x00000bc0 0x00000004 Code RO 327 i.MemManage_Handler vk035_it.o + 0x00000bc4 0x00000bc4 0x00000004 Code RO 328 i.NMI_Handler vk035_it.o + 0x00000bc8 0x00000bc8 0x00000002 Code RO 329 i.PendSV_Handler vk035_it.o + 0x00000bca 0x00000bca 0x00000002 PAD + 0x00000bcc 0x00000bcc 0x00000074 Code RO 215 i.RCU_AHBClkCmd gpio.o + 0x00000c40 0x00000c40 0x00000050 Code RO 216 i.RCU_AHBRstCmd gpio.o + 0x00000c90 0x00000c90 0x00000074 Code RO 1345 i.RCU_AHBRstCmd plib035_gpio.o + 0x00000d04 0x00000d04 0x0000006c Code RO 270 i.RCU_ClkOutConfig rcu.o + 0x00000d70 0x00000d70 0x000001a8 Code RO 1922 i.RCU_PLL_AutoConfig plib035_rcu.o + 0x00000f18 0x00000f18 0x00000128 Code RO 1924 i.RCU_PLL_Init plib035_rcu.o + 0x00001040 0x00001040 0x00000050 Code RO 1925 i.RCU_PLL_OutCmd plib035_rcu.o + 0x00001090 0x00001090 0x00000010 Code RO 1926 i.RCU_PLL_StructInit plib035_rcu.o + 0x000010a0 0x000010a0 0x000000d4 Code RO 1927 i.RCU_SysClkChangeCmd plib035_rcu.o + 0x00001174 0x00001174 0x00000002 Code RO 330 i.SVC_Handler vk035_it.o + 0x00001176 0x00001176 0x00000002 PAD + 0x00001178 0x00001178 0x00000010 Code RO 331 i.SysTick_Handler vk035_it.o + 0x00001188 0x00001188 0x00000090 Code RO 881 i.SystemCoreClockUpdate system_k1921vk035.o + 0x00001218 0x00001218 0x0000000c Code RO 882 i.SystemInit system_k1921vk035.o + 0x00001224 0x00001224 0x00000004 Code RO 332 i.UsageFault_Handler vk035_it.o + 0x00001228 0x00001228 0x0000000e Code RO 2381 i._is_digit c_w.l(__printf_wp.o) + 0x00001236 0x00001236 0x00000004 Code RO 2256 i._sys_exit retarget.o + 0x0000123a 0x0000123a 0x00000002 PAD + 0x0000123c 0x0000123c 0x00000038 Code RO 7 i.assert_failed main.o + 0x00001274 0x00001274 0x00000008 Code RO 2258 i.ferror retarget.o + 0x0000127c 0x0000127c 0x0000000e Code RO 2260 i.fputc retarget.o + 0x0000128a 0x0000128a 0x00000002 PAD + 0x0000128c 0x0000128c 0x00000064 Code RO 218 i.gpio_init gpio.o + 0x000012f0 0x000012f0 0x00000008 Code RO 9 i.main main.o + 0x000012f8 0x000012f8 0x00000080 Code RO 10 i.periph_init main.o + 0x00001378 0x00001378 0x000000e4 Code RO 2321 i.retarget_init retarget_conf.o + 0x0000145c 0x0000145c 0x0000001c Code RO 2322 i.retarget_put_char retarget_conf.o + 0x00001478 0x00001478 0x000000dc Code RO 272 i.sysclk_init rcu.o + 0x00001554 0x00001554 0x000002b0 Code RO 2414 x$fpl$ddiv fz_wm.l(ddiv.o) + 0x00001804 0x00001804 0x0000005e Code RO 2417 x$fpl$dfix fz_wm.l(dfix.o) + 0x00001862 0x00001862 0x00000026 Code RO 2421 x$fpl$dfltu fz_wm.l(dflt_clz.o) + 0x00001888 0x00001888 0x0000009c Code RO 2510 x$fpl$dnaninf fz_wm.l(dnaninf.o) + 0x00001924 0x00001924 0x0000000c Code RO 2512 x$fpl$dretinf fz_wm.l(dretinf.o) + 0x00001930 0x00001930 0x0000000a Code RO 2562 x$fpl$fpinit fz_wm.l(fpinit.o) + 0x0000193a 0x0000193a 0x00000000 Code RO 2514 x$fpl$usenofp fz_wm.l(usenofp.o) + 0x0000193a 0x0000193a 0x00000002 PAD + 0x0000193c 0x0000193c 0x00000020 Data RO 2656 Region$$Table anon$$obj.o + + + Execution Region ER_RW (Exec base: 0x20000000, Load base: 0x0000195c, Size: 0x000001a4, Max: 0xffffffff, ABSOLUTE, COMPRESSED[0x00000024]) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x20000000 COMPRESSED 0x00000188 Data RW 220 .data gpio.o + 0x20000188 COMPRESSED 0x00000009 Data RW 274 .data rcu.o + 0x20000191 COMPRESSED 0x00000003 PAD + 0x20000194 COMPRESSED 0x00000008 Data RW 883 .data system_k1921vk035.o + 0x2000019c COMPRESSED 0x00000008 Data RW 2261 .data retarget.o + + + Execution Region ER_ZI (Exec base: 0x200001a4, Load base: 0x00001980, Size: 0x00000664, Max: 0xffffffff, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x200001a4 - 0x00000060 Zero RW 2565 .bss c_w.l(libspace.o) + 0x20000204 0x00001980 0x00000004 PAD + 0x20000208 - 0x00000200 Zero RW 925 HEAP startup_k1921vk035.o + 0x20000408 - 0x00000400 Zero RW 924 STACK startup_k1921vk035.o + + +============================================================================== + +Image component sizes + + + Code (inc. data) RO Data RW Data ZI Data Debug Object Name + + 296 72 0 392 0 11008 gpio.o + 198 96 0 0 0 206397 main.o + 1180 352 0 0 0 12760 plib035_gpio.o + 1104 266 0 0 0 13951 plib035_rcu.o + 328 80 0 9 0 40469 rcu.o + 26 0 0 8 0 3375 retarget.o + 256 34 0 0 0 1204 retarget_conf.o + 64 26 344 0 1536 892 startup_k1921vk035.o + 368 34 0 8 0 2906 system_k1921vk035.o + 42 4 0 0 0 3994 vk035_it.o + + ---------------------------------------------------------------------- + 3870 964 376 420 1536 296956 Object Totals + 0 0 32 0 0 0 (incl. Generated) + 8 0 0 3 0 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name + + 90 0 0 0 0 0 __dczerorl2.o + 8 0 0 0 0 68 __main.o + 284 0 0 0 0 156 __printf_wp.o + 0 0 0 0 0 0 __rtentry.o + 12 0 0 0 0 0 __rtentry2.o + 6 0 0 0 0 0 __rtentry4.o + 52 8 0 0 0 0 __scatter.o + 28 0 0 0 0 0 __scatter_zi.o + 44 0 0 0 0 108 _printf_char.o + 48 6 0 0 0 96 _printf_char_common.o + 36 4 0 0 0 80 _printf_char_file.o + 6 0 0 0 0 0 _printf_d.o + 120 16 0 0 0 92 _printf_dec.o + 178 0 0 0 0 88 _printf_intcommon.o + 78 0 0 0 0 108 _printf_pad.o + 0 0 0 0 0 0 _printf_percent.o + 4 0 0 0 0 0 _printf_percent_end.o + 6 0 0 0 0 0 _printf_s.o + 82 0 0 0 0 80 _printf_str.o + 18 0 0 0 0 80 exit.o + 6 0 0 0 0 152 heapauxi.o + 2 0 0 0 0 0 libinit.o + 6 0 0 0 0 0 libinit2.o + 2 0 0 0 0 0 libshutdown.o + 2 0 0 0 0 0 libshutdown2.o + 8 4 0 0 96 68 libspace.o + 24 4 0 0 0 84 noretval__2printf.o + 2 0 0 0 0 0 rtexit.o + 10 0 0 0 0 0 rtexit2.o + 74 0 0 0 0 80 sys_stackheap_outer.o + 2 0 0 0 0 68 use_no_semi.o + 688 140 0 0 0 256 ddiv.o + 94 4 0 0 0 140 dfix.o + 38 0 0 0 0 116 dflt_clz.o + 156 4 0 0 0 140 dnaninf.o + 12 0 0 0 0 116 dretinf.o + 10 0 0 0 0 116 fpinit.o + 0 0 0 0 0 0 usenofp.o + + ---------------------------------------------------------------------- + 2246 190 0 0 100 2292 Library Totals + 10 0 0 0 4 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Name + + 1238 42 0 0 96 1408 c_w.l + 998 148 0 0 0 884 fz_wm.l + + ---------------------------------------------------------------------- + 2246 190 0 0 100 2292 Library Totals + + ---------------------------------------------------------------------- + +============================================================================== + + + Code (inc. data) RO Data RW Data ZI Data Debug + + 6116 1154 376 420 1636 294324 Grand Totals + 6116 1154 376 36 1636 294324 ELF Image Totals (compressed) + 6116 1154 376 36 0 0 ROM Totals + +============================================================================== + + Total RO Size (Code + RO Data) 6492 ( 6.34kB) + Total RW Size (RW Data + ZI Data) 2056 ( 2.01kB) + Total ROM Size (Code + RO Data + RW Data) 6528 ( 6.38kB) + +============================================================================== + diff --git a/Listings/startup_k1921vk035.lst b/Listings/startup_k1921vk035.lst new file mode 100644 index 0000000..04037aa --- /dev/null +++ b/Listings/startup_k1921vk035.lst @@ -0,0 +1,1961 @@ + + + +ARM Macro Assembler Page 1 + + + 1 00000000 ;******************** (C) COPYRIGHT 2018 NIIET ********* + *********** + 2 00000000 ;* File Name : startup_K1921VK035.s + 3 00000000 ;* Author : NIIET + 4 00000000 ;* Version : V1.7 + 5 00000000 ;* Date : 02.05.2018 + 6 00000000 ;* Description : K1921VK035 vector table for MDK- + ARM + 7 00000000 ;* toolchain. + 8 00000000 ;* This module performs: + 9 00000000 ;* - Set the initial SP + 10 00000000 ;* - Set the initial PC == Reset_Ha + ndler + 11 00000000 ;* - Set the vector table entries w + ith the exceptions ISR address + 12 00000000 ;* - Configure the clock system + 13 00000000 ;* - Branches to __main in the C li + brary (which eventually + 14 00000000 ;* calls main()). + 15 00000000 ;* After Reset the CortexM4 process + or is in Thread mode, + 16 00000000 ;* priority is Privileged, and the + Stack is set to Main. + 17 00000000 ;* <<< Use Configuration Wizard in Context Menu >>> + 18 00000000 ;******************************************************* + ************************ + 19 00000000 ; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS A + T PROVIDING CUSTOMERS + 20 00000000 ; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN OR + DER FOR THEM TO SAVE TIME. + 21 00000000 ; AS A RESULT, NIIET SHALL NOT BE HELD LIABLE FOR ANY DI + RECT, + 22 00000000 ; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY + CLAIMS ARISING FROM THE + 23 00000000 ; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOM + ERS OF THE CODING + 24 00000000 ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR + PRODUCTS. + 25 00000000 ;******************************************************* + ************************ + 26 00000000 + 27 00000000 ; Amount of memory (in bytes) allocated for Stack + 28 00000000 ; Tailor this value to your application needs + 29 00000000 ; Stack Configuration + 30 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + 31 00000000 ; + 32 00000000 + 33 00000000 00000400 + Stack_Size + EQU 0x00000400 + 34 00000000 + 35 00000000 AREA STACK, NOINIT, READWRITE, ALIGN +=3 + 36 00000000 Stack_Mem + SPACE Stack_Size + 37 00000400 __initial_sp + 38 00000400 + 39 00000400 + 40 00000400 ; Heap Configuration + + + +ARM Macro Assembler Page 2 + + + 41 00000400 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + 42 00000400 ; + 43 00000400 + 44 00000400 00000200 + Heap_Size + EQU 0x00000200 + 45 00000400 + 46 00000400 AREA HEAP, NOINIT, READWRITE, ALIGN= +3 + 47 00000000 __heap_base + 48 00000000 Heap_Mem + SPACE Heap_Size + 49 00000200 __heap_limit + 50 00000200 + 51 00000200 PRESERVE8 + 52 00000200 THUMB + 53 00000200 + 54 00000200 + 55 00000200 ; Vector Table Mapped to Address 0 at Reset + 56 00000200 AREA RESET, DATA, READONLY + 57 00000000 EXPORT __Vectors + 58 00000000 EXPORT __Vectors_End + 59 00000000 EXPORT __Vectors_Size + 60 00000000 + 61 00000000 00000000 + __Vectors + DCD __initial_sp ; Top of Stack + 62 00000004 00000000 DCD Reset_Handler ; Reset Handler + 63 00000008 00000000 DCD NMI_Handler ; NMI Handler + 64 0000000C 00000000 DCD HardFault_Handler ; Hard Fault + Handler + 65 00000010 00000000 DCD MemManage_Handler + ; MPU Fault Handler + + 66 00000014 00000000 DCD BusFault_Handler + ; Bus Fault Handler + + 67 00000018 00000000 DCD UsageFault_Handler ; Usage Faul + t Handler + 68 0000001C 00000000 DCD 0 ; Reserved + 69 00000020 00000000 DCD 0 ; Reserved + 70 00000024 00000000 DCD 0 ; Reserved + 71 00000028 00000000 DCD 0 ; Reserved + 72 0000002C 00000000 DCD SVC_Handler ; SVCall Handler + 73 00000030 00000000 DCD DebugMon_Handler ; Debug Monito + r Handler + 74 00000034 00000000 DCD 0 ; Reserved + 75 00000038 00000000 DCD PendSV_Handler ; PendSV Handler + + 76 0000003C 00000000 DCD SysTick_Handler + ; SysTick Handler + 77 00000040 + 78 00000040 ; External Interrupts + 79 00000040 00000000 DCD WDT_IRQHandler ; Watchdog timer + interrupt + 80 00000044 00000000 DCD RCU_IRQHandler ; Reset and cloc + k unit interrupt + 81 00000048 00000000 DCD MFLASH_IRQHandler + ; MFLASH interrupt + + + +ARM Macro Assembler Page 3 + + + 82 0000004C 00000000 DCD GPIOA_IRQHandler + ; GPIO A interrupt + 83 00000050 00000000 DCD GPIOB_IRQHandler + ; GPIO B interrupt + 84 00000054 00000000 DCD DMA_CH0_IRQHandler ; DMA channe + l 0 interrupt + 85 00000058 00000000 DCD DMA_CH1_IRQHandler ; DMA channe + l 1 interrupt + 86 0000005C 00000000 DCD DMA_CH2_IRQHandler ; DMA channe + l 2 interrupt + 87 00000060 00000000 DCD DMA_CH3_IRQHandler ; DMA channe + l 3 interrupt + 88 00000064 00000000 DCD DMA_CH4_IRQHandler ; DMA channe + l 4 interrupt + 89 00000068 00000000 DCD DMA_CH5_IRQHandler ; DMA channe + l 5 interrupt + 90 0000006C 00000000 DCD DMA_CH6_IRQHandler ; DMA channe + l 6 interrupt + 91 00000070 00000000 DCD DMA_CH7_IRQHandler ; DMA channe + l 7 interrupt + 92 00000074 00000000 DCD DMA_CH8_IRQHandler ; DMA channe + l 8 interrupt + 93 00000078 00000000 DCD DMA_CH9_IRQHandler ; DMA channe + l 9 interrupt + 94 0000007C 00000000 DCD DMA_CH10_IRQHandler ; DMA chann + el 10 interrupt + 95 00000080 00000000 DCD DMA_CH11_IRQHandler ; DMA chann + el 11 interrupt + 96 00000084 00000000 DCD DMA_CH12_IRQHandler ; DMA chann + el 12 interrupt + 97 00000088 00000000 DCD DMA_CH13_IRQHandler ; DMA chann + el 13 interrupt + 98 0000008C 00000000 DCD DMA_CH14_IRQHandler ; DMA chann + el 14 interrupt + 99 00000090 00000000 DCD DMA_CH15_IRQHandler ; DMA chann + el 15 interrupt + 100 00000094 00000000 DCD TMR0_IRQHandler + ; Timer 0 interrupt + + 101 00000098 00000000 DCD TMR1_IRQHandler + ; Timer 1 interrupt + + 102 0000009C 00000000 DCD TMR2_IRQHandler + ; Timer 2 interrupt + + 103 000000A0 00000000 DCD TMR3_IRQHandler + ; Timer 3 interrupt + + 104 000000A4 00000000 DCD UART0_TD_IRQHandler ; UART0 Tra + nsmit Done interrup + t + 105 000000A8 00000000 DCD UART0_RX_IRQHandler ; UART0 Rec + ieve interrupt + 106 000000AC 00000000 DCD UART0_TX_IRQHandler ; UART0 Tra + nsmit interrupt + 107 000000B0 00000000 DCD UART0_E_RT_IRQHandler ; UART0 E + rror and Receive Ti + meout interrupt + 108 000000B4 00000000 DCD UART1_TD_IRQHandler ; UART1 Tra + + + +ARM Macro Assembler Page 4 + + + nsmit Done interrup + t + 109 000000B8 00000000 DCD UART1_RX_IRQHandler ; UART1 Rec + ieve interrupt + 110 000000BC 00000000 DCD UART1_TX_IRQHandler ; UART1 Tra + nsmit interrupt + 111 000000C0 00000000 DCD UART1_E_RT_IRQHandler ; UART1 E + rror and Receive Ti + meout interrupt + 112 000000C4 00000000 DCD SPI_RO_RT_IRQHandler ; SPI RX F + IFO overrun and Rec + eive Timeout interr + upt + 113 000000C8 00000000 DCD SPI_RX_IRQHandler ; SPI Receive + interrupt + 114 000000CC 00000000 DCD SPI_TX_IRQHandler ; SPI Transmi + t interrupt + 115 000000D0 00000000 DCD I2C_IRQHandler ; I2C interrupt + 116 000000D4 00000000 DCD ECAP0_IRQHandler + ; ECAP0 interrupt + 117 000000D8 00000000 DCD ECAP1_IRQHandler + ; ECAP1 interrupt + 118 000000DC 00000000 DCD ECAP2_IRQHandler + ; ECAP2 interrupt + 119 000000E0 00000000 DCD PWM0_IRQHandler + ; PWM0 interrupt + 120 000000E4 00000000 DCD PWM0_HD_IRQHandler + ; PWM0 HD interrupt + + 121 000000E8 00000000 DCD PWM0_TZ_IRQHandler + ; PWM0 TZ interrupt + + 122 000000EC 00000000 DCD PWM1_IRQHandler + ; PWM1 interrupt + 123 000000F0 00000000 DCD PWM1_HD_IRQHandler + ; PWM1 HD interrupt + + 124 000000F4 00000000 DCD PWM1_TZ_IRQHandler + ; PWM1 TZ interrupt + + 125 000000F8 00000000 DCD PWM2_IRQHandler + ; PWM2 interrupt + 126 000000FC 00000000 DCD PWM2_HD_IRQHandler + ; PWM2 HD interrupt + + 127 00000100 00000000 DCD PWM2_TZ_IRQHandler + ; PWM2 TZ interrupt + + 128 00000104 00000000 DCD QEP_IRQHandler ; QEP interrupt + 129 00000108 00000000 DCD ADC_SEQ0_IRQHandler ; ADC Seque + ncer 0 interrupt + 130 0000010C 00000000 DCD ADC_SEQ1_IRQHandler ; ADC Seque + ncer 1 interrupt + 131 00000110 00000000 DCD ADC_DC_IRQHandler ; ADC Digital + Comparator interru + pt + 132 00000114 00000000 DCD CAN0_IRQHandler + ; CAN0 interrupt + 133 00000118 00000000 DCD CAN1_IRQHandler + + + +ARM Macro Assembler Page 5 + + + ; CAN1 interrupt + 134 0000011C 00000000 DCD CAN2_IRQHandler + ; CAN2 interrupt + 135 00000120 00000000 DCD CAN3_IRQHandler + ; CAN3 interrupt + 136 00000124 00000000 DCD CAN4_IRQHandler + ; CAN4 interrupt + 137 00000128 00000000 DCD CAN5_IRQHandler + ; CAN5 interrupt + 138 0000012C 00000000 DCD CAN6_IRQHandler + ; CAN6 interrupt + 139 00000130 00000000 DCD CAN7_IRQHandler + ; CAN7 interrupt + 140 00000134 00000000 DCD CAN8_IRQHandler + ; CAN8 interrupt + 141 00000138 00000000 DCD CAN9_IRQHandler + ; CAN9 interrupt + 142 0000013C 00000000 DCD CAN10_IRQHandler + ; CAN10 interrupt + 143 00000140 00000000 DCD CAN11_IRQHandler + ; CAN11 interrupt + 144 00000144 00000000 DCD CAN12_IRQHandler + ; CAN12 interrupt + 145 00000148 00000000 DCD CAN13_IRQHandler + ; CAN13 interrupt + 146 0000014C 00000000 DCD CAN14_IRQHandler + ; CAN14 interrupt + 147 00000150 00000000 DCD CAN15_IRQHandler + ; CAN15 interrupt + 148 00000154 00000000 DCD FPU_IRQHandler ; FPU exception + interrupt + 149 00000158 + 150 00000158 __Vectors_End + 151 00000158 + 152 00000158 00000158 + __Vectors_Size + EQU __Vectors_End - __Vectors + 153 00000158 + 154 00000158 AREA |.text|, CODE, READONLY + 155 00000000 + 156 00000000 ; Reset handler + 157 00000000 Reset_Handler + PROC + 158 00000000 EXPORT Reset_Handler [WEAK +] + 159 00000000 IMPORT __main + 160 00000000 IMPORT SystemInit + 161 00000000 4809 LDR R0, =SystemInit + 162 00000002 4780 BLX R0 + 163 00000004 4809 LDR R0, =__main + 164 00000006 4700 BX R0 + 165 00000008 ENDP + 166 00000008 + 167 00000008 ; Dummy Exception Handlers (infinite loops which can be + modified) + 168 00000008 + 169 00000008 NMI_Handler + PROC + 170 00000008 EXPORT NMI_Handler [WEA + + + +ARM Macro Assembler Page 6 + + +K] + 171 00000008 E7FE B . + 172 0000000A ENDP + 174 0000000A HardFault_Handler + PROC + 175 0000000A EXPORT HardFault_Handler [WEA +K] + 176 0000000A E7FE B . + 177 0000000C ENDP + 179 0000000C MemManage_Handler + PROC + 180 0000000C EXPORT MemManage_Handler [WEA +K] + 181 0000000C E7FE B . + 182 0000000E ENDP + 184 0000000E BusFault_Handler + PROC + 185 0000000E EXPORT BusFault_Handler [WEA +K] + 186 0000000E E7FE B . + 187 00000010 ENDP + 189 00000010 UsageFault_Handler + PROC + 190 00000010 EXPORT UsageFault_Handler [WEA +K] + 191 00000010 E7FE B . + 192 00000012 ENDP + 193 00000012 SVC_Handler + PROC + 194 00000012 EXPORT SVC_Handler [WEA +K] + 195 00000012 E7FE B . + 196 00000014 ENDP + 198 00000014 DebugMon_Handler + PROC + 199 00000014 EXPORT DebugMon_Handler [WEA +K] + 200 00000014 E7FE B . + 201 00000016 ENDP + 202 00000016 PendSV_Handler + PROC + 203 00000016 EXPORT PendSV_Handler [WEA +K] + 204 00000016 E7FE B . + 205 00000018 ENDP + 206 00000018 SysTick_Handler + PROC + 207 00000018 EXPORT SysTick_Handler [WEA +K] + 208 00000018 E7FE B . + 209 0000001A ENDP + 210 0000001A + 211 0000001A Default_Handler + PROC + 212 0000001A + 213 0000001A EXPORT WDT_IRQHandler [WEAK] + 214 0000001A EXPORT RCU_IRQHandler [WEAK] + 215 0000001A EXPORT MFLASH_IRQHandler [WE +AK] + + + +ARM Macro Assembler Page 7 + + + 216 0000001A EXPORT GPIOA_IRQHandler [WEA +K] + 217 0000001A EXPORT GPIOB_IRQHandler [WEA +K] + 218 0000001A EXPORT DMA_CH0_IRQHandler [W +EAK] + 219 0000001A EXPORT DMA_CH1_IRQHandler [W +EAK] + 220 0000001A EXPORT DMA_CH2_IRQHandler [W +EAK] + 221 0000001A EXPORT DMA_CH3_IRQHandler [W +EAK] + 222 0000001A EXPORT DMA_CH4_IRQHandler [W +EAK] + 223 0000001A EXPORT DMA_CH5_IRQHandler [W +EAK] + 224 0000001A EXPORT DMA_CH6_IRQHandler [W +EAK] + 225 0000001A EXPORT DMA_CH7_IRQHandler [W +EAK] + 226 0000001A EXPORT DMA_CH8_IRQHandler [W +EAK] + 227 0000001A EXPORT DMA_CH9_IRQHandler [W +EAK] + 228 0000001A EXPORT DMA_CH10_IRQHandler [ +WEAK] + 229 0000001A EXPORT DMA_CH11_IRQHandler [ +WEAK] + 230 0000001A EXPORT DMA_CH12_IRQHandler [ +WEAK] + 231 0000001A EXPORT DMA_CH13_IRQHandler [ +WEAK] + 232 0000001A EXPORT DMA_CH14_IRQHandler [ +WEAK] + 233 0000001A EXPORT DMA_CH15_IRQHandler [ +WEAK] + 234 0000001A EXPORT TMR0_IRQHandler [WEAK +] + 235 0000001A EXPORT TMR1_IRQHandler [WEAK +] + 236 0000001A EXPORT TMR2_IRQHandler [WEAK +] + 237 0000001A EXPORT TMR3_IRQHandler [WEAK +] + 238 0000001A EXPORT UART0_TD_IRQHandler [ +WEAK] + 239 0000001A EXPORT UART0_RX_IRQHandler [ +WEAK] + 240 0000001A EXPORT UART0_TX_IRQHandler [ +WEAK] + 241 0000001A EXPORT UART0_E_RT_IRQHandler + [WEAK] + 242 0000001A EXPORT UART1_TD_IRQHandler [ +WEAK] + 243 0000001A EXPORT UART1_RX_IRQHandler [ +WEAK] + 244 0000001A EXPORT UART1_TX_IRQHandler [ +WEAK] + 245 0000001A EXPORT UART1_E_RT_IRQHandler + + + +ARM Macro Assembler Page 8 + + + [WEAK] + 246 0000001A EXPORT SPI_RO_RT_IRQHandler +[WEAK] + 247 0000001A EXPORT SPI_RX_IRQHandler [WE +AK] + 248 0000001A EXPORT SPI_TX_IRQHandler [WE +AK] + 249 0000001A EXPORT I2C_IRQHandler [WEAK] + 250 0000001A EXPORT ECAP0_IRQHandler [WEA +K] + 251 0000001A EXPORT ECAP1_IRQHandler [WEA +K] + 252 0000001A EXPORT ECAP2_IRQHandler [WEA +K] + 253 0000001A EXPORT PWM0_IRQHandler [WEAK +] + 254 0000001A EXPORT PWM0_HD_IRQHandler [W +EAK] + 255 0000001A EXPORT PWM0_TZ_IRQHandler [W +EAK] + 256 0000001A EXPORT PWM1_IRQHandler [WEAK +] + 257 0000001A EXPORT PWM1_HD_IRQHandler [W +EAK] + 258 0000001A EXPORT PWM1_TZ_IRQHandler [W +EAK] + 259 0000001A EXPORT PWM2_IRQHandler [WEAK +] + 260 0000001A EXPORT PWM2_HD_IRQHandler [W +EAK] + 261 0000001A EXPORT PWM2_TZ_IRQHandler [W +EAK] + 262 0000001A EXPORT QEP_IRQHandler [WEAK] + 263 0000001A EXPORT ADC_SEQ0_IRQHandler [ +WEAK] + 264 0000001A EXPORT ADC_SEQ1_IRQHandler [ +WEAK] + 265 0000001A EXPORT ADC_DC_IRQHandler [WE +AK] + 266 0000001A EXPORT CAN0_IRQHandler [WEAK +] + 267 0000001A EXPORT CAN1_IRQHandler [WEAK +] + 268 0000001A EXPORT CAN2_IRQHandler [WEAK +] + 269 0000001A EXPORT CAN3_IRQHandler [WEAK +] + 270 0000001A EXPORT CAN4_IRQHandler [WEAK +] + 271 0000001A EXPORT CAN5_IRQHandler [WEAK +] + 272 0000001A EXPORT CAN6_IRQHandler [WEAK +] + 273 0000001A EXPORT CAN7_IRQHandler [WEAK +] + 274 0000001A EXPORT CAN8_IRQHandler [WEAK +] + 275 0000001A EXPORT CAN9_IRQHandler [WEAK +] + + + +ARM Macro Assembler Page 9 + + + 276 0000001A EXPORT CAN10_IRQHandler [WEA +K] + 277 0000001A EXPORT CAN11_IRQHandler [WEA +K] + 278 0000001A EXPORT CAN12_IRQHandler [WEA +K] + 279 0000001A EXPORT CAN13_IRQHandler [WEA +K] + 280 0000001A EXPORT CAN14_IRQHandler [WEA +K] + 281 0000001A EXPORT CAN15_IRQHandler [WEA +K] + 282 0000001A EXPORT FPU_IRQHandler [WEAK] + 283 0000001A + 284 0000001A + 285 0000001A + 286 0000001A WDT_IRQHandler + 287 0000001A RCU_IRQHandler + 288 0000001A MFLASH_IRQHandler + 289 0000001A GPIOA_IRQHandler + 290 0000001A GPIOB_IRQHandler + 291 0000001A DMA_CH0_IRQHandler + 292 0000001A DMA_CH1_IRQHandler + 293 0000001A DMA_CH2_IRQHandler + 294 0000001A DMA_CH3_IRQHandler + 295 0000001A DMA_CH4_IRQHandler + 296 0000001A DMA_CH5_IRQHandler + 297 0000001A DMA_CH6_IRQHandler + 298 0000001A DMA_CH7_IRQHandler + 299 0000001A DMA_CH8_IRQHandler + 300 0000001A DMA_CH9_IRQHandler + 301 0000001A DMA_CH10_IRQHandler + 302 0000001A DMA_CH11_IRQHandler + 303 0000001A DMA_CH12_IRQHandler + 304 0000001A DMA_CH13_IRQHandler + 305 0000001A DMA_CH14_IRQHandler + 306 0000001A DMA_CH15_IRQHandler + 307 0000001A TMR0_IRQHandler + 308 0000001A TMR1_IRQHandler + 309 0000001A TMR2_IRQHandler + 310 0000001A TMR3_IRQHandler + 311 0000001A UART0_TD_IRQHandler + 312 0000001A UART0_RX_IRQHandler + 313 0000001A UART0_TX_IRQHandler + 314 0000001A UART0_E_RT_IRQHandler + 315 0000001A UART1_TD_IRQHandler + 316 0000001A UART1_RX_IRQHandler + 317 0000001A UART1_TX_IRQHandler + 318 0000001A UART1_E_RT_IRQHandler + 319 0000001A SPI_RO_RT_IRQHandler + 320 0000001A SPI_RX_IRQHandler + 321 0000001A SPI_TX_IRQHandler + 322 0000001A I2C_IRQHandler + 323 0000001A ECAP0_IRQHandler + 324 0000001A ECAP1_IRQHandler + 325 0000001A ECAP2_IRQHandler + 326 0000001A PWM0_IRQHandler + 327 0000001A PWM0_HD_IRQHandler + 328 0000001A PWM0_TZ_IRQHandler + + + +ARM Macro Assembler Page 10 + + + 329 0000001A PWM1_IRQHandler + 330 0000001A PWM1_HD_IRQHandler + 331 0000001A PWM1_TZ_IRQHandler + 332 0000001A PWM2_IRQHandler + 333 0000001A PWM2_HD_IRQHandler + 334 0000001A PWM2_TZ_IRQHandler + 335 0000001A QEP_IRQHandler + 336 0000001A ADC_SEQ0_IRQHandler + 337 0000001A ADC_SEQ1_IRQHandler + 338 0000001A ADC_DC_IRQHandler + 339 0000001A CAN0_IRQHandler + 340 0000001A CAN1_IRQHandler + 341 0000001A CAN2_IRQHandler + 342 0000001A CAN3_IRQHandler + 343 0000001A CAN4_IRQHandler + 344 0000001A CAN5_IRQHandler + 345 0000001A CAN6_IRQHandler + 346 0000001A CAN7_IRQHandler + 347 0000001A CAN8_IRQHandler + 348 0000001A CAN9_IRQHandler + 349 0000001A CAN10_IRQHandler + 350 0000001A CAN11_IRQHandler + 351 0000001A CAN12_IRQHandler + 352 0000001A CAN13_IRQHandler + 353 0000001A CAN14_IRQHandler + 354 0000001A CAN15_IRQHandler + 355 0000001A FPU_IRQHandler + 356 0000001A + 357 0000001A + 358 0000001A + 359 0000001A E7FE B . + 360 0000001C + 361 0000001C ENDP + 362 0000001C + 363 0000001C ALIGN + 364 0000001C + 365 0000001C ;******************************************************* + ************************ + 366 0000001C ; User Stack and Heap initialization + 367 0000001C ;******************************************************* + ************************ + 368 0000001C IF :DEF:__MICROLIB + 375 0000001C + 376 0000001C IMPORT __use_two_region_memory + 377 0000001C EXPORT __user_initial_stackheap + 378 0000001C + 379 0000001C __user_initial_stackheap + 380 0000001C + 381 0000001C 4804 LDR R0, = Heap_Mem + 382 0000001E 4905 LDR R1, =(Stack_Mem + Stack_Size) + 383 00000020 4A05 LDR R2, = (Heap_Mem + Heap_Size) + 384 00000022 4B06 LDR R3, = Stack_Mem + 385 00000024 4770 BX LR + 386 00000026 + 387 00000026 00 00 ALIGN + 388 00000028 + 389 00000028 ENDIF + 390 00000028 + 391 00000028 END + + + +ARM Macro Assembler Page 11 + + + 00000000 + 00000000 + 00000000 + 00000400 + 00000200 + 00000000 +Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M4.fp.sp --apcs= +interwork --depend=.\objects\startup_k1921vk035.d -o.\objects\startup_k1921vk03 +5.o -IC:\Users\I\AppData\Local\Arm\Packs\NIIET\K1921VK035_DFP\2.0.6\Device\Incl +ude --predefine="__UVISION_VERSION SETA 538" --predefine="K1921VK035 SETA 1" -- +list=.\listings\startup_k1921vk035.lst platform\Device\NIIET\K1921VK035\Source\ +ARM\startup_K1921VK035.s + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +STACK 00000000 + +Symbol: STACK + Definitions + At line 35 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + Uses + None +Comment: STACK unused +Stack_Mem 00000000 + +Symbol: Stack_Mem + Definitions + At line 36 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + Uses + At line 382 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 384 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +__initial_sp 00000400 + +Symbol: __initial_sp + Definitions + At line 37 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + Uses + At line 61 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s +Comment: __initial_sp used once +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +HEAP 00000000 + +Symbol: HEAP + Definitions + At line 46 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + Uses + None +Comment: HEAP unused +Heap_Mem 00000000 + +Symbol: Heap_Mem + Definitions + At line 48 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + Uses + At line 381 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 383 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +__heap_base 00000000 + +Symbol: __heap_base + Definitions + At line 47 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + Uses + None +Comment: __heap_base unused +__heap_limit 00000200 + +Symbol: __heap_limit + Definitions + At line 49 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + Uses + None +Comment: __heap_limit unused +4 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +RESET 00000000 + +Symbol: RESET + Definitions + At line 56 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + Uses + None +Comment: RESET unused +__Vectors 00000000 + +Symbol: __Vectors + Definitions + At line 61 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + Uses + At line 57 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 152 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +__Vectors_End 00000158 + +Symbol: __Vectors_End + Definitions + At line 150 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 58 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 152 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +.text 00000000 + +Symbol: .text + Definitions + At line 154 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + None +Comment: .text unused +ADC_DC_IRQHandler 0000001A + +Symbol: ADC_DC_IRQHandler + Definitions + At line 338 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 131 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 265 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +ADC_SEQ0_IRQHandler 0000001A + +Symbol: ADC_SEQ0_IRQHandler + Definitions + At line 336 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 129 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 263 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +ADC_SEQ1_IRQHandler 0000001A + +Symbol: ADC_SEQ1_IRQHandler + Definitions + At line 337 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 130 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 264 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +BusFault_Handler 0000000E + +Symbol: BusFault_Handler + Definitions + At line 184 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 66 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 185 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +CAN0_IRQHandler 0000001A + + + + +ARM Macro Assembler Page 2 Alphabetic symbol ordering +Relocatable symbols + +Symbol: CAN0_IRQHandler + Definitions + At line 339 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 132 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 266 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +CAN10_IRQHandler 0000001A + +Symbol: CAN10_IRQHandler + Definitions + At line 349 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 142 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 276 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +CAN11_IRQHandler 0000001A + +Symbol: CAN11_IRQHandler + Definitions + At line 350 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 143 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 277 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +CAN12_IRQHandler 0000001A + +Symbol: CAN12_IRQHandler + Definitions + At line 351 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 144 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 278 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +CAN13_IRQHandler 0000001A + +Symbol: CAN13_IRQHandler + Definitions + At line 352 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 145 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 279 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +CAN14_IRQHandler 0000001A + + + +ARM Macro Assembler Page 3 Alphabetic symbol ordering +Relocatable symbols + + +Symbol: CAN14_IRQHandler + Definitions + At line 353 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 146 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 280 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +CAN15_IRQHandler 0000001A + +Symbol: CAN15_IRQHandler + Definitions + At line 354 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 147 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 281 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +CAN1_IRQHandler 0000001A + +Symbol: CAN1_IRQHandler + Definitions + At line 340 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 133 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 267 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +CAN2_IRQHandler 0000001A + +Symbol: CAN2_IRQHandler + Definitions + At line 341 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 134 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 268 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +CAN3_IRQHandler 0000001A + +Symbol: CAN3_IRQHandler + Definitions + At line 342 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 135 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 269 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + + + + +ARM Macro Assembler Page 4 Alphabetic symbol ordering +Relocatable symbols + +CAN4_IRQHandler 0000001A + +Symbol: CAN4_IRQHandler + Definitions + At line 343 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 136 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 270 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +CAN5_IRQHandler 0000001A + +Symbol: CAN5_IRQHandler + Definitions + At line 344 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 137 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 271 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +CAN6_IRQHandler 0000001A + +Symbol: CAN6_IRQHandler + Definitions + At line 345 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 138 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 272 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +CAN7_IRQHandler 0000001A + +Symbol: CAN7_IRQHandler + Definitions + At line 346 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 139 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 273 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +CAN8_IRQHandler 0000001A + +Symbol: CAN8_IRQHandler + Definitions + At line 347 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 140 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 274 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + + + +ARM Macro Assembler Page 5 Alphabetic symbol ordering +Relocatable symbols + + +CAN9_IRQHandler 0000001A + +Symbol: CAN9_IRQHandler + Definitions + At line 348 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 141 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 275 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +DMA_CH0_IRQHandler 0000001A + +Symbol: DMA_CH0_IRQHandler + Definitions + At line 291 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 84 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 218 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +DMA_CH10_IRQHandler 0000001A + +Symbol: DMA_CH10_IRQHandler + Definitions + At line 301 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 94 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 228 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +DMA_CH11_IRQHandler 0000001A + +Symbol: DMA_CH11_IRQHandler + Definitions + At line 302 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 95 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 229 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +DMA_CH12_IRQHandler 0000001A + +Symbol: DMA_CH12_IRQHandler + Definitions + At line 303 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 96 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 230 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K + + + +ARM Macro Assembler Page 6 Alphabetic symbol ordering +Relocatable symbols + +1921VK035.s + +DMA_CH13_IRQHandler 0000001A + +Symbol: DMA_CH13_IRQHandler + Definitions + At line 304 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 97 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 231 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +DMA_CH14_IRQHandler 0000001A + +Symbol: DMA_CH14_IRQHandler + Definitions + At line 305 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 98 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 232 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +DMA_CH15_IRQHandler 0000001A + +Symbol: DMA_CH15_IRQHandler + Definitions + At line 306 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 99 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 233 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +DMA_CH1_IRQHandler 0000001A + +Symbol: DMA_CH1_IRQHandler + Definitions + At line 292 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 85 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 219 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +DMA_CH2_IRQHandler 0000001A + +Symbol: DMA_CH2_IRQHandler + Definitions + At line 293 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 86 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + + + +ARM Macro Assembler Page 7 Alphabetic symbol ordering +Relocatable symbols + + At line 220 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +DMA_CH3_IRQHandler 0000001A + +Symbol: DMA_CH3_IRQHandler + Definitions + At line 294 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 87 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 221 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +DMA_CH4_IRQHandler 0000001A + +Symbol: DMA_CH4_IRQHandler + Definitions + At line 295 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 88 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 222 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +DMA_CH5_IRQHandler 0000001A + +Symbol: DMA_CH5_IRQHandler + Definitions + At line 296 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 89 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 223 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +DMA_CH6_IRQHandler 0000001A + +Symbol: DMA_CH6_IRQHandler + Definitions + At line 297 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 90 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 224 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +DMA_CH7_IRQHandler 0000001A + +Symbol: DMA_CH7_IRQHandler + Definitions + At line 298 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 91 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 + + + +ARM Macro Assembler Page 8 Alphabetic symbol ordering +Relocatable symbols + +921VK035.s + At line 225 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +DMA_CH8_IRQHandler 0000001A + +Symbol: DMA_CH8_IRQHandler + Definitions + At line 299 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 92 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 226 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +DMA_CH9_IRQHandler 0000001A + +Symbol: DMA_CH9_IRQHandler + Definitions + At line 300 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 93 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 227 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +DebugMon_Handler 00000014 + +Symbol: DebugMon_Handler + Definitions + At line 198 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 73 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 199 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +Default_Handler 0000001A + +Symbol: Default_Handler + Definitions + At line 211 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + None +Comment: Default_Handler unused +ECAP0_IRQHandler 0000001A + +Symbol: ECAP0_IRQHandler + Definitions + At line 323 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 116 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 250 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K + + + +ARM Macro Assembler Page 9 Alphabetic symbol ordering +Relocatable symbols + +1921VK035.s + +ECAP1_IRQHandler 0000001A + +Symbol: ECAP1_IRQHandler + Definitions + At line 324 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 117 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 251 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +ECAP2_IRQHandler 0000001A + +Symbol: ECAP2_IRQHandler + Definitions + At line 325 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 118 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 252 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +FPU_IRQHandler 0000001A + +Symbol: FPU_IRQHandler + Definitions + At line 355 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 148 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 282 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +GPIOA_IRQHandler 0000001A + +Symbol: GPIOA_IRQHandler + Definitions + At line 289 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 82 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 216 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +GPIOB_IRQHandler 0000001A + +Symbol: GPIOB_IRQHandler + Definitions + At line 290 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 83 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + + + +ARM Macro Assembler Page 10 Alphabetic symbol ordering +Relocatable symbols + + At line 217 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +HardFault_Handler 0000000A + +Symbol: HardFault_Handler + Definitions + At line 174 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 64 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 175 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +I2C_IRQHandler 0000001A + +Symbol: I2C_IRQHandler + Definitions + At line 322 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 115 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 249 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +MFLASH_IRQHandler 0000001A + +Symbol: MFLASH_IRQHandler + Definitions + At line 288 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 81 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 215 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +MemManage_Handler 0000000C + +Symbol: MemManage_Handler + Definitions + At line 179 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 65 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 180 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +NMI_Handler 00000008 + +Symbol: NMI_Handler + Definitions + At line 169 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 63 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 + + + +ARM Macro Assembler Page 11 Alphabetic symbol ordering +Relocatable symbols + +921VK035.s + At line 170 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +PWM0_HD_IRQHandler 0000001A + +Symbol: PWM0_HD_IRQHandler + Definitions + At line 327 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 120 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 254 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +PWM0_IRQHandler 0000001A + +Symbol: PWM0_IRQHandler + Definitions + At line 326 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 119 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 253 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +PWM0_TZ_IRQHandler 0000001A + +Symbol: PWM0_TZ_IRQHandler + Definitions + At line 328 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 121 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 255 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +PWM1_HD_IRQHandler 0000001A + +Symbol: PWM1_HD_IRQHandler + Definitions + At line 330 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 123 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 257 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +PWM1_IRQHandler 0000001A + +Symbol: PWM1_IRQHandler + Definitions + At line 329 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + + + +ARM Macro Assembler Page 12 Alphabetic symbol ordering +Relocatable symbols + + At line 122 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 256 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +PWM1_TZ_IRQHandler 0000001A + +Symbol: PWM1_TZ_IRQHandler + Definitions + At line 331 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 124 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 258 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +PWM2_HD_IRQHandler 0000001A + +Symbol: PWM2_HD_IRQHandler + Definitions + At line 333 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 126 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 260 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +PWM2_IRQHandler 0000001A + +Symbol: PWM2_IRQHandler + Definitions + At line 332 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 125 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 259 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +PWM2_TZ_IRQHandler 0000001A + +Symbol: PWM2_TZ_IRQHandler + Definitions + At line 334 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 127 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 261 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +PendSV_Handler 00000016 + +Symbol: PendSV_Handler + Definitions + At line 202 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + + + +ARM Macro Assembler Page 13 Alphabetic symbol ordering +Relocatable symbols + + Uses + At line 75 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 203 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +QEP_IRQHandler 0000001A + +Symbol: QEP_IRQHandler + Definitions + At line 335 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 128 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 262 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +RCU_IRQHandler 0000001A + +Symbol: RCU_IRQHandler + Definitions + At line 287 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 80 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 214 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +Reset_Handler 00000000 + +Symbol: Reset_Handler + Definitions + At line 157 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 62 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 158 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +SPI_RO_RT_IRQHandler 0000001A + +Symbol: SPI_RO_RT_IRQHandler + Definitions + At line 319 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 112 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 246 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +SPI_RX_IRQHandler 0000001A + +Symbol: SPI_RX_IRQHandler + Definitions + At line 320 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K + + + +ARM Macro Assembler Page 14 Alphabetic symbol ordering +Relocatable symbols + +1921VK035.s + Uses + At line 113 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 247 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +SPI_TX_IRQHandler 0000001A + +Symbol: SPI_TX_IRQHandler + Definitions + At line 321 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 114 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 248 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +SVC_Handler 00000012 + +Symbol: SVC_Handler + Definitions + At line 193 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 72 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 194 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +SysTick_Handler 00000018 + +Symbol: SysTick_Handler + Definitions + At line 206 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 76 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 207 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +TMR0_IRQHandler 0000001A + +Symbol: TMR0_IRQHandler + Definitions + At line 307 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 100 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 234 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +TMR1_IRQHandler 0000001A + +Symbol: TMR1_IRQHandler + Definitions + + + +ARM Macro Assembler Page 15 Alphabetic symbol ordering +Relocatable symbols + + At line 308 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 101 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 235 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +TMR2_IRQHandler 0000001A + +Symbol: TMR2_IRQHandler + Definitions + At line 309 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 102 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 236 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +TMR3_IRQHandler 0000001A + +Symbol: TMR3_IRQHandler + Definitions + At line 310 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 103 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 237 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +UART0_E_RT_IRQHandler 0000001A + +Symbol: UART0_E_RT_IRQHandler + Definitions + At line 314 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 107 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 241 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +UART0_RX_IRQHandler 0000001A + +Symbol: UART0_RX_IRQHandler + Definitions + At line 312 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 105 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 239 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +UART0_TD_IRQHandler 0000001A + +Symbol: UART0_TD_IRQHandler + + + +ARM Macro Assembler Page 16 Alphabetic symbol ordering +Relocatable symbols + + Definitions + At line 311 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 104 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 238 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +UART0_TX_IRQHandler 0000001A + +Symbol: UART0_TX_IRQHandler + Definitions + At line 313 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 106 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 240 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +UART1_E_RT_IRQHandler 0000001A + +Symbol: UART1_E_RT_IRQHandler + Definitions + At line 318 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 111 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 245 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +UART1_RX_IRQHandler 0000001A + +Symbol: UART1_RX_IRQHandler + Definitions + At line 316 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 109 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 243 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +UART1_TD_IRQHandler 0000001A + +Symbol: UART1_TD_IRQHandler + Definitions + At line 315 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 108 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 242 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +UART1_TX_IRQHandler 0000001A + + + + +ARM Macro Assembler Page 17 Alphabetic symbol ordering +Relocatable symbols + +Symbol: UART1_TX_IRQHandler + Definitions + At line 317 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 110 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + At line 244 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +UsageFault_Handler 00000010 + +Symbol: UsageFault_Handler + Definitions + At line 189 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 67 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 190 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +WDT_IRQHandler 0000001A + +Symbol: WDT_IRQHandler + Definitions + At line 286 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 79 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 213 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +__user_initial_stackheap 0000001C + +Symbol: __user_initial_stackheap + Definitions + At line 379 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 377 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s +Comment: __user_initial_stackheap used once +83 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Absolute symbols + +Heap_Size 00000200 + +Symbol: Heap_Size + Definitions + At line 44 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + Uses + At line 48 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 383 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +Stack_Size 00000400 + +Symbol: Stack_Size + Definitions + At line 33 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + Uses + At line 36 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s + At line 382 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + +__Vectors_Size 00000158 + +Symbol: __Vectors_Size + Definitions + At line 152 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 59 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1 +921VK035.s +Comment: __Vectors_Size used once +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +External symbols + +SystemInit 00000000 + +Symbol: SystemInit + Definitions + At line 160 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 161 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s +Comment: SystemInit used once +__main 00000000 + +Symbol: __main + Definitions + At line 159 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + At line 163 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s +Comment: __main used once +__use_two_region_memory 00000000 + +Symbol: __use_two_region_memory + Definitions + At line 376 in file platform\Device\NIIET\K1921VK035\Source\ARM\startup_K +1921VK035.s + Uses + None +Comment: __use_two_region_memory unused +3 symbols +436 symbols in table diff --git a/Listings/template.map b/Listings/template.map new file mode 100644 index 0000000..cdc10c8 --- /dev/null +++ b/Listings/template.map @@ -0,0 +1,1316 @@ +Component: ARM Compiler 5.06 update 7 (build 960) Tool: armlink [4d3601] + +============================================================================== + +Section Cross References + + system_k1921vk035.o(i.SystemCoreClockUpdate) refers to system_k1921vk035.o(.data) for .data + system_k1921vk035.o(i.SystemInit) refers to system_k1921vk035.o(i.ClkInit) for ClkInit + system_k1921vk035.o(i.SystemInit) refers to system_k1921vk035.o(i.FPUInit) for FPUInit + startup_k1921vk035.o(STACK) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_k1921vk035.o(HEAP) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_k1921vk035.o(RESET) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_k1921vk035.o(RESET) refers to startup_k1921vk035.o(STACK) for __initial_sp + startup_k1921vk035.o(RESET) refers to startup_k1921vk035.o(.text) for Reset_Handler + startup_k1921vk035.o(RESET) refers to vk035_it.o(i.NMI_Handler) for NMI_Handler + startup_k1921vk035.o(RESET) refers to vk035_it.o(i.HardFault_Handler) for HardFault_Handler + startup_k1921vk035.o(RESET) refers to vk035_it.o(i.MemManage_Handler) for MemManage_Handler + startup_k1921vk035.o(RESET) refers to vk035_it.o(i.BusFault_Handler) for BusFault_Handler + startup_k1921vk035.o(RESET) refers to vk035_it.o(i.UsageFault_Handler) for UsageFault_Handler + startup_k1921vk035.o(RESET) refers to vk035_it.o(i.SVC_Handler) for SVC_Handler + startup_k1921vk035.o(RESET) refers to vk035_it.o(i.DebugMon_Handler) for DebugMon_Handler + startup_k1921vk035.o(RESET) refers to vk035_it.o(i.PendSV_Handler) for PendSV_Handler + startup_k1921vk035.o(RESET) refers to vk035_it.o(i.SysTick_Handler) for SysTick_Handler + startup_k1921vk035.o(.text) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_k1921vk035.o(.text) refers to system_k1921vk035.o(i.SystemInit) for SystemInit + startup_k1921vk035.o(.text) refers to __main.o(!!!main) for __main + startup_k1921vk035.o(.text) refers to startup_k1921vk035.o(HEAP) for Heap_Mem + startup_k1921vk035.o(.text) refers to startup_k1921vk035.o(STACK) for Stack_Mem + main.o(i.assert_failed) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + main.o(i.assert_failed) refers to _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) for _printf_d + main.o(i.assert_failed) refers to _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) for _printf_s + main.o(i.assert_failed) refers to _printf_dec.o(.text) for _printf_int_dec + main.o(i.assert_failed) refers to _printf_str.o(.text) for _printf_str + main.o(i.assert_failed) refers to noretval__2printf.o(.text) for __2printf + main.o(i.main) refers to main.o(i.periph_init) for periph_init + main.o(i.periph_init) refers to _printf_pad.o(.text) for _printf_pre_padding + main.o(i.periph_init) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + main.o(i.periph_init) refers to _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) for _printf_d + main.o(i.periph_init) refers to _printf_dec.o(.text) for _printf_int_dec + main.o(i.periph_init) refers to system_k1921vk035.o(i.SystemCoreClockUpdate) for SystemCoreClockUpdate + main.o(i.periph_init) refers to rcu.o(i.sysclk_init) for sysclk_init + main.o(i.periph_init) refers to gpio.o(i.gpio_init) for gpio_init + main.o(i.periph_init) refers to retarget_conf.o(i.retarget_init) for retarget_init + main.o(i.periph_init) refers to dflt_clz.o(x$fpl$dfltu) for __aeabi_ui2d + main.o(i.periph_init) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv + main.o(i.periph_init) refers to dfix.o(x$fpl$dfix) for __aeabi_d2iz + main.o(i.periph_init) refers to noretval__2printf.o(.text) for __2printf + main.o(i.periph_init) refers to system_k1921vk035.o(.data) for SystemCoreClock + gpio.o(i.gpio_init) refers to plib035_gpio.o(i.GPIO_DeInit) for GPIO_DeInit + gpio.o(i.gpio_init) refers to plib035_gpio.o(i.GPIO_Init) for GPIO_Init + gpio.o(i.gpio_init) refers to gpio.o(.data) for .data + rcu.o(i.RCU_ClkOutConfig) refers to main.o(i.assert_failed) for assert_failed + rcu.o(i.sysclk_init) refers to plib035_rcu.o(i.RCU_PLL_AutoConfig) for RCU_PLL_AutoConfig + rcu.o(i.sysclk_init) refers to main.o(i.Error_Handler) for Error_Handler + rcu.o(i.sysclk_init) refers to system_k1921vk035.o(i.SystemCoreClockUpdate) for SystemCoreClockUpdate + rcu.o(i.sysclk_init) refers to rcu.o(i.RCU_ClkOutConfig) for RCU_ClkOutConfig + rcu.o(i.sysclk_init) refers to rcu.o(.data) for .data + vk035_it.o(i.SysTick_Handler) refers to system_k1921vk035.o(.data) for uwTick + plib035_adc.o(i.ADC_DC_Config) refers to main.o(i.assert_failed) for assert_failed + plib035_adc.o(i.ADC_DC_Config) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init + plib035_adc.o(i.ADC_DC_Init) refers to main.o(i.assert_failed) for assert_failed + plib035_adc.o(i.ADC_DC_Init) refers to plib035_adc.o(i.ADC_DC_Config) for ADC_DC_Config + plib035_adc.o(i.ADC_DC_Init) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init + plib035_adc.o(i.ADC_DeInit) refers to plib035_adc.o(i.RCU_ADCRstCmd) for RCU_ADCRstCmd + plib035_adc.o(i.ADC_SEQ_DCEnableCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_adc.o(i.ADC_SEQ_DCEnableCmd) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init + plib035_adc.o(i.ADC_SEQ_Init) refers to main.o(i.assert_failed) for assert_failed + plib035_adc.o(i.ADC_SEQ_Init) refers to plib035_adc.o(i.ADC_SEQ_ReqConfig) for ADC_SEQ_ReqConfig + plib035_adc.o(i.ADC_SEQ_Init) refers to plib035_adc.o(i.ADC_SEQ_DCEnableCmd) for ADC_SEQ_DCEnableCmd + plib035_adc.o(i.ADC_SEQ_ReqConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_adc.o(i.ADC_SEQ_ReqConfig) refers to plib035_adc.o(i.ADC_SEQ_Init) for i.ADC_SEQ_Init + plib035_adc.o(i.RCU_ADCRstCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_dma.o(i.DMA_ChannelInit) refers to main.o(i.assert_failed) for assert_failed + plib035_dma.o(i.DMA_Init) refers to plib035_dma.o(i.DMA_ProtectConfig) for DMA_ProtectConfig + plib035_dma.o(i.DMA_Init) refers to main.o(i.assert_failed) for assert_failed + plib035_dma.o(i.DMA_ProtectConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_dma.o(i.DMA_ProtectConfig) refers to plib035_dma.o(i.DMA_Init) for i.DMA_Init + plib035_ecap.o(i.ECAP_Capture_Init) refers to main.o(i.assert_failed) for assert_failed + plib035_ecap.o(i.ECAP_Capture_Init) refers to plib035_ecap.o(i.ECAP_Init) for i.ECAP_Init + plib035_ecap.o(i.ECAP_DeInit) refers to main.o(i.assert_failed) for assert_failed + plib035_ecap.o(i.ECAP_DeInit) refers to plib035_ecap.o(i.RCU_APBRstCmd) for RCU_APBRstCmd + plib035_ecap.o(i.ECAP_Init) refers to main.o(i.assert_failed) for assert_failed + plib035_ecap.o(i.ECAP_PWM_Init) refers to main.o(i.assert_failed) for assert_failed + plib035_ecap.o(i.ECAP_PWM_Init) refers to plib035_ecap.o(i.ECAP_Init) for i.ECAP_Init + plib035_ecap.o(i.RCU_APBRstCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_gpio.o(i.GPIO_AltFuncCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_gpio.o(i.GPIO_AltFuncCmd) refers to plib035_gpio.o(i.GPIO_DigitalCmd) for i.GPIO_DigitalCmd + plib035_gpio.o(i.GPIO_DeInit) refers to main.o(i.assert_failed) for assert_failed + plib035_gpio.o(i.GPIO_DeInit) refers to plib035_gpio.o(i.RCU_AHBRstCmd) for RCU_AHBRstCmd + plib035_gpio.o(i.GPIO_DigitalCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_gpio.o(i.GPIO_DriveModeConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_gpio.o(i.GPIO_DriveModeConfig) refers to plib035_gpio.o(i.GPIO_ModeConfig) for GPIO_ModeConfig + plib035_gpio.o(i.GPIO_InModeConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_gpio.o(i.GPIO_InModeConfig) refers to plib035_gpio.o(i.GPIO_ModeConfig) for GPIO_ModeConfig + plib035_gpio.o(i.GPIO_Init) refers to plib035_gpio.o(i.GPIO_OutCmd) for GPIO_OutCmd + plib035_gpio.o(i.GPIO_Init) refers to plib035_gpio.o(i.GPIO_AltFuncCmd) for GPIO_AltFuncCmd + plib035_gpio.o(i.GPIO_Init) refers to plib035_gpio.o(i.GPIO_OutModeConfig) for GPIO_OutModeConfig + plib035_gpio.o(i.GPIO_Init) refers to plib035_gpio.o(i.GPIO_InModeConfig) for GPIO_InModeConfig + plib035_gpio.o(i.GPIO_Init) refers to plib035_gpio.o(i.GPIO_PullModeConfig) for GPIO_PullModeConfig + plib035_gpio.o(i.GPIO_Init) refers to plib035_gpio.o(i.GPIO_DriveModeConfig) for GPIO_DriveModeConfig + plib035_gpio.o(i.GPIO_Init) refers to plib035_gpio.o(i.GPIO_DigitalCmd) for GPIO_DigitalCmd + plib035_gpio.o(i.GPIO_OutCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_gpio.o(i.GPIO_OutCmd) refers to plib035_gpio.o(i.GPIO_DigitalCmd) for i.GPIO_DigitalCmd + plib035_gpio.o(i.GPIO_OutModeConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_gpio.o(i.GPIO_OutModeConfig) refers to plib035_gpio.o(i.GPIO_ModeConfig) for GPIO_ModeConfig + plib035_gpio.o(i.GPIO_PullModeConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_gpio.o(i.GPIO_PullModeConfig) refers to plib035_gpio.o(i.GPIO_ModeConfig) for GPIO_ModeConfig + plib035_gpio.o(i.RCU_AHBRstCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_i2c.o(i.I2C_FSFreqConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_i2c.o(i.I2C_HSFreqConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_i2c.o(i.I2C_HSFreqConfig) refers to plib035_i2c.o(i.I2C_FSFreqConfig) for i.I2C_FSFreqConfig + plib035_mflash.o(i.MFLASH_EraseFull) refers to main.o(i.assert_failed) for assert_failed + plib035_mflash.o(i.MFLASH_EraseFull) refers to plib035_mflash.o(i.MFLASH_SetCmd) for MFLASH_SetCmd + plib035_mflash.o(i.MFLASH_EraseFull) refers to plib035_mflash.o(i.MFLASH_BusyStatus) for MFLASH_BusyStatus + plib035_mflash.o(i.MFLASH_ErasePage) refers to main.o(i.assert_failed) for assert_failed + plib035_mflash.o(i.MFLASH_ErasePage) refers to plib035_mflash.o(i.MFLASH_SetCmd) for MFLASH_SetCmd + plib035_mflash.o(i.MFLASH_ErasePage) refers to plib035_mflash.o(i.MFLASH_BusyStatus) for MFLASH_BusyStatus + plib035_mflash.o(i.MFLASH_ReadData) refers to main.o(i.assert_failed) for assert_failed + plib035_mflash.o(i.MFLASH_ReadData) refers to plib035_mflash.o(i.MFLASH_SetCmd) for MFLASH_SetCmd + plib035_mflash.o(i.MFLASH_ReadData) refers to plib035_mflash.o(i.MFLASH_BusyStatus) for MFLASH_BusyStatus + plib035_mflash.o(i.MFLASH_WriteData) refers to main.o(i.assert_failed) for assert_failed + plib035_mflash.o(i.MFLASH_WriteData) refers to plib035_mflash.o(i.MFLASH_SetCmd) for MFLASH_SetCmd + plib035_mflash.o(i.MFLASH_WriteData) refers to plib035_mflash.o(i.MFLASH_BusyStatus) for MFLASH_BusyStatus + plib035_mflash.o(i.MFLASH_WriteData) refers to plib035_mflash.o(i.MFLASH_ReadData) for i.MFLASH_ReadData + plib035_pwm.o(i.PWM_AQ_ActionAConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_AQ_ActionBConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_AQ_Init) refers to plib035_pwm.o(i.PWM_AQ_ActionAConfig) for PWM_AQ_ActionAConfig + plib035_pwm.o(i.PWM_AQ_Init) refers to plib035_pwm.o(i.PWM_AQ_ActionBConfig) for PWM_AQ_ActionBConfig + plib035_pwm.o(i.PWM_CMP_CmpADirectLoadCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_CMP_CmpALoadEventConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_CMP_Init) refers to plib035_pwm.o(i.PWM_CMP_CmpALoadEventConfig) for PWM_CMP_CmpALoadEventConfig + plib035_pwm.o(i.PWM_CMP_Init) refers to plib035_pwm.o(i.PWM_CMP_CmpADirectLoadCmd) for PWM_CMP_CmpADirectLoadCmd + plib035_pwm.o(i.PWM_CMP_Init) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_CMP_Init) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_DB_Init) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_DB_Init) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_DeInit) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_DeInit) refers to plib035_pwm.o(i.RCU_APBRstCmd) for RCU_APBRstCmd + plib035_pwm.o(i.PWM_ET_Init) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_ET_Init) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_HD_Init) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_HD_Init) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_TB_ClkDivConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_TB_ClkDivConfig) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.PWM_TB_Init) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_TB_Init) refers to plib035_pwm.o(i.PWM_TB_ClkDivConfig) for PWM_TB_ClkDivConfig + plib035_pwm.o(i.PWM_TZ_Init) refers to main.o(i.assert_failed) for assert_failed + plib035_pwm.o(i.PWM_TZ_Init) refers to plib035_pwm.o(i.PWM_TB_Init) for i.PWM_TB_Init + plib035_pwm.o(i.RCU_APBRstCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_qep.o(i.QEP_CAP_Init) refers to main.o(i.assert_failed) for assert_failed + plib035_qep.o(i.QEP_CAP_Init) refers to plib035_qep.o(i.QEP_PC_Init) for i.QEP_PC_Init + plib035_qep.o(i.QEP_CMP_Init) refers to main.o(i.assert_failed) for assert_failed + plib035_qep.o(i.QEP_CMP_Init) refers to plib035_qep.o(i.QEP_PC_Init) for i.QEP_PC_Init + plib035_qep.o(i.QEP_DeInit) refers to plib035_qep.o(i.RCU_APBRstCmd) for RCU_APBRstCmd + plib035_qep.o(i.QEP_PC_Init) refers to main.o(i.assert_failed) for assert_failed + plib035_qep.o(i.RCU_APBRstCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_rcu.o(i.MFLASH_LatencyConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_rcu.o(i.RCU_GetADCClkFreq) refers to plib035_rcu.o(i.getPeriphClkFreq) for getPeriphClkFreq + plib035_rcu.o(i.RCU_GetClkOutFreq) refers to plib035_rcu.o(i.getSysPeriphClkFreq) for getSysPeriphClkFreq + plib035_rcu.o(i.RCU_GetPLLDivClkFreq) refers to plib035_rcu.o(i.RCU_GetPLLClkFreq) for RCU_GetPLLClkFreq + plib035_rcu.o(i.RCU_GetSPIClkFreq) refers to plib035_rcu.o(i.getPeriphClkFreq) for getPeriphClkFreq + plib035_rcu.o(i.RCU_GetSysClkFreq) refers to plib035_rcu.o(i.getSysClkFreq) for getSysClkFreq + plib035_rcu.o(i.RCU_GetTraceClkFreq) refers to plib035_rcu.o(i.getSysPeriphClkFreq) for getSysPeriphClkFreq + plib035_rcu.o(i.RCU_GetUARTClkFreq) refers to plib035_rcu.o(i.getPeriphClkFreq) for getPeriphClkFreq + plib035_rcu.o(i.RCU_GetWDTClkFreq) refers to plib035_rcu.o(i.getSysPeriphClkFreq) for getSysPeriphClkFreq + plib035_rcu.o(i.RCU_PLL_AutoConfig) refers to plib035_rcu.o(i.RCU_PLL_StructInit) for RCU_PLL_StructInit + plib035_rcu.o(i.RCU_PLL_AutoConfig) refers to plib035_rcu.o(i.RCU_PLL_Init) for RCU_PLL_Init + plib035_rcu.o(i.RCU_PLL_AutoConfig) refers to plib035_rcu.o(i.MFLASH_LatencyConfig) for MFLASH_LatencyConfig + plib035_rcu.o(i.RCU_PLL_AutoConfig) refers to plib035_rcu.o(i.RCU_SysClkChangeCmd) for RCU_SysClkChangeCmd + plib035_rcu.o(i.RCU_PLL_DeInit) refers to plib035_rcu.o(i.RCU_PLL_OutCmd) for RCU_PLL_OutCmd + plib035_rcu.o(i.RCU_PLL_Init) refers to main.o(i.assert_failed) for assert_failed + plib035_rcu.o(i.RCU_PLL_Init) refers to plib035_rcu.o(i.RCU_PLL_OutCmd) for RCU_PLL_OutCmd + plib035_rcu.o(i.RCU_PLL_OutCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_rcu.o(i.RCU_SysClkChangeCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_rcu.o(i.getPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetOSIClkFreq) for RCU_GetOSIClkFreq + plib035_rcu.o(i.getPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetOSEClkFreq) for RCU_GetOSEClkFreq + plib035_rcu.o(i.getPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetPLLClkFreq) for RCU_GetPLLClkFreq + plib035_rcu.o(i.getPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetPLLDivClkFreq) for RCU_GetPLLDivClkFreq + plib035_rcu.o(i.getSysClkFreq) refers to plib035_rcu.o(i.RCU_GetPLLDivClkFreq) for RCU_GetPLLDivClkFreq + plib035_rcu.o(i.getSysClkFreq) refers to plib035_rcu.o(i.RCU_GetOSIClkFreq) for RCU_GetOSIClkFreq + plib035_rcu.o(i.getSysClkFreq) refers to plib035_rcu.o(i.RCU_GetOSEClkFreq) for RCU_GetOSEClkFreq + plib035_rcu.o(i.getSysClkFreq) refers to plib035_rcu.o(i.RCU_GetPLLClkFreq) for RCU_GetPLLClkFreq + plib035_rcu.o(i.getSysPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetPLLDivClkFreq) for RCU_GetPLLDivClkFreq + plib035_rcu.o(i.getSysPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetOSEClkFreq) for RCU_GetOSEClkFreq + plib035_rcu.o(i.getSysPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetPLLClkFreq) for RCU_GetPLLClkFreq + plib035_rcu.o(i.getSysPeriphClkFreq) refers to plib035_rcu.o(i.RCU_GetOSIClkFreq) for RCU_GetOSIClkFreq + plib035_spi.o(i.RCU_SPIRstCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_spi.o(i.SPI_DeInit) refers to plib035_spi.o(i.RCU_SPIRstCmd) for RCU_SPIRstCmd + plib035_spi.o(i.SPI_Init) refers to main.o(i.assert_failed) for assert_failed + plib035_tmr.o(i.TMR_FreqConfig) refers to plib035_tmr.o(i.TMR_SetLoad) for TMR_SetLoad + plib035_tmr.o(i.TMR_PeriodConfig) refers to plib035_tmr.o(i.TMR_SetLoad) for TMR_SetLoad + plib035_tmr.o(i.TMR_SetLoad) refers to main.o(i.assert_failed) for assert_failed + plib035_uart.o(i.RCU_UARTRstCmd) refers to main.o(i.assert_failed) for assert_failed + plib035_uart.o(i.UART_AutoBaudConfig) refers to main.o(i.assert_failed) for assert_failed + plib035_uart.o(i.UART_AutoBaudConfig) refers to plib035_rcu.o(i.RCU_GetUARTClkFreq) for RCU_GetUARTClkFreq + plib035_uart.o(i.UART_DeInit) refers to main.o(i.assert_failed) for assert_failed + plib035_uart.o(i.UART_DeInit) refers to plib035_uart.o(i.RCU_UARTRstCmd) for RCU_UARTRstCmd + plib035_uart.o(i.UART_Init) refers to plib035_uart.o(i.UART_AutoBaudConfig) for UART_AutoBaudConfig + plib035_uart.o(i.UART_Init) refers to main.o(i.assert_failed) for assert_failed + retarget.o(.rev16_text) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi + retarget.o(.revsh_text) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi + retarget.o(.rrx_text) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi + retarget.o(i._sys_exit) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi + retarget.o(i._ttywrch) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi + retarget.o(i._ttywrch) refers to retarget_conf.o(i.retarget_put_char) for retarget_put_char + retarget.o(i.ferror) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi + retarget.o(i.fgetc) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi + retarget.o(i.fgetc) refers to retarget_conf.o(i.retarget_get_char) for retarget_get_char + retarget.o(i.fputc) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi + retarget.o(i.fputc) refers to retarget_conf.o(i.retarget_put_char) for retarget_put_char + retarget.o(.data) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi + retarget.o(.data) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi + retarget_conf.o(i.retarget_init) refers to system_k1921vk035.o(.data) for SystemCoreClock + __2printf.o(.text) refers to _printf_char_file.o(.text) for _printf_char_file + __2printf.o(.text) refers to retarget.o(.data) for __stdout + noretval__2printf.o(.text) refers to _printf_char_file.o(.text) for _printf_char_file + noretval__2printf.o(.text) refers to retarget.o(.data) for __stdout + __printf.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + _printf_str.o(.text) refers (Special) to _printf_char.o(.text) for _printf_cs_common + _printf_str.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_str.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding + _printf_dec.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + __printf_flags.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags.o(.text) refers to __printf_flags.o(.constdata) for .constdata + __printf_ss.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_ss.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_ss.o(.text) refers to __printf_flags_ss.o(.constdata) for .constdata + __printf_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit + __printf_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit + __printf_flags_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_wp.o(.text) refers to __printf_flags_wp.o(.constdata) for .constdata + __printf_ss_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit + __printf_ss_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_ss_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit + __printf_flags_ss_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_ss_wp.o(.text) refers to __printf_flags_ss_wp.o(.constdata) for .constdata + _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) refers (Weak) to _printf_char.o(.text) for _printf_string + _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) refers (Weak) to _printf_dec.o(.text) for _printf_int_dec + _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) refers (Special) to _printf_percent_end.o(.ARM.Collect$$_printf_percent$$00000017) for _printf_percent_end + __main.o(!!!main) refers to __rtentry.o(.ARM.Collect$$rtentry$$00000000) for __rt_entry + ddiv.o(x$fpl$drdiv) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + ddiv.o(x$fpl$drdiv) refers to ddiv.o(x$fpl$ddiv) for ddiv_entry + ddiv.o(x$fpl$ddiv) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + ddiv.o(x$fpl$ddiv) refers to dretinf.o(x$fpl$dretinf) for __fpl_dretinf + ddiv.o(x$fpl$ddiv) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + dfix.o(x$fpl$dfix) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dfix.o(x$fpl$dfix) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + dfix.o(x$fpl$dfixr) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dfix.o(x$fpl$dfixr) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + dflt_clz.o(x$fpl$dfltu) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dflt_clz.o(x$fpl$dflt) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dflt_clz.o(x$fpl$dfltn) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for __rt_entry_li + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for __rt_entry_main + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) for __rt_entry_postli_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000009) for __rt_entry_postsh_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000002) for __rt_entry_presh_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for __rt_entry_sh + _printf_intcommon.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_intcommon.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_intcommon.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding + _printf_char.o(.text) refers (Weak) to _printf_str.o(.text) for _printf_str + _printf_char_file.o(.text) refers to _printf_char_common.o(.text) for _printf_char_common + _printf_char_file.o(.text) refers to retarget.o(i.ferror) for ferror + _printf_char_file.o(.text) refers to retarget.o(i.fputc) for fputc + dnaninf.o(x$fpl$dnaninf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dretinf.o(x$fpl$dretinf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + __rtentry2.o(.ARM.Collect$$rtentry$$00000008) refers to boardinit2.o(.text) for _platform_post_stackheap_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) refers to libinit.o(.ARM.Collect$$libinit$$00000000) for __rt_lib_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) refers to boardinit3.o(.text) for _platform_post_lib_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to main.o(i.main) for main + __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to exit.o(.text) for exit + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000001) for .ARM.Collect$$rtentry$$00000001 + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000008) for .ARM.Collect$$rtentry$$00000008 + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for .ARM.Collect$$rtentry$$0000000A + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) for .ARM.Collect$$rtentry$$0000000B + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for .ARM.Collect$$rtentry$$0000000D + __rtentry4.o(.ARM.Collect$$rtentry$$00000004) refers to sys_stackheap_outer.o(.text) for __user_setup_stackheap + __rtentry4.o(.ARM.exidx) refers to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for .ARM.Collect$$rtentry$$00000004 + _printf_char_common.o(.text) refers to __printf_wp.o(.text) for __printf + sys_stackheap_outer.o(.text) refers to libspace.o(.text) for __user_perproc_libspace + sys_stackheap_outer.o(.text) refers to startup_k1921vk035.o(.text) for __user_initial_stackheap + exit.o(.text) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for __rt_exit + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002E) for __rt_lib_init_alloca_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002C) for __rt_lib_init_argv_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001B) for __rt_lib_init_atexit_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000021) for __rt_lib_init_clock_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000032) for __rt_lib_init_cpp_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000030) for __rt_lib_init_exceptions_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000001) for __rt_lib_init_fp_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001F) for __rt_lib_init_fp_trap_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000023) for __rt_lib_init_getenv_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000A) for __rt_lib_init_heap_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000011) for __rt_lib_init_lc_collate_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000013) for __rt_lib_init_lc_ctype_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000015) for __rt_lib_init_lc_monetary_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000017) for __rt_lib_init_lc_numeric_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000019) for __rt_lib_init_lc_time_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000004) for __rt_lib_init_preinit_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000E) for __rt_lib_init_rand_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000033) for __rt_lib_init_return + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001D) for __rt_lib_init_signal_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000025) for __rt_lib_init_stdio_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000C) for __rt_lib_init_user_alloc_1 + libspace.o(.text) refers to libspace.o(.bss) for __libspace_start + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 + rtexit.o(.ARM.exidx) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for .ARM.Collect$$rtexit$$00000000 + libinit2.o(.ARM.Collect$$libinit$$00000001) refers to fpinit.o(x$fpl$fpinit) for _fp_init + libinit2.o(.ARM.Collect$$libinit$$00000010) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000012) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000014) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000016) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000018) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000026) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer + libinit2.o(.ARM.Collect$$libinit$$00000027) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer + rtexit2.o(.ARM.Collect$$rtexit$$00000003) refers to libshutdown.o(.ARM.Collect$$libshutdown$$00000000) for __rt_lib_shutdown + rtexit2.o(.ARM.Collect$$rtexit$$00000004) refers to retarget.o(i._sys_exit) for _sys_exit + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000001) for .ARM.Collect$$rtexit$$00000001 + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for .ARM.Collect$$rtexit$$00000003 + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for .ARM.Collect$$rtexit$$00000004 + argv_veneer.o(.emb_text) refers to no_argv.o(.text) for __ARM_get_argv + _get_argv_nomalloc.o(.text) refers (Special) to hrguard.o(.text) for __heap_region$guard + _get_argv_nomalloc.o(.text) refers to defsig_rtmem_outer.o(.text) for __rt_SIGRTMEM + _get_argv_nomalloc.o(.text) refers to sys_command.o(.text) for _sys_command_string + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) for __rt_lib_shutdown_cpp_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) for __rt_lib_shutdown_fini_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000009) for __rt_lib_shutdown_fp_trap_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000011) for __rt_lib_shutdown_heap_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000012) for __rt_lib_shutdown_return + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) for __rt_lib_shutdown_signal_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000006) for __rt_lib_shutdown_stdio_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000E) for __rt_lib_shutdown_user_alloc_1 + sys_command.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_command.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + defsig_rtmem_outer.o(.text) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner + defsig_rtmem_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit + defsig_rtmem_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise + rt_raise.o(.text) refers to __raise.o(.text) for __raise + rt_raise.o(.text) refers to retarget.o(i._sys_exit) for _sys_exit + defsig_exit.o(.text) refers to retarget.o(i._sys_exit) for _sys_exit + defsig_rtmem_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + __raise.o(.text) refers to defsig.o(CL$$defsig) for __default_signal_handler + defsig_general.o(.text) refers to retarget.o(i._ttywrch) for _ttywrch + defsig.o(CL$$defsig) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner + defsig_abrt_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_fpe_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtred_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_stak_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_pvfn_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_cppl_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_segv_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_other.o(.text) refers to defsig_general.o(.text) for __default_signal_display + + +============================================================================== + +Removing Unused input sections from the image. + + Removing system_k1921vk035.o(.rev16_text), (4 bytes). + Removing system_k1921vk035.o(.revsh_text), (4 bytes). + Removing system_k1921vk035.o(.rrx_text), (6 bytes). + Removing main.o(.rev16_text), (4 bytes). + Removing main.o(.revsh_text), (4 bytes). + Removing main.o(.rrx_text), (6 bytes). + Removing gpio.o(.rev16_text), (4 bytes). + Removing gpio.o(.revsh_text), (4 bytes). + Removing gpio.o(.rrx_text), (6 bytes). + Removing rcu.o(.rev16_text), (4 bytes). + Removing rcu.o(.revsh_text), (4 bytes). + Removing rcu.o(.rrx_text), (6 bytes). + Removing vk035_it.o(.rev16_text), (4 bytes). + Removing vk035_it.o(.revsh_text), (4 bytes). + Removing vk035_it.o(.rrx_text), (6 bytes). + Removing plib035_adc.o(.rev16_text), (4 bytes). + Removing plib035_adc.o(.revsh_text), (4 bytes). + Removing plib035_adc.o(.rrx_text), (6 bytes). + Removing plib035_adc.o(i.ADC_DC_Config), (116 bytes). + Removing plib035_adc.o(i.ADC_DC_Init), (316 bytes). + Removing plib035_adc.o(i.ADC_DC_StructInit), (18 bytes). + Removing plib035_adc.o(i.ADC_DeInit), (18 bytes). + Removing plib035_adc.o(i.ADC_SEQ_DCEnableCmd), (96 bytes). + Removing plib035_adc.o(i.ADC_SEQ_Init), (568 bytes). + Removing plib035_adc.o(i.ADC_SEQ_ReqConfig), (104 bytes). + Removing plib035_adc.o(i.ADC_SEQ_StructInit), (52 bytes). + Removing plib035_adc.o(i.RCU_ADCRstCmd), (80 bytes). + Removing plib035_can.o(.rev16_text), (4 bytes). + Removing plib035_can.o(.revsh_text), (4 bytes). + Removing plib035_can.o(.rrx_text), (6 bytes). + Removing plib035_dma.o(.rev16_text), (4 bytes). + Removing plib035_dma.o(.revsh_text), (4 bytes). + Removing plib035_dma.o(.rrx_text), (6 bytes). + Removing plib035_dma.o(i.DMA_ChannelDeInit), (10 bytes). + Removing plib035_dma.o(i.DMA_ChannelInit), (492 bytes). + Removing plib035_dma.o(i.DMA_ChannelStructInit), (40 bytes). + Removing plib035_dma.o(i.DMA_DeInit), (28 bytes). + Removing plib035_dma.o(i.DMA_Init), (292 bytes). + Removing plib035_dma.o(i.DMA_ProtectConfig), (100 bytes). + Removing plib035_dma.o(i.DMA_StructInit), (26 bytes). + Removing plib035_ecap.o(.rev16_text), (4 bytes). + Removing plib035_ecap.o(.revsh_text), (4 bytes). + Removing plib035_ecap.o(.rrx_text), (6 bytes). + Removing plib035_ecap.o(i.ECAP_Capture_Init), (632 bytes). + Removing plib035_ecap.o(i.ECAP_Capture_StructInit), (28 bytes). + Removing plib035_ecap.o(i.ECAP_DeInit), (124 bytes). + Removing plib035_ecap.o(i.ECAP_Init), (276 bytes). + Removing plib035_ecap.o(i.ECAP_PWM_Init), (144 bytes). + Removing plib035_ecap.o(i.ECAP_PWM_StructInit), (18 bytes). + Removing plib035_ecap.o(i.ECAP_StructInit), (12 bytes). + Removing plib035_ecap.o(i.RCU_APBRstCmd), (152 bytes). + Removing plib035_gpio.o(.rev16_text), (4 bytes). + Removing plib035_gpio.o(.revsh_text), (4 bytes). + Removing plib035_gpio.o(.rrx_text), (6 bytes). + Removing plib035_gpio.o(i.GPIO_StructInit), (24 bytes). + Removing plib035_i2c.o(.rev16_text), (4 bytes). + Removing plib035_i2c.o(.revsh_text), (4 bytes). + Removing plib035_i2c.o(.rrx_text), (6 bytes). + Removing plib035_i2c.o(i.I2C_FSFreqConfig), (104 bytes). + Removing plib035_i2c.o(i.I2C_HSFreqConfig), (72 bytes). + Removing plib035_mflash.o(.rev16_text), (4 bytes). + Removing plib035_mflash.o(.revsh_text), (4 bytes). + Removing plib035_mflash.o(.rrx_text), (6 bytes). + Removing plib035_mflash.o(i.MFLASH_BusyStatus), (16 bytes). + Removing plib035_mflash.o(i.MFLASH_EraseFull), (92 bytes). + Removing plib035_mflash.o(i.MFLASH_ErasePage), (132 bytes). + Removing plib035_mflash.o(i.MFLASH_ReadData), (212 bytes). + Removing plib035_mflash.o(i.MFLASH_SetCmd), (20 bytes). + Removing plib035_mflash.o(i.MFLASH_WriteData), (180 bytes). + Removing plib035_pmu.o(.rev16_text), (4 bytes). + Removing plib035_pmu.o(.revsh_text), (4 bytes). + Removing plib035_pmu.o(.rrx_text), (6 bytes). + Removing plib035_pwm.o(.rev16_text), (4 bytes). + Removing plib035_pwm.o(.revsh_text), (4 bytes). + Removing plib035_pwm.o(.rrx_text), (6 bytes). + Removing plib035_pwm.o(i.PWM_AQ_ActionAConfig), (160 bytes). + Removing plib035_pwm.o(i.PWM_AQ_ActionBConfig), (160 bytes). + Removing plib035_pwm.o(i.PWM_AQ_Init), (130 bytes). + Removing plib035_pwm.o(i.PWM_AQ_StructInit), (28 bytes). + Removing plib035_pwm.o(i.PWM_CMP_CmpADirectLoadCmd), (112 bytes). + Removing plib035_pwm.o(i.PWM_CMP_CmpALoadEventConfig), (120 bytes). + Removing plib035_pwm.o(i.PWM_CMP_Init), (168 bytes). + Removing plib035_pwm.o(i.PWM_CMP_StructInit), (16 bytes). + Removing plib035_pwm.o(i.PWM_DB_Init), (292 bytes). + Removing plib035_pwm.o(i.PWM_DB_StructInit), (14 bytes). + Removing plib035_pwm.o(i.PWM_DeInit), (116 bytes). + Removing plib035_pwm.o(i.PWM_ET_Init), (680 bytes). + Removing plib035_pwm.o(i.PWM_ET_StructInit), (30 bytes). + Removing plib035_pwm.o(i.PWM_HD_Init), (336 bytes). + Removing plib035_pwm.o(i.PWM_HD_StructInit), (16 bytes). + Removing plib035_pwm.o(i.PWM_TB_ClkDivConfig), (152 bytes). + Removing plib035_pwm.o(i.PWM_TB_Init), (532 bytes). + Removing plib035_pwm.o(i.PWM_TB_StructInit), (24 bytes). + Removing plib035_pwm.o(i.PWM_TZ_Init), (248 bytes). + Removing plib035_pwm.o(i.PWM_TZ_StructInit), (12 bytes). + Removing plib035_pwm.o(i.RCU_APBRstCmd), (152 bytes). + Removing plib035_qep.o(.rev16_text), (4 bytes). + Removing plib035_qep.o(.revsh_text), (4 bytes). + Removing plib035_qep.o(.rrx_text), (6 bytes). + Removing plib035_qep.o(i.QEP_CAP_Init), (224 bytes). + Removing plib035_qep.o(i.QEP_CAP_StructInit), (18 bytes). + Removing plib035_qep.o(i.QEP_CMP_Init), (180 bytes). + Removing plib035_qep.o(i.QEP_CMP_StructInit), (18 bytes). + Removing plib035_qep.o(i.QEP_DeInit), (26 bytes). + Removing plib035_qep.o(i.QEP_PC_Init), (280 bytes). + Removing plib035_qep.o(i.QEP_PC_StructInit), (24 bytes). + Removing plib035_qep.o(i.RCU_APBRstCmd), (152 bytes). + Removing plib035_rcu.o(.rev16_text), (4 bytes). + Removing plib035_rcu.o(.revsh_text), (4 bytes). + Removing plib035_rcu.o(.rrx_text), (6 bytes). + Removing plib035_rcu.o(i.RCU_GetADCClkFreq), (48 bytes). + Removing plib035_rcu.o(i.RCU_GetClkOutFreq), (44 bytes). + Removing plib035_rcu.o(i.RCU_GetOSEClkFreq), (8 bytes). + Removing plib035_rcu.o(i.RCU_GetOSIClkFreq), (8 bytes). + Removing plib035_rcu.o(i.RCU_GetPLLClkFreq), (56 bytes). + Removing plib035_rcu.o(i.RCU_GetPLLDivClkFreq), (28 bytes). + Removing plib035_rcu.o(i.RCU_GetSPIClkFreq), (48 bytes). + Removing plib035_rcu.o(i.RCU_GetSysClkFreq), (16 bytes). + Removing plib035_rcu.o(i.RCU_GetTraceClkFreq), (44 bytes). + Removing plib035_rcu.o(i.RCU_GetUARTClkFreq), (48 bytes). + Removing plib035_rcu.o(i.RCU_GetWDTClkFreq), (44 bytes). + Removing plib035_rcu.o(i.RCU_PLL_DeInit), (24 bytes). + Removing plib035_rcu.o(i.getPeriphClkFreq), (38 bytes). + Removing plib035_rcu.o(i.getSysClkFreq), (38 bytes). + Removing plib035_rcu.o(i.getSysPeriphClkFreq), (38 bytes). + Removing plib035_spi.o(.rev16_text), (4 bytes). + Removing plib035_spi.o(.revsh_text), (4 bytes). + Removing plib035_spi.o(.rrx_text), (6 bytes). + Removing plib035_spi.o(i.RCU_SPIRstCmd), (80 bytes). + Removing plib035_spi.o(i.SPI_DeInit), (18 bytes). + Removing plib035_spi.o(i.SPI_Init), (228 bytes). + Removing plib035_spi.o(i.SPI_StructInit), (18 bytes). + Removing plib035_tmr.o(.rev16_text), (4 bytes). + Removing plib035_tmr.o(.revsh_text), (4 bytes). + Removing plib035_tmr.o(.rrx_text), (6 bytes). + Removing plib035_tmr.o(i.TMR_FreqConfig), (8 bytes). + Removing plib035_tmr.o(i.TMR_PeriodConfig), (16 bytes). + Removing plib035_tmr.o(i.TMR_SetLoad), (100 bytes). + Removing plib035_uart.o(.rev16_text), (4 bytes). + Removing plib035_uart.o(.revsh_text), (4 bytes). + Removing plib035_uart.o(.rrx_text), (6 bytes). + Removing plib035_uart.o(i.RCU_UARTRstCmd), (84 bytes). + Removing plib035_uart.o(i.UART_AutoBaudConfig), (260 bytes). + Removing plib035_uart.o(i.UART_DeInit), (100 bytes). + Removing plib035_uart.o(i.UART_Init), (316 bytes). + Removing plib035_uart.o(i.UART_StructInit), (24 bytes). + Removing plib035_wdt.o(.rev16_text), (4 bytes). + Removing plib035_wdt.o(.revsh_text), (4 bytes). + Removing plib035_wdt.o(.rrx_text), (6 bytes). + Removing retarget.o(.rev16_text), (4 bytes). + Removing retarget.o(.revsh_text), (4 bytes). + Removing retarget.o(.rrx_text), (6 bytes). + Removing retarget.o(i._ttywrch), (4 bytes). + Removing retarget.o(i.fgetc), (4 bytes). + Removing retarget.o(.data), (4 bytes). + Removing retarget_conf.o(.rev16_text), (4 bytes). + Removing retarget_conf.o(.revsh_text), (4 bytes). + Removing retarget_conf.o(.rrx_text), (6 bytes). + Removing retarget_conf.o(i.retarget_get_char), (20 bytes). + +159 unused section(s) (total 11136 bytes) removed from the image. + +============================================================================== + +Image Symbol Table + + Local Symbols + + Symbol Name Value Ov Type Size Object(Section) + + RESET 0x00000000 Section 344 startup_k1921vk035.o(RESET) + ../clib/angel/boardlib.s 0x00000000 Number 0 boardshut.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit3.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit2.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit1.o ABSOLUTE + ../clib/angel/dczerorl2.s 0x00000000 Number 0 __dczerorl2.o ABSOLUTE + ../clib/angel/handlers.s 0x00000000 Number 0 __scatter_zi.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 rtexit2.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry2.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 rtexit.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry4.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_raise.o ABSOLUTE + ../clib/angel/scatter.s 0x00000000 Number 0 __scatter.o ABSOLUTE + ../clib/angel/startup.s 0x00000000 Number 0 __main.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 sys_stackheap_outer.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 indicate_semi.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 use_no_semi.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 libspace.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_command.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 argv_veneer.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 argv_veneer.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 _get_argv_nomalloc.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 no_argv.o ABSOLUTE + ../clib/heapalloc.c 0x00000000 Number 0 hrguard.o ABSOLUTE + ../clib/heapaux.c 0x00000000 Number 0 heapauxi.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libshutdown.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libshutdown2.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libinit2.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libinit.o ABSOLUTE + ../clib/misc.s 0x00000000 Number 0 printf_stubs.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_dec.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_ss.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_flags_ss.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_wp.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_flags_wp.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_flags.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_flags_ss_wp.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_nopercent.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_ss_wp.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_char_file.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_char.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_intcommon.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_char_common.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __2printf.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 noretval__2printf.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_pad.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_str.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_percent_end.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_s.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_d.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_percent.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtred_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_stak_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_pvfn_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_cppl_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_segv_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_other.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 __raise.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_formal.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_outer.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_general.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_abrt_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_exit.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_fpe_inner.o ABSOLUTE + ../clib/signal.s 0x00000000 Number 0 defsig.o ABSOLUTE + ../clib/stdlib.c 0x00000000 Number 0 exit.o ABSOLUTE + ../fplib/ddiv.s 0x00000000 Number 0 ddiv.o ABSOLUTE + ../fplib/dfix.s 0x00000000 Number 0 dfix.o ABSOLUTE + ../fplib/dflt.s 0x00000000 Number 0 dflt_clz.o ABSOLUTE + ../fplib/dnaninf.s 0x00000000 Number 0 dnaninf.o ABSOLUTE + ../fplib/dretinf.s 0x00000000 Number 0 dretinf.o ABSOLUTE + ../fplib/fpinit.s 0x00000000 Number 0 fpinit.o ABSOLUTE + ../fplib/usenofp.s 0x00000000 Number 0 usenofp.o ABSOLUTE + Core\App\gpio.c 0x00000000 Number 0 gpio.o ABSOLUTE + Core\App\main.c 0x00000000 Number 0 main.o ABSOLUTE + Core\App\rcu.c 0x00000000 Number 0 rcu.o ABSOLUTE + Core\App\vk035_it.c 0x00000000 Number 0 vk035_it.o ABSOLUTE + Core\\App\\gpio.c 0x00000000 Number 0 gpio.o ABSOLUTE + Core\\App\\main.c 0x00000000 Number 0 main.o ABSOLUTE + Core\\App\\rcu.c 0x00000000 Number 0 rcu.o ABSOLUTE + Core\\App\\vk035_it.c 0x00000000 Number 0 vk035_it.o ABSOLUTE + dc.s 0x00000000 Number 0 dc.o ABSOLUTE + platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1921VK035.s 0x00000000 Number 0 startup_k1921vk035.o ABSOLUTE + platform\Device\NIIET\K1921VK035\Source\system_K1921VK035.c 0x00000000 Number 0 system_k1921vk035.o ABSOLUTE + platform\\Device\\NIIET\\K1921VK035\\Source\\system_K1921VK035.c 0x00000000 Number 0 system_k1921vk035.o ABSOLUTE + platform\\plib035\\src\\plib035_adc.c 0x00000000 Number 0 plib035_adc.o ABSOLUTE + platform\\plib035\\src\\plib035_can.c 0x00000000 Number 0 plib035_can.o ABSOLUTE + platform\\plib035\\src\\plib035_dma.c 0x00000000 Number 0 plib035_dma.o ABSOLUTE + platform\\plib035\\src\\plib035_ecap.c 0x00000000 Number 0 plib035_ecap.o ABSOLUTE + platform\\plib035\\src\\plib035_gpio.c 0x00000000 Number 0 plib035_gpio.o ABSOLUTE + platform\\plib035\\src\\plib035_i2c.c 0x00000000 Number 0 plib035_i2c.o ABSOLUTE + platform\\plib035\\src\\plib035_mflash.c 0x00000000 Number 0 plib035_mflash.o ABSOLUTE + platform\\plib035\\src\\plib035_pmu.c 0x00000000 Number 0 plib035_pmu.o ABSOLUTE + platform\\plib035\\src\\plib035_pwm.c 0x00000000 Number 0 plib035_pwm.o ABSOLUTE + platform\\plib035\\src\\plib035_qep.c 0x00000000 Number 0 plib035_qep.o ABSOLUTE + platform\\plib035\\src\\plib035_rcu.c 0x00000000 Number 0 plib035_rcu.o ABSOLUTE + platform\\plib035\\src\\plib035_spi.c 0x00000000 Number 0 plib035_spi.o ABSOLUTE + platform\\plib035\\src\\plib035_tmr.c 0x00000000 Number 0 plib035_tmr.o ABSOLUTE + platform\\plib035\\src\\plib035_uart.c 0x00000000 Number 0 plib035_uart.o ABSOLUTE + platform\\plib035\\src\\plib035_wdt.c 0x00000000 Number 0 plib035_wdt.o ABSOLUTE + platform\\retarget\\retarget.c 0x00000000 Number 0 retarget.o ABSOLUTE + platform\\retarget\\retarget_conf.c 0x00000000 Number 0 retarget_conf.o ABSOLUTE + platform\plib035\src\plib035_adc.c 0x00000000 Number 0 plib035_adc.o ABSOLUTE + platform\plib035\src\plib035_can.c 0x00000000 Number 0 plib035_can.o ABSOLUTE + platform\plib035\src\plib035_dma.c 0x00000000 Number 0 plib035_dma.o ABSOLUTE + platform\plib035\src\plib035_ecap.c 0x00000000 Number 0 plib035_ecap.o ABSOLUTE + platform\plib035\src\plib035_gpio.c 0x00000000 Number 0 plib035_gpio.o ABSOLUTE + platform\plib035\src\plib035_i2c.c 0x00000000 Number 0 plib035_i2c.o ABSOLUTE + platform\plib035\src\plib035_mflash.c 0x00000000 Number 0 plib035_mflash.o ABSOLUTE + platform\plib035\src\plib035_pmu.c 0x00000000 Number 0 plib035_pmu.o ABSOLUTE + platform\plib035\src\plib035_pwm.c 0x00000000 Number 0 plib035_pwm.o ABSOLUTE + platform\plib035\src\plib035_qep.c 0x00000000 Number 0 plib035_qep.o ABSOLUTE + platform\plib035\src\plib035_rcu.c 0x00000000 Number 0 plib035_rcu.o ABSOLUTE + platform\plib035\src\plib035_spi.c 0x00000000 Number 0 plib035_spi.o ABSOLUTE + platform\plib035\src\plib035_tmr.c 0x00000000 Number 0 plib035_tmr.o ABSOLUTE + platform\plib035\src\plib035_uart.c 0x00000000 Number 0 plib035_uart.o ABSOLUTE + platform\plib035\src\plib035_wdt.c 0x00000000 Number 0 plib035_wdt.o ABSOLUTE + platform\retarget\retarget.c 0x00000000 Number 0 retarget.o ABSOLUTE + platform\retarget\retarget_conf.c 0x00000000 Number 0 retarget_conf.o ABSOLUTE + !!!main 0x00000158 Section 8 __main.o(!!!main) + !!!scatter 0x00000160 Section 52 __scatter.o(!!!scatter) + !!dczerorl2 0x00000194 Section 90 __dczerorl2.o(!!dczerorl2) + !!handler_zi 0x000001f0 Section 28 __scatter_zi.o(!!handler_zi) + .ARM.Collect$$_printf_percent$$00000000 0x0000020c Section 0 _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) + .ARM.Collect$$_printf_percent$$00000009 0x0000020c Section 6 _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) + .ARM.Collect$$_printf_percent$$00000014 0x00000212 Section 6 _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) + .ARM.Collect$$_printf_percent$$00000017 0x00000218 Section 4 _printf_percent_end.o(.ARM.Collect$$_printf_percent$$00000017) + .ARM.Collect$$libinit$$00000000 0x0000021c Section 2 libinit.o(.ARM.Collect$$libinit$$00000000) + .ARM.Collect$$libinit$$00000001 0x0000021e Section 4 libinit2.o(.ARM.Collect$$libinit$$00000001) + .ARM.Collect$$libinit$$00000004 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000004) + .ARM.Collect$$libinit$$0000000A 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000A) + .ARM.Collect$$libinit$$0000000C 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000C) + .ARM.Collect$$libinit$$0000000E 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000E) + .ARM.Collect$$libinit$$00000011 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000011) + .ARM.Collect$$libinit$$00000013 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000013) + .ARM.Collect$$libinit$$00000015 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000015) + .ARM.Collect$$libinit$$00000017 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000017) + .ARM.Collect$$libinit$$00000019 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000019) + .ARM.Collect$$libinit$$0000001B 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001B) + .ARM.Collect$$libinit$$0000001D 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001D) + .ARM.Collect$$libinit$$0000001F 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001F) + .ARM.Collect$$libinit$$00000021 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000021) + .ARM.Collect$$libinit$$00000023 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000023) + .ARM.Collect$$libinit$$00000025 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000025) + .ARM.Collect$$libinit$$0000002C 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000002C) + .ARM.Collect$$libinit$$0000002E 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000002E) + .ARM.Collect$$libinit$$00000030 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000030) + .ARM.Collect$$libinit$$00000032 0x00000222 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000032) + .ARM.Collect$$libinit$$00000033 0x00000222 Section 2 libinit2.o(.ARM.Collect$$libinit$$00000033) + .ARM.Collect$$libshutdown$$00000000 0x00000224 Section 2 libshutdown.o(.ARM.Collect$$libshutdown$$00000000) + .ARM.Collect$$libshutdown$$00000002 0x00000226 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) + .ARM.Collect$$libshutdown$$00000004 0x00000226 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) + .ARM.Collect$$libshutdown$$00000006 0x00000226 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000006) + .ARM.Collect$$libshutdown$$00000009 0x00000226 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000009) + .ARM.Collect$$libshutdown$$0000000C 0x00000226 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) + .ARM.Collect$$libshutdown$$0000000E 0x00000226 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000E) + .ARM.Collect$$libshutdown$$00000011 0x00000226 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000011) + .ARM.Collect$$libshutdown$$00000012 0x00000226 Section 2 libshutdown2.o(.ARM.Collect$$libshutdown$$00000012) + .ARM.Collect$$rtentry$$00000000 0x00000228 Section 0 __rtentry.o(.ARM.Collect$$rtentry$$00000000) + .ARM.Collect$$rtentry$$00000002 0x00000228 Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000002) + .ARM.Collect$$rtentry$$00000004 0x00000228 Section 6 __rtentry4.o(.ARM.Collect$$rtentry$$00000004) + .ARM.Collect$$rtentry$$00000009 0x0000022e Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000009) + .ARM.Collect$$rtentry$$0000000A 0x0000022e Section 4 __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) + .ARM.Collect$$rtentry$$0000000C 0x00000232 Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) + .ARM.Collect$$rtentry$$0000000D 0x00000232 Section 8 __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) + .ARM.Collect$$rtexit$$00000000 0x0000023a Section 2 rtexit.o(.ARM.Collect$$rtexit$$00000000) + .ARM.Collect$$rtexit$$00000002 0x0000023c Section 0 rtexit2.o(.ARM.Collect$$rtexit$$00000002) + .ARM.Collect$$rtexit$$00000003 0x0000023c Section 4 rtexit2.o(.ARM.Collect$$rtexit$$00000003) + .ARM.Collect$$rtexit$$00000004 0x00000240 Section 6 rtexit2.o(.ARM.Collect$$rtexit$$00000004) + .text 0x00000248 Section 64 startup_k1921vk035.o(.text) + $v0 0x00000248 Number 0 startup_k1921vk035.o(.text) + .text 0x00000288 Section 2 use_no_semi.o(.text) + .text 0x0000028c Section 0 noretval__2printf.o(.text) + .text 0x000002a4 Section 0 _printf_pad.o(.text) + .text 0x000002f2 Section 0 _printf_str.o(.text) + .text 0x00000344 Section 0 _printf_dec.o(.text) + .text 0x000003bc Section 0 __printf_wp.o(.text) + .text 0x000004ca Section 0 heapauxi.o(.text) + .text 0x000004d0 Section 0 _printf_intcommon.o(.text) + .text 0x00000582 Section 0 _printf_char.o(.text) + .text 0x000005b0 Section 0 _printf_char_file.o(.text) + .text 0x000005d4 Section 0 _printf_char_common.o(.text) + _printf_input_char 0x000005d5 Thumb Code 10 _printf_char_common.o(.text) + .text 0x00000604 Section 74 sys_stackheap_outer.o(.text) + .text 0x0000064e Section 0 exit.o(.text) + .text 0x00000660 Section 8 libspace.o(.text) + i.BusFault_Handler 0x00000668 Section 0 vk035_it.o(i.BusFault_Handler) + i.ClkInit 0x0000066c Section 0 system_k1921vk035.o(i.ClkInit) + i.DebugMon_Handler 0x000006e0 Section 0 vk035_it.o(i.DebugMon_Handler) + i.Error_Handler 0x000006e2 Section 0 main.o(i.Error_Handler) + i.FPUInit 0x000006e8 Section 0 system_k1921vk035.o(i.FPUInit) + i.GPIO_AltFuncCmd 0x00000700 Section 0 plib035_gpio.o(i.GPIO_AltFuncCmd) + GPIO_AltFuncCmd 0x00000701 Thumb Code 74 plib035_gpio.o(i.GPIO_AltFuncCmd) + i.GPIO_DeInit 0x00000758 Section 0 plib035_gpio.o(i.GPIO_DeInit) + i.GPIO_DigitalCmd 0x000007bc Section 0 plib035_gpio.o(i.GPIO_DigitalCmd) + GPIO_DigitalCmd 0x000007bd Thumb Code 74 plib035_gpio.o(i.GPIO_DigitalCmd) + i.GPIO_DriveModeConfig 0x00000838 Section 0 plib035_gpio.o(i.GPIO_DriveModeConfig) + i.GPIO_InModeConfig 0x000008b4 Section 0 plib035_gpio.o(i.GPIO_InModeConfig) + i.GPIO_Init 0x0000092c Section 0 plib035_gpio.o(i.GPIO_Init) + i.GPIO_ModeConfig 0x0000097c Section 0 plib035_gpio.o(i.GPIO_ModeConfig) + GPIO_ModeConfig 0x0000097d Thumb Code 44 plib035_gpio.o(i.GPIO_ModeConfig) + i.GPIO_OutCmd 0x000009a8 Section 0 plib035_gpio.o(i.GPIO_OutCmd) + GPIO_OutCmd 0x000009a9 Thumb Code 74 plib035_gpio.o(i.GPIO_OutCmd) + i.GPIO_OutModeConfig 0x00000a00 Section 0 plib035_gpio.o(i.GPIO_OutModeConfig) + i.GPIO_PullModeConfig 0x00000a78 Section 0 plib035_gpio.o(i.GPIO_PullModeConfig) + i.HardFault_Handler 0x00000af0 Section 0 vk035_it.o(i.HardFault_Handler) + i.MFLASH_LatencyConfig 0x00000af4 Section 0 plib035_rcu.o(i.MFLASH_LatencyConfig) + MFLASH_LatencyConfig 0x00000af5 Thumb Code 28 plib035_rcu.o(i.MFLASH_LatencyConfig) + i.MemManage_Handler 0x00000b3c Section 0 vk035_it.o(i.MemManage_Handler) + i.NMI_Handler 0x00000b3e Section 0 vk035_it.o(i.NMI_Handler) + i.PendSV_Handler 0x00000b40 Section 0 vk035_it.o(i.PendSV_Handler) + i.RCU_AHBRstCmd 0x00000b44 Section 0 plib035_gpio.o(i.RCU_AHBRstCmd) + RCU_AHBRstCmd 0x00000b45 Thumb Code 64 plib035_gpio.o(i.RCU_AHBRstCmd) + i.RCU_ClkOutConfig 0x00000bb0 Section 0 rcu.o(i.RCU_ClkOutConfig) + RCU_ClkOutConfig 0x00000bb1 Thumb Code 86 rcu.o(i.RCU_ClkOutConfig) + i.RCU_PLL_AutoConfig 0x00000c38 Section 0 plib035_rcu.o(i.RCU_PLL_AutoConfig) + i.RCU_PLL_Init 0x00000d98 Section 0 plib035_rcu.o(i.RCU_PLL_Init) + i.RCU_PLL_OutCmd 0x00000e98 Section 0 plib035_rcu.o(i.RCU_PLL_OutCmd) + RCU_PLL_OutCmd 0x00000e99 Thumb Code 34 plib035_rcu.o(i.RCU_PLL_OutCmd) + i.RCU_PLL_StructInit 0x00000ee8 Section 0 plib035_rcu.o(i.RCU_PLL_StructInit) + i.RCU_SysClkChangeCmd 0x00000ef8 Section 0 plib035_rcu.o(i.RCU_SysClkChangeCmd) + i.SVC_Handler 0x00000fb0 Section 0 vk035_it.o(i.SVC_Handler) + i.SysTick_Handler 0x00000fb4 Section 0 vk035_it.o(i.SysTick_Handler) + i.SystemCoreClockUpdate 0x00000fc4 Section 0 system_k1921vk035.o(i.SystemCoreClockUpdate) + i.SystemInit 0x00001034 Section 0 system_k1921vk035.o(i.SystemInit) + i.UsageFault_Handler 0x00001042 Section 0 vk035_it.o(i.UsageFault_Handler) + i._is_digit 0x00001044 Section 0 __printf_wp.o(i._is_digit) + i._sys_exit 0x00001052 Section 0 retarget.o(i._sys_exit) + i.assert_failed 0x00001054 Section 0 main.o(i.assert_failed) + i.ferror 0x00001084 Section 0 retarget.o(i.ferror) + i.fputc 0x0000108a Section 0 retarget.o(i.fputc) + i.gpio_init 0x00001090 Section 0 gpio.o(i.gpio_init) + i.main 0x00001104 Section 0 main.o(i.main) + i.periph_init 0x0000110c Section 0 main.o(i.periph_init) + i.retarget_init 0x0000117c Section 0 retarget_conf.o(i.retarget_init) + i.retarget_put_char 0x0000123c Section 0 retarget_conf.o(i.retarget_put_char) + i.sysclk_init 0x00001250 Section 0 rcu.o(i.sysclk_init) + x$fpl$ddiv 0x000012b8 Section 688 ddiv.o(x$fpl$ddiv) + $v0 0x000012b8 Number 0 ddiv.o(x$fpl$ddiv) + ddiv_entry 0x000012bf Thumb Code 0 ddiv.o(x$fpl$ddiv) + x$fpl$dfix 0x00001568 Section 94 dfix.o(x$fpl$dfix) + $v0 0x00001568 Number 0 dfix.o(x$fpl$dfix) + x$fpl$dfltu 0x000015c6 Section 38 dflt_clz.o(x$fpl$dfltu) + $v0 0x000015c6 Number 0 dflt_clz.o(x$fpl$dfltu) + x$fpl$dnaninf 0x000015ec Section 156 dnaninf.o(x$fpl$dnaninf) + $v0 0x000015ec Number 0 dnaninf.o(x$fpl$dnaninf) + x$fpl$dretinf 0x00001688 Section 12 dretinf.o(x$fpl$dretinf) + $v0 0x00001688 Number 0 dretinf.o(x$fpl$dretinf) + x$fpl$fpinit 0x00001694 Section 10 fpinit.o(x$fpl$fpinit) + $v0 0x00001694 Number 0 fpinit.o(x$fpl$fpinit) + x$fpl$usenofp 0x0000169e Section 0 usenofp.o(x$fpl$usenofp) + .data 0x20000000 Section 4 system_k1921vk035.o(.data) + .data 0x20000004 Section 4 system_k1921vk035.o(.data) + .data 0x20000008 Section 384 gpio.o(.data) + gpioa_config 0x20000008 Data 192 gpio.o(.data) + gpiob_config 0x200000c8 Data 192 gpio.o(.data) + .data 0x20000188 Section 1 rcu.o(.data) + OS_Type 0x20000188 Data 1 rcu.o(.data) + .data 0x2000018c Section 4 retarget.o(.data) + .bss 0x20000190 Section 96 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Code 0 startup_k1921vk035.o(.text) + CAN13_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + CAN14_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + CAN15_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + CAN1_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + CAN2_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + CAN3_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + CAN4_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + CAN5_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + CAN6_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + CAN7_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + CAN8_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + CAN9_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH0_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH10_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH11_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH12_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH13_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH14_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH15_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH1_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH2_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH3_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH4_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH5_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH6_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH7_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH8_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + DMA_CH9_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + ECAP0_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + ECAP1_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + ECAP2_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + FPU_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + GPIOA_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + GPIOB_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + I2C_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + MFLASH_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + PWM0_HD_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + PWM0_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + PWM0_TZ_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + PWM1_HD_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + PWM1_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + PWM1_TZ_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + PWM2_HD_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + PWM2_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + PWM2_TZ_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + QEP_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + RCU_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + SPI_RO_RT_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + SPI_RX_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + SPI_TX_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + TMR0_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + TMR1_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + TMR2_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + TMR3_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + UART0_E_RT_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + UART0_RX_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + UART0_TD_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + UART0_TX_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + UART1_E_RT_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + UART1_RX_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + UART1_TD_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + UART1_TX_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + WDT_IRQHandler 0x00000263 Thumb Code 0 startup_k1921vk035.o(.text) + __user_initial_stackheap 0x00000265 Thumb Code 0 startup_k1921vk035.o(.text) + __I$use$semihosting 0x00000289 Thumb Code 0 use_no_semi.o(.text) + __use_no_semihosting_swi 0x00000289 Thumb Code 2 use_no_semi.o(.text) + __2printf 0x0000028d Thumb Code 20 noretval__2printf.o(.text) + _printf_pre_padding 0x000002a5 Thumb Code 44 _printf_pad.o(.text) + _printf_post_padding 0x000002d1 Thumb Code 34 _printf_pad.o(.text) + _printf_str 0x000002f3 Thumb Code 82 _printf_str.o(.text) + _printf_int_dec 0x00000345 Thumb Code 104 _printf_dec.o(.text) + __printf 0x000003bd Thumb Code 270 __printf_wp.o(.text) + __use_two_region_memory 0x000004cb Thumb Code 2 heapauxi.o(.text) + __rt_heap_escrow$2region 0x000004cd Thumb Code 2 heapauxi.o(.text) + __rt_heap_expand$2region 0x000004cf Thumb Code 2 heapauxi.o(.text) + _printf_int_common 0x000004d1 Thumb Code 178 _printf_intcommon.o(.text) + _printf_cs_common 0x00000583 Thumb Code 20 _printf_char.o(.text) + _printf_char 0x00000597 Thumb Code 16 _printf_char.o(.text) + _printf_string 0x000005a7 Thumb Code 8 _printf_char.o(.text) + _printf_char_file 0x000005b1 Thumb Code 32 _printf_char_file.o(.text) + _printf_char_common 0x000005df Thumb Code 32 _printf_char_common.o(.text) + __user_setup_stackheap 0x00000605 Thumb Code 74 sys_stackheap_outer.o(.text) + exit 0x0000064f Thumb Code 18 exit.o(.text) + __user_libspace 0x00000661 Thumb Code 8 libspace.o(.text) + __user_perproc_libspace 0x00000661 Thumb Code 0 libspace.o(.text) + __user_perthread_libspace 0x00000661 Thumb Code 0 libspace.o(.text) + BusFault_Handler 0x00000669 Thumb Code 2 vk035_it.o(i.BusFault_Handler) + ClkInit 0x0000066d Thumb Code 106 system_k1921vk035.o(i.ClkInit) + DebugMon_Handler 0x000006e1 Thumb Code 2 vk035_it.o(i.DebugMon_Handler) + Error_Handler 0x000006e3 Thumb Code 4 main.o(i.Error_Handler) + FPUInit 0x000006e9 Thumb Code 18 system_k1921vk035.o(i.FPUInit) + GPIO_DeInit 0x00000759 Thumb Code 54 plib035_gpio.o(i.GPIO_DeInit) + GPIO_DriveModeConfig 0x00000839 Thumb Code 80 plib035_gpio.o(i.GPIO_DriveModeConfig) + GPIO_InModeConfig 0x000008b5 Thumb Code 76 plib035_gpio.o(i.GPIO_InModeConfig) + GPIO_Init 0x0000092d Thumb Code 80 plib035_gpio.o(i.GPIO_Init) + GPIO_OutModeConfig 0x00000a01 Thumb Code 76 plib035_gpio.o(i.GPIO_OutModeConfig) + GPIO_PullModeConfig 0x00000a79 Thumb Code 76 plib035_gpio.o(i.GPIO_PullModeConfig) + HardFault_Handler 0x00000af1 Thumb Code 2 vk035_it.o(i.HardFault_Handler) + MemManage_Handler 0x00000b3d Thumb Code 2 vk035_it.o(i.MemManage_Handler) + NMI_Handler 0x00000b3f Thumb Code 2 vk035_it.o(i.NMI_Handler) + PendSV_Handler 0x00000b41 Thumb Code 2 vk035_it.o(i.PendSV_Handler) + RCU_PLL_AutoConfig 0x00000c39 Thumb Code 304 plib035_rcu.o(i.RCU_PLL_AutoConfig) + RCU_PLL_Init 0x00000d99 Thumb Code 212 plib035_rcu.o(i.RCU_PLL_Init) + RCU_PLL_StructInit 0x00000ee9 Thumb Code 16 plib035_rcu.o(i.RCU_PLL_StructInit) + RCU_SysClkChangeCmd 0x00000ef9 Thumb Code 104 plib035_rcu.o(i.RCU_SysClkChangeCmd) + SVC_Handler 0x00000fb1 Thumb Code 2 vk035_it.o(i.SVC_Handler) + SysTick_Handler 0x00000fb5 Thumb Code 10 vk035_it.o(i.SysTick_Handler) + SystemCoreClockUpdate 0x00000fc5 Thumb Code 96 system_k1921vk035.o(i.SystemCoreClockUpdate) + SystemInit 0x00001035 Thumb Code 14 system_k1921vk035.o(i.SystemInit) + UsageFault_Handler 0x00001043 Thumb Code 2 vk035_it.o(i.UsageFault_Handler) + _is_digit 0x00001045 Thumb Code 14 __printf_wp.o(i._is_digit) + _sys_exit 0x00001053 Thumb Code 2 retarget.o(i._sys_exit) + assert_failed 0x00001055 Thumb Code 12 main.o(i.assert_failed) + ferror 0x00001085 Thumb Code 6 retarget.o(i.ferror) + fputc 0x0000108b Thumb Code 4 retarget.o(i.fputc) + gpio_init 0x00001091 Thumb Code 100 gpio.o(i.gpio_init) + main 0x00001105 Thumb Code 6 main.o(i.main) + periph_init 0x0000110d Thumb Code 54 main.o(i.periph_init) + retarget_init 0x0000117d Thumb Code 166 retarget_conf.o(i.retarget_init) + retarget_put_char 0x0000123d Thumb Code 14 retarget_conf.o(i.retarget_put_char) + sysclk_init 0x00001251 Thumb Code 80 rcu.o(i.sysclk_init) + __aeabi_ddiv 0x000012b9 Thumb Code 0 ddiv.o(x$fpl$ddiv) + _ddiv 0x000012b9 Thumb Code 552 ddiv.o(x$fpl$ddiv) + __aeabi_d2iz 0x00001569 Thumb Code 0 dfix.o(x$fpl$dfix) + _dfix 0x00001569 Thumb Code 94 dfix.o(x$fpl$dfix) + __aeabi_ui2d 0x000015c7 Thumb Code 0 dflt_clz.o(x$fpl$dfltu) + _dfltu 0x000015c7 Thumb Code 38 dflt_clz.o(x$fpl$dfltu) + __fpl_dnaninf 0x000015ed Thumb Code 156 dnaninf.o(x$fpl$dnaninf) + __fpl_dretinf 0x00001689 Thumb Code 12 dretinf.o(x$fpl$dretinf) + _fp_init 0x00001695 Thumb Code 10 fpinit.o(x$fpl$fpinit) + __fplib_config_fpu_vfp 0x0000169d Thumb Code 0 fpinit.o(x$fpl$fpinit) + __fplib_config_pureend_doubles 0x0000169d Thumb Code 0 fpinit.o(x$fpl$fpinit) + __I$use$fp 0x0000169e Number 0 usenofp.o(x$fpl$usenofp) + Region$$Table$$Base 0x000016a0 Number 0 anon$$obj.o(Region$$Table) + Region$$Table$$Limit 0x000016c0 Number 0 anon$$obj.o(Region$$Table) + SystemCoreClock 0x20000000 Data 4 system_k1921vk035.o(.data) + uwTick 0x20000004 Data 4 system_k1921vk035.o(.data) + __stdout 0x2000018c Data 4 retarget.o(.data) + __libspace_start 0x20000190 Data 96 libspace.o(.bss) + __temporary_stack_top$libspace 0x200001f0 Data 0 libspace.o(.bss) + + + +============================================================================== + +Memory Map of the image + + Image Entry point : 0x00000249 + + Load Region LR_1 (Base: 0x00000000, Size: 0x00001850, Max: 0xffffffff, ABSOLUTE, COMPRESSED[0x000016e4]) + + Execution Region ER_RO (Exec base: 0x00000000, Load base: 0x00000000, Size: 0x000016c0, Max: 0xffffffff, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x00000000 0x00000000 0x00000158 Data RO 77 RESET startup_k1921vk035.o + 0x00000158 0x00000158 0x00000008 Code RO 1417 * !!!main c_w.l(__main.o) + 0x00000160 0x00000160 0x00000034 Code RO 1602 !!!scatter c_w.l(__scatter.o) + 0x00000194 0x00000194 0x0000005a Code RO 1600 !!dczerorl2 c_w.l(__dczerorl2.o) + 0x000001ee 0x000001ee 0x00000002 PAD + 0x000001f0 0x000001f0 0x0000001c Code RO 1604 !!handler_zi c_w.l(__scatter_zi.o) + 0x0000020c 0x0000020c 0x00000000 Code RO 1414 .ARM.Collect$$_printf_percent$$00000000 c_w.l(_printf_percent.o) + 0x0000020c 0x0000020c 0x00000006 Code RO 1413 .ARM.Collect$$_printf_percent$$00000009 c_w.l(_printf_d.o) + 0x00000212 0x00000212 0x00000006 Code RO 1412 .ARM.Collect$$_printf_percent$$00000014 c_w.l(_printf_s.o) + 0x00000218 0x00000218 0x00000004 Code RO 1440 .ARM.Collect$$_printf_percent$$00000017 c_w.l(_printf_percent_end.o) + 0x0000021c 0x0000021c 0x00000002 Code RO 1474 .ARM.Collect$$libinit$$00000000 c_w.l(libinit.o) + 0x0000021e 0x0000021e 0x00000004 Code RO 1480 .ARM.Collect$$libinit$$00000001 c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 1483 .ARM.Collect$$libinit$$00000004 c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 1486 .ARM.Collect$$libinit$$0000000A c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 1488 .ARM.Collect$$libinit$$0000000C c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 1490 .ARM.Collect$$libinit$$0000000E c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 1493 .ARM.Collect$$libinit$$00000011 c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 1495 .ARM.Collect$$libinit$$00000013 c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 1497 .ARM.Collect$$libinit$$00000015 c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 1499 .ARM.Collect$$libinit$$00000017 c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 1501 .ARM.Collect$$libinit$$00000019 c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 1503 .ARM.Collect$$libinit$$0000001B c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 1505 .ARM.Collect$$libinit$$0000001D c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 1507 .ARM.Collect$$libinit$$0000001F c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 1509 .ARM.Collect$$libinit$$00000021 c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 1511 .ARM.Collect$$libinit$$00000023 c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 1513 .ARM.Collect$$libinit$$00000025 c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 1517 .ARM.Collect$$libinit$$0000002C c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 1519 .ARM.Collect$$libinit$$0000002E c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 1521 .ARM.Collect$$libinit$$00000030 c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000000 Code RO 1523 .ARM.Collect$$libinit$$00000032 c_w.l(libinit2.o) + 0x00000222 0x00000222 0x00000002 Code RO 1524 .ARM.Collect$$libinit$$00000033 c_w.l(libinit2.o) + 0x00000224 0x00000224 0x00000002 Code RO 1542 .ARM.Collect$$libshutdown$$00000000 c_w.l(libshutdown.o) + 0x00000226 0x00000226 0x00000000 Code RO 1552 .ARM.Collect$$libshutdown$$00000002 c_w.l(libshutdown2.o) + 0x00000226 0x00000226 0x00000000 Code RO 1554 .ARM.Collect$$libshutdown$$00000004 c_w.l(libshutdown2.o) + 0x00000226 0x00000226 0x00000000 Code RO 1556 .ARM.Collect$$libshutdown$$00000006 c_w.l(libshutdown2.o) + 0x00000226 0x00000226 0x00000000 Code RO 1559 .ARM.Collect$$libshutdown$$00000009 c_w.l(libshutdown2.o) + 0x00000226 0x00000226 0x00000000 Code RO 1562 .ARM.Collect$$libshutdown$$0000000C c_w.l(libshutdown2.o) + 0x00000226 0x00000226 0x00000000 Code RO 1564 .ARM.Collect$$libshutdown$$0000000E c_w.l(libshutdown2.o) + 0x00000226 0x00000226 0x00000000 Code RO 1567 .ARM.Collect$$libshutdown$$00000011 c_w.l(libshutdown2.o) + 0x00000226 0x00000226 0x00000002 Code RO 1568 .ARM.Collect$$libshutdown$$00000012 c_w.l(libshutdown2.o) + 0x00000228 0x00000228 0x00000000 Code RO 1433 .ARM.Collect$$rtentry$$00000000 c_w.l(__rtentry.o) + 0x00000228 0x00000228 0x00000000 Code RO 1447 .ARM.Collect$$rtentry$$00000002 c_w.l(__rtentry2.o) + 0x00000228 0x00000228 0x00000006 Code RO 1459 .ARM.Collect$$rtentry$$00000004 c_w.l(__rtentry4.o) + 0x0000022e 0x0000022e 0x00000000 Code RO 1449 .ARM.Collect$$rtentry$$00000009 c_w.l(__rtentry2.o) + 0x0000022e 0x0000022e 0x00000004 Code RO 1450 .ARM.Collect$$rtentry$$0000000A c_w.l(__rtentry2.o) + 0x00000232 0x00000232 0x00000000 Code RO 1452 .ARM.Collect$$rtentry$$0000000C c_w.l(__rtentry2.o) + 0x00000232 0x00000232 0x00000008 Code RO 1453 .ARM.Collect$$rtentry$$0000000D c_w.l(__rtentry2.o) + 0x0000023a 0x0000023a 0x00000002 Code RO 1478 .ARM.Collect$$rtexit$$00000000 c_w.l(rtexit.o) + 0x0000023c 0x0000023c 0x00000000 Code RO 1526 .ARM.Collect$$rtexit$$00000002 c_w.l(rtexit2.o) + 0x0000023c 0x0000023c 0x00000004 Code RO 1527 .ARM.Collect$$rtexit$$00000003 c_w.l(rtexit2.o) + 0x00000240 0x00000240 0x00000006 Code RO 1528 .ARM.Collect$$rtexit$$00000004 c_w.l(rtexit2.o) + 0x00000246 0x00000246 0x00000002 PAD + 0x00000248 0x00000248 0x00000040 Code RO 78 * .text startup_k1921vk035.o + 0x00000288 0x00000288 0x00000002 Code RO 1378 .text c_w.l(use_no_semi.o) + 0x0000028a 0x0000028a 0x00000002 PAD + 0x0000028c 0x0000028c 0x00000018 Code RO 1382 .text c_w.l(noretval__2printf.o) + 0x000002a4 0x000002a4 0x0000004e Code RO 1386 .text c_w.l(_printf_pad.o) + 0x000002f2 0x000002f2 0x00000052 Code RO 1388 .text c_w.l(_printf_str.o) + 0x00000344 0x00000344 0x00000078 Code RO 1390 .text c_w.l(_printf_dec.o) + 0x000003bc 0x000003bc 0x0000010e Code RO 1400 .text c_w.l(__printf_wp.o) + 0x000004ca 0x000004ca 0x00000006 Code RO 1415 .text c_w.l(heapauxi.o) + 0x000004d0 0x000004d0 0x000000b2 Code RO 1434 .text c_w.l(_printf_intcommon.o) + 0x00000582 0x00000582 0x0000002c Code RO 1436 .text c_w.l(_printf_char.o) + 0x000005ae 0x000005ae 0x00000002 PAD + 0x000005b0 0x000005b0 0x00000024 Code RO 1438 .text c_w.l(_printf_char_file.o) + 0x000005d4 0x000005d4 0x00000030 Code RO 1461 .text c_w.l(_printf_char_common.o) + 0x00000604 0x00000604 0x0000004a Code RO 1463 .text c_w.l(sys_stackheap_outer.o) + 0x0000064e 0x0000064e 0x00000012 Code RO 1467 .text c_w.l(exit.o) + 0x00000660 0x00000660 0x00000008 Code RO 1475 .text c_w.l(libspace.o) + 0x00000668 0x00000668 0x00000002 Code RO 274 i.BusFault_Handler vk035_it.o + 0x0000066a 0x0000066a 0x00000002 PAD + 0x0000066c 0x0000066c 0x00000074 Code RO 4 i.ClkInit system_k1921vk035.o + 0x000006e0 0x000006e0 0x00000002 Code RO 275 i.DebugMon_Handler vk035_it.o + 0x000006e2 0x000006e2 0x00000004 Code RO 85 i.Error_Handler main.o + 0x000006e6 0x000006e6 0x00000002 PAD + 0x000006e8 0x000006e8 0x00000018 Code RO 5 i.FPUInit system_k1921vk035.o + 0x00000700 0x00000700 0x00000058 Code RO 571 i.GPIO_AltFuncCmd plib035_gpio.o + 0x00000758 0x00000758 0x00000064 Code RO 572 i.GPIO_DeInit plib035_gpio.o + 0x000007bc 0x000007bc 0x0000007c Code RO 573 i.GPIO_DigitalCmd plib035_gpio.o + 0x00000838 0x00000838 0x0000007c Code RO 574 i.GPIO_DriveModeConfig plib035_gpio.o + 0x000008b4 0x000008b4 0x00000078 Code RO 575 i.GPIO_InModeConfig plib035_gpio.o + 0x0000092c 0x0000092c 0x00000050 Code RO 576 i.GPIO_Init plib035_gpio.o + 0x0000097c 0x0000097c 0x0000002c Code RO 577 i.GPIO_ModeConfig plib035_gpio.o + 0x000009a8 0x000009a8 0x00000058 Code RO 578 i.GPIO_OutCmd plib035_gpio.o + 0x00000a00 0x00000a00 0x00000078 Code RO 579 i.GPIO_OutModeConfig plib035_gpio.o + 0x00000a78 0x00000a78 0x00000078 Code RO 580 i.GPIO_PullModeConfig plib035_gpio.o + 0x00000af0 0x00000af0 0x00000002 Code RO 276 i.HardFault_Handler vk035_it.o + 0x00000af2 0x00000af2 0x00000002 PAD + 0x00000af4 0x00000af4 0x00000048 Code RO 977 i.MFLASH_LatencyConfig plib035_rcu.o + 0x00000b3c 0x00000b3c 0x00000002 Code RO 277 i.MemManage_Handler vk035_it.o + 0x00000b3e 0x00000b3e 0x00000002 Code RO 278 i.NMI_Handler vk035_it.o + 0x00000b40 0x00000b40 0x00000002 Code RO 279 i.PendSV_Handler vk035_it.o + 0x00000b42 0x00000b42 0x00000002 PAD + 0x00000b44 0x00000b44 0x0000006c Code RO 582 i.RCU_AHBRstCmd plib035_gpio.o + 0x00000bb0 0x00000bb0 0x00000088 Code RO 236 i.RCU_ClkOutConfig rcu.o + 0x00000c38 0x00000c38 0x00000160 Code RO 989 i.RCU_PLL_AutoConfig plib035_rcu.o + 0x00000d98 0x00000d98 0x00000100 Code RO 991 i.RCU_PLL_Init plib035_rcu.o + 0x00000e98 0x00000e98 0x00000050 Code RO 992 i.RCU_PLL_OutCmd plib035_rcu.o + 0x00000ee8 0x00000ee8 0x00000010 Code RO 993 i.RCU_PLL_StructInit plib035_rcu.o + 0x00000ef8 0x00000ef8 0x000000b8 Code RO 994 i.RCU_SysClkChangeCmd plib035_rcu.o + 0x00000fb0 0x00000fb0 0x00000002 Code RO 280 i.SVC_Handler vk035_it.o + 0x00000fb2 0x00000fb2 0x00000002 PAD + 0x00000fb4 0x00000fb4 0x00000010 Code RO 281 i.SysTick_Handler vk035_it.o + 0x00000fc4 0x00000fc4 0x00000070 Code RO 6 i.SystemCoreClockUpdate system_k1921vk035.o + 0x00001034 0x00001034 0x0000000e Code RO 7 i.SystemInit system_k1921vk035.o + 0x00001042 0x00001042 0x00000002 Code RO 282 i.UsageFault_Handler vk035_it.o + 0x00001044 0x00001044 0x0000000e Code RO 1402 i._is_digit c_w.l(__printf_wp.o) + 0x00001052 0x00001052 0x00000002 Code RO 1278 i._sys_exit retarget.o + 0x00001054 0x00001054 0x00000030 Code RO 86 i.assert_failed main.o + 0x00001084 0x00001084 0x00000006 Code RO 1280 i.ferror retarget.o + 0x0000108a 0x0000108a 0x00000004 Code RO 1282 i.fputc retarget.o + 0x0000108e 0x0000108e 0x00000002 PAD + 0x00001090 0x00001090 0x00000074 Code RO 204 i.gpio_init gpio.o + 0x00001104 0x00001104 0x00000006 Code RO 87 i.main main.o + 0x0000110a 0x0000110a 0x00000002 PAD + 0x0000110c 0x0000110c 0x00000070 Code RO 88 i.periph_init main.o + 0x0000117c 0x0000117c 0x000000c0 Code RO 1344 i.retarget_init retarget_conf.o + 0x0000123c 0x0000123c 0x00000014 Code RO 1345 i.retarget_put_char retarget_conf.o + 0x00001250 0x00001250 0x00000068 Code RO 237 i.sysclk_init rcu.o + 0x000012b8 0x000012b8 0x000002b0 Code RO 1420 x$fpl$ddiv fz_wm.l(ddiv.o) + 0x00001568 0x00001568 0x0000005e Code RO 1423 x$fpl$dfix fz_wm.l(dfix.o) + 0x000015c6 0x000015c6 0x00000026 Code RO 1427 x$fpl$dfltu fz_wm.l(dflt_clz.o) + 0x000015ec 0x000015ec 0x0000009c Code RO 1441 x$fpl$dnaninf fz_wm.l(dnaninf.o) + 0x00001688 0x00001688 0x0000000c Code RO 1443 x$fpl$dretinf fz_wm.l(dretinf.o) + 0x00001694 0x00001694 0x0000000a Code RO 1534 x$fpl$fpinit fz_wm.l(fpinit.o) + 0x0000169e 0x0000169e 0x00000000 Code RO 1445 x$fpl$usenofp fz_wm.l(usenofp.o) + 0x0000169e 0x0000169e 0x00000002 PAD + 0x000016a0 0x000016a0 0x00000020 Data RO 1598 Region$$Table anon$$obj.o + + + Execution Region ER_RW (Exec base: 0x20000000, Load base: 0x000016c0, Size: 0x00000190, Max: 0xffffffff, ABSOLUTE, COMPRESSED[0x00000024]) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x20000000 COMPRESSED 0x00000004 Data RW 8 .data system_k1921vk035.o + 0x20000004 COMPRESSED 0x00000004 Data RW 9 .data system_k1921vk035.o + 0x20000008 COMPRESSED 0x00000180 Data RW 205 .data gpio.o + 0x20000188 COMPRESSED 0x00000001 Data RW 238 .data rcu.o + 0x20000189 COMPRESSED 0x00000003 PAD + 0x2000018c COMPRESSED 0x00000004 Data RW 1283 .data retarget.o + + + Execution Region ER_ZI (Exec base: 0x20000190, Load base: 0x000016e4, Size: 0x00000660, Max: 0xffffffff, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x20000190 - 0x00000060 Zero RW 1476 .bss c_w.l(libspace.o) + 0x200001f0 - 0x00000200 Zero RW 76 HEAP startup_k1921vk035.o + 0x200003f0 - 0x00000400 Zero RW 75 STACK startup_k1921vk035.o + + +============================================================================== + +Image component sizes + + + Code (inc. data) RO Data RW Data ZI Data Debug Object Name + + 116 16 0 384 0 10416 gpio.o + 170 94 0 0 0 8505 main.o + 1116 344 0 0 0 12904 plib035_gpio.o + 960 262 0 0 0 15871 plib035_rcu.o + 240 74 0 1 0 40297 rcu.o + 12 0 0 4 0 3303 retarget.o + 212 32 0 0 0 1204 retarget_conf.o + 64 26 344 0 1536 892 startup_k1921vk035.o + 266 32 0 8 0 197926 system_k1921vk035.o + 32 6 0 0 0 3974 vk035_it.o + + ---------------------------------------------------------------------- + 3202 886 376 400 1536 295292 Object Totals + 0 0 32 0 0 0 (incl. Generated) + 14 0 0 3 0 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name + + 90 0 0 0 0 0 __dczerorl2.o + 8 0 0 0 0 68 __main.o + 284 0 0 0 0 156 __printf_wp.o + 0 0 0 0 0 0 __rtentry.o + 12 0 0 0 0 0 __rtentry2.o + 6 0 0 0 0 0 __rtentry4.o + 52 8 0 0 0 0 __scatter.o + 28 0 0 0 0 0 __scatter_zi.o + 44 0 0 0 0 108 _printf_char.o + 48 6 0 0 0 96 _printf_char_common.o + 36 4 0 0 0 80 _printf_char_file.o + 6 0 0 0 0 0 _printf_d.o + 120 16 0 0 0 92 _printf_dec.o + 178 0 0 0 0 88 _printf_intcommon.o + 78 0 0 0 0 108 _printf_pad.o + 0 0 0 0 0 0 _printf_percent.o + 4 0 0 0 0 0 _printf_percent_end.o + 6 0 0 0 0 0 _printf_s.o + 82 0 0 0 0 80 _printf_str.o + 18 0 0 0 0 80 exit.o + 6 0 0 0 0 152 heapauxi.o + 2 0 0 0 0 0 libinit.o + 6 0 0 0 0 0 libinit2.o + 2 0 0 0 0 0 libshutdown.o + 2 0 0 0 0 0 libshutdown2.o + 8 4 0 0 96 68 libspace.o + 24 4 0 0 0 84 noretval__2printf.o + 2 0 0 0 0 0 rtexit.o + 10 0 0 0 0 0 rtexit2.o + 74 0 0 0 0 80 sys_stackheap_outer.o + 2 0 0 0 0 68 use_no_semi.o + 688 140 0 0 0 256 ddiv.o + 94 4 0 0 0 140 dfix.o + 38 0 0 0 0 116 dflt_clz.o + 156 4 0 0 0 140 dnaninf.o + 12 0 0 0 0 116 dretinf.o + 10 0 0 0 0 116 fpinit.o + 0 0 0 0 0 0 usenofp.o + + ---------------------------------------------------------------------- + 2246 190 0 0 96 2292 Library Totals + 10 0 0 0 0 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Name + + 1238 42 0 0 96 1408 c_w.l + 998 148 0 0 0 884 fz_wm.l + + ---------------------------------------------------------------------- + 2246 190 0 0 96 2292 Library Totals + + ---------------------------------------------------------------------- + +============================================================================== + + + Code (inc. data) RO Data RW Data ZI Data Debug + + 5448 1076 376 400 1632 292960 Grand Totals + 5448 1076 376 36 1632 292960 ELF Image Totals (compressed) + 5448 1076 376 36 0 0 ROM Totals + +============================================================================== + + Total RO Size (Code + RO Data) 5824 ( 5.69kB) + Total RW Size (RW Data + ZI Data) 2032 ( 1.98kB) + Total ROM Size (Code + RO Data + RW Data) 5860 ( 5.72kB) + +============================================================================== + diff --git a/Template.uvoptx b/Template.uvoptx new file mode 100644 index 0000000..33b54d6 --- /dev/null +++ b/Template.uvoptx @@ -0,0 +1,750 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp; *.cc; *.cxx + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + JL2CM3 + -U-O14 -O14 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN1 -FF0K1921VK035.FLM -FS00 -FL010000 -FP0($$Device:K1921VK035$Flash\K1921VK035.FLM) + + + 0 + DLGUARM + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0K1921VK035 -FS00 -FL010000 -FP0($$Device:K1921VK035$Flash\K1921VK035.FLM)) + + + + + + 0 + 1 + uwTick,0x0A + + + 1 + 1 + start,0x0A + + + 2 + 1 + uwTick,0x0A + + + 3 + 1 + (uwTick-start) < ms + + + 4 + 1 + ms,0x0A + + + 5 + 1 + local_time() + + + 6 + 1 + GPIOA + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Config + 1 + 0 + 0 + 0 + + 1 + 1 + 5 + 0 + 0 + 0 + .\Core\Config\mylibs_config.h + mylibs_config.h + 0 + 0 + + + 1 + 2 + 5 + 0 + 0 + 0 + .\Core\Config\mylibs_include.h + mylibs_include.h + 0 + 0 + + + 1 + 3 + 5 + 0 + 0 + 0 + .\Core\Config\SEGGER_RTT_Conf.h + SEGGER_RTT_Conf.h + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + .\Core\App\gpio.h + gpio.h + 0 + 0 + + + 1 + 5 + 5 + 0 + 0 + 0 + .\Core\App\rcu.h + rcu.h + 0 + 0 + + + + + src + 1 + 0 + 0 + 0 + + 2 + 6 + 1 + 0 + 0 + 0 + .\Core\App\main.c + main.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + .\Core\App\gpio.c + gpio.c + 0 + 0 + + + 2 + 8 + 1 + 0 + 0 + 0 + .\Core\App\rcu.c + rcu.c + 0 + 0 + + + 2 + 9 + 1 + 0 + 0 + 0 + .\Core\App\vk035_it.c + vk035_it.c + 0 + 0 + + + + + MyLibs + 0 + 0 + 0 + 0 + + 3 + 10 + 5 + 0 + 0 + 0 + .\Core\ExtendedLibs\MyLibs\Inc\bench_time.h + bench_time.h + 0 + 0 + + + 3 + 11 + 5 + 0 + 0 + 0 + .\Core\ExtendedLibs\MyLibs\Inc\bit_access.h + bit_access.h + 0 + 0 + + + 3 + 12 + 5 + 0 + 0 + 0 + .\Core\ExtendedLibs\MyLibs\Inc\gen_optimizer.h + gen_optimizer.h + 0 + 0 + + + 3 + 13 + 5 + 0 + 0 + 0 + .\Core\ExtendedLibs\MyLibs\Inc\mylibs_defs.h + mylibs_defs.h + 0 + 0 + + + 3 + 14 + 5 + 0 + 0 + 0 + .\Core\ExtendedLibs\MyLibs\Inc\trace.h + trace.h + 0 + 0 + + + 3 + 15 + 5 + 0 + 0 + 0 + .\Core\ExtendedLibs\MyLibs\Inc\trackers.h + trackers.h + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + .\Core\ExtendedLibs\RTT\SEGGER_RTT.c + SEGGER_RTT.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + .\Core\ExtendedLibs\RTT\SEGGER_RTT_printf.c + SEGGER_RTT_printf.c + 0 + 0 + + + 3 + 18 + 5 + 0 + 0 + 0 + .\Core\ExtendedLibs\MyLibs\Inc\filters.h + filters.h + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + .\Core\ExtendedLibs\MyLibs\Src\filters.c + filters.c + 0 + 0 + + + + + startup + 0 + 0 + 0 + 0 + + 4 + 20 + 1 + 0 + 0 + 0 + .\platform\Device\NIIET\K1921VK035\Source\system_K1921VK035.c + system_K1921VK035.c + 0 + 0 + + + 4 + 21 + 2 + 0 + 0 + 0 + .\platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1921VK035.s + startup_K1921VK035.s + 0 + 0 + + + + + plib035 + 0 + 0 + 0 + 0 + + 5 + 22 + 1 + 0 + 0 + 0 + .\platform\plib035\src\plib035_adc.c + plib035_adc.c + 0 + 0 + + + 5 + 23 + 1 + 0 + 0 + 0 + .\platform\plib035\src\plib035_can.c + plib035_can.c + 0 + 0 + + + 5 + 24 + 1 + 0 + 0 + 0 + .\platform\plib035\src\plib035_dma.c + plib035_dma.c + 0 + 0 + + + 5 + 25 + 1 + 0 + 0 + 0 + .\platform\plib035\src\plib035_ecap.c + plib035_ecap.c + 0 + 0 + + + 5 + 26 + 1 + 0 + 0 + 0 + .\platform\plib035\src\plib035_gpio.c + plib035_gpio.c + 0 + 0 + + + 5 + 27 + 1 + 0 + 0 + 0 + .\platform\plib035\src\plib035_i2c.c + plib035_i2c.c + 0 + 0 + + + 5 + 28 + 1 + 0 + 0 + 0 + .\platform\plib035\src\plib035_mflash.c + plib035_mflash.c + 0 + 0 + + + 5 + 29 + 1 + 0 + 0 + 0 + .\platform\plib035\src\plib035_pmu.c + plib035_pmu.c + 0 + 0 + + + 5 + 30 + 1 + 0 + 0 + 0 + .\platform\plib035\src\plib035_pwm.c + plib035_pwm.c + 0 + 0 + + + 5 + 31 + 1 + 0 + 0 + 0 + .\platform\plib035\src\plib035_qep.c + plib035_qep.c + 0 + 0 + + + 5 + 32 + 1 + 0 + 0 + 0 + .\platform\plib035\src\plib035_rcu.c + plib035_rcu.c + 0 + 0 + + + 5 + 33 + 1 + 0 + 0 + 0 + .\platform\plib035\src\plib035_spi.c + plib035_spi.c + 0 + 0 + + + 5 + 34 + 1 + 0 + 0 + 0 + .\platform\plib035\src\plib035_tmr.c + plib035_tmr.c + 0 + 0 + + + 5 + 35 + 1 + 0 + 0 + 0 + .\platform\plib035\src\plib035_uart.c + plib035_uart.c + 0 + 0 + + + 5 + 36 + 1 + 0 + 0 + 0 + .\platform\plib035\src\plib035_wdt.c + plib035_wdt.c + 0 + 0 + + + + + Retarget + 0 + 0 + 0 + 0 + + 6 + 37 + 1 + 0 + 0 + 0 + .\platform\retarget\retarget.c + retarget.c + 0 + 0 + + + 6 + 38 + 1 + 0 + 0 + 0 + .\platform\retarget\retarget_conf.c + retarget_conf.c + 0 + 0 + + + 6 + 39 + 5 + 0 + 0 + 0 + .\platform\retarget\retarget_conf.h + retarget_conf.h + 0 + 0 + + + + diff --git a/Template.uvprojx b/Template.uvprojx new file mode 100644 index 0000000..6cf06e1 --- /dev/null +++ b/Template.uvprojx @@ -0,0 +1,628 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + K1921VK035 + Generic + NIIET.K1921VK035_DFP.2.0.6 + http://www.keil.com/pack/ + IRAM(0x20000000,0x4000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC3000 -FN2 -FF0K1921VK035 -FS00 -FL010000 -FF1K1921VK035_SRV -FS10 -FL1100000 -FP0($$Device:K1921VK035$Flash\K1921VK035.FLM) -FP1($$Device:K1921VK035$Flash\K1921VK035_SRV.FLM)) + 0 + $$Device:K1921VK035$Device\Include\K1921VK035.h + + + + + + + + + + $$Device:K1921VK035$SVD\K1921VK035.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + Firmware + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 3 + 5 + 1 + 1 + 0 + 0 + 0 + + + RETARGET, RETARGET_USE_UART, SYSCLK_OSE, OSECLK_VAL=24000000, CKO_NONE, USE_FULL_ASSERT + + .\platform\CMSIS\Core\Include;.\platform\Device\NIIET\K1921VK035\Include;.\platform\plib035\inc;.\platform\retarget;.\platform\retarget\Template\K1921VK035;.\Core\App;.\Core\Config;.\Core\ExtendedLibs;.\Core\ExtendedLibs\MyLibs\Inc;.\Core\ExtendedLibs\RTT + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Config + + + mylibs_config.h + 5 + .\Core\Config\mylibs_config.h + + + mylibs_include.h + 5 + .\Core\Config\mylibs_include.h + + + SEGGER_RTT_Conf.h + 5 + .\Core\Config\SEGGER_RTT_Conf.h + + + gpio.h + 5 + .\Core\App\gpio.h + + + rcu.h + 5 + .\Core\App\rcu.h + + + + + src + + + main.c + 1 + .\Core\App\main.c + + + gpio.c + 1 + .\Core\App\gpio.c + + + rcu.c + 1 + .\Core\App\rcu.c + + + vk035_it.c + 1 + .\Core\App\vk035_it.c + + + + + MyLibs + + + bench_time.h + 5 + .\Core\ExtendedLibs\MyLibs\Inc\bench_time.h + + + bit_access.h + 5 + .\Core\ExtendedLibs\MyLibs\Inc\bit_access.h + + + gen_optimizer.h + 5 + .\Core\ExtendedLibs\MyLibs\Inc\gen_optimizer.h + + + mylibs_defs.h + 5 + .\Core\ExtendedLibs\MyLibs\Inc\mylibs_defs.h + + + trace.h + 5 + .\Core\ExtendedLibs\MyLibs\Inc\trace.h + + + trackers.h + 5 + .\Core\ExtendedLibs\MyLibs\Inc\trackers.h + + + SEGGER_RTT.c + 1 + .\Core\ExtendedLibs\RTT\SEGGER_RTT.c + + + SEGGER_RTT_printf.c + 1 + .\Core\ExtendedLibs\RTT\SEGGER_RTT_printf.c + + + filters.h + 5 + .\Core\ExtendedLibs\MyLibs\Inc\filters.h + + + filters.c + 1 + .\Core\ExtendedLibs\MyLibs\Src\filters.c + + + + + startup + + + system_K1921VK035.c + 1 + .\platform\Device\NIIET\K1921VK035\Source\system_K1921VK035.c + + + startup_K1921VK035.s + 2 + .\platform\Device\NIIET\K1921VK035\Source\ARM\startup_K1921VK035.s + + + + + plib035 + + + plib035_adc.c + 1 + .\platform\plib035\src\plib035_adc.c + + + plib035_can.c + 1 + .\platform\plib035\src\plib035_can.c + + + plib035_dma.c + 1 + .\platform\plib035\src\plib035_dma.c + + + plib035_ecap.c + 1 + .\platform\plib035\src\plib035_ecap.c + + + plib035_gpio.c + 1 + .\platform\plib035\src\plib035_gpio.c + + + plib035_i2c.c + 1 + .\platform\plib035\src\plib035_i2c.c + + + plib035_mflash.c + 1 + .\platform\plib035\src\plib035_mflash.c + + + plib035_pmu.c + 1 + .\platform\plib035\src\plib035_pmu.c + + + plib035_pwm.c + 1 + .\platform\plib035\src\plib035_pwm.c + + + plib035_qep.c + 1 + .\platform\plib035\src\plib035_qep.c + + + plib035_rcu.c + 1 + .\platform\plib035\src\plib035_rcu.c + + + plib035_spi.c + 1 + .\platform\plib035\src\plib035_spi.c + + + plib035_tmr.c + 1 + .\platform\plib035\src\plib035_tmr.c + + + plib035_uart.c + 1 + .\platform\plib035\src\plib035_uart.c + + + plib035_wdt.c + 1 + .\platform\plib035\src\plib035_wdt.c + + + + + Retarget + + + retarget.c + 1 + .\platform\retarget\retarget.c + + + retarget_conf.c + 1 + .\platform\retarget\retarget_conf.c + + + retarget_conf.h + 5 + .\platform\retarget\retarget_conf.h + + + + + + + + + + + + + + + + + UKSI + 1 + + + + + diff --git a/platform/CMSIS/Core/Include/cmsis_armcc.h b/platform/CMSIS/Core/Include/cmsis_armcc.h new file mode 100644 index 0000000..b127d2f --- /dev/null +++ b/platform/CMSIS/Core/Include/cmsis_armcc.h @@ -0,0 +1,867 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (ARM compiler V5) header file + * @version V5.0.2 + * @date 13. February 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/platform/CMSIS/Core/Include/cmsis_armclang.h b/platform/CMSIS/Core/Include/cmsis_armclang.h new file mode 100644 index 0000000..50b839d --- /dev/null +++ b/platform/CMSIS/Core/Include/cmsis_armclang.h @@ -0,0 +1,1815 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler ARMCLANG (ARM compiler V6) header file + * @version V5.0.3 + * @date 27. March 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for ARM Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return(result); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Get Process Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + + return(result); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Get Main Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Set Main Stack Pointer Limit (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/platform/CMSIS/Core/Include/cmsis_cmcpp.h b/platform/CMSIS/Core/Include/cmsis_cmcpp.h new file mode 100644 index 0000000..07a5235 --- /dev/null +++ b/platform/CMSIS/Core/Include/cmsis_cmcpp.h @@ -0,0 +1,127 @@ +/**************************************************************************//** + * @file cmsis_cmcpp.h + * @brief CMSIS compiler CMCPP_ARM header file + * @version V5.0.2 + * @date 13. February 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_CMCPP_H +#define __CMSIS_CMCPP_H + +/* ignore some GCC warnings */ +/*#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" */ + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static inline /*__attribute__((always_inline)) static inline*/ +#endif +#ifndef __NO_RETURN + #define __NO_RETURN /*__attribute__((__noreturn__))*/ +#endif +#ifndef __USED + #define __USED /*__attribute__((used))*/ +#endif +#ifndef __WEAK + #define __WEAK /*__attribute__((weak))*/ +#endif +#ifndef __PACKED + #define __PACKED __packed +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif + +//#ifndef __UNALIGNED_UINT32 /* deprecated */ +/* #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif */ +#ifndef __ALIGNED + #define __ALIGNED(x) /*__attribute__((aligned(x)))*/ +#endif +#ifndef __RESTRICT + #define __RESTRICT /*__restrict*/ +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + + +#endif /* __CMSISG_CMCPP_H */ + diff --git a/platform/CMSIS/Core/Include/cmsis_compiler.h b/platform/CMSIS/Core/Include/cmsis_compiler.h new file mode 100644 index 0000000..2613c28 --- /dev/null +++ b/platform/CMSIS/Core/Include/cmsis_compiler.h @@ -0,0 +1,264 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.2 + * @date 13. February 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * ARM Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * ARM Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * CMCPP-ARM Compiler + */ +#elif defined ( __CMCPPARM__ ) + #include "cmsis_cmcpp.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI ARM Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/platform/CMSIS/Core/Include/cmsis_gcc.h b/platform/CMSIS/Core/Include/cmsis_gcc.h new file mode 100644 index 0000000..8401734 --- /dev/null +++ b/platform/CMSIS/Core/Include/cmsis_gcc.h @@ -0,0 +1,2026 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.2 + * @date 13. February 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return(result); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Get Process Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + + return(result); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Get Main Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Set Main Stack Pointer Limit (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */ + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/platform/CMSIS/Core/Include/cmsis_iccarm.h b/platform/CMSIS/Core/Include/cmsis_iccarm.h new file mode 100644 index 0000000..b45b89b --- /dev/null +++ b/platform/CMSIS/Core/Include/cmsis_iccarm.h @@ -0,0 +1,906 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR compiler) header file + * @version V5.0.3 + * @date 29. August 2017 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT restrict +#endif + + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/platform/CMSIS/Core/Include/cmsis_version.h b/platform/CMSIS/Core/Include/cmsis_version.h new file mode 100644 index 0000000..660f612 --- /dev/null +++ b/platform/CMSIS/Core/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/platform/CMSIS/Core/Include/core_cm4.h b/platform/CMSIS/Core/Include/core_cm4.h new file mode 100644 index 0000000..dc71a8f --- /dev/null +++ b/platform/CMSIS/Core/Include/core_cm4.h @@ -0,0 +1,2115 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.0.3 + * @date 09. August 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/CMSIS/Core/Include/mpu_armv7.h b/platform/CMSIS/Core/Include/mpu_armv7.h new file mode 100644 index 0000000..49b86ab --- /dev/null +++ b/platform/CMSIS/Core/Include/mpu_armv7.h @@ -0,0 +1,204 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for ARMv7 MPU + * @version V5.0.3 + * @date 09. August 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) + +#define ARM_MPU_AP_NONE 0U +#define ARM_MPU_AP_PRIV 1U +#define ARM_MPU_AP_URO 2U +#define ARM_MPU_AP_FULL 3U +#define ARM_MPU_AP_PRO 5U +#define ARM_MPU_AP_RO 6U + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Region Attribut and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (MPU_RASR_ENABLE_Msk)) + + +/** +* Struct for a single MPU Region +*/ +#if defined (__CMCPPARM__) +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; +#else +typedef struct _ARM_MPU_Region_t { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; +#endif + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/platform/Device/NIIET/K1921VK035/Include/K1921VK035.h b/platform/Device/NIIET/K1921VK035/Include/K1921VK035.h new file mode 100644 index 0000000..233fb0a --- /dev/null +++ b/platform/Device/NIIET/K1921VK035/Include/K1921VK035.h @@ -0,0 +1,10223 @@ +/******************************************************************************* + * @file: K1921VK035.h + * @author NIIET + * @version: V2.10 + * @date: 22.02.2019 + * @brief: K1921VK035 header file + ******************************************************************************* + *

+ * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, NIIET NOT BE HELD LIABLE FOR ANY DIRECT, + * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2019 NIIET

+ ******************************************************************************* + * FILE K1921VK035.h + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __K1921VK035_H +#define __K1921VK035_H + +#define __I volatile const /*!< defines 'read only' permissions */ +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + +/* Start of section using anonymous unions */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#elif defined (__CMCPPARM__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* Configuration of the Cortex-M4F Processor and Core Peripherals */ +#define __CM4_REV 0x0001 /*!< Cortex-M4F Core Revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ + +#include "stdint.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************/ +/* Interrupt Number Definition */ +/******************************************************************************/ + +typedef enum IRQn +{ +/*-- Cortex-M4F Processor Exceptions Numbers ---------------------------------*/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer Interrupt */ +/*-- Device specific Interrupt Numbers ---------------------------------------*/ + WDT_IRQn = 0, /*!< Watchdog timer interrupt */ + RCU_IRQn = 1, /*!< Reset and clock unit interrupt */ + MFLASH_IRQn = 2, /*!< MFLASH interrupt */ + GPIOA_IRQn = 3, /*!< GPIO A interrupt */ + GPIOB_IRQn = 4, /*!< GPIO B interrupt */ + DMA_CH0_IRQn = 5, /*!< DMA channel 0 interrupt */ + DMA_CH1_IRQn = 6, /*!< DMA channel 1 interrupt */ + DMA_CH2_IRQn = 7, /*!< DMA channel 2 interrupt */ + DMA_CH3_IRQn = 8, /*!< DMA channel 3 interrupt */ + DMA_CH4_IRQn = 9, /*!< DMA channel 4 interrupt */ + DMA_CH5_IRQn = 10, /*!< DMA channel 5 interrupt */ + DMA_CH6_IRQn = 11, /*!< DMA channel 6 interrupt */ + DMA_CH7_IRQn = 12, /*!< DMA channel 7 interrupt */ + DMA_CH8_IRQn = 13, /*!< DMA channel 8 interrupt */ + DMA_CH9_IRQn = 14, /*!< DMA channel 9 interrupt */ + DMA_CH10_IRQn = 15, /*!< DMA channel 10 interrupt */ + DMA_CH11_IRQn = 16, /*!< DMA channel 11 interrupt */ + DMA_CH12_IRQn = 17, /*!< DMA channel 12 interrupt */ + DMA_CH13_IRQn = 18, /*!< DMA channel 13 interrupt */ + DMA_CH14_IRQn = 19, /*!< DMA channel 14 interrupt */ + DMA_CH15_IRQn = 20, /*!< DMA channel 15 interrupt */ + TMR0_IRQn = 21, /*!< Timer 0 interrupt */ + TMR1_IRQn = 22, /*!< Timer 1 interrupt */ + TMR2_IRQn = 23, /*!< Timer 2 interrupt */ + TMR3_IRQn = 24, /*!< Timer 3 interrupt */ + UART0_TD_IRQn = 25, /*!< UART0 Transmit Done interrupt */ + UART0_RX_IRQn = 26, /*!< UART0 Recieve interrupt */ + UART0_TX_IRQn = 27, /*!< UART0 Transmit interrupt */ + UART0_E_RT_IRQn = 28, /*!< UART0 Error and Receive Timeout interrupt*/ + UART1_TD_IRQn = 29, /*!< UART1 Transmit Done interrupt */ + UART1_RX_IRQn = 30, /*!< UART1 Recieve interrupt */ + UART1_TX_IRQn = 31, /*!< UART1 Transmit interrupt */ + UART1_E_RT_IRQn = 32, /*!< UART1 Error and Receive Timeout interrupt*/ + SPI_RO_RT_IRQn = 33, /*!< SPI RX FIFO overrun and Receive Timeout interrupt*/ + SPI_RX_IRQn = 34, /*!< SPI Receive interrupt */ + SPI_TX_IRQn = 35, /*!< SPI Transmit interrupt */ + I2C_IRQn = 36, /*!< I2C interrupt */ + ECAP0_IRQn = 37, /*!< ECAP0 interrupt */ + ECAP1_IRQn = 38, /*!< ECAP1 interrupt */ + ECAP2_IRQn = 39, /*!< ECAP2 interrupt */ + PWM0_IRQn = 40, /*!< PWM0 interrupt */ + PWM0_HD_IRQn = 41, /*!< PWM0 HD interrupt */ + PWM0_TZ_IRQn = 42, /*!< PWM0 TZ interrupt */ + PWM1_IRQn = 43, /*!< PWM1 interrupt */ + PWM1_HD_IRQn = 44, /*!< PWM1 HD interrupt */ + PWM1_TZ_IRQn = 45, /*!< PWM1 TZ interrupt */ + PWM2_IRQn = 46, /*!< PWM2 interrupt */ + PWM2_HD_IRQn = 47, /*!< PWM2 HD interrupt */ + PWM2_TZ_IRQn = 48, /*!< PWM2 TZ interrupt */ + QEP_IRQn = 49, /*!< QEP interrupt */ + ADC_SEQ0_IRQn = 50, /*!< ADC Sequencer 0 interrupt */ + ADC_SEQ1_IRQn = 51, /*!< ADC Sequencer 1 interrupt */ + ADC_DC_IRQn = 52, /*!< ADC Digital Comparator interrupt */ + CAN0_IRQn = 53, /*!< CAN0 interrupt */ + CAN1_IRQn = 54, /*!< CAN1 interrupt */ + CAN2_IRQn = 55, /*!< CAN2 interrupt */ + CAN3_IRQn = 56, /*!< CAN3 interrupt */ + CAN4_IRQn = 57, /*!< CAN4 interrupt */ + CAN5_IRQn = 58, /*!< CAN5 interrupt */ + CAN6_IRQn = 59, /*!< CAN6 interrupt */ + CAN7_IRQn = 60, /*!< CAN7 interrupt */ + CAN8_IRQn = 61, /*!< CAN8 interrupt */ + CAN9_IRQn = 62, /*!< CAN9 interrupt */ + CAN10_IRQn = 63, /*!< CAN10 interrupt */ + CAN11_IRQn = 64, /*!< CAN11 interrupt */ + CAN12_IRQn = 65, /*!< CAN12 interrupt */ + CAN13_IRQn = 66, /*!< CAN13 interrupt */ + CAN14_IRQn = 67, /*!< CAN14 interrupt */ + CAN15_IRQn = 68, /*!< CAN15 interrupt */ + FPU_IRQn = 69, /*!< FPU exception interrupt */ +} IRQn_Type; + +#include /* Cortex-M4 processor and core peripherals */ +#include /* System initialization */ + +/******************************************************************************/ +/* System Specific Defenitions */ +/******************************************************************************/ +/*-- System memory ----------------------------------------------------------*/ +#define MEM_MFLASH_BASE 0x00000000UL +#define MEM_MFLASH_BUS_WIDTH_WORDS 2UL +#define MEM_MFLASH_PAGE_SIZE 1024UL +#define MEM_MFLASH_PAGE_SIZE_LOG2 10UL +#define MEM_MFLASH_PAGE_TOTAL 64UL +#define MEM_MFLASH_SIZE (MEM_MFLASH_PAGE_TOTAL*MEM_MFLASH_PAGE_SIZE) +#define MEM_MFLASH_NVR_PAGE_SIZE (MEM_MFLASH_PAGE_SIZE) +#define MEM_MFLASH_NVR_PAGE_SIZE_LOG2 (MEM_MFLASH_PAGE_SIZE_LOG2) +#define MEM_MFLASH_NVR_PAGE_TOTAL 4UL +#define MEM_MFLASH_NVR_SIZE (MEM_MFLASH_NVR_PAGE_TOTAL*MEM_MFLASH_NVR_PAGE_SIZE) +#define MEM_RAM_BASE 0x20000000UL +#define MEM_RAM_SIZE 0x4000UL + +/*-- CFGWORD: System configure word -----------------------------------------*/ +#define CFGWORD_BASE 0x00000C00UL + +typedef struct { + uint32_t JTAGEN : 1; /*!< Enable JTAG pins (default 1 - enabled) */ + uint32_t DEBUGEN : 1; /*!< Enable core debug (default 1 - enabled) */ + uint32_t NVRWE : 1; /*!< NVR flash region write enable (default 1 - enabled) */ + uint32_t FLASHWE : 1; /*!< Main flash region write enable (default 1 - enabled) */ + uint32_t BMODEDIS : 1; /*!< Bootloader disable (default 1 - disabled) */ +} CFGWORD_bits; + +/* Bit field positions: */ +#define CFGWORD_JTAGEN_Pos 0 /*!< Enable JTAG pins (default 1 - enabled) */ +#define CFGWORD_DEBUGEN_Pos 1 /*!< Enable core debug (default 1 - enabled) */ +#define CFGWORD_NVRWE_Pos 2 /*!< NVR flash region write enable (default 1 - enabled) */ +#define CFGWORD_FLASHWE_Pos 3 /*!< Main flash region write enable (default 1 - enabled) */ +#define CFGWORD_BMODEDIS_Pos 4 /*!< Bootloader disable (default 1 - disabled) */ + +/* Bit field masks: */ +#define CFGWORD_JTAGEN_Msk 0x00000001UL /*!< Enable JTAG pins (default 1 - enabled) */ +#define CFGWORD_DEBUGEN_Msk 0x00000002UL /*!< Enable core debug (default 1 - enabled) */ +#define CFGWORD_NVRWE_Msk 0x00000004UL /*!< NVR flash region write enable (default 1 - enabled) */ +#define CFGWORD_FLASHWE_Msk 0x00000008UL /*!< Main flash region write enable (default 1 - enabled) */ +#define CFGWORD_BMODEDIS_Msk 0x00000010UL /*!< Bootloader disable (default 1 - disabled) */ + +/*-- CHANNEL_CFG: DMA channel configure word --------------------------------*/ +typedef struct { + uint32_t CYCLE_CTRL : 3; /*!< The operating mode of the DMA cycle */ + uint32_t NEXT_USEBURST : 1; /*!< Controls if the DMA->USEBURSTSET bit is set to a 1 */ + uint32_t N_MINUS_1 : 10; /*!< The total number of DMA transfers that the DMA cycle contains */ + uint32_t R_POWER : 4; /*!< Control how many DMA transfers can occur before the controller rearbitrates (2^R_POWER, 1024 max) */ + uint32_t SRC_PROT_PRIV : 1; /*!< Bus protection when the controller reads the source data: privileged access */ + uint32_t SRC_PROT_BUFF : 1; /*!< Bus protection when the controller reads the source data: bufferable access */ + uint32_t SRC_PROT_CACHE : 1; /*!< Bus protection when the controller reads the source data: cacheable access */ + uint32_t DST_PROT_PRIV : 1; /*!< Bus protection when the controller writes the destination data: privileged access */ + uint32_t DST_PROT_BUFF : 1; /*!< Bus protection when the controller writes the destination data: bufferable access */ + uint32_t DST_PROT_CACHE : 1; /*!< Bus protection when the controller writes the destination data: cacheable access */ + uint32_t SRC_SIZE : 2; /*!< Size of the source data */ + uint32_t SRC_INC : 2; /*!< Source address increment */ + uint32_t DST_SIZE : 2; /*!< Destination data size */ + uint32_t DST_INC : 2; /*!< Destination address increment */ +} _CHANNEL_CFG_bits; + +/* Bit field positions: */ +#define DMA_CHANNEL_CFG_CYCLE_CTRL_Pos 0 /*!< The operating mode of the DMA cycle */ +#define DMA_CHANNEL_CFG_NEXT_USEBURST_Pos 3 /*!< Controls if the DMA->USEBURSTSET bit is set to a 1 */ +#define DMA_CHANNEL_CFG_N_MINUS_1_Pos 4 /*!< The total number of DMA transfers that the DMA cycle contains */ +#define DMA_CHANNEL_CFG_R_POWER_Pos 14 /*!< Control how many DMA transfers can occur before the controller rearbitrates */ +#define DMA_CHANNEL_CFG_SRC_PROT_PRIV_Pos 18 /*!< Bus protection when the controller reads the source data: privileged access */ +#define DMA_CHANNEL_CFG_SRC_PROT_BUFF_Pos 19 /*!< Bus protection when the controller reads the source data: bufferable access */ +#define DMA_CHANNEL_CFG_SRC_PROT_CACHE_Pos 20 /*!< Bus protection when the controller reads the source data: cacheable access */ +#define DMA_CHANNEL_CFG_DST_PROT_PRIV_Pos 21 /*!< Bus protection when the controller writes the destination data: privileged access */ +#define DMA_CHANNEL_CFG_DST_PROT_BUFF_Pos 22 /*!< Bus protection when the controller writes the destination data: bufferable access */ +#define DMA_CHANNEL_CFG_DST_PROT_CACHE_Pos 23 /*!< Bus protection when the controller writes the destination data: cacheable access */ +#define DMA_CHANNEL_CFG_SRC_SIZE_Pos 24 /*!< Size of the source data */ +#define DMA_CHANNEL_CFG_SRC_INC_Pos 26 /*!< Source address increment */ +#define DMA_CHANNEL_CFG_DST_SIZE_Pos 28 /*!< Destination data size */ +#define DMA_CHANNEL_CFG_DST_INC_Pos 30 /*!< Destination address increment */ + +/* Bit field masks: */ +#define DMA_CHANNEL_CFG_CYCLE_CTRL_Msk 0x00000007UL /*!< The operating mode of the DMA cycle */ +#define DMA_CHANNEL_CFG_NEXT_USEBURST_Msk 0x00000008UL /*!< Controls if the DMA->USEBURSTSET bit is set to a 1 */ +#define DMA_CHANNEL_CFG_N_MINUS_1_Msk 0x00003FF0UL /*!< The total number of DMA transfers that the DMA cycle contains */ +#define DMA_CHANNEL_CFG_R_POWER_Msk 0x0003C000UL /*!< Control how many DMA transfers can occur before the controller rearbitrates */ +#define DMA_CHANNEL_CFG_SRC_PROT_PRIV_Msk 0x00040000UL /*!< Bus protection when the controller reads the source data: privileged access */ +#define DMA_CHANNEL_CFG_SRC_PROT_BUFF_Msk 0x00080000UL /*!< Bus protection when the controller reads the source data: bufferable access */ +#define DMA_CHANNEL_CFG_SRC_PROT_CACHE_Msk 0x00100000UL /*!< Bus protection when the controller reads the source data: cacheable access */ +#define DMA_CHANNEL_CFG_DST_PROT_PRIV_Msk 0x00200000UL /*!< Bus protection when the controller writes the destination data: privileged access */ +#define DMA_CHANNEL_CFG_DST_PROT_BUFF_Msk 0x00400000UL /*!< Bus protection when the controller writes the destination data: bufferable access */ +#define DMA_CHANNEL_CFG_DST_PROT_CACHE_Msk 0x00800000UL /*!< Bus protection when the controller writes the destination data: cacheable access */ +#define DMA_CHANNEL_CFG_SRC_SIZE_Msk 0x03000000UL /*!< Size of the source data */ +#define DMA_CHANNEL_CFG_SRC_INC_Msk 0x0C000000UL /*!< Source address increment */ +#define DMA_CHANNEL_CFG_DST_SIZE_Msk 0x30000000UL /*!< Destination data size */ +#define DMA_CHANNEL_CFG_DST_INC_Msk 0xC0000000UL /*!< Destination address increment */ + +/* Bit field enums: */ +typedef enum { + DMA_CHANNEL_CFG_CYCLE_CTRL_Stop = 0x0UL, /*!< Stop */ + DMA_CHANNEL_CFG_CYCLE_CTRL_Basic = 0x1UL, /*!< Basic */ + DMA_CHANNEL_CFG_CYCLE_CTRL_AutoReq = 0x2UL, /*!< Auto-request */ + DMA_CHANNEL_CFG_CYCLE_CTRL_PingPong = 0x3UL, /*!< Ping-pong */ + DMA_CHANNEL_CFG_CYCLE_CTRL_MemScatGathPrim = 0x4UL, /*!< Memory scatter-gather for primary structure */ + DMA_CHANNEL_CFG_CYCLE_CTRL_MemScatGathAlt = 0x5UL, /*!< Memory scatter-gather for alternative structure */ + DMA_CHANNEL_CFG_CYCLE_CTRL_PeriphScatGathPrim = 0x6UL, /*!< Peripheral scatter-gather for primary structure */ + DMA_CHANNEL_CFG_CYCLE_CTRL_PeriphScatGathAlt = 0x7UL, /*!< Peripheral scatter-gather for alternative structure */ +} DMA_CHANNEL_CFG_CYCLE_CTRL_Enum; + +typedef enum { + DMA_CHANNEL_CFG_SRC_SIZE_Byte = 0x0UL, /*!< 8 bit */ + DMA_CHANNEL_CFG_SRC_SIZE_Halfword = 0x1UL, /*!< 16 bit */ + DMA_CHANNEL_CFG_SRC_SIZE_Word = 0x2UL, /*!< 32 bit */ +} DMA_CHANNEL_CFG_SRC_SIZE_Enum; + +typedef enum { + DMA_CHANNEL_CFG_SRC_INC_Byte = 0x0UL, /*!< 8 bit */ + DMA_CHANNEL_CFG_SRC_INC_Halfword = 0x1UL, /*!< 16 bit */ + DMA_CHANNEL_CFG_SRC_INC_Word = 0x2UL, /*!< 32 bit */ + DMA_CHANNEL_CFG_SRC_INC_None = 0x3UL, /*!< No increment */ +} DMA_CHANNEL_CFG_SRC_INC_Enum; + +typedef enum { + DMA_CHANNEL_CFG_DST_SIZE_Byte = 0x0UL, /*!< 8 bit */ + DMA_CHANNEL_CFG_DST_SIZE_Halfword = 0x1UL, /*!< 16 bit */ + DMA_CHANNEL_CFG_DST_SIZE_Word = 0x2UL, /*!< 32 bit */ +} DMA_CHANNEL_CFG_DST_SIZE_Enum; + +typedef enum { + DMA_CHANNEL_CFG_DST_INC_Byte = 0x0UL, /*!< 8 bit */ + DMA_CHANNEL_CFG_DST_INC_Halfword = 0x1UL, /*!< 16 bit */ + DMA_CHANNEL_CFG_DST_INC_Word = 0x2UL, /*!< 32 bit */ + DMA_CHANNEL_CFG_DST_INC_None = 0x3UL, /*!< No increment */ +} DMA_CHANNEL_CFG_DST_INC_Enum; + +/*-- DMA channel structure --------------------------------------------------*/ +typedef struct +{ + __IO uint32_t SRC_DATA_END_PTR; /*!< Source data end pointer */ + __IO uint32_t DST_DATA_END_PTR; /*!< Destination data end pointer */ + union { + __IO uint32_t CHANNEL_CFG; /*!< Channel configure word */ + __IO _CHANNEL_CFG_bits CHANNEL_CFG_bit; /*!< channel configure word: bit access */ + }; + __IO uint32_t RESERVED; +} DMA_Channel_TypeDef; + +/*-- DMA control structure --------------------------------------------------*/ +typedef struct +{ + DMA_Channel_TypeDef CH[16]; /*!< Control structure channels */ +} DMA_CtrlStruct_TypeDef; + +#define DMA_CH_UART0TX 0 /*!< UART0 TX DMA channel */ +#define DMA_CH_UART1TX 1 /*!< UART1 TX DMA channel */ +#define DMA_CH_UART0RX 2 /*!< UART0 RX DMA channel */ +#define DMA_CH_UART1RX 3 /*!< UART1 RX DMA channel */ +#define DMA_CH_ADCSEQ0 4 /*!< ADC sequencer 0 DMA channel */ +#define DMA_CH_ADCSEQ1 5 /*!< ADC sequencer 1 DMA channel */ +#define DMA_CH_SPITX 6 /*!< SPI TX DMA channel */ +#define DMA_CH_SPIRX 7 /*!< SPI RX DMA channel */ +#define DMA_CH_QEP 8 /*!< QEP DMA channel */ +#define DMA_CH_GPIOA 8 /*!< GPIOA DMA channel */ +#define DMA_CH_GPIOB 9 /*!< GPIOB DMA channel */ +#define DMA_CH_TMR0 9 /*!< TMR0 DMA channel */ +#define DMA_CH_TMR1 10 /*!< TMR1 DMA channel */ +#define DMA_CH_TMR2 11 /*!< TMR2 DMA channel */ +#define DMA_CH_TMR3 12 /*!< TMR3 DMA channel */ +#define DMA_CH_PWM0B 10 /*!< PWM0B DMA channel */ +#define DMA_CH_PWM1B 11 /*!< PWM1B DMA channel */ +#define DMA_CH_PWM2B 12 /*!< PWM2B DMA channel */ +#define DMA_CH_PWM0A 13 /*!< PWM0A DMA channel */ +#define DMA_CH_PWM1A 14 /*!< PWM1A DMA channel */ +#define DMA_CH_PWM2A 15 /*!< PWM2A DMA channel */ + +/*-- DMA control data summary -----------------------------------------------*/ +/*!< WARNING: struct should be 512 byte aligned! Allowed addresses 0xXXXXX000, 0xXXXXX200, 0xXXXXX400, etc */ +typedef struct +{ + DMA_CtrlStruct_TypeDef PRM_DATA; /*!< Primary control structure */ + DMA_CtrlStruct_TypeDef ALT_DATA; /*!< Alternative control structure */ +} DMA_CtrlData_TypeDef; + + +/******************************************************************************/ +/* SIU registers */ +/******************************************************************************/ + +/*-- PWMSYNC: PWM syncronization control register ------------------------------------------------------------*/ +typedef struct { + uint32_t :8; /*!< RESERVED */ + uint32_t PRESCRST :3; /*!< PWM prescalers reset control */ +} _SIU_PWMSYNC_bits; + +/* Bit field positions: */ +#define SIU_PWMSYNC_PRESCRST_Pos 8 /*!< PWM prescalers reset control */ + +/* Bit field masks: */ +#define SIU_PWMSYNC_PRESCRST_Msk 0x00000700UL /*!< PWM prescalers reset control */ + +/*-- SERVCTL: Service mode control register ------------------------------------------------------------------*/ +typedef struct { + uint32_t CHIPCLR :1; /*!< On-chip memories full clear task start */ + uint32_t DONE :1; /*!< Status of clear task */ + uint32_t :29; /*!< RESERVED */ + uint32_t SERVEN :1; /*!< */ +} _SIU_SERVCTL_bits; + +/* Bit field positions: */ +#define SIU_SERVCTL_CHIPCLR_Pos 0 /*!< On-chip memories full clear task start */ +#define SIU_SERVCTL_DONE_Pos 1 /*!< Status of clear task */ +#define SIU_SERVCTL_SERVEN_Pos 31 /*!< */ + +/* Bit field masks: */ +#define SIU_SERVCTL_CHIPCLR_Msk 0x00000001UL /*!< On-chip memories full clear task start */ +#define SIU_SERVCTL_DONE_Msk 0x00000002UL /*!< Status of clear task */ +#define SIU_SERVCTL_SERVEN_Msk 0x80000000UL /*!< */ + +/*-- CLKOUTCTL: Clock out control register -------------------------------------------------------------------*/ +typedef struct { + uint32_t CLKOUTEN :1; /*!< Enable clockout pin */ +} _SIU_CLKOUTCTL_bits; + +/* Bit field positions: */ +#define SIU_CLKOUTCTL_CLKOUTEN_Pos 0 /*!< Enable clockout pin */ + +/* Bit field masks: */ +#define SIU_CLKOUTCTL_CLKOUTEN_Msk 0x00000001UL /*!< Enable clockout pin */ + +/*-- REMAPAF: QEP altfunc control ----------------------------------------------------------------------------*/ +typedef struct { + uint32_t QEPEN :1; /*!< Enable QEP altfunc */ + uint32_t ECAP0EN :1; /*!< Enable ECAP0 altfunc */ + uint32_t ECAP1EN :1; /*!< Enable ECAP1 altfunc */ + uint32_t ECAP2EN :1; /*!< Enable ECAP2 altfunc */ +} _SIU_REMAPAF_bits; + +/* Bit field positions: */ +#define SIU_REMAPAF_QEPEN_Pos 0 /*!< Enable QEP altfunc */ +#define SIU_REMAPAF_ECAP0EN_Pos 1 /*!< Enable ECAP0 altfunc */ +#define SIU_REMAPAF_ECAP1EN_Pos 2 /*!< Enable ECAP1 altfunc */ +#define SIU_REMAPAF_ECAP2EN_Pos 3 /*!< Enable ECAP2 altfunc */ + +/* Bit field masks: */ +#define SIU_REMAPAF_QEPEN_Msk 0x00000001UL /*!< Enable QEP altfunc */ +#define SIU_REMAPAF_ECAP0EN_Msk 0x00000002UL /*!< Enable ECAP0 altfunc */ +#define SIU_REMAPAF_ECAP1EN_Msk 0x00000004UL /*!< Enable ECAP1 altfunc */ +#define SIU_REMAPAF_ECAP2EN_Msk 0x00000008UL /*!< Enable ECAP2 altfunc */ + +/*-- DMAMUX: DMA external requests mux control register ------------------------------------------------------*/ +typedef struct { + uint32_t SRCSEL8 :1; /*!< Request source select for DMA channel 8 */ + uint32_t :3; /*!< RESERVED */ + uint32_t SRCSEL9 :1; /*!< Request source select for DMA channel 9 */ + uint32_t :3; /*!< RESERVED */ + uint32_t SRCSEL10 :1; /*!< Request source select for DMA channel 10 */ + uint32_t :3; /*!< RESERVED */ + uint32_t SRCSEL11 :1; /*!< Request source select for DMA channel 11 */ + uint32_t :3; /*!< RESERVED */ + uint32_t SRCSEL12 :1; /*!< Request source select for DMA channel 12 */ + uint32_t :3; /*!< RESERVED */ + uint32_t SRCSEL13 :1; /*!< Request source select for DMA channel 13 */ + uint32_t :3; /*!< RESERVED */ + uint32_t SRCSEL14 :1; /*!< Request source select for DMA channel 14 */ + uint32_t :3; /*!< RESERVED */ + uint32_t SRCSEL15 :1; /*!< Request source select for DMA channel 15 */ +} _SIU_DMAMUX_bits; + +/* Bit field positions: */ +#define SIU_DMAMUX_SRCSEL8_Pos 0 /*!< Request source select for DMA channel 8 */ +#define SIU_DMAMUX_SRCSEL9_Pos 4 /*!< Request source select for DMA channel 9 */ +#define SIU_DMAMUX_SRCSEL10_Pos 8 /*!< Request source select for DMA channel 10 */ +#define SIU_DMAMUX_SRCSEL11_Pos 12 /*!< Request source select for DMA channel 11 */ +#define SIU_DMAMUX_SRCSEL12_Pos 16 /*!< Request source select for DMA channel 12 */ +#define SIU_DMAMUX_SRCSEL13_Pos 20 /*!< Request source select for DMA channel 13 */ +#define SIU_DMAMUX_SRCSEL14_Pos 24 /*!< Request source select for DMA channel 14 */ +#define SIU_DMAMUX_SRCSEL15_Pos 28 /*!< Request source select for DMA channel 15 */ + +/* Bit field masks: */ +#define SIU_DMAMUX_SRCSEL8_Msk 0x00000001UL /*!< Request source select for DMA channel 8 */ +#define SIU_DMAMUX_SRCSEL9_Msk 0x00000010UL /*!< Request source select for DMA channel 9 */ +#define SIU_DMAMUX_SRCSEL10_Msk 0x00000100UL /*!< Request source select for DMA channel 10 */ +#define SIU_DMAMUX_SRCSEL11_Msk 0x00001000UL /*!< Request source select for DMA channel 11 */ +#define SIU_DMAMUX_SRCSEL12_Msk 0x00010000UL /*!< Request source select for DMA channel 12 */ +#define SIU_DMAMUX_SRCSEL13_Msk 0x00100000UL /*!< Request source select for DMA channel 13 */ +#define SIU_DMAMUX_SRCSEL14_Msk 0x01000000UL /*!< Request source select for DMA channel 14 */ +#define SIU_DMAMUX_SRCSEL15_Msk 0x10000000UL /*!< Request source select for DMA channel 15 */ + +/* Bit field enums: */ +typedef enum { + SIU_DMAMUX_SRCSEL8_QEP = 0x0UL, /*!< request by QEP */ + SIU_DMAMUX_SRCSEL8_GPIOA = 0x1UL, /*!< request by GPIOA */ +} SIU_DMAMUX_SRCSEL8_Enum; + +typedef enum { + SIU_DMAMUX_SRCSEL9_TMR0 = 0x0UL, /*!< request by TMR0 */ + SIU_DMAMUX_SRCSEL9_GPIOB = 0x1UL, /*!< request by GPIOB */ +} SIU_DMAMUX_SRCSEL9_Enum; + +typedef enum { + SIU_DMAMUX_SRCSEL10_TMR1 = 0x0UL, /*!< request by TMR1 */ + SIU_DMAMUX_SRCSEL10_PWM0B = 0x1UL, /*!< request by PWM0B */ +} SIU_DMAMUX_SRCSEL10_Enum; + +typedef enum { + SIU_DMAMUX_SRCSEL11_TMR2 = 0x0UL, /*!< request by TMR2 */ + SIU_DMAMUX_SRCSEL11_PWM1B = 0x1UL, /*!< request by PWM1B */ +} SIU_DMAMUX_SRCSEL11_Enum; + +typedef enum { + SIU_DMAMUX_SRCSEL12_TMR3 = 0x0UL, /*!< request by TMR3 */ + SIU_DMAMUX_SRCSEL12_PWM2B = 0x1UL, /*!< request by PWM2B */ +} SIU_DMAMUX_SRCSEL12_Enum; + +typedef enum { + SIU_DMAMUX_SRCSEL13_PWM0A = 0x0UL, /*!< request by PWM0A */ + SIU_DMAMUX_SRCSEL13_Reserved = 0x1UL, /*!< no source */ +} SIU_DMAMUX_SRCSEL13_Enum; + +typedef enum { + SIU_DMAMUX_SRCSEL14_PWM1A = 0x0UL, /*!< request by PWM1A */ + SIU_DMAMUX_SRCSEL14_Reserved = 0x1UL, /*!< no source */ +} SIU_DMAMUX_SRCSEL14_Enum; + +typedef enum { + SIU_DMAMUX_SRCSEL15_PWM2A = 0x0UL, /*!< request by PWM2A */ + SIU_DMAMUX_SRCSEL15_Reserved = 0x1UL, /*!< no source */ +} SIU_DMAMUX_SRCSEL15_Enum; + +/*-- CHIPID: Chip identifier ---------------------------------------------------------------------------------*/ +typedef struct { + uint32_t REV :4; /*!< Revision number */ + uint32_t ID :28; /*!< Model ID */ +} _SIU_CHIPID_bits; + +/* Bit field positions: */ +#define SIU_CHIPID_REV_Pos 0 /*!< Revision number */ +#define SIU_CHIPID_ID_Pos 4 /*!< Model ID */ + +/* Bit field masks: */ +#define SIU_CHIPID_REV_Msk 0x0000000FUL /*!< Revision number */ +#define SIU_CHIPID_ID_Msk 0xFFFFFFF0UL /*!< Model ID */ + +typedef struct { + __IO uint32_t Reserved0[4]; + union { /*!< PWM syncronization control register */ + __IO uint32_t PWMSYNC; /*!< PWMSYNC : type used for word access */ + __IO _SIU_PWMSYNC_bits PWMSYNC_bit; /*!< PWMSYNC_bit: structure used for bit access */ + }; + union { /*!< Service mode control register */ + __IO uint32_t SERVCTL; /*!< SERVCTL : type used for word access */ + __IO _SIU_SERVCTL_bits SERVCTL_bit; /*!< SERVCTL_bit: structure used for bit access */ + }; + union { /*!< Clock out control register */ + __IO uint32_t CLKOUTCTL; /*!< CLKOUTCTL : type used for word access */ + __IO _SIU_CLKOUTCTL_bits CLKOUTCTL_bit; /*!< CLKOUTCTL_bit: structure used for bit access */ + }; + union { /*!< QEP altfunc control */ + __IO uint32_t REMAPAF; /*!< REMAPAF : type used for word access */ + __IO _SIU_REMAPAF_bits REMAPAF_bit; /*!< REMAPAF_bit: structure used for bit access */ + }; + union { /*!< DMA external requests mux control register */ + __IO uint32_t DMAMUX; /*!< DMAMUX : type used for word access */ + __IO _SIU_DMAMUX_bits DMAMUX_bit; /*!< DMAMUX_bit: structure used for bit access */ + }; + __IO uint32_t Reserved1[1014]; + union { /*!< Chip identifier */ + __I uint32_t CHIPID; /*!< CHIPID : type used for word access */ + __I _SIU_CHIPID_bits CHIPID_bit; /*!< CHIPID_bit: structure used for bit access */ + }; +} SIU_TypeDef; + + +/******************************************************************************/ +/* RCU registers */ +/******************************************************************************/ + +/*-- OSICFG: Internal oscillator configuration register ------------------------------------------------------*/ +typedef struct { + uint32_t EN :1; /*!< Oscillator 8MHz enable */ + uint32_t :15; /*!< RESERVED */ + uint32_t CAL :10; /*!< Oscillator 8MHz calibration value */ +} _RCU_OSICFG_bits; + +/* Bit field positions: */ +#define RCU_OSICFG_EN_Pos 0 /*!< Oscillator 8MHz enable */ +#define RCU_OSICFG_CAL_Pos 16 /*!< Oscillator 8MHz calibration value */ + +/* Bit field masks: */ +#define RCU_OSICFG_EN_Msk 0x00000001UL /*!< Oscillator 8MHz enable */ +#define RCU_OSICFG_CAL_Msk 0x03FF0000UL /*!< Oscillator 8MHz calibration value */ + +/*-- OSECFG: External oscillator configuration register ------------------------------------------------------*/ +typedef struct { + uint32_t XOEN :1; /*!< Enable output XO_OSC from external oscillator */ + uint32_t EN :1; /*!< Enable external oscallator */ +} _RCU_OSECFG_bits; + +/* Bit field positions: */ +#define RCU_OSECFG_XOEN_Pos 0 /*!< Enable output XO_OSC from external oscillator */ +#define RCU_OSECFG_EN_Pos 1 /*!< Enable external oscallator */ + +/* Bit field masks: */ +#define RCU_OSECFG_XOEN_Msk 0x00000001UL /*!< Enable output XO_OSC from external oscillator */ +#define RCU_OSECFG_EN_Msk 0x00000002UL /*!< Enable external oscallator */ + +/*-- PLLCFG: PLL configuration register ----------------------------------------------------------------------*/ +typedef struct { + uint32_t M :6; /*!< PLL M Coefficient */ + uint32_t :2; /*!< RESERVED */ + uint32_t N :6; /*!< PLL N Coefficient */ + uint32_t :2; /*!< RESERVED */ + uint32_t OD :2; /*!< PLL OD Coefficient */ + uint32_t :2; /*!< RESERVED */ + uint32_t REFSRC :1; /*!< PLL Reference source select bit */ + uint32_t :3; /*!< RESERVED */ + uint32_t BYPASS :1; /*!< PLL Bypass enable */ + uint32_t :1; /*!< RESERVED */ + uint32_t OUTEN :1; /*!< Enable PLL out */ + uint32_t :1; /*!< RESERVED */ + uint32_t LOCK :1; /*!< PLL status lock */ +} _RCU_PLLCFG_bits; + +/* Bit field positions: */ +#define RCU_PLLCFG_M_Pos 0 /*!< PLL M Coefficient */ +#define RCU_PLLCFG_N_Pos 8 /*!< PLL N Coefficient */ +#define RCU_PLLCFG_OD_Pos 16 /*!< PLL OD Coefficient */ +#define RCU_PLLCFG_REFSRC_Pos 20 /*!< PLL Reference source select bit */ +#define RCU_PLLCFG_BYPASS_Pos 24 /*!< PLL Bypass enable */ +#define RCU_PLLCFG_OUTEN_Pos 26 /*!< Enable PLL out */ +#define RCU_PLLCFG_LOCK_Pos 28 /*!< PLL status lock */ + +/* Bit field masks: */ +#define RCU_PLLCFG_M_Msk 0x0000003FUL /*!< PLL M Coefficient */ +#define RCU_PLLCFG_N_Msk 0x00003F00UL /*!< PLL N Coefficient */ +#define RCU_PLLCFG_OD_Msk 0x00030000UL /*!< PLL OD Coefficient */ +#define RCU_PLLCFG_REFSRC_Msk 0x00100000UL /*!< PLL Reference source select bit */ +#define RCU_PLLCFG_BYPASS_Msk 0x01000000UL /*!< PLL Bypass enable */ +#define RCU_PLLCFG_OUTEN_Msk 0x04000000UL /*!< Enable PLL out */ +#define RCU_PLLCFG_LOCK_Msk 0x10000000UL /*!< PLL status lock */ + +/* Bit field enums: */ +typedef enum { + RCU_PLLCFG_OD_Disable = 0x0UL, /*!< disabled */ + RCU_PLLCFG_OD_Div2 = 0x1UL, /*!< divide by 2 */ + RCU_PLLCFG_OD_Div4 = 0x2UL, /*!< divide by 4 */ + RCU_PLLCFG_OD_Div8 = 0x3UL, /*!< divide by 8 */ +} RCU_PLLCFG_OD_Enum; + +typedef enum { + RCU_PLLCFG_REFSRC_OSECLK = 0x0UL, /*!< external oscillator */ + RCU_PLLCFG_REFSRC_OSICLK = 0x1UL, /*!< internal oscillator */ +} RCU_PLLCFG_REFSRC_Enum; + +/*-- PLLDIV: PLL divider register ----------------------------------------------------------------------------*/ +typedef struct { + uint32_t DIVEN :1; /*!< PLL Divider enable bit */ + uint32_t :7; /*!< RESERVED */ + uint32_t DIV :6; /*!< PLL divider coefficent */ +} _RCU_PLLDIV_bits; + +/* Bit field positions: */ +#define RCU_PLLDIV_DIVEN_Pos 0 /*!< PLL Divider enable bit */ +#define RCU_PLLDIV_DIV_Pos 8 /*!< PLL divider coefficent */ + +/* Bit field masks: */ +#define RCU_PLLDIV_DIVEN_Msk 0x00000001UL /*!< PLL Divider enable bit */ +#define RCU_PLLDIV_DIV_Msk 0x00003F00UL /*!< PLL divider coefficent */ + +/*-- SYSCLKCFG: System clock configuration register ----------------------------------------------------------*/ +typedef struct { + uint32_t SYSSEL :2; /*!< System clock source selection */ + uint32_t :14; /*!< RESERVED */ + uint32_t SECEN :1; /*!< Enable clock security system */ +} _RCU_SYSCLKCFG_bits; + +/* Bit field positions: */ +#define RCU_SYSCLKCFG_SYSSEL_Pos 0 /*!< System clock source selection */ +#define RCU_SYSCLKCFG_SECEN_Pos 16 /*!< Enable clock security system */ + +/* Bit field masks: */ +#define RCU_SYSCLKCFG_SYSSEL_Msk 0x00000003UL /*!< System clock source selection */ +#define RCU_SYSCLKCFG_SECEN_Msk 0x00010000UL /*!< Enable clock security system */ + +/* Bit field enums: */ +typedef enum { + RCU_SYSCLKCFG_SYSSEL_OSICLK = 0x0UL, /*!< internal oscillator */ + RCU_SYSCLKCFG_SYSSEL_OSECLK = 0x1UL, /*!< external oscillator */ + RCU_SYSCLKCFG_SYSSEL_PLLCLK = 0x2UL, /*!< PLL output clock */ + RCU_SYSCLKCFG_SYSSEL_PLLDIVCLK = 0x3UL, /*!< PLL divided clock */ +} RCU_SYSCLKCFG_SYSSEL_Enum; + +/*-- SYSCLKSTAT: System clock status register ----------------------------------------------------------------*/ +typedef struct { + uint32_t SYSSTAT :2; /*!< Current system source clock */ + uint32_t :2; /*!< RESERVED */ + uint32_t BUSY :1; /*!< Clock manager is busy, for example, when change clock source */ + uint32_t :3; /*!< RESERVED */ + uint32_t SYSFAIL :1; /*!< Error in current clock was detected */ + uint32_t :8; /*!< RESERVED */ + uint32_t OSECLKERR :1; /*!< External oscillator clock fail */ + uint32_t PLLCLKERR :1; /*!< PLL source clock fail */ + uint32_t PLLDIVCLKERR :1; /*!< PLL divided clock fail */ + uint32_t :5; /*!< RESERVED */ + uint32_t OSECLKOK :1; /*!< External oscillator clock good */ + uint32_t PLLCLKOK :1; /*!< PLL clock good */ + uint32_t PLLDIVCLKOK :1; /*!< PLL divided clock good */ +} _RCU_SYSCLKSTAT_bits; + +/* Bit field positions: */ +#define RCU_SYSCLKSTAT_SYSSTAT_Pos 0 /*!< Current system source clock */ +#define RCU_SYSCLKSTAT_BUSY_Pos 4 /*!< Clock manager is busy, for example, when change clock source */ +#define RCU_SYSCLKSTAT_SYSFAIL_Pos 8 /*!< Error in current clock was detected */ +#define RCU_SYSCLKSTAT_OSECLKERR_Pos 17 /*!< External oscillator clock fail */ +#define RCU_SYSCLKSTAT_PLLCLKERR_Pos 18 /*!< PLL source clock fail */ +#define RCU_SYSCLKSTAT_PLLDIVCLKERR_Pos 19 /*!< PLL divided clock fail */ +#define RCU_SYSCLKSTAT_OSECLKOK_Pos 25 /*!< External oscillator clock good */ +#define RCU_SYSCLKSTAT_PLLCLKOK_Pos 26 /*!< PLL clock good */ +#define RCU_SYSCLKSTAT_PLLDIVCLKOK_Pos 27 /*!< PLL divided clock good */ + +/* Bit field masks: */ +#define RCU_SYSCLKSTAT_SYSSTAT_Msk 0x00000003UL /*!< Current system source clock */ +#define RCU_SYSCLKSTAT_BUSY_Msk 0x00000010UL /*!< Clock manager is busy, for example, when change clock source */ +#define RCU_SYSCLKSTAT_SYSFAIL_Msk 0x00000100UL /*!< Error in current clock was detected */ +#define RCU_SYSCLKSTAT_OSECLKERR_Msk 0x00020000UL /*!< External oscillator clock fail */ +#define RCU_SYSCLKSTAT_PLLCLKERR_Msk 0x00040000UL /*!< PLL source clock fail */ +#define RCU_SYSCLKSTAT_PLLDIVCLKERR_Msk 0x00080000UL /*!< PLL divided clock fail */ +#define RCU_SYSCLKSTAT_OSECLKOK_Msk 0x02000000UL /*!< External oscillator clock good */ +#define RCU_SYSCLKSTAT_PLLCLKOK_Msk 0x04000000UL /*!< PLL clock good */ +#define RCU_SYSCLKSTAT_PLLDIVCLKOK_Msk 0x08000000UL /*!< PLL divided clock good */ + +/* Bit field enums: */ +typedef enum { + RCU_SYSCLKSTAT_SYSSTAT_OSICLK = 0x0UL, /*!< internal oscillator */ + RCU_SYSCLKSTAT_SYSSTAT_OSECLK = 0x1UL, /*!< external oscillator */ + RCU_SYSCLKSTAT_SYSSTAT_PLLCLK = 0x2UL, /*!< PLL output clock */ + RCU_SYSCLKSTAT_SYSSTAT_PLLDIVCLK = 0x3UL, /*!< PLL divided clock */ +} RCU_SYSCLKSTAT_SYSSTAT_Enum; + +/*-- SECPRD: Security sysytem clock period register ----------------------------------------------------------*/ +typedef struct { + uint32_t :8; /*!< RESERVED */ + uint32_t OSECLK :8; /*!< Max counter value for external oscillator clock fail detection */ + uint32_t PLLCLK :8; /*!< Max counter value for PLL clock fail detection */ + uint32_t PLLDIVCLK :8; /*!< Max counter value for PLL clock fail detection */ +} _RCU_SECPRD_bits; + +/* Bit field positions: */ +#define RCU_SECPRD_OSECLK_Pos 8 /*!< Max counter value for external oscillator clock fail detection */ +#define RCU_SECPRD_PLLCLK_Pos 16 /*!< Max counter value for PLL clock fail detection */ +#define RCU_SECPRD_PLLDIVCLK_Pos 24 /*!< Max counter value for PLL clock fail detection */ + +/* Bit field masks: */ +#define RCU_SECPRD_OSECLK_Msk 0x0000FF00UL /*!< Max counter value for external oscillator clock fail detection */ +#define RCU_SECPRD_PLLCLK_Msk 0x00FF0000UL /*!< Max counter value for PLL clock fail detection */ +#define RCU_SECPRD_PLLDIVCLK_Msk 0xFF000000UL /*!< Max counter value for PLL clock fail detection */ + +/*-- SYSRSTCFG: System reset configuration register ----------------------------------------------------------*/ +typedef struct { + uint32_t LOCKUPEN :1; /*!< Enable reset when processor in LOCKUP state */ +} _RCU_SYSRSTCFG_bits; + +/* Bit field positions: */ +#define RCU_SYSRSTCFG_LOCKUPEN_Pos 0 /*!< Enable reset when processor in LOCKUP state */ + +/* Bit field masks: */ +#define RCU_SYSRSTCFG_LOCKUPEN_Msk 0x00000001UL /*!< Enable reset when processor in LOCKUP state */ + +/*-- SYSRSTSTAT: Reset status register -----------------------------------------------------------------------*/ +typedef struct { + uint32_t POR :1; /*!< PowerOn Reset status */ + uint32_t WDOG :1; /*!< WatchDog Reset status */ + uint32_t SYSRST :1; /*!< System Reset Status */ + uint32_t LOCKUP :1; /*!< Lockup Reset Status */ +} _RCU_SYSRSTSTAT_bits; + +/* Bit field positions: */ +#define RCU_SYSRSTSTAT_POR_Pos 0 /*!< PowerOn Reset status */ +#define RCU_SYSRSTSTAT_WDOG_Pos 1 /*!< WatchDog Reset status */ +#define RCU_SYSRSTSTAT_SYSRST_Pos 2 /*!< System Reset Status */ +#define RCU_SYSRSTSTAT_LOCKUP_Pos 3 /*!< Lockup Reset Status */ + +/* Bit field masks: */ +#define RCU_SYSRSTSTAT_POR_Msk 0x00000001UL /*!< PowerOn Reset status */ +#define RCU_SYSRSTSTAT_WDOG_Msk 0x00000002UL /*!< WatchDog Reset status */ +#define RCU_SYSRSTSTAT_SYSRST_Msk 0x00000004UL /*!< System Reset Status */ +#define RCU_SYSRSTSTAT_LOCKUP_Msk 0x00000008UL /*!< Lockup Reset Status */ + +/*-- INTEN: Interrupt enable register ------------------------------------------------------------------------*/ +typedef struct { + uint32_t :1; /*!< RESERVED */ + uint32_t OSECLKERR :1; /*!< Enable OSECLK fail interrupt */ + uint32_t PLLCLKERR :1; /*!< Enable PLLCLK fail interrupt */ + uint32_t PLLDIVCLKERR :1; /*!< Enable PLLDIVCLK fail interrupt */ + uint32_t :5; /*!< RESERVED */ + uint32_t OSECLKOK :1; /*!< Enable OSECLK good interrupt */ + uint32_t PLLCLKOK :1; /*!< Enable PLLCLK good interrupt */ + uint32_t PLLDIVCLKOK :1; /*!< Enable PLLDIVCLK good interrupt */ + uint32_t :4; /*!< RESERVED */ + uint32_t PLLLOCK :1; /*!< Enable int from pll lock signal */ +} _RCU_INTEN_bits; + +/* Bit field positions: */ +#define RCU_INTEN_OSECLKERR_Pos 1 /*!< Enable OSECLK fail interrupt */ +#define RCU_INTEN_PLLCLKERR_Pos 2 /*!< Enable PLLCLK fail interrupt */ +#define RCU_INTEN_PLLDIVCLKERR_Pos 3 /*!< Enable PLLDIVCLK fail interrupt */ +#define RCU_INTEN_OSECLKOK_Pos 9 /*!< Enable OSECLK good interrupt */ +#define RCU_INTEN_PLLCLKOK_Pos 10 /*!< Enable PLLCLK good interrupt */ +#define RCU_INTEN_PLLDIVCLKOK_Pos 11 /*!< Enable PLLDIVCLK good interrupt */ +#define RCU_INTEN_PLLLOCK_Pos 16 /*!< Enable int from pll lock signal */ + +/* Bit field masks: */ +#define RCU_INTEN_OSECLKERR_Msk 0x00000002UL /*!< Enable OSECLK fail interrupt */ +#define RCU_INTEN_PLLCLKERR_Msk 0x00000004UL /*!< Enable PLLCLK fail interrupt */ +#define RCU_INTEN_PLLDIVCLKERR_Msk 0x00000008UL /*!< Enable PLLDIVCLK fail interrupt */ +#define RCU_INTEN_OSECLKOK_Msk 0x00000200UL /*!< Enable OSECLK good interrupt */ +#define RCU_INTEN_PLLCLKOK_Msk 0x00000400UL /*!< Enable PLLCLK good interrupt */ +#define RCU_INTEN_PLLDIVCLKOK_Msk 0x00000800UL /*!< Enable PLLDIVCLK good interrupt */ +#define RCU_INTEN_PLLLOCK_Msk 0x00010000UL /*!< Enable int from pll lock signal */ + +/*-- INTSTAT: Interrupt status register ----------------------------------------------------------------------*/ +typedef struct { + uint32_t :1; /*!< RESERVED */ + uint32_t OSECLKERR :1; /*!< Status external oscillator clock fail signal */ + uint32_t PLLCLKERR :1; /*!< Status PLL clock fail signal */ + uint32_t PLLDIVCLKERR :1; /*!< Status PLLDIV clock fail signal */ + uint32_t :5; /*!< RESERVED */ + uint32_t OSECLKOK :1; /*!< Status external oscillator clock good signal */ + uint32_t PLLCLKOK :1; /*!< Status PLL clock good signal */ + uint32_t PLLDIVCLKOK :1; /*!< Status PLLDIV clock good signal */ + uint32_t :4; /*!< RESERVED */ + uint32_t PLLLOCK :1; /*!< Status pll lock signal */ + uint32_t :3; /*!< RESERVED */ + uint32_t SYSFAIL :1; /*!< Current clock failed status */ +} _RCU_INTSTAT_bits; + +/* Bit field positions: */ +#define RCU_INTSTAT_OSECLKERR_Pos 1 /*!< Status external oscillator clock fail signal */ +#define RCU_INTSTAT_PLLCLKERR_Pos 2 /*!< Status PLL clock fail signal */ +#define RCU_INTSTAT_PLLDIVCLKERR_Pos 3 /*!< Status PLLDIV clock fail signal */ +#define RCU_INTSTAT_OSECLKOK_Pos 9 /*!< Status external oscillator clock good signal */ +#define RCU_INTSTAT_PLLCLKOK_Pos 10 /*!< Status PLL clock good signal */ +#define RCU_INTSTAT_PLLDIVCLKOK_Pos 11 /*!< Status PLLDIV clock good signal */ +#define RCU_INTSTAT_PLLLOCK_Pos 16 /*!< Status pll lock signal */ +#define RCU_INTSTAT_SYSFAIL_Pos 20 /*!< Current clock failed status */ + +/* Bit field masks: */ +#define RCU_INTSTAT_OSECLKERR_Msk 0x00000002UL /*!< Status external oscillator clock fail signal */ +#define RCU_INTSTAT_PLLCLKERR_Msk 0x00000004UL /*!< Status PLL clock fail signal */ +#define RCU_INTSTAT_PLLDIVCLKERR_Msk 0x00000008UL /*!< Status PLLDIV clock fail signal */ +#define RCU_INTSTAT_OSECLKOK_Msk 0x00000200UL /*!< Status external oscillator clock good signal */ +#define RCU_INTSTAT_PLLCLKOK_Msk 0x00000400UL /*!< Status PLL clock good signal */ +#define RCU_INTSTAT_PLLDIVCLKOK_Msk 0x00000800UL /*!< Status PLLDIV clock good signal */ +#define RCU_INTSTAT_PLLLOCK_Msk 0x00010000UL /*!< Status pll lock signal */ +#define RCU_INTSTAT_SYSFAIL_Msk 0x00100000UL /*!< Current clock failed status */ + +/*-- TRACECFG: Trace clock configuration register ------------------------------------------------------------*/ +typedef struct { + uint32_t CLKEN :1; /*!< Clock enable */ + uint32_t :7; /*!< RESERVED */ + uint32_t CLKSEL :2; /*!< Clock source select */ + uint32_t :6; /*!< RESERVED */ + uint32_t DIVEN :1; /*!< Enable divider */ + uint32_t :7; /*!< RESERVED */ + uint32_t DIVN :6; /*!< Divider coefficient */ +} _RCU_TRACECFG_bits; + +/* Bit field positions: */ +#define RCU_TRACECFG_CLKEN_Pos 0 /*!< Clock enable */ +#define RCU_TRACECFG_CLKSEL_Pos 8 /*!< Clock source select */ +#define RCU_TRACECFG_DIVEN_Pos 16 /*!< Enable divider */ +#define RCU_TRACECFG_DIVN_Pos 24 /*!< Divider coefficient */ + +/* Bit field masks: */ +#define RCU_TRACECFG_CLKEN_Msk 0x00000001UL /*!< Clock enable */ +#define RCU_TRACECFG_CLKSEL_Msk 0x00000300UL /*!< Clock source select */ +#define RCU_TRACECFG_DIVEN_Msk 0x00010000UL /*!< Enable divider */ +#define RCU_TRACECFG_DIVN_Msk 0x3F000000UL /*!< Divider coefficient */ + +/* Bit field enums: */ +typedef enum { + RCU_TRACECFG_CLKSEL_OSICLK = 0x0UL, /*!< internal oscillator */ + RCU_TRACECFG_CLKSEL_OSECLK = 0x1UL, /*!< external oscillator */ + RCU_TRACECFG_CLKSEL_PLLCLK = 0x2UL, /*!< PLL output clock */ + RCU_TRACECFG_CLKSEL_PLLDIVCLK = 0x3UL, /*!< PLL divided clock */ +} RCU_TRACECFG_CLKSEL_Enum; + +/*-- CLKOUTCFG: Clockout configuration register --------------------------------------------------------------*/ +typedef struct { + uint32_t CLKEN :1; /*!< Clock enable */ + uint32_t :7; /*!< RESERVED */ + uint32_t CLKSEL :2; /*!< Clock source select */ + uint32_t :6; /*!< RESERVED */ + uint32_t DIVEN :1; /*!< Enable divider */ + uint32_t :7; /*!< RESERVED */ + uint32_t DIVN :3; /*!< Divider coefficient */ +} _RCU_CLKOUTCFG_bits; + +/* Bit field positions: */ +#define RCU_CLKOUTCFG_CLKEN_Pos 0 /*!< Clock enable */ +#define RCU_CLKOUTCFG_CLKSEL_Pos 8 /*!< Clock source select */ +#define RCU_CLKOUTCFG_DIVEN_Pos 16 /*!< Enable divider */ +#define RCU_CLKOUTCFG_DIVN_Pos 24 /*!< Divider coefficient */ + +/* Bit field masks: */ +#define RCU_CLKOUTCFG_CLKEN_Msk 0x00000001UL /*!< Clock enable */ +#define RCU_CLKOUTCFG_CLKSEL_Msk 0x00000300UL /*!< Clock source select */ +#define RCU_CLKOUTCFG_DIVEN_Msk 0x00010000UL /*!< Enable divider */ +#define RCU_CLKOUTCFG_DIVN_Msk 0x07000000UL /*!< Divider coefficient */ + +/* Bit field enums: */ +typedef enum { + RCU_CLKOUTCFG_CLKSEL_OSICLK = 0x0UL, /*!< internal oscillator */ + RCU_CLKOUTCFG_CLKSEL_OSECLK = 0x1UL, /*!< external oscillator */ + RCU_CLKOUTCFG_CLKSEL_PLLCLK = 0x2UL, /*!< PLL output clock */ + RCU_CLKOUTCFG_CLKSEL_PLLDIVCLK = 0x3UL, /*!< PLL divided clock */ +} RCU_CLKOUTCFG_CLKSEL_Enum; + +/*-- WDTCFG: WatchDog configuration register -----------------------------------------------------------------*/ +typedef struct { + uint32_t CLKEN :1; /*!< Clock enable */ + uint32_t :3; /*!< RESERVED */ + uint32_t RSTDIS :1; /*!< Reset disable */ + uint32_t :3; /*!< RESERVED */ + uint32_t CLKSEL :2; /*!< Clock source select */ + uint32_t :6; /*!< RESERVED */ + uint32_t DIVEN :1; /*!< Enable divider */ + uint32_t :7; /*!< RESERVED */ + uint32_t DIVN :6; /*!< Divider coefficient */ +} _RCU_WDTCFG_bits; + +/* Bit field positions: */ +#define RCU_WDTCFG_CLKEN_Pos 0 /*!< Clock enable */ +#define RCU_WDTCFG_RSTDIS_Pos 4 /*!< Reset disable */ +#define RCU_WDTCFG_CLKSEL_Pos 8 /*!< Clock source select */ +#define RCU_WDTCFG_DIVEN_Pos 16 /*!< Enable divider */ +#define RCU_WDTCFG_DIVN_Pos 24 /*!< Divider coefficient */ + +/* Bit field masks: */ +#define RCU_WDTCFG_CLKEN_Msk 0x00000001UL /*!< Clock enable */ +#define RCU_WDTCFG_RSTDIS_Msk 0x00000010UL /*!< Reset disable */ +#define RCU_WDTCFG_CLKSEL_Msk 0x00000300UL /*!< Clock source select */ +#define RCU_WDTCFG_DIVEN_Msk 0x00010000UL /*!< Enable divider */ +#define RCU_WDTCFG_DIVN_Msk 0x3F000000UL /*!< Divider coefficient */ + +/* Bit field enums: */ +typedef enum { + RCU_WDTCFG_CLKSEL_OSICLK = 0x0UL, /*!< internal oscillator */ + RCU_WDTCFG_CLKSEL_OSECLK = 0x1UL, /*!< external oscillator */ + RCU_WDTCFG_CLKSEL_PLLCLK = 0x2UL, /*!< PLL output clock */ + RCU_WDTCFG_CLKSEL_PLLDIVCLK = 0x3UL, /*!< PLL divided clock */ +} RCU_WDTCFG_CLKSEL_Enum; + +/*-- UARTCFG: UARTCFG: UART clock and reset configuration register --------------------------------------------*/ +typedef struct { + uint32_t CLKEN :1; /*!< Clock enable */ + uint32_t :3; /*!< RESERVED */ + uint32_t RSTDIS :1; /*!< Reset disable */ + uint32_t :3; /*!< RESERVED */ + uint32_t CLKSEL :2; /*!< Clock source select */ + uint32_t :6; /*!< RESERVED */ + uint32_t DIVEN :1; /*!< Enable divider */ + uint32_t :7; /*!< RESERVED */ + uint32_t DIVN :6; /*!< Divider coefficient */ +} _RCU_UARTCFG_UARTCFG_bits; + +/* Bit field positions: */ +#define RCU_UARTCFG_UARTCFG_CLKEN_Pos 0 /*!< Clock enable */ +#define RCU_UARTCFG_UARTCFG_RSTDIS_Pos 4 /*!< Reset disable */ +#define RCU_UARTCFG_UARTCFG_CLKSEL_Pos 8 /*!< Clock source select */ +#define RCU_UARTCFG_UARTCFG_DIVEN_Pos 16 /*!< Enable divider */ +#define RCU_UARTCFG_UARTCFG_DIVN_Pos 24 /*!< Divider coefficient */ + +/* Bit field masks: */ +#define RCU_UARTCFG_UARTCFG_CLKEN_Msk 0x00000001UL /*!< Clock enable */ +#define RCU_UARTCFG_UARTCFG_RSTDIS_Msk 0x00000010UL /*!< Reset disable */ +#define RCU_UARTCFG_UARTCFG_CLKSEL_Msk 0x00000300UL /*!< Clock source select */ +#define RCU_UARTCFG_UARTCFG_DIVEN_Msk 0x00010000UL /*!< Enable divider */ +#define RCU_UARTCFG_UARTCFG_DIVN_Msk 0x3F000000UL /*!< Divider coefficient */ + +/* Bit field enums: */ +typedef enum { + RCU_UARTCFG_UARTCFG_CLKSEL_OSECLK = 0x0UL, /*!< external oscillator */ + RCU_UARTCFG_UARTCFG_CLKSEL_PLLCLK = 0x1UL, /*!< PLL output clock */ + RCU_UARTCFG_UARTCFG_CLKSEL_PLLDIVCLK = 0x2UL, /*!< PLL divided clock */ + RCU_UARTCFG_UARTCFG_CLKSEL_OSICLK = 0x3UL, /*!< internal oscillator */ +} RCU_UARTCFG_UARTCFG_CLKSEL_Enum; + +/*-- SPICFG: SPI clock and reset configuration register ------------------------------------------------------*/ +typedef struct { + uint32_t CLKEN :1; /*!< Clock enable */ + uint32_t :3; /*!< RESERVED */ + uint32_t RSTDIS :1; /*!< Reset disable */ + uint32_t :3; /*!< RESERVED */ + uint32_t CLKSEL :2; /*!< Clock source select */ + uint32_t :6; /*!< RESERVED */ + uint32_t DIVEN :1; /*!< Enable divider */ + uint32_t :7; /*!< RESERVED */ + uint32_t DIVN :6; /*!< Divider coefficient */ +} _RCU_SPICFG_bits; + +/* Bit field positions: */ +#define RCU_SPICFG_CLKEN_Pos 0 /*!< Clock enable */ +#define RCU_SPICFG_RSTDIS_Pos 4 /*!< Reset disable */ +#define RCU_SPICFG_CLKSEL_Pos 8 /*!< Clock source select */ +#define RCU_SPICFG_DIVEN_Pos 16 /*!< Enable divider */ +#define RCU_SPICFG_DIVN_Pos 24 /*!< Divider coefficient */ + +/* Bit field masks: */ +#define RCU_SPICFG_CLKEN_Msk 0x00000001UL /*!< Clock enable */ +#define RCU_SPICFG_RSTDIS_Msk 0x00000010UL /*!< Reset disable */ +#define RCU_SPICFG_CLKSEL_Msk 0x00000300UL /*!< Clock source select */ +#define RCU_SPICFG_DIVEN_Msk 0x00010000UL /*!< Enable divider */ +#define RCU_SPICFG_DIVN_Msk 0x3F000000UL /*!< Divider coefficient */ + +/* Bit field enums: */ +typedef enum { + RCU_SPICFG_CLKSEL_OSECLK = 0x0UL, /*!< external oscillator */ + RCU_SPICFG_CLKSEL_PLLCLK = 0x1UL, /*!< PLL output clock */ + RCU_SPICFG_CLKSEL_PLLDIVCLK = 0x2UL, /*!< PLL divided clock */ + RCU_SPICFG_CLKSEL_OSICLK = 0x3UL, /*!< internal oscillator */ +} RCU_SPICFG_CLKSEL_Enum; + +/*-- ADCCFG: ADC clock and reset configuration register ------------------------------------------------------*/ +typedef struct { + uint32_t CLKEN :1; /*!< Clock enable */ + uint32_t :3; /*!< RESERVED */ + uint32_t RSTDIS :1; /*!< Reset disable */ + uint32_t :3; /*!< RESERVED */ + uint32_t CLKSEL :2; /*!< Clock source select */ + uint32_t :6; /*!< RESERVED */ + uint32_t DIVEN :1; /*!< Enable divider */ + uint32_t :7; /*!< RESERVED */ + uint32_t DIVN :6; /*!< Divider coefficient */ +} _RCU_ADCCFG_bits; + +/* Bit field positions: */ +#define RCU_ADCCFG_CLKEN_Pos 0 /*!< Clock enable */ +#define RCU_ADCCFG_RSTDIS_Pos 4 /*!< Reset disable */ +#define RCU_ADCCFG_CLKSEL_Pos 8 /*!< Clock source select */ +#define RCU_ADCCFG_DIVEN_Pos 16 /*!< Enable divider */ +#define RCU_ADCCFG_DIVN_Pos 24 /*!< Divider coefficient */ + +/* Bit field masks: */ +#define RCU_ADCCFG_CLKEN_Msk 0x00000001UL /*!< Clock enable */ +#define RCU_ADCCFG_RSTDIS_Msk 0x00000010UL /*!< Reset disable */ +#define RCU_ADCCFG_CLKSEL_Msk 0x00000300UL /*!< Clock source select */ +#define RCU_ADCCFG_DIVEN_Msk 0x00010000UL /*!< Enable divider */ +#define RCU_ADCCFG_DIVN_Msk 0x3F000000UL /*!< Divider coefficient */ + +/* Bit field enums: */ +typedef enum { + RCU_ADCCFG_CLKSEL_OSECLK = 0x0UL, /*!< external oscillator */ + RCU_ADCCFG_CLKSEL_PLLCLK = 0x1UL, /*!< PLL output clock */ + RCU_ADCCFG_CLKSEL_PLLDIVCLK = 0x2UL, /*!< PLL divided clock */ + RCU_ADCCFG_CLKSEL_OSICLK = 0x3UL, /*!< internal oscillator */ +} RCU_ADCCFG_CLKSEL_Enum; + +/*-- PCLKCFG: APB clock configuration register ---------------------------------------------------------------*/ +typedef struct { + uint32_t TMR0EN :1; /*!< Enable clock for TMR0 */ + uint32_t TMR1EN :1; /*!< Enable clock for TMR1 */ + uint32_t TMR2EN :1; /*!< Enable clock for TMR2 */ + uint32_t TMR3EN :1; /*!< Enable clock for TMR3 */ + uint32_t PWM0EN :1; /*!< Enable clock for PWM0 */ + uint32_t PWM1EN :1; /*!< Enable clock for PWM1 */ + uint32_t PWM2EN :1; /*!< Enable clock for PWM2 */ + uint32_t I2CEN :1; /*!< Enable clock for I2C */ + uint32_t QEPEN :1; /*!< Enable clock for QEP */ + uint32_t ECAP0EN :1; /*!< Enable clock for ECAP0 */ + uint32_t ECAP1EN :1; /*!< Enable clock for ECAP1 */ + uint32_t ECAP2EN :1; /*!< Enable clock for ECAP2 */ +} _RCU_PCLKCFG_bits; + +/* Bit field positions: */ +#define RCU_PCLKCFG_TMR0EN_Pos 0 /*!< Enable clock for TMR0 */ +#define RCU_PCLKCFG_TMR1EN_Pos 1 /*!< Enable clock for TMR1 */ +#define RCU_PCLKCFG_TMR2EN_Pos 2 /*!< Enable clock for TMR2 */ +#define RCU_PCLKCFG_TMR3EN_Pos 3 /*!< Enable clock for TMR3 */ +#define RCU_PCLKCFG_PWM0EN_Pos 4 /*!< Enable clock for PWM0 */ +#define RCU_PCLKCFG_PWM1EN_Pos 5 /*!< Enable clock for PWM1 */ +#define RCU_PCLKCFG_PWM2EN_Pos 6 /*!< Enable clock for PWM2 */ +#define RCU_PCLKCFG_I2CEN_Pos 7 /*!< Enable clock for I2C */ +#define RCU_PCLKCFG_QEPEN_Pos 8 /*!< Enable clock for QEP */ +#define RCU_PCLKCFG_ECAP0EN_Pos 9 /*!< Enable clock for ECAP0 */ +#define RCU_PCLKCFG_ECAP1EN_Pos 10 /*!< Enable clock for ECAP1 */ +#define RCU_PCLKCFG_ECAP2EN_Pos 11 /*!< Enable clock for ECAP2 */ + +/* Bit field masks: */ +#define RCU_PCLKCFG_TMR0EN_Msk 0x00000001UL /*!< Enable clock for TMR0 */ +#define RCU_PCLKCFG_TMR1EN_Msk 0x00000002UL /*!< Enable clock for TMR1 */ +#define RCU_PCLKCFG_TMR2EN_Msk 0x00000004UL /*!< Enable clock for TMR2 */ +#define RCU_PCLKCFG_TMR3EN_Msk 0x00000008UL /*!< Enable clock for TMR3 */ +#define RCU_PCLKCFG_PWM0EN_Msk 0x00000010UL /*!< Enable clock for PWM0 */ +#define RCU_PCLKCFG_PWM1EN_Msk 0x00000020UL /*!< Enable clock for PWM1 */ +#define RCU_PCLKCFG_PWM2EN_Msk 0x00000040UL /*!< Enable clock for PWM2 */ +#define RCU_PCLKCFG_I2CEN_Msk 0x00000080UL /*!< Enable clock for I2C */ +#define RCU_PCLKCFG_QEPEN_Msk 0x00000100UL /*!< Enable clock for QEP */ +#define RCU_PCLKCFG_ECAP0EN_Msk 0x00000200UL /*!< Enable clock for ECAP0 */ +#define RCU_PCLKCFG_ECAP1EN_Msk 0x00000400UL /*!< Enable clock for ECAP1 */ +#define RCU_PCLKCFG_ECAP2EN_Msk 0x00000800UL /*!< Enable clock for ECAP2 */ + +/*-- PRSTCFG: APB reset configuration register ---------------------------------------------------------------*/ +typedef struct { + uint32_t TMR0EN :1; /*!< Disable reset from TMR0 */ + uint32_t TMR1EN :1; /*!< Disable reset from TMR1 */ + uint32_t TMR2EN :1; /*!< Disable reset from TMR2 */ + uint32_t TMR3EN :1; /*!< Disable reset from TMR3 */ + uint32_t PWM0EN :1; /*!< Disable reset from PWM0 */ + uint32_t PWM1EN :1; /*!< Disable reset from PWM1 */ + uint32_t PWM2EN :1; /*!< Disable reset from PWM2 */ + uint32_t I2CEN :1; /*!< Disable reset from I2C */ + uint32_t QEPEN :1; /*!< Disable reset from QEP */ + uint32_t ECAP0EN :1; /*!< Disable reset from ECAP0 */ + uint32_t ECAP1EN :1; /*!< Disable reset from ECAP1 */ + uint32_t ECAP2EN :1; /*!< Disable reset from ECAP2 */ +} _RCU_PRSTCFG_bits; + +/* Bit field positions: */ +#define RCU_PRSTCFG_TMR0EN_Pos 0 /*!< Disable reset from TMR0 */ +#define RCU_PRSTCFG_TMR1EN_Pos 1 /*!< Disable reset from TMR1 */ +#define RCU_PRSTCFG_TMR2EN_Pos 2 /*!< Disable reset from TMR2 */ +#define RCU_PRSTCFG_TMR3EN_Pos 3 /*!< Disable reset from TMR3 */ +#define RCU_PRSTCFG_PWM0EN_Pos 4 /*!< Disable reset from PWM0 */ +#define RCU_PRSTCFG_PWM1EN_Pos 5 /*!< Disable reset from PWM1 */ +#define RCU_PRSTCFG_PWM2EN_Pos 6 /*!< Disable reset from PWM2 */ +#define RCU_PRSTCFG_I2CEN_Pos 7 /*!< Disable reset from I2C */ +#define RCU_PRSTCFG_QEPEN_Pos 8 /*!< Disable reset from QEP */ +#define RCU_PRSTCFG_ECAP0EN_Pos 9 /*!< Disable reset from ECAP0 */ +#define RCU_PRSTCFG_ECAP1EN_Pos 10 /*!< Disable reset from ECAP1 */ +#define RCU_PRSTCFG_ECAP2EN_Pos 11 /*!< Disable reset from ECAP2 */ + +/* Bit field masks: */ +#define RCU_PRSTCFG_TMR0EN_Msk 0x00000001UL /*!< Disable reset from TMR0 */ +#define RCU_PRSTCFG_TMR1EN_Msk 0x00000002UL /*!< Disable reset from TMR1 */ +#define RCU_PRSTCFG_TMR2EN_Msk 0x00000004UL /*!< Disable reset from TMR2 */ +#define RCU_PRSTCFG_TMR3EN_Msk 0x00000008UL /*!< Disable reset from TMR3 */ +#define RCU_PRSTCFG_PWM0EN_Msk 0x00000010UL /*!< Disable reset from PWM0 */ +#define RCU_PRSTCFG_PWM1EN_Msk 0x00000020UL /*!< Disable reset from PWM1 */ +#define RCU_PRSTCFG_PWM2EN_Msk 0x00000040UL /*!< Disable reset from PWM2 */ +#define RCU_PRSTCFG_I2CEN_Msk 0x00000080UL /*!< Disable reset from I2C */ +#define RCU_PRSTCFG_QEPEN_Msk 0x00000100UL /*!< Disable reset from QEP */ +#define RCU_PRSTCFG_ECAP0EN_Msk 0x00000200UL /*!< Disable reset from ECAP0 */ +#define RCU_PRSTCFG_ECAP1EN_Msk 0x00000400UL /*!< Disable reset from ECAP1 */ +#define RCU_PRSTCFG_ECAP2EN_Msk 0x00000800UL /*!< Disable reset from ECAP2 */ + +/*-- HCLKCFG: AHB clock configuration register ---------------------------------------------------------------*/ +typedef struct { + uint32_t GPIOAEN :1; /*!< Enable clock for GPIOA port */ + uint32_t GPIOBEN :1; /*!< Enable clock for GPIOB port */ + uint32_t CANEN :1; /*!< Enable clock for CAN */ +} _RCU_HCLKCFG_bits; + +/* Bit field positions: */ +#define RCU_HCLKCFG_GPIOAEN_Pos 0 /*!< Enable clock for GPIOA port */ +#define RCU_HCLKCFG_GPIOBEN_Pos 1 /*!< Enable clock for GPIOB port */ +#define RCU_HCLKCFG_CANEN_Pos 2 /*!< Enable clock for CAN */ + +/* Bit field masks: */ +#define RCU_HCLKCFG_GPIOAEN_Msk 0x00000001UL /*!< Enable clock for GPIOA port */ +#define RCU_HCLKCFG_GPIOBEN_Msk 0x00000002UL /*!< Enable clock for GPIOB port */ +#define RCU_HCLKCFG_CANEN_Msk 0x00000004UL /*!< Enable clock for CAN */ + +/*-- HRSTCFG: AHB reset configuration register ---------------------------------------------------------------*/ +typedef struct { + uint32_t GPIOAEN :1; /*!< Disable reset from GPIOA port */ + uint32_t GPIOBEN :1; /*!< Disable reset from GPIOB port */ + uint32_t CANEN :1; /*!< Disable reset from CAN */ +} _RCU_HRSTCFG_bits; + +/* Bit field positions: */ +#define RCU_HRSTCFG_GPIOAEN_Pos 0 /*!< Disable reset from GPIOA port */ +#define RCU_HRSTCFG_GPIOBEN_Pos 1 /*!< Disable reset from GPIOB port */ +#define RCU_HRSTCFG_CANEN_Pos 2 /*!< Disable reset from CAN */ + +/* Bit field masks: */ +#define RCU_HRSTCFG_GPIOAEN_Msk 0x00000001UL /*!< Disable reset from GPIOA port */ +#define RCU_HRSTCFG_GPIOBEN_Msk 0x00000002UL /*!< Disable reset from GPIOB port */ +#define RCU_HRSTCFG_CANEN_Msk 0x00000004UL /*!< Disable reset from CAN */ + +//Cluster UARTCFG: +typedef struct { + union { + /*!< UART clock and reset configuration register */ + __IO uint32_t UARTCFG; /*!< UARTCFG : type used for word access */ + __IO _RCU_UARTCFG_UARTCFG_bits UARTCFG_bit; /*!< UARTCFG_bit: structure used for bit access */ + }; +} _RCU_UARTCFG_TypeDef; +typedef struct { + union { /*!< Internal oscillator configuration register */ + __IO uint32_t OSICFG; /*!< OSICFG : type used for word access */ + __IO _RCU_OSICFG_bits OSICFG_bit; /*!< OSICFG_bit: structure used for bit access */ + }; + union { /*!< External oscillator configuration register */ + __IO uint32_t OSECFG; /*!< OSECFG : type used for word access */ + __IO _RCU_OSECFG_bits OSECFG_bit; /*!< OSECFG_bit: structure used for bit access */ + }; + union { /*!< PLL configuration register */ + __IO uint32_t PLLCFG; /*!< PLLCFG : type used for word access */ + __IO _RCU_PLLCFG_bits PLLCFG_bit; /*!< PLLCFG_bit: structure used for bit access */ + }; + union { /*!< PLL divider register */ + __IO uint32_t PLLDIV; /*!< PLLDIV : type used for word access */ + __IO _RCU_PLLDIV_bits PLLDIV_bit; /*!< PLLDIV_bit: structure used for bit access */ + }; + union { /*!< System clock configuration register */ + __IO uint32_t SYSCLKCFG; /*!< SYSCLKCFG : type used for word access */ + __IO _RCU_SYSCLKCFG_bits SYSCLKCFG_bit; /*!< SYSCLKCFG_bit: structure used for bit access */ + }; + union { /*!< System clock status register */ + __I uint32_t SYSCLKSTAT; /*!< SYSCLKSTAT : type used for word access */ + __I _RCU_SYSCLKSTAT_bits SYSCLKSTAT_bit; /*!< SYSCLKSTAT_bit: structure used for bit access */ + }; + union { /*!< Security sysytem clock period register */ + __IO uint32_t SECPRD; /*!< SECPRD : type used for word access */ + __IO _RCU_SECPRD_bits SECPRD_bit; /*!< SECPRD_bit: structure used for bit access */ + }; + union { /*!< System reset configuration register */ + __IO uint32_t SYSRSTCFG; /*!< SYSRSTCFG : type used for word access */ + __IO _RCU_SYSRSTCFG_bits SYSRSTCFG_bit; /*!< SYSRSTCFG_bit: structure used for bit access */ + }; + union { /*!< Reset status register */ + __IO uint32_t SYSRSTSTAT; /*!< SYSRSTSTAT : type used for word access */ + __IO _RCU_SYSRSTSTAT_bits SYSRSTSTAT_bit; /*!< SYSRSTSTAT_bit: structure used for bit access */ + }; + union { /*!< Interrupt enable register */ + __IO uint32_t INTEN; /*!< INTEN : type used for word access */ + __IO _RCU_INTEN_bits INTEN_bit; /*!< INTEN_bit: structure used for bit access */ + }; + union { /*!< Interrupt status register */ + __IO uint32_t INTSTAT; /*!< INTSTAT : type used for word access */ + __IO _RCU_INTSTAT_bits INTSTAT_bit; /*!< INTSTAT_bit: structure used for bit access */ + }; + union { /*!< Trace clock configuration register */ + __IO uint32_t TRACECFG; /*!< TRACECFG : type used for word access */ + __IO _RCU_TRACECFG_bits TRACECFG_bit; /*!< TRACECFG_bit: structure used for bit access */ + }; + union { /*!< Clockout configuration register */ + __IO uint32_t CLKOUTCFG; /*!< CLKOUTCFG : type used for word access */ + __IO _RCU_CLKOUTCFG_bits CLKOUTCFG_bit; /*!< CLKOUTCFG_bit: structure used for bit access */ + }; + union { /*!< WatchDog configuration register */ + __IO uint32_t WDTCFG; /*!< WDTCFG : type used for word access */ + __IO _RCU_WDTCFG_bits WDTCFG_bit; /*!< WDTCFG_bit: structure used for bit access */ + }; + __IO uint32_t Reserved0[10]; + _RCU_UARTCFG_TypeDef UARTCFG[2]; + __IO uint32_t Reserved1[6]; + union { /*!< SPI clock and reset configuration register */ + __IO uint32_t SPICFG; /*!< SPICFG : type used for word access */ + __IO _RCU_SPICFG_bits SPICFG_bit; /*!< SPICFG_bit: structure used for bit access */ + }; + __IO uint32_t Reserved2[7]; + union { /*!< ADC clock and reset configuration register */ + __IO uint32_t ADCCFG; /*!< ADCCFG : type used for word access */ + __IO _RCU_ADCCFG_bits ADCCFG_bit; /*!< ADCCFG_bit: structure used for bit access */ + }; + __IO uint32_t Reserved3[15]; + union { /*!< APB clock configuration register */ + __IO uint32_t PCLKCFG; /*!< PCLKCFG : type used for word access */ + __IO _RCU_PCLKCFG_bits PCLKCFG_bit; /*!< PCLKCFG_bit: structure used for bit access */ + }; + __IO uint32_t Reserved4[3]; + union { /*!< APB reset configuration register */ + __IO uint32_t PRSTCFG; /*!< PRSTCFG : type used for word access */ + __IO _RCU_PRSTCFG_bits PRSTCFG_bit; /*!< PRSTCFG_bit: structure used for bit access */ + }; + __IO uint32_t Reserved5[3]; + union { /*!< AHB clock configuration register */ + __IO uint32_t HCLKCFG; /*!< HCLKCFG : type used for word access */ + __IO _RCU_HCLKCFG_bits HCLKCFG_bit; /*!< HCLKCFG_bit: structure used for bit access */ + }; + union { /*!< AHB reset configuration register */ + __IO uint32_t HRSTCFG; /*!< HRSTCFG : type used for word access */ + __IO _RCU_HRSTCFG_bits HRSTCFG_bit; /*!< HRSTCFG_bit: structure used for bit access */ + }; +} RCU_TypeDef; + + +/******************************************************************************/ +/* PMU registers */ +/******************************************************************************/ + +/*-- CFG: PMU Configuration Register -------------------------------------------------------------------------*/ +typedef struct { + uint32_t EN :1; /*!< Enable PMU */ +} _PMU_CFG_bits; + +/* Bit field positions: */ +#define PMU_CFG_EN_Pos 0 /*!< Enable PMU */ + +/* Bit field masks: */ +#define PMU_CFG_EN_Msk 0x00000001UL /*!< Enable PMU */ + +/*-- PUDEL: PMU Powerup Delay Value --------------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :16; /*!< Delay value for powerup peripheral blocks (in OSICLK ticks) */ +} _PMU_PUDEL_bits; + +/* Bit field positions: */ +#define PMU_PUDEL_VAL_Pos 0 /*!< Delay value for powerup peripheral blocks (in OSICLK ticks) */ + +/* Bit field masks: */ +#define PMU_PUDEL_VAL_Msk 0x0000FFFFUL /*!< Delay value for powerup peripheral blocks (in OSICLK ticks) */ + +/*-- PDEN: PMU Enable Powerdown for peripheral ---------------------------------------------------------------*/ +typedef struct { + uint32_t PLLPD :1; /*!< Enable powerdown for PLL */ + uint32_t MFLASHPD :1; /*!< Enable powerdown for MFLASH */ + uint32_t OSEPD :1; /*!< Enable powerdown for external oscillator */ +} _PMU_PDEN_bits; + +/* Bit field positions: */ +#define PMU_PDEN_PLLPD_Pos 0 /*!< Enable powerdown for PLL */ +#define PMU_PDEN_MFLASHPD_Pos 1 /*!< Enable powerdown for MFLASH */ +#define PMU_PDEN_OSEPD_Pos 2 /*!< Enable powerdown for external oscillator */ + +/* Bit field masks: */ +#define PMU_PDEN_PLLPD_Msk 0x00000001UL /*!< Enable powerdown for PLL */ +#define PMU_PDEN_MFLASHPD_Msk 0x00000002UL /*!< Enable powerdown for MFLASH */ +#define PMU_PDEN_OSEPD_Msk 0x00000004UL /*!< Enable powerdown for external oscillator */ + +/*-- RXEVEN: PMU RX Event generation enable register ---------------------------------------------------------*/ +typedef struct { + uint32_t GPIOAEV :1; /*!< Enable RX event from GPIOA pins */ + uint32_t GPIOBEV :1; /*!< Enable RX event from GPIOB pins */ +} _PMU_RXEVEN_bits; + +/* Bit field positions: */ +#define PMU_RXEVEN_GPIOAEV_Pos 0 /*!< Enable RX event from GPIOA pins */ +#define PMU_RXEVEN_GPIOBEV_Pos 1 /*!< Enable RX event from GPIOB pins */ + +/* Bit field masks: */ +#define PMU_RXEVEN_GPIOAEV_Msk 0x00000001UL /*!< Enable RX event from GPIOA pins */ +#define PMU_RXEVEN_GPIOBEV_Msk 0x00000002UL /*!< Enable RX event from GPIOB pins */ + +typedef struct { + union { /*!< PMU Configuration Register */ + __IO uint32_t CFG; /*!< CFG : type used for word access */ + __IO _PMU_CFG_bits CFG_bit; /*!< CFG_bit: structure used for bit access */ + }; + union { /*!< PMU Powerup Delay Value */ + __IO uint32_t PUDEL; /*!< PUDEL : type used for word access */ + __IO _PMU_PUDEL_bits PUDEL_bit; /*!< PUDEL_bit: structure used for bit access */ + }; + union { /*!< PMU Enable Powerdown for peripheral */ + __IO uint32_t PDEN; /*!< PDEN : type used for word access */ + __IO _PMU_PDEN_bits PDEN_bit; /*!< PDEN_bit: structure used for bit access */ + }; + union { /*!< PMU RX Event generation enable register */ + __IO uint32_t RXEVEN; /*!< RXEVEN : type used for word access */ + __IO _PMU_RXEVEN_bits RXEVEN_bit; /*!< RXEVEN_bit: structure used for bit access */ + }; +} PMU_TypeDef; + + +/******************************************************************************/ +/* WDT registers */ +/******************************************************************************/ + +/*-- LOAD: Watchdog Load Register ----------------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< Begin value counter */ +} _WDT_LOAD_bits; + +/* Bit field positions: */ +#define WDT_LOAD_VAL_Pos 0 /*!< Begin value counter */ + +/* Bit field masks: */ +#define WDT_LOAD_VAL_Msk 0xFFFFFFFFUL /*!< Begin value counter */ + +/*-- VALUE: Watchdog Value Register --------------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< Current value counter */ +} _WDT_VALUE_bits; + +/* Bit field positions: */ +#define WDT_VALUE_VAL_Pos 0 /*!< Current value counter */ + +/* Bit field masks: */ +#define WDT_VALUE_VAL_Msk 0xFFFFFFFFUL /*!< Current value counter */ + +/*-- CTRL: Watchdog Control Register -------------------------------------------------------------------------*/ +typedef struct { + uint32_t INTEN :1; /*!< Enable the interrupt event */ + uint32_t RESEN :1; /*!< Enable watchdog reset output */ +} _WDT_CTRL_bits; + +/* Bit field positions: */ +#define WDT_CTRL_INTEN_Pos 0 /*!< Enable the interrupt event */ +#define WDT_CTRL_RESEN_Pos 1 /*!< Enable watchdog reset output */ + +/* Bit field masks: */ +#define WDT_CTRL_INTEN_Msk 0x00000001UL /*!< Enable the interrupt event */ +#define WDT_CTRL_RESEN_Msk 0x00000002UL /*!< Enable watchdog reset output */ + +/*-- INTCLR: Watchdog Clear Interrupt Register ---------------------------------------------------------------*/ +typedef struct { + uint32_t WDTCLR :32; /*!< Reset interrupt WDT */ +} _WDT_INTCLR_bits; + +/* Bit field positions: */ +#define WDT_INTCLR_WDTCLR_Pos 0 /*!< Reset interrupt WDT */ + +/* Bit field masks: */ +#define WDT_INTCLR_WDTCLR_Msk 0xFFFFFFFFUL /*!< Reset interrupt WDT */ + +/*-- RIS: Watchdog Raw Interrupt Status Register -------------------------------------------------------------*/ +typedef struct { + uint32_t RAWWDTINT :1; /*!< Raw interrupt status from the counter */ +} _WDT_RIS_bits; + +/* Bit field positions: */ +#define WDT_RIS_RAWWDTINT_Pos 0 /*!< Raw interrupt status from the counter */ + +/* Bit field masks: */ +#define WDT_RIS_RAWWDTINT_Msk 0x00000001UL /*!< Raw interrupt status from the counter */ + +/*-- MIS: Watchdog Interrupt Status Register -----------------------------------------------------------------*/ +typedef struct { + uint32_t WDTINT :1; /*!< Enabled interrupt status from the counter */ +} _WDT_MIS_bits; + +/* Bit field positions: */ +#define WDT_MIS_WDTINT_Pos 0 /*!< Enabled interrupt status from the counter */ + +/* Bit field masks: */ +#define WDT_MIS_WDTINT_Msk 0x00000001UL /*!< Enabled interrupt status from the counter */ + +/*-- LOCK: Watchdog Lock Register ----------------------------------------------------------------------------*/ +typedef struct { + uint32_t REGWRDIS :1; /*!< Disable write to all registers Watchdog */ +} _WDT_LOCK_bits; + +/* Bit field positions: */ +#define WDT_LOCK_REGWRDIS_Pos 0 /*!< Disable write to all registers Watchdog */ + +/* Bit field masks: */ +#define WDT_LOCK_REGWRDIS_Msk 0x00000001UL /*!< Disable write to all registers Watchdog */ + +typedef struct { + union { /*!< Watchdog Load Register */ + __IO uint32_t LOAD; /*!< LOAD : type used for word access */ + __IO _WDT_LOAD_bits LOAD_bit; /*!< LOAD_bit: structure used for bit access */ + }; + union { /*!< Watchdog Value Register */ + __I uint32_t VALUE; /*!< VALUE : type used for word access */ + __I _WDT_VALUE_bits VALUE_bit; /*!< VALUE_bit: structure used for bit access */ + }; + union { /*!< Watchdog Control Register */ + __IO uint32_t CTRL; /*!< CTRL : type used for word access */ + __IO _WDT_CTRL_bits CTRL_bit; /*!< CTRL_bit: structure used for bit access */ + }; + union { /*!< Watchdog Clear Interrupt Register */ + __O uint32_t INTCLR; /*!< INTCLR : type used for word access */ + __O _WDT_INTCLR_bits INTCLR_bit; /*!< INTCLR_bit: structure used for bit access */ + }; + union { /*!< Watchdog Raw Interrupt Status Register */ + __I uint32_t RIS; /*!< RIS : type used for word access */ + __I _WDT_RIS_bits RIS_bit; /*!< RIS_bit: structure used for bit access */ + }; + union { /*!< Watchdog Interrupt Status Register */ + __I uint32_t MIS; /*!< MIS : type used for word access */ + __I _WDT_MIS_bits MIS_bit; /*!< MIS_bit: structure used for bit access */ + }; + __IO uint32_t Reserved0[762]; + union { /*!< Watchdog Lock Register */ + __O uint32_t LOCK; /*!< LOCK : type used for word access */ + __O _WDT_LOCK_bits LOCK_bit; /*!< LOCK_bit: structure used for bit access */ + }; +} WDT_TypeDef; + + +/******************************************************************************/ +/* TMR registers */ +/******************************************************************************/ + +/*-- CTRL: Control Timer register ----------------------------------------------------------------------------*/ +typedef struct { + uint32_t ON :1; /*!< Enable Timer */ + uint32_t EXTINEN :1; /*!< Enable external input as ENABLE */ + uint32_t EXTINCLK :1; /*!< Enable external input as CLK */ + uint32_t INTEN :1; /*!< Enable Timer interrupt */ +} _TMR_CTRL_bits; + +/* Bit field positions: */ +#define TMR_CTRL_ON_Pos 0 /*!< Enable Timer */ +#define TMR_CTRL_EXTINEN_Pos 1 /*!< Enable external input as ENABLE */ +#define TMR_CTRL_EXTINCLK_Pos 2 /*!< Enable external input as CLK */ +#define TMR_CTRL_INTEN_Pos 3 /*!< Enable Timer interrupt */ + +/* Bit field masks: */ +#define TMR_CTRL_ON_Msk 0x00000001UL /*!< Enable Timer */ +#define TMR_CTRL_EXTINEN_Msk 0x00000002UL /*!< Enable external input as ENABLE */ +#define TMR_CTRL_EXTINCLK_Msk 0x00000004UL /*!< Enable external input as CLK */ +#define TMR_CTRL_INTEN_Msk 0x00000008UL /*!< Enable Timer interrupt */ + +/*-- VALUE: Current value timer register ---------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< Current value timer */ +} _TMR_VALUE_bits; + +/* Bit field positions: */ +#define TMR_VALUE_VAL_Pos 0 /*!< Current value timer */ + +/* Bit field masks: */ +#define TMR_VALUE_VAL_Msk 0xFFFFFFFFUL /*!< Current value timer */ + +/*-- LOAD: Reload value timer register -----------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< Reload value. A write to this register sets the current value */ +} _TMR_LOAD_bits; + +/* Bit field positions: */ +#define TMR_LOAD_VAL_Pos 0 /*!< Reload value. A write to this register sets the current value */ + +/* Bit field masks: */ +#define TMR_LOAD_VAL_Msk 0xFFFFFFFFUL /*!< Reload value. A write to this register sets the current value */ + +/*-- INTSTATUS: Interrupt status register --------------------------------------------------------------------*/ +typedef struct { + uint32_t INT :1; /*!< Timer interrupt flag */ +} _TMR_INTSTATUS_bits; + +/* Bit field positions: */ +#define TMR_INTSTATUS_INT_Pos 0 /*!< Timer interrupt flag */ + +/* Bit field masks: */ +#define TMR_INTSTATUS_INT_Msk 0x00000001UL /*!< Timer interrupt flag */ + +/*-- DMAREQ: DMA request register ----------------------------------------------------------------------------*/ +typedef struct { + uint32_t EN :1; /*!< */ +} _TMR_DMAREQ_bits; + +/* Bit field positions: */ +#define TMR_DMAREQ_EN_Pos 0 /*!< */ + +/* Bit field masks: */ +#define TMR_DMAREQ_EN_Msk 0x00000001UL /*!< */ + +/*-- ADCSOC: ADC start of conversion register ----------------------------------------------------------------*/ +typedef struct { + uint32_t EN :1; /*!< */ +} _TMR_ADCSOC_bits; + +/* Bit field positions: */ +#define TMR_ADCSOC_EN_Pos 0 /*!< */ + +/* Bit field masks: */ +#define TMR_ADCSOC_EN_Msk 0x00000001UL /*!< */ + +typedef struct { + union { /*!< Control Timer register */ + __IO uint32_t CTRL; /*!< CTRL : type used for word access */ + __IO _TMR_CTRL_bits CTRL_bit; /*!< CTRL_bit: structure used for bit access */ + }; + union { /*!< Current value timer register */ + __IO uint32_t VALUE; /*!< VALUE : type used for word access */ + __IO _TMR_VALUE_bits VALUE_bit; /*!< VALUE_bit: structure used for bit access */ + }; + union { /*!< Reload value timer register */ + __IO uint32_t LOAD; /*!< LOAD : type used for word access */ + __IO _TMR_LOAD_bits LOAD_bit; /*!< LOAD_bit: structure used for bit access */ + }; + union { /*!< Interrupt status register */ + __IO uint32_t INTSTATUS; /*!< INTSTATUS : type used for word access */ + __IO _TMR_INTSTATUS_bits INTSTATUS_bit; /*!< INTSTATUS_bit: structure used for bit access */ + }; + union { /*!< DMA request register */ + __IO uint32_t DMAREQ; /*!< DMAREQ : type used for word access */ + __IO _TMR_DMAREQ_bits DMAREQ_bit; /*!< DMAREQ_bit: structure used for bit access */ + }; + union { /*!< ADC start of conversion register */ + __IO uint32_t ADCSOC; /*!< ADCSOC : type used for word access */ + __IO _TMR_ADCSOC_bits ADCSOC_bit; /*!< ADCSOC_bit: structure used for bit access */ + }; +} TMR_TypeDef; + + +/******************************************************************************/ +/* ADC registers */ +/******************************************************************************/ + +/*-- SEQEN: Enable sequencer register ------------------------------------------------------------------------*/ +typedef struct { + uint32_t SEQEN0 :1; /*!< Enable sequencer 0 */ + uint32_t SEQEN1 :1; /*!< Enable sequencer 1 */ +} _ADC_SEQEN_bits; + +/* Bit field positions: */ +#define ADC_SEQEN_SEQEN0_Pos 0 /*!< Enable sequencer 0 */ +#define ADC_SEQEN_SEQEN1_Pos 1 /*!< Enable sequencer 1 */ + +/* Bit field masks: */ +#define ADC_SEQEN_SEQEN0_Msk 0x00000001UL /*!< Enable sequencer 0 */ +#define ADC_SEQEN_SEQEN1_Msk 0x00000002UL /*!< Enable sequencer 1 */ + +/*-- SEQSYNC: Sequencer sync register ------------------------------------------------------------------------*/ +typedef struct { + uint32_t SYNC0 :1; /*!< Enable sequencer 0 software sync */ + uint32_t SYNC1 :1; /*!< Enable sequencer 1 software sync */ + uint32_t :29; /*!< RESERVED */ + uint32_t GSYNC :1; /*!< Sync all sequencers */ +} _ADC_SEQSYNC_bits; + +/* Bit field positions: */ +#define ADC_SEQSYNC_SYNC0_Pos 0 /*!< Enable sequencer 0 software sync */ +#define ADC_SEQSYNC_SYNC1_Pos 1 /*!< Enable sequencer 1 software sync */ +#define ADC_SEQSYNC_GSYNC_Pos 31 /*!< Sync all sequencers */ + +/* Bit field masks: */ +#define ADC_SEQSYNC_SYNC0_Msk 0x00000001UL /*!< Enable sequencer 0 software sync */ +#define ADC_SEQSYNC_SYNC1_Msk 0x00000002UL /*!< Enable sequencer 1 software sync */ +#define ADC_SEQSYNC_GSYNC_Msk 0x80000000UL /*!< Sync all sequencers */ + +/*-- FSTAT: FIFO overflow status register --------------------------------------------------------------------*/ +typedef struct { + uint32_t OV0 :1; /*!< Sequencer 0 FIFO overflow */ + uint32_t OV1 :1; /*!< Sequencer 1 FIFO overflow */ + uint32_t :6; /*!< RESERVED */ + uint32_t UN0 :1; /*!< Sequencer 0 FIFO underflow */ + uint32_t UN1 :1; /*!< Sequencer 1 FIFO underflow */ + uint32_t :6; /*!< RESERVED */ + uint32_t DOV0 :1; /*!< Sequencer 0 FIFO DMA request overflow */ + uint32_t DOV1 :1; /*!< Sequencer 1 FIFO DMA request overflow */ +} _ADC_FSTAT_bits; + +/* Bit field positions: */ +#define ADC_FSTAT_OV0_Pos 0 /*!< Sequencer 0 FIFO overflow */ +#define ADC_FSTAT_OV1_Pos 1 /*!< Sequencer 1 FIFO overflow */ +#define ADC_FSTAT_UN0_Pos 8 /*!< Sequencer 0 FIFO underflow */ +#define ADC_FSTAT_UN1_Pos 9 /*!< Sequencer 1 FIFO underflow */ +#define ADC_FSTAT_DOV0_Pos 16 /*!< Sequencer 0 FIFO DMA request overflow */ +#define ADC_FSTAT_DOV1_Pos 17 /*!< Sequencer 1 FIFO DMA request overflow */ + +/* Bit field masks: */ +#define ADC_FSTAT_OV0_Msk 0x00000001UL /*!< Sequencer 0 FIFO overflow */ +#define ADC_FSTAT_OV1_Msk 0x00000002UL /*!< Sequencer 1 FIFO overflow */ +#define ADC_FSTAT_UN0_Msk 0x00000100UL /*!< Sequencer 0 FIFO underflow */ +#define ADC_FSTAT_UN1_Msk 0x00000200UL /*!< Sequencer 1 FIFO underflow */ +#define ADC_FSTAT_DOV0_Msk 0x00010000UL /*!< Sequencer 0 FIFO DMA request overflow */ +#define ADC_FSTAT_DOV1_Msk 0x00020000UL /*!< Sequencer 1 FIFO DMA request overflow */ + +/*-- BSTAT: Busy status register -----------------------------------------------------------------------------*/ +typedef struct { + uint32_t SEQBUSY0 :1; /*!< Sequencer 0 busy */ + uint32_t SEQBUSY1 :1; /*!< Sequencer 1 busy */ + uint32_t :14; /*!< RESERVED */ + uint32_t ADCBUSY :1; /*!< ADC module conversion busy */ +} _ADC_BSTAT_bits; + +/* Bit field positions: */ +#define ADC_BSTAT_SEQBUSY0_Pos 0 /*!< Sequencer 0 busy */ +#define ADC_BSTAT_SEQBUSY1_Pos 1 /*!< Sequencer 1 busy */ +#define ADC_BSTAT_ADCBUSY_Pos 16 /*!< ADC module conversion busy */ + +/* Bit field masks: */ +#define ADC_BSTAT_SEQBUSY0_Msk 0x00000001UL /*!< Sequencer 0 busy */ +#define ADC_BSTAT_SEQBUSY1_Msk 0x00000002UL /*!< Sequencer 1 busy */ +#define ADC_BSTAT_ADCBUSY_Msk 0x00010000UL /*!< ADC module conversion busy */ + +/*-- DCTRIG: Digital comparator output trigger status register -----------------------------------------------*/ +typedef struct { + uint32_t TOS0 :1; /*!< DC 0 output trigger status */ + uint32_t TOS1 :1; /*!< DC 1 output trigger status */ + uint32_t TOS2 :1; /*!< DC 2 output trigger status */ + uint32_t TOS3 :1; /*!< DC 3 output trigger status */ + uint32_t :12; /*!< RESERVED */ + uint32_t DCEV0 :1; /*!< Digital compare event 0 */ + uint32_t DCEV1 :1; /*!< Digital compare event 1 */ + uint32_t DCEV2 :1; /*!< Digital compare event 2 */ + uint32_t DCEV3 :1; /*!< Digital compare event 3 */ +} _ADC_DCTRIG_bits; + +/* Bit field positions: */ +#define ADC_DCTRIG_TOS0_Pos 0 /*!< DC 0 output trigger status */ +#define ADC_DCTRIG_TOS1_Pos 1 /*!< DC 1 output trigger status */ +#define ADC_DCTRIG_TOS2_Pos 2 /*!< DC 2 output trigger status */ +#define ADC_DCTRIG_TOS3_Pos 3 /*!< DC 3 output trigger status */ +#define ADC_DCTRIG_DCEV0_Pos 16 /*!< Digital compare event 0 */ +#define ADC_DCTRIG_DCEV1_Pos 17 /*!< Digital compare event 1 */ +#define ADC_DCTRIG_DCEV2_Pos 18 /*!< Digital compare event 2 */ +#define ADC_DCTRIG_DCEV3_Pos 19 /*!< Digital compare event 3 */ + +/* Bit field masks: */ +#define ADC_DCTRIG_TOS0_Msk 0x00000001UL /*!< DC 0 output trigger status */ +#define ADC_DCTRIG_TOS1_Msk 0x00000002UL /*!< DC 1 output trigger status */ +#define ADC_DCTRIG_TOS2_Msk 0x00000004UL /*!< DC 2 output trigger status */ +#define ADC_DCTRIG_TOS3_Msk 0x00000008UL /*!< DC 3 output trigger status */ +#define ADC_DCTRIG_DCEV0_Msk 0x00010000UL /*!< Digital compare event 0 */ +#define ADC_DCTRIG_DCEV1_Msk 0x00020000UL /*!< Digital compare event 1 */ +#define ADC_DCTRIG_DCEV2_Msk 0x00040000UL /*!< Digital compare event 2 */ +#define ADC_DCTRIG_DCEV3_Msk 0x00080000UL /*!< Digital compare event 3 */ + +/*-- CICNT: Interrupt counter clear control ------------------------------------------------------------------*/ +typedef struct { + uint32_t ICNT0 :1; /*!< Clear interrupt counter on sequencer 0 start */ + uint32_t ICNT1 :1; /*!< Clear interrupt counter on sequencer 1 start */ +} _ADC_CICNT_bits; + +/* Bit field positions: */ +#define ADC_CICNT_ICNT0_Pos 0 /*!< Clear interrupt counter on sequencer 0 start */ +#define ADC_CICNT_ICNT1_Pos 1 /*!< Clear interrupt counter on sequencer 1 start */ + +/* Bit field masks: */ +#define ADC_CICNT_ICNT0_Msk 0x00000001UL /*!< Clear interrupt counter on sequencer 0 start */ +#define ADC_CICNT_ICNT1_Msk 0x00000002UL /*!< Clear interrupt counter on sequencer 1 start */ + +/*-- EMUX: Sequencer start event selection register ----------------------------------------------------------*/ +typedef struct { + uint32_t EM0 :4; /*!< Select start event for sequencer 0 */ + uint32_t EM1 :4; /*!< Select start event for sequencer 1 */ +} _ADC_EMUX_bits; + +/* Bit field positions: */ +#define ADC_EMUX_EM0_Pos 0 /*!< Select start event for sequencer 0 */ +#define ADC_EMUX_EM1_Pos 4 /*!< Select start event for sequencer 1 */ + +/* Bit field masks: */ +#define ADC_EMUX_EM0_Msk 0x0000000FUL /*!< Select start event for sequencer 0 */ +#define ADC_EMUX_EM1_Msk 0x000000F0UL /*!< Select start event for sequencer 1 */ + +/* Bit field enums: */ +typedef enum { + ADC_EMUX_EM0_SwReq = 0x0UL, /*!< software request by GSYNC bit */ + ADC_EMUX_EM0_GPIOA = 0x1UL, /*!< GPIOA interrupt */ + ADC_EMUX_EM0_GPIOB = 0x2UL, /*!< GPIOB interrupt */ + ADC_EMUX_EM0_TMR0 = 0x3UL, /*!< Timer 0 request */ + ADC_EMUX_EM0_TMR1 = 0x4UL, /*!< Timer 1 request */ + ADC_EMUX_EM0_TMR2 = 0x5UL, /*!< Timer 2 request */ + ADC_EMUX_EM0_TMR3 = 0x6UL, /*!< Timer 3 request */ + ADC_EMUX_EM0_PWM012A = 0x7UL, /*!< PWM0,1,2 A channel request */ + ADC_EMUX_EM0_PWM012B = 0x8UL, /*!< PWM0,1,2 B channel request */ + ADC_EMUX_EM0_Cycle = 0xFUL, /*!< Cycle mode */ +} ADC_EMUX_EM0_Enum; + +typedef enum { + ADC_EMUX_EM1_SwReq = 0x0UL, /*!< software request by GSYNC bit */ + ADC_EMUX_EM1_GPIOA = 0x1UL, /*!< GPIOA interrupt */ + ADC_EMUX_EM1_GPIOB = 0x2UL, /*!< GPIOB interrupt */ + ADC_EMUX_EM1_TMR0 = 0x3UL, /*!< Timer 0 request */ + ADC_EMUX_EM1_TMR1 = 0x4UL, /*!< Timer 1 request */ + ADC_EMUX_EM1_TMR2 = 0x5UL, /*!< Timer 2 request */ + ADC_EMUX_EM1_TMR3 = 0x6UL, /*!< Timer 3 request */ + ADC_EMUX_EM1_PWM012A = 0x7UL, /*!< PWM0,1,2 A channel request */ + ADC_EMUX_EM1_PWM012B = 0x8UL, /*!< PWM0,1,2 B channel request */ + ADC_EMUX_EM1_Cycle = 0xFUL, /*!< Cycle mode */ +} ADC_EMUX_EM1_Enum; + +/*-- RIS: Raw interrupt status register ----------------------------------------------------------------------*/ +typedef struct { + uint32_t SEQRIS0 :1; /*!< Sequencer 0 raw interrupt status */ + uint32_t SEQRIS1 :1; /*!< Sequencer 1 raw interrupt status */ + uint32_t :6; /*!< RESERVED */ + uint32_t DCRIS0 :1; /*!< Raw interrupt status of Digital Comparator 0 */ + uint32_t DCRIS1 :1; /*!< Raw interrupt status of Digital Comparator 1 */ + uint32_t DCRIS2 :1; /*!< Raw interrupt status of Digital Comparator 2 */ + uint32_t DCRIS3 :1; /*!< Raw interrupt status of Digital Comparator 3 */ +} _ADC_RIS_bits; + +/* Bit field positions: */ +#define ADC_RIS_SEQRIS0_Pos 0 /*!< Sequencer 0 raw interrupt status */ +#define ADC_RIS_SEQRIS1_Pos 1 /*!< Sequencer 1 raw interrupt status */ +#define ADC_RIS_DCRIS0_Pos 8 /*!< Raw interrupt status of Digital Comparator 0 */ +#define ADC_RIS_DCRIS1_Pos 9 /*!< Raw interrupt status of Digital Comparator 1 */ +#define ADC_RIS_DCRIS2_Pos 10 /*!< Raw interrupt status of Digital Comparator 2 */ +#define ADC_RIS_DCRIS3_Pos 11 /*!< Raw interrupt status of Digital Comparator 3 */ + +/* Bit field masks: */ +#define ADC_RIS_SEQRIS0_Msk 0x00000001UL /*!< Sequencer 0 raw interrupt status */ +#define ADC_RIS_SEQRIS1_Msk 0x00000002UL /*!< Sequencer 1 raw interrupt status */ +#define ADC_RIS_DCRIS0_Msk 0x00000100UL /*!< Raw interrupt status of Digital Comparator 0 */ +#define ADC_RIS_DCRIS1_Msk 0x00000200UL /*!< Raw interrupt status of Digital Comparator 1 */ +#define ADC_RIS_DCRIS2_Msk 0x00000400UL /*!< Raw interrupt status of Digital Comparator 2 */ +#define ADC_RIS_DCRIS3_Msk 0x00000800UL /*!< Raw interrupt status of Digital Comparator 3 */ + +/*-- IM: Interrupt mask register -----------------------------------------------------------------------------*/ +typedef struct { + uint32_t SEQIM0 :1; /*!< Sequencer 0 interrupt mask */ + uint32_t SEQIM1 :1; /*!< Sequencer 1 interrupt mask */ + uint32_t :6; /*!< RESERVED */ + uint32_t DCIM0 :1; /*!< Interrupt mask of Digital Comparator 0 */ + uint32_t DCIM1 :1; /*!< Interrupt mask of Digital Comparator 1 */ + uint32_t DCIM2 :1; /*!< Interrupt mask of Digital Comparator 2 */ + uint32_t DCIM3 :1; /*!< Interrupt mask of Digital Comparator 3 */ +} _ADC_IM_bits; + +/* Bit field positions: */ +#define ADC_IM_SEQIM0_Pos 0 /*!< Sequencer 0 interrupt mask */ +#define ADC_IM_SEQIM1_Pos 1 /*!< Sequencer 1 interrupt mask */ +#define ADC_IM_DCIM0_Pos 8 /*!< Interrupt mask of Digital Comparator 0 */ +#define ADC_IM_DCIM1_Pos 9 /*!< Interrupt mask of Digital Comparator 1 */ +#define ADC_IM_DCIM2_Pos 10 /*!< Interrupt mask of Digital Comparator 2 */ +#define ADC_IM_DCIM3_Pos 11 /*!< Interrupt mask of Digital Comparator 3 */ + +/* Bit field masks: */ +#define ADC_IM_SEQIM0_Msk 0x00000001UL /*!< Sequencer 0 interrupt mask */ +#define ADC_IM_SEQIM1_Msk 0x00000002UL /*!< Sequencer 1 interrupt mask */ +#define ADC_IM_DCIM0_Msk 0x00000100UL /*!< Interrupt mask of Digital Comparator 0 */ +#define ADC_IM_DCIM1_Msk 0x00000200UL /*!< Interrupt mask of Digital Comparator 1 */ +#define ADC_IM_DCIM2_Msk 0x00000400UL /*!< Interrupt mask of Digital Comparator 2 */ +#define ADC_IM_DCIM3_Msk 0x00000800UL /*!< Interrupt mask of Digital Comparator 3 */ + +/*-- MIS: Masked interrupt status and clear register ---------------------------------------------------------*/ +typedef struct { + uint32_t SEQMIS0 :1; /*!< Sequencer 0 masked interrupt status */ + uint32_t SEQMIS1 :1; /*!< Sequencer 1 masked interrupt status */ + uint32_t :6; /*!< RESERVED */ + uint32_t DCMIS0 :1; /*!< DC 0 masked interrupt status */ + uint32_t DCMIS1 :1; /*!< DC 1 masked interrupt status */ + uint32_t DCMIS2 :1; /*!< DC 2 masked interrupt status */ + uint32_t DCMIS3 :1; /*!< DC 3 masked interrupt status */ +} _ADC_MIS_bits; + +/* Bit field positions: */ +#define ADC_MIS_SEQMIS0_Pos 0 /*!< Sequencer 0 masked interrupt status */ +#define ADC_MIS_SEQMIS1_Pos 1 /*!< Sequencer 1 masked interrupt status */ +#define ADC_MIS_DCMIS0_Pos 8 /*!< DC 0 masked interrupt status */ +#define ADC_MIS_DCMIS1_Pos 9 /*!< DC 1 masked interrupt status */ +#define ADC_MIS_DCMIS2_Pos 10 /*!< DC 2 masked interrupt status */ +#define ADC_MIS_DCMIS3_Pos 11 /*!< DC 3 masked interrupt status */ + +/* Bit field masks: */ +#define ADC_MIS_SEQMIS0_Msk 0x00000001UL /*!< Sequencer 0 masked interrupt status */ +#define ADC_MIS_SEQMIS1_Msk 0x00000002UL /*!< Sequencer 1 masked interrupt status */ +#define ADC_MIS_DCMIS0_Msk 0x00000100UL /*!< DC 0 masked interrupt status */ +#define ADC_MIS_DCMIS1_Msk 0x00000200UL /*!< DC 1 masked interrupt status */ +#define ADC_MIS_DCMIS2_Msk 0x00000400UL /*!< DC 2 masked interrupt status */ +#define ADC_MIS_DCMIS3_Msk 0x00000800UL /*!< DC 3 masked interrupt status */ + +/*-- IC: Interrupt clear register ----------------------------------------------------------------------------*/ +typedef struct { + uint32_t SEQIC0 :1; /*!< Sequencer 0 interrupt status clear */ + uint32_t SEQIC1 :1; /*!< Sequencer 1 interrupt status clear */ + uint32_t :6; /*!< RESERVED */ + uint32_t DCIC0 :1; /*!< DC 0 interrupt status clear */ + uint32_t DCIC1 :1; /*!< DC 1 interrupt status clear */ + uint32_t DCIC2 :1; /*!< DC 2 interrupt status clear */ + uint32_t DCIC3 :1; /*!< DC 3 interrupt status clear */ +} _ADC_IC_bits; + +/* Bit field positions: */ +#define ADC_IC_SEQIC0_Pos 0 /*!< Sequencer 0 interrupt status clear */ +#define ADC_IC_SEQIC1_Pos 1 /*!< Sequencer 1 interrupt status clear */ +#define ADC_IC_DCIC0_Pos 8 /*!< DC 0 interrupt status clear */ +#define ADC_IC_DCIC1_Pos 9 /*!< DC 1 interrupt status clear */ +#define ADC_IC_DCIC2_Pos 10 /*!< DC 2 interrupt status clear */ +#define ADC_IC_DCIC3_Pos 11 /*!< DC 3 interrupt status clear */ + +/* Bit field masks: */ +#define ADC_IC_SEQIC0_Msk 0x00000001UL /*!< Sequencer 0 interrupt status clear */ +#define ADC_IC_SEQIC1_Msk 0x00000002UL /*!< Sequencer 1 interrupt status clear */ +#define ADC_IC_DCIC0_Msk 0x00000100UL /*!< DC 0 interrupt status clear */ +#define ADC_IC_DCIC1_Msk 0x00000200UL /*!< DC 1 interrupt status clear */ +#define ADC_IC_DCIC2_Msk 0x00000400UL /*!< DC 2 interrupt status clear */ +#define ADC_IC_DCIC3_Msk 0x00000800UL /*!< DC 3 interrupt status clear */ + +/*-- SEQ: SRQSEL: Sequencer request ADC channels selection register -------------------------------------------*/ +typedef struct { + uint32_t RQ0 :2; /*!< Select ADC channel for request 0 */ + uint32_t :2; /*!< RESERVED */ + uint32_t RQ1 :2; /*!< Select ADC channel for request 1 */ + uint32_t :2; /*!< RESERVED */ + uint32_t RQ2 :2; /*!< Select ADC channel for request 2 */ + uint32_t :2; /*!< RESERVED */ + uint32_t RQ3 :2; /*!< Select ADC channel for request 3 */ +} _ADC_SEQ_SRQSEL_bits; + +/* Bit field positions: */ +#define ADC_SEQ_SRQSEL_RQ0_Pos 0 /*!< Select ADC channel for request 0 */ +#define ADC_SEQ_SRQSEL_RQ1_Pos 4 /*!< Select ADC channel for request 1 */ +#define ADC_SEQ_SRQSEL_RQ2_Pos 8 /*!< Select ADC channel for request 2 */ +#define ADC_SEQ_SRQSEL_RQ3_Pos 12 /*!< Select ADC channel for request 3 */ + +/* Bit field masks: */ +#define ADC_SEQ_SRQSEL_RQ0_Msk 0x00000003UL /*!< Select ADC channel for request 0 */ +#define ADC_SEQ_SRQSEL_RQ1_Msk 0x00000030UL /*!< Select ADC channel for request 1 */ +#define ADC_SEQ_SRQSEL_RQ2_Msk 0x00000300UL /*!< Select ADC channel for request 2 */ +#define ADC_SEQ_SRQSEL_RQ3_Msk 0x00003000UL /*!< Select ADC channel for request 3 */ + +/*-- SEQ: SRQCTL: Sequencer request control register ----------------------------------------------------------*/ +typedef struct { + uint32_t RQMAX :2; /*!< Request queue max depth */ + uint32_t :6; /*!< RESERVED */ + uint32_t QAVGEN :1; /*!< Queue avearage (scanning) enable */ + uint32_t QAVGVAL :3; /*!< Queue average value */ +} _ADC_SEQ_SRQCTL_bits; + +/* Bit field positions: */ +#define ADC_SEQ_SRQCTL_RQMAX_Pos 0 /*!< Request queue max depth */ +#define ADC_SEQ_SRQCTL_QAVGEN_Pos 8 /*!< Queue avearage (scanning) enable */ +#define ADC_SEQ_SRQCTL_QAVGVAL_Pos 9 /*!< Queue average value */ + +/* Bit field masks: */ +#define ADC_SEQ_SRQCTL_RQMAX_Msk 0x00000003UL /*!< Request queue max depth */ +#define ADC_SEQ_SRQCTL_QAVGEN_Msk 0x00000100UL /*!< Queue avearage (scanning) enable */ +#define ADC_SEQ_SRQCTL_QAVGVAL_Msk 0x00000E00UL /*!< Queue average value */ + +/* Bit field enums: */ +typedef enum { + ADC_SEQ_SRQCTL_QAVGVAL_Disable = 0x0UL, /*!< Average disabled */ + ADC_SEQ_SRQCTL_QAVGVAL_Average2 = 0x1UL, /*!< Average with 2 measures */ + ADC_SEQ_SRQCTL_QAVGVAL_Average4 = 0x2UL, /*!< Average with 4 measures */ + ADC_SEQ_SRQCTL_QAVGVAL_Average8 = 0x3UL, /*!< Average with 8 measures */ + ADC_SEQ_SRQCTL_QAVGVAL_Average16 = 0x4UL, /*!< Average with 16 measures */ + ADC_SEQ_SRQCTL_QAVGVAL_Average32 = 0x5UL, /*!< Average with 32 measures */ + ADC_SEQ_SRQCTL_QAVGVAL_Average64 = 0x6UL, /*!< Average with 64 measures */ +} ADC_SEQ_SRQCTL_QAVGVAL_Enum; + +/*-- SEQ: SRQSTAT: Sequencer request status register ----------------------------------------------------------*/ +typedef struct { + uint32_t RQPTR :2; /*!< Pointer to queue current request */ + uint32_t :6; /*!< RESERVED */ + uint32_t RQBUSY :1; /*!< Active request status */ +} _ADC_SEQ_SRQSTAT_bits; + +/* Bit field positions: */ +#define ADC_SEQ_SRQSTAT_RQPTR_Pos 0 /*!< Pointer to queue current request */ +#define ADC_SEQ_SRQSTAT_RQBUSY_Pos 8 /*!< Active request status */ + +/* Bit field masks: */ +#define ADC_SEQ_SRQSTAT_RQPTR_Msk 0x00000003UL /*!< Pointer to queue current request */ +#define ADC_SEQ_SRQSTAT_RQBUSY_Msk 0x00000100UL /*!< Active request status */ + +/*-- SEQ: SDMACTL: Sequencer DMA control register -------------------------------------------------------------*/ +typedef struct { + uint32_t DMAEN :1; /*!< Enable DMA use */ + uint32_t :7; /*!< RESERVED */ + uint32_t WMARK :3; /*!< FIFO load threshold for DMA request generation */ +} _ADC_SEQ_SDMACTL_bits; + +/* Bit field positions: */ +#define ADC_SEQ_SDMACTL_DMAEN_Pos 0 /*!< Enable DMA use */ +#define ADC_SEQ_SDMACTL_WMARK_Pos 8 /*!< FIFO load threshold for DMA request generation */ + +/* Bit field masks: */ +#define ADC_SEQ_SDMACTL_DMAEN_Msk 0x00000001UL /*!< Enable DMA use */ +#define ADC_SEQ_SDMACTL_WMARK_Msk 0x00000700UL /*!< FIFO load threshold for DMA request generation */ + +/* Bit field enums: */ +typedef enum { + ADC_SEQ_SDMACTL_WMARK_Level1 = 0x1UL, /*!< 1 measure for dma request */ + ADC_SEQ_SDMACTL_WMARK_Level2 = 0x2UL, /*!< 2 measures for dma request */ + ADC_SEQ_SDMACTL_WMARK_Level4 = 0x3UL, /*!< 4 measures for dma request */ + ADC_SEQ_SDMACTL_WMARK_Level8 = 0x4UL, /*!< 8 measures for dma request */ + ADC_SEQ_SDMACTL_WMARK_Level16 = 0x5UL, /*!< 16 measures for dma request */ + ADC_SEQ_SDMACTL_WMARK_Level32 = 0x6UL, /*!< 32 measures for dma request */ +} ADC_SEQ_SDMACTL_WMARK_Enum; + +/*-- SEQ: SCCTL: Sequencer ADC interrupt and restart counter control register ---------------------------------*/ +typedef struct { + uint32_t RCNT :8; /*!< Current number of ADC restarts by sequencer */ + uint32_t RAVGEN :1; /*!< Average of ADC restarts enable */ + uint32_t :7; /*!< RESERVED */ + uint32_t ICNT :8; /*!< Number of ADC requests for interrupt generation */ +} _ADC_SEQ_SCCTL_bits; + +/* Bit field positions: */ +#define ADC_SEQ_SCCTL_RCNT_Pos 0 /*!< Current number of ADC restarts by sequencer */ +#define ADC_SEQ_SCCTL_RAVGEN_Pos 8 /*!< Average of ADC restarts enable */ +#define ADC_SEQ_SCCTL_ICNT_Pos 16 /*!< Number of ADC requests for interrupt generation */ + +/* Bit field masks: */ +#define ADC_SEQ_SCCTL_RCNT_Msk 0x000000FFUL /*!< Current number of ADC restarts by sequencer */ +#define ADC_SEQ_SCCTL_RAVGEN_Msk 0x00000100UL /*!< Average of ADC restarts enable */ +#define ADC_SEQ_SCCTL_ICNT_Msk 0x00FF0000UL /*!< Number of ADC requests for interrupt generation */ + +/*-- SEQ: SCVAL: Sequencer ADC interrupt and restart counter current value register ---------------------------------*/ +typedef struct { + uint32_t RCNT :8; /*!< Current number of ADC restarts by sequencer */ + uint32_t :8; /*!< RESERVED */ + uint32_t ICNT :8; /*!< Current number of ADC requests for interrupt generation */ + uint32_t ICLR :1; /*!< Clear interrupt counter */ +} _ADC_SEQ_SCVAL_bits; + +/* Bit field positions: */ +#define ADC_SEQ_SCVAL_RCNT_Pos 0 /*!< Current number of ADC restarts by sequencer */ +#define ADC_SEQ_SCVAL_ICNT_Pos 16 /*!< Current number of ADC requests for interrupt generation */ +#define ADC_SEQ_SCVAL_ICLR_Pos 24 /*!< Clear interrupt counter */ + +/* Bit field masks: */ +#define ADC_SEQ_SCVAL_RCNT_Msk 0x000000FFUL /*!< Current number of ADC restarts by sequencer */ +#define ADC_SEQ_SCVAL_ICNT_Msk 0x00FF0000UL /*!< Current number of ADC requests for interrupt generation */ +#define ADC_SEQ_SCVAL_ICLR_Msk 0x01000000UL /*!< Clear interrupt counter */ + +/*-- SEQ: SDC: Sequencer digital comparator selection register ------------------------------------------------*/ +typedef struct { + uint32_t DC0 :1; /*!< Enable DC 0 */ + uint32_t DC1 :1; /*!< Enable DC 1 */ + uint32_t DC2 :1; /*!< Enable DC 2 */ + uint32_t DC3 :1; /*!< Enable DC 3 */ +} _ADC_SEQ_SDC_bits; + +/* Bit field positions: */ +#define ADC_SEQ_SDC_DC0_Pos 0 /*!< Enable DC 0 */ +#define ADC_SEQ_SDC_DC1_Pos 1 /*!< Enable DC 1 */ +#define ADC_SEQ_SDC_DC2_Pos 2 /*!< Enable DC 2 */ +#define ADC_SEQ_SDC_DC3_Pos 3 /*!< Enable DC 3 */ + +/* Bit field masks: */ +#define ADC_SEQ_SDC_DC0_Msk 0x00000001UL /*!< Enable DC 0 */ +#define ADC_SEQ_SDC_DC1_Msk 0x00000002UL /*!< Enable DC 1 */ +#define ADC_SEQ_SDC_DC2_Msk 0x00000004UL /*!< Enable DC 2 */ +#define ADC_SEQ_SDC_DC3_Msk 0x00000008UL /*!< Enable DC 3 */ + +/*-- SEQ: SRTMR: Sequencer ADC restart timer register ---------------------------------------------------------*/ +typedef struct { + uint32_t VAL :24; /*!< Sequencer ADC restart timer value */ + uint32_t :7; /*!< RESERVED */ + uint32_t NOWAIT :1; /*!< Timer update with no waiting the end of current seq task */ +} _ADC_SEQ_SRTMR_bits; + +/* Bit field positions: */ +#define ADC_SEQ_SRTMR_VAL_Pos 0 /*!< Sequencer ADC restart timer value */ +#define ADC_SEQ_SRTMR_NOWAIT_Pos 31 /*!< Timer update with no waiting the end of current seq task */ + +/* Bit field masks: */ +#define ADC_SEQ_SRTMR_VAL_Msk 0x00FFFFFFUL /*!< Sequencer ADC restart timer value */ +#define ADC_SEQ_SRTMR_NOWAIT_Msk 0x80000000UL /*!< Timer update with no waiting the end of current seq task */ + +/*-- SEQ: SFLOAD: Sequencer FIFO load status register ---------------------------------------------------------*/ +typedef struct { + uint32_t VAL :6; /*!< Sequencer FIFO current load value */ +} _ADC_SEQ_SFLOAD_bits; + +/* Bit field positions: */ +#define ADC_SEQ_SFLOAD_VAL_Pos 0 /*!< Sequencer FIFO current load value */ + +/* Bit field masks: */ +#define ADC_SEQ_SFLOAD_VAL_Msk 0x0000003FUL /*!< Sequencer FIFO current load value */ + +/*-- SEQ: SFIFO: Sequencer FIFO register ----------------------------------------------------------------------*/ +typedef struct { + uint32_t DATA :12; /*!< AD conversion value */ +} _ADC_SEQ_SFIFO_bits; + +/* Bit field positions: */ +#define ADC_SEQ_SFIFO_DATA_Pos 0 /*!< AD conversion value */ + +/* Bit field masks: */ +#define ADC_SEQ_SFIFO_DATA_Msk 0x00000FFFUL /*!< AD conversion value */ + +/*-- DC: DCTL: Digital comparator control register ------------------------------------------------------------*/ +typedef struct { + uint32_t CIM :2; /*!< DC interrupt generation mode */ + uint32_t CIC :2; /*!< DC interrupt generation compare conditions */ + uint32_t CIE :1; /*!< Enable DC interrupt generation */ + uint32_t :3; /*!< RESERVED */ + uint32_t CTM :2; /*!< DC output trigger mode */ + uint32_t CTC :2; /*!< DC output trigger compare conditions */ + uint32_t CTE :1; /*!< Enable DC output trigger */ + uint32_t :3; /*!< RESERVED */ + uint32_t CHNL :2; /*!< ADC channel selection */ + uint32_t :6; /*!< RESERVED */ + uint32_t SRC :1; /*!< Select data source for comparation: ADC module (0) or sequencer(1) */ +} _ADC_DC_DCTL_bits; + +/* Bit field positions: */ +#define ADC_DC_DCTL_CIM_Pos 0 /*!< DC interrupt generation mode */ +#define ADC_DC_DCTL_CIC_Pos 2 /*!< DC interrupt generation compare conditions */ +#define ADC_DC_DCTL_CIE_Pos 4 /*!< Enable DC interrupt generation */ +#define ADC_DC_DCTL_CTM_Pos 8 /*!< DC output trigger mode */ +#define ADC_DC_DCTL_CTC_Pos 10 /*!< DC output trigger compare conditions */ +#define ADC_DC_DCTL_CTE_Pos 12 /*!< Enable DC output trigger */ +#define ADC_DC_DCTL_CHNL_Pos 16 /*!< ADC channel selection */ +#define ADC_DC_DCTL_SRC_Pos 24 /*!< Select data source for comparation: ADC module (0) or sequencer(1) */ + +/* Bit field masks: */ +#define ADC_DC_DCTL_CIM_Msk 0x00000003UL /*!< DC interrupt generation mode */ +#define ADC_DC_DCTL_CIC_Msk 0x0000000CUL /*!< DC interrupt generation compare conditions */ +#define ADC_DC_DCTL_CIE_Msk 0x00000010UL /*!< Enable DC interrupt generation */ +#define ADC_DC_DCTL_CTM_Msk 0x00000300UL /*!< DC output trigger mode */ +#define ADC_DC_DCTL_CTC_Msk 0x00000C00UL /*!< DC output trigger compare conditions */ +#define ADC_DC_DCTL_CTE_Msk 0x00001000UL /*!< Enable DC output trigger */ +#define ADC_DC_DCTL_CHNL_Msk 0x00030000UL /*!< ADC channel selection */ +#define ADC_DC_DCTL_SRC_Msk 0x01000000UL /*!< Select data source for comparation: ADC module (0) or sequencer(1) */ + +/* Bit field enums: */ +typedef enum { + ADC_DC_DCTL_CIM_Multiple = 0x0UL, /*!< multiple trigger mode */ + ADC_DC_DCTL_CIM_Single = 0x1UL, /*!< single trigger mode */ + ADC_DC_DCTL_CIM_MultipleHyst = 0x2UL, /*!< multiple trigger mode with hysteresis */ + ADC_DC_DCTL_CIM_SingleHyst = 0x3UL, /*!< single trigger mode with hysteresis */ +} ADC_DC_DCTL_CIM_Enum; + +typedef enum { + ADC_DC_DCTL_CIC_Low = 0x0UL, /*!< result lower or equal COMP0 */ + ADC_DC_DCTL_CIC_Window = 0x1UL, /*!< result between COMP0 and COMP1 or equal any of them */ + ADC_DC_DCTL_CIC_High = 0x2UL, /*!< result higher or equal COMP1 */ +} ADC_DC_DCTL_CIC_Enum; + +typedef enum { + ADC_DC_DCTL_CTM_Multiple = 0x0UL, /*!< multiple trigger mode */ + ADC_DC_DCTL_CTM_Single = 0x1UL, /*!< single trigger mode */ + ADC_DC_DCTL_CTM_MultipleHyst = 0x2UL, /*!< multiple trigger mode with hysteresis */ + ADC_DC_DCTL_CTM_SingleHyst = 0x3UL, /*!< single trigger mode with hysteresis */ +} ADC_DC_DCTL_CTM_Enum; + +typedef enum { + ADC_DC_DCTL_CTC_Low = 0x0UL, /*!< result lower or equal COMP0 */ + ADC_DC_DCTL_CTC_Window = 0x1UL, /*!< result between COMP0 and COMP1 or equal any of them */ + ADC_DC_DCTL_CTC_High = 0x2UL, /*!< result higher or equal COMP1 */ +} ADC_DC_DCTL_CTC_Enum; + +/*-- DC: DCMP: Digital comparator range register --------------------------------------------------------------*/ +typedef struct { + uint32_t CMPL :12; /*!< Low threshold compare value */ + uint32_t :4; /*!< RESERVED */ + uint32_t CMPH :12; /*!< High threshold compare value */ +} _ADC_DC_DCMP_bits; + +/* Bit field positions: */ +#define ADC_DC_DCMP_CMPL_Pos 0 /*!< Low threshold compare value */ +#define ADC_DC_DCMP_CMPH_Pos 16 /*!< High threshold compare value */ + +/* Bit field masks: */ +#define ADC_DC_DCMP_CMPL_Msk 0x00000FFFUL /*!< Low threshold compare value */ +#define ADC_DC_DCMP_CMPH_Msk 0x0FFF0000UL /*!< High threshold compare value */ + +/*-- DC: DDATA: Digital comparator last compared data register ------------------------------------------------*/ +typedef struct { + uint32_t VAL :12; /*!< Value of last compared AD conversion result */ +} _ADC_DC_DDATA_bits; + +/* Bit field positions: */ +#define ADC_DC_DDATA_VAL_Pos 0 /*!< Value of last compared AD conversion result */ + +/* Bit field masks: */ +#define ADC_DC_DDATA_VAL_Msk 0x00000FFFUL /*!< Value of last compared AD conversion result */ + +/*-- ACTL: ADC module control register -----------------------------------------------------------------------*/ +typedef struct { + uint32_t ADCEN :1; /*!< Enable ADC module */ + uint32_t ADCRDY :1; /*!< ADC ready for conversions */ +} _ADC_ACTL_bits; + +/* Bit field positions: */ +#define ADC_ACTL_ADCEN_Pos 0 /*!< Enable ADC module */ +#define ADC_ACTL_ADCRDY_Pos 1 /*!< ADC ready for conversions */ + +/* Bit field masks: */ +#define ADC_ACTL_ADCEN_Msk 0x00000001UL /*!< Enable ADC module */ +#define ADC_ACTL_ADCRDY_Msk 0x00000002UL /*!< ADC ready for conversions */ + +/*-- CHCTL: CHCTL: ADC channel control register ---------------------------------------------------------------*/ +typedef struct { + uint32_t OFFTRIM :9; /*!< ADC channel offset trimm value */ + uint32_t :7; /*!< RESERVED */ + uint32_t GAINTRIM :9; /*!< ADC channel gain trimm value */ + uint32_t :3; /*!< RESERVED */ + uint32_t PRIORITY :1; /*!< ADC channel priority level */ +} _ADC_CHCTL_CHCTL_bits; + +/* Bit field positions: */ +#define ADC_CHCTL_CHCTL_OFFTRIM_Pos 0 /*!< ADC channel offset trimm value */ +#define ADC_CHCTL_CHCTL_GAINTRIM_Pos 16 /*!< ADC channel gain trimm value */ +#define ADC_CHCTL_CHCTL_PRIORITY_Pos 28 /*!< ADC channel priority level */ + +/* Bit field masks: */ +#define ADC_CHCTL_CHCTL_OFFTRIM_Msk 0x000001FFUL /*!< ADC channel offset trimm value */ +#define ADC_CHCTL_CHCTL_GAINTRIM_Msk 0x01FF0000UL /*!< ADC channel gain trimm value */ +#define ADC_CHCTL_CHCTL_PRIORITY_Msk 0x10000000UL /*!< ADC channel priority level */ + +//Cluster SEQ: +typedef struct { + union { + /*!< Sequencer request ADC channels selection register */ + __IO uint32_t SRQSEL; /*!< SRQSEL : type used for word access */ + __IO _ADC_SEQ_SRQSEL_bits SRQSEL_bit; /*!< SRQSEL_bit: structure used for bit access */ + }; + __IO uint32_t Reserved0[3]; + union { + /*!< Sequencer request control register */ + __IO uint32_t SRQCTL; /*!< SRQCTL : type used for word access */ + __IO _ADC_SEQ_SRQCTL_bits SRQCTL_bit; /*!< SRQCTL_bit: structure used for bit access */ + }; + union { + /*!< Sequencer request status register */ + __I uint32_t SRQSTAT; /*!< SRQSTAT : type used for word access */ + __I _ADC_SEQ_SRQSTAT_bits SRQSTAT_bit; /*!< SRQSTAT_bit: structure used for bit access */ + }; + union { + /*!< Sequencer DMA control register */ + __IO uint32_t SDMACTL; /*!< SDMACTL : type used for word access */ + __IO _ADC_SEQ_SDMACTL_bits SDMACTL_bit; /*!< SDMACTL_bit: structure used for bit access */ + }; + union { + /*!< Sequencer ADC interrupt and restart counter control register */ + __IO uint32_t SCCTL; /*!< SCCTL : type used for word access */ + __IO _ADC_SEQ_SCCTL_bits SCCTL_bit; /*!< SCCTL_bit: structure used for bit access */ + }; + union { + /*!< Sequencer ADC interrupt and restart counter current value register */ + __O uint32_t SCVAL; /*!< SCVAL : type used for word access */ + __O _ADC_SEQ_SCVAL_bits SCVAL_bit; /*!< SCVAL_bit: structure used for bit access */ + }; + union { + /*!< Sequencer digital comparator selection register */ + __IO uint32_t SDC; /*!< SDC : type used for word access */ + __IO _ADC_SEQ_SDC_bits SDC_bit; /*!< SDC_bit: structure used for bit access */ + }; + union { + /*!< Sequencer ADC restart timer register */ + __IO uint32_t SRTMR; /*!< SRTMR : type used for word access */ + __IO _ADC_SEQ_SRTMR_bits SRTMR_bit; /*!< SRTMR_bit: structure used for bit access */ + }; + union { + /*!< Sequencer FIFO load status register */ + __I uint32_t SFLOAD; /*!< SFLOAD : type used for word access */ + __I _ADC_SEQ_SFLOAD_bits SFLOAD_bit; /*!< SFLOAD_bit: structure used for bit access */ + }; + union { + /*!< Sequencer FIFO register */ + __I uint32_t SFIFO; /*!< SFIFO : type used for word access */ + __I _ADC_SEQ_SFIFO_bits SFIFO_bit; /*!< SFIFO_bit: structure used for bit access */ + }; +} _ADC_SEQ_TypeDef; +//Cluster DC: +typedef struct { + union { + /*!< Digital comparator control register */ + __IO uint32_t DCTL; /*!< DCTL : type used for word access */ + __IO _ADC_DC_DCTL_bits DCTL_bit; /*!< DCTL_bit: structure used for bit access */ + }; + union { + /*!< Digital comparator range register */ + __IO uint32_t DCMP; /*!< DCMP : type used for word access */ + __IO _ADC_DC_DCMP_bits DCMP_bit; /*!< DCMP_bit: structure used for bit access */ + }; + union { + /*!< Digital comparator last compared data register */ + __I uint32_t DDATA; /*!< DDATA : type used for word access */ + __I _ADC_DC_DDATA_bits DDATA_bit; /*!< DDATA_bit: structure used for bit access */ + }; +} _ADC_DC_TypeDef; +//Cluster CHCTL: +typedef struct { + union { + /*!< ADC channel control register */ + __IO uint32_t CHCTL; /*!< CHCTL : type used for word access */ + __IO _ADC_CHCTL_CHCTL_bits CHCTL_bit; /*!< CHCTL_bit: structure used for bit access */ + }; +} _ADC_CHCTL_TypeDef; +typedef struct { + union { /*!< Enable sequencer register */ + __IO uint32_t SEQEN; /*!< SEQEN : type used for word access */ + __IO _ADC_SEQEN_bits SEQEN_bit; /*!< SEQEN_bit: structure used for bit access */ + }; + union { /*!< Sequencer sync register */ + __IO uint32_t SEQSYNC; /*!< SEQSYNC : type used for word access */ + __IO _ADC_SEQSYNC_bits SEQSYNC_bit; /*!< SEQSYNC_bit: structure used for bit access */ + }; + union { /*!< FIFO overflow status register */ + __IO uint32_t FSTAT; /*!< FSTAT : type used for word access */ + __IO _ADC_FSTAT_bits FSTAT_bit; /*!< FSTAT_bit: structure used for bit access */ + }; + union { /*!< Busy status register */ + __I uint32_t BSTAT; /*!< BSTAT : type used for word access */ + __I _ADC_BSTAT_bits BSTAT_bit; /*!< BSTAT_bit: structure used for bit access */ + }; + union { /*!< Digital comparator output trigger status register */ + __IO uint32_t DCTRIG; /*!< DCTRIG : type used for word access */ + __IO _ADC_DCTRIG_bits DCTRIG_bit; /*!< DCTRIG_bit: structure used for bit access */ + }; + union { /*!< Interrupt counter clear control */ + __IO uint32_t CICNT; /*!< CICNT : type used for word access */ + __IO _ADC_CICNT_bits CICNT_bit; /*!< CICNT_bit: structure used for bit access */ + }; + union { /*!< Sequencer start event selection register */ + __IO uint32_t EMUX; /*!< EMUX : type used for word access */ + __IO _ADC_EMUX_bits EMUX_bit; /*!< EMUX_bit: structure used for bit access */ + }; + union { /*!< Raw interrupt status register */ + __I uint32_t RIS; /*!< RIS : type used for word access */ + __I _ADC_RIS_bits RIS_bit; /*!< RIS_bit: structure used for bit access */ + }; + union { /*!< Interrupt mask register */ + __IO uint32_t IM; /*!< IM : type used for word access */ + __IO _ADC_IM_bits IM_bit; /*!< IM_bit: structure used for bit access */ + }; + union { /*!< Masked interrupt status and clear register */ + __I uint32_t MIS; /*!< MIS : type used for word access */ + __I _ADC_MIS_bits MIS_bit; /*!< MIS_bit: structure used for bit access */ + }; + union { /*!< Interrupt clear register */ + __O uint32_t IC; /*!< IC : type used for word access */ + __O _ADC_IC_bits IC_bit; /*!< IC_bit: structure used for bit access */ + }; + __IO uint32_t Reserved0[5]; + _ADC_SEQ_TypeDef SEQ[2]; + __IO uint32_t Reserved1[86]; + _ADC_DC_TypeDef DC[4]; + __IO uint32_t Reserved2[116]; + union { /*!< ADC module control register */ + __IO uint32_t ACTL; /*!< ACTL : type used for word access */ + __IO _ADC_ACTL_bits ACTL_bit; /*!< ACTL_bit: structure used for bit access */ + }; + __IO uint32_t Reserved3[63]; + _ADC_CHCTL_TypeDef CHCTL[4]; +} ADC_TypeDef; + + +/******************************************************************************/ +/* GPIO registers */ +/******************************************************************************/ + +/*-- DATA: Data Input register -------------------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :16; /*!< Data input */ +} _GPIO_DATA_bits; + +/* Bit field positions: */ +#define GPIO_DATA_VAL_Pos 0 /*!< Data input */ + +/* Bit field masks: */ +#define GPIO_DATA_VAL_Msk 0x0000FFFFUL /*!< Data input */ + +/*-- DATAOUT: Data output register ---------------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :16; /*!< Data output */ +} _GPIO_DATAOUT_bits; + +/* Bit field positions: */ +#define GPIO_DATAOUT_VAL_Pos 0 /*!< Data output */ + +/* Bit field masks: */ +#define GPIO_DATAOUT_VAL_Msk 0x0000FFFFUL /*!< Data output */ + +/*-- DATAOUTSET: Data output set bits register ---------------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< Data output set bit 0 */ + uint32_t PIN1 :1; /*!< Data output set bit 1 */ + uint32_t PIN2 :1; /*!< Data output set bit 2 */ + uint32_t PIN3 :1; /*!< Data output set bit 3 */ + uint32_t PIN4 :1; /*!< Data output set bit 4 */ + uint32_t PIN5 :1; /*!< Data output set bit 5 */ + uint32_t PIN6 :1; /*!< Data output set bit 6 */ + uint32_t PIN7 :1; /*!< Data output set bit 7 */ + uint32_t PIN8 :1; /*!< Data output set bit 8 */ + uint32_t PIN9 :1; /*!< Data output set bit 9 */ + uint32_t PIN10 :1; /*!< Data output set bit 10 */ + uint32_t PIN11 :1; /*!< Data output set bit 11 */ + uint32_t PIN12 :1; /*!< Data output set bit 12 */ + uint32_t PIN13 :1; /*!< Data output set bit 13 */ + uint32_t PIN14 :1; /*!< Data output set bit 14 */ + uint32_t PIN15 :1; /*!< Data output set bit 15 */ +} _GPIO_DATAOUTSET_bits; + +/* Bit field positions: */ +#define GPIO_DATAOUTSET_PIN0_Pos 0 /*!< Data output set bit 0 */ +#define GPIO_DATAOUTSET_PIN1_Pos 1 /*!< Data output set bit 1 */ +#define GPIO_DATAOUTSET_PIN2_Pos 2 /*!< Data output set bit 2 */ +#define GPIO_DATAOUTSET_PIN3_Pos 3 /*!< Data output set bit 3 */ +#define GPIO_DATAOUTSET_PIN4_Pos 4 /*!< Data output set bit 4 */ +#define GPIO_DATAOUTSET_PIN5_Pos 5 /*!< Data output set bit 5 */ +#define GPIO_DATAOUTSET_PIN6_Pos 6 /*!< Data output set bit 6 */ +#define GPIO_DATAOUTSET_PIN7_Pos 7 /*!< Data output set bit 7 */ +#define GPIO_DATAOUTSET_PIN8_Pos 8 /*!< Data output set bit 8 */ +#define GPIO_DATAOUTSET_PIN9_Pos 9 /*!< Data output set bit 9 */ +#define GPIO_DATAOUTSET_PIN10_Pos 10 /*!< Data output set bit 10 */ +#define GPIO_DATAOUTSET_PIN11_Pos 11 /*!< Data output set bit 11 */ +#define GPIO_DATAOUTSET_PIN12_Pos 12 /*!< Data output set bit 12 */ +#define GPIO_DATAOUTSET_PIN13_Pos 13 /*!< Data output set bit 13 */ +#define GPIO_DATAOUTSET_PIN14_Pos 14 /*!< Data output set bit 14 */ +#define GPIO_DATAOUTSET_PIN15_Pos 15 /*!< Data output set bit 15 */ + +/* Bit field masks: */ +#define GPIO_DATAOUTSET_PIN0_Msk 0x00000001UL /*!< Data output set bit 0 */ +#define GPIO_DATAOUTSET_PIN1_Msk 0x00000002UL /*!< Data output set bit 1 */ +#define GPIO_DATAOUTSET_PIN2_Msk 0x00000004UL /*!< Data output set bit 2 */ +#define GPIO_DATAOUTSET_PIN3_Msk 0x00000008UL /*!< Data output set bit 3 */ +#define GPIO_DATAOUTSET_PIN4_Msk 0x00000010UL /*!< Data output set bit 4 */ +#define GPIO_DATAOUTSET_PIN5_Msk 0x00000020UL /*!< Data output set bit 5 */ +#define GPIO_DATAOUTSET_PIN6_Msk 0x00000040UL /*!< Data output set bit 6 */ +#define GPIO_DATAOUTSET_PIN7_Msk 0x00000080UL /*!< Data output set bit 7 */ +#define GPIO_DATAOUTSET_PIN8_Msk 0x00000100UL /*!< Data output set bit 8 */ +#define GPIO_DATAOUTSET_PIN9_Msk 0x00000200UL /*!< Data output set bit 9 */ +#define GPIO_DATAOUTSET_PIN10_Msk 0x00000400UL /*!< Data output set bit 10 */ +#define GPIO_DATAOUTSET_PIN11_Msk 0x00000800UL /*!< Data output set bit 11 */ +#define GPIO_DATAOUTSET_PIN12_Msk 0x00001000UL /*!< Data output set bit 12 */ +#define GPIO_DATAOUTSET_PIN13_Msk 0x00002000UL /*!< Data output set bit 13 */ +#define GPIO_DATAOUTSET_PIN14_Msk 0x00004000UL /*!< Data output set bit 14 */ +#define GPIO_DATAOUTSET_PIN15_Msk 0x00008000UL /*!< Data output set bit 15 */ + +/*-- DATAOUTCLR: Data output clear bits register -------------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< Data output clear bit 0 */ + uint32_t PIN1 :1; /*!< Data output clear bit 1 */ + uint32_t PIN2 :1; /*!< Data output clear bit 2 */ + uint32_t PIN3 :1; /*!< Data output clear bit 3 */ + uint32_t PIN4 :1; /*!< Data output clear bit 4 */ + uint32_t PIN5 :1; /*!< Data output clear bit 5 */ + uint32_t PIN6 :1; /*!< Data output clear bit 6 */ + uint32_t PIN7 :1; /*!< Data output clear bit 7 */ + uint32_t PIN8 :1; /*!< Data output clear bit 8 */ + uint32_t PIN9 :1; /*!< Data output clear bit 9 */ + uint32_t PIN10 :1; /*!< Data output clear bit 10 */ + uint32_t PIN11 :1; /*!< Data output clear bit 11 */ + uint32_t PIN12 :1; /*!< Data output clear bit 12 */ + uint32_t PIN13 :1; /*!< Data output clear bit 13 */ + uint32_t PIN14 :1; /*!< Data output clear bit 14 */ + uint32_t PIN15 :1; /*!< Data output clear bit 15 */ +} _GPIO_DATAOUTCLR_bits; + +/* Bit field positions: */ +#define GPIO_DATAOUTCLR_PIN0_Pos 0 /*!< Data output clear bit 0 */ +#define GPIO_DATAOUTCLR_PIN1_Pos 1 /*!< Data output clear bit 1 */ +#define GPIO_DATAOUTCLR_PIN2_Pos 2 /*!< Data output clear bit 2 */ +#define GPIO_DATAOUTCLR_PIN3_Pos 3 /*!< Data output clear bit 3 */ +#define GPIO_DATAOUTCLR_PIN4_Pos 4 /*!< Data output clear bit 4 */ +#define GPIO_DATAOUTCLR_PIN5_Pos 5 /*!< Data output clear bit 5 */ +#define GPIO_DATAOUTCLR_PIN6_Pos 6 /*!< Data output clear bit 6 */ +#define GPIO_DATAOUTCLR_PIN7_Pos 7 /*!< Data output clear bit 7 */ +#define GPIO_DATAOUTCLR_PIN8_Pos 8 /*!< Data output clear bit 8 */ +#define GPIO_DATAOUTCLR_PIN9_Pos 9 /*!< Data output clear bit 9 */ +#define GPIO_DATAOUTCLR_PIN10_Pos 10 /*!< Data output clear bit 10 */ +#define GPIO_DATAOUTCLR_PIN11_Pos 11 /*!< Data output clear bit 11 */ +#define GPIO_DATAOUTCLR_PIN12_Pos 12 /*!< Data output clear bit 12 */ +#define GPIO_DATAOUTCLR_PIN13_Pos 13 /*!< Data output clear bit 13 */ +#define GPIO_DATAOUTCLR_PIN14_Pos 14 /*!< Data output clear bit 14 */ +#define GPIO_DATAOUTCLR_PIN15_Pos 15 /*!< Data output clear bit 15 */ + +/* Bit field masks: */ +#define GPIO_DATAOUTCLR_PIN0_Msk 0x00000001UL /*!< Data output clear bit 0 */ +#define GPIO_DATAOUTCLR_PIN1_Msk 0x00000002UL /*!< Data output clear bit 1 */ +#define GPIO_DATAOUTCLR_PIN2_Msk 0x00000004UL /*!< Data output clear bit 2 */ +#define GPIO_DATAOUTCLR_PIN3_Msk 0x00000008UL /*!< Data output clear bit 3 */ +#define GPIO_DATAOUTCLR_PIN4_Msk 0x00000010UL /*!< Data output clear bit 4 */ +#define GPIO_DATAOUTCLR_PIN5_Msk 0x00000020UL /*!< Data output clear bit 5 */ +#define GPIO_DATAOUTCLR_PIN6_Msk 0x00000040UL /*!< Data output clear bit 6 */ +#define GPIO_DATAOUTCLR_PIN7_Msk 0x00000080UL /*!< Data output clear bit 7 */ +#define GPIO_DATAOUTCLR_PIN8_Msk 0x00000100UL /*!< Data output clear bit 8 */ +#define GPIO_DATAOUTCLR_PIN9_Msk 0x00000200UL /*!< Data output clear bit 9 */ +#define GPIO_DATAOUTCLR_PIN10_Msk 0x00000400UL /*!< Data output clear bit 10 */ +#define GPIO_DATAOUTCLR_PIN11_Msk 0x00000800UL /*!< Data output clear bit 11 */ +#define GPIO_DATAOUTCLR_PIN12_Msk 0x00001000UL /*!< Data output clear bit 12 */ +#define GPIO_DATAOUTCLR_PIN13_Msk 0x00002000UL /*!< Data output clear bit 13 */ +#define GPIO_DATAOUTCLR_PIN14_Msk 0x00004000UL /*!< Data output clear bit 14 */ +#define GPIO_DATAOUTCLR_PIN15_Msk 0x00008000UL /*!< Data output clear bit 15 */ + +/*-- DATAOUTTGL: Data output toogle bits register ------------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< Data output toogle bit 0 */ + uint32_t PIN1 :1; /*!< Data output toogle bit 1 */ + uint32_t PIN2 :1; /*!< Data output toogle bit 2 */ + uint32_t PIN3 :1; /*!< Data output toogle bit 3 */ + uint32_t PIN4 :1; /*!< Data output toogle bit 4 */ + uint32_t PIN5 :1; /*!< Data output toogle bit 5 */ + uint32_t PIN6 :1; /*!< Data output toogle bit 6 */ + uint32_t PIN7 :1; /*!< Data output toogle bit 7 */ + uint32_t PIN8 :1; /*!< Data output toogle bit 8 */ + uint32_t PIN9 :1; /*!< Data output toogle bit 9 */ + uint32_t PIN10 :1; /*!< Data output toogle bit 10 */ + uint32_t PIN11 :1; /*!< Data output toogle bit 11 */ + uint32_t PIN12 :1; /*!< Data output toogle bit 12 */ + uint32_t PIN13 :1; /*!< Data output toogle bit 13 */ + uint32_t PIN14 :1; /*!< Data output toogle bit 14 */ + uint32_t PIN15 :1; /*!< Data output toogle bit 15 */ +} _GPIO_DATAOUTTGL_bits; + +/* Bit field positions: */ +#define GPIO_DATAOUTTGL_PIN0_Pos 0 /*!< Data output toogle bit 0 */ +#define GPIO_DATAOUTTGL_PIN1_Pos 1 /*!< Data output toogle bit 1 */ +#define GPIO_DATAOUTTGL_PIN2_Pos 2 /*!< Data output toogle bit 2 */ +#define GPIO_DATAOUTTGL_PIN3_Pos 3 /*!< Data output toogle bit 3 */ +#define GPIO_DATAOUTTGL_PIN4_Pos 4 /*!< Data output toogle bit 4 */ +#define GPIO_DATAOUTTGL_PIN5_Pos 5 /*!< Data output toogle bit 5 */ +#define GPIO_DATAOUTTGL_PIN6_Pos 6 /*!< Data output toogle bit 6 */ +#define GPIO_DATAOUTTGL_PIN7_Pos 7 /*!< Data output toogle bit 7 */ +#define GPIO_DATAOUTTGL_PIN8_Pos 8 /*!< Data output toogle bit 8 */ +#define GPIO_DATAOUTTGL_PIN9_Pos 9 /*!< Data output toogle bit 9 */ +#define GPIO_DATAOUTTGL_PIN10_Pos 10 /*!< Data output toogle bit 10 */ +#define GPIO_DATAOUTTGL_PIN11_Pos 11 /*!< Data output toogle bit 11 */ +#define GPIO_DATAOUTTGL_PIN12_Pos 12 /*!< Data output toogle bit 12 */ +#define GPIO_DATAOUTTGL_PIN13_Pos 13 /*!< Data output toogle bit 13 */ +#define GPIO_DATAOUTTGL_PIN14_Pos 14 /*!< Data output toogle bit 14 */ +#define GPIO_DATAOUTTGL_PIN15_Pos 15 /*!< Data output toogle bit 15 */ + +/* Bit field masks: */ +#define GPIO_DATAOUTTGL_PIN0_Msk 0x00000001UL /*!< Data output toogle bit 0 */ +#define GPIO_DATAOUTTGL_PIN1_Msk 0x00000002UL /*!< Data output toogle bit 1 */ +#define GPIO_DATAOUTTGL_PIN2_Msk 0x00000004UL /*!< Data output toogle bit 2 */ +#define GPIO_DATAOUTTGL_PIN3_Msk 0x00000008UL /*!< Data output toogle bit 3 */ +#define GPIO_DATAOUTTGL_PIN4_Msk 0x00000010UL /*!< Data output toogle bit 4 */ +#define GPIO_DATAOUTTGL_PIN5_Msk 0x00000020UL /*!< Data output toogle bit 5 */ +#define GPIO_DATAOUTTGL_PIN6_Msk 0x00000040UL /*!< Data output toogle bit 6 */ +#define GPIO_DATAOUTTGL_PIN7_Msk 0x00000080UL /*!< Data output toogle bit 7 */ +#define GPIO_DATAOUTTGL_PIN8_Msk 0x00000100UL /*!< Data output toogle bit 8 */ +#define GPIO_DATAOUTTGL_PIN9_Msk 0x00000200UL /*!< Data output toogle bit 9 */ +#define GPIO_DATAOUTTGL_PIN10_Msk 0x00000400UL /*!< Data output toogle bit 10 */ +#define GPIO_DATAOUTTGL_PIN11_Msk 0x00000800UL /*!< Data output toogle bit 11 */ +#define GPIO_DATAOUTTGL_PIN12_Msk 0x00001000UL /*!< Data output toogle bit 12 */ +#define GPIO_DATAOUTTGL_PIN13_Msk 0x00002000UL /*!< Data output toogle bit 13 */ +#define GPIO_DATAOUTTGL_PIN14_Msk 0x00004000UL /*!< Data output toogle bit 14 */ +#define GPIO_DATAOUTTGL_PIN15_Msk 0x00008000UL /*!< Data output toogle bit 15 */ + +/*-- DENSET: Digital function (PAD) enable register ----------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< Digital function (PAD) enable on pin 0 */ + uint32_t PIN1 :1; /*!< Digital function (PAD) enable on pin 1 */ + uint32_t PIN2 :1; /*!< Digital function (PAD) enable on pin 2 */ + uint32_t PIN3 :1; /*!< Digital function (PAD) enable on pin 3 */ + uint32_t PIN4 :1; /*!< Digital function (PAD) enable on pin 4 */ + uint32_t PIN5 :1; /*!< Digital function (PAD) enable on pin 5 */ + uint32_t PIN6 :1; /*!< Digital function (PAD) enable on pin 6 */ + uint32_t PIN7 :1; /*!< Digital function (PAD) enable on pin 7 */ + uint32_t PIN8 :1; /*!< Digital function (PAD) enable on pin 8 */ + uint32_t PIN9 :1; /*!< Digital function (PAD) enable on pin 9 */ + uint32_t PIN10 :1; /*!< Digital function (PAD) enable on pin 10 */ + uint32_t PIN11 :1; /*!< Digital function (PAD) enable on pin 11 */ + uint32_t PIN12 :1; /*!< Digital function (PAD) enable on pin 12 */ + uint32_t PIN13 :1; /*!< Digital function (PAD) enable on pin 13 */ + uint32_t PIN14 :1; /*!< Digital function (PAD) enable on pin 14 */ + uint32_t PIN15 :1; /*!< Digital function (PAD) enable on pin 15 */ +} _GPIO_DENSET_bits; + +/* Bit field positions: */ +#define GPIO_DENSET_PIN0_Pos 0 /*!< Digital function (PAD) enable on pin 0 */ +#define GPIO_DENSET_PIN1_Pos 1 /*!< Digital function (PAD) enable on pin 1 */ +#define GPIO_DENSET_PIN2_Pos 2 /*!< Digital function (PAD) enable on pin 2 */ +#define GPIO_DENSET_PIN3_Pos 3 /*!< Digital function (PAD) enable on pin 3 */ +#define GPIO_DENSET_PIN4_Pos 4 /*!< Digital function (PAD) enable on pin 4 */ +#define GPIO_DENSET_PIN5_Pos 5 /*!< Digital function (PAD) enable on pin 5 */ +#define GPIO_DENSET_PIN6_Pos 6 /*!< Digital function (PAD) enable on pin 6 */ +#define GPIO_DENSET_PIN7_Pos 7 /*!< Digital function (PAD) enable on pin 7 */ +#define GPIO_DENSET_PIN8_Pos 8 /*!< Digital function (PAD) enable on pin 8 */ +#define GPIO_DENSET_PIN9_Pos 9 /*!< Digital function (PAD) enable on pin 9 */ +#define GPIO_DENSET_PIN10_Pos 10 /*!< Digital function (PAD) enable on pin 10 */ +#define GPIO_DENSET_PIN11_Pos 11 /*!< Digital function (PAD) enable on pin 11 */ +#define GPIO_DENSET_PIN12_Pos 12 /*!< Digital function (PAD) enable on pin 12 */ +#define GPIO_DENSET_PIN13_Pos 13 /*!< Digital function (PAD) enable on pin 13 */ +#define GPIO_DENSET_PIN14_Pos 14 /*!< Digital function (PAD) enable on pin 14 */ +#define GPIO_DENSET_PIN15_Pos 15 /*!< Digital function (PAD) enable on pin 15 */ + +/* Bit field masks: */ +#define GPIO_DENSET_PIN0_Msk 0x00000001UL /*!< Digital function (PAD) enable on pin 0 */ +#define GPIO_DENSET_PIN1_Msk 0x00000002UL /*!< Digital function (PAD) enable on pin 1 */ +#define GPIO_DENSET_PIN2_Msk 0x00000004UL /*!< Digital function (PAD) enable on pin 2 */ +#define GPIO_DENSET_PIN3_Msk 0x00000008UL /*!< Digital function (PAD) enable on pin 3 */ +#define GPIO_DENSET_PIN4_Msk 0x00000010UL /*!< Digital function (PAD) enable on pin 4 */ +#define GPIO_DENSET_PIN5_Msk 0x00000020UL /*!< Digital function (PAD) enable on pin 5 */ +#define GPIO_DENSET_PIN6_Msk 0x00000040UL /*!< Digital function (PAD) enable on pin 6 */ +#define GPIO_DENSET_PIN7_Msk 0x00000080UL /*!< Digital function (PAD) enable on pin 7 */ +#define GPIO_DENSET_PIN8_Msk 0x00000100UL /*!< Digital function (PAD) enable on pin 8 */ +#define GPIO_DENSET_PIN9_Msk 0x00000200UL /*!< Digital function (PAD) enable on pin 9 */ +#define GPIO_DENSET_PIN10_Msk 0x00000400UL /*!< Digital function (PAD) enable on pin 10 */ +#define GPIO_DENSET_PIN11_Msk 0x00000800UL /*!< Digital function (PAD) enable on pin 11 */ +#define GPIO_DENSET_PIN12_Msk 0x00001000UL /*!< Digital function (PAD) enable on pin 12 */ +#define GPIO_DENSET_PIN13_Msk 0x00002000UL /*!< Digital function (PAD) enable on pin 13 */ +#define GPIO_DENSET_PIN14_Msk 0x00004000UL /*!< Digital function (PAD) enable on pin 14 */ +#define GPIO_DENSET_PIN15_Msk 0x00008000UL /*!< Digital function (PAD) enable on pin 15 */ + +/*-- DENCLR: Digital function (PAD) disable register ---------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< Digital function (PAD) disable on pin 0 */ + uint32_t PIN1 :1; /*!< Digital function (PAD) disable on pin 1 */ + uint32_t PIN2 :1; /*!< Digital function (PAD) disable on pin 2 */ + uint32_t PIN3 :1; /*!< Digital function (PAD) disable on pin 3 */ + uint32_t PIN4 :1; /*!< Digital function (PAD) disable on pin 4 */ + uint32_t PIN5 :1; /*!< Digital function (PAD) disable on pin 5 */ + uint32_t PIN6 :1; /*!< Digital function (PAD) disable on pin 6 */ + uint32_t PIN7 :1; /*!< Digital function (PAD) disable on pin 7 */ + uint32_t PIN8 :1; /*!< Digital function (PAD) disable on pin 8 */ + uint32_t PIN9 :1; /*!< Digital function (PAD) disable on pin 9 */ + uint32_t PIN10 :1; /*!< Digital function (PAD) disable on pin 10 */ + uint32_t PIN11 :1; /*!< Digital function (PAD) disable on pin 11 */ + uint32_t PIN12 :1; /*!< Digital function (PAD) disable on pin 12 */ + uint32_t PIN13 :1; /*!< Digital function (PAD) disable on pin 13 */ + uint32_t PIN14 :1; /*!< Digital function (PAD) disable on pin 14 */ + uint32_t PIN15 :1; /*!< Digital function (PAD) disable on pin 15 */ +} _GPIO_DENCLR_bits; + +/* Bit field positions: */ +#define GPIO_DENCLR_PIN0_Pos 0 /*!< Digital function (PAD) disable on pin 0 */ +#define GPIO_DENCLR_PIN1_Pos 1 /*!< Digital function (PAD) disable on pin 1 */ +#define GPIO_DENCLR_PIN2_Pos 2 /*!< Digital function (PAD) disable on pin 2 */ +#define GPIO_DENCLR_PIN3_Pos 3 /*!< Digital function (PAD) disable on pin 3 */ +#define GPIO_DENCLR_PIN4_Pos 4 /*!< Digital function (PAD) disable on pin 4 */ +#define GPIO_DENCLR_PIN5_Pos 5 /*!< Digital function (PAD) disable on pin 5 */ +#define GPIO_DENCLR_PIN6_Pos 6 /*!< Digital function (PAD) disable on pin 6 */ +#define GPIO_DENCLR_PIN7_Pos 7 /*!< Digital function (PAD) disable on pin 7 */ +#define GPIO_DENCLR_PIN8_Pos 8 /*!< Digital function (PAD) disable on pin 8 */ +#define GPIO_DENCLR_PIN9_Pos 9 /*!< Digital function (PAD) disable on pin 9 */ +#define GPIO_DENCLR_PIN10_Pos 10 /*!< Digital function (PAD) disable on pin 10 */ +#define GPIO_DENCLR_PIN11_Pos 11 /*!< Digital function (PAD) disable on pin 11 */ +#define GPIO_DENCLR_PIN12_Pos 12 /*!< Digital function (PAD) disable on pin 12 */ +#define GPIO_DENCLR_PIN13_Pos 13 /*!< Digital function (PAD) disable on pin 13 */ +#define GPIO_DENCLR_PIN14_Pos 14 /*!< Digital function (PAD) disable on pin 14 */ +#define GPIO_DENCLR_PIN15_Pos 15 /*!< Digital function (PAD) disable on pin 15 */ + +/* Bit field masks: */ +#define GPIO_DENCLR_PIN0_Msk 0x00000001UL /*!< Digital function (PAD) disable on pin 0 */ +#define GPIO_DENCLR_PIN1_Msk 0x00000002UL /*!< Digital function (PAD) disable on pin 1 */ +#define GPIO_DENCLR_PIN2_Msk 0x00000004UL /*!< Digital function (PAD) disable on pin 2 */ +#define GPIO_DENCLR_PIN3_Msk 0x00000008UL /*!< Digital function (PAD) disable on pin 3 */ +#define GPIO_DENCLR_PIN4_Msk 0x00000010UL /*!< Digital function (PAD) disable on pin 4 */ +#define GPIO_DENCLR_PIN5_Msk 0x00000020UL /*!< Digital function (PAD) disable on pin 5 */ +#define GPIO_DENCLR_PIN6_Msk 0x00000040UL /*!< Digital function (PAD) disable on pin 6 */ +#define GPIO_DENCLR_PIN7_Msk 0x00000080UL /*!< Digital function (PAD) disable on pin 7 */ +#define GPIO_DENCLR_PIN8_Msk 0x00000100UL /*!< Digital function (PAD) disable on pin 8 */ +#define GPIO_DENCLR_PIN9_Msk 0x00000200UL /*!< Digital function (PAD) disable on pin 9 */ +#define GPIO_DENCLR_PIN10_Msk 0x00000400UL /*!< Digital function (PAD) disable on pin 10 */ +#define GPIO_DENCLR_PIN11_Msk 0x00000800UL /*!< Digital function (PAD) disable on pin 11 */ +#define GPIO_DENCLR_PIN12_Msk 0x00001000UL /*!< Digital function (PAD) disable on pin 12 */ +#define GPIO_DENCLR_PIN13_Msk 0x00002000UL /*!< Digital function (PAD) disable on pin 13 */ +#define GPIO_DENCLR_PIN14_Msk 0x00004000UL /*!< Digital function (PAD) disable on pin 14 */ +#define GPIO_DENCLR_PIN15_Msk 0x00008000UL /*!< Digital function (PAD) disable on pin 15 */ + +/*-- INMODE: Select input mode register ----------------------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :2; /*!< Select input mode for pin 0 */ + uint32_t PIN1 :2; /*!< Select input mode for pin 1 */ + uint32_t PIN2 :2; /*!< Select input mode for pin 2 */ + uint32_t PIN3 :2; /*!< Select input mode for pin 3 */ + uint32_t PIN4 :2; /*!< Select input mode for pin 4 */ + uint32_t PIN5 :2; /*!< Select input mode for pin 5 */ + uint32_t PIN6 :2; /*!< Select input mode for pin 6 */ + uint32_t PIN7 :2; /*!< Select input mode for pin 7 */ + uint32_t PIN8 :2; /*!< Select input mode for pin 8 */ + uint32_t PIN9 :2; /*!< Select input mode for pin 9 */ + uint32_t PIN10 :2; /*!< Select input mode for pin 10 */ + uint32_t PIN11 :2; /*!< Select input mode for pin 11 */ + uint32_t PIN12 :2; /*!< Select input mode for pin 12 */ + uint32_t PIN13 :2; /*!< Select input mode for pin 13 */ + uint32_t PIN14 :2; /*!< Select input mode for pin 14 */ + uint32_t PIN15 :2; /*!< Select input mode for pin 15 */ +} _GPIO_INMODE_bits; + +/* Bit field positions: */ +#define GPIO_INMODE_PIN0_Pos 0 /*!< Select input mode for pin 0 */ +#define GPIO_INMODE_PIN1_Pos 2 /*!< Select input mode for pin 1 */ +#define GPIO_INMODE_PIN2_Pos 4 /*!< Select input mode for pin 2 */ +#define GPIO_INMODE_PIN3_Pos 6 /*!< Select input mode for pin 3 */ +#define GPIO_INMODE_PIN4_Pos 8 /*!< Select input mode for pin 4 */ +#define GPIO_INMODE_PIN5_Pos 10 /*!< Select input mode for pin 5 */ +#define GPIO_INMODE_PIN6_Pos 12 /*!< Select input mode for pin 6 */ +#define GPIO_INMODE_PIN7_Pos 14 /*!< Select input mode for pin 7 */ +#define GPIO_INMODE_PIN8_Pos 16 /*!< Select input mode for pin 8 */ +#define GPIO_INMODE_PIN9_Pos 18 /*!< Select input mode for pin 9 */ +#define GPIO_INMODE_PIN10_Pos 20 /*!< Select input mode for pin 10 */ +#define GPIO_INMODE_PIN11_Pos 22 /*!< Select input mode for pin 11 */ +#define GPIO_INMODE_PIN12_Pos 24 /*!< Select input mode for pin 12 */ +#define GPIO_INMODE_PIN13_Pos 26 /*!< Select input mode for pin 13 */ +#define GPIO_INMODE_PIN14_Pos 28 /*!< Select input mode for pin 14 */ +#define GPIO_INMODE_PIN15_Pos 30 /*!< Select input mode for pin 15 */ + +/* Bit field masks: */ +#define GPIO_INMODE_PIN0_Msk 0x00000003UL /*!< Select input mode for pin 0 */ +#define GPIO_INMODE_PIN1_Msk 0x0000000CUL /*!< Select input mode for pin 1 */ +#define GPIO_INMODE_PIN2_Msk 0x00000030UL /*!< Select input mode for pin 2 */ +#define GPIO_INMODE_PIN3_Msk 0x000000C0UL /*!< Select input mode for pin 3 */ +#define GPIO_INMODE_PIN4_Msk 0x00000300UL /*!< Select input mode for pin 4 */ +#define GPIO_INMODE_PIN5_Msk 0x00000C00UL /*!< Select input mode for pin 5 */ +#define GPIO_INMODE_PIN6_Msk 0x00003000UL /*!< Select input mode for pin 6 */ +#define GPIO_INMODE_PIN7_Msk 0x0000C000UL /*!< Select input mode for pin 7 */ +#define GPIO_INMODE_PIN8_Msk 0x00030000UL /*!< Select input mode for pin 8 */ +#define GPIO_INMODE_PIN9_Msk 0x000C0000UL /*!< Select input mode for pin 9 */ +#define GPIO_INMODE_PIN10_Msk 0x00300000UL /*!< Select input mode for pin 10 */ +#define GPIO_INMODE_PIN11_Msk 0x00C00000UL /*!< Select input mode for pin 11 */ +#define GPIO_INMODE_PIN12_Msk 0x03000000UL /*!< Select input mode for pin 12 */ +#define GPIO_INMODE_PIN13_Msk 0x0C000000UL /*!< Select input mode for pin 13 */ +#define GPIO_INMODE_PIN14_Msk 0x30000000UL /*!< Select input mode for pin 14 */ +#define GPIO_INMODE_PIN15_Msk 0xC0000000UL /*!< Select input mode for pin 15 */ + +/* Bit field enums: */ +typedef enum { + GPIO_INMODE_PIN0_Schmitt = 0x0UL, /*!< Scmitt buffer */ + GPIO_INMODE_PIN0_CMOS = 0x1UL, /*!< CMOS buffer */ + GPIO_INMODE_PIN0_Disable = 0x3UL, /*!< Input buffer disabled */ +} GPIO_INMODE_PIN0_Enum; + +typedef enum { + GPIO_INMODE_PIN1_Schmitt = 0x0UL, /*!< Scmitt buffer */ + GPIO_INMODE_PIN1_CMOS = 0x1UL, /*!< CMOS buffer */ + GPIO_INMODE_PIN1_Disable = 0x3UL, /*!< Input buffer disabled */ +} GPIO_INMODE_PIN1_Enum; + +typedef enum { + GPIO_INMODE_PIN2_Schmitt = 0x0UL, /*!< Scmitt buffer */ + GPIO_INMODE_PIN2_CMOS = 0x1UL, /*!< CMOS buffer */ + GPIO_INMODE_PIN2_Disable = 0x3UL, /*!< Input buffer disabled */ +} GPIO_INMODE_PIN2_Enum; + +typedef enum { + GPIO_INMODE_PIN3_Schmitt = 0x0UL, /*!< Scmitt buffer */ + GPIO_INMODE_PIN3_CMOS = 0x1UL, /*!< CMOS buffer */ + GPIO_INMODE_PIN3_Disable = 0x3UL, /*!< Input buffer disabled */ +} GPIO_INMODE_PIN3_Enum; + +typedef enum { + GPIO_INMODE_PIN4_Schmitt = 0x0UL, /*!< Scmitt buffer */ + GPIO_INMODE_PIN4_CMOS = 0x1UL, /*!< CMOS buffer */ + GPIO_INMODE_PIN4_Disable = 0x3UL, /*!< Input buffer disabled */ +} GPIO_INMODE_PIN4_Enum; + +typedef enum { + GPIO_INMODE_PIN5_Schmitt = 0x0UL, /*!< Scmitt buffer */ + GPIO_INMODE_PIN5_CMOS = 0x1UL, /*!< CMOS buffer */ + GPIO_INMODE_PIN5_Disable = 0x3UL, /*!< Input buffer disabled */ +} GPIO_INMODE_PIN5_Enum; + +typedef enum { + GPIO_INMODE_PIN6_Schmitt = 0x0UL, /*!< Scmitt buffer */ + GPIO_INMODE_PIN6_CMOS = 0x1UL, /*!< CMOS buffer */ + GPIO_INMODE_PIN6_Disable = 0x3UL, /*!< Input buffer disabled */ +} GPIO_INMODE_PIN6_Enum; + +typedef enum { + GPIO_INMODE_PIN7_Schmitt = 0x0UL, /*!< Scmitt buffer */ + GPIO_INMODE_PIN7_CMOS = 0x1UL, /*!< CMOS buffer */ + GPIO_INMODE_PIN7_Disable = 0x3UL, /*!< Input buffer disabled */ +} GPIO_INMODE_PIN7_Enum; + +typedef enum { + GPIO_INMODE_PIN8_Schmitt = 0x0UL, /*!< Scmitt buffer */ + GPIO_INMODE_PIN8_CMOS = 0x1UL, /*!< CMOS buffer */ + GPIO_INMODE_PIN8_Disable = 0x3UL, /*!< Input buffer disabled */ +} GPIO_INMODE_PIN8_Enum; + +typedef enum { + GPIO_INMODE_PIN9_Schmitt = 0x0UL, /*!< Scmitt buffer */ + GPIO_INMODE_PIN9_CMOS = 0x1UL, /*!< CMOS buffer */ + GPIO_INMODE_PIN9_Disable = 0x3UL, /*!< Input buffer disabled */ +} GPIO_INMODE_PIN9_Enum; + +typedef enum { + GPIO_INMODE_PIN10_Schmitt = 0x0UL, /*!< Scmitt buffer */ + GPIO_INMODE_PIN10_CMOS = 0x1UL, /*!< CMOS buffer */ + GPIO_INMODE_PIN10_Disable = 0x3UL, /*!< Input buffer disabled */ +} GPIO_INMODE_PIN10_Enum; + +typedef enum { + GPIO_INMODE_PIN11_Schmitt = 0x0UL, /*!< Scmitt buffer */ + GPIO_INMODE_PIN11_CMOS = 0x1UL, /*!< CMOS buffer */ + GPIO_INMODE_PIN11_Disable = 0x3UL, /*!< Input buffer disabled */ +} GPIO_INMODE_PIN11_Enum; + +typedef enum { + GPIO_INMODE_PIN12_Schmitt = 0x0UL, /*!< Scmitt buffer */ + GPIO_INMODE_PIN12_CMOS = 0x1UL, /*!< CMOS buffer */ + GPIO_INMODE_PIN12_Disable = 0x3UL, /*!< Input buffer disabled */ +} GPIO_INMODE_PIN12_Enum; + +typedef enum { + GPIO_INMODE_PIN13_Schmitt = 0x0UL, /*!< Scmitt buffer */ + GPIO_INMODE_PIN13_CMOS = 0x1UL, /*!< CMOS buffer */ + GPIO_INMODE_PIN13_Disable = 0x3UL, /*!< Input buffer disabled */ +} GPIO_INMODE_PIN13_Enum; + +typedef enum { + GPIO_INMODE_PIN14_Schmitt = 0x0UL, /*!< Scmitt buffer */ + GPIO_INMODE_PIN14_CMOS = 0x1UL, /*!< CMOS buffer */ + GPIO_INMODE_PIN14_Disable = 0x3UL, /*!< Input buffer disabled */ +} GPIO_INMODE_PIN14_Enum; + +typedef enum { + GPIO_INMODE_PIN15_Schmitt = 0x0UL, /*!< Scmitt buffer */ + GPIO_INMODE_PIN15_CMOS = 0x1UL, /*!< CMOS buffer */ + GPIO_INMODE_PIN15_Disable = 0x3UL, /*!< Input buffer disabled */ +} GPIO_INMODE_PIN15_Enum; + +/*-- PULLMODE: Select pull mode register ---------------------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :2; /*!< Select pull mode for pin 0 */ + uint32_t PIN1 :2; /*!< Select pull mode for pin 1 */ + uint32_t PIN2 :2; /*!< Select pull mode for pin 2 */ + uint32_t PIN3 :2; /*!< Select pull mode for pin 3 */ + uint32_t PIN4 :2; /*!< Select pull mode for pin 4 */ + uint32_t PIN5 :2; /*!< Select pull mode for pin 5 */ + uint32_t PIN6 :2; /*!< Select pull mode for pin 6 */ + uint32_t PIN7 :2; /*!< Select pull mode for pin 7 */ + uint32_t PIN8 :2; /*!< Select pull mode for pin 8 */ + uint32_t PIN9 :2; /*!< Select pull mode for pin 9 */ + uint32_t PIN10 :2; /*!< Select pull mode for pin 10 */ + uint32_t PIN11 :2; /*!< Select pull mode for pin 11 */ + uint32_t PIN12 :2; /*!< Select pull mode for pin 12 */ + uint32_t PIN13 :2; /*!< Select pull mode for pin 13 */ + uint32_t PIN14 :2; /*!< Select pull mode for pin 14 */ + uint32_t PIN15 :2; /*!< Select pull mode for pin 15 */ +} _GPIO_PULLMODE_bits; + +/* Bit field positions: */ +#define GPIO_PULLMODE_PIN0_Pos 0 /*!< Select pull mode for pin 0 */ +#define GPIO_PULLMODE_PIN1_Pos 2 /*!< Select pull mode for pin 1 */ +#define GPIO_PULLMODE_PIN2_Pos 4 /*!< Select pull mode for pin 2 */ +#define GPIO_PULLMODE_PIN3_Pos 6 /*!< Select pull mode for pin 3 */ +#define GPIO_PULLMODE_PIN4_Pos 8 /*!< Select pull mode for pin 4 */ +#define GPIO_PULLMODE_PIN5_Pos 10 /*!< Select pull mode for pin 5 */ +#define GPIO_PULLMODE_PIN6_Pos 12 /*!< Select pull mode for pin 6 */ +#define GPIO_PULLMODE_PIN7_Pos 14 /*!< Select pull mode for pin 7 */ +#define GPIO_PULLMODE_PIN8_Pos 16 /*!< Select pull mode for pin 8 */ +#define GPIO_PULLMODE_PIN9_Pos 18 /*!< Select pull mode for pin 9 */ +#define GPIO_PULLMODE_PIN10_Pos 20 /*!< Select pull mode for pin 10 */ +#define GPIO_PULLMODE_PIN11_Pos 22 /*!< Select pull mode for pin 11 */ +#define GPIO_PULLMODE_PIN12_Pos 24 /*!< Select pull mode for pin 12 */ +#define GPIO_PULLMODE_PIN13_Pos 26 /*!< Select pull mode for pin 13 */ +#define GPIO_PULLMODE_PIN14_Pos 28 /*!< Select pull mode for pin 14 */ +#define GPIO_PULLMODE_PIN15_Pos 30 /*!< Select pull mode for pin 15 */ + +/* Bit field masks: */ +#define GPIO_PULLMODE_PIN0_Msk 0x00000003UL /*!< Select pull mode for pin 0 */ +#define GPIO_PULLMODE_PIN1_Msk 0x0000000CUL /*!< Select pull mode for pin 1 */ +#define GPIO_PULLMODE_PIN2_Msk 0x00000030UL /*!< Select pull mode for pin 2 */ +#define GPIO_PULLMODE_PIN3_Msk 0x000000C0UL /*!< Select pull mode for pin 3 */ +#define GPIO_PULLMODE_PIN4_Msk 0x00000300UL /*!< Select pull mode for pin 4 */ +#define GPIO_PULLMODE_PIN5_Msk 0x00000C00UL /*!< Select pull mode for pin 5 */ +#define GPIO_PULLMODE_PIN6_Msk 0x00003000UL /*!< Select pull mode for pin 6 */ +#define GPIO_PULLMODE_PIN7_Msk 0x0000C000UL /*!< Select pull mode for pin 7 */ +#define GPIO_PULLMODE_PIN8_Msk 0x00030000UL /*!< Select pull mode for pin 8 */ +#define GPIO_PULLMODE_PIN9_Msk 0x000C0000UL /*!< Select pull mode for pin 9 */ +#define GPIO_PULLMODE_PIN10_Msk 0x00300000UL /*!< Select pull mode for pin 10 */ +#define GPIO_PULLMODE_PIN11_Msk 0x00C00000UL /*!< Select pull mode for pin 11 */ +#define GPIO_PULLMODE_PIN12_Msk 0x03000000UL /*!< Select pull mode for pin 12 */ +#define GPIO_PULLMODE_PIN13_Msk 0x0C000000UL /*!< Select pull mode for pin 13 */ +#define GPIO_PULLMODE_PIN14_Msk 0x30000000UL /*!< Select pull mode for pin 14 */ +#define GPIO_PULLMODE_PIN15_Msk 0xC0000000UL /*!< Select pull mode for pin 15 */ + +/* Bit field enums: */ +typedef enum { + GPIO_PULLMODE_PIN0_Disable = 0x0UL, /*!< Pull disabled */ + GPIO_PULLMODE_PIN0_PU = 0x1UL, /*!< Pull-up */ + GPIO_PULLMODE_PIN0_PD = 0x2UL, /*!< Pull-down */ +} GPIO_PULLMODE_PIN0_Enum; + +typedef enum { + GPIO_PULLMODE_PIN1_Disable = 0x0UL, /*!< Pull disabled */ + GPIO_PULLMODE_PIN1_PU = 0x1UL, /*!< Pull-up */ + GPIO_PULLMODE_PIN1_PD = 0x2UL, /*!< Pull-down */ +} GPIO_PULLMODE_PIN1_Enum; + +typedef enum { + GPIO_PULLMODE_PIN2_Disable = 0x0UL, /*!< Pull disabled */ + GPIO_PULLMODE_PIN2_PU = 0x1UL, /*!< Pull-up */ + GPIO_PULLMODE_PIN2_PD = 0x2UL, /*!< Pull-down */ +} GPIO_PULLMODE_PIN2_Enum; + +typedef enum { + GPIO_PULLMODE_PIN3_Disable = 0x0UL, /*!< Pull disabled */ + GPIO_PULLMODE_PIN3_PU = 0x1UL, /*!< Pull-up */ + GPIO_PULLMODE_PIN3_PD = 0x2UL, /*!< Pull-down */ +} GPIO_PULLMODE_PIN3_Enum; + +typedef enum { + GPIO_PULLMODE_PIN4_Disable = 0x0UL, /*!< Pull disabled */ + GPIO_PULLMODE_PIN4_PU = 0x1UL, /*!< Pull-up */ + GPIO_PULLMODE_PIN4_PD = 0x2UL, /*!< Pull-down */ +} GPIO_PULLMODE_PIN4_Enum; + +typedef enum { + GPIO_PULLMODE_PIN5_Disable = 0x0UL, /*!< Pull disabled */ + GPIO_PULLMODE_PIN5_PU = 0x1UL, /*!< Pull-up */ + GPIO_PULLMODE_PIN5_PD = 0x2UL, /*!< Pull-down */ +} GPIO_PULLMODE_PIN5_Enum; + +typedef enum { + GPIO_PULLMODE_PIN6_Disable = 0x0UL, /*!< Pull disabled */ + GPIO_PULLMODE_PIN6_PU = 0x1UL, /*!< Pull-up */ + GPIO_PULLMODE_PIN6_PD = 0x2UL, /*!< Pull-down */ +} GPIO_PULLMODE_PIN6_Enum; + +typedef enum { + GPIO_PULLMODE_PIN7_Disable = 0x0UL, /*!< Pull disabled */ + GPIO_PULLMODE_PIN7_PU = 0x1UL, /*!< Pull-up */ + GPIO_PULLMODE_PIN7_PD = 0x2UL, /*!< Pull-down */ +} GPIO_PULLMODE_PIN7_Enum; + +typedef enum { + GPIO_PULLMODE_PIN8_Disable = 0x0UL, /*!< Pull disabled */ + GPIO_PULLMODE_PIN8_PU = 0x1UL, /*!< Pull-up */ + GPIO_PULLMODE_PIN8_PD = 0x2UL, /*!< Pull-down */ +} GPIO_PULLMODE_PIN8_Enum; + +typedef enum { + GPIO_PULLMODE_PIN9_Disable = 0x0UL, /*!< Pull disabled */ + GPIO_PULLMODE_PIN9_PU = 0x1UL, /*!< Pull-up */ + GPIO_PULLMODE_PIN9_PD = 0x2UL, /*!< Pull-down */ +} GPIO_PULLMODE_PIN9_Enum; + +typedef enum { + GPIO_PULLMODE_PIN10_Disable = 0x0UL, /*!< Pull disabled */ + GPIO_PULLMODE_PIN10_PU = 0x1UL, /*!< Pull-up */ + GPIO_PULLMODE_PIN10_PD = 0x2UL, /*!< Pull-down */ +} GPIO_PULLMODE_PIN10_Enum; + +typedef enum { + GPIO_PULLMODE_PIN11_Disable = 0x0UL, /*!< Pull disabled */ + GPIO_PULLMODE_PIN11_PU = 0x1UL, /*!< Pull-up */ + GPIO_PULLMODE_PIN11_PD = 0x2UL, /*!< Pull-down */ +} GPIO_PULLMODE_PIN11_Enum; + +typedef enum { + GPIO_PULLMODE_PIN12_Disable = 0x0UL, /*!< Pull disabled */ + GPIO_PULLMODE_PIN12_PU = 0x1UL, /*!< Pull-up */ + GPIO_PULLMODE_PIN12_PD = 0x2UL, /*!< Pull-down */ +} GPIO_PULLMODE_PIN12_Enum; + +typedef enum { + GPIO_PULLMODE_PIN13_Disable = 0x0UL, /*!< Pull disabled */ + GPIO_PULLMODE_PIN13_PU = 0x1UL, /*!< Pull-up */ + GPIO_PULLMODE_PIN13_PD = 0x2UL, /*!< Pull-down */ +} GPIO_PULLMODE_PIN13_Enum; + +typedef enum { + GPIO_PULLMODE_PIN14_Disable = 0x0UL, /*!< Pull disabled */ + GPIO_PULLMODE_PIN14_PU = 0x1UL, /*!< Pull-up */ + GPIO_PULLMODE_PIN14_PD = 0x2UL, /*!< Pull-down */ +} GPIO_PULLMODE_PIN14_Enum; + +typedef enum { + GPIO_PULLMODE_PIN15_Disable = 0x0UL, /*!< Pull disabled */ + GPIO_PULLMODE_PIN15_PU = 0x1UL, /*!< Pull-up */ + GPIO_PULLMODE_PIN15_PD = 0x2UL, /*!< Pull-down */ +} GPIO_PULLMODE_PIN15_Enum; + +/*-- OUTMODE: Select output mode register --------------------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :2; /*!< Select output mode for pin 0 */ + uint32_t PIN1 :2; /*!< Select output mode for pin 1 */ + uint32_t PIN2 :2; /*!< Select output mode for pin 2 */ + uint32_t PIN3 :2; /*!< Select output mode for pin 3 */ + uint32_t PIN4 :2; /*!< Select output mode for pin 4 */ + uint32_t PIN5 :2; /*!< Select output mode for pin 5 */ + uint32_t PIN6 :2; /*!< Select output mode for pin 6 */ + uint32_t PIN7 :2; /*!< Select output mode for pin 7 */ + uint32_t PIN8 :2; /*!< Select output mode for pin 8 */ + uint32_t PIN9 :2; /*!< Select output mode for pin 9 */ + uint32_t PIN10 :2; /*!< Select output mode for pin 10 */ + uint32_t PIN11 :2; /*!< Select output mode for pin 11 */ + uint32_t PIN12 :2; /*!< Select output mode for pin 12 */ + uint32_t PIN13 :2; /*!< Select output mode for pin 13 */ + uint32_t PIN14 :2; /*!< Select output mode for pin 14 */ + uint32_t PIN15 :2; /*!< Select output mode for pin 15 */ +} _GPIO_OUTMODE_bits; + +/* Bit field positions: */ +#define GPIO_OUTMODE_PIN0_Pos 0 /*!< Select output mode for pin 0 */ +#define GPIO_OUTMODE_PIN1_Pos 2 /*!< Select output mode for pin 1 */ +#define GPIO_OUTMODE_PIN2_Pos 4 /*!< Select output mode for pin 2 */ +#define GPIO_OUTMODE_PIN3_Pos 6 /*!< Select output mode for pin 3 */ +#define GPIO_OUTMODE_PIN4_Pos 8 /*!< Select output mode for pin 4 */ +#define GPIO_OUTMODE_PIN5_Pos 10 /*!< Select output mode for pin 5 */ +#define GPIO_OUTMODE_PIN6_Pos 12 /*!< Select output mode for pin 6 */ +#define GPIO_OUTMODE_PIN7_Pos 14 /*!< Select output mode for pin 7 */ +#define GPIO_OUTMODE_PIN8_Pos 16 /*!< Select output mode for pin 8 */ +#define GPIO_OUTMODE_PIN9_Pos 18 /*!< Select output mode for pin 9 */ +#define GPIO_OUTMODE_PIN10_Pos 20 /*!< Select output mode for pin 10 */ +#define GPIO_OUTMODE_PIN11_Pos 22 /*!< Select output mode for pin 11 */ +#define GPIO_OUTMODE_PIN12_Pos 24 /*!< Select output mode for pin 12 */ +#define GPIO_OUTMODE_PIN13_Pos 26 /*!< Select output mode for pin 13 */ +#define GPIO_OUTMODE_PIN14_Pos 28 /*!< Select output mode for pin 14 */ +#define GPIO_OUTMODE_PIN15_Pos 30 /*!< Select output mode for pin 15 */ + +/* Bit field masks: */ +#define GPIO_OUTMODE_PIN0_Msk 0x00000003UL /*!< Select output mode for pin 0 */ +#define GPIO_OUTMODE_PIN1_Msk 0x0000000CUL /*!< Select output mode for pin 1 */ +#define GPIO_OUTMODE_PIN2_Msk 0x00000030UL /*!< Select output mode for pin 2 */ +#define GPIO_OUTMODE_PIN3_Msk 0x000000C0UL /*!< Select output mode for pin 3 */ +#define GPIO_OUTMODE_PIN4_Msk 0x00000300UL /*!< Select output mode for pin 4 */ +#define GPIO_OUTMODE_PIN5_Msk 0x00000C00UL /*!< Select output mode for pin 5 */ +#define GPIO_OUTMODE_PIN6_Msk 0x00003000UL /*!< Select output mode for pin 6 */ +#define GPIO_OUTMODE_PIN7_Msk 0x0000C000UL /*!< Select output mode for pin 7 */ +#define GPIO_OUTMODE_PIN8_Msk 0x00030000UL /*!< Select output mode for pin 8 */ +#define GPIO_OUTMODE_PIN9_Msk 0x000C0000UL /*!< Select output mode for pin 9 */ +#define GPIO_OUTMODE_PIN10_Msk 0x00300000UL /*!< Select output mode for pin 10 */ +#define GPIO_OUTMODE_PIN11_Msk 0x00C00000UL /*!< Select output mode for pin 11 */ +#define GPIO_OUTMODE_PIN12_Msk 0x03000000UL /*!< Select output mode for pin 12 */ +#define GPIO_OUTMODE_PIN13_Msk 0x0C000000UL /*!< Select output mode for pin 13 */ +#define GPIO_OUTMODE_PIN14_Msk 0x30000000UL /*!< Select output mode for pin 14 */ +#define GPIO_OUTMODE_PIN15_Msk 0xC0000000UL /*!< Select output mode for pin 15 */ + +/* Bit field enums: */ +typedef enum { + GPIO_OUTMODE_PIN0_PP = 0x0UL, /*!< Push-pull output */ + GPIO_OUTMODE_PIN0_OD = 0x1UL, /*!< Open drain output */ + GPIO_OUTMODE_PIN0_OS = 0x2UL, /*!< Open source output */ +} GPIO_OUTMODE_PIN0_Enum; + +typedef enum { + GPIO_OUTMODE_PIN1_PP = 0x0UL, /*!< Push-pull output */ + GPIO_OUTMODE_PIN1_OD = 0x1UL, /*!< Open drain output */ + GPIO_OUTMODE_PIN1_OS = 0x2UL, /*!< Open source output */ +} GPIO_OUTMODE_PIN1_Enum; + +typedef enum { + GPIO_OUTMODE_PIN2_PP = 0x0UL, /*!< Push-pull output */ + GPIO_OUTMODE_PIN2_OD = 0x1UL, /*!< Open drain output */ + GPIO_OUTMODE_PIN2_OS = 0x2UL, /*!< Open source output */ +} GPIO_OUTMODE_PIN2_Enum; + +typedef enum { + GPIO_OUTMODE_PIN3_PP = 0x0UL, /*!< Push-pull output */ + GPIO_OUTMODE_PIN3_OD = 0x1UL, /*!< Open drain output */ + GPIO_OUTMODE_PIN3_OS = 0x2UL, /*!< Open source output */ +} GPIO_OUTMODE_PIN3_Enum; + +typedef enum { + GPIO_OUTMODE_PIN4_PP = 0x0UL, /*!< Push-pull output */ + GPIO_OUTMODE_PIN4_OD = 0x1UL, /*!< Open drain output */ + GPIO_OUTMODE_PIN4_OS = 0x2UL, /*!< Open source output */ +} GPIO_OUTMODE_PIN4_Enum; + +typedef enum { + GPIO_OUTMODE_PIN5_PP = 0x0UL, /*!< Push-pull output */ + GPIO_OUTMODE_PIN5_OD = 0x1UL, /*!< Open drain output */ + GPIO_OUTMODE_PIN5_OS = 0x2UL, /*!< Open source output */ +} GPIO_OUTMODE_PIN5_Enum; + +typedef enum { + GPIO_OUTMODE_PIN6_PP = 0x0UL, /*!< Push-pull output */ + GPIO_OUTMODE_PIN6_OD = 0x1UL, /*!< Open drain output */ + GPIO_OUTMODE_PIN6_OS = 0x2UL, /*!< Open source output */ +} GPIO_OUTMODE_PIN6_Enum; + +typedef enum { + GPIO_OUTMODE_PIN7_PP = 0x0UL, /*!< Push-pull output */ + GPIO_OUTMODE_PIN7_OD = 0x1UL, /*!< Open drain output */ + GPIO_OUTMODE_PIN7_OS = 0x2UL, /*!< Open source output */ +} GPIO_OUTMODE_PIN7_Enum; + +typedef enum { + GPIO_OUTMODE_PIN8_PP = 0x0UL, /*!< Push-pull output */ + GPIO_OUTMODE_PIN8_OD = 0x1UL, /*!< Open drain output */ + GPIO_OUTMODE_PIN8_OS = 0x2UL, /*!< Open source output */ +} GPIO_OUTMODE_PIN8_Enum; + +typedef enum { + GPIO_OUTMODE_PIN9_PP = 0x0UL, /*!< Push-pull output */ + GPIO_OUTMODE_PIN9_OD = 0x1UL, /*!< Open drain output */ + GPIO_OUTMODE_PIN9_OS = 0x2UL, /*!< Open source output */ +} GPIO_OUTMODE_PIN9_Enum; + +typedef enum { + GPIO_OUTMODE_PIN10_PP = 0x0UL, /*!< Push-pull output */ + GPIO_OUTMODE_PIN10_OD = 0x1UL, /*!< Open drain output */ + GPIO_OUTMODE_PIN10_OS = 0x2UL, /*!< Open source output */ +} GPIO_OUTMODE_PIN10_Enum; + +typedef enum { + GPIO_OUTMODE_PIN11_PP = 0x0UL, /*!< Push-pull output */ + GPIO_OUTMODE_PIN11_OD = 0x1UL, /*!< Open drain output */ + GPIO_OUTMODE_PIN11_OS = 0x2UL, /*!< Open source output */ +} GPIO_OUTMODE_PIN11_Enum; + +typedef enum { + GPIO_OUTMODE_PIN12_PP = 0x0UL, /*!< Push-pull output */ + GPIO_OUTMODE_PIN12_OD = 0x1UL, /*!< Open drain output */ + GPIO_OUTMODE_PIN12_OS = 0x2UL, /*!< Open source output */ +} GPIO_OUTMODE_PIN12_Enum; + +typedef enum { + GPIO_OUTMODE_PIN13_PP = 0x0UL, /*!< Push-pull output */ + GPIO_OUTMODE_PIN13_OD = 0x1UL, /*!< Open drain output */ + GPIO_OUTMODE_PIN13_OS = 0x2UL, /*!< Open source output */ +} GPIO_OUTMODE_PIN13_Enum; + +typedef enum { + GPIO_OUTMODE_PIN14_PP = 0x0UL, /*!< Push-pull output */ + GPIO_OUTMODE_PIN14_OD = 0x1UL, /*!< Open drain output */ + GPIO_OUTMODE_PIN14_OS = 0x2UL, /*!< Open source output */ +} GPIO_OUTMODE_PIN14_Enum; + +typedef enum { + GPIO_OUTMODE_PIN15_PP = 0x0UL, /*!< Push-pull output */ + GPIO_OUTMODE_PIN15_OD = 0x1UL, /*!< Open drain output */ + GPIO_OUTMODE_PIN15_OS = 0x2UL, /*!< Open source output */ +} GPIO_OUTMODE_PIN15_Enum; + +/*-- DRIVEMODE: Select drive mode register -------------------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :2; /*!< Select drive mode for pin 0 */ + uint32_t PIN1 :2; /*!< Select drive mode for pin 1 */ + uint32_t PIN2 :2; /*!< Select drive mode for pin 2 */ + uint32_t PIN3 :2; /*!< Select drive mode for pin 3 */ + uint32_t PIN4 :2; /*!< Select drive mode for pin 4 */ + uint32_t PIN5 :2; /*!< Select drive mode for pin 5 */ + uint32_t PIN6 :2; /*!< Select drive mode for pin 6 */ + uint32_t PIN7 :2; /*!< Select drive mode for pin 7 */ + uint32_t PIN8 :2; /*!< Select drive mode for pin 8 */ + uint32_t PIN9 :2; /*!< Select drive mode for pin 9 */ + uint32_t PIN10 :2; /*!< Select drive mode for pin 10 */ + uint32_t PIN11 :2; /*!< Select drive mode for pin 11 */ + uint32_t PIN12 :2; /*!< Select drive mode for pin 12 */ + uint32_t PIN13 :2; /*!< Select drive mode for pin 13 */ + uint32_t PIN14 :2; /*!< Select drive mode for pin 14 */ + uint32_t PIN15 :2; /*!< Select drive mode for pin 15 */ +} _GPIO_DRIVEMODE_bits; + +/* Bit field positions: */ +#define GPIO_DRIVEMODE_PIN0_Pos 0 /*!< Select drive mode for pin 0 */ +#define GPIO_DRIVEMODE_PIN1_Pos 2 /*!< Select drive mode for pin 1 */ +#define GPIO_DRIVEMODE_PIN2_Pos 4 /*!< Select drive mode for pin 2 */ +#define GPIO_DRIVEMODE_PIN3_Pos 6 /*!< Select drive mode for pin 3 */ +#define GPIO_DRIVEMODE_PIN4_Pos 8 /*!< Select drive mode for pin 4 */ +#define GPIO_DRIVEMODE_PIN5_Pos 10 /*!< Select drive mode for pin 5 */ +#define GPIO_DRIVEMODE_PIN6_Pos 12 /*!< Select drive mode for pin 6 */ +#define GPIO_DRIVEMODE_PIN7_Pos 14 /*!< Select drive mode for pin 7 */ +#define GPIO_DRIVEMODE_PIN8_Pos 16 /*!< Select drive mode for pin 8 */ +#define GPIO_DRIVEMODE_PIN9_Pos 18 /*!< Select drive mode for pin 9 */ +#define GPIO_DRIVEMODE_PIN10_Pos 20 /*!< Select drive mode for pin 10 */ +#define GPIO_DRIVEMODE_PIN11_Pos 22 /*!< Select drive mode for pin 11 */ +#define GPIO_DRIVEMODE_PIN12_Pos 24 /*!< Select drive mode for pin 12 */ +#define GPIO_DRIVEMODE_PIN13_Pos 26 /*!< Select drive mode for pin 13 */ +#define GPIO_DRIVEMODE_PIN14_Pos 28 /*!< Select drive mode for pin 14 */ +#define GPIO_DRIVEMODE_PIN15_Pos 30 /*!< Select drive mode for pin 15 */ + +/* Bit field masks: */ +#define GPIO_DRIVEMODE_PIN0_Msk 0x00000003UL /*!< Select drive mode for pin 0 */ +#define GPIO_DRIVEMODE_PIN1_Msk 0x0000000CUL /*!< Select drive mode for pin 1 */ +#define GPIO_DRIVEMODE_PIN2_Msk 0x00000030UL /*!< Select drive mode for pin 2 */ +#define GPIO_DRIVEMODE_PIN3_Msk 0x000000C0UL /*!< Select drive mode for pin 3 */ +#define GPIO_DRIVEMODE_PIN4_Msk 0x00000300UL /*!< Select drive mode for pin 4 */ +#define GPIO_DRIVEMODE_PIN5_Msk 0x00000C00UL /*!< Select drive mode for pin 5 */ +#define GPIO_DRIVEMODE_PIN6_Msk 0x00003000UL /*!< Select drive mode for pin 6 */ +#define GPIO_DRIVEMODE_PIN7_Msk 0x0000C000UL /*!< Select drive mode for pin 7 */ +#define GPIO_DRIVEMODE_PIN8_Msk 0x00030000UL /*!< Select drive mode for pin 8 */ +#define GPIO_DRIVEMODE_PIN9_Msk 0x000C0000UL /*!< Select drive mode for pin 9 */ +#define GPIO_DRIVEMODE_PIN10_Msk 0x00300000UL /*!< Select drive mode for pin 10 */ +#define GPIO_DRIVEMODE_PIN11_Msk 0x00C00000UL /*!< Select drive mode for pin 11 */ +#define GPIO_DRIVEMODE_PIN12_Msk 0x03000000UL /*!< Select drive mode for pin 12 */ +#define GPIO_DRIVEMODE_PIN13_Msk 0x0C000000UL /*!< Select drive mode for pin 13 */ +#define GPIO_DRIVEMODE_PIN14_Msk 0x30000000UL /*!< Select drive mode for pin 14 */ +#define GPIO_DRIVEMODE_PIN15_Msk 0xC0000000UL /*!< Select drive mode for pin 15 */ + +/* Bit field enums: */ +typedef enum { + GPIO_DRIVEMODE_PIN0_HF = 0x0UL, /*!< High strength and Fast rate */ + GPIO_DRIVEMODE_PIN0_HS = 0x1UL, /*!< High strength and Slow rate */ + GPIO_DRIVEMODE_PIN0_LF = 0x2UL, /*!< Low strength and Fast rate */ + GPIO_DRIVEMODE_PIN0_LS = 0x3UL, /*!< Low strength and Slow rate */ +} GPIO_DRIVEMODE_PIN0_Enum; + +typedef enum { + GPIO_DRIVEMODE_PIN1_HF = 0x0UL, /*!< High strength and Fast rate */ + GPIO_DRIVEMODE_PIN1_HS = 0x1UL, /*!< High strength and Slow rate */ + GPIO_DRIVEMODE_PIN1_LF = 0x2UL, /*!< Low strength and Fast rate */ + GPIO_DRIVEMODE_PIN1_LS = 0x3UL, /*!< Low strength and Slow rate */ +} GPIO_DRIVEMODE_PIN1_Enum; + +typedef enum { + GPIO_DRIVEMODE_PIN2_HF = 0x0UL, /*!< High strength and Fast rate */ + GPIO_DRIVEMODE_PIN2_HS = 0x1UL, /*!< High strength and Slow rate */ + GPIO_DRIVEMODE_PIN2_LF = 0x2UL, /*!< Low strength and Fast rate */ + GPIO_DRIVEMODE_PIN2_LS = 0x3UL, /*!< Low strength and Slow rate */ +} GPIO_DRIVEMODE_PIN2_Enum; + +typedef enum { + GPIO_DRIVEMODE_PIN3_HF = 0x0UL, /*!< High strength and Fast rate */ + GPIO_DRIVEMODE_PIN3_HS = 0x1UL, /*!< High strength and Slow rate */ + GPIO_DRIVEMODE_PIN3_LF = 0x2UL, /*!< Low strength and Fast rate */ + GPIO_DRIVEMODE_PIN3_LS = 0x3UL, /*!< Low strength and Slow rate */ +} GPIO_DRIVEMODE_PIN3_Enum; + +typedef enum { + GPIO_DRIVEMODE_PIN4_HF = 0x0UL, /*!< High strength and Fast rate */ + GPIO_DRIVEMODE_PIN4_HS = 0x1UL, /*!< High strength and Slow rate */ + GPIO_DRIVEMODE_PIN4_LF = 0x2UL, /*!< Low strength and Fast rate */ + GPIO_DRIVEMODE_PIN4_LS = 0x3UL, /*!< Low strength and Slow rate */ +} GPIO_DRIVEMODE_PIN4_Enum; + +typedef enum { + GPIO_DRIVEMODE_PIN5_HF = 0x0UL, /*!< High strength and Fast rate */ + GPIO_DRIVEMODE_PIN5_HS = 0x1UL, /*!< High strength and Slow rate */ + GPIO_DRIVEMODE_PIN5_LF = 0x2UL, /*!< Low strength and Fast rate */ + GPIO_DRIVEMODE_PIN5_LS = 0x3UL, /*!< Low strength and Slow rate */ +} GPIO_DRIVEMODE_PIN5_Enum; + +typedef enum { + GPIO_DRIVEMODE_PIN6_HF = 0x0UL, /*!< High strength and Fast rate */ + GPIO_DRIVEMODE_PIN6_HS = 0x1UL, /*!< High strength and Slow rate */ + GPIO_DRIVEMODE_PIN6_LF = 0x2UL, /*!< Low strength and Fast rate */ + GPIO_DRIVEMODE_PIN6_LS = 0x3UL, /*!< Low strength and Slow rate */ +} GPIO_DRIVEMODE_PIN6_Enum; + +typedef enum { + GPIO_DRIVEMODE_PIN7_HF = 0x0UL, /*!< High strength and Fast rate */ + GPIO_DRIVEMODE_PIN7_HS = 0x1UL, /*!< High strength and Slow rate */ + GPIO_DRIVEMODE_PIN7_LF = 0x2UL, /*!< Low strength and Fast rate */ + GPIO_DRIVEMODE_PIN7_LS = 0x3UL, /*!< Low strength and Slow rate */ +} GPIO_DRIVEMODE_PIN7_Enum; + +typedef enum { + GPIO_DRIVEMODE_PIN8_HF = 0x0UL, /*!< High strength and Fast rate */ + GPIO_DRIVEMODE_PIN8_HS = 0x1UL, /*!< High strength and Slow rate */ + GPIO_DRIVEMODE_PIN8_LF = 0x2UL, /*!< Low strength and Fast rate */ + GPIO_DRIVEMODE_PIN8_LS = 0x3UL, /*!< Low strength and Slow rate */ +} GPIO_DRIVEMODE_PIN8_Enum; + +typedef enum { + GPIO_DRIVEMODE_PIN9_HF = 0x0UL, /*!< High strength and Fast rate */ + GPIO_DRIVEMODE_PIN9_HS = 0x1UL, /*!< High strength and Slow rate */ + GPIO_DRIVEMODE_PIN9_LF = 0x2UL, /*!< Low strength and Fast rate */ + GPIO_DRIVEMODE_PIN9_LS = 0x3UL, /*!< Low strength and Slow rate */ +} GPIO_DRIVEMODE_PIN9_Enum; + +typedef enum { + GPIO_DRIVEMODE_PIN10_HF = 0x0UL, /*!< High strength and Fast rate */ + GPIO_DRIVEMODE_PIN10_HS = 0x1UL, /*!< High strength and Slow rate */ + GPIO_DRIVEMODE_PIN10_LF = 0x2UL, /*!< Low strength and Fast rate */ + GPIO_DRIVEMODE_PIN10_LS = 0x3UL, /*!< Low strength and Slow rate */ +} GPIO_DRIVEMODE_PIN10_Enum; + +typedef enum { + GPIO_DRIVEMODE_PIN11_HF = 0x0UL, /*!< High strength and Fast rate */ + GPIO_DRIVEMODE_PIN11_HS = 0x1UL, /*!< High strength and Slow rate */ + GPIO_DRIVEMODE_PIN11_LF = 0x2UL, /*!< Low strength and Fast rate */ + GPIO_DRIVEMODE_PIN11_LS = 0x3UL, /*!< Low strength and Slow rate */ +} GPIO_DRIVEMODE_PIN11_Enum; + +typedef enum { + GPIO_DRIVEMODE_PIN12_HF = 0x0UL, /*!< High strength and Fast rate */ + GPIO_DRIVEMODE_PIN12_HS = 0x1UL, /*!< High strength and Slow rate */ + GPIO_DRIVEMODE_PIN12_LF = 0x2UL, /*!< Low strength and Fast rate */ + GPIO_DRIVEMODE_PIN12_LS = 0x3UL, /*!< Low strength and Slow rate */ +} GPIO_DRIVEMODE_PIN12_Enum; + +typedef enum { + GPIO_DRIVEMODE_PIN13_HF = 0x0UL, /*!< High strength and Fast rate */ + GPIO_DRIVEMODE_PIN13_HS = 0x1UL, /*!< High strength and Slow rate */ + GPIO_DRIVEMODE_PIN13_LF = 0x2UL, /*!< Low strength and Fast rate */ + GPIO_DRIVEMODE_PIN13_LS = 0x3UL, /*!< Low strength and Slow rate */ +} GPIO_DRIVEMODE_PIN13_Enum; + +typedef enum { + GPIO_DRIVEMODE_PIN14_HF = 0x0UL, /*!< High strength and Fast rate */ + GPIO_DRIVEMODE_PIN14_HS = 0x1UL, /*!< High strength and Slow rate */ + GPIO_DRIVEMODE_PIN14_LF = 0x2UL, /*!< Low strength and Fast rate */ + GPIO_DRIVEMODE_PIN14_LS = 0x3UL, /*!< Low strength and Slow rate */ +} GPIO_DRIVEMODE_PIN14_Enum; + +typedef enum { + GPIO_DRIVEMODE_PIN15_HF = 0x0UL, /*!< High strength and Fast rate */ + GPIO_DRIVEMODE_PIN15_HS = 0x1UL, /*!< High strength and Slow rate */ + GPIO_DRIVEMODE_PIN15_LF = 0x2UL, /*!< Low strength and Fast rate */ + GPIO_DRIVEMODE_PIN15_LS = 0x3UL, /*!< Low strength and Slow rate */ +} GPIO_DRIVEMODE_PIN15_Enum; + +/*-- OUTENSET: Output enable register ------------------------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< Output enable for pin 0 */ + uint32_t PIN1 :1; /*!< Output enable for pin 1 */ + uint32_t PIN2 :1; /*!< Output enable for pin 2 */ + uint32_t PIN3 :1; /*!< Output enable for pin 3 */ + uint32_t PIN4 :1; /*!< Output enable for pin 4 */ + uint32_t PIN5 :1; /*!< Output enable for pin 5 */ + uint32_t PIN6 :1; /*!< Output enable for pin 6 */ + uint32_t PIN7 :1; /*!< Output enable for pin 7 */ + uint32_t PIN8 :1; /*!< Output enable for pin 8 */ + uint32_t PIN9 :1; /*!< Output enable for pin 9 */ + uint32_t PIN10 :1; /*!< Output enable for pin 10 */ + uint32_t PIN11 :1; /*!< Output enable for pin 11 */ + uint32_t PIN12 :1; /*!< Output enable for pin 12 */ + uint32_t PIN13 :1; /*!< Output enable for pin 13 */ + uint32_t PIN14 :1; /*!< Output enable for pin 14 */ + uint32_t PIN15 :1; /*!< Output enable for pin 15 */ +} _GPIO_OUTENSET_bits; + +/* Bit field positions: */ +#define GPIO_OUTENSET_PIN0_Pos 0 /*!< Output enable for pin 0 */ +#define GPIO_OUTENSET_PIN1_Pos 1 /*!< Output enable for pin 1 */ +#define GPIO_OUTENSET_PIN2_Pos 2 /*!< Output enable for pin 2 */ +#define GPIO_OUTENSET_PIN3_Pos 3 /*!< Output enable for pin 3 */ +#define GPIO_OUTENSET_PIN4_Pos 4 /*!< Output enable for pin 4 */ +#define GPIO_OUTENSET_PIN5_Pos 5 /*!< Output enable for pin 5 */ +#define GPIO_OUTENSET_PIN6_Pos 6 /*!< Output enable for pin 6 */ +#define GPIO_OUTENSET_PIN7_Pos 7 /*!< Output enable for pin 7 */ +#define GPIO_OUTENSET_PIN8_Pos 8 /*!< Output enable for pin 8 */ +#define GPIO_OUTENSET_PIN9_Pos 9 /*!< Output enable for pin 9 */ +#define GPIO_OUTENSET_PIN10_Pos 10 /*!< Output enable for pin 10 */ +#define GPIO_OUTENSET_PIN11_Pos 11 /*!< Output enable for pin 11 */ +#define GPIO_OUTENSET_PIN12_Pos 12 /*!< Output enable for pin 12 */ +#define GPIO_OUTENSET_PIN13_Pos 13 /*!< Output enable for pin 13 */ +#define GPIO_OUTENSET_PIN14_Pos 14 /*!< Output enable for pin 14 */ +#define GPIO_OUTENSET_PIN15_Pos 15 /*!< Output enable for pin 15 */ + +/* Bit field masks: */ +#define GPIO_OUTENSET_PIN0_Msk 0x00000001UL /*!< Output enable for pin 0 */ +#define GPIO_OUTENSET_PIN1_Msk 0x00000002UL /*!< Output enable for pin 1 */ +#define GPIO_OUTENSET_PIN2_Msk 0x00000004UL /*!< Output enable for pin 2 */ +#define GPIO_OUTENSET_PIN3_Msk 0x00000008UL /*!< Output enable for pin 3 */ +#define GPIO_OUTENSET_PIN4_Msk 0x00000010UL /*!< Output enable for pin 4 */ +#define GPIO_OUTENSET_PIN5_Msk 0x00000020UL /*!< Output enable for pin 5 */ +#define GPIO_OUTENSET_PIN6_Msk 0x00000040UL /*!< Output enable for pin 6 */ +#define GPIO_OUTENSET_PIN7_Msk 0x00000080UL /*!< Output enable for pin 7 */ +#define GPIO_OUTENSET_PIN8_Msk 0x00000100UL /*!< Output enable for pin 8 */ +#define GPIO_OUTENSET_PIN9_Msk 0x00000200UL /*!< Output enable for pin 9 */ +#define GPIO_OUTENSET_PIN10_Msk 0x00000400UL /*!< Output enable for pin 10 */ +#define GPIO_OUTENSET_PIN11_Msk 0x00000800UL /*!< Output enable for pin 11 */ +#define GPIO_OUTENSET_PIN12_Msk 0x00001000UL /*!< Output enable for pin 12 */ +#define GPIO_OUTENSET_PIN13_Msk 0x00002000UL /*!< Output enable for pin 13 */ +#define GPIO_OUTENSET_PIN14_Msk 0x00004000UL /*!< Output enable for pin 14 */ +#define GPIO_OUTENSET_PIN15_Msk 0x00008000UL /*!< Output enable for pin 15 */ + +/*-- OUTENCLR: Output disable register -----------------------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< Output disable for pin 0 */ + uint32_t PIN1 :1; /*!< Output disable for pin 1 */ + uint32_t PIN2 :1; /*!< Output disable for pin 2 */ + uint32_t PIN3 :1; /*!< Output disable for pin 3 */ + uint32_t PIN4 :1; /*!< Output disable for pin 4 */ + uint32_t PIN5 :1; /*!< Output disable for pin 5 */ + uint32_t PIN6 :1; /*!< Output disable for pin 6 */ + uint32_t PIN7 :1; /*!< Output disable for pin 7 */ + uint32_t PIN8 :1; /*!< Output disable for pin 8 */ + uint32_t PIN9 :1; /*!< Output disable for pin 9 */ + uint32_t PIN10 :1; /*!< Output disable for pin 10 */ + uint32_t PIN11 :1; /*!< Output disable for pin 11 */ + uint32_t PIN12 :1; /*!< Output disable for pin 12 */ + uint32_t PIN13 :1; /*!< Output disable for pin 13 */ + uint32_t PIN14 :1; /*!< Output disable for pin 14 */ + uint32_t PIN15 :1; /*!< Output disable for pin 15 */ +} _GPIO_OUTENCLR_bits; + +/* Bit field positions: */ +#define GPIO_OUTENCLR_PIN0_Pos 0 /*!< Output disable for pin 0 */ +#define GPIO_OUTENCLR_PIN1_Pos 1 /*!< Output disable for pin 1 */ +#define GPIO_OUTENCLR_PIN2_Pos 2 /*!< Output disable for pin 2 */ +#define GPIO_OUTENCLR_PIN3_Pos 3 /*!< Output disable for pin 3 */ +#define GPIO_OUTENCLR_PIN4_Pos 4 /*!< Output disable for pin 4 */ +#define GPIO_OUTENCLR_PIN5_Pos 5 /*!< Output disable for pin 5 */ +#define GPIO_OUTENCLR_PIN6_Pos 6 /*!< Output disable for pin 6 */ +#define GPIO_OUTENCLR_PIN7_Pos 7 /*!< Output disable for pin 7 */ +#define GPIO_OUTENCLR_PIN8_Pos 8 /*!< Output disable for pin 8 */ +#define GPIO_OUTENCLR_PIN9_Pos 9 /*!< Output disable for pin 9 */ +#define GPIO_OUTENCLR_PIN10_Pos 10 /*!< Output disable for pin 10 */ +#define GPIO_OUTENCLR_PIN11_Pos 11 /*!< Output disable for pin 11 */ +#define GPIO_OUTENCLR_PIN12_Pos 12 /*!< Output disable for pin 12 */ +#define GPIO_OUTENCLR_PIN13_Pos 13 /*!< Output disable for pin 13 */ +#define GPIO_OUTENCLR_PIN14_Pos 14 /*!< Output disable for pin 14 */ +#define GPIO_OUTENCLR_PIN15_Pos 15 /*!< Output disable for pin 15 */ + +/* Bit field masks: */ +#define GPIO_OUTENCLR_PIN0_Msk 0x00000001UL /*!< Output disable for pin 0 */ +#define GPIO_OUTENCLR_PIN1_Msk 0x00000002UL /*!< Output disable for pin 1 */ +#define GPIO_OUTENCLR_PIN2_Msk 0x00000004UL /*!< Output disable for pin 2 */ +#define GPIO_OUTENCLR_PIN3_Msk 0x00000008UL /*!< Output disable for pin 3 */ +#define GPIO_OUTENCLR_PIN4_Msk 0x00000010UL /*!< Output disable for pin 4 */ +#define GPIO_OUTENCLR_PIN5_Msk 0x00000020UL /*!< Output disable for pin 5 */ +#define GPIO_OUTENCLR_PIN6_Msk 0x00000040UL /*!< Output disable for pin 6 */ +#define GPIO_OUTENCLR_PIN7_Msk 0x00000080UL /*!< Output disable for pin 7 */ +#define GPIO_OUTENCLR_PIN8_Msk 0x00000100UL /*!< Output disable for pin 8 */ +#define GPIO_OUTENCLR_PIN9_Msk 0x00000200UL /*!< Output disable for pin 9 */ +#define GPIO_OUTENCLR_PIN10_Msk 0x00000400UL /*!< Output disable for pin 10 */ +#define GPIO_OUTENCLR_PIN11_Msk 0x00000800UL /*!< Output disable for pin 11 */ +#define GPIO_OUTENCLR_PIN12_Msk 0x00001000UL /*!< Output disable for pin 12 */ +#define GPIO_OUTENCLR_PIN13_Msk 0x00002000UL /*!< Output disable for pin 13 */ +#define GPIO_OUTENCLR_PIN14_Msk 0x00004000UL /*!< Output disable for pin 14 */ +#define GPIO_OUTENCLR_PIN15_Msk 0x00008000UL /*!< Output disable for pin 15 */ + +/*-- ALTFUNCSET: Alternative function enable register --------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< Alternative function enable for pin 0 */ + uint32_t PIN1 :1; /*!< Alternative function enable for pin 1 */ + uint32_t PIN2 :1; /*!< Alternative function enable for pin 2 */ + uint32_t PIN3 :1; /*!< Alternative function enable for pin 3 */ + uint32_t PIN4 :1; /*!< Alternative function enable for pin 4 */ + uint32_t PIN5 :1; /*!< Alternative function enable for pin 5 */ + uint32_t PIN6 :1; /*!< Alternative function enable for pin 6 */ + uint32_t PIN7 :1; /*!< Alternative function enable for pin 7 */ + uint32_t PIN8 :1; /*!< Alternative function enable for pin 8 */ + uint32_t PIN9 :1; /*!< Alternative function enable for pin 9 */ + uint32_t PIN10 :1; /*!< Alternative function enable for pin 10 */ + uint32_t PIN11 :1; /*!< Alternative function enable for pin 11 */ + uint32_t PIN12 :1; /*!< Alternative function enable for pin 12 */ + uint32_t PIN13 :1; /*!< Alternative function enable for pin 13 */ + uint32_t PIN14 :1; /*!< Alternative function enable for pin 14 */ + uint32_t PIN15 :1; /*!< Alternative function enable for pin 15 */ +} _GPIO_ALTFUNCSET_bits; + +/* Bit field positions: */ +#define GPIO_ALTFUNCSET_PIN0_Pos 0 /*!< Alternative function enable for pin 0 */ +#define GPIO_ALTFUNCSET_PIN1_Pos 1 /*!< Alternative function enable for pin 1 */ +#define GPIO_ALTFUNCSET_PIN2_Pos 2 /*!< Alternative function enable for pin 2 */ +#define GPIO_ALTFUNCSET_PIN3_Pos 3 /*!< Alternative function enable for pin 3 */ +#define GPIO_ALTFUNCSET_PIN4_Pos 4 /*!< Alternative function enable for pin 4 */ +#define GPIO_ALTFUNCSET_PIN5_Pos 5 /*!< Alternative function enable for pin 5 */ +#define GPIO_ALTFUNCSET_PIN6_Pos 6 /*!< Alternative function enable for pin 6 */ +#define GPIO_ALTFUNCSET_PIN7_Pos 7 /*!< Alternative function enable for pin 7 */ +#define GPIO_ALTFUNCSET_PIN8_Pos 8 /*!< Alternative function enable for pin 8 */ +#define GPIO_ALTFUNCSET_PIN9_Pos 9 /*!< Alternative function enable for pin 9 */ +#define GPIO_ALTFUNCSET_PIN10_Pos 10 /*!< Alternative function enable for pin 10 */ +#define GPIO_ALTFUNCSET_PIN11_Pos 11 /*!< Alternative function enable for pin 11 */ +#define GPIO_ALTFUNCSET_PIN12_Pos 12 /*!< Alternative function enable for pin 12 */ +#define GPIO_ALTFUNCSET_PIN13_Pos 13 /*!< Alternative function enable for pin 13 */ +#define GPIO_ALTFUNCSET_PIN14_Pos 14 /*!< Alternative function enable for pin 14 */ +#define GPIO_ALTFUNCSET_PIN15_Pos 15 /*!< Alternative function enable for pin 15 */ + +/* Bit field masks: */ +#define GPIO_ALTFUNCSET_PIN0_Msk 0x00000001UL /*!< Alternative function enable for pin 0 */ +#define GPIO_ALTFUNCSET_PIN1_Msk 0x00000002UL /*!< Alternative function enable for pin 1 */ +#define GPIO_ALTFUNCSET_PIN2_Msk 0x00000004UL /*!< Alternative function enable for pin 2 */ +#define GPIO_ALTFUNCSET_PIN3_Msk 0x00000008UL /*!< Alternative function enable for pin 3 */ +#define GPIO_ALTFUNCSET_PIN4_Msk 0x00000010UL /*!< Alternative function enable for pin 4 */ +#define GPIO_ALTFUNCSET_PIN5_Msk 0x00000020UL /*!< Alternative function enable for pin 5 */ +#define GPIO_ALTFUNCSET_PIN6_Msk 0x00000040UL /*!< Alternative function enable for pin 6 */ +#define GPIO_ALTFUNCSET_PIN7_Msk 0x00000080UL /*!< Alternative function enable for pin 7 */ +#define GPIO_ALTFUNCSET_PIN8_Msk 0x00000100UL /*!< Alternative function enable for pin 8 */ +#define GPIO_ALTFUNCSET_PIN9_Msk 0x00000200UL /*!< Alternative function enable for pin 9 */ +#define GPIO_ALTFUNCSET_PIN10_Msk 0x00000400UL /*!< Alternative function enable for pin 10 */ +#define GPIO_ALTFUNCSET_PIN11_Msk 0x00000800UL /*!< Alternative function enable for pin 11 */ +#define GPIO_ALTFUNCSET_PIN12_Msk 0x00001000UL /*!< Alternative function enable for pin 12 */ +#define GPIO_ALTFUNCSET_PIN13_Msk 0x00002000UL /*!< Alternative function enable for pin 13 */ +#define GPIO_ALTFUNCSET_PIN14_Msk 0x00004000UL /*!< Alternative function enable for pin 14 */ +#define GPIO_ALTFUNCSET_PIN15_Msk 0x00008000UL /*!< Alternative function enable for pin 15 */ + +/*-- ALTFUNCCLR: Alternative function disable register -------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< Alternative function disable for pin 0 */ + uint32_t PIN1 :1; /*!< Alternative function disable for pin 1 */ + uint32_t PIN2 :1; /*!< Alternative function disable for pin 2 */ + uint32_t PIN3 :1; /*!< Alternative function disable for pin 3 */ + uint32_t PIN4 :1; /*!< Alternative function disable for pin 4 */ + uint32_t PIN5 :1; /*!< Alternative function disable for pin 5 */ + uint32_t PIN6 :1; /*!< Alternative function disable for pin 6 */ + uint32_t PIN7 :1; /*!< Alternative function disable for pin 7 */ + uint32_t PIN8 :1; /*!< Alternative function disable for pin 8 */ + uint32_t PIN9 :1; /*!< Alternative function disable for pin 9 */ + uint32_t PIN10 :1; /*!< Alternative function disable for pin 10 */ + uint32_t PIN11 :1; /*!< Alternative function disable for pin 11 */ + uint32_t PIN12 :1; /*!< Alternative function disable for pin 12 */ + uint32_t PIN13 :1; /*!< Alternative function disable for pin 13 */ + uint32_t PIN14 :1; /*!< Alternative function disable for pin 14 */ + uint32_t PIN15 :1; /*!< Alternative function disable for pin 15 */ +} _GPIO_ALTFUNCCLR_bits; + +/* Bit field positions: */ +#define GPIO_ALTFUNCCLR_PIN0_Pos 0 /*!< Alternative function disable for pin 0 */ +#define GPIO_ALTFUNCCLR_PIN1_Pos 1 /*!< Alternative function disable for pin 1 */ +#define GPIO_ALTFUNCCLR_PIN2_Pos 2 /*!< Alternative function disable for pin 2 */ +#define GPIO_ALTFUNCCLR_PIN3_Pos 3 /*!< Alternative function disable for pin 3 */ +#define GPIO_ALTFUNCCLR_PIN4_Pos 4 /*!< Alternative function disable for pin 4 */ +#define GPIO_ALTFUNCCLR_PIN5_Pos 5 /*!< Alternative function disable for pin 5 */ +#define GPIO_ALTFUNCCLR_PIN6_Pos 6 /*!< Alternative function disable for pin 6 */ +#define GPIO_ALTFUNCCLR_PIN7_Pos 7 /*!< Alternative function disable for pin 7 */ +#define GPIO_ALTFUNCCLR_PIN8_Pos 8 /*!< Alternative function disable for pin 8 */ +#define GPIO_ALTFUNCCLR_PIN9_Pos 9 /*!< Alternative function disable for pin 9 */ +#define GPIO_ALTFUNCCLR_PIN10_Pos 10 /*!< Alternative function disable for pin 10 */ +#define GPIO_ALTFUNCCLR_PIN11_Pos 11 /*!< Alternative function disable for pin 11 */ +#define GPIO_ALTFUNCCLR_PIN12_Pos 12 /*!< Alternative function disable for pin 12 */ +#define GPIO_ALTFUNCCLR_PIN13_Pos 13 /*!< Alternative function disable for pin 13 */ +#define GPIO_ALTFUNCCLR_PIN14_Pos 14 /*!< Alternative function disable for pin 14 */ +#define GPIO_ALTFUNCCLR_PIN15_Pos 15 /*!< Alternative function disable for pin 15 */ + +/* Bit field masks: */ +#define GPIO_ALTFUNCCLR_PIN0_Msk 0x00000001UL /*!< Alternative function disable for pin 0 */ +#define GPIO_ALTFUNCCLR_PIN1_Msk 0x00000002UL /*!< Alternative function disable for pin 1 */ +#define GPIO_ALTFUNCCLR_PIN2_Msk 0x00000004UL /*!< Alternative function disable for pin 2 */ +#define GPIO_ALTFUNCCLR_PIN3_Msk 0x00000008UL /*!< Alternative function disable for pin 3 */ +#define GPIO_ALTFUNCCLR_PIN4_Msk 0x00000010UL /*!< Alternative function disable for pin 4 */ +#define GPIO_ALTFUNCCLR_PIN5_Msk 0x00000020UL /*!< Alternative function disable for pin 5 */ +#define GPIO_ALTFUNCCLR_PIN6_Msk 0x00000040UL /*!< Alternative function disable for pin 6 */ +#define GPIO_ALTFUNCCLR_PIN7_Msk 0x00000080UL /*!< Alternative function disable for pin 7 */ +#define GPIO_ALTFUNCCLR_PIN8_Msk 0x00000100UL /*!< Alternative function disable for pin 8 */ +#define GPIO_ALTFUNCCLR_PIN9_Msk 0x00000200UL /*!< Alternative function disable for pin 9 */ +#define GPIO_ALTFUNCCLR_PIN10_Msk 0x00000400UL /*!< Alternative function disable for pin 10 */ +#define GPIO_ALTFUNCCLR_PIN11_Msk 0x00000800UL /*!< Alternative function disable for pin 11 */ +#define GPIO_ALTFUNCCLR_PIN12_Msk 0x00001000UL /*!< Alternative function disable for pin 12 */ +#define GPIO_ALTFUNCCLR_PIN13_Msk 0x00002000UL /*!< Alternative function disable for pin 13 */ +#define GPIO_ALTFUNCCLR_PIN14_Msk 0x00004000UL /*!< Alternative function disable for pin 14 */ +#define GPIO_ALTFUNCCLR_PIN15_Msk 0x00008000UL /*!< Alternative function disable for pin 15 */ + +/*-- SYNCSET: Additional double flip-flop syncronization enable register -------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 0 */ + uint32_t PIN1 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 1 */ + uint32_t PIN2 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 2 */ + uint32_t PIN3 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 3 */ + uint32_t PIN4 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 4 */ + uint32_t PIN5 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 5 */ + uint32_t PIN6 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 6 */ + uint32_t PIN7 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 7 */ + uint32_t PIN8 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 8 */ + uint32_t PIN9 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 9 */ + uint32_t PIN10 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 10 */ + uint32_t PIN11 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 11 */ + uint32_t PIN12 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 12 */ + uint32_t PIN13 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 13 */ + uint32_t PIN14 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 14 */ + uint32_t PIN15 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 15 */ +} _GPIO_SYNCSET_bits; + +/* Bit field positions: */ +#define GPIO_SYNCSET_PIN0_Pos 0 /*!< Additional double flip-flop syncronization buffer enable for pin 0 */ +#define GPIO_SYNCSET_PIN1_Pos 1 /*!< Additional double flip-flop syncronization buffer enable for pin 1 */ +#define GPIO_SYNCSET_PIN2_Pos 2 /*!< Additional double flip-flop syncronization buffer enable for pin 2 */ +#define GPIO_SYNCSET_PIN3_Pos 3 /*!< Additional double flip-flop syncronization buffer enable for pin 3 */ +#define GPIO_SYNCSET_PIN4_Pos 4 /*!< Additional double flip-flop syncronization buffer enable for pin 4 */ +#define GPIO_SYNCSET_PIN5_Pos 5 /*!< Additional double flip-flop syncronization buffer enable for pin 5 */ +#define GPIO_SYNCSET_PIN6_Pos 6 /*!< Additional double flip-flop syncronization buffer enable for pin 6 */ +#define GPIO_SYNCSET_PIN7_Pos 7 /*!< Additional double flip-flop syncronization buffer enable for pin 7 */ +#define GPIO_SYNCSET_PIN8_Pos 8 /*!< Additional double flip-flop syncronization buffer enable for pin 8 */ +#define GPIO_SYNCSET_PIN9_Pos 9 /*!< Additional double flip-flop syncronization buffer enable for pin 9 */ +#define GPIO_SYNCSET_PIN10_Pos 10 /*!< Additional double flip-flop syncronization buffer enable for pin 10 */ +#define GPIO_SYNCSET_PIN11_Pos 11 /*!< Additional double flip-flop syncronization buffer enable for pin 11 */ +#define GPIO_SYNCSET_PIN12_Pos 12 /*!< Additional double flip-flop syncronization buffer enable for pin 12 */ +#define GPIO_SYNCSET_PIN13_Pos 13 /*!< Additional double flip-flop syncronization buffer enable for pin 13 */ +#define GPIO_SYNCSET_PIN14_Pos 14 /*!< Additional double flip-flop syncronization buffer enable for pin 14 */ +#define GPIO_SYNCSET_PIN15_Pos 15 /*!< Additional double flip-flop syncronization buffer enable for pin 15 */ + +/* Bit field masks: */ +#define GPIO_SYNCSET_PIN0_Msk 0x00000001UL /*!< Additional double flip-flop syncronization buffer enable for pin 0 */ +#define GPIO_SYNCSET_PIN1_Msk 0x00000002UL /*!< Additional double flip-flop syncronization buffer enable for pin 1 */ +#define GPIO_SYNCSET_PIN2_Msk 0x00000004UL /*!< Additional double flip-flop syncronization buffer enable for pin 2 */ +#define GPIO_SYNCSET_PIN3_Msk 0x00000008UL /*!< Additional double flip-flop syncronization buffer enable for pin 3 */ +#define GPIO_SYNCSET_PIN4_Msk 0x00000010UL /*!< Additional double flip-flop syncronization buffer enable for pin 4 */ +#define GPIO_SYNCSET_PIN5_Msk 0x00000020UL /*!< Additional double flip-flop syncronization buffer enable for pin 5 */ +#define GPIO_SYNCSET_PIN6_Msk 0x00000040UL /*!< Additional double flip-flop syncronization buffer enable for pin 6 */ +#define GPIO_SYNCSET_PIN7_Msk 0x00000080UL /*!< Additional double flip-flop syncronization buffer enable for pin 7 */ +#define GPIO_SYNCSET_PIN8_Msk 0x00000100UL /*!< Additional double flip-flop syncronization buffer enable for pin 8 */ +#define GPIO_SYNCSET_PIN9_Msk 0x00000200UL /*!< Additional double flip-flop syncronization buffer enable for pin 9 */ +#define GPIO_SYNCSET_PIN10_Msk 0x00000400UL /*!< Additional double flip-flop syncronization buffer enable for pin 10 */ +#define GPIO_SYNCSET_PIN11_Msk 0x00000800UL /*!< Additional double flip-flop syncronization buffer enable for pin 11 */ +#define GPIO_SYNCSET_PIN12_Msk 0x00001000UL /*!< Additional double flip-flop syncronization buffer enable for pin 12 */ +#define GPIO_SYNCSET_PIN13_Msk 0x00002000UL /*!< Additional double flip-flop syncronization buffer enable for pin 13 */ +#define GPIO_SYNCSET_PIN14_Msk 0x00004000UL /*!< Additional double flip-flop syncronization buffer enable for pin 14 */ +#define GPIO_SYNCSET_PIN15_Msk 0x00008000UL /*!< Additional double flip-flop syncronization buffer enable for pin 15 */ + +/*-- SYNCCLR: Additional double flip-flop syncronization disable register ------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< Additional double flip-flop syncronization disable for pin 0 */ + uint32_t PIN1 :1; /*!< Additional double flip-flop syncronization disable for pin 1 */ + uint32_t PIN2 :1; /*!< Additional double flip-flop syncronization disable for pin 2 */ + uint32_t PIN3 :1; /*!< Additional double flip-flop syncronization disable for pin 3 */ + uint32_t PIN4 :1; /*!< Additional double flip-flop syncronization disable for pin 4 */ + uint32_t PIN5 :1; /*!< Additional double flip-flop syncronization disable for pin 5 */ + uint32_t PIN6 :1; /*!< Additional double flip-flop syncronization disable for pin 6 */ + uint32_t PIN7 :1; /*!< Additional double flip-flop syncronization disable for pin 7 */ + uint32_t PIN8 :1; /*!< Additional double flip-flop syncronization disable for pin 8 */ + uint32_t PIN9 :1; /*!< Additional double flip-flop syncronization disable for pin 9 */ + uint32_t PIN10 :1; /*!< Additional double flip-flop syncronization disable for pin 10 */ + uint32_t PIN11 :1; /*!< Additional double flip-flop syncronization disable for pin 11 */ + uint32_t PIN12 :1; /*!< Additional double flip-flop syncronization disable for pin 12 */ + uint32_t PIN13 :1; /*!< Additional double flip-flop syncronization disable for pin 13 */ + uint32_t PIN14 :1; /*!< Additional double flip-flop syncronization disable for pin 14 */ + uint32_t PIN15 :1; /*!< Additional double flip-flop syncronization disable for pin 15 */ +} _GPIO_SYNCCLR_bits; + +/* Bit field positions: */ +#define GPIO_SYNCCLR_PIN0_Pos 0 /*!< Additional double flip-flop syncronization disable for pin 0 */ +#define GPIO_SYNCCLR_PIN1_Pos 1 /*!< Additional double flip-flop syncronization disable for pin 1 */ +#define GPIO_SYNCCLR_PIN2_Pos 2 /*!< Additional double flip-flop syncronization disable for pin 2 */ +#define GPIO_SYNCCLR_PIN3_Pos 3 /*!< Additional double flip-flop syncronization disable for pin 3 */ +#define GPIO_SYNCCLR_PIN4_Pos 4 /*!< Additional double flip-flop syncronization disable for pin 4 */ +#define GPIO_SYNCCLR_PIN5_Pos 5 /*!< Additional double flip-flop syncronization disable for pin 5 */ +#define GPIO_SYNCCLR_PIN6_Pos 6 /*!< Additional double flip-flop syncronization disable for pin 6 */ +#define GPIO_SYNCCLR_PIN7_Pos 7 /*!< Additional double flip-flop syncronization disable for pin 7 */ +#define GPIO_SYNCCLR_PIN8_Pos 8 /*!< Additional double flip-flop syncronization disable for pin 8 */ +#define GPIO_SYNCCLR_PIN9_Pos 9 /*!< Additional double flip-flop syncronization disable for pin 9 */ +#define GPIO_SYNCCLR_PIN10_Pos 10 /*!< Additional double flip-flop syncronization disable for pin 10 */ +#define GPIO_SYNCCLR_PIN11_Pos 11 /*!< Additional double flip-flop syncronization disable for pin 11 */ +#define GPIO_SYNCCLR_PIN12_Pos 12 /*!< Additional double flip-flop syncronization disable for pin 12 */ +#define GPIO_SYNCCLR_PIN13_Pos 13 /*!< Additional double flip-flop syncronization disable for pin 13 */ +#define GPIO_SYNCCLR_PIN14_Pos 14 /*!< Additional double flip-flop syncronization disable for pin 14 */ +#define GPIO_SYNCCLR_PIN15_Pos 15 /*!< Additional double flip-flop syncronization disable for pin 15 */ + +/* Bit field masks: */ +#define GPIO_SYNCCLR_PIN0_Msk 0x00000001UL /*!< Additional double flip-flop syncronization disable for pin 0 */ +#define GPIO_SYNCCLR_PIN1_Msk 0x00000002UL /*!< Additional double flip-flop syncronization disable for pin 1 */ +#define GPIO_SYNCCLR_PIN2_Msk 0x00000004UL /*!< Additional double flip-flop syncronization disable for pin 2 */ +#define GPIO_SYNCCLR_PIN3_Msk 0x00000008UL /*!< Additional double flip-flop syncronization disable for pin 3 */ +#define GPIO_SYNCCLR_PIN4_Msk 0x00000010UL /*!< Additional double flip-flop syncronization disable for pin 4 */ +#define GPIO_SYNCCLR_PIN5_Msk 0x00000020UL /*!< Additional double flip-flop syncronization disable for pin 5 */ +#define GPIO_SYNCCLR_PIN6_Msk 0x00000040UL /*!< Additional double flip-flop syncronization disable for pin 6 */ +#define GPIO_SYNCCLR_PIN7_Msk 0x00000080UL /*!< Additional double flip-flop syncronization disable for pin 7 */ +#define GPIO_SYNCCLR_PIN8_Msk 0x00000100UL /*!< Additional double flip-flop syncronization disable for pin 8 */ +#define GPIO_SYNCCLR_PIN9_Msk 0x00000200UL /*!< Additional double flip-flop syncronization disable for pin 9 */ +#define GPIO_SYNCCLR_PIN10_Msk 0x00000400UL /*!< Additional double flip-flop syncronization disable for pin 10 */ +#define GPIO_SYNCCLR_PIN11_Msk 0x00000800UL /*!< Additional double flip-flop syncronization disable for pin 11 */ +#define GPIO_SYNCCLR_PIN12_Msk 0x00001000UL /*!< Additional double flip-flop syncronization disable for pin 12 */ +#define GPIO_SYNCCLR_PIN13_Msk 0x00002000UL /*!< Additional double flip-flop syncronization disable for pin 13 */ +#define GPIO_SYNCCLR_PIN14_Msk 0x00004000UL /*!< Additional double flip-flop syncronization disable for pin 14 */ +#define GPIO_SYNCCLR_PIN15_Msk 0x00008000UL /*!< Additional double flip-flop syncronization disable for pin 15 */ + +/*-- QUALSET: Qualifier enable register ----------------------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< Qualifier enable for pin 0 */ + uint32_t PIN1 :1; /*!< Qualifier enable for pin 1 */ + uint32_t PIN2 :1; /*!< Qualifier enable for pin 2 */ + uint32_t PIN3 :1; /*!< Qualifier enable for pin 3 */ + uint32_t PIN4 :1; /*!< Qualifier enable for pin 4 */ + uint32_t PIN5 :1; /*!< Qualifier enable for pin 5 */ + uint32_t PIN6 :1; /*!< Qualifier enable for pin 6 */ + uint32_t PIN7 :1; /*!< Qualifier enable for pin 7 */ + uint32_t PIN8 :1; /*!< Qualifier enable for pin 8 */ + uint32_t PIN9 :1; /*!< Qualifier enable for pin 9 */ + uint32_t PIN10 :1; /*!< Qualifier enable for pin 10 */ + uint32_t PIN11 :1; /*!< Qualifier enable for pin 11 */ + uint32_t PIN12 :1; /*!< Qualifier enable for pin 12 */ + uint32_t PIN13 :1; /*!< Qualifier enable for pin 13 */ + uint32_t PIN14 :1; /*!< Qualifier enable for pin 14 */ + uint32_t PIN15 :1; /*!< Qualifier enable for pin 15 */ +} _GPIO_QUALSET_bits; + +/* Bit field positions: */ +#define GPIO_QUALSET_PIN0_Pos 0 /*!< Qualifier enable for pin 0 */ +#define GPIO_QUALSET_PIN1_Pos 1 /*!< Qualifier enable for pin 1 */ +#define GPIO_QUALSET_PIN2_Pos 2 /*!< Qualifier enable for pin 2 */ +#define GPIO_QUALSET_PIN3_Pos 3 /*!< Qualifier enable for pin 3 */ +#define GPIO_QUALSET_PIN4_Pos 4 /*!< Qualifier enable for pin 4 */ +#define GPIO_QUALSET_PIN5_Pos 5 /*!< Qualifier enable for pin 5 */ +#define GPIO_QUALSET_PIN6_Pos 6 /*!< Qualifier enable for pin 6 */ +#define GPIO_QUALSET_PIN7_Pos 7 /*!< Qualifier enable for pin 7 */ +#define GPIO_QUALSET_PIN8_Pos 8 /*!< Qualifier enable for pin 8 */ +#define GPIO_QUALSET_PIN9_Pos 9 /*!< Qualifier enable for pin 9 */ +#define GPIO_QUALSET_PIN10_Pos 10 /*!< Qualifier enable for pin 10 */ +#define GPIO_QUALSET_PIN11_Pos 11 /*!< Qualifier enable for pin 11 */ +#define GPIO_QUALSET_PIN12_Pos 12 /*!< Qualifier enable for pin 12 */ +#define GPIO_QUALSET_PIN13_Pos 13 /*!< Qualifier enable for pin 13 */ +#define GPIO_QUALSET_PIN14_Pos 14 /*!< Qualifier enable for pin 14 */ +#define GPIO_QUALSET_PIN15_Pos 15 /*!< Qualifier enable for pin 15 */ + +/* Bit field masks: */ +#define GPIO_QUALSET_PIN0_Msk 0x00000001UL /*!< Qualifier enable for pin 0 */ +#define GPIO_QUALSET_PIN1_Msk 0x00000002UL /*!< Qualifier enable for pin 1 */ +#define GPIO_QUALSET_PIN2_Msk 0x00000004UL /*!< Qualifier enable for pin 2 */ +#define GPIO_QUALSET_PIN3_Msk 0x00000008UL /*!< Qualifier enable for pin 3 */ +#define GPIO_QUALSET_PIN4_Msk 0x00000010UL /*!< Qualifier enable for pin 4 */ +#define GPIO_QUALSET_PIN5_Msk 0x00000020UL /*!< Qualifier enable for pin 5 */ +#define GPIO_QUALSET_PIN6_Msk 0x00000040UL /*!< Qualifier enable for pin 6 */ +#define GPIO_QUALSET_PIN7_Msk 0x00000080UL /*!< Qualifier enable for pin 7 */ +#define GPIO_QUALSET_PIN8_Msk 0x00000100UL /*!< Qualifier enable for pin 8 */ +#define GPIO_QUALSET_PIN9_Msk 0x00000200UL /*!< Qualifier enable for pin 9 */ +#define GPIO_QUALSET_PIN10_Msk 0x00000400UL /*!< Qualifier enable for pin 10 */ +#define GPIO_QUALSET_PIN11_Msk 0x00000800UL /*!< Qualifier enable for pin 11 */ +#define GPIO_QUALSET_PIN12_Msk 0x00001000UL /*!< Qualifier enable for pin 12 */ +#define GPIO_QUALSET_PIN13_Msk 0x00002000UL /*!< Qualifier enable for pin 13 */ +#define GPIO_QUALSET_PIN14_Msk 0x00004000UL /*!< Qualifier enable for pin 14 */ +#define GPIO_QUALSET_PIN15_Msk 0x00008000UL /*!< Qualifier enable for pin 15 */ + +/*-- QUALCLR: Qualifier disable register ---------------------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< Qualifier disable for pin 0 */ + uint32_t PIN1 :1; /*!< Qualifier disable for pin 1 */ + uint32_t PIN2 :1; /*!< Qualifier disable for pin 2 */ + uint32_t PIN3 :1; /*!< Qualifier disable for pin 3 */ + uint32_t PIN4 :1; /*!< Qualifier disable for pin 4 */ + uint32_t PIN5 :1; /*!< Qualifier disable for pin 5 */ + uint32_t PIN6 :1; /*!< Qualifier disable for pin 6 */ + uint32_t PIN7 :1; /*!< Qualifier disable for pin 7 */ + uint32_t PIN8 :1; /*!< Qualifier disable for pin 8 */ + uint32_t PIN9 :1; /*!< Qualifier disable for pin 9 */ + uint32_t PIN10 :1; /*!< Qualifier disable for pin 10 */ + uint32_t PIN11 :1; /*!< Qualifier disable for pin 11 */ + uint32_t PIN12 :1; /*!< Qualifier disable for pin 12 */ + uint32_t PIN13 :1; /*!< Qualifier disable for pin 13 */ + uint32_t PIN14 :1; /*!< Qualifier disable for pin 14 */ + uint32_t PIN15 :1; /*!< Qualifier disable for pin 15 */ +} _GPIO_QUALCLR_bits; + +/* Bit field positions: */ +#define GPIO_QUALCLR_PIN0_Pos 0 /*!< Qualifier disable for pin 0 */ +#define GPIO_QUALCLR_PIN1_Pos 1 /*!< Qualifier disable for pin 1 */ +#define GPIO_QUALCLR_PIN2_Pos 2 /*!< Qualifier disable for pin 2 */ +#define GPIO_QUALCLR_PIN3_Pos 3 /*!< Qualifier disable for pin 3 */ +#define GPIO_QUALCLR_PIN4_Pos 4 /*!< Qualifier disable for pin 4 */ +#define GPIO_QUALCLR_PIN5_Pos 5 /*!< Qualifier disable for pin 5 */ +#define GPIO_QUALCLR_PIN6_Pos 6 /*!< Qualifier disable for pin 6 */ +#define GPIO_QUALCLR_PIN7_Pos 7 /*!< Qualifier disable for pin 7 */ +#define GPIO_QUALCLR_PIN8_Pos 8 /*!< Qualifier disable for pin 8 */ +#define GPIO_QUALCLR_PIN9_Pos 9 /*!< Qualifier disable for pin 9 */ +#define GPIO_QUALCLR_PIN10_Pos 10 /*!< Qualifier disable for pin 10 */ +#define GPIO_QUALCLR_PIN11_Pos 11 /*!< Qualifier disable for pin 11 */ +#define GPIO_QUALCLR_PIN12_Pos 12 /*!< Qualifier disable for pin 12 */ +#define GPIO_QUALCLR_PIN13_Pos 13 /*!< Qualifier disable for pin 13 */ +#define GPIO_QUALCLR_PIN14_Pos 14 /*!< Qualifier disable for pin 14 */ +#define GPIO_QUALCLR_PIN15_Pos 15 /*!< Qualifier disable for pin 15 */ + +/* Bit field masks: */ +#define GPIO_QUALCLR_PIN0_Msk 0x00000001UL /*!< Qualifier disable for pin 0 */ +#define GPIO_QUALCLR_PIN1_Msk 0x00000002UL /*!< Qualifier disable for pin 1 */ +#define GPIO_QUALCLR_PIN2_Msk 0x00000004UL /*!< Qualifier disable for pin 2 */ +#define GPIO_QUALCLR_PIN3_Msk 0x00000008UL /*!< Qualifier disable for pin 3 */ +#define GPIO_QUALCLR_PIN4_Msk 0x00000010UL /*!< Qualifier disable for pin 4 */ +#define GPIO_QUALCLR_PIN5_Msk 0x00000020UL /*!< Qualifier disable for pin 5 */ +#define GPIO_QUALCLR_PIN6_Msk 0x00000040UL /*!< Qualifier disable for pin 6 */ +#define GPIO_QUALCLR_PIN7_Msk 0x00000080UL /*!< Qualifier disable for pin 7 */ +#define GPIO_QUALCLR_PIN8_Msk 0x00000100UL /*!< Qualifier disable for pin 8 */ +#define GPIO_QUALCLR_PIN9_Msk 0x00000200UL /*!< Qualifier disable for pin 9 */ +#define GPIO_QUALCLR_PIN10_Msk 0x00000400UL /*!< Qualifier disable for pin 10 */ +#define GPIO_QUALCLR_PIN11_Msk 0x00000800UL /*!< Qualifier disable for pin 11 */ +#define GPIO_QUALCLR_PIN12_Msk 0x00001000UL /*!< Qualifier disable for pin 12 */ +#define GPIO_QUALCLR_PIN13_Msk 0x00002000UL /*!< Qualifier disable for pin 13 */ +#define GPIO_QUALCLR_PIN14_Msk 0x00004000UL /*!< Qualifier disable for pin 14 */ +#define GPIO_QUALCLR_PIN15_Msk 0x00008000UL /*!< Qualifier disable for pin 15 */ + +/*-- QUALMODESET: Qualifier mode set register ----------------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< Qualifier mode set for pin 0 */ + uint32_t PIN1 :1; /*!< Qualifier mode set for pin 1 */ + uint32_t PIN2 :1; /*!< Qualifier mode set for pin 2 */ + uint32_t PIN3 :1; /*!< Qualifier mode set for pin 3 */ + uint32_t PIN4 :1; /*!< Qualifier mode set for pin 4 */ + uint32_t PIN5 :1; /*!< Qualifier mode set for pin 5 */ + uint32_t PIN6 :1; /*!< Qualifier mode set for pin 6 */ + uint32_t PIN7 :1; /*!< Qualifier mode set for pin 7 */ + uint32_t PIN8 :1; /*!< Qualifier mode set for pin 8 */ + uint32_t PIN9 :1; /*!< Qualifier mode set for pin 9 */ + uint32_t PIN10 :1; /*!< Qualifier mode set for pin 10 */ + uint32_t PIN11 :1; /*!< Qualifier mode set for pin 11 */ + uint32_t PIN12 :1; /*!< Qualifier mode set for pin 12 */ + uint32_t PIN13 :1; /*!< Qualifier mode set for pin 13 */ + uint32_t PIN14 :1; /*!< Qualifier mode set for pin 14 */ + uint32_t PIN15 :1; /*!< Qualifier mode set for pin 15 */ +} _GPIO_QUALMODESET_bits; + +/* Bit field positions: */ +#define GPIO_QUALMODESET_PIN0_Pos 0 /*!< Qualifier mode set for pin 0 */ +#define GPIO_QUALMODESET_PIN1_Pos 1 /*!< Qualifier mode set for pin 1 */ +#define GPIO_QUALMODESET_PIN2_Pos 2 /*!< Qualifier mode set for pin 2 */ +#define GPIO_QUALMODESET_PIN3_Pos 3 /*!< Qualifier mode set for pin 3 */ +#define GPIO_QUALMODESET_PIN4_Pos 4 /*!< Qualifier mode set for pin 4 */ +#define GPIO_QUALMODESET_PIN5_Pos 5 /*!< Qualifier mode set for pin 5 */ +#define GPIO_QUALMODESET_PIN6_Pos 6 /*!< Qualifier mode set for pin 6 */ +#define GPIO_QUALMODESET_PIN7_Pos 7 /*!< Qualifier mode set for pin 7 */ +#define GPIO_QUALMODESET_PIN8_Pos 8 /*!< Qualifier mode set for pin 8 */ +#define GPIO_QUALMODESET_PIN9_Pos 9 /*!< Qualifier mode set for pin 9 */ +#define GPIO_QUALMODESET_PIN10_Pos 10 /*!< Qualifier mode set for pin 10 */ +#define GPIO_QUALMODESET_PIN11_Pos 11 /*!< Qualifier mode set for pin 11 */ +#define GPIO_QUALMODESET_PIN12_Pos 12 /*!< Qualifier mode set for pin 12 */ +#define GPIO_QUALMODESET_PIN13_Pos 13 /*!< Qualifier mode set for pin 13 */ +#define GPIO_QUALMODESET_PIN14_Pos 14 /*!< Qualifier mode set for pin 14 */ +#define GPIO_QUALMODESET_PIN15_Pos 15 /*!< Qualifier mode set for pin 15 */ + +/* Bit field masks: */ +#define GPIO_QUALMODESET_PIN0_Msk 0x00000001UL /*!< Qualifier mode set for pin 0 */ +#define GPIO_QUALMODESET_PIN1_Msk 0x00000002UL /*!< Qualifier mode set for pin 1 */ +#define GPIO_QUALMODESET_PIN2_Msk 0x00000004UL /*!< Qualifier mode set for pin 2 */ +#define GPIO_QUALMODESET_PIN3_Msk 0x00000008UL /*!< Qualifier mode set for pin 3 */ +#define GPIO_QUALMODESET_PIN4_Msk 0x00000010UL /*!< Qualifier mode set for pin 4 */ +#define GPIO_QUALMODESET_PIN5_Msk 0x00000020UL /*!< Qualifier mode set for pin 5 */ +#define GPIO_QUALMODESET_PIN6_Msk 0x00000040UL /*!< Qualifier mode set for pin 6 */ +#define GPIO_QUALMODESET_PIN7_Msk 0x00000080UL /*!< Qualifier mode set for pin 7 */ +#define GPIO_QUALMODESET_PIN8_Msk 0x00000100UL /*!< Qualifier mode set for pin 8 */ +#define GPIO_QUALMODESET_PIN9_Msk 0x00000200UL /*!< Qualifier mode set for pin 9 */ +#define GPIO_QUALMODESET_PIN10_Msk 0x00000400UL /*!< Qualifier mode set for pin 10 */ +#define GPIO_QUALMODESET_PIN11_Msk 0x00000800UL /*!< Qualifier mode set for pin 11 */ +#define GPIO_QUALMODESET_PIN12_Msk 0x00001000UL /*!< Qualifier mode set for pin 12 */ +#define GPIO_QUALMODESET_PIN13_Msk 0x00002000UL /*!< Qualifier mode set for pin 13 */ +#define GPIO_QUALMODESET_PIN14_Msk 0x00004000UL /*!< Qualifier mode set for pin 14 */ +#define GPIO_QUALMODESET_PIN15_Msk 0x00008000UL /*!< Qualifier mode set for pin 15 */ + +/*-- QUALMODECLR: Qualifier mode clear register --------------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< Qualifier mode clear for pin 0 */ + uint32_t PIN1 :1; /*!< Qualifier mode clear for pin 1 */ + uint32_t PIN2 :1; /*!< Qualifier mode clear for pin 2 */ + uint32_t PIN3 :1; /*!< Qualifier mode clear for pin 3 */ + uint32_t PIN4 :1; /*!< Qualifier mode clear for pin 4 */ + uint32_t PIN5 :1; /*!< Qualifier mode clear for pin 5 */ + uint32_t PIN6 :1; /*!< Qualifier mode clear for pin 6 */ + uint32_t PIN7 :1; /*!< Qualifier mode clear for pin 7 */ + uint32_t PIN8 :1; /*!< Qualifier mode clear for pin 8 */ + uint32_t PIN9 :1; /*!< Qualifier mode clear for pin 9 */ + uint32_t PIN10 :1; /*!< Qualifier mode clear for pin 10 */ + uint32_t PIN11 :1; /*!< Qualifier mode clear for pin 11 */ + uint32_t PIN12 :1; /*!< Qualifier mode clear for pin 12 */ + uint32_t PIN13 :1; /*!< Qualifier mode clear for pin 13 */ + uint32_t PIN14 :1; /*!< Qualifier mode clear for pin 14 */ + uint32_t PIN15 :1; /*!< Qualifier mode clear for pin 15 */ +} _GPIO_QUALMODECLR_bits; + +/* Bit field positions: */ +#define GPIO_QUALMODECLR_PIN0_Pos 0 /*!< Qualifier mode clear for pin 0 */ +#define GPIO_QUALMODECLR_PIN1_Pos 1 /*!< Qualifier mode clear for pin 1 */ +#define GPIO_QUALMODECLR_PIN2_Pos 2 /*!< Qualifier mode clear for pin 2 */ +#define GPIO_QUALMODECLR_PIN3_Pos 3 /*!< Qualifier mode clear for pin 3 */ +#define GPIO_QUALMODECLR_PIN4_Pos 4 /*!< Qualifier mode clear for pin 4 */ +#define GPIO_QUALMODECLR_PIN5_Pos 5 /*!< Qualifier mode clear for pin 5 */ +#define GPIO_QUALMODECLR_PIN6_Pos 6 /*!< Qualifier mode clear for pin 6 */ +#define GPIO_QUALMODECLR_PIN7_Pos 7 /*!< Qualifier mode clear for pin 7 */ +#define GPIO_QUALMODECLR_PIN8_Pos 8 /*!< Qualifier mode clear for pin 8 */ +#define GPIO_QUALMODECLR_PIN9_Pos 9 /*!< Qualifier mode clear for pin 9 */ +#define GPIO_QUALMODECLR_PIN10_Pos 10 /*!< Qualifier mode clear for pin 10 */ +#define GPIO_QUALMODECLR_PIN11_Pos 11 /*!< Qualifier mode clear for pin 11 */ +#define GPIO_QUALMODECLR_PIN12_Pos 12 /*!< Qualifier mode clear for pin 12 */ +#define GPIO_QUALMODECLR_PIN13_Pos 13 /*!< Qualifier mode clear for pin 13 */ +#define GPIO_QUALMODECLR_PIN14_Pos 14 /*!< Qualifier mode clear for pin 14 */ +#define GPIO_QUALMODECLR_PIN15_Pos 15 /*!< Qualifier mode clear for pin 15 */ + +/* Bit field masks: */ +#define GPIO_QUALMODECLR_PIN0_Msk 0x00000001UL /*!< Qualifier mode clear for pin 0 */ +#define GPIO_QUALMODECLR_PIN1_Msk 0x00000002UL /*!< Qualifier mode clear for pin 1 */ +#define GPIO_QUALMODECLR_PIN2_Msk 0x00000004UL /*!< Qualifier mode clear for pin 2 */ +#define GPIO_QUALMODECLR_PIN3_Msk 0x00000008UL /*!< Qualifier mode clear for pin 3 */ +#define GPIO_QUALMODECLR_PIN4_Msk 0x00000010UL /*!< Qualifier mode clear for pin 4 */ +#define GPIO_QUALMODECLR_PIN5_Msk 0x00000020UL /*!< Qualifier mode clear for pin 5 */ +#define GPIO_QUALMODECLR_PIN6_Msk 0x00000040UL /*!< Qualifier mode clear for pin 6 */ +#define GPIO_QUALMODECLR_PIN7_Msk 0x00000080UL /*!< Qualifier mode clear for pin 7 */ +#define GPIO_QUALMODECLR_PIN8_Msk 0x00000100UL /*!< Qualifier mode clear for pin 8 */ +#define GPIO_QUALMODECLR_PIN9_Msk 0x00000200UL /*!< Qualifier mode clear for pin 9 */ +#define GPIO_QUALMODECLR_PIN10_Msk 0x00000400UL /*!< Qualifier mode clear for pin 10 */ +#define GPIO_QUALMODECLR_PIN11_Msk 0x00000800UL /*!< Qualifier mode clear for pin 11 */ +#define GPIO_QUALMODECLR_PIN12_Msk 0x00001000UL /*!< Qualifier mode clear for pin 12 */ +#define GPIO_QUALMODECLR_PIN13_Msk 0x00002000UL /*!< Qualifier mode clear for pin 13 */ +#define GPIO_QUALMODECLR_PIN14_Msk 0x00004000UL /*!< Qualifier mode clear for pin 14 */ +#define GPIO_QUALMODECLR_PIN15_Msk 0x00008000UL /*!< Qualifier mode clear for pin 15 */ + +/*-- QUALSAMPLE: Qualifier sample period register ------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :8; /*!< Qualifier sample period */ +} _GPIO_QUALSAMPLE_bits; + +/* Bit field positions: */ +#define GPIO_QUALSAMPLE_VAL_Pos 0 /*!< Qualifier sample period */ + +/* Bit field masks: */ +#define GPIO_QUALSAMPLE_VAL_Msk 0x000000FFUL /*!< Qualifier sample period */ + +/*-- INTENSET: Interrupt enable register ---------------------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< Interrupt enable for pin 0 */ + uint32_t PIN1 :1; /*!< Interrupt enable for pin 1 */ + uint32_t PIN2 :1; /*!< Interrupt enable for pin 2 */ + uint32_t PIN3 :1; /*!< Interrupt enable for pin 3 */ + uint32_t PIN4 :1; /*!< Interrupt enable for pin 4 */ + uint32_t PIN5 :1; /*!< Interrupt enable for pin 5 */ + uint32_t PIN6 :1; /*!< Interrupt enable for pin 6 */ + uint32_t PIN7 :1; /*!< Interrupt enable for pin 7 */ + uint32_t PIN8 :1; /*!< Interrupt enable for pin 8 */ + uint32_t PIN9 :1; /*!< Interrupt enable for pin 9 */ + uint32_t PIN10 :1; /*!< Interrupt enable for pin 10 */ + uint32_t PIN11 :1; /*!< Interrupt enable for pin 11 */ + uint32_t PIN12 :1; /*!< Interrupt enable for pin 12 */ + uint32_t PIN13 :1; /*!< Interrupt enable for pin 13 */ + uint32_t PIN14 :1; /*!< Interrupt enable for pin 14 */ + uint32_t PIN15 :1; /*!< Interrupt enable for pin 15 */ +} _GPIO_INTENSET_bits; + +/* Bit field positions: */ +#define GPIO_INTENSET_PIN0_Pos 0 /*!< Interrupt enable for pin 0 */ +#define GPIO_INTENSET_PIN1_Pos 1 /*!< Interrupt enable for pin 1 */ +#define GPIO_INTENSET_PIN2_Pos 2 /*!< Interrupt enable for pin 2 */ +#define GPIO_INTENSET_PIN3_Pos 3 /*!< Interrupt enable for pin 3 */ +#define GPIO_INTENSET_PIN4_Pos 4 /*!< Interrupt enable for pin 4 */ +#define GPIO_INTENSET_PIN5_Pos 5 /*!< Interrupt enable for pin 5 */ +#define GPIO_INTENSET_PIN6_Pos 6 /*!< Interrupt enable for pin 6 */ +#define GPIO_INTENSET_PIN7_Pos 7 /*!< Interrupt enable for pin 7 */ +#define GPIO_INTENSET_PIN8_Pos 8 /*!< Interrupt enable for pin 8 */ +#define GPIO_INTENSET_PIN9_Pos 9 /*!< Interrupt enable for pin 9 */ +#define GPIO_INTENSET_PIN10_Pos 10 /*!< Interrupt enable for pin 10 */ +#define GPIO_INTENSET_PIN11_Pos 11 /*!< Interrupt enable for pin 11 */ +#define GPIO_INTENSET_PIN12_Pos 12 /*!< Interrupt enable for pin 12 */ +#define GPIO_INTENSET_PIN13_Pos 13 /*!< Interrupt enable for pin 13 */ +#define GPIO_INTENSET_PIN14_Pos 14 /*!< Interrupt enable for pin 14 */ +#define GPIO_INTENSET_PIN15_Pos 15 /*!< Interrupt enable for pin 15 */ + +/* Bit field masks: */ +#define GPIO_INTENSET_PIN0_Msk 0x00000001UL /*!< Interrupt enable for pin 0 */ +#define GPIO_INTENSET_PIN1_Msk 0x00000002UL /*!< Interrupt enable for pin 1 */ +#define GPIO_INTENSET_PIN2_Msk 0x00000004UL /*!< Interrupt enable for pin 2 */ +#define GPIO_INTENSET_PIN3_Msk 0x00000008UL /*!< Interrupt enable for pin 3 */ +#define GPIO_INTENSET_PIN4_Msk 0x00000010UL /*!< Interrupt enable for pin 4 */ +#define GPIO_INTENSET_PIN5_Msk 0x00000020UL /*!< Interrupt enable for pin 5 */ +#define GPIO_INTENSET_PIN6_Msk 0x00000040UL /*!< Interrupt enable for pin 6 */ +#define GPIO_INTENSET_PIN7_Msk 0x00000080UL /*!< Interrupt enable for pin 7 */ +#define GPIO_INTENSET_PIN8_Msk 0x00000100UL /*!< Interrupt enable for pin 8 */ +#define GPIO_INTENSET_PIN9_Msk 0x00000200UL /*!< Interrupt enable for pin 9 */ +#define GPIO_INTENSET_PIN10_Msk 0x00000400UL /*!< Interrupt enable for pin 10 */ +#define GPIO_INTENSET_PIN11_Msk 0x00000800UL /*!< Interrupt enable for pin 11 */ +#define GPIO_INTENSET_PIN12_Msk 0x00001000UL /*!< Interrupt enable for pin 12 */ +#define GPIO_INTENSET_PIN13_Msk 0x00002000UL /*!< Interrupt enable for pin 13 */ +#define GPIO_INTENSET_PIN14_Msk 0x00004000UL /*!< Interrupt enable for pin 14 */ +#define GPIO_INTENSET_PIN15_Msk 0x00008000UL /*!< Interrupt enable for pin 15 */ + +/*-- INTENCLR: Interrupt disable register --------------------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< Interrupt disable for pin 0 */ + uint32_t PIN1 :1; /*!< Interrupt disable for pin 1 */ + uint32_t PIN2 :1; /*!< Interrupt disable for pin 2 */ + uint32_t PIN3 :1; /*!< Interrupt disable for pin 3 */ + uint32_t PIN4 :1; /*!< Interrupt disable for pin 4 */ + uint32_t PIN5 :1; /*!< Interrupt disable for pin 5 */ + uint32_t PIN6 :1; /*!< Interrupt disable for pin 6 */ + uint32_t PIN7 :1; /*!< Interrupt disable for pin 7 */ + uint32_t PIN8 :1; /*!< Interrupt disable for pin 8 */ + uint32_t PIN9 :1; /*!< Interrupt disable for pin 9 */ + uint32_t PIN10 :1; /*!< Interrupt disable for pin 10 */ + uint32_t PIN11 :1; /*!< Interrupt disable for pin 11 */ + uint32_t PIN12 :1; /*!< Interrupt disable for pin 12 */ + uint32_t PIN13 :1; /*!< Interrupt disable for pin 13 */ + uint32_t PIN14 :1; /*!< Interrupt disable for pin 14 */ + uint32_t PIN15 :1; /*!< Interrupt disable for pin 15 */ +} _GPIO_INTENCLR_bits; + +/* Bit field positions: */ +#define GPIO_INTENCLR_PIN0_Pos 0 /*!< Interrupt disable for pin 0 */ +#define GPIO_INTENCLR_PIN1_Pos 1 /*!< Interrupt disable for pin 1 */ +#define GPIO_INTENCLR_PIN2_Pos 2 /*!< Interrupt disable for pin 2 */ +#define GPIO_INTENCLR_PIN3_Pos 3 /*!< Interrupt disable for pin 3 */ +#define GPIO_INTENCLR_PIN4_Pos 4 /*!< Interrupt disable for pin 4 */ +#define GPIO_INTENCLR_PIN5_Pos 5 /*!< Interrupt disable for pin 5 */ +#define GPIO_INTENCLR_PIN6_Pos 6 /*!< Interrupt disable for pin 6 */ +#define GPIO_INTENCLR_PIN7_Pos 7 /*!< Interrupt disable for pin 7 */ +#define GPIO_INTENCLR_PIN8_Pos 8 /*!< Interrupt disable for pin 8 */ +#define GPIO_INTENCLR_PIN9_Pos 9 /*!< Interrupt disable for pin 9 */ +#define GPIO_INTENCLR_PIN10_Pos 10 /*!< Interrupt disable for pin 10 */ +#define GPIO_INTENCLR_PIN11_Pos 11 /*!< Interrupt disable for pin 11 */ +#define GPIO_INTENCLR_PIN12_Pos 12 /*!< Interrupt disable for pin 12 */ +#define GPIO_INTENCLR_PIN13_Pos 13 /*!< Interrupt disable for pin 13 */ +#define GPIO_INTENCLR_PIN14_Pos 14 /*!< Interrupt disable for pin 14 */ +#define GPIO_INTENCLR_PIN15_Pos 15 /*!< Interrupt disable for pin 15 */ + +/* Bit field masks: */ +#define GPIO_INTENCLR_PIN0_Msk 0x00000001UL /*!< Interrupt disable for pin 0 */ +#define GPIO_INTENCLR_PIN1_Msk 0x00000002UL /*!< Interrupt disable for pin 1 */ +#define GPIO_INTENCLR_PIN2_Msk 0x00000004UL /*!< Interrupt disable for pin 2 */ +#define GPIO_INTENCLR_PIN3_Msk 0x00000008UL /*!< Interrupt disable for pin 3 */ +#define GPIO_INTENCLR_PIN4_Msk 0x00000010UL /*!< Interrupt disable for pin 4 */ +#define GPIO_INTENCLR_PIN5_Msk 0x00000020UL /*!< Interrupt disable for pin 5 */ +#define GPIO_INTENCLR_PIN6_Msk 0x00000040UL /*!< Interrupt disable for pin 6 */ +#define GPIO_INTENCLR_PIN7_Msk 0x00000080UL /*!< Interrupt disable for pin 7 */ +#define GPIO_INTENCLR_PIN8_Msk 0x00000100UL /*!< Interrupt disable for pin 8 */ +#define GPIO_INTENCLR_PIN9_Msk 0x00000200UL /*!< Interrupt disable for pin 9 */ +#define GPIO_INTENCLR_PIN10_Msk 0x00000400UL /*!< Interrupt disable for pin 10 */ +#define GPIO_INTENCLR_PIN11_Msk 0x00000800UL /*!< Interrupt disable for pin 11 */ +#define GPIO_INTENCLR_PIN12_Msk 0x00001000UL /*!< Interrupt disable for pin 12 */ +#define GPIO_INTENCLR_PIN13_Msk 0x00002000UL /*!< Interrupt disable for pin 13 */ +#define GPIO_INTENCLR_PIN14_Msk 0x00004000UL /*!< Interrupt disable for pin 14 */ +#define GPIO_INTENCLR_PIN15_Msk 0x00008000UL /*!< Interrupt disable for pin 15 */ + +/*-- INTTYPESET: Interrupt type set register -----------------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< Interrupt type set for pin 0 */ + uint32_t PIN1 :1; /*!< Interrupt type set for pin 1 */ + uint32_t PIN2 :1; /*!< Interrupt type set for pin 2 */ + uint32_t PIN3 :1; /*!< Interrupt type set for pin 3 */ + uint32_t PIN4 :1; /*!< Interrupt type set for pin 4 */ + uint32_t PIN5 :1; /*!< Interrupt type set for pin 5 */ + uint32_t PIN6 :1; /*!< Interrupt type set for pin 6 */ + uint32_t PIN7 :1; /*!< Interrupt type set for pin 7 */ + uint32_t PIN8 :1; /*!< Interrupt type set for pin 8 */ + uint32_t PIN9 :1; /*!< Interrupt type set for pin 9 */ + uint32_t PIN10 :1; /*!< Interrupt type set for pin 10 */ + uint32_t PIN11 :1; /*!< Interrupt type set for pin 11 */ + uint32_t PIN12 :1; /*!< Interrupt type set for pin 12 */ + uint32_t PIN13 :1; /*!< Interrupt type set for pin 13 */ + uint32_t PIN14 :1; /*!< Interrupt type set for pin 14 */ + uint32_t PIN15 :1; /*!< Interrupt type set for pin 15 */ +} _GPIO_INTTYPESET_bits; + +/* Bit field positions: */ +#define GPIO_INTTYPESET_PIN0_Pos 0 /*!< Interrupt type set for pin 0 */ +#define GPIO_INTTYPESET_PIN1_Pos 1 /*!< Interrupt type set for pin 1 */ +#define GPIO_INTTYPESET_PIN2_Pos 2 /*!< Interrupt type set for pin 2 */ +#define GPIO_INTTYPESET_PIN3_Pos 3 /*!< Interrupt type set for pin 3 */ +#define GPIO_INTTYPESET_PIN4_Pos 4 /*!< Interrupt type set for pin 4 */ +#define GPIO_INTTYPESET_PIN5_Pos 5 /*!< Interrupt type set for pin 5 */ +#define GPIO_INTTYPESET_PIN6_Pos 6 /*!< Interrupt type set for pin 6 */ +#define GPIO_INTTYPESET_PIN7_Pos 7 /*!< Interrupt type set for pin 7 */ +#define GPIO_INTTYPESET_PIN8_Pos 8 /*!< Interrupt type set for pin 8 */ +#define GPIO_INTTYPESET_PIN9_Pos 9 /*!< Interrupt type set for pin 9 */ +#define GPIO_INTTYPESET_PIN10_Pos 10 /*!< Interrupt type set for pin 10 */ +#define GPIO_INTTYPESET_PIN11_Pos 11 /*!< Interrupt type set for pin 11 */ +#define GPIO_INTTYPESET_PIN12_Pos 12 /*!< Interrupt type set for pin 12 */ +#define GPIO_INTTYPESET_PIN13_Pos 13 /*!< Interrupt type set for pin 13 */ +#define GPIO_INTTYPESET_PIN14_Pos 14 /*!< Interrupt type set for pin 14 */ +#define GPIO_INTTYPESET_PIN15_Pos 15 /*!< Interrupt type set for pin 15 */ + +/* Bit field masks: */ +#define GPIO_INTTYPESET_PIN0_Msk 0x00000001UL /*!< Interrupt type set for pin 0 */ +#define GPIO_INTTYPESET_PIN1_Msk 0x00000002UL /*!< Interrupt type set for pin 1 */ +#define GPIO_INTTYPESET_PIN2_Msk 0x00000004UL /*!< Interrupt type set for pin 2 */ +#define GPIO_INTTYPESET_PIN3_Msk 0x00000008UL /*!< Interrupt type set for pin 3 */ +#define GPIO_INTTYPESET_PIN4_Msk 0x00000010UL /*!< Interrupt type set for pin 4 */ +#define GPIO_INTTYPESET_PIN5_Msk 0x00000020UL /*!< Interrupt type set for pin 5 */ +#define GPIO_INTTYPESET_PIN6_Msk 0x00000040UL /*!< Interrupt type set for pin 6 */ +#define GPIO_INTTYPESET_PIN7_Msk 0x00000080UL /*!< Interrupt type set for pin 7 */ +#define GPIO_INTTYPESET_PIN8_Msk 0x00000100UL /*!< Interrupt type set for pin 8 */ +#define GPIO_INTTYPESET_PIN9_Msk 0x00000200UL /*!< Interrupt type set for pin 9 */ +#define GPIO_INTTYPESET_PIN10_Msk 0x00000400UL /*!< Interrupt type set for pin 10 */ +#define GPIO_INTTYPESET_PIN11_Msk 0x00000800UL /*!< Interrupt type set for pin 11 */ +#define GPIO_INTTYPESET_PIN12_Msk 0x00001000UL /*!< Interrupt type set for pin 12 */ +#define GPIO_INTTYPESET_PIN13_Msk 0x00002000UL /*!< Interrupt type set for pin 13 */ +#define GPIO_INTTYPESET_PIN14_Msk 0x00004000UL /*!< Interrupt type set for pin 14 */ +#define GPIO_INTTYPESET_PIN15_Msk 0x00008000UL /*!< Interrupt type set for pin 15 */ + +/*-- INTTYPECLR: Interrupt type clear register ---------------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< Interrupt type clear for pin 0 */ + uint32_t PIN1 :1; /*!< Interrupt type clear for pin 1 */ + uint32_t PIN2 :1; /*!< Interrupt type clear for pin 2 */ + uint32_t PIN3 :1; /*!< Interrupt type clear for pin 3 */ + uint32_t PIN4 :1; /*!< Interrupt type clear for pin 4 */ + uint32_t PIN5 :1; /*!< Interrupt type clear for pin 5 */ + uint32_t PIN6 :1; /*!< Interrupt type clear for pin 6 */ + uint32_t PIN7 :1; /*!< Interrupt type clear for pin 7 */ + uint32_t PIN8 :1; /*!< Interrupt type clear for pin 8 */ + uint32_t PIN9 :1; /*!< Interrupt type clear for pin 9 */ + uint32_t PIN10 :1; /*!< Interrupt type clear for pin 10 */ + uint32_t PIN11 :1; /*!< Interrupt type clear for pin 11 */ + uint32_t PIN12 :1; /*!< Interrupt type clear for pin 12 */ + uint32_t PIN13 :1; /*!< Interrupt type clear for pin 13 */ + uint32_t PIN14 :1; /*!< Interrupt type clear for pin 14 */ + uint32_t PIN15 :1; /*!< Interrupt type clear for pin 15 */ +} _GPIO_INTTYPECLR_bits; + +/* Bit field positions: */ +#define GPIO_INTTYPECLR_PIN0_Pos 0 /*!< Interrupt type clear for pin 0 */ +#define GPIO_INTTYPECLR_PIN1_Pos 1 /*!< Interrupt type clear for pin 1 */ +#define GPIO_INTTYPECLR_PIN2_Pos 2 /*!< Interrupt type clear for pin 2 */ +#define GPIO_INTTYPECLR_PIN3_Pos 3 /*!< Interrupt type clear for pin 3 */ +#define GPIO_INTTYPECLR_PIN4_Pos 4 /*!< Interrupt type clear for pin 4 */ +#define GPIO_INTTYPECLR_PIN5_Pos 5 /*!< Interrupt type clear for pin 5 */ +#define GPIO_INTTYPECLR_PIN6_Pos 6 /*!< Interrupt type clear for pin 6 */ +#define GPIO_INTTYPECLR_PIN7_Pos 7 /*!< Interrupt type clear for pin 7 */ +#define GPIO_INTTYPECLR_PIN8_Pos 8 /*!< Interrupt type clear for pin 8 */ +#define GPIO_INTTYPECLR_PIN9_Pos 9 /*!< Interrupt type clear for pin 9 */ +#define GPIO_INTTYPECLR_PIN10_Pos 10 /*!< Interrupt type clear for pin 10 */ +#define GPIO_INTTYPECLR_PIN11_Pos 11 /*!< Interrupt type clear for pin 11 */ +#define GPIO_INTTYPECLR_PIN12_Pos 12 /*!< Interrupt type clear for pin 12 */ +#define GPIO_INTTYPECLR_PIN13_Pos 13 /*!< Interrupt type clear for pin 13 */ +#define GPIO_INTTYPECLR_PIN14_Pos 14 /*!< Interrupt type clear for pin 14 */ +#define GPIO_INTTYPECLR_PIN15_Pos 15 /*!< Interrupt type clear for pin 15 */ + +/* Bit field masks: */ +#define GPIO_INTTYPECLR_PIN0_Msk 0x00000001UL /*!< Interrupt type clear for pin 0 */ +#define GPIO_INTTYPECLR_PIN1_Msk 0x00000002UL /*!< Interrupt type clear for pin 1 */ +#define GPIO_INTTYPECLR_PIN2_Msk 0x00000004UL /*!< Interrupt type clear for pin 2 */ +#define GPIO_INTTYPECLR_PIN3_Msk 0x00000008UL /*!< Interrupt type clear for pin 3 */ +#define GPIO_INTTYPECLR_PIN4_Msk 0x00000010UL /*!< Interrupt type clear for pin 4 */ +#define GPIO_INTTYPECLR_PIN5_Msk 0x00000020UL /*!< Interrupt type clear for pin 5 */ +#define GPIO_INTTYPECLR_PIN6_Msk 0x00000040UL /*!< Interrupt type clear for pin 6 */ +#define GPIO_INTTYPECLR_PIN7_Msk 0x00000080UL /*!< Interrupt type clear for pin 7 */ +#define GPIO_INTTYPECLR_PIN8_Msk 0x00000100UL /*!< Interrupt type clear for pin 8 */ +#define GPIO_INTTYPECLR_PIN9_Msk 0x00000200UL /*!< Interrupt type clear for pin 9 */ +#define GPIO_INTTYPECLR_PIN10_Msk 0x00000400UL /*!< Interrupt type clear for pin 10 */ +#define GPIO_INTTYPECLR_PIN11_Msk 0x00000800UL /*!< Interrupt type clear for pin 11 */ +#define GPIO_INTTYPECLR_PIN12_Msk 0x00001000UL /*!< Interrupt type clear for pin 12 */ +#define GPIO_INTTYPECLR_PIN13_Msk 0x00002000UL /*!< Interrupt type clear for pin 13 */ +#define GPIO_INTTYPECLR_PIN14_Msk 0x00004000UL /*!< Interrupt type clear for pin 14 */ +#define GPIO_INTTYPECLR_PIN15_Msk 0x00008000UL /*!< Interrupt type clear for pin 15 */ + +/*-- INTPOLSET: Interrupt polarity set register --------------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< Interrupt polarity set for pin 0 */ + uint32_t PIN1 :1; /*!< Interrupt polarity set for pin 1 */ + uint32_t PIN2 :1; /*!< Interrupt polarity set for pin 2 */ + uint32_t PIN3 :1; /*!< Interrupt polarity set for pin 3 */ + uint32_t PIN4 :1; /*!< Interrupt polarity set for pin 4 */ + uint32_t PIN5 :1; /*!< Interrupt polarity set for pin 5 */ + uint32_t PIN6 :1; /*!< Interrupt polarity set for pin 6 */ + uint32_t PIN7 :1; /*!< Interrupt polarity set for pin 7 */ + uint32_t PIN8 :1; /*!< Interrupt polarity set for pin 8 */ + uint32_t PIN9 :1; /*!< Interrupt polarity set for pin 9 */ + uint32_t PIN10 :1; /*!< Interrupt polarity set for pin 10 */ + uint32_t PIN11 :1; /*!< Interrupt polarity set for pin 11 */ + uint32_t PIN12 :1; /*!< Interrupt polarity set for pin 12 */ + uint32_t PIN13 :1; /*!< Interrupt polarity set for pin 13 */ + uint32_t PIN14 :1; /*!< Interrupt polarity set for pin 14 */ + uint32_t PIN15 :1; /*!< Interrupt polarity set for pin 15 */ +} _GPIO_INTPOLSET_bits; + +/* Bit field positions: */ +#define GPIO_INTPOLSET_PIN0_Pos 0 /*!< Interrupt polarity set for pin 0 */ +#define GPIO_INTPOLSET_PIN1_Pos 1 /*!< Interrupt polarity set for pin 1 */ +#define GPIO_INTPOLSET_PIN2_Pos 2 /*!< Interrupt polarity set for pin 2 */ +#define GPIO_INTPOLSET_PIN3_Pos 3 /*!< Interrupt polarity set for pin 3 */ +#define GPIO_INTPOLSET_PIN4_Pos 4 /*!< Interrupt polarity set for pin 4 */ +#define GPIO_INTPOLSET_PIN5_Pos 5 /*!< Interrupt polarity set for pin 5 */ +#define GPIO_INTPOLSET_PIN6_Pos 6 /*!< Interrupt polarity set for pin 6 */ +#define GPIO_INTPOLSET_PIN7_Pos 7 /*!< Interrupt polarity set for pin 7 */ +#define GPIO_INTPOLSET_PIN8_Pos 8 /*!< Interrupt polarity set for pin 8 */ +#define GPIO_INTPOLSET_PIN9_Pos 9 /*!< Interrupt polarity set for pin 9 */ +#define GPIO_INTPOLSET_PIN10_Pos 10 /*!< Interrupt polarity set for pin 10 */ +#define GPIO_INTPOLSET_PIN11_Pos 11 /*!< Interrupt polarity set for pin 11 */ +#define GPIO_INTPOLSET_PIN12_Pos 12 /*!< Interrupt polarity set for pin 12 */ +#define GPIO_INTPOLSET_PIN13_Pos 13 /*!< Interrupt polarity set for pin 13 */ +#define GPIO_INTPOLSET_PIN14_Pos 14 /*!< Interrupt polarity set for pin 14 */ +#define GPIO_INTPOLSET_PIN15_Pos 15 /*!< Interrupt polarity set for pin 15 */ + +/* Bit field masks: */ +#define GPIO_INTPOLSET_PIN0_Msk 0x00000001UL /*!< Interrupt polarity set for pin 0 */ +#define GPIO_INTPOLSET_PIN1_Msk 0x00000002UL /*!< Interrupt polarity set for pin 1 */ +#define GPIO_INTPOLSET_PIN2_Msk 0x00000004UL /*!< Interrupt polarity set for pin 2 */ +#define GPIO_INTPOLSET_PIN3_Msk 0x00000008UL /*!< Interrupt polarity set for pin 3 */ +#define GPIO_INTPOLSET_PIN4_Msk 0x00000010UL /*!< Interrupt polarity set for pin 4 */ +#define GPIO_INTPOLSET_PIN5_Msk 0x00000020UL /*!< Interrupt polarity set for pin 5 */ +#define GPIO_INTPOLSET_PIN6_Msk 0x00000040UL /*!< Interrupt polarity set for pin 6 */ +#define GPIO_INTPOLSET_PIN7_Msk 0x00000080UL /*!< Interrupt polarity set for pin 7 */ +#define GPIO_INTPOLSET_PIN8_Msk 0x00000100UL /*!< Interrupt polarity set for pin 8 */ +#define GPIO_INTPOLSET_PIN9_Msk 0x00000200UL /*!< Interrupt polarity set for pin 9 */ +#define GPIO_INTPOLSET_PIN10_Msk 0x00000400UL /*!< Interrupt polarity set for pin 10 */ +#define GPIO_INTPOLSET_PIN11_Msk 0x00000800UL /*!< Interrupt polarity set for pin 11 */ +#define GPIO_INTPOLSET_PIN12_Msk 0x00001000UL /*!< Interrupt polarity set for pin 12 */ +#define GPIO_INTPOLSET_PIN13_Msk 0x00002000UL /*!< Interrupt polarity set for pin 13 */ +#define GPIO_INTPOLSET_PIN14_Msk 0x00004000UL /*!< Interrupt polarity set for pin 14 */ +#define GPIO_INTPOLSET_PIN15_Msk 0x00008000UL /*!< Interrupt polarity set for pin 15 */ + +/*-- INTPOLCLR: Interrupt polarity clear register ------------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< Interrupt polarity clear for pin 0 */ + uint32_t PIN1 :1; /*!< Interrupt polarity clear for pin 1 */ + uint32_t PIN2 :1; /*!< Interrupt polarity clear for pin 2 */ + uint32_t PIN3 :1; /*!< Interrupt polarity clear for pin 3 */ + uint32_t PIN4 :1; /*!< Interrupt polarity clear for pin 4 */ + uint32_t PIN5 :1; /*!< Interrupt polarity clear for pin 5 */ + uint32_t PIN6 :1; /*!< Interrupt polarity clear for pin 6 */ + uint32_t PIN7 :1; /*!< Interrupt polarity clear for pin 7 */ + uint32_t PIN8 :1; /*!< Interrupt polarity clear for pin 8 */ + uint32_t PIN9 :1; /*!< Interrupt polarity clear for pin 9 */ + uint32_t PIN10 :1; /*!< Interrupt polarity clear for pin 10 */ + uint32_t PIN11 :1; /*!< Interrupt polarity clear for pin 11 */ + uint32_t PIN12 :1; /*!< Interrupt polarity clear for pin 12 */ + uint32_t PIN13 :1; /*!< Interrupt polarity clear for pin 13 */ + uint32_t PIN14 :1; /*!< Interrupt polarity clear for pin 14 */ + uint32_t PIN15 :1; /*!< Interrupt polarity clear for pin 15 */ +} _GPIO_INTPOLCLR_bits; + +/* Bit field positions: */ +#define GPIO_INTPOLCLR_PIN0_Pos 0 /*!< Interrupt polarity clear for pin 0 */ +#define GPIO_INTPOLCLR_PIN1_Pos 1 /*!< Interrupt polarity clear for pin 1 */ +#define GPIO_INTPOLCLR_PIN2_Pos 2 /*!< Interrupt polarity clear for pin 2 */ +#define GPIO_INTPOLCLR_PIN3_Pos 3 /*!< Interrupt polarity clear for pin 3 */ +#define GPIO_INTPOLCLR_PIN4_Pos 4 /*!< Interrupt polarity clear for pin 4 */ +#define GPIO_INTPOLCLR_PIN5_Pos 5 /*!< Interrupt polarity clear for pin 5 */ +#define GPIO_INTPOLCLR_PIN6_Pos 6 /*!< Interrupt polarity clear for pin 6 */ +#define GPIO_INTPOLCLR_PIN7_Pos 7 /*!< Interrupt polarity clear for pin 7 */ +#define GPIO_INTPOLCLR_PIN8_Pos 8 /*!< Interrupt polarity clear for pin 8 */ +#define GPIO_INTPOLCLR_PIN9_Pos 9 /*!< Interrupt polarity clear for pin 9 */ +#define GPIO_INTPOLCLR_PIN10_Pos 10 /*!< Interrupt polarity clear for pin 10 */ +#define GPIO_INTPOLCLR_PIN11_Pos 11 /*!< Interrupt polarity clear for pin 11 */ +#define GPIO_INTPOLCLR_PIN12_Pos 12 /*!< Interrupt polarity clear for pin 12 */ +#define GPIO_INTPOLCLR_PIN13_Pos 13 /*!< Interrupt polarity clear for pin 13 */ +#define GPIO_INTPOLCLR_PIN14_Pos 14 /*!< Interrupt polarity clear for pin 14 */ +#define GPIO_INTPOLCLR_PIN15_Pos 15 /*!< Interrupt polarity clear for pin 15 */ + +/* Bit field masks: */ +#define GPIO_INTPOLCLR_PIN0_Msk 0x00000001UL /*!< Interrupt polarity clear for pin 0 */ +#define GPIO_INTPOLCLR_PIN1_Msk 0x00000002UL /*!< Interrupt polarity clear for pin 1 */ +#define GPIO_INTPOLCLR_PIN2_Msk 0x00000004UL /*!< Interrupt polarity clear for pin 2 */ +#define GPIO_INTPOLCLR_PIN3_Msk 0x00000008UL /*!< Interrupt polarity clear for pin 3 */ +#define GPIO_INTPOLCLR_PIN4_Msk 0x00000010UL /*!< Interrupt polarity clear for pin 4 */ +#define GPIO_INTPOLCLR_PIN5_Msk 0x00000020UL /*!< Interrupt polarity clear for pin 5 */ +#define GPIO_INTPOLCLR_PIN6_Msk 0x00000040UL /*!< Interrupt polarity clear for pin 6 */ +#define GPIO_INTPOLCLR_PIN7_Msk 0x00000080UL /*!< Interrupt polarity clear for pin 7 */ +#define GPIO_INTPOLCLR_PIN8_Msk 0x00000100UL /*!< Interrupt polarity clear for pin 8 */ +#define GPIO_INTPOLCLR_PIN9_Msk 0x00000200UL /*!< Interrupt polarity clear for pin 9 */ +#define GPIO_INTPOLCLR_PIN10_Msk 0x00000400UL /*!< Interrupt polarity clear for pin 10 */ +#define GPIO_INTPOLCLR_PIN11_Msk 0x00000800UL /*!< Interrupt polarity clear for pin 11 */ +#define GPIO_INTPOLCLR_PIN12_Msk 0x00001000UL /*!< Interrupt polarity clear for pin 12 */ +#define GPIO_INTPOLCLR_PIN13_Msk 0x00002000UL /*!< Interrupt polarity clear for pin 13 */ +#define GPIO_INTPOLCLR_PIN14_Msk 0x00004000UL /*!< Interrupt polarity clear for pin 14 */ +#define GPIO_INTPOLCLR_PIN15_Msk 0x00008000UL /*!< Interrupt polarity clear for pin 15 */ + +/*-- INTEDGESET: Interrupt every edge set register -----------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< Interrupt every edge set for pin 0 */ + uint32_t PIN1 :1; /*!< Interrupt every edge set for pin 1 */ + uint32_t PIN2 :1; /*!< Interrupt every edge set for pin 2 */ + uint32_t PIN3 :1; /*!< Interrupt every edge set for pin 3 */ + uint32_t PIN4 :1; /*!< Interrupt every edge set for pin 4 */ + uint32_t PIN5 :1; /*!< Interrupt every edge set for pin 5 */ + uint32_t PIN6 :1; /*!< Interrupt every edge set for pin 6 */ + uint32_t PIN7 :1; /*!< Interrupt every edge set for pin 7 */ + uint32_t PIN8 :1; /*!< Interrupt every edge set for pin 8 */ + uint32_t PIN9 :1; /*!< Interrupt every edge set for pin 9 */ + uint32_t PIN10 :1; /*!< Interrupt every edge set for pin 10 */ + uint32_t PIN11 :1; /*!< Interrupt every edge set for pin 11 */ + uint32_t PIN12 :1; /*!< Interrupt every edge set for pin 12 */ + uint32_t PIN13 :1; /*!< Interrupt every edge set for pin 13 */ + uint32_t PIN14 :1; /*!< Interrupt every edge set for pin 14 */ + uint32_t PIN15 :1; /*!< Interrupt every edge set for pin 15 */ +} _GPIO_INTEDGESET_bits; + +/* Bit field positions: */ +#define GPIO_INTEDGESET_PIN0_Pos 0 /*!< Interrupt every edge set for pin 0 */ +#define GPIO_INTEDGESET_PIN1_Pos 1 /*!< Interrupt every edge set for pin 1 */ +#define GPIO_INTEDGESET_PIN2_Pos 2 /*!< Interrupt every edge set for pin 2 */ +#define GPIO_INTEDGESET_PIN3_Pos 3 /*!< Interrupt every edge set for pin 3 */ +#define GPIO_INTEDGESET_PIN4_Pos 4 /*!< Interrupt every edge set for pin 4 */ +#define GPIO_INTEDGESET_PIN5_Pos 5 /*!< Interrupt every edge set for pin 5 */ +#define GPIO_INTEDGESET_PIN6_Pos 6 /*!< Interrupt every edge set for pin 6 */ +#define GPIO_INTEDGESET_PIN7_Pos 7 /*!< Interrupt every edge set for pin 7 */ +#define GPIO_INTEDGESET_PIN8_Pos 8 /*!< Interrupt every edge set for pin 8 */ +#define GPIO_INTEDGESET_PIN9_Pos 9 /*!< Interrupt every edge set for pin 9 */ +#define GPIO_INTEDGESET_PIN10_Pos 10 /*!< Interrupt every edge set for pin 10 */ +#define GPIO_INTEDGESET_PIN11_Pos 11 /*!< Interrupt every edge set for pin 11 */ +#define GPIO_INTEDGESET_PIN12_Pos 12 /*!< Interrupt every edge set for pin 12 */ +#define GPIO_INTEDGESET_PIN13_Pos 13 /*!< Interrupt every edge set for pin 13 */ +#define GPIO_INTEDGESET_PIN14_Pos 14 /*!< Interrupt every edge set for pin 14 */ +#define GPIO_INTEDGESET_PIN15_Pos 15 /*!< Interrupt every edge set for pin 15 */ + +/* Bit field masks: */ +#define GPIO_INTEDGESET_PIN0_Msk 0x00000001UL /*!< Interrupt every edge set for pin 0 */ +#define GPIO_INTEDGESET_PIN1_Msk 0x00000002UL /*!< Interrupt every edge set for pin 1 */ +#define GPIO_INTEDGESET_PIN2_Msk 0x00000004UL /*!< Interrupt every edge set for pin 2 */ +#define GPIO_INTEDGESET_PIN3_Msk 0x00000008UL /*!< Interrupt every edge set for pin 3 */ +#define GPIO_INTEDGESET_PIN4_Msk 0x00000010UL /*!< Interrupt every edge set for pin 4 */ +#define GPIO_INTEDGESET_PIN5_Msk 0x00000020UL /*!< Interrupt every edge set for pin 5 */ +#define GPIO_INTEDGESET_PIN6_Msk 0x00000040UL /*!< Interrupt every edge set for pin 6 */ +#define GPIO_INTEDGESET_PIN7_Msk 0x00000080UL /*!< Interrupt every edge set for pin 7 */ +#define GPIO_INTEDGESET_PIN8_Msk 0x00000100UL /*!< Interrupt every edge set for pin 8 */ +#define GPIO_INTEDGESET_PIN9_Msk 0x00000200UL /*!< Interrupt every edge set for pin 9 */ +#define GPIO_INTEDGESET_PIN10_Msk 0x00000400UL /*!< Interrupt every edge set for pin 10 */ +#define GPIO_INTEDGESET_PIN11_Msk 0x00000800UL /*!< Interrupt every edge set for pin 11 */ +#define GPIO_INTEDGESET_PIN12_Msk 0x00001000UL /*!< Interrupt every edge set for pin 12 */ +#define GPIO_INTEDGESET_PIN13_Msk 0x00002000UL /*!< Interrupt every edge set for pin 13 */ +#define GPIO_INTEDGESET_PIN14_Msk 0x00004000UL /*!< Interrupt every edge set for pin 14 */ +#define GPIO_INTEDGESET_PIN15_Msk 0x00008000UL /*!< Interrupt every edge set for pin 15 */ + +/*-- INTEDGECLR: Interrupt every edge clear register ---------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< Interrupt every edge clear for pin 0 */ + uint32_t PIN1 :1; /*!< Interrupt every edge clear for pin 1 */ + uint32_t PIN2 :1; /*!< Interrupt every edge clear for pin 2 */ + uint32_t PIN3 :1; /*!< Interrupt every edge clear for pin 3 */ + uint32_t PIN4 :1; /*!< Interrupt every edge clear for pin 4 */ + uint32_t PIN5 :1; /*!< Interrupt every edge clear for pin 5 */ + uint32_t PIN6 :1; /*!< Interrupt every edge clear for pin 6 */ + uint32_t PIN7 :1; /*!< Interrupt every edge clear for pin 7 */ + uint32_t PIN8 :1; /*!< Interrupt every edge clear for pin 8 */ + uint32_t PIN9 :1; /*!< Interrupt every edge clear for pin 9 */ + uint32_t PIN10 :1; /*!< Interrupt every edge clear for pin 10 */ + uint32_t PIN11 :1; /*!< Interrupt every edge clear for pin 11 */ + uint32_t PIN12 :1; /*!< Interrupt every edge clear for pin 12 */ + uint32_t PIN13 :1; /*!< Interrupt every edge clear for pin 13 */ + uint32_t PIN14 :1; /*!< Interrupt every edge clear for pin 14 */ + uint32_t PIN15 :1; /*!< Interrupt every edge clear for pin 15 */ +} _GPIO_INTEDGECLR_bits; + +/* Bit field positions: */ +#define GPIO_INTEDGECLR_PIN0_Pos 0 /*!< Interrupt every edge clear for pin 0 */ +#define GPIO_INTEDGECLR_PIN1_Pos 1 /*!< Interrupt every edge clear for pin 1 */ +#define GPIO_INTEDGECLR_PIN2_Pos 2 /*!< Interrupt every edge clear for pin 2 */ +#define GPIO_INTEDGECLR_PIN3_Pos 3 /*!< Interrupt every edge clear for pin 3 */ +#define GPIO_INTEDGECLR_PIN4_Pos 4 /*!< Interrupt every edge clear for pin 4 */ +#define GPIO_INTEDGECLR_PIN5_Pos 5 /*!< Interrupt every edge clear for pin 5 */ +#define GPIO_INTEDGECLR_PIN6_Pos 6 /*!< Interrupt every edge clear for pin 6 */ +#define GPIO_INTEDGECLR_PIN7_Pos 7 /*!< Interrupt every edge clear for pin 7 */ +#define GPIO_INTEDGECLR_PIN8_Pos 8 /*!< Interrupt every edge clear for pin 8 */ +#define GPIO_INTEDGECLR_PIN9_Pos 9 /*!< Interrupt every edge clear for pin 9 */ +#define GPIO_INTEDGECLR_PIN10_Pos 10 /*!< Interrupt every edge clear for pin 10 */ +#define GPIO_INTEDGECLR_PIN11_Pos 11 /*!< Interrupt every edge clear for pin 11 */ +#define GPIO_INTEDGECLR_PIN12_Pos 12 /*!< Interrupt every edge clear for pin 12 */ +#define GPIO_INTEDGECLR_PIN13_Pos 13 /*!< Interrupt every edge clear for pin 13 */ +#define GPIO_INTEDGECLR_PIN14_Pos 14 /*!< Interrupt every edge clear for pin 14 */ +#define GPIO_INTEDGECLR_PIN15_Pos 15 /*!< Interrupt every edge clear for pin 15 */ + +/* Bit field masks: */ +#define GPIO_INTEDGECLR_PIN0_Msk 0x00000001UL /*!< Interrupt every edge clear for pin 0 */ +#define GPIO_INTEDGECLR_PIN1_Msk 0x00000002UL /*!< Interrupt every edge clear for pin 1 */ +#define GPIO_INTEDGECLR_PIN2_Msk 0x00000004UL /*!< Interrupt every edge clear for pin 2 */ +#define GPIO_INTEDGECLR_PIN3_Msk 0x00000008UL /*!< Interrupt every edge clear for pin 3 */ +#define GPIO_INTEDGECLR_PIN4_Msk 0x00000010UL /*!< Interrupt every edge clear for pin 4 */ +#define GPIO_INTEDGECLR_PIN5_Msk 0x00000020UL /*!< Interrupt every edge clear for pin 5 */ +#define GPIO_INTEDGECLR_PIN6_Msk 0x00000040UL /*!< Interrupt every edge clear for pin 6 */ +#define GPIO_INTEDGECLR_PIN7_Msk 0x00000080UL /*!< Interrupt every edge clear for pin 7 */ +#define GPIO_INTEDGECLR_PIN8_Msk 0x00000100UL /*!< Interrupt every edge clear for pin 8 */ +#define GPIO_INTEDGECLR_PIN9_Msk 0x00000200UL /*!< Interrupt every edge clear for pin 9 */ +#define GPIO_INTEDGECLR_PIN10_Msk 0x00000400UL /*!< Interrupt every edge clear for pin 10 */ +#define GPIO_INTEDGECLR_PIN11_Msk 0x00000800UL /*!< Interrupt every edge clear for pin 11 */ +#define GPIO_INTEDGECLR_PIN12_Msk 0x00001000UL /*!< Interrupt every edge clear for pin 12 */ +#define GPIO_INTEDGECLR_PIN13_Msk 0x00002000UL /*!< Interrupt every edge clear for pin 13 */ +#define GPIO_INTEDGECLR_PIN14_Msk 0x00004000UL /*!< Interrupt every edge clear for pin 14 */ +#define GPIO_INTEDGECLR_PIN15_Msk 0x00008000UL /*!< Interrupt every edge clear for pin 15 */ + +/*-- INTSTATUS: Interrupt status -----------------------------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< Interrupt status of pin 0 */ + uint32_t PIN1 :1; /*!< Interrupt status of pin 1 */ + uint32_t PIN2 :1; /*!< Interrupt status of pin 2 */ + uint32_t PIN3 :1; /*!< Interrupt status of pin 3 */ + uint32_t PIN4 :1; /*!< Interrupt status of pin 4 */ + uint32_t PIN5 :1; /*!< Interrupt status of pin 5 */ + uint32_t PIN6 :1; /*!< Interrupt status of pin 6 */ + uint32_t PIN7 :1; /*!< Interrupt status of pin 7 */ + uint32_t PIN8 :1; /*!< Interrupt status of pin 8 */ + uint32_t PIN9 :1; /*!< Interrupt status of pin 9 */ + uint32_t PIN10 :1; /*!< Interrupt status of pin 10 */ + uint32_t PIN11 :1; /*!< Interrupt status of pin 11 */ + uint32_t PIN12 :1; /*!< Interrupt status of pin 12 */ + uint32_t PIN13 :1; /*!< Interrupt status of pin 13 */ + uint32_t PIN14 :1; /*!< Interrupt status of pin 14 */ + uint32_t PIN15 :1; /*!< Interrupt status of pin 15 */ +} _GPIO_INTSTATUS_bits; + +/* Bit field positions: */ +#define GPIO_INTSTATUS_PIN0_Pos 0 /*!< Interrupt status of pin 0 */ +#define GPIO_INTSTATUS_PIN1_Pos 1 /*!< Interrupt status of pin 1 */ +#define GPIO_INTSTATUS_PIN2_Pos 2 /*!< Interrupt status of pin 2 */ +#define GPIO_INTSTATUS_PIN3_Pos 3 /*!< Interrupt status of pin 3 */ +#define GPIO_INTSTATUS_PIN4_Pos 4 /*!< Interrupt status of pin 4 */ +#define GPIO_INTSTATUS_PIN5_Pos 5 /*!< Interrupt status of pin 5 */ +#define GPIO_INTSTATUS_PIN6_Pos 6 /*!< Interrupt status of pin 6 */ +#define GPIO_INTSTATUS_PIN7_Pos 7 /*!< Interrupt status of pin 7 */ +#define GPIO_INTSTATUS_PIN8_Pos 8 /*!< Interrupt status of pin 8 */ +#define GPIO_INTSTATUS_PIN9_Pos 9 /*!< Interrupt status of pin 9 */ +#define GPIO_INTSTATUS_PIN10_Pos 10 /*!< Interrupt status of pin 10 */ +#define GPIO_INTSTATUS_PIN11_Pos 11 /*!< Interrupt status of pin 11 */ +#define GPIO_INTSTATUS_PIN12_Pos 12 /*!< Interrupt status of pin 12 */ +#define GPIO_INTSTATUS_PIN13_Pos 13 /*!< Interrupt status of pin 13 */ +#define GPIO_INTSTATUS_PIN14_Pos 14 /*!< Interrupt status of pin 14 */ +#define GPIO_INTSTATUS_PIN15_Pos 15 /*!< Interrupt status of pin 15 */ + +/* Bit field masks: */ +#define GPIO_INTSTATUS_PIN0_Msk 0x00000001UL /*!< Interrupt status of pin 0 */ +#define GPIO_INTSTATUS_PIN1_Msk 0x00000002UL /*!< Interrupt status of pin 1 */ +#define GPIO_INTSTATUS_PIN2_Msk 0x00000004UL /*!< Interrupt status of pin 2 */ +#define GPIO_INTSTATUS_PIN3_Msk 0x00000008UL /*!< Interrupt status of pin 3 */ +#define GPIO_INTSTATUS_PIN4_Msk 0x00000010UL /*!< Interrupt status of pin 4 */ +#define GPIO_INTSTATUS_PIN5_Msk 0x00000020UL /*!< Interrupt status of pin 5 */ +#define GPIO_INTSTATUS_PIN6_Msk 0x00000040UL /*!< Interrupt status of pin 6 */ +#define GPIO_INTSTATUS_PIN7_Msk 0x00000080UL /*!< Interrupt status of pin 7 */ +#define GPIO_INTSTATUS_PIN8_Msk 0x00000100UL /*!< Interrupt status of pin 8 */ +#define GPIO_INTSTATUS_PIN9_Msk 0x00000200UL /*!< Interrupt status of pin 9 */ +#define GPIO_INTSTATUS_PIN10_Msk 0x00000400UL /*!< Interrupt status of pin 10 */ +#define GPIO_INTSTATUS_PIN11_Msk 0x00000800UL /*!< Interrupt status of pin 11 */ +#define GPIO_INTSTATUS_PIN12_Msk 0x00001000UL /*!< Interrupt status of pin 12 */ +#define GPIO_INTSTATUS_PIN13_Msk 0x00002000UL /*!< Interrupt status of pin 13 */ +#define GPIO_INTSTATUS_PIN14_Msk 0x00004000UL /*!< Interrupt status of pin 14 */ +#define GPIO_INTSTATUS_PIN15_Msk 0x00008000UL /*!< Interrupt status of pin 15 */ + +/*-- DMAREQSET: DMA request enable register ------------------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< DMA request enable for pin 0 */ + uint32_t PIN1 :1; /*!< DMA request enable for pin 1 */ + uint32_t PIN2 :1; /*!< DMA request enable for pin 2 */ + uint32_t PIN3 :1; /*!< DMA request enable for pin 3 */ + uint32_t PIN4 :1; /*!< DMA request enable for pin 4 */ + uint32_t PIN5 :1; /*!< DMA request enable for pin 5 */ + uint32_t PIN6 :1; /*!< DMA request enable for pin 6 */ + uint32_t PIN7 :1; /*!< DMA request enable for pin 7 */ + uint32_t PIN8 :1; /*!< DMA request enable for pin 8 */ + uint32_t PIN9 :1; /*!< DMA request enable for pin 9 */ + uint32_t PIN10 :1; /*!< DMA request enable for pin 10 */ + uint32_t PIN11 :1; /*!< DMA request enable for pin 11 */ + uint32_t PIN12 :1; /*!< DMA request enable for pin 12 */ + uint32_t PIN13 :1; /*!< DMA request enable for pin 13 */ + uint32_t PIN14 :1; /*!< DMA request enable for pin 14 */ + uint32_t PIN15 :1; /*!< DMA request enable for pin 15 */ +} _GPIO_DMAREQSET_bits; + +/* Bit field positions: */ +#define GPIO_DMAREQSET_PIN0_Pos 0 /*!< DMA request enable for pin 0 */ +#define GPIO_DMAREQSET_PIN1_Pos 1 /*!< DMA request enable for pin 1 */ +#define GPIO_DMAREQSET_PIN2_Pos 2 /*!< DMA request enable for pin 2 */ +#define GPIO_DMAREQSET_PIN3_Pos 3 /*!< DMA request enable for pin 3 */ +#define GPIO_DMAREQSET_PIN4_Pos 4 /*!< DMA request enable for pin 4 */ +#define GPIO_DMAREQSET_PIN5_Pos 5 /*!< DMA request enable for pin 5 */ +#define GPIO_DMAREQSET_PIN6_Pos 6 /*!< DMA request enable for pin 6 */ +#define GPIO_DMAREQSET_PIN7_Pos 7 /*!< DMA request enable for pin 7 */ +#define GPIO_DMAREQSET_PIN8_Pos 8 /*!< DMA request enable for pin 8 */ +#define GPIO_DMAREQSET_PIN9_Pos 9 /*!< DMA request enable for pin 9 */ +#define GPIO_DMAREQSET_PIN10_Pos 10 /*!< DMA request enable for pin 10 */ +#define GPIO_DMAREQSET_PIN11_Pos 11 /*!< DMA request enable for pin 11 */ +#define GPIO_DMAREQSET_PIN12_Pos 12 /*!< DMA request enable for pin 12 */ +#define GPIO_DMAREQSET_PIN13_Pos 13 /*!< DMA request enable for pin 13 */ +#define GPIO_DMAREQSET_PIN14_Pos 14 /*!< DMA request enable for pin 14 */ +#define GPIO_DMAREQSET_PIN15_Pos 15 /*!< DMA request enable for pin 15 */ + +/* Bit field masks: */ +#define GPIO_DMAREQSET_PIN0_Msk 0x00000001UL /*!< DMA request enable for pin 0 */ +#define GPIO_DMAREQSET_PIN1_Msk 0x00000002UL /*!< DMA request enable for pin 1 */ +#define GPIO_DMAREQSET_PIN2_Msk 0x00000004UL /*!< DMA request enable for pin 2 */ +#define GPIO_DMAREQSET_PIN3_Msk 0x00000008UL /*!< DMA request enable for pin 3 */ +#define GPIO_DMAREQSET_PIN4_Msk 0x00000010UL /*!< DMA request enable for pin 4 */ +#define GPIO_DMAREQSET_PIN5_Msk 0x00000020UL /*!< DMA request enable for pin 5 */ +#define GPIO_DMAREQSET_PIN6_Msk 0x00000040UL /*!< DMA request enable for pin 6 */ +#define GPIO_DMAREQSET_PIN7_Msk 0x00000080UL /*!< DMA request enable for pin 7 */ +#define GPIO_DMAREQSET_PIN8_Msk 0x00000100UL /*!< DMA request enable for pin 8 */ +#define GPIO_DMAREQSET_PIN9_Msk 0x00000200UL /*!< DMA request enable for pin 9 */ +#define GPIO_DMAREQSET_PIN10_Msk 0x00000400UL /*!< DMA request enable for pin 10 */ +#define GPIO_DMAREQSET_PIN11_Msk 0x00000800UL /*!< DMA request enable for pin 11 */ +#define GPIO_DMAREQSET_PIN12_Msk 0x00001000UL /*!< DMA request enable for pin 12 */ +#define GPIO_DMAREQSET_PIN13_Msk 0x00002000UL /*!< DMA request enable for pin 13 */ +#define GPIO_DMAREQSET_PIN14_Msk 0x00004000UL /*!< DMA request enable for pin 14 */ +#define GPIO_DMAREQSET_PIN15_Msk 0x00008000UL /*!< DMA request enable for pin 15 */ + +/*-- DMAREQCLR: DMA request disable register -----------------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< DMA request disable for pin 0 */ + uint32_t PIN1 :1; /*!< DMA request disable for pin 1 */ + uint32_t PIN2 :1; /*!< DMA request disable for pin 2 */ + uint32_t PIN3 :1; /*!< DMA request disable for pin 3 */ + uint32_t PIN4 :1; /*!< DMA request disable for pin 4 */ + uint32_t PIN5 :1; /*!< DMA request disable for pin 5 */ + uint32_t PIN6 :1; /*!< DMA request disable for pin 6 */ + uint32_t PIN7 :1; /*!< DMA request disable for pin 7 */ + uint32_t PIN8 :1; /*!< DMA request disable for pin 8 */ + uint32_t PIN9 :1; /*!< DMA request disable for pin 9 */ + uint32_t PIN10 :1; /*!< DMA request disable for pin 10 */ + uint32_t PIN11 :1; /*!< DMA request disable for pin 11 */ + uint32_t PIN12 :1; /*!< DMA request disable for pin 12 */ + uint32_t PIN13 :1; /*!< DMA request disable for pin 13 */ + uint32_t PIN14 :1; /*!< DMA request disable for pin 14 */ + uint32_t PIN15 :1; /*!< DMA request disable for pin 15 */ +} _GPIO_DMAREQCLR_bits; + +/* Bit field positions: */ +#define GPIO_DMAREQCLR_PIN0_Pos 0 /*!< DMA request disable for pin 0 */ +#define GPIO_DMAREQCLR_PIN1_Pos 1 /*!< DMA request disable for pin 1 */ +#define GPIO_DMAREQCLR_PIN2_Pos 2 /*!< DMA request disable for pin 2 */ +#define GPIO_DMAREQCLR_PIN3_Pos 3 /*!< DMA request disable for pin 3 */ +#define GPIO_DMAREQCLR_PIN4_Pos 4 /*!< DMA request disable for pin 4 */ +#define GPIO_DMAREQCLR_PIN5_Pos 5 /*!< DMA request disable for pin 5 */ +#define GPIO_DMAREQCLR_PIN6_Pos 6 /*!< DMA request disable for pin 6 */ +#define GPIO_DMAREQCLR_PIN7_Pos 7 /*!< DMA request disable for pin 7 */ +#define GPIO_DMAREQCLR_PIN8_Pos 8 /*!< DMA request disable for pin 8 */ +#define GPIO_DMAREQCLR_PIN9_Pos 9 /*!< DMA request disable for pin 9 */ +#define GPIO_DMAREQCLR_PIN10_Pos 10 /*!< DMA request disable for pin 10 */ +#define GPIO_DMAREQCLR_PIN11_Pos 11 /*!< DMA request disable for pin 11 */ +#define GPIO_DMAREQCLR_PIN12_Pos 12 /*!< DMA request disable for pin 12 */ +#define GPIO_DMAREQCLR_PIN13_Pos 13 /*!< DMA request disable for pin 13 */ +#define GPIO_DMAREQCLR_PIN14_Pos 14 /*!< DMA request disable for pin 14 */ +#define GPIO_DMAREQCLR_PIN15_Pos 15 /*!< DMA request disable for pin 15 */ + +/* Bit field masks: */ +#define GPIO_DMAREQCLR_PIN0_Msk 0x00000001UL /*!< DMA request disable for pin 0 */ +#define GPIO_DMAREQCLR_PIN1_Msk 0x00000002UL /*!< DMA request disable for pin 1 */ +#define GPIO_DMAREQCLR_PIN2_Msk 0x00000004UL /*!< DMA request disable for pin 2 */ +#define GPIO_DMAREQCLR_PIN3_Msk 0x00000008UL /*!< DMA request disable for pin 3 */ +#define GPIO_DMAREQCLR_PIN4_Msk 0x00000010UL /*!< DMA request disable for pin 4 */ +#define GPIO_DMAREQCLR_PIN5_Msk 0x00000020UL /*!< DMA request disable for pin 5 */ +#define GPIO_DMAREQCLR_PIN6_Msk 0x00000040UL /*!< DMA request disable for pin 6 */ +#define GPIO_DMAREQCLR_PIN7_Msk 0x00000080UL /*!< DMA request disable for pin 7 */ +#define GPIO_DMAREQCLR_PIN8_Msk 0x00000100UL /*!< DMA request disable for pin 8 */ +#define GPIO_DMAREQCLR_PIN9_Msk 0x00000200UL /*!< DMA request disable for pin 9 */ +#define GPIO_DMAREQCLR_PIN10_Msk 0x00000400UL /*!< DMA request disable for pin 10 */ +#define GPIO_DMAREQCLR_PIN11_Msk 0x00000800UL /*!< DMA request disable for pin 11 */ +#define GPIO_DMAREQCLR_PIN12_Msk 0x00001000UL /*!< DMA request disable for pin 12 */ +#define GPIO_DMAREQCLR_PIN13_Msk 0x00002000UL /*!< DMA request disable for pin 13 */ +#define GPIO_DMAREQCLR_PIN14_Msk 0x00004000UL /*!< DMA request disable for pin 14 */ +#define GPIO_DMAREQCLR_PIN15_Msk 0x00008000UL /*!< DMA request disable for pin 15 */ + +/*-- ADCSOCSET: ADC Start Of Conversion enable register ------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< ADC SOC enable for pin 0 */ + uint32_t PIN1 :1; /*!< ADC SOC enable for pin 1 */ + uint32_t PIN2 :1; /*!< ADC SOC enable for pin 2 */ + uint32_t PIN3 :1; /*!< ADC SOC enable for pin 3 */ + uint32_t PIN4 :1; /*!< ADC SOC enable for pin 4 */ + uint32_t PIN5 :1; /*!< ADC SOC enable for pin 5 */ + uint32_t PIN6 :1; /*!< ADC SOC enable for pin 6 */ + uint32_t PIN7 :1; /*!< ADC SOC enable for pin 7 */ + uint32_t PIN8 :1; /*!< ADC SOC enable for pin 8 */ + uint32_t PIN9 :1; /*!< ADC SOC enable for pin 9 */ + uint32_t PIN10 :1; /*!< ADC SOC enable for pin 10 */ + uint32_t PIN11 :1; /*!< ADC SOC enable for pin 11 */ + uint32_t PIN12 :1; /*!< ADC SOC enable for pin 12 */ + uint32_t PIN13 :1; /*!< ADC SOC enable for pin 13 */ + uint32_t PIN14 :1; /*!< ADC SOC enable for pin 14 */ + uint32_t PIN15 :1; /*!< ADC SOC enable for pin 15 */ +} _GPIO_ADCSOCSET_bits; + +/* Bit field positions: */ +#define GPIO_ADCSOCSET_PIN0_Pos 0 /*!< ADC SOC enable for pin 0 */ +#define GPIO_ADCSOCSET_PIN1_Pos 1 /*!< ADC SOC enable for pin 1 */ +#define GPIO_ADCSOCSET_PIN2_Pos 2 /*!< ADC SOC enable for pin 2 */ +#define GPIO_ADCSOCSET_PIN3_Pos 3 /*!< ADC SOC enable for pin 3 */ +#define GPIO_ADCSOCSET_PIN4_Pos 4 /*!< ADC SOC enable for pin 4 */ +#define GPIO_ADCSOCSET_PIN5_Pos 5 /*!< ADC SOC enable for pin 5 */ +#define GPIO_ADCSOCSET_PIN6_Pos 6 /*!< ADC SOC enable for pin 6 */ +#define GPIO_ADCSOCSET_PIN7_Pos 7 /*!< ADC SOC enable for pin 7 */ +#define GPIO_ADCSOCSET_PIN8_Pos 8 /*!< ADC SOC enable for pin 8 */ +#define GPIO_ADCSOCSET_PIN9_Pos 9 /*!< ADC SOC enable for pin 9 */ +#define GPIO_ADCSOCSET_PIN10_Pos 10 /*!< ADC SOC enable for pin 10 */ +#define GPIO_ADCSOCSET_PIN11_Pos 11 /*!< ADC SOC enable for pin 11 */ +#define GPIO_ADCSOCSET_PIN12_Pos 12 /*!< ADC SOC enable for pin 12 */ +#define GPIO_ADCSOCSET_PIN13_Pos 13 /*!< ADC SOC enable for pin 13 */ +#define GPIO_ADCSOCSET_PIN14_Pos 14 /*!< ADC SOC enable for pin 14 */ +#define GPIO_ADCSOCSET_PIN15_Pos 15 /*!< ADC SOC enable for pin 15 */ + +/* Bit field masks: */ +#define GPIO_ADCSOCSET_PIN0_Msk 0x00000001UL /*!< ADC SOC enable for pin 0 */ +#define GPIO_ADCSOCSET_PIN1_Msk 0x00000002UL /*!< ADC SOC enable for pin 1 */ +#define GPIO_ADCSOCSET_PIN2_Msk 0x00000004UL /*!< ADC SOC enable for pin 2 */ +#define GPIO_ADCSOCSET_PIN3_Msk 0x00000008UL /*!< ADC SOC enable for pin 3 */ +#define GPIO_ADCSOCSET_PIN4_Msk 0x00000010UL /*!< ADC SOC enable for pin 4 */ +#define GPIO_ADCSOCSET_PIN5_Msk 0x00000020UL /*!< ADC SOC enable for pin 5 */ +#define GPIO_ADCSOCSET_PIN6_Msk 0x00000040UL /*!< ADC SOC enable for pin 6 */ +#define GPIO_ADCSOCSET_PIN7_Msk 0x00000080UL /*!< ADC SOC enable for pin 7 */ +#define GPIO_ADCSOCSET_PIN8_Msk 0x00000100UL /*!< ADC SOC enable for pin 8 */ +#define GPIO_ADCSOCSET_PIN9_Msk 0x00000200UL /*!< ADC SOC enable for pin 9 */ +#define GPIO_ADCSOCSET_PIN10_Msk 0x00000400UL /*!< ADC SOC enable for pin 10 */ +#define GPIO_ADCSOCSET_PIN11_Msk 0x00000800UL /*!< ADC SOC enable for pin 11 */ +#define GPIO_ADCSOCSET_PIN12_Msk 0x00001000UL /*!< ADC SOC enable for pin 12 */ +#define GPIO_ADCSOCSET_PIN13_Msk 0x00002000UL /*!< ADC SOC enable for pin 13 */ +#define GPIO_ADCSOCSET_PIN14_Msk 0x00004000UL /*!< ADC SOC enable for pin 14 */ +#define GPIO_ADCSOCSET_PIN15_Msk 0x00008000UL /*!< ADC SOC enable for pin 15 */ + +/*-- ADCSOCCLR: ADC Start Of Conversion disable register -----------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< ADC SOC disable for pin 0 */ + uint32_t PIN1 :1; /*!< ADC SOC disable for pin 1 */ + uint32_t PIN2 :1; /*!< ADC SOC disable for pin 2 */ + uint32_t PIN3 :1; /*!< ADC SOC disable for pin 3 */ + uint32_t PIN4 :1; /*!< ADC SOC disable for pin 4 */ + uint32_t PIN5 :1; /*!< ADC SOC disable for pin 5 */ + uint32_t PIN6 :1; /*!< ADC SOC disable for pin 6 */ + uint32_t PIN7 :1; /*!< ADC SOC disable for pin 7 */ + uint32_t PIN8 :1; /*!< ADC SOC disable for pin 8 */ + uint32_t PIN9 :1; /*!< ADC SOC disable for pin 9 */ + uint32_t PIN10 :1; /*!< ADC SOC disable for pin 10 */ + uint32_t PIN11 :1; /*!< ADC SOC disable for pin 11 */ + uint32_t PIN12 :1; /*!< ADC SOC disable for pin 12 */ + uint32_t PIN13 :1; /*!< ADC SOC disable for pin 13 */ + uint32_t PIN14 :1; /*!< ADC SOC disable for pin 14 */ + uint32_t PIN15 :1; /*!< ADC SOC disable for pin 15 */ +} _GPIO_ADCSOCCLR_bits; + +/* Bit field positions: */ +#define GPIO_ADCSOCCLR_PIN0_Pos 0 /*!< ADC SOC disable for pin 0 */ +#define GPIO_ADCSOCCLR_PIN1_Pos 1 /*!< ADC SOC disable for pin 1 */ +#define GPIO_ADCSOCCLR_PIN2_Pos 2 /*!< ADC SOC disable for pin 2 */ +#define GPIO_ADCSOCCLR_PIN3_Pos 3 /*!< ADC SOC disable for pin 3 */ +#define GPIO_ADCSOCCLR_PIN4_Pos 4 /*!< ADC SOC disable for pin 4 */ +#define GPIO_ADCSOCCLR_PIN5_Pos 5 /*!< ADC SOC disable for pin 5 */ +#define GPIO_ADCSOCCLR_PIN6_Pos 6 /*!< ADC SOC disable for pin 6 */ +#define GPIO_ADCSOCCLR_PIN7_Pos 7 /*!< ADC SOC disable for pin 7 */ +#define GPIO_ADCSOCCLR_PIN8_Pos 8 /*!< ADC SOC disable for pin 8 */ +#define GPIO_ADCSOCCLR_PIN9_Pos 9 /*!< ADC SOC disable for pin 9 */ +#define GPIO_ADCSOCCLR_PIN10_Pos 10 /*!< ADC SOC disable for pin 10 */ +#define GPIO_ADCSOCCLR_PIN11_Pos 11 /*!< ADC SOC disable for pin 11 */ +#define GPIO_ADCSOCCLR_PIN12_Pos 12 /*!< ADC SOC disable for pin 12 */ +#define GPIO_ADCSOCCLR_PIN13_Pos 13 /*!< ADC SOC disable for pin 13 */ +#define GPIO_ADCSOCCLR_PIN14_Pos 14 /*!< ADC SOC disable for pin 14 */ +#define GPIO_ADCSOCCLR_PIN15_Pos 15 /*!< ADC SOC disable for pin 15 */ + +/* Bit field masks: */ +#define GPIO_ADCSOCCLR_PIN0_Msk 0x00000001UL /*!< ADC SOC disable for pin 0 */ +#define GPIO_ADCSOCCLR_PIN1_Msk 0x00000002UL /*!< ADC SOC disable for pin 1 */ +#define GPIO_ADCSOCCLR_PIN2_Msk 0x00000004UL /*!< ADC SOC disable for pin 2 */ +#define GPIO_ADCSOCCLR_PIN3_Msk 0x00000008UL /*!< ADC SOC disable for pin 3 */ +#define GPIO_ADCSOCCLR_PIN4_Msk 0x00000010UL /*!< ADC SOC disable for pin 4 */ +#define GPIO_ADCSOCCLR_PIN5_Msk 0x00000020UL /*!< ADC SOC disable for pin 5 */ +#define GPIO_ADCSOCCLR_PIN6_Msk 0x00000040UL /*!< ADC SOC disable for pin 6 */ +#define GPIO_ADCSOCCLR_PIN7_Msk 0x00000080UL /*!< ADC SOC disable for pin 7 */ +#define GPIO_ADCSOCCLR_PIN8_Msk 0x00000100UL /*!< ADC SOC disable for pin 8 */ +#define GPIO_ADCSOCCLR_PIN9_Msk 0x00000200UL /*!< ADC SOC disable for pin 9 */ +#define GPIO_ADCSOCCLR_PIN10_Msk 0x00000400UL /*!< ADC SOC disable for pin 10 */ +#define GPIO_ADCSOCCLR_PIN11_Msk 0x00000800UL /*!< ADC SOC disable for pin 11 */ +#define GPIO_ADCSOCCLR_PIN12_Msk 0x00001000UL /*!< ADC SOC disable for pin 12 */ +#define GPIO_ADCSOCCLR_PIN13_Msk 0x00002000UL /*!< ADC SOC disable for pin 13 */ +#define GPIO_ADCSOCCLR_PIN14_Msk 0x00004000UL /*!< ADC SOC disable for pin 14 */ +#define GPIO_ADCSOCCLR_PIN15_Msk 0x00008000UL /*!< ADC SOC disable for pin 15 */ + +/*-- RXEVSET: Core RXEV request enable register --------------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< RXEV enable for pin 0 */ + uint32_t PIN1 :1; /*!< RXEV enable for pin 1 */ + uint32_t PIN2 :1; /*!< RXEV enable for pin 2 */ + uint32_t PIN3 :1; /*!< RXEV enable for pin 3 */ + uint32_t PIN4 :1; /*!< RXEV enable for pin 4 */ + uint32_t PIN5 :1; /*!< RXEV enable for pin 5 */ + uint32_t PIN6 :1; /*!< RXEV enable for pin 6 */ + uint32_t PIN7 :1; /*!< RXEV enable for pin 7 */ + uint32_t PIN8 :1; /*!< RXEV enable for pin 8 */ + uint32_t PIN9 :1; /*!< RXEV enable for pin 9 */ + uint32_t PIN10 :1; /*!< RXEV enable for pin 10 */ + uint32_t PIN11 :1; /*!< RXEV enable for pin 11 */ + uint32_t PIN12 :1; /*!< RXEV enable for pin 12 */ + uint32_t PIN13 :1; /*!< RXEV enable for pin 13 */ + uint32_t PIN14 :1; /*!< RXEV enable for pin 14 */ + uint32_t PIN15 :1; /*!< RXEV enable for pin 15 */ +} _GPIO_RXEVSET_bits; + +/* Bit field positions: */ +#define GPIO_RXEVSET_PIN0_Pos 0 /*!< RXEV enable for pin 0 */ +#define GPIO_RXEVSET_PIN1_Pos 1 /*!< RXEV enable for pin 1 */ +#define GPIO_RXEVSET_PIN2_Pos 2 /*!< RXEV enable for pin 2 */ +#define GPIO_RXEVSET_PIN3_Pos 3 /*!< RXEV enable for pin 3 */ +#define GPIO_RXEVSET_PIN4_Pos 4 /*!< RXEV enable for pin 4 */ +#define GPIO_RXEVSET_PIN5_Pos 5 /*!< RXEV enable for pin 5 */ +#define GPIO_RXEVSET_PIN6_Pos 6 /*!< RXEV enable for pin 6 */ +#define GPIO_RXEVSET_PIN7_Pos 7 /*!< RXEV enable for pin 7 */ +#define GPIO_RXEVSET_PIN8_Pos 8 /*!< RXEV enable for pin 8 */ +#define GPIO_RXEVSET_PIN9_Pos 9 /*!< RXEV enable for pin 9 */ +#define GPIO_RXEVSET_PIN10_Pos 10 /*!< RXEV enable for pin 10 */ +#define GPIO_RXEVSET_PIN11_Pos 11 /*!< RXEV enable for pin 11 */ +#define GPIO_RXEVSET_PIN12_Pos 12 /*!< RXEV enable for pin 12 */ +#define GPIO_RXEVSET_PIN13_Pos 13 /*!< RXEV enable for pin 13 */ +#define GPIO_RXEVSET_PIN14_Pos 14 /*!< RXEV enable for pin 14 */ +#define GPIO_RXEVSET_PIN15_Pos 15 /*!< RXEV enable for pin 15 */ + +/* Bit field masks: */ +#define GPIO_RXEVSET_PIN0_Msk 0x00000001UL /*!< RXEV enable for pin 0 */ +#define GPIO_RXEVSET_PIN1_Msk 0x00000002UL /*!< RXEV enable for pin 1 */ +#define GPIO_RXEVSET_PIN2_Msk 0x00000004UL /*!< RXEV enable for pin 2 */ +#define GPIO_RXEVSET_PIN3_Msk 0x00000008UL /*!< RXEV enable for pin 3 */ +#define GPIO_RXEVSET_PIN4_Msk 0x00000010UL /*!< RXEV enable for pin 4 */ +#define GPIO_RXEVSET_PIN5_Msk 0x00000020UL /*!< RXEV enable for pin 5 */ +#define GPIO_RXEVSET_PIN6_Msk 0x00000040UL /*!< RXEV enable for pin 6 */ +#define GPIO_RXEVSET_PIN7_Msk 0x00000080UL /*!< RXEV enable for pin 7 */ +#define GPIO_RXEVSET_PIN8_Msk 0x00000100UL /*!< RXEV enable for pin 8 */ +#define GPIO_RXEVSET_PIN9_Msk 0x00000200UL /*!< RXEV enable for pin 9 */ +#define GPIO_RXEVSET_PIN10_Msk 0x00000400UL /*!< RXEV enable for pin 10 */ +#define GPIO_RXEVSET_PIN11_Msk 0x00000800UL /*!< RXEV enable for pin 11 */ +#define GPIO_RXEVSET_PIN12_Msk 0x00001000UL /*!< RXEV enable for pin 12 */ +#define GPIO_RXEVSET_PIN13_Msk 0x00002000UL /*!< RXEV enable for pin 13 */ +#define GPIO_RXEVSET_PIN14_Msk 0x00004000UL /*!< RXEV enable for pin 14 */ +#define GPIO_RXEVSET_PIN15_Msk 0x00008000UL /*!< RXEV enable for pin 15 */ + +/*-- RXEVCLR: Core RXEV request disable register -------------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< RXEV disable for pin 0 */ + uint32_t PIN1 :1; /*!< RXEV disable for pin 1 */ + uint32_t PIN2 :1; /*!< RXEV disable for pin 2 */ + uint32_t PIN3 :1; /*!< RXEV disable for pin 3 */ + uint32_t PIN4 :1; /*!< RXEV disable for pin 4 */ + uint32_t PIN5 :1; /*!< RXEV disable for pin 5 */ + uint32_t PIN6 :1; /*!< RXEV disable for pin 6 */ + uint32_t PIN7 :1; /*!< RXEV disable for pin 7 */ + uint32_t PIN8 :1; /*!< RXEV disable for pin 8 */ + uint32_t PIN9 :1; /*!< RXEV disable for pin 9 */ + uint32_t PIN10 :1; /*!< RXEV disable for pin 10 */ + uint32_t PIN11 :1; /*!< RXEV disable for pin 11 */ + uint32_t PIN12 :1; /*!< RXEV disable for pin 12 */ + uint32_t PIN13 :1; /*!< RXEV disable for pin 13 */ + uint32_t PIN14 :1; /*!< RXEV disable for pin 14 */ + uint32_t PIN15 :1; /*!< RXEV disable for pin 15 */ +} _GPIO_RXEVCLR_bits; + +/* Bit field positions: */ +#define GPIO_RXEVCLR_PIN0_Pos 0 /*!< RXEV disable for pin 0 */ +#define GPIO_RXEVCLR_PIN1_Pos 1 /*!< RXEV disable for pin 1 */ +#define GPIO_RXEVCLR_PIN2_Pos 2 /*!< RXEV disable for pin 2 */ +#define GPIO_RXEVCLR_PIN3_Pos 3 /*!< RXEV disable for pin 3 */ +#define GPIO_RXEVCLR_PIN4_Pos 4 /*!< RXEV disable for pin 4 */ +#define GPIO_RXEVCLR_PIN5_Pos 5 /*!< RXEV disable for pin 5 */ +#define GPIO_RXEVCLR_PIN6_Pos 6 /*!< RXEV disable for pin 6 */ +#define GPIO_RXEVCLR_PIN7_Pos 7 /*!< RXEV disable for pin 7 */ +#define GPIO_RXEVCLR_PIN8_Pos 8 /*!< RXEV disable for pin 8 */ +#define GPIO_RXEVCLR_PIN9_Pos 9 /*!< RXEV disable for pin 9 */ +#define GPIO_RXEVCLR_PIN10_Pos 10 /*!< RXEV disable for pin 10 */ +#define GPIO_RXEVCLR_PIN11_Pos 11 /*!< RXEV disable for pin 11 */ +#define GPIO_RXEVCLR_PIN12_Pos 12 /*!< RXEV disable for pin 12 */ +#define GPIO_RXEVCLR_PIN13_Pos 13 /*!< RXEV disable for pin 13 */ +#define GPIO_RXEVCLR_PIN14_Pos 14 /*!< RXEV disable for pin 14 */ +#define GPIO_RXEVCLR_PIN15_Pos 15 /*!< RXEV disable for pin 15 */ + +/* Bit field masks: */ +#define GPIO_RXEVCLR_PIN0_Msk 0x00000001UL /*!< RXEV disable for pin 0 */ +#define GPIO_RXEVCLR_PIN1_Msk 0x00000002UL /*!< RXEV disable for pin 1 */ +#define GPIO_RXEVCLR_PIN2_Msk 0x00000004UL /*!< RXEV disable for pin 2 */ +#define GPIO_RXEVCLR_PIN3_Msk 0x00000008UL /*!< RXEV disable for pin 3 */ +#define GPIO_RXEVCLR_PIN4_Msk 0x00000010UL /*!< RXEV disable for pin 4 */ +#define GPIO_RXEVCLR_PIN5_Msk 0x00000020UL /*!< RXEV disable for pin 5 */ +#define GPIO_RXEVCLR_PIN6_Msk 0x00000040UL /*!< RXEV disable for pin 6 */ +#define GPIO_RXEVCLR_PIN7_Msk 0x00000080UL /*!< RXEV disable for pin 7 */ +#define GPIO_RXEVCLR_PIN8_Msk 0x00000100UL /*!< RXEV disable for pin 8 */ +#define GPIO_RXEVCLR_PIN9_Msk 0x00000200UL /*!< RXEV disable for pin 9 */ +#define GPIO_RXEVCLR_PIN10_Msk 0x00000400UL /*!< RXEV disable for pin 10 */ +#define GPIO_RXEVCLR_PIN11_Msk 0x00000800UL /*!< RXEV disable for pin 11 */ +#define GPIO_RXEVCLR_PIN12_Msk 0x00001000UL /*!< RXEV disable for pin 12 */ +#define GPIO_RXEVCLR_PIN13_Msk 0x00002000UL /*!< RXEV disable for pin 13 */ +#define GPIO_RXEVCLR_PIN14_Msk 0x00004000UL /*!< RXEV disable for pin 14 */ +#define GPIO_RXEVCLR_PIN15_Msk 0x00008000UL /*!< RXEV disable for pin 15 */ + +/*-- LOCKKEY: Key register to unlock LOCKSET/LOCKCLR registers for write (KEY=0xADEADBEE) ---------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< Key to unlock LOCKSET/LOCKCLR registers for write (KEY=0xADEADBEE) */ +} _GPIO_LOCKKEY_bits; + +/* Bit field positions: */ +#define GPIO_LOCKKEY_VAL_Pos 0 /*!< Key to unlock LOCKSET/LOCKCLR registers for write (KEY=0xADEADBEE) */ + +/* Bit field masks: */ +#define GPIO_LOCKKEY_VAL_Msk 0xFFFFFFFFUL /*!< Key to unlock LOCKSET/LOCKCLR registers for write (KEY=0xADEADBEE) */ + +/* Bit field enums: */ +typedef enum { + GPIO_LOCKKEY_VAL_LOCK = -286331154, /*!< 0xEEEEEEEE, 0xEEEEEEEE, key to lock registers */ + GPIO_LOCKKEY_VAL_UNLOCK = -1377117202, /*!< 0xADEADBEE, 0xADEADBEE, key to unlock registers */ +} GPIO_LOCKKEY_VAL_Enum; + +/*-- LOCKSTAT: LOCKSET/LOCKCLR write enable status register --------------------------------------------------*/ +typedef struct { + uint32_t WREN :1; /*!< LOCKSET/LOCKCLR write enable status */ +} _GPIO_LOCKSTAT_bits; + +/* Bit field positions: */ +#define GPIO_LOCKSTAT_WREN_Pos 0 /*!< LOCKSET/LOCKCLR write enable status */ + +/* Bit field masks: */ +#define GPIO_LOCKSTAT_WREN_Msk 0x00000001UL /*!< LOCKSET/LOCKCLR write enable status */ + +/*-- LOCKSET: Lock pins configuration enable register --------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< Lock configuration enable for pin 0 */ + uint32_t PIN1 :1; /*!< Lock configuration enable for pin 1 */ + uint32_t PIN2 :1; /*!< Lock configuration enable for pin 2 */ + uint32_t PIN3 :1; /*!< Lock configuration enable for pin 3 */ + uint32_t PIN4 :1; /*!< Lock configuration enable for pin 4 */ + uint32_t PIN5 :1; /*!< Lock configuration enable for pin 5 */ + uint32_t PIN6 :1; /*!< Lock configuration enable for pin 6 */ + uint32_t PIN7 :1; /*!< Lock configuration enable for pin 7 */ + uint32_t PIN8 :1; /*!< Lock configuration enable for pin 8 */ + uint32_t PIN9 :1; /*!< Lock configuration enable for pin 9 */ + uint32_t PIN10 :1; /*!< Lock configuration enable for pin 10 */ + uint32_t PIN11 :1; /*!< Lock configuration enable for pin 11 */ + uint32_t PIN12 :1; /*!< Lock configuration enable for pin 12 */ + uint32_t PIN13 :1; /*!< Lock configuration enable for pin 13 */ + uint32_t PIN14 :1; /*!< Lock configuration enable for pin 14 */ + uint32_t PIN15 :1; /*!< Lock configuration enable for pin 15 */ +} _GPIO_LOCKSET_bits; + +/* Bit field positions: */ +#define GPIO_LOCKSET_PIN0_Pos 0 /*!< Lock configuration enable for pin 0 */ +#define GPIO_LOCKSET_PIN1_Pos 1 /*!< Lock configuration enable for pin 1 */ +#define GPIO_LOCKSET_PIN2_Pos 2 /*!< Lock configuration enable for pin 2 */ +#define GPIO_LOCKSET_PIN3_Pos 3 /*!< Lock configuration enable for pin 3 */ +#define GPIO_LOCKSET_PIN4_Pos 4 /*!< Lock configuration enable for pin 4 */ +#define GPIO_LOCKSET_PIN5_Pos 5 /*!< Lock configuration enable for pin 5 */ +#define GPIO_LOCKSET_PIN6_Pos 6 /*!< Lock configuration enable for pin 6 */ +#define GPIO_LOCKSET_PIN7_Pos 7 /*!< Lock configuration enable for pin 7 */ +#define GPIO_LOCKSET_PIN8_Pos 8 /*!< Lock configuration enable for pin 8 */ +#define GPIO_LOCKSET_PIN9_Pos 9 /*!< Lock configuration enable for pin 9 */ +#define GPIO_LOCKSET_PIN10_Pos 10 /*!< Lock configuration enable for pin 10 */ +#define GPIO_LOCKSET_PIN11_Pos 11 /*!< Lock configuration enable for pin 11 */ +#define GPIO_LOCKSET_PIN12_Pos 12 /*!< Lock configuration enable for pin 12 */ +#define GPIO_LOCKSET_PIN13_Pos 13 /*!< Lock configuration enable for pin 13 */ +#define GPIO_LOCKSET_PIN14_Pos 14 /*!< Lock configuration enable for pin 14 */ +#define GPIO_LOCKSET_PIN15_Pos 15 /*!< Lock configuration enable for pin 15 */ + +/* Bit field masks: */ +#define GPIO_LOCKSET_PIN0_Msk 0x00000001UL /*!< Lock configuration enable for pin 0 */ +#define GPIO_LOCKSET_PIN1_Msk 0x00000002UL /*!< Lock configuration enable for pin 1 */ +#define GPIO_LOCKSET_PIN2_Msk 0x00000004UL /*!< Lock configuration enable for pin 2 */ +#define GPIO_LOCKSET_PIN3_Msk 0x00000008UL /*!< Lock configuration enable for pin 3 */ +#define GPIO_LOCKSET_PIN4_Msk 0x00000010UL /*!< Lock configuration enable for pin 4 */ +#define GPIO_LOCKSET_PIN5_Msk 0x00000020UL /*!< Lock configuration enable for pin 5 */ +#define GPIO_LOCKSET_PIN6_Msk 0x00000040UL /*!< Lock configuration enable for pin 6 */ +#define GPIO_LOCKSET_PIN7_Msk 0x00000080UL /*!< Lock configuration enable for pin 7 */ +#define GPIO_LOCKSET_PIN8_Msk 0x00000100UL /*!< Lock configuration enable for pin 8 */ +#define GPIO_LOCKSET_PIN9_Msk 0x00000200UL /*!< Lock configuration enable for pin 9 */ +#define GPIO_LOCKSET_PIN10_Msk 0x00000400UL /*!< Lock configuration enable for pin 10 */ +#define GPIO_LOCKSET_PIN11_Msk 0x00000800UL /*!< Lock configuration enable for pin 11 */ +#define GPIO_LOCKSET_PIN12_Msk 0x00001000UL /*!< Lock configuration enable for pin 12 */ +#define GPIO_LOCKSET_PIN13_Msk 0x00002000UL /*!< Lock configuration enable for pin 13 */ +#define GPIO_LOCKSET_PIN14_Msk 0x00004000UL /*!< Lock configuration enable for pin 14 */ +#define GPIO_LOCKSET_PIN15_Msk 0x00008000UL /*!< Lock configuration enable for pin 15 */ + +/*-- LOCKCLR: Lock pins configuration disable register -------------------------------------------------------*/ +typedef struct { + uint32_t PIN0 :1; /*!< Lock configuration disable for pin 0 */ + uint32_t PIN1 :1; /*!< Lock configuration disable for pin 1 */ + uint32_t PIN2 :1; /*!< Lock configuration disable for pin 2 */ + uint32_t PIN3 :1; /*!< Lock configuration disable for pin 3 */ + uint32_t PIN4 :1; /*!< Lock configuration disable for pin 4 */ + uint32_t PIN5 :1; /*!< Lock configuration disable for pin 5 */ + uint32_t PIN6 :1; /*!< Lock configuration disable for pin 6 */ + uint32_t PIN7 :1; /*!< Lock configuration disable for pin 7 */ + uint32_t PIN8 :1; /*!< Lock configuration disable for pin 8 */ + uint32_t PIN9 :1; /*!< Lock configuration disable for pin 9 */ + uint32_t PIN10 :1; /*!< Lock configuration disable for pin 10 */ + uint32_t PIN11 :1; /*!< Lock configuration disable for pin 11 */ + uint32_t PIN12 :1; /*!< Lock configuration disable for pin 12 */ + uint32_t PIN13 :1; /*!< Lock configuration disable for pin 13 */ + uint32_t PIN14 :1; /*!< Lock configuration disable for pin 14 */ + uint32_t PIN15 :1; /*!< Lock configuration disable for pin 15 */ +} _GPIO_LOCKCLR_bits; + +/* Bit field positions: */ +#define GPIO_LOCKCLR_PIN0_Pos 0 /*!< Lock configuration disable for pin 0 */ +#define GPIO_LOCKCLR_PIN1_Pos 1 /*!< Lock configuration disable for pin 1 */ +#define GPIO_LOCKCLR_PIN2_Pos 2 /*!< Lock configuration disable for pin 2 */ +#define GPIO_LOCKCLR_PIN3_Pos 3 /*!< Lock configuration disable for pin 3 */ +#define GPIO_LOCKCLR_PIN4_Pos 4 /*!< Lock configuration disable for pin 4 */ +#define GPIO_LOCKCLR_PIN5_Pos 5 /*!< Lock configuration disable for pin 5 */ +#define GPIO_LOCKCLR_PIN6_Pos 6 /*!< Lock configuration disable for pin 6 */ +#define GPIO_LOCKCLR_PIN7_Pos 7 /*!< Lock configuration disable for pin 7 */ +#define GPIO_LOCKCLR_PIN8_Pos 8 /*!< Lock configuration disable for pin 8 */ +#define GPIO_LOCKCLR_PIN9_Pos 9 /*!< Lock configuration disable for pin 9 */ +#define GPIO_LOCKCLR_PIN10_Pos 10 /*!< Lock configuration disable for pin 10 */ +#define GPIO_LOCKCLR_PIN11_Pos 11 /*!< Lock configuration disable for pin 11 */ +#define GPIO_LOCKCLR_PIN12_Pos 12 /*!< Lock configuration disable for pin 12 */ +#define GPIO_LOCKCLR_PIN13_Pos 13 /*!< Lock configuration disable for pin 13 */ +#define GPIO_LOCKCLR_PIN14_Pos 14 /*!< Lock configuration disable for pin 14 */ +#define GPIO_LOCKCLR_PIN15_Pos 15 /*!< Lock configuration disable for pin 15 */ + +/* Bit field masks: */ +#define GPIO_LOCKCLR_PIN0_Msk 0x00000001UL /*!< Lock configuration disable for pin 0 */ +#define GPIO_LOCKCLR_PIN1_Msk 0x00000002UL /*!< Lock configuration disable for pin 1 */ +#define GPIO_LOCKCLR_PIN2_Msk 0x00000004UL /*!< Lock configuration disable for pin 2 */ +#define GPIO_LOCKCLR_PIN3_Msk 0x00000008UL /*!< Lock configuration disable for pin 3 */ +#define GPIO_LOCKCLR_PIN4_Msk 0x00000010UL /*!< Lock configuration disable for pin 4 */ +#define GPIO_LOCKCLR_PIN5_Msk 0x00000020UL /*!< Lock configuration disable for pin 5 */ +#define GPIO_LOCKCLR_PIN6_Msk 0x00000040UL /*!< Lock configuration disable for pin 6 */ +#define GPIO_LOCKCLR_PIN7_Msk 0x00000080UL /*!< Lock configuration disable for pin 7 */ +#define GPIO_LOCKCLR_PIN8_Msk 0x00000100UL /*!< Lock configuration disable for pin 8 */ +#define GPIO_LOCKCLR_PIN9_Msk 0x00000200UL /*!< Lock configuration disable for pin 9 */ +#define GPIO_LOCKCLR_PIN10_Msk 0x00000400UL /*!< Lock configuration disable for pin 10 */ +#define GPIO_LOCKCLR_PIN11_Msk 0x00000800UL /*!< Lock configuration disable for pin 11 */ +#define GPIO_LOCKCLR_PIN12_Msk 0x00001000UL /*!< Lock configuration disable for pin 12 */ +#define GPIO_LOCKCLR_PIN13_Msk 0x00002000UL /*!< Lock configuration disable for pin 13 */ +#define GPIO_LOCKCLR_PIN14_Msk 0x00004000UL /*!< Lock configuration disable for pin 14 */ +#define GPIO_LOCKCLR_PIN15_Msk 0x00008000UL /*!< Lock configuration disable for pin 15 */ + +/*-- MASKLB: MASKLB: Mask register low byte of port -----------------------------------------------------------*/ +typedef struct { + uint32_t VAL :8; /*!< Mask low byte */ +} _GPIO_MASKLB_MASKLB_bits; + +/* Bit field positions: */ +#define GPIO_MASKLB_MASKLB_VAL_Pos 0 /*!< Mask low byte */ + +/* Bit field masks: */ +#define GPIO_MASKLB_MASKLB_VAL_Msk 0x000000FFUL /*!< Mask low byte */ + +/*-- MASKHB: MASKHB: Mask register High byte of port ----------------------------------------------------------*/ +typedef struct { + uint32_t :8; /*!< RESERVED */ + uint32_t VAL :8; /*!< Mask high byte */ +} _GPIO_MASKHB_MASKHB_bits; + +/* Bit field positions: */ +#define GPIO_MASKHB_MASKHB_VAL_Pos 8 /*!< Mask high byte */ + +/* Bit field masks: */ +#define GPIO_MASKHB_MASKHB_VAL_Msk 0x0000FF00UL /*!< Mask high byte */ + +//Cluster MASKLB: +typedef struct { + union { + /*!< Mask register low byte of port */ + __IO uint32_t MASKLB; /*!< MASKLB : type used for word access */ + __IO _GPIO_MASKLB_MASKLB_bits MASKLB_bit; /*!< MASKLB_bit: structure used for bit access */ + }; +} _GPIO_MASKLB_TypeDef; +//Cluster MASKHB: +typedef struct { + union { + /*!< Mask register High byte of port */ + __IO uint32_t MASKHB; /*!< MASKHB : type used for word access */ + __IO _GPIO_MASKHB_MASKHB_bits MASKHB_bit; /*!< MASKHB_bit: structure used for bit access */ + }; +} _GPIO_MASKHB_TypeDef; +typedef struct { + union { /*!< Data Input register */ + __IO uint32_t DATA; /*!< DATA : type used for word access */ + __IO _GPIO_DATA_bits DATA_bit; /*!< DATA_bit: structure used for bit access */ + }; + union { /*!< Data output register */ + __IO uint32_t DATAOUT; /*!< DATAOUT : type used for word access */ + __IO _GPIO_DATAOUT_bits DATAOUT_bit; /*!< DATAOUT_bit: structure used for bit access */ + }; + union { /*!< Data output set bits register */ + __IO uint32_t DATAOUTSET; /*!< DATAOUTSET : type used for word access */ + __IO _GPIO_DATAOUTSET_bits DATAOUTSET_bit; /*!< DATAOUTSET_bit: structure used for bit access */ + }; + union { /*!< Data output clear bits register */ + __IO uint32_t DATAOUTCLR; /*!< DATAOUTCLR : type used for word access */ + __IO _GPIO_DATAOUTCLR_bits DATAOUTCLR_bit; /*!< DATAOUTCLR_bit: structure used for bit access */ + }; + union { /*!< Data output toogle bits register */ + __IO uint32_t DATAOUTTGL; /*!< DATAOUTTGL : type used for word access */ + __IO _GPIO_DATAOUTTGL_bits DATAOUTTGL_bit; /*!< DATAOUTTGL_bit: structure used for bit access */ + }; + union { /*!< Digital function (PAD) enable register */ + __IO uint32_t DENSET; /*!< DENSET : type used for word access */ + __IO _GPIO_DENSET_bits DENSET_bit; /*!< DENSET_bit: structure used for bit access */ + }; + union { /*!< Digital function (PAD) disable register */ + __IO uint32_t DENCLR; /*!< DENCLR : type used for word access */ + __IO _GPIO_DENCLR_bits DENCLR_bit; /*!< DENCLR_bit: structure used for bit access */ + }; + union { /*!< Select input mode register */ + __IO uint32_t INMODE; /*!< INMODE : type used for word access */ + __IO _GPIO_INMODE_bits INMODE_bit; /*!< INMODE_bit: structure used for bit access */ + }; + union { /*!< Select pull mode register */ + __IO uint32_t PULLMODE; /*!< PULLMODE : type used for word access */ + __IO _GPIO_PULLMODE_bits PULLMODE_bit; /*!< PULLMODE_bit: structure used for bit access */ + }; + union { /*!< Select output mode register */ + __IO uint32_t OUTMODE; /*!< OUTMODE : type used for word access */ + __IO _GPIO_OUTMODE_bits OUTMODE_bit; /*!< OUTMODE_bit: structure used for bit access */ + }; + union { /*!< Select drive mode register */ + __IO uint32_t DRIVEMODE; /*!< DRIVEMODE : type used for word access */ + __IO _GPIO_DRIVEMODE_bits DRIVEMODE_bit; /*!< DRIVEMODE_bit: structure used for bit access */ + }; + union { /*!< Output enable register */ + __IO uint32_t OUTENSET; /*!< OUTENSET : type used for word access */ + __IO _GPIO_OUTENSET_bits OUTENSET_bit; /*!< OUTENSET_bit: structure used for bit access */ + }; + union { /*!< Output disable register */ + __IO uint32_t OUTENCLR; /*!< OUTENCLR : type used for word access */ + __IO _GPIO_OUTENCLR_bits OUTENCLR_bit; /*!< OUTENCLR_bit: structure used for bit access */ + }; + union { /*!< Alternative function enable register */ + __IO uint32_t ALTFUNCSET; /*!< ALTFUNCSET : type used for word access */ + __IO _GPIO_ALTFUNCSET_bits ALTFUNCSET_bit; /*!< ALTFUNCSET_bit: structure used for bit access */ + }; + union { /*!< Alternative function disable register */ + __IO uint32_t ALTFUNCCLR; /*!< ALTFUNCCLR : type used for word access */ + __IO _GPIO_ALTFUNCCLR_bits ALTFUNCCLR_bit; /*!< ALTFUNCCLR_bit: structure used for bit access */ + }; + __IO uint32_t Reserved0[2]; + union { /*!< Additional double flip-flop syncronization enable register */ + __IO uint32_t SYNCSET; /*!< SYNCSET : type used for word access */ + __IO _GPIO_SYNCSET_bits SYNCSET_bit; /*!< SYNCSET_bit: structure used for bit access */ + }; + union { /*!< Additional double flip-flop syncronization disable register */ + __IO uint32_t SYNCCLR; /*!< SYNCCLR : type used for word access */ + __IO _GPIO_SYNCCLR_bits SYNCCLR_bit; /*!< SYNCCLR_bit: structure used for bit access */ + }; + union { /*!< Qualifier enable register */ + __IO uint32_t QUALSET; /*!< QUALSET : type used for word access */ + __IO _GPIO_QUALSET_bits QUALSET_bit; /*!< QUALSET_bit: structure used for bit access */ + }; + union { /*!< Qualifier disable register */ + __IO uint32_t QUALCLR; /*!< QUALCLR : type used for word access */ + __IO _GPIO_QUALCLR_bits QUALCLR_bit; /*!< QUALCLR_bit: structure used for bit access */ + }; + union { /*!< Qualifier mode set register */ + __IO uint32_t QUALMODESET; /*!< QUALMODESET : type used for word access */ + __IO _GPIO_QUALMODESET_bits QUALMODESET_bit; /*!< QUALMODESET_bit: structure used for bit access */ + }; + union { /*!< Qualifier mode clear register */ + __IO uint32_t QUALMODECLR; /*!< QUALMODECLR : type used for word access */ + __IO _GPIO_QUALMODECLR_bits QUALMODECLR_bit; /*!< QUALMODECLR_bit: structure used for bit access */ + }; + union { /*!< Qualifier sample period register */ + __IO uint32_t QUALSAMPLE; /*!< QUALSAMPLE : type used for word access */ + __IO _GPIO_QUALSAMPLE_bits QUALSAMPLE_bit; /*!< QUALSAMPLE_bit: structure used for bit access */ + }; + union { /*!< Interrupt enable register */ + __IO uint32_t INTENSET; /*!< INTENSET : type used for word access */ + __IO _GPIO_INTENSET_bits INTENSET_bit; /*!< INTENSET_bit: structure used for bit access */ + }; + union { /*!< Interrupt disable register */ + __IO uint32_t INTENCLR; /*!< INTENCLR : type used for word access */ + __IO _GPIO_INTENCLR_bits INTENCLR_bit; /*!< INTENCLR_bit: structure used for bit access */ + }; + union { /*!< Interrupt type set register */ + __IO uint32_t INTTYPESET; /*!< INTTYPESET : type used for word access */ + __IO _GPIO_INTTYPESET_bits INTTYPESET_bit; /*!< INTTYPESET_bit: structure used for bit access */ + }; + union { /*!< Interrupt type clear register */ + __IO uint32_t INTTYPECLR; /*!< INTTYPECLR : type used for word access */ + __IO _GPIO_INTTYPECLR_bits INTTYPECLR_bit; /*!< INTTYPECLR_bit: structure used for bit access */ + }; + union { /*!< Interrupt polarity set register */ + __IO uint32_t INTPOLSET; /*!< INTPOLSET : type used for word access */ + __IO _GPIO_INTPOLSET_bits INTPOLSET_bit; /*!< INTPOLSET_bit: structure used for bit access */ + }; + union { /*!< Interrupt polarity clear register */ + __IO uint32_t INTPOLCLR; /*!< INTPOLCLR : type used for word access */ + __IO _GPIO_INTPOLCLR_bits INTPOLCLR_bit; /*!< INTPOLCLR_bit: structure used for bit access */ + }; + union { /*!< Interrupt every edge set register */ + __IO uint32_t INTEDGESET; /*!< INTEDGESET : type used for word access */ + __IO _GPIO_INTEDGESET_bits INTEDGESET_bit; /*!< INTEDGESET_bit: structure used for bit access */ + }; + union { /*!< Interrupt every edge clear register */ + __IO uint32_t INTEDGECLR; /*!< INTEDGECLR : type used for word access */ + __IO _GPIO_INTEDGECLR_bits INTEDGECLR_bit; /*!< INTEDGECLR_bit: structure used for bit access */ + }; + union { /*!< Interrupt status */ + __IO uint32_t INTSTATUS; /*!< INTSTATUS : type used for word access */ + __IO _GPIO_INTSTATUS_bits INTSTATUS_bit; /*!< INTSTATUS_bit: structure used for bit access */ + }; + union { /*!< DMA request enable register */ + __IO uint32_t DMAREQSET; /*!< DMAREQSET : type used for word access */ + __IO _GPIO_DMAREQSET_bits DMAREQSET_bit; /*!< DMAREQSET_bit: structure used for bit access */ + }; + union { /*!< DMA request disable register */ + __IO uint32_t DMAREQCLR; /*!< DMAREQCLR : type used for word access */ + __IO _GPIO_DMAREQCLR_bits DMAREQCLR_bit; /*!< DMAREQCLR_bit: structure used for bit access */ + }; + union { /*!< ADC Start Of Conversion enable register */ + __IO uint32_t ADCSOCSET; /*!< ADCSOCSET : type used for word access */ + __IO _GPIO_ADCSOCSET_bits ADCSOCSET_bit; /*!< ADCSOCSET_bit: structure used for bit access */ + }; + union { /*!< ADC Start Of Conversion disable register */ + __IO uint32_t ADCSOCCLR; /*!< ADCSOCCLR : type used for word access */ + __IO _GPIO_ADCSOCCLR_bits ADCSOCCLR_bit; /*!< ADCSOCCLR_bit: structure used for bit access */ + }; + union { /*!< Core RXEV request enable register */ + __IO uint32_t RXEVSET; /*!< RXEVSET : type used for word access */ + __IO _GPIO_RXEVSET_bits RXEVSET_bit; /*!< RXEVSET_bit: structure used for bit access */ + }; + union { /*!< Core RXEV request disable register */ + __IO uint32_t RXEVCLR; /*!< RXEVCLR : type used for word access */ + __IO _GPIO_RXEVCLR_bits RXEVCLR_bit; /*!< RXEVCLR_bit: structure used for bit access */ + }; + union { + union { /*!< Key register to unlock LOCKSET/LOCKCLR registers for write (KEY=0xADEADBEE) */ + __O uint32_t LOCKKEY; /*!< LOCKKEY : type used for word access */ + __O _GPIO_LOCKKEY_bits LOCKKEY_bit; /*!< LOCKKEY_bit: structure used for bit access */ + }; + struct { + union { /*!< LOCKSET/LOCKCLR write enable status register */ + __I uint32_t LOCKSTAT; /*!< LOCKSTAT : type used for word access */ + __I _GPIO_LOCKSTAT_bits LOCKSTAT_bit; /*!< LOCKSTAT_bit: structure used for bit access */ + }; + }; + }; + union { /*!< Lock pins configuration enable register */ + __IO uint32_t LOCKSET; /*!< LOCKSET : type used for word access */ + __IO _GPIO_LOCKSET_bits LOCKSET_bit; /*!< LOCKSET_bit: structure used for bit access */ + }; + union { /*!< Lock pins configuration disable register */ + __IO uint32_t LOCKCLR; /*!< LOCKCLR : type used for word access */ + __IO _GPIO_LOCKCLR_bits LOCKCLR_bit; /*!< LOCKCLR_bit: structure used for bit access */ + }; + __IO uint32_t Reserved1[214]; + _GPIO_MASKLB_TypeDef MASKLB[256]; + _GPIO_MASKHB_TypeDef MASKHB[256]; +} GPIO_TypeDef; + + +/******************************************************************************/ +/* UART registers */ +/******************************************************************************/ + +/*-- DR: Data Register ---------------------------------------------------------------------------------------*/ +typedef struct { + uint32_t DATA :8; /*!< Received/Transmitted data character */ + uint32_t FE :1; /*!< Framing error */ + uint32_t PE :1; /*!< Parity error */ + uint32_t BE :1; /*!< Break error */ + uint32_t OE :1; /*!< Overrun error */ +} _UART_DR_bits; + +/* Bit field positions: */ +#define UART_DR_DATA_Pos 0 /*!< Received/Transmitted data character */ +#define UART_DR_FE_Pos 8 /*!< Framing error */ +#define UART_DR_PE_Pos 9 /*!< Parity error */ +#define UART_DR_BE_Pos 10 /*!< Break error */ +#define UART_DR_OE_Pos 11 /*!< Overrun error */ + +/* Bit field masks: */ +#define UART_DR_DATA_Msk 0x000000FFUL /*!< Received/Transmitted data character */ +#define UART_DR_FE_Msk 0x00000100UL /*!< Framing error */ +#define UART_DR_PE_Msk 0x00000200UL /*!< Parity error */ +#define UART_DR_BE_Msk 0x00000400UL /*!< Break error */ +#define UART_DR_OE_Msk 0x00000800UL /*!< Overrun error */ + +/*-- RSR: Receive Status Register/Error Clear Register -------------------------------------------------------*/ +typedef struct { + uint32_t FE :1; /*!< Framing error */ + uint32_t PE :1; /*!< Parity error */ + uint32_t BE :1; /*!< Break error */ + uint32_t OE :1; /*!< Overrun error */ +} _UART_RSR_bits; + +/* Bit field positions: */ +#define UART_RSR_FE_Pos 0 /*!< Framing error */ +#define UART_RSR_PE_Pos 1 /*!< Parity error */ +#define UART_RSR_BE_Pos 2 /*!< Break error */ +#define UART_RSR_OE_Pos 3 /*!< Overrun error */ + +/* Bit field masks: */ +#define UART_RSR_FE_Msk 0x00000001UL /*!< Framing error */ +#define UART_RSR_PE_Msk 0x00000002UL /*!< Parity error */ +#define UART_RSR_BE_Msk 0x00000004UL /*!< Break error */ +#define UART_RSR_OE_Msk 0x00000008UL /*!< Overrun error */ + +/*-- FR: Flag Register ---------------------------------------------------------------------------------------*/ +typedef struct { + uint32_t :3; /*!< RESERVED */ + uint32_t BUSY :1; /*!< UART busy */ + uint32_t RXFE :1; /*!< Receive FIFO empty */ + uint32_t TXFF :1; /*!< Transmit FIFO full */ + uint32_t RXFF :1; /*!< Receive FIFO full */ + uint32_t TXFE :1; /*!< Transmit FIFO empty */ +} _UART_FR_bits; + +/* Bit field positions: */ +#define UART_FR_BUSY_Pos 3 /*!< UART busy */ +#define UART_FR_RXFE_Pos 4 /*!< Receive FIFO empty */ +#define UART_FR_TXFF_Pos 5 /*!< Transmit FIFO full */ +#define UART_FR_RXFF_Pos 6 /*!< Receive FIFO full */ +#define UART_FR_TXFE_Pos 7 /*!< Transmit FIFO empty */ + +/* Bit field masks: */ +#define UART_FR_BUSY_Msk 0x00000008UL /*!< UART busy */ +#define UART_FR_RXFE_Msk 0x00000010UL /*!< Receive FIFO empty */ +#define UART_FR_TXFF_Msk 0x00000020UL /*!< Transmit FIFO full */ +#define UART_FR_RXFF_Msk 0x00000040UL /*!< Receive FIFO full */ +#define UART_FR_TXFE_Msk 0x00000080UL /*!< Transmit FIFO empty */ + +/*-- IBRD: Integer Baud Rate Register ------------------------------------------------------------------------*/ +typedef struct { + uint32_t DIVINT :16; /*!< The integer baud rate divisor */ +} _UART_IBRD_bits; + +/* Bit field positions: */ +#define UART_IBRD_DIVINT_Pos 0 /*!< The integer baud rate divisor */ + +/* Bit field masks: */ +#define UART_IBRD_DIVINT_Msk 0x0000FFFFUL /*!< The integer baud rate divisor */ + +/*-- FBRD: Fractional Baud Rate Register ---------------------------------------------------------------------*/ +typedef struct { + uint32_t DIVFRAC :6; /*!< The fractional baud rate divisor */ +} _UART_FBRD_bits; + +/* Bit field positions: */ +#define UART_FBRD_DIVFRAC_Pos 0 /*!< The fractional baud rate divisor */ + +/* Bit field masks: */ +#define UART_FBRD_DIVFRAC_Msk 0x0000003FUL /*!< The fractional baud rate divisor */ + +/*-- LCRH: Line Control Register -----------------------------------------------------------------------------*/ +typedef struct { + uint32_t BRK :1; /*!< Send break */ + uint32_t PEN :1; /*!< Parity enable */ + uint32_t EPS :1; /*!< Even parity select */ + uint32_t STP2 :1; /*!< Two stop bits select */ + uint32_t FEN :1; /*!< Enable FIFOs */ + uint32_t WLEN :2; /*!< Word length */ + uint32_t SPS :1; /*!< Stick parity select */ +} _UART_LCRH_bits; + +/* Bit field positions: */ +#define UART_LCRH_BRK_Pos 0 /*!< Send break */ +#define UART_LCRH_PEN_Pos 1 /*!< Parity enable */ +#define UART_LCRH_EPS_Pos 2 /*!< Even parity select */ +#define UART_LCRH_STP2_Pos 3 /*!< Two stop bits select */ +#define UART_LCRH_FEN_Pos 4 /*!< Enable FIFOs */ +#define UART_LCRH_WLEN_Pos 5 /*!< Word length */ +#define UART_LCRH_SPS_Pos 7 /*!< Stick parity select */ + +/* Bit field masks: */ +#define UART_LCRH_BRK_Msk 0x00000001UL /*!< Send break */ +#define UART_LCRH_PEN_Msk 0x00000002UL /*!< Parity enable */ +#define UART_LCRH_EPS_Msk 0x00000004UL /*!< Even parity select */ +#define UART_LCRH_STP2_Msk 0x00000008UL /*!< Two stop bits select */ +#define UART_LCRH_FEN_Msk 0x00000010UL /*!< Enable FIFOs */ +#define UART_LCRH_WLEN_Msk 0x00000060UL /*!< Word length */ +#define UART_LCRH_SPS_Msk 0x00000080UL /*!< Stick parity select */ + +/* Bit field enums: */ +typedef enum { + UART_LCRH_WLEN_5bit = 0x0UL, /*!< 5 bit in informational word */ + UART_LCRH_WLEN_6bit = 0x1UL, /*!< 6 bit in informational word */ + UART_LCRH_WLEN_7bit = 0x2UL, /*!< 7 bit in informational word */ + UART_LCRH_WLEN_8bit = 0x3UL, /*!< 8 bit in informational word */ +} UART_LCRH_WLEN_Enum; + +/*-- CR: Control Register ------------------------------------------------------------------------------------*/ +typedef struct { + uint32_t UARTEN :1; /*!< UART enable */ + uint32_t :7; /*!< RESERVED */ + uint32_t TXE :1; /*!< Transmit enable */ + uint32_t RXE :1; /*!< Receive enable */ +} _UART_CR_bits; + +/* Bit field positions: */ +#define UART_CR_UARTEN_Pos 0 /*!< UART enable */ +#define UART_CR_TXE_Pos 8 /*!< Transmit enable */ +#define UART_CR_RXE_Pos 9 /*!< Receive enable */ + +/* Bit field masks: */ +#define UART_CR_UARTEN_Msk 0x00000001UL /*!< UART enable */ +#define UART_CR_TXE_Msk 0x00000100UL /*!< Transmit enable */ +#define UART_CR_RXE_Msk 0x00000200UL /*!< Receive enable */ + +/*-- IFLS: Interrupt FIFO Level Select Register --------------------------------------------------------------*/ +typedef struct { + uint32_t TXIFLSEL :3; /*!< Transmit interrupt FIFO level select */ + uint32_t RXIFLSEL :3; /*!< Receive interrupt FIFO level select */ +} _UART_IFLS_bits; + +/* Bit field positions: */ +#define UART_IFLS_TXIFLSEL_Pos 0 /*!< Transmit interrupt FIFO level select */ +#define UART_IFLS_RXIFLSEL_Pos 3 /*!< Receive interrupt FIFO level select */ + +/* Bit field masks: */ +#define UART_IFLS_TXIFLSEL_Msk 0x00000007UL /*!< Transmit interrupt FIFO level select */ +#define UART_IFLS_RXIFLSEL_Msk 0x00000038UL /*!< Receive interrupt FIFO level select */ + +/* Bit field enums: */ +typedef enum { + UART_IFLS_TXIFLSEL_Lvl18 = 0x0UL, /*!< interrupt on 1/8 */ + UART_IFLS_TXIFLSEL_Lvl14 = 0x1UL, /*!< interrupt on 1/4 */ + UART_IFLS_TXIFLSEL_Lvl12 = 0x2UL, /*!< interrupt on 1/2 */ + UART_IFLS_TXIFLSEL_Lvl34 = 0x3UL, /*!< interrupt on 3/4 */ + UART_IFLS_TXIFLSEL_Lvl78 = 0x4UL, /*!< interrupt on 7/8 */ +} UART_IFLS_TXIFLSEL_Enum; + +typedef enum { + UART_IFLS_RXIFLSEL_Lvl18 = 0x0UL, /*!< interrupt on 1/8 */ + UART_IFLS_RXIFLSEL_Lvl14 = 0x1UL, /*!< interrupt on 1/4 */ + UART_IFLS_RXIFLSEL_Lvl12 = 0x2UL, /*!< interrupt on 1/2 */ + UART_IFLS_RXIFLSEL_Lvl34 = 0x3UL, /*!< interrupt on 3/4 */ + UART_IFLS_RXIFLSEL_Lvl78 = 0x4UL, /*!< interrupt on 7/8 */ +} UART_IFLS_RXIFLSEL_Enum; + +/*-- IMSC: Interrupt Mask Set/Clear Register -----------------------------------------------------------------*/ +typedef struct { + uint32_t :4; /*!< RESERVED */ + uint32_t RXIM :1; /*!< Receive interrupt mask */ + uint32_t TXIM :1; /*!< Transmit interrupt mask */ + uint32_t RTIM :1; /*!< Receive timeout interrupt mask */ + uint32_t FEIM :1; /*!< Framing error interrupt mask */ + uint32_t PEIM :1; /*!< Parity error interrupt mask */ + uint32_t BEIM :1; /*!< Break error interrupt mask */ + uint32_t OEIM :1; /*!< Overrun error interrupt mask */ + uint32_t TDIM :1; /*!< Transmit done interrupt mask */ +} _UART_IMSC_bits; + +/* Bit field positions: */ +#define UART_IMSC_RXIM_Pos 4 /*!< Receive interrupt mask */ +#define UART_IMSC_TXIM_Pos 5 /*!< Transmit interrupt mask */ +#define UART_IMSC_RTIM_Pos 6 /*!< Receive timeout interrupt mask */ +#define UART_IMSC_FEIM_Pos 7 /*!< Framing error interrupt mask */ +#define UART_IMSC_PEIM_Pos 8 /*!< Parity error interrupt mask */ +#define UART_IMSC_BEIM_Pos 9 /*!< Break error interrupt mask */ +#define UART_IMSC_OEIM_Pos 10 /*!< Overrun error interrupt mask */ +#define UART_IMSC_TDIM_Pos 11 /*!< Transmit done interrupt mask */ + +/* Bit field masks: */ +#define UART_IMSC_RXIM_Msk 0x00000010UL /*!< Receive interrupt mask */ +#define UART_IMSC_TXIM_Msk 0x00000020UL /*!< Transmit interrupt mask */ +#define UART_IMSC_RTIM_Msk 0x00000040UL /*!< Receive timeout interrupt mask */ +#define UART_IMSC_FEIM_Msk 0x00000080UL /*!< Framing error interrupt mask */ +#define UART_IMSC_PEIM_Msk 0x00000100UL /*!< Parity error interrupt mask */ +#define UART_IMSC_BEIM_Msk 0x00000200UL /*!< Break error interrupt mask */ +#define UART_IMSC_OEIM_Msk 0x00000400UL /*!< Overrun error interrupt mask */ +#define UART_IMSC_TDIM_Msk 0x00000800UL /*!< Transmit done interrupt mask */ + +/*-- RIS: Raw Interrupt Status Register ----------------------------------------------------------------------*/ +typedef struct { + uint32_t :4; /*!< RESERVED */ + uint32_t RXRIS :1; /*!< Receive interrupt status */ + uint32_t TXRIS :1; /*!< Transmit interrupt status */ + uint32_t RTRIS :1; /*!< Receive timeout interrupt status */ + uint32_t FERIS :1; /*!< Framing error interrupt status */ + uint32_t PERIS :1; /*!< Parity error interrupt status */ + uint32_t BERIS :1; /*!< Break error interrupt status */ + uint32_t OERIS :1; /*!< Overrun error interrupt status */ + uint32_t TDRIS :1; /*!< Transmit done raw interrupt status */ +} _UART_RIS_bits; + +/* Bit field positions: */ +#define UART_RIS_RXRIS_Pos 4 /*!< Receive interrupt status */ +#define UART_RIS_TXRIS_Pos 5 /*!< Transmit interrupt status */ +#define UART_RIS_RTRIS_Pos 6 /*!< Receive timeout interrupt status */ +#define UART_RIS_FERIS_Pos 7 /*!< Framing error interrupt status */ +#define UART_RIS_PERIS_Pos 8 /*!< Parity error interrupt status */ +#define UART_RIS_BERIS_Pos 9 /*!< Break error interrupt status */ +#define UART_RIS_OERIS_Pos 10 /*!< Overrun error interrupt status */ +#define UART_RIS_TDRIS_Pos 11 /*!< Transmit done raw interrupt status */ + +/* Bit field masks: */ +#define UART_RIS_RXRIS_Msk 0x00000010UL /*!< Receive interrupt status */ +#define UART_RIS_TXRIS_Msk 0x00000020UL /*!< Transmit interrupt status */ +#define UART_RIS_RTRIS_Msk 0x00000040UL /*!< Receive timeout interrupt status */ +#define UART_RIS_FERIS_Msk 0x00000080UL /*!< Framing error interrupt status */ +#define UART_RIS_PERIS_Msk 0x00000100UL /*!< Parity error interrupt status */ +#define UART_RIS_BERIS_Msk 0x00000200UL /*!< Break error interrupt status */ +#define UART_RIS_OERIS_Msk 0x00000400UL /*!< Overrun error interrupt status */ +#define UART_RIS_TDRIS_Msk 0x00000800UL /*!< Transmit done raw interrupt status */ + +/*-- MIS: Masked Interrupt Status Register -------------------------------------------------------------------*/ +typedef struct { + uint32_t :4; /*!< RESERVED */ + uint32_t RXMIS :1; /*!< Receive masked interrupt status */ + uint32_t TXMIS :1; /*!< Transmit masked interrupt status */ + uint32_t RTMIS :1; /*!< Receive timeout masked interrupt status */ + uint32_t FEMIS :1; /*!< Framing error masked interrupt status */ + uint32_t PEMIS :1; /*!< Parity error masked interrupt status */ + uint32_t BEMIS :1; /*!< Break error masked interrupt status */ + uint32_t OEMIS :1; /*!< Overrun error masked interrupt status */ + uint32_t TDMIS :1; /*!< Transmit done masked interrupt status */ +} _UART_MIS_bits; + +/* Bit field positions: */ +#define UART_MIS_RXMIS_Pos 4 /*!< Receive masked interrupt status */ +#define UART_MIS_TXMIS_Pos 5 /*!< Transmit masked interrupt status */ +#define UART_MIS_RTMIS_Pos 6 /*!< Receive timeout masked interrupt status */ +#define UART_MIS_FEMIS_Pos 7 /*!< Framing error masked interrupt status */ +#define UART_MIS_PEMIS_Pos 8 /*!< Parity error masked interrupt status */ +#define UART_MIS_BEMIS_Pos 9 /*!< Break error masked interrupt status */ +#define UART_MIS_OEMIS_Pos 10 /*!< Overrun error masked interrupt status */ +#define UART_MIS_TDMIS_Pos 11 /*!< Transmit done masked interrupt status */ + +/* Bit field masks: */ +#define UART_MIS_RXMIS_Msk 0x00000010UL /*!< Receive masked interrupt status */ +#define UART_MIS_TXMIS_Msk 0x00000020UL /*!< Transmit masked interrupt status */ +#define UART_MIS_RTMIS_Msk 0x00000040UL /*!< Receive timeout masked interrupt status */ +#define UART_MIS_FEMIS_Msk 0x00000080UL /*!< Framing error masked interrupt status */ +#define UART_MIS_PEMIS_Msk 0x00000100UL /*!< Parity error masked interrupt status */ +#define UART_MIS_BEMIS_Msk 0x00000200UL /*!< Break error masked interrupt status */ +#define UART_MIS_OEMIS_Msk 0x00000400UL /*!< Overrun error masked interrupt status */ +#define UART_MIS_TDMIS_Msk 0x00000800UL /*!< Transmit done masked interrupt status */ + +/*-- ICR: Interrupt Clear Register ---------------------------------------------------------------------------*/ +typedef struct { + uint32_t :4; /*!< RESERVED */ + uint32_t RXIC :1; /*!< Receive interrupt clear */ + uint32_t TXIC :1; /*!< Transmit interrupt clear */ + uint32_t RTIC :1; /*!< Receive timeout interrupt clear */ + uint32_t FEIC :1; /*!< Framing error interrupt clear */ + uint32_t PEIC :1; /*!< Parity error interrupt clear */ + uint32_t BEIC :1; /*!< Break error interrupt clear */ + uint32_t OEIC :1; /*!< Overrun error interrupt clear */ + uint32_t TDIC :1; /*!< Transmit done interrupt clear */ +} _UART_ICR_bits; + +/* Bit field positions: */ +#define UART_ICR_RXIC_Pos 4 /*!< Receive interrupt clear */ +#define UART_ICR_TXIC_Pos 5 /*!< Transmit interrupt clear */ +#define UART_ICR_RTIC_Pos 6 /*!< Receive timeout interrupt clear */ +#define UART_ICR_FEIC_Pos 7 /*!< Framing error interrupt clear */ +#define UART_ICR_PEIC_Pos 8 /*!< Parity error interrupt clear */ +#define UART_ICR_BEIC_Pos 9 /*!< Break error interrupt clear */ +#define UART_ICR_OEIC_Pos 10 /*!< Overrun error interrupt clear */ +#define UART_ICR_TDIC_Pos 11 /*!< Transmit done interrupt clear */ + +/* Bit field masks: */ +#define UART_ICR_RXIC_Msk 0x00000010UL /*!< Receive interrupt clear */ +#define UART_ICR_TXIC_Msk 0x00000020UL /*!< Transmit interrupt clear */ +#define UART_ICR_RTIC_Msk 0x00000040UL /*!< Receive timeout interrupt clear */ +#define UART_ICR_FEIC_Msk 0x00000080UL /*!< Framing error interrupt clear */ +#define UART_ICR_PEIC_Msk 0x00000100UL /*!< Parity error interrupt clear */ +#define UART_ICR_BEIC_Msk 0x00000200UL /*!< Break error interrupt clear */ +#define UART_ICR_OEIC_Msk 0x00000400UL /*!< Overrun error interrupt clear */ +#define UART_ICR_TDIC_Msk 0x00000800UL /*!< Transmit done interrupt clear */ + +/*-- DMACR: DMA Control Register -----------------------------------------------------------------------------*/ +typedef struct { + uint32_t RXDMAE :1; /*!< Receive DMA enable */ + uint32_t TXDMAE :1; /*!< Transmit DMA enable */ + uint32_t DMAONERR :1; /*!< DMA on error */ +} _UART_DMACR_bits; + +/* Bit field positions: */ +#define UART_DMACR_RXDMAE_Pos 0 /*!< Receive DMA enable */ +#define UART_DMACR_TXDMAE_Pos 1 /*!< Transmit DMA enable */ +#define UART_DMACR_DMAONERR_Pos 2 /*!< DMA on error */ + +/* Bit field masks: */ +#define UART_DMACR_RXDMAE_Msk 0x00000001UL /*!< Receive DMA enable */ +#define UART_DMACR_TXDMAE_Msk 0x00000002UL /*!< Transmit DMA enable */ +#define UART_DMACR_DMAONERR_Msk 0x00000004UL /*!< DMA on error */ + +typedef struct { + union { /*!< Data Register */ + __IO uint32_t DR; /*!< DR : type used for word access */ + __IO _UART_DR_bits DR_bit; /*!< DR_bit: structure used for bit access */ + }; + union { /*!< Receive Status Register/Error Clear Register */ + __IO uint32_t RSR; /*!< RSR : type used for word access */ + __IO _UART_RSR_bits RSR_bit; /*!< RSR_bit: structure used for bit access */ + }; + __IO uint32_t Reserved0[4]; + union { /*!< Flag Register */ + __I uint32_t FR; /*!< FR : type used for word access */ + __I _UART_FR_bits FR_bit; /*!< FR_bit: structure used for bit access */ + }; + __IO uint32_t Reserved1[2]; + union { /*!< Integer Baud Rate Register */ + __IO uint32_t IBRD; /*!< IBRD : type used for word access */ + __IO _UART_IBRD_bits IBRD_bit; /*!< IBRD_bit: structure used for bit access */ + }; + union { /*!< Fractional Baud Rate Register */ + __IO uint32_t FBRD; /*!< FBRD : type used for word access */ + __IO _UART_FBRD_bits FBRD_bit; /*!< FBRD_bit: structure used for bit access */ + }; + union { /*!< Line Control Register */ + __IO uint32_t LCRH; /*!< LCRH : type used for word access */ + __IO _UART_LCRH_bits LCRH_bit; /*!< LCRH_bit: structure used for bit access */ + }; + union { /*!< Control Register */ + __IO uint32_t CR; /*!< CR : type used for word access */ + __IO _UART_CR_bits CR_bit; /*!< CR_bit: structure used for bit access */ + }; + union { /*!< Interrupt FIFO Level Select Register */ + __IO uint32_t IFLS; /*!< IFLS : type used for word access */ + __IO _UART_IFLS_bits IFLS_bit; /*!< IFLS_bit: structure used for bit access */ + }; + union { /*!< Interrupt Mask Set/Clear Register */ + __IO uint32_t IMSC; /*!< IMSC : type used for word access */ + __IO _UART_IMSC_bits IMSC_bit; /*!< IMSC_bit: structure used for bit access */ + }; + union { /*!< Raw Interrupt Status Register */ + __IO uint32_t RIS; /*!< RIS : type used for word access */ + __IO _UART_RIS_bits RIS_bit; /*!< RIS_bit: structure used for bit access */ + }; + union { /*!< Masked Interrupt Status Register */ + __IO uint32_t MIS; /*!< MIS : type used for word access */ + __IO _UART_MIS_bits MIS_bit; /*!< MIS_bit: structure used for bit access */ + }; + union { /*!< Interrupt Clear Register */ + __IO uint32_t ICR; /*!< ICR : type used for word access */ + __IO _UART_ICR_bits ICR_bit; /*!< ICR_bit: structure used for bit access */ + }; + union { /*!< DMA Control Register */ + __IO uint32_t DMACR; /*!< DMACR : type used for word access */ + __IO _UART_DMACR_bits DMACR_bit; /*!< DMACR_bit: structure used for bit access */ + }; +} UART_TypeDef; + + +/******************************************************************************/ +/* DMA registers */ +/******************************************************************************/ + +/*-- STATUS: Status DMA register -----------------------------------------------------------------------------*/ +typedef struct { + uint32_t MASTEREN :1; /*!< Indicate enable DMA */ + uint32_t :3; /*!< RESERVED */ + uint32_t STATE :4; /*!< State of DMA */ + uint32_t :8; /*!< RESERVED */ + uint32_t CHNLS :5; /*!< Number channel DMA (write: N-1) */ +} _DMA_STATUS_bits; + +/* Bit field positions: */ +#define DMA_STATUS_MASTEREN_Pos 0 /*!< Indicate enable DMA */ +#define DMA_STATUS_STATE_Pos 4 /*!< State of DMA */ +#define DMA_STATUS_CHNLS_Pos 16 /*!< Number channel DMA (write: N-1) */ + +/* Bit field masks: */ +#define DMA_STATUS_MASTEREN_Msk 0x00000001UL /*!< Indicate enable DMA */ +#define DMA_STATUS_STATE_Msk 0x000000F0UL /*!< State of DMA */ +#define DMA_STATUS_CHNLS_Msk 0x001F0000UL /*!< Number channel DMA (write: N-1) */ + +/* Bit field enums: */ +typedef enum { + DMA_STATUS_STATE_Free = 0x0UL, /*!< At rest */ + DMA_STATUS_STATE_ReadConfigData = 0x1UL, /*!< Reading the config data structure */ + DMA_STATUS_STATE_ReadSrcDataEndPtr = 0x2UL, /*!< Reading sourse data end pointer */ + DMA_STATUS_STATE_ReadDstDataEndPtr = 0x3UL, /*!< Reading destination data end pointer */ + DMA_STATUS_STATE_ReadSrcData = 0x4UL, /*!< Reading source data */ + DMA_STATUS_STATE_WrireDstData = 0x5UL, /*!< Writing data to the destination */ + DMA_STATUS_STATE_WaitReq = 0x6UL, /*!< Waiting for a request */ + DMA_STATUS_STATE_WriteConfigData = 0x7UL, /*!< Write config structure of the channel */ + DMA_STATUS_STATE_Pause = 0x8UL, /*!< Suspended */ + DMA_STATUS_STATE_Done = 0x9UL, /*!< Executed */ + DMA_STATUS_STATE_PeriphScatGath = 0xAUL, /*!< mode "peripheral scather-gather" */ +} DMA_STATUS_STATE_Enum; + +/*-- CFG: DMA configuration register -------------------------------------------------------------------------*/ +typedef struct { + uint32_t MASTEREN :1; /*!< Enable DMA */ + uint32_t :4; /*!< RESERVED */ + uint32_t CHPROT :3; /*!< Sets the AHB-Lite protection */ +} _DMA_CFG_bits; + +/* Bit field positions: */ +#define DMA_CFG_MASTEREN_Pos 0 /*!< Enable DMA */ +#define DMA_CFG_CHPROT_Pos 5 /*!< Sets the AHB-Lite protection */ + +/* Bit field masks: */ +#define DMA_CFG_MASTEREN_Msk 0x00000001UL /*!< Enable DMA */ +#define DMA_CFG_CHPROT_Msk 0x000000E0UL /*!< Sets the AHB-Lite protection */ + +/*-- BASEPTR: Channel control data base pointer --------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< Base address of the primary control data */ +} _DMA_BASEPTR_bits; + +/* Bit field positions: */ +#define DMA_BASEPTR_VAL_Pos 0 /*!< Base address of the primary control data */ + +/* Bit field masks: */ +#define DMA_BASEPTR_VAL_Msk 0xFFFFFFFFUL /*!< Base address of the primary control data */ + +/*-- ALTBASEPTR: Channel alternate control data base pointer -------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< Base address of alternative control data */ +} _DMA_ALTBASEPTR_bits; + +/* Bit field positions: */ +#define DMA_ALTBASEPTR_VAL_Pos 0 /*!< Base address of alternative control data */ + +/* Bit field masks: */ +#define DMA_ALTBASEPTR_VAL_Msk 0xFFFFFFFFUL /*!< Base address of alternative control data */ + +/*-- WAITONREQ: Channel wait on request status ---------------------------------------------------------------*/ +typedef struct { + uint32_t CH0 :1; /*!< Returns the status of the DMA request signals */ + uint32_t CH1 :1; /*!< Returns the status of the DMA request signals */ + uint32_t CH2 :1; /*!< Returns the status of the DMA request signals */ + uint32_t CH3 :1; /*!< Returns the status of the DMA request signals */ + uint32_t CH4 :1; /*!< Returns the status of the DMA request signals */ + uint32_t CH5 :1; /*!< Returns the status of the DMA request signals */ + uint32_t CH6 :1; /*!< Returns the status of the DMA request signals */ + uint32_t CH7 :1; /*!< Returns the status of the DMA request signals */ + uint32_t CH8 :1; /*!< Returns the status of the DMA request signals */ + uint32_t CH9 :1; /*!< Returns the status of the DMA request signals */ + uint32_t CH10 :1; /*!< Returns the status of the DMA request signals */ + uint32_t CH11 :1; /*!< Returns the status of the DMA request signals */ + uint32_t CH12 :1; /*!< Returns the status of the DMA request signals */ + uint32_t CH13 :1; /*!< Returns the status of the DMA request signals */ + uint32_t CH14 :1; /*!< Returns the status of the DMA request signals */ + uint32_t CH15 :1; /*!< Returns the status of the DMA request signals */ +} _DMA_WAITONREQ_bits; + +/* Bit field positions: */ +#define DMA_WAITONREQ_CH0_Pos 0 /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH1_Pos 1 /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH2_Pos 2 /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH3_Pos 3 /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH4_Pos 4 /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH5_Pos 5 /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH6_Pos 6 /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH7_Pos 7 /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH8_Pos 8 /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH9_Pos 9 /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH10_Pos 10 /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH11_Pos 11 /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH12_Pos 12 /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH13_Pos 13 /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH14_Pos 14 /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH15_Pos 15 /*!< Returns the status of the DMA request signals */ + +/* Bit field masks: */ +#define DMA_WAITONREQ_CH0_Msk 0x00000001UL /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH1_Msk 0x00000002UL /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH2_Msk 0x00000004UL /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH3_Msk 0x00000008UL /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH4_Msk 0x00000010UL /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH5_Msk 0x00000020UL /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH6_Msk 0x00000040UL /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH7_Msk 0x00000080UL /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH8_Msk 0x00000100UL /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH9_Msk 0x00000200UL /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH10_Msk 0x00000400UL /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH11_Msk 0x00000800UL /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH12_Msk 0x00001000UL /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH13_Msk 0x00002000UL /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH14_Msk 0x00004000UL /*!< Returns the status of the DMA request signals */ +#define DMA_WAITONREQ_CH15_Msk 0x00008000UL /*!< Returns the status of the DMA request signals */ + +/*-- SWREQ: Channel software request -------------------------------------------------------------------------*/ +typedef struct { + uint32_t CH0 :1; /*!< Set software request on channel */ + uint32_t CH1 :1; /*!< Set software request on channel */ + uint32_t CH2 :1; /*!< Set software request on channel */ + uint32_t CH3 :1; /*!< Set software request on channel */ + uint32_t CH4 :1; /*!< Set software request on channel */ + uint32_t CH5 :1; /*!< Set software request on channel */ + uint32_t CH6 :1; /*!< Set software request on channel */ + uint32_t CH7 :1; /*!< Set software request on channel */ + uint32_t CH8 :1; /*!< Set software request on channel */ + uint32_t CH9 :1; /*!< Set software request on channel */ + uint32_t CH10 :1; /*!< Set software request on channel */ + uint32_t CH11 :1; /*!< Set software request on channel */ + uint32_t CH12 :1; /*!< Set software request on channel */ + uint32_t CH13 :1; /*!< Set software request on channel */ + uint32_t CH14 :1; /*!< Set software request on channel */ + uint32_t CH15 :1; /*!< Set software request on channel */ +} _DMA_SWREQ_bits; + +/* Bit field positions: */ +#define DMA_SWREQ_CH0_Pos 0 /*!< Set software request on channel */ +#define DMA_SWREQ_CH1_Pos 1 /*!< Set software request on channel */ +#define DMA_SWREQ_CH2_Pos 2 /*!< Set software request on channel */ +#define DMA_SWREQ_CH3_Pos 3 /*!< Set software request on channel */ +#define DMA_SWREQ_CH4_Pos 4 /*!< Set software request on channel */ +#define DMA_SWREQ_CH5_Pos 5 /*!< Set software request on channel */ +#define DMA_SWREQ_CH6_Pos 6 /*!< Set software request on channel */ +#define DMA_SWREQ_CH7_Pos 7 /*!< Set software request on channel */ +#define DMA_SWREQ_CH8_Pos 8 /*!< Set software request on channel */ +#define DMA_SWREQ_CH9_Pos 9 /*!< Set software request on channel */ +#define DMA_SWREQ_CH10_Pos 10 /*!< Set software request on channel */ +#define DMA_SWREQ_CH11_Pos 11 /*!< Set software request on channel */ +#define DMA_SWREQ_CH12_Pos 12 /*!< Set software request on channel */ +#define DMA_SWREQ_CH13_Pos 13 /*!< Set software request on channel */ +#define DMA_SWREQ_CH14_Pos 14 /*!< Set software request on channel */ +#define DMA_SWREQ_CH15_Pos 15 /*!< Set software request on channel */ + +/* Bit field masks: */ +#define DMA_SWREQ_CH0_Msk 0x00000001UL /*!< Set software request on channel */ +#define DMA_SWREQ_CH1_Msk 0x00000002UL /*!< Set software request on channel */ +#define DMA_SWREQ_CH2_Msk 0x00000004UL /*!< Set software request on channel */ +#define DMA_SWREQ_CH3_Msk 0x00000008UL /*!< Set software request on channel */ +#define DMA_SWREQ_CH4_Msk 0x00000010UL /*!< Set software request on channel */ +#define DMA_SWREQ_CH5_Msk 0x00000020UL /*!< Set software request on channel */ +#define DMA_SWREQ_CH6_Msk 0x00000040UL /*!< Set software request on channel */ +#define DMA_SWREQ_CH7_Msk 0x00000080UL /*!< Set software request on channel */ +#define DMA_SWREQ_CH8_Msk 0x00000100UL /*!< Set software request on channel */ +#define DMA_SWREQ_CH9_Msk 0x00000200UL /*!< Set software request on channel */ +#define DMA_SWREQ_CH10_Msk 0x00000400UL /*!< Set software request on channel */ +#define DMA_SWREQ_CH11_Msk 0x00000800UL /*!< Set software request on channel */ +#define DMA_SWREQ_CH12_Msk 0x00001000UL /*!< Set software request on channel */ +#define DMA_SWREQ_CH13_Msk 0x00002000UL /*!< Set software request on channel */ +#define DMA_SWREQ_CH14_Msk 0x00004000UL /*!< Set software request on channel */ +#define DMA_SWREQ_CH15_Msk 0x00008000UL /*!< Set software request on channel */ + +/*-- USEBURSTSET: Channel useburst set -----------------------------------------------------------------------*/ +typedef struct { + uint32_t CH0 :1; /*!< Enable single requests */ + uint32_t CH1 :1; /*!< Enable single requests */ + uint32_t CH2 :1; /*!< Enable single requests */ + uint32_t CH3 :1; /*!< Enable single requests */ + uint32_t CH4 :1; /*!< Enable single requests */ + uint32_t CH5 :1; /*!< Enable single requests */ + uint32_t CH6 :1; /*!< Enable single requests */ + uint32_t CH7 :1; /*!< Enable single requests */ + uint32_t CH8 :1; /*!< Enable single requests */ + uint32_t CH9 :1; /*!< Enable single requests */ + uint32_t CH10 :1; /*!< Enable single requests */ + uint32_t CH11 :1; /*!< Enable single requests */ + uint32_t CH12 :1; /*!< Enable single requests */ + uint32_t CH13 :1; /*!< Enable single requests */ + uint32_t CH14 :1; /*!< Enable single requests */ + uint32_t CH15 :1; /*!< Enable single requests */ +} _DMA_USEBURSTSET_bits; + +/* Bit field positions: */ +#define DMA_USEBURSTSET_CH0_Pos 0 /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH1_Pos 1 /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH2_Pos 2 /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH3_Pos 3 /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH4_Pos 4 /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH5_Pos 5 /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH6_Pos 6 /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH7_Pos 7 /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH8_Pos 8 /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH9_Pos 9 /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH10_Pos 10 /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH11_Pos 11 /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH12_Pos 12 /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH13_Pos 13 /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH14_Pos 14 /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH15_Pos 15 /*!< Enable single requests */ + +/* Bit field masks: */ +#define DMA_USEBURSTSET_CH0_Msk 0x00000001UL /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH1_Msk 0x00000002UL /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH2_Msk 0x00000004UL /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH3_Msk 0x00000008UL /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH4_Msk 0x00000010UL /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH5_Msk 0x00000020UL /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH6_Msk 0x00000040UL /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH7_Msk 0x00000080UL /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH8_Msk 0x00000100UL /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH9_Msk 0x00000200UL /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH10_Msk 0x00000400UL /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH11_Msk 0x00000800UL /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH12_Msk 0x00001000UL /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH13_Msk 0x00002000UL /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH14_Msk 0x00004000UL /*!< Enable single requests */ +#define DMA_USEBURSTSET_CH15_Msk 0x00008000UL /*!< Enable single requests */ + +/*-- USEBURSTCLR: Channel useburst clear ---------------------------------------------------------------------*/ +typedef struct { + uint32_t CH0 :1; /*!< Disable single requests */ + uint32_t CH1 :1; /*!< Disable single requests */ + uint32_t CH2 :1; /*!< Disable single requests */ + uint32_t CH3 :1; /*!< Disable single requests */ + uint32_t CH4 :1; /*!< Disable single requests */ + uint32_t CH5 :1; /*!< Disable single requests */ + uint32_t CH6 :1; /*!< Disable single requests */ + uint32_t CH7 :1; /*!< Disable single requests */ + uint32_t CH8 :1; /*!< Disable single requests */ + uint32_t CH9 :1; /*!< Disable single requests */ + uint32_t CH10 :1; /*!< Disable single requests */ + uint32_t CH11 :1; /*!< Disable single requests */ + uint32_t CH12 :1; /*!< Disable single requests */ + uint32_t CH13 :1; /*!< Disable single requests */ + uint32_t CH14 :1; /*!< Disable single requests */ + uint32_t CH15 :1; /*!< Disable single requests */ +} _DMA_USEBURSTCLR_bits; + +/* Bit field positions: */ +#define DMA_USEBURSTCLR_CH0_Pos 0 /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH1_Pos 1 /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH2_Pos 2 /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH3_Pos 3 /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH4_Pos 4 /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH5_Pos 5 /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH6_Pos 6 /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH7_Pos 7 /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH8_Pos 8 /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH9_Pos 9 /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH10_Pos 10 /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH11_Pos 11 /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH12_Pos 12 /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH13_Pos 13 /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH14_Pos 14 /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH15_Pos 15 /*!< Disable single requests */ + +/* Bit field masks: */ +#define DMA_USEBURSTCLR_CH0_Msk 0x00000001UL /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH1_Msk 0x00000002UL /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH2_Msk 0x00000004UL /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH3_Msk 0x00000008UL /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH4_Msk 0x00000010UL /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH5_Msk 0x00000020UL /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH6_Msk 0x00000040UL /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH7_Msk 0x00000080UL /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH8_Msk 0x00000100UL /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH9_Msk 0x00000200UL /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH10_Msk 0x00000400UL /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH11_Msk 0x00000800UL /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH12_Msk 0x00001000UL /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH13_Msk 0x00002000UL /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH14_Msk 0x00004000UL /*!< Disable single requests */ +#define DMA_USEBURSTCLR_CH15_Msk 0x00008000UL /*!< Disable single requests */ + +/*-- REQMASKSET: Channel request mask set --------------------------------------------------------------------*/ +typedef struct { + uint32_t CH0 :1; /*!< External requests are enabled for channel */ + uint32_t CH1 :1; /*!< External requests are enabled for channel */ + uint32_t CH2 :1; /*!< External requests are enabled for channel */ + uint32_t CH3 :1; /*!< External requests are enabled for channel */ + uint32_t CH4 :1; /*!< External requests are enabled for channel */ + uint32_t CH5 :1; /*!< External requests are enabled for channel */ + uint32_t CH6 :1; /*!< External requests are enabled for channel */ + uint32_t CH7 :1; /*!< External requests are enabled for channel */ + uint32_t CH8 :1; /*!< External requests are enabled for channel */ + uint32_t CH9 :1; /*!< External requests are enabled for channel */ + uint32_t CH10 :1; /*!< External requests are enabled for channel */ + uint32_t CH11 :1; /*!< External requests are enabled for channel */ + uint32_t CH12 :1; /*!< External requests are enabled for channel */ + uint32_t CH13 :1; /*!< External requests are enabled for channel */ + uint32_t CH14 :1; /*!< External requests are enabled for channel */ + uint32_t CH15 :1; /*!< External requests are enabled for channel */ +} _DMA_REQMASKSET_bits; + +/* Bit field positions: */ +#define DMA_REQMASKSET_CH0_Pos 0 /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH1_Pos 1 /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH2_Pos 2 /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH3_Pos 3 /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH4_Pos 4 /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH5_Pos 5 /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH6_Pos 6 /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH7_Pos 7 /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH8_Pos 8 /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH9_Pos 9 /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH10_Pos 10 /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH11_Pos 11 /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH12_Pos 12 /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH13_Pos 13 /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH14_Pos 14 /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH15_Pos 15 /*!< External requests are enabled for channel */ + +/* Bit field masks: */ +#define DMA_REQMASKSET_CH0_Msk 0x00000001UL /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH1_Msk 0x00000002UL /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH2_Msk 0x00000004UL /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH3_Msk 0x00000008UL /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH4_Msk 0x00000010UL /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH5_Msk 0x00000020UL /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH6_Msk 0x00000040UL /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH7_Msk 0x00000080UL /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH8_Msk 0x00000100UL /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH9_Msk 0x00000200UL /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH10_Msk 0x00000400UL /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH11_Msk 0x00000800UL /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH12_Msk 0x00001000UL /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH13_Msk 0x00002000UL /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH14_Msk 0x00004000UL /*!< External requests are enabled for channel */ +#define DMA_REQMASKSET_CH15_Msk 0x00008000UL /*!< External requests are enabled for channel */ + +/*-- REQMASKCLR: Channel request mask clear ------------------------------------------------------------------*/ +typedef struct { + uint32_t CH0 :1; /*!< External requests are disabled for channel */ + uint32_t CH1 :1; /*!< External requests are disabled for channel */ + uint32_t CH2 :1; /*!< External requests are disabled for channel */ + uint32_t CH3 :1; /*!< External requests are disabled for channel */ + uint32_t CH4 :1; /*!< External requests are disabled for channel */ + uint32_t CH5 :1; /*!< External requests are disabled for channel */ + uint32_t CH6 :1; /*!< External requests are disabled for channel */ + uint32_t CH7 :1; /*!< External requests are disabled for channel */ + uint32_t CH8 :1; /*!< External requests are disabled for channel */ + uint32_t CH9 :1; /*!< External requests are disabled for channel */ + uint32_t CH10 :1; /*!< External requests are disabled for channel */ + uint32_t CH11 :1; /*!< External requests are disabled for channel */ + uint32_t CH12 :1; /*!< External requests are disabled for channel */ + uint32_t CH13 :1; /*!< External requests are disabled for channel */ + uint32_t CH14 :1; /*!< External requests are disabled for channel */ + uint32_t CH15 :1; /*!< External requests are disabled for channel */ +} _DMA_REQMASKCLR_bits; + +/* Bit field positions: */ +#define DMA_REQMASKCLR_CH0_Pos 0 /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH1_Pos 1 /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH2_Pos 2 /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH3_Pos 3 /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH4_Pos 4 /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH5_Pos 5 /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH6_Pos 6 /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH7_Pos 7 /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH8_Pos 8 /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH9_Pos 9 /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH10_Pos 10 /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH11_Pos 11 /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH12_Pos 12 /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH13_Pos 13 /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH14_Pos 14 /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH15_Pos 15 /*!< External requests are disabled for channel */ + +/* Bit field masks: */ +#define DMA_REQMASKCLR_CH0_Msk 0x00000001UL /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH1_Msk 0x00000002UL /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH2_Msk 0x00000004UL /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH3_Msk 0x00000008UL /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH4_Msk 0x00000010UL /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH5_Msk 0x00000020UL /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH6_Msk 0x00000040UL /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH7_Msk 0x00000080UL /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH8_Msk 0x00000100UL /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH9_Msk 0x00000200UL /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH10_Msk 0x00000400UL /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH11_Msk 0x00000800UL /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH12_Msk 0x00001000UL /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH13_Msk 0x00002000UL /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH14_Msk 0x00004000UL /*!< External requests are disabled for channel */ +#define DMA_REQMASKCLR_CH15_Msk 0x00008000UL /*!< External requests are disabled for channel */ + +/*-- ENSET: Channel enable set -------------------------------------------------------------------------------*/ +typedef struct { + uint32_t CH0 :1; /*!< Enable channel */ + uint32_t CH1 :1; /*!< Enable channel */ + uint32_t CH2 :1; /*!< Enable channel */ + uint32_t CH3 :1; /*!< Enable channel */ + uint32_t CH4 :1; /*!< Enable channel */ + uint32_t CH5 :1; /*!< Enable channel */ + uint32_t CH6 :1; /*!< Enable channel */ + uint32_t CH7 :1; /*!< Enable channel */ + uint32_t CH8 :1; /*!< Enable channel */ + uint32_t CH9 :1; /*!< Enable channel */ + uint32_t CH10 :1; /*!< Enable channel */ + uint32_t CH11 :1; /*!< Enable channel */ + uint32_t CH12 :1; /*!< Enable channel */ + uint32_t CH13 :1; /*!< Enable channel */ + uint32_t CH14 :1; /*!< Enable channel */ + uint32_t CH15 :1; /*!< Enable channel */ +} _DMA_ENSET_bits; + +/* Bit field positions: */ +#define DMA_ENSET_CH0_Pos 0 /*!< Enable channel */ +#define DMA_ENSET_CH1_Pos 1 /*!< Enable channel */ +#define DMA_ENSET_CH2_Pos 2 /*!< Enable channel */ +#define DMA_ENSET_CH3_Pos 3 /*!< Enable channel */ +#define DMA_ENSET_CH4_Pos 4 /*!< Enable channel */ +#define DMA_ENSET_CH5_Pos 5 /*!< Enable channel */ +#define DMA_ENSET_CH6_Pos 6 /*!< Enable channel */ +#define DMA_ENSET_CH7_Pos 7 /*!< Enable channel */ +#define DMA_ENSET_CH8_Pos 8 /*!< Enable channel */ +#define DMA_ENSET_CH9_Pos 9 /*!< Enable channel */ +#define DMA_ENSET_CH10_Pos 10 /*!< Enable channel */ +#define DMA_ENSET_CH11_Pos 11 /*!< Enable channel */ +#define DMA_ENSET_CH12_Pos 12 /*!< Enable channel */ +#define DMA_ENSET_CH13_Pos 13 /*!< Enable channel */ +#define DMA_ENSET_CH14_Pos 14 /*!< Enable channel */ +#define DMA_ENSET_CH15_Pos 15 /*!< Enable channel */ + +/* Bit field masks: */ +#define DMA_ENSET_CH0_Msk 0x00000001UL /*!< Enable channel */ +#define DMA_ENSET_CH1_Msk 0x00000002UL /*!< Enable channel */ +#define DMA_ENSET_CH2_Msk 0x00000004UL /*!< Enable channel */ +#define DMA_ENSET_CH3_Msk 0x00000008UL /*!< Enable channel */ +#define DMA_ENSET_CH4_Msk 0x00000010UL /*!< Enable channel */ +#define DMA_ENSET_CH5_Msk 0x00000020UL /*!< Enable channel */ +#define DMA_ENSET_CH6_Msk 0x00000040UL /*!< Enable channel */ +#define DMA_ENSET_CH7_Msk 0x00000080UL /*!< Enable channel */ +#define DMA_ENSET_CH8_Msk 0x00000100UL /*!< Enable channel */ +#define DMA_ENSET_CH9_Msk 0x00000200UL /*!< Enable channel */ +#define DMA_ENSET_CH10_Msk 0x00000400UL /*!< Enable channel */ +#define DMA_ENSET_CH11_Msk 0x00000800UL /*!< Enable channel */ +#define DMA_ENSET_CH12_Msk 0x00001000UL /*!< Enable channel */ +#define DMA_ENSET_CH13_Msk 0x00002000UL /*!< Enable channel */ +#define DMA_ENSET_CH14_Msk 0x00004000UL /*!< Enable channel */ +#define DMA_ENSET_CH15_Msk 0x00008000UL /*!< Enable channel */ + +/*-- ENCLR: Channel enable clear -----------------------------------------------------------------------------*/ +typedef struct { + uint32_t CH0 :1; /*!< Disable channel */ + uint32_t CH1 :1; /*!< Disable channel */ + uint32_t CH2 :1; /*!< Disable channel */ + uint32_t CH3 :1; /*!< Disable channel */ + uint32_t CH4 :1; /*!< Disable channel */ + uint32_t CH5 :1; /*!< Disable channel */ + uint32_t CH6 :1; /*!< Disable channel */ + uint32_t CH7 :1; /*!< Disable channel */ + uint32_t CH8 :1; /*!< Disable channel */ + uint32_t CH9 :1; /*!< Disable channel */ + uint32_t CH10 :1; /*!< Disable channel */ + uint32_t CH11 :1; /*!< Disable channel */ + uint32_t CH12 :1; /*!< Disable channel */ + uint32_t CH13 :1; /*!< Disable channel */ + uint32_t CH14 :1; /*!< Disable channel */ + uint32_t CH15 :1; /*!< Disable channel */ +} _DMA_ENCLR_bits; + +/* Bit field positions: */ +#define DMA_ENCLR_CH0_Pos 0 /*!< Disable channel */ +#define DMA_ENCLR_CH1_Pos 1 /*!< Disable channel */ +#define DMA_ENCLR_CH2_Pos 2 /*!< Disable channel */ +#define DMA_ENCLR_CH3_Pos 3 /*!< Disable channel */ +#define DMA_ENCLR_CH4_Pos 4 /*!< Disable channel */ +#define DMA_ENCLR_CH5_Pos 5 /*!< Disable channel */ +#define DMA_ENCLR_CH6_Pos 6 /*!< Disable channel */ +#define DMA_ENCLR_CH7_Pos 7 /*!< Disable channel */ +#define DMA_ENCLR_CH8_Pos 8 /*!< Disable channel */ +#define DMA_ENCLR_CH9_Pos 9 /*!< Disable channel */ +#define DMA_ENCLR_CH10_Pos 10 /*!< Disable channel */ +#define DMA_ENCLR_CH11_Pos 11 /*!< Disable channel */ +#define DMA_ENCLR_CH12_Pos 12 /*!< Disable channel */ +#define DMA_ENCLR_CH13_Pos 13 /*!< Disable channel */ +#define DMA_ENCLR_CH14_Pos 14 /*!< Disable channel */ +#define DMA_ENCLR_CH15_Pos 15 /*!< Disable channel */ + +/* Bit field masks: */ +#define DMA_ENCLR_CH0_Msk 0x00000001UL /*!< Disable channel */ +#define DMA_ENCLR_CH1_Msk 0x00000002UL /*!< Disable channel */ +#define DMA_ENCLR_CH2_Msk 0x00000004UL /*!< Disable channel */ +#define DMA_ENCLR_CH3_Msk 0x00000008UL /*!< Disable channel */ +#define DMA_ENCLR_CH4_Msk 0x00000010UL /*!< Disable channel */ +#define DMA_ENCLR_CH5_Msk 0x00000020UL /*!< Disable channel */ +#define DMA_ENCLR_CH6_Msk 0x00000040UL /*!< Disable channel */ +#define DMA_ENCLR_CH7_Msk 0x00000080UL /*!< Disable channel */ +#define DMA_ENCLR_CH8_Msk 0x00000100UL /*!< Disable channel */ +#define DMA_ENCLR_CH9_Msk 0x00000200UL /*!< Disable channel */ +#define DMA_ENCLR_CH10_Msk 0x00000400UL /*!< Disable channel */ +#define DMA_ENCLR_CH11_Msk 0x00000800UL /*!< Disable channel */ +#define DMA_ENCLR_CH12_Msk 0x00001000UL /*!< Disable channel */ +#define DMA_ENCLR_CH13_Msk 0x00002000UL /*!< Disable channel */ +#define DMA_ENCLR_CH14_Msk 0x00004000UL /*!< Disable channel */ +#define DMA_ENCLR_CH15_Msk 0x00008000UL /*!< Disable channel */ + +/*-- PRIALTSET: Channel primary-alternate set ----------------------------------------------------------------*/ +typedef struct { + uint32_t CH0 :1; /*!< Set primary / alternate channel control data structure */ + uint32_t CH1 :1; /*!< Set primary / alternate channel control data structure */ + uint32_t CH2 :1; /*!< Set primary / alternate channel control data structure */ + uint32_t CH3 :1; /*!< Set primary / alternate channel control data structure */ + uint32_t CH4 :1; /*!< Set primary / alternate channel control data structure */ + uint32_t CH5 :1; /*!< Set primary / alternate channel control data structure */ + uint32_t CH6 :1; /*!< Set primary / alternate channel control data structure */ + uint32_t CH7 :1; /*!< Set primary / alternate channel control data structure */ + uint32_t CH8 :1; /*!< Set primary / alternate channel control data structure */ + uint32_t CH9 :1; /*!< Set primary / alternate channel control data structure */ + uint32_t CH10 :1; /*!< Set primary / alternate channel control data structure */ + uint32_t CH11 :1; /*!< Set primary / alternate channel control data structure */ + uint32_t CH12 :1; /*!< Set primary / alternate channel control data structure */ + uint32_t CH13 :1; /*!< Set primary / alternate channel control data structure */ + uint32_t CH14 :1; /*!< Set primary / alternate channel control data structure */ + uint32_t CH15 :1; /*!< Set primary / alternate channel control data structure */ +} _DMA_PRIALTSET_bits; + +/* Bit field positions: */ +#define DMA_PRIALTSET_CH0_Pos 0 /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH1_Pos 1 /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH2_Pos 2 /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH3_Pos 3 /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH4_Pos 4 /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH5_Pos 5 /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH6_Pos 6 /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH7_Pos 7 /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH8_Pos 8 /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH9_Pos 9 /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH10_Pos 10 /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH11_Pos 11 /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH12_Pos 12 /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH13_Pos 13 /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH14_Pos 14 /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH15_Pos 15 /*!< Set primary / alternate channel control data structure */ + +/* Bit field masks: */ +#define DMA_PRIALTSET_CH0_Msk 0x00000001UL /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH1_Msk 0x00000002UL /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH2_Msk 0x00000004UL /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH3_Msk 0x00000008UL /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH4_Msk 0x00000010UL /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH5_Msk 0x00000020UL /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH6_Msk 0x00000040UL /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH7_Msk 0x00000080UL /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH8_Msk 0x00000100UL /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH9_Msk 0x00000200UL /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH10_Msk 0x00000400UL /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH11_Msk 0x00000800UL /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH12_Msk 0x00001000UL /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH13_Msk 0x00002000UL /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH14_Msk 0x00004000UL /*!< Set primary / alternate channel control data structure */ +#define DMA_PRIALTSET_CH15_Msk 0x00008000UL /*!< Set primary / alternate channel control data structure */ + +/*-- PRIALTCLR: Channel primary-alternate clear --------------------------------------------------------------*/ +typedef struct { + uint32_t CH0 :1; /*!< Clear primary / alternate channel control data structure */ + uint32_t CH1 :1; /*!< Clear primary / alternate channel control data structure */ + uint32_t CH2 :1; /*!< Clear primary / alternate channel control data structure */ + uint32_t CH3 :1; /*!< Clear primary / alternate channel control data structure */ + uint32_t CH4 :1; /*!< Clear primary / alternate channel control data structure */ + uint32_t CH5 :1; /*!< Clear primary / alternate channel control data structure */ + uint32_t CH6 :1; /*!< Clear primary / alternate channel control data structure */ + uint32_t CH7 :1; /*!< Clear primary / alternate channel control data structure */ + uint32_t CH8 :1; /*!< Clear primary / alternate channel control data structure */ + uint32_t CH9 :1; /*!< Clear primary / alternate channel control data structure */ + uint32_t CH10 :1; /*!< Clear primary / alternate channel control data structure */ + uint32_t CH11 :1; /*!< Clear primary / alternate channel control data structure */ + uint32_t CH12 :1; /*!< Clear primary / alternate channel control data structure */ + uint32_t CH13 :1; /*!< Clear primary / alternate channel control data structure */ + uint32_t CH14 :1; /*!< Clear primary / alternate channel control data structure */ + uint32_t CH15 :1; /*!< Clear primary / alternate channel control data structure */ +} _DMA_PRIALTCLR_bits; + +/* Bit field positions: */ +#define DMA_PRIALTCLR_CH0_Pos 0 /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH1_Pos 1 /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH2_Pos 2 /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH3_Pos 3 /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH4_Pos 4 /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH5_Pos 5 /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH6_Pos 6 /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH7_Pos 7 /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH8_Pos 8 /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH9_Pos 9 /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH10_Pos 10 /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH11_Pos 11 /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH12_Pos 12 /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH13_Pos 13 /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH14_Pos 14 /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH15_Pos 15 /*!< Clear primary / alternate channel control data structure */ + +/* Bit field masks: */ +#define DMA_PRIALTCLR_CH0_Msk 0x00000001UL /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH1_Msk 0x00000002UL /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH2_Msk 0x00000004UL /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH3_Msk 0x00000008UL /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH4_Msk 0x00000010UL /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH5_Msk 0x00000020UL /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH6_Msk 0x00000040UL /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH7_Msk 0x00000080UL /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH8_Msk 0x00000100UL /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH9_Msk 0x00000200UL /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH10_Msk 0x00000400UL /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH11_Msk 0x00000800UL /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH12_Msk 0x00001000UL /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH13_Msk 0x00002000UL /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH14_Msk 0x00004000UL /*!< Clear primary / alternate channel control data structure */ +#define DMA_PRIALTCLR_CH15_Msk 0x00008000UL /*!< Clear primary / alternate channel control data structure */ + +/*-- PRIORITYSET: Channel priority set -----------------------------------------------------------------------*/ +typedef struct { + uint32_t CH0 :1; /*!< Set the priority of channel */ + uint32_t CH1 :1; /*!< Set the priority of channel */ + uint32_t CH2 :1; /*!< Set the priority of channel */ + uint32_t CH3 :1; /*!< Set the priority of channel */ + uint32_t CH4 :1; /*!< Set the priority of channel */ + uint32_t CH5 :1; /*!< Set the priority of channel */ + uint32_t CH6 :1; /*!< Set the priority of channel */ + uint32_t CH7 :1; /*!< Set the priority of channel */ + uint32_t CH8 :1; /*!< Set the priority of channel */ + uint32_t CH9 :1; /*!< Set the priority of channel */ + uint32_t CH10 :1; /*!< Set the priority of channel */ + uint32_t CH11 :1; /*!< Set the priority of channel */ + uint32_t CH12 :1; /*!< Set the priority of channel */ + uint32_t CH13 :1; /*!< Set the priority of channel */ + uint32_t CH14 :1; /*!< Set the priority of channel */ + uint32_t CH15 :1; /*!< Set the priority of channel */ +} _DMA_PRIORITYSET_bits; + +/* Bit field positions: */ +#define DMA_PRIORITYSET_CH0_Pos 0 /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH1_Pos 1 /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH2_Pos 2 /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH3_Pos 3 /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH4_Pos 4 /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH5_Pos 5 /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH6_Pos 6 /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH7_Pos 7 /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH8_Pos 8 /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH9_Pos 9 /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH10_Pos 10 /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH11_Pos 11 /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH12_Pos 12 /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH13_Pos 13 /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH14_Pos 14 /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH15_Pos 15 /*!< Set the priority of channel */ + +/* Bit field masks: */ +#define DMA_PRIORITYSET_CH0_Msk 0x00000001UL /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH1_Msk 0x00000002UL /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH2_Msk 0x00000004UL /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH3_Msk 0x00000008UL /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH4_Msk 0x00000010UL /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH5_Msk 0x00000020UL /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH6_Msk 0x00000040UL /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH7_Msk 0x00000080UL /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH8_Msk 0x00000100UL /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH9_Msk 0x00000200UL /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH10_Msk 0x00000400UL /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH11_Msk 0x00000800UL /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH12_Msk 0x00001000UL /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH13_Msk 0x00002000UL /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH14_Msk 0x00004000UL /*!< Set the priority of channel */ +#define DMA_PRIORITYSET_CH15_Msk 0x00008000UL /*!< Set the priority of channel */ + +/*-- PRIORITYCLR: Channel priority clear ---------------------------------------------------------------------*/ +typedef struct { + uint32_t CH0 :1; /*!< Clear the priority */ + uint32_t CH1 :1; /*!< Clear the priority */ + uint32_t CH2 :1; /*!< Clear the priority */ + uint32_t CH3 :1; /*!< Clear the priority */ + uint32_t CH4 :1; /*!< Clear the priority */ + uint32_t CH5 :1; /*!< Clear the priority */ + uint32_t CH6 :1; /*!< Clear the priority */ + uint32_t CH7 :1; /*!< Clear the priority */ + uint32_t CH8 :1; /*!< Clear the priority */ + uint32_t CH9 :1; /*!< Clear the priority */ + uint32_t CH10 :1; /*!< Clear the priority */ + uint32_t CH11 :1; /*!< Clear the priority */ + uint32_t CH12 :1; /*!< Clear the priority */ + uint32_t CH13 :1; /*!< Clear the priority */ + uint32_t CH14 :1; /*!< Clear the priority */ + uint32_t CH15 :1; /*!< Clear the priority */ +} _DMA_PRIORITYCLR_bits; + +/* Bit field positions: */ +#define DMA_PRIORITYCLR_CH0_Pos 0 /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH1_Pos 1 /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH2_Pos 2 /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH3_Pos 3 /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH4_Pos 4 /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH5_Pos 5 /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH6_Pos 6 /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH7_Pos 7 /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH8_Pos 8 /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH9_Pos 9 /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH10_Pos 10 /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH11_Pos 11 /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH12_Pos 12 /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH13_Pos 13 /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH14_Pos 14 /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH15_Pos 15 /*!< Clear the priority */ + +/* Bit field masks: */ +#define DMA_PRIORITYCLR_CH0_Msk 0x00000001UL /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH1_Msk 0x00000002UL /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH2_Msk 0x00000004UL /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH3_Msk 0x00000008UL /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH4_Msk 0x00000010UL /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH5_Msk 0x00000020UL /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH6_Msk 0x00000040UL /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH7_Msk 0x00000080UL /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH8_Msk 0x00000100UL /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH9_Msk 0x00000200UL /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH10_Msk 0x00000400UL /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH11_Msk 0x00000800UL /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH12_Msk 0x00001000UL /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH13_Msk 0x00002000UL /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH14_Msk 0x00004000UL /*!< Clear the priority */ +#define DMA_PRIORITYCLR_CH15_Msk 0x00008000UL /*!< Clear the priority */ + +/*-- ERRCLR: Bus error register ------------------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :1; /*!< Indicate Error on bus AHB-Lite */ +} _DMA_ERRCLR_bits; + +/* Bit field positions: */ +#define DMA_ERRCLR_VAL_Pos 0 /*!< Indicate Error on bus AHB-Lite */ + +/* Bit field masks: */ +#define DMA_ERRCLR_VAL_Msk 0x00000001UL /*!< Indicate Error on bus AHB-Lite */ + +typedef struct { + union { /*!< Status DMA register */ + __I uint32_t STATUS; /*!< STATUS : type used for word access */ + __I _DMA_STATUS_bits STATUS_bit; /*!< STATUS_bit: structure used for bit access */ + }; + union { /*!< DMA configuration register */ + __O uint32_t CFG; /*!< CFG : type used for word access */ + __O _DMA_CFG_bits CFG_bit; /*!< CFG_bit: structure used for bit access */ + }; + union { /*!< Channel control data base pointer */ + __IO uint32_t BASEPTR; /*!< BASEPTR : type used for word access */ + __IO _DMA_BASEPTR_bits BASEPTR_bit; /*!< BASEPTR_bit: structure used for bit access */ + }; + union { /*!< Channel alternate control data base pointer */ + __I uint32_t ALTBASEPTR; /*!< ALTBASEPTR : type used for word access */ + __I _DMA_ALTBASEPTR_bits ALTBASEPTR_bit; /*!< ALTBASEPTR_bit: structure used for bit access */ + }; + union { /*!< Channel wait on request status */ + __I uint32_t WAITONREQ; /*!< WAITONREQ : type used for word access */ + __I _DMA_WAITONREQ_bits WAITONREQ_bit; /*!< WAITONREQ_bit: structure used for bit access */ + }; + union { /*!< Channel software request */ + __O uint32_t SWREQ; /*!< SWREQ : type used for word access */ + __O _DMA_SWREQ_bits SWREQ_bit; /*!< SWREQ_bit: structure used for bit access */ + }; + union { /*!< Channel useburst set */ + __IO uint32_t USEBURSTSET; /*!< USEBURSTSET : type used for word access */ + __IO _DMA_USEBURSTSET_bits USEBURSTSET_bit; /*!< USEBURSTSET_bit: structure used for bit access */ + }; + union { /*!< Channel useburst clear */ + __O uint32_t USEBURSTCLR; /*!< USEBURSTCLR : type used for word access */ + __O _DMA_USEBURSTCLR_bits USEBURSTCLR_bit; /*!< USEBURSTCLR_bit: structure used for bit access */ + }; + union { /*!< Channel request mask set */ + __IO uint32_t REQMASKSET; /*!< REQMASKSET : type used for word access */ + __IO _DMA_REQMASKSET_bits REQMASKSET_bit; /*!< REQMASKSET_bit: structure used for bit access */ + }; + union { /*!< Channel request mask clear */ + __O uint32_t REQMASKCLR; /*!< REQMASKCLR : type used for word access */ + __O _DMA_REQMASKCLR_bits REQMASKCLR_bit; /*!< REQMASKCLR_bit: structure used for bit access */ + }; + union { /*!< Channel enable set */ + __IO uint32_t ENSET; /*!< ENSET : type used for word access */ + __IO _DMA_ENSET_bits ENSET_bit; /*!< ENSET_bit: structure used for bit access */ + }; + union { /*!< Channel enable clear */ + __O uint32_t ENCLR; /*!< ENCLR : type used for word access */ + __O _DMA_ENCLR_bits ENCLR_bit; /*!< ENCLR_bit: structure used for bit access */ + }; + union { /*!< Channel primary-alternate set */ + __IO uint32_t PRIALTSET; /*!< PRIALTSET : type used for word access */ + __IO _DMA_PRIALTSET_bits PRIALTSET_bit; /*!< PRIALTSET_bit: structure used for bit access */ + }; + union { /*!< Channel primary-alternate clear */ + __O uint32_t PRIALTCLR; /*!< PRIALTCLR : type used for word access */ + __O _DMA_PRIALTCLR_bits PRIALTCLR_bit; /*!< PRIALTCLR_bit: structure used for bit access */ + }; + union { /*!< Channel priority set */ + __IO uint32_t PRIORITYSET; /*!< PRIORITYSET : type used for word access */ + __IO _DMA_PRIORITYSET_bits PRIORITYSET_bit; /*!< PRIORITYSET_bit: structure used for bit access */ + }; + union { /*!< Channel priority clear */ + __O uint32_t PRIORITYCLR; /*!< PRIORITYCLR : type used for word access */ + __O _DMA_PRIORITYCLR_bits PRIORITYCLR_bit; /*!< PRIORITYCLR_bit: structure used for bit access */ + }; + __IO uint32_t Reserved0[3]; + union { /*!< Bus error register */ + __IO uint32_t ERRCLR; /*!< ERRCLR : type used for word access */ + __IO _DMA_ERRCLR_bits ERRCLR_bit; /*!< ERRCLR_bit: structure used for bit access */ + }; +} DMA_TypeDef; + + +/******************************************************************************/ +/* MFLASH registers */ +/******************************************************************************/ + +/*-- ADDR: Address Register ----------------------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< Address value for flash operations */ +} _MFLASH_ADDR_bits; + +/* Bit field positions: */ +#define MFLASH_ADDR_VAL_Pos 0 /*!< Address value for flash operations */ + +/* Bit field masks: */ +#define MFLASH_ADDR_VAL_Msk 0xFFFFFFFFUL /*!< Address value for flash operations */ + +/*-- DATA: DATA: Data Register --------------------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< Data register value for flash operations */ +} _MFLASH_DATA_DATA_bits; + +/* Bit field positions: */ +#define MFLASH_DATA_DATA_VAL_Pos 0 /*!< Data register value for flash operations */ + +/* Bit field masks: */ +#define MFLASH_DATA_DATA_VAL_Msk 0xFFFFFFFFUL /*!< Data register value for flash operations */ + +/*-- CMD: Command Register -----------------------------------------------------------------------------------*/ +typedef struct { + uint32_t RD :1; /*!< Read enable command */ + uint32_t WR :1; /*!< Write enable command */ + uint32_t ERSEC :1; /*!< Erase sector enable command */ + uint32_t ERALL :1; /*!< Erase all enable command */ + uint32_t :4; /*!< RESERVED */ + uint32_t NVRON :1; /*!< NVR access bit */ + uint32_t :7; /*!< RESERVED */ + uint32_t KEY :16; /*!< Magic Key for flash access "C0DE" */ +} _MFLASH_CMD_bits; + +/* Bit field positions: */ +#define MFLASH_CMD_RD_Pos 0 /*!< Read enable command */ +#define MFLASH_CMD_WR_Pos 1 /*!< Write enable command */ +#define MFLASH_CMD_ERSEC_Pos 2 /*!< Erase sector enable command */ +#define MFLASH_CMD_ERALL_Pos 3 /*!< Erase all enable command */ +#define MFLASH_CMD_NVRON_Pos 8 /*!< NVR access bit */ +#define MFLASH_CMD_KEY_Pos 16 /*!< Magic Key for flash access "C0DE" */ + +/* Bit field masks: */ +#define MFLASH_CMD_RD_Msk 0x00000001UL /*!< Read enable command */ +#define MFLASH_CMD_WR_Msk 0x00000002UL /*!< Write enable command */ +#define MFLASH_CMD_ERSEC_Msk 0x00000004UL /*!< Erase sector enable command */ +#define MFLASH_CMD_ERALL_Msk 0x00000008UL /*!< Erase all enable command */ +#define MFLASH_CMD_NVRON_Msk 0x00000100UL /*!< NVR access bit */ +#define MFLASH_CMD_KEY_Msk 0xFFFF0000UL /*!< Magic Key for flash access "C0DE" */ + +/* Bit field enums: */ +typedef enum { + MFLASH_CMD_KEY_Access = 0xC0DEUL, /*!< magic Key for flash access */ +} MFLASH_CMD_KEY_Enum; + +/*-- STAT: Status Register -----------------------------------------------------------------------------------*/ +typedef struct { + uint32_t BUSY :1; /*!< Busy status bit when command is processing */ + uint32_t IRQF :1; /*!< IRQ Flag set when command done. Set by hardware only if IRQEN bit is set. */ +} _MFLASH_STAT_bits; + +/* Bit field positions: */ +#define MFLASH_STAT_BUSY_Pos 0 /*!< Busy status bit when command is processing */ +#define MFLASH_STAT_IRQF_Pos 1 /*!< IRQ Flag set when command done. Set by hardware only if IRQEN bit is set. */ + +/* Bit field masks: */ +#define MFLASH_STAT_BUSY_Msk 0x00000001UL /*!< Busy status bit when command is processing */ +#define MFLASH_STAT_IRQF_Msk 0x00000002UL /*!< IRQ Flag set when command done. Set by hardware only if IRQEN bit is set. */ + +/*-- CTRL: Control Register ----------------------------------------------------------------------------------*/ +typedef struct { + uint32_t PEN :1; /*!< Prefetch enable bit */ + uint32_t ICEN :1; /*!< I-Cache enable bit */ + uint32_t DCEN :1; /*!< D-Cache enable bit */ + uint32_t :1; /*!< RESERVED */ + uint32_t IRQEN :1; /*!< Interrupt enable bit */ + uint32_t :3; /*!< RESERVED */ + uint32_t IFLUSH :1; /*!< Flush I-Cache request bit */ + uint32_t DFLUSH :1; /*!< Flush D-Cache request bit */ + uint32_t :6; /*!< RESERVED */ + uint32_t LAT :4; /*!< Flash latency */ +} _MFLASH_CTRL_bits; + +/* Bit field positions: */ +#define MFLASH_CTRL_PEN_Pos 0 /*!< Prefetch enable bit */ +#define MFLASH_CTRL_ICEN_Pos 1 /*!< I-Cache enable bit */ +#define MFLASH_CTRL_DCEN_Pos 2 /*!< D-Cache enable bit */ +#define MFLASH_CTRL_IRQEN_Pos 4 /*!< Interrupt enable bit */ +#define MFLASH_CTRL_IFLUSH_Pos 8 /*!< Flush I-Cache request bit */ +#define MFLASH_CTRL_DFLUSH_Pos 9 /*!< Flush D-Cache request bit */ +#define MFLASH_CTRL_LAT_Pos 16 /*!< Flash latency */ + +/* Bit field masks: */ +#define MFLASH_CTRL_PEN_Msk 0x00000001UL /*!< Prefetch enable bit */ +#define MFLASH_CTRL_ICEN_Msk 0x00000002UL /*!< I-Cache enable bit */ +#define MFLASH_CTRL_DCEN_Msk 0x00000004UL /*!< D-Cache enable bit */ +#define MFLASH_CTRL_IRQEN_Msk 0x00000010UL /*!< Interrupt enable bit */ +#define MFLASH_CTRL_IFLUSH_Msk 0x00000100UL /*!< Flush I-Cache request bit */ +#define MFLASH_CTRL_DFLUSH_Msk 0x00000200UL /*!< Flush D-Cache request bit */ +#define MFLASH_CTRL_LAT_Msk 0x000F0000UL /*!< Flash latency */ + +/*-- ICSTAT: ICACHE Status Register --------------------------------------------------------------------------*/ +typedef struct { + uint32_t BUSY :1; /*!< Busy flag for I-Cache flush/test system */ +} _MFLASH_ICSTAT_bits; + +/* Bit field positions: */ +#define MFLASH_ICSTAT_BUSY_Pos 0 /*!< Busy flag for I-Cache flush/test system */ + +/* Bit field masks: */ +#define MFLASH_ICSTAT_BUSY_Msk 0x00000001UL /*!< Busy flag for I-Cache flush/test system */ + +/*-- DCSTAT: DCACHE Status Register --------------------------------------------------------------------------*/ +typedef struct { + uint32_t BUSY :1; /*!< Busy flag for D-Cache flush/test system */ +} _MFLASH_DCSTAT_bits; + +/* Bit field positions: */ +#define MFLASH_DCSTAT_BUSY_Pos 0 /*!< Busy flag for D-Cache flush/test system */ + +/* Bit field masks: */ +#define MFLASH_DCSTAT_BUSY_Msk 0x00000001UL /*!< Busy flag for D-Cache flush/test system */ + +/*-- BDIS: Boot Mode Disable register ------------------------------------------------------------------------*/ +typedef struct { + uint32_t BMDIS :1; /*!< Disable boot mode after system reset command */ +} _MFLASH_BDIS_bits; + +/* Bit field positions: */ +#define MFLASH_BDIS_BMDIS_Pos 0 /*!< Disable boot mode after system reset command */ + +/* Bit field masks: */ +#define MFLASH_BDIS_BMDIS_Msk 0x00000001UL /*!< Disable boot mode after system reset command */ + +//Cluster DATA: +typedef struct { + union { + /*!< Data Register */ + __IO uint32_t DATA; /*!< DATA : type used for word access */ + __IO _MFLASH_DATA_DATA_bits DATA_bit; /*!< DATA_bit: structure used for bit access */ + }; +} _MFLASH_DATA_TypeDef; +typedef struct { + union { /*!< Address Register */ + __IO uint32_t ADDR; /*!< ADDR : type used for word access */ + __IO _MFLASH_ADDR_bits ADDR_bit; /*!< ADDR_bit: structure used for bit access */ + }; + _MFLASH_DATA_TypeDef DATA[2]; + __IO uint32_t Reserved0[6]; + union { /*!< Command Register */ + __IO uint32_t CMD; /*!< CMD : type used for word access */ + __IO _MFLASH_CMD_bits CMD_bit; /*!< CMD_bit: structure used for bit access */ + }; + union { /*!< Status Register */ + __IO uint32_t STAT; /*!< STAT : type used for word access */ + __IO _MFLASH_STAT_bits STAT_bit; /*!< STAT_bit: structure used for bit access */ + }; + union { /*!< Control Register */ + __IO uint32_t CTRL; /*!< CTRL : type used for word access */ + __IO _MFLASH_CTRL_bits CTRL_bit; /*!< CTRL_bit: structure used for bit access */ + }; + __IO uint32_t Reserved1; + union { /*!< ICACHE Status Register */ + __I uint32_t ICSTAT; /*!< ICSTAT : type used for word access */ + __I _MFLASH_ICSTAT_bits ICSTAT_bit; /*!< ICSTAT_bit: structure used for bit access */ + }; + union { /*!< DCACHE Status Register */ + __I uint32_t DCSTAT; /*!< DCSTAT : type used for word access */ + __I _MFLASH_DCSTAT_bits DCSTAT_bit; /*!< DCSTAT_bit: structure used for bit access */ + }; + __IO uint32_t Reserved2[15]; + union { /*!< Boot Mode Disable register */ + __IO uint32_t BDIS; /*!< BDIS : type used for word access */ + __IO _MFLASH_BDIS_bits BDIS_bit; /*!< BDIS_bit: structure used for bit access */ + }; +} MFLASH_TypeDef; + + +/******************************************************************************/ +/* QEP registers */ +/******************************************************************************/ + +/*-- QPOSCNT: Position Counter register ----------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< */ +} _QEP_QPOSCNT_bits; + +/* Bit field positions: */ +#define QEP_QPOSCNT_VAL_Pos 0 /*!< */ + +/* Bit field masks: */ +#define QEP_QPOSCNT_VAL_Msk 0xFFFFFFFFUL /*!< */ + +/*-- QPOSINIT: Position Counter Initialization register ------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< */ +} _QEP_QPOSINIT_bits; + +/* Bit field positions: */ +#define QEP_QPOSINIT_VAL_Pos 0 /*!< */ + +/* Bit field masks: */ +#define QEP_QPOSINIT_VAL_Msk 0xFFFFFFFFUL /*!< */ + +/*-- QPOSMAX: Maximum Position Count register ----------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< */ +} _QEP_QPOSMAX_bits; + +/* Bit field positions: */ +#define QEP_QPOSMAX_VAL_Pos 0 /*!< */ + +/* Bit field masks: */ +#define QEP_QPOSMAX_VAL_Msk 0xFFFFFFFFUL /*!< */ + +/*-- QPOSCMP: Position-compare register ----------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< */ +} _QEP_QPOSCMP_bits; + +/* Bit field positions: */ +#define QEP_QPOSCMP_VAL_Pos 0 /*!< */ + +/* Bit field masks: */ +#define QEP_QPOSCMP_VAL_Msk 0xFFFFFFFFUL /*!< */ + +/*-- QPOSILAT: Index Position Latch register -----------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< */ +} _QEP_QPOSILAT_bits; + +/* Bit field positions: */ +#define QEP_QPOSILAT_VAL_Pos 0 /*!< */ + +/* Bit field masks: */ +#define QEP_QPOSILAT_VAL_Msk 0xFFFFFFFFUL /*!< */ + +/*-- QPOSSLAT: Strobe Position Latch register ----------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< */ +} _QEP_QPOSSLAT_bits; + +/* Bit field positions: */ +#define QEP_QPOSSLAT_VAL_Pos 0 /*!< */ + +/* Bit field masks: */ +#define QEP_QPOSSLAT_VAL_Msk 0xFFFFFFFFUL /*!< */ + +/*-- QPOSLAT: Position Counter Latch register ----------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< */ +} _QEP_QPOSLAT_bits; + +/* Bit field positions: */ +#define QEP_QPOSLAT_VAL_Pos 0 /*!< */ + +/* Bit field masks: */ +#define QEP_QPOSLAT_VAL_Msk 0xFFFFFFFFUL /*!< */ + +/*-- QUTMR: Unit Timer register ------------------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< */ +} _QEP_QUTMR_bits; + +/* Bit field positions: */ +#define QEP_QUTMR_VAL_Pos 0 /*!< */ + +/* Bit field masks: */ +#define QEP_QUTMR_VAL_Msk 0xFFFFFFFFUL /*!< */ + +/*-- QUPRD: Unit Period register -----------------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< */ +} _QEP_QUPRD_bits; + +/* Bit field positions: */ +#define QEP_QUPRD_VAL_Pos 0 /*!< */ + +/* Bit field masks: */ +#define QEP_QUPRD_VAL_Msk 0xFFFFFFFFUL /*!< */ + +/*-- QWDTMR: Watchdog Timer register -------------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< */ +} _QEP_QWDTMR_bits; + +/* Bit field positions: */ +#define QEP_QWDTMR_VAL_Pos 0 /*!< */ + +/* Bit field masks: */ +#define QEP_QWDTMR_VAL_Msk 0xFFFFFFFFUL /*!< */ + +/*-- QWDPRD: Watchdog Period register ------------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< */ +} _QEP_QWDPRD_bits; + +/* Bit field positions: */ +#define QEP_QWDPRD_VAL_Pos 0 /*!< */ + +/* Bit field masks: */ +#define QEP_QWDPRD_VAL_Msk 0xFFFFFFFFUL /*!< */ + +/*-- QDECCTL: Decoder Control register -----------------------------------------------------------------------*/ +typedef struct { + uint32_t :5; /*!< RESERVED */ + uint32_t QSP :1; /*!< QEPS input polarity */ + uint32_t QIP :1; /*!< QEPI input polarity */ + uint32_t QBP :1; /*!< QEPB input polarity */ + uint32_t QAP :1; /*!< QEPA input polarity */ + uint32_t IGATE :1; /*!< Index pulse gating option */ + uint32_t SWAP :1; /*!< Swap quadrature clock inputs */ + uint32_t XCR :1; /*!< External clock rate */ + uint32_t SPSEL :1; /*!< Sync output pin selection */ + uint32_t SOEN :1; /*!< Sync output-enable */ + uint32_t QSRC :2; /*!< Position-counter source selection */ +} _QEP_QDECCTL_bits; + +/* Bit field positions: */ +#define QEP_QDECCTL_QSP_Pos 5 /*!< QEPS input polarity */ +#define QEP_QDECCTL_QIP_Pos 6 /*!< QEPI input polarity */ +#define QEP_QDECCTL_QBP_Pos 7 /*!< QEPB input polarity */ +#define QEP_QDECCTL_QAP_Pos 8 /*!< QEPA input polarity */ +#define QEP_QDECCTL_IGATE_Pos 9 /*!< Index pulse gating option */ +#define QEP_QDECCTL_SWAP_Pos 10 /*!< Swap quadrature clock inputs */ +#define QEP_QDECCTL_XCR_Pos 11 /*!< External clock rate */ +#define QEP_QDECCTL_SPSEL_Pos 12 /*!< Sync output pin selection */ +#define QEP_QDECCTL_SOEN_Pos 13 /*!< Sync output-enable */ +#define QEP_QDECCTL_QSRC_Pos 14 /*!< Position-counter source selection */ + +/* Bit field masks: */ +#define QEP_QDECCTL_QSP_Msk 0x00000020UL /*!< QEPS input polarity */ +#define QEP_QDECCTL_QIP_Msk 0x00000040UL /*!< QEPI input polarity */ +#define QEP_QDECCTL_QBP_Msk 0x00000080UL /*!< QEPB input polarity */ +#define QEP_QDECCTL_QAP_Msk 0x00000100UL /*!< QEPA input polarity */ +#define QEP_QDECCTL_IGATE_Msk 0x00000200UL /*!< Index pulse gating option */ +#define QEP_QDECCTL_SWAP_Msk 0x00000400UL /*!< Swap quadrature clock inputs */ +#define QEP_QDECCTL_XCR_Msk 0x00000800UL /*!< External clock rate */ +#define QEP_QDECCTL_SPSEL_Msk 0x00001000UL /*!< Sync output pin selection */ +#define QEP_QDECCTL_SOEN_Msk 0x00002000UL /*!< Sync output-enable */ +#define QEP_QDECCTL_QSRC_Msk 0x0000C000UL /*!< Position-counter source selection */ + +/* Bit field enums: */ +typedef enum { + QEP_QDECCTL_QSRC_Quad = 0x0UL, /*!< quadrature mode */ + QEP_QDECCTL_QSRC_CountDir = 0x1UL, /*!< count/direction mode */ + QEP_QDECCTL_QSRC_Up = 0x2UL, /*!< count up */ + QEP_QDECCTL_QSRC_Down = 0x3UL, /*!< count down */ +} QEP_QDECCTL_QSRC_Enum; + +/*-- QEPCTL: Control register --------------------------------------------------------------------------------*/ +typedef struct { + uint32_t WDE :1; /*!< QEP watchdog enable */ + uint32_t UTE :1; /*!< QEP unit timer enable */ + uint32_t QCLM :1; /*!< QEP capture latch mode */ + uint32_t QPEN :1; /*!< Quadrature position counter enable/software reset */ + uint32_t IEL :2; /*!< Index event latch of position counter (software index marker) */ + uint32_t SEL :1; /*!< Strobe event latch of position counter */ + uint32_t SWI :1; /*!< Software initialization of position counter */ + uint32_t IEI :2; /*!< Index event initialization of position counter */ + uint32_t SEI :2; /*!< Strobe event initialization of position counter */ + uint32_t PCRM :2; /*!< Position counter reset mode */ + uint32_t FREESOFT :2; /*!< Emulation Control Bits */ +} _QEP_QEPCTL_bits; + +/* Bit field positions: */ +#define QEP_QEPCTL_WDE_Pos 0 /*!< QEP watchdog enable */ +#define QEP_QEPCTL_UTE_Pos 1 /*!< QEP unit timer enable */ +#define QEP_QEPCTL_QCLM_Pos 2 /*!< QEP capture latch mode */ +#define QEP_QEPCTL_QPEN_Pos 3 /*!< Quadrature position counter enable/software reset */ +#define QEP_QEPCTL_IEL_Pos 4 /*!< Index event latch of position counter (software index marker) */ +#define QEP_QEPCTL_SEL_Pos 6 /*!< Strobe event latch of position counter */ +#define QEP_QEPCTL_SWI_Pos 7 /*!< Software initialization of position counter */ +#define QEP_QEPCTL_IEI_Pos 8 /*!< Index event initialization of position counter */ +#define QEP_QEPCTL_SEI_Pos 10 /*!< Strobe event initialization of position counter */ +#define QEP_QEPCTL_PCRM_Pos 12 /*!< Position counter reset mode */ +#define QEP_QEPCTL_FREESOFT_Pos 14 /*!< Emulation Control Bits */ + +/* Bit field masks: */ +#define QEP_QEPCTL_WDE_Msk 0x00000001UL /*!< QEP watchdog enable */ +#define QEP_QEPCTL_UTE_Msk 0x00000002UL /*!< QEP unit timer enable */ +#define QEP_QEPCTL_QCLM_Msk 0x00000004UL /*!< QEP capture latch mode */ +#define QEP_QEPCTL_QPEN_Msk 0x00000008UL /*!< Quadrature position counter enable/software reset */ +#define QEP_QEPCTL_IEL_Msk 0x00000030UL /*!< Index event latch of position counter (software index marker) */ +#define QEP_QEPCTL_SEL_Msk 0x00000040UL /*!< Strobe event latch of position counter */ +#define QEP_QEPCTL_SWI_Msk 0x00000080UL /*!< Software initialization of position counter */ +#define QEP_QEPCTL_IEI_Msk 0x00000300UL /*!< Index event initialization of position counter */ +#define QEP_QEPCTL_SEI_Msk 0x00000C00UL /*!< Strobe event initialization of position counter */ +#define QEP_QEPCTL_PCRM_Msk 0x00003000UL /*!< Position counter reset mode */ +#define QEP_QEPCTL_FREESOFT_Msk 0x0000C000UL /*!< Emulation Control Bits */ + +/* Bit field enums: */ +typedef enum { + QEP_QEPCTL_IEL_NoLatch = 0x0UL, /*!< no position counter latch */ + QEP_QEPCTL_IEL_IndPos = 0x1UL, /*!< latch on index signal posedge */ + QEP_QEPCTL_IEL_IndNeg = 0x2UL, /*!< latch on index signal negedge */ + QEP_QEPCTL_IEL_IndMark = 0x3UL, /*!< latch on index marker */ +} QEP_QEPCTL_IEL_Enum; + +typedef enum { + QEP_QEPCTL_IEI_NoInit = 0x0UL, /*!< no initialization */ + QEP_QEPCTL_IEI_QEPIPos = 0x2UL, /*!< init on posedge QEPI */ + QEP_QEPCTL_IEI_QEPINeg = 0x3UL, /*!< init on negedge QEPI */ +} QEP_QEPCTL_IEI_Enum; + +typedef enum { + QEP_QEPCTL_SEI_NoInit = 0x0UL, /*!< no initialization */ + QEP_QEPCTL_SEI_QEPSPos = 0x2UL, /*!< init on posedge QEPI */ + QEP_QEPCTL_SEI_QEPSDir = 0x3UL, /*!< init depends on direction - on posedge if direction is up, on negedge if direction is down */ +} QEP_QEPCTL_SEI_Enum; + +typedef enum { + QEP_QEPCTL_PCRM_Ind = 0x0UL, /*!< reset on index */ + QEP_QEPCTL_PCRM_PosMax = 0x1UL, /*!< reset on max position count */ + QEP_QEPCTL_PCRM_FirstInd = 0x2UL, /*!< reset on the first index */ + QEP_QEPCTL_PCRM_Time = 0x3UL, /*!< reset on time counter */ +} QEP_QEPCTL_PCRM_Enum; + +typedef enum { + QEP_QEPCTL_FREESOFT_Stop = 0x0UL, /*!< counters are blocked */ + QEP_QEPCTL_FREESOFT_StopAtOvf = 0x1UL, /*!< stop after overflow */ + QEP_QEPCTL_FREESOFT_Free = 0x2UL, /*!< no count stop in debug mode */ +} QEP_QEPCTL_FREESOFT_Enum; + +/*-- QCAPCTL: Capture Control register -----------------------------------------------------------------------*/ +typedef struct { + uint32_t UPPS :4; /*!< Unit position event prescaler */ + uint32_t CCPS :3; /*!< QEP capture timer clock prescaler */ + uint32_t SELEVENT :1; /*!< Reset timer control */ + uint32_t :7; /*!< RESERVED */ + uint32_t CEN :1; /*!< Enable eQEP capture */ + uint32_t EPSLD :1; /*!< Enhanced prescalers load */ +} _QEP_QCAPCTL_bits; + +/* Bit field positions: */ +#define QEP_QCAPCTL_UPPS_Pos 0 /*!< Unit position event prescaler */ +#define QEP_QCAPCTL_CCPS_Pos 4 /*!< QEP capture timer clock prescaler */ +#define QEP_QCAPCTL_SELEVENT_Pos 7 /*!< Reset timer control */ +#define QEP_QCAPCTL_CEN_Pos 15 /*!< Enable eQEP capture */ +#define QEP_QCAPCTL_EPSLD_Pos 16 /*!< Enhanced prescalers load */ + +/* Bit field masks: */ +#define QEP_QCAPCTL_UPPS_Msk 0x0000000FUL /*!< Unit position event prescaler */ +#define QEP_QCAPCTL_CCPS_Msk 0x00000070UL /*!< QEP capture timer clock prescaler */ +#define QEP_QCAPCTL_SELEVENT_Msk 0x00000080UL /*!< Reset timer control */ +#define QEP_QCAPCTL_CEN_Msk 0x00008000UL /*!< Enable eQEP capture */ +#define QEP_QCAPCTL_EPSLD_Msk 0x00010000UL /*!< Enhanced prescalers load */ + +/* Bit field enums: */ +typedef enum { + QEP_QCAPCTL_UPPS_Disable = 0x0UL, /*!< quad signal not divided */ + QEP_QCAPCTL_UPPS_Div2 = 0x1UL, /*!< quad signal divided by 2 */ + QEP_QCAPCTL_UPPS_Div4 = 0x2UL, /*!< quad signal divided by 4 */ + QEP_QCAPCTL_UPPS_Div8 = 0x3UL, /*!< quad signal divided by 8 */ + QEP_QCAPCTL_UPPS_Div16 = 0x4UL, /*!< quad signal divided by 16 */ + QEP_QCAPCTL_UPPS_Div32 = 0x5UL, /*!< quad signal divided by 32 */ + QEP_QCAPCTL_UPPS_Div64 = 0x6UL, /*!< quad signal divided by 64 */ + QEP_QCAPCTL_UPPS_Div128 = 0x7UL, /*!< quad signal divided by 128 */ + QEP_QCAPCTL_UPPS_Div256 = 0x8UL, /*!< quad signal divided by 256 */ + QEP_QCAPCTL_UPPS_Div512 = 0x9UL, /*!< quad signal divided by 512 */ + QEP_QCAPCTL_UPPS_Div1024 = 0xAUL, /*!< quad signal divided by 1024 */ + QEP_QCAPCTL_UPPS_Div2048 = 0xBUL, /*!< quad signal divided by 2048 */ +} QEP_QCAPCTL_UPPS_Enum; + +typedef enum { + QEP_QCAPCTL_CCPS_Disable = 0x0UL, /*!< no divider */ + QEP_QCAPCTL_CCPS_Div2 = 0x1UL, /*!< sysclk divided by 2 */ + QEP_QCAPCTL_CCPS_Div4 = 0x2UL, /*!< sysclk divided by 4 */ + QEP_QCAPCTL_CCPS_Div8 = 0x3UL, /*!< sysclk divided by 8 */ + QEP_QCAPCTL_CCPS_Div16 = 0x4UL, /*!< sysclk divided by 16 */ + QEP_QCAPCTL_CCPS_Div32 = 0x5UL, /*!< sysclk divided by 32 */ + QEP_QCAPCTL_CCPS_Div64 = 0x6UL, /*!< sysclk divided by 64 */ + QEP_QCAPCTL_CCPS_Div128 = 0x7UL, /*!< sysclk divided by 128 */ +} QEP_QCAPCTL_CCPS_Enum; + +/*-- QPOSCTL: Position-compare Control register --------------------------------------------------------------*/ +typedef struct { + uint32_t PCSPW :12; /*!< Select-position-compare sync output pulse width */ + uint32_t PCE :1; /*!< Position-compare enable/disable */ + uint32_t PCPOL :1; /*!< Polarity of sync output */ + uint32_t PCLOAD :1; /*!< Position-compare shadow load mode */ + uint32_t PCSHDW :1; /*!< Position-compare shadow enable */ +} _QEP_QPOSCTL_bits; + +/* Bit field positions: */ +#define QEP_QPOSCTL_PCSPW_Pos 0 /*!< Select-position-compare sync output pulse width */ +#define QEP_QPOSCTL_PCE_Pos 12 /*!< Position-compare enable/disable */ +#define QEP_QPOSCTL_PCPOL_Pos 13 /*!< Polarity of sync output */ +#define QEP_QPOSCTL_PCLOAD_Pos 14 /*!< Position-compare shadow load mode */ +#define QEP_QPOSCTL_PCSHDW_Pos 15 /*!< Position-compare shadow enable */ + +/* Bit field masks: */ +#define QEP_QPOSCTL_PCSPW_Msk 0x00000FFFUL /*!< Select-position-compare sync output pulse width */ +#define QEP_QPOSCTL_PCE_Msk 0x00001000UL /*!< Position-compare enable/disable */ +#define QEP_QPOSCTL_PCPOL_Msk 0x00002000UL /*!< Polarity of sync output */ +#define QEP_QPOSCTL_PCLOAD_Msk 0x00004000UL /*!< Position-compare shadow load mode */ +#define QEP_QPOSCTL_PCSHDW_Msk 0x00008000UL /*!< Position-compare shadow enable */ + +/*-- QEINT: Interrupt Enable register ------------------------------------------------------------------------*/ +typedef struct { + uint32_t :1; /*!< RESERVED */ + uint32_t PCE :1; /*!< Position counter error interrupt enable */ + uint32_t QPE :1; /*!< Quadrature phase error interrupt enable */ + uint32_t QDC :1; /*!< Quadrature direction change interrupt enable */ + uint32_t WTO :1; /*!< Watchdog time out interrupt enable */ + uint32_t PCU :1; /*!< Position counter underflow interrupt enable */ + uint32_t PCO :1; /*!< Position counter overflow interrupt enable */ + uint32_t PCR :1; /*!< Position-compare ready interrupt enable */ + uint32_t PCM :1; /*!< Position-compare match interrupt enable */ + uint32_t SEL :1; /*!< Strobe event latch interrupt enable */ + uint32_t IEL :1; /*!< Index event latch interrupt enable */ + uint32_t UTO :1; /*!< Unit time out interrupt enable */ +} _QEP_QEINT_bits; + +/* Bit field positions: */ +#define QEP_QEINT_PCE_Pos 1 /*!< Position counter error interrupt enable */ +#define QEP_QEINT_QPE_Pos 2 /*!< Quadrature phase error interrupt enable */ +#define QEP_QEINT_QDC_Pos 3 /*!< Quadrature direction change interrupt enable */ +#define QEP_QEINT_WTO_Pos 4 /*!< Watchdog time out interrupt enable */ +#define QEP_QEINT_PCU_Pos 5 /*!< Position counter underflow interrupt enable */ +#define QEP_QEINT_PCO_Pos 6 /*!< Position counter overflow interrupt enable */ +#define QEP_QEINT_PCR_Pos 7 /*!< Position-compare ready interrupt enable */ +#define QEP_QEINT_PCM_Pos 8 /*!< Position-compare match interrupt enable */ +#define QEP_QEINT_SEL_Pos 9 /*!< Strobe event latch interrupt enable */ +#define QEP_QEINT_IEL_Pos 10 /*!< Index event latch interrupt enable */ +#define QEP_QEINT_UTO_Pos 11 /*!< Unit time out interrupt enable */ + +/* Bit field masks: */ +#define QEP_QEINT_PCE_Msk 0x00000002UL /*!< Position counter error interrupt enable */ +#define QEP_QEINT_QPE_Msk 0x00000004UL /*!< Quadrature phase error interrupt enable */ +#define QEP_QEINT_QDC_Msk 0x00000008UL /*!< Quadrature direction change interrupt enable */ +#define QEP_QEINT_WTO_Msk 0x00000010UL /*!< Watchdog time out interrupt enable */ +#define QEP_QEINT_PCU_Msk 0x00000020UL /*!< Position counter underflow interrupt enable */ +#define QEP_QEINT_PCO_Msk 0x00000040UL /*!< Position counter overflow interrupt enable */ +#define QEP_QEINT_PCR_Msk 0x00000080UL /*!< Position-compare ready interrupt enable */ +#define QEP_QEINT_PCM_Msk 0x00000100UL /*!< Position-compare match interrupt enable */ +#define QEP_QEINT_SEL_Msk 0x00000200UL /*!< Strobe event latch interrupt enable */ +#define QEP_QEINT_IEL_Msk 0x00000400UL /*!< Index event latch interrupt enable */ +#define QEP_QEINT_UTO_Msk 0x00000800UL /*!< Unit time out interrupt enable */ + +/*-- QFLG: Interrupt Flag register ---------------------------------------------------------------------------*/ +typedef struct { + uint32_t INT :1; /*!< Global interrupt status flag */ + uint32_t PCE :1; /*!< Position counter error interrupt flag */ + uint32_t QPE :1; /*!< Quadrature phase error interrupt flag */ + uint32_t QDC :1; /*!< Quadrature direction change interrupt flag */ + uint32_t WTO :1; /*!< Watchdog timeout interrupt flag */ + uint32_t PCU :1; /*!< Position counter underflow interrupt flag */ + uint32_t PCO :1; /*!< Position counter overflow interrupt flag */ + uint32_t PCR :1; /*!< Position-compare ready interrupt flag */ + uint32_t PCM :1; /*!< QEP compare match event interrupt flag */ + uint32_t SEL :1; /*!< Strobe event latch interrupt flag + */ + uint32_t IEL :1; /*!< Index event latch interrupt flag */ + uint32_t UTO :1; /*!< Unit time out interrupt flag */ + uint32_t :4; /*!< RESERVED */ + uint32_t QFLGLAT :12; /*!< Latches QFLG[11:0] on every QPOSCNT read */ +} _QEP_QFLG_bits; + +/* Bit field positions: */ +#define QEP_QFLG_INT_Pos 0 /*!< Global interrupt status flag */ +#define QEP_QFLG_PCE_Pos 1 /*!< Position counter error interrupt flag */ +#define QEP_QFLG_QPE_Pos 2 /*!< Quadrature phase error interrupt flag */ +#define QEP_QFLG_QDC_Pos 3 /*!< Quadrature direction change interrupt flag */ +#define QEP_QFLG_WTO_Pos 4 /*!< Watchdog timeout interrupt flag */ +#define QEP_QFLG_PCU_Pos 5 /*!< Position counter underflow interrupt flag */ +#define QEP_QFLG_PCO_Pos 6 /*!< Position counter overflow interrupt flag */ +#define QEP_QFLG_PCR_Pos 7 /*!< Position-compare ready interrupt flag */ +#define QEP_QFLG_PCM_Pos 8 /*!< QEP compare match event interrupt flag */ +#define QEP_QFLG_SEL_Pos 9 /*!< Strobe event latch interrupt flag + */ +#define QEP_QFLG_IEL_Pos 10 /*!< Index event latch interrupt flag */ +#define QEP_QFLG_UTO_Pos 11 /*!< Unit time out interrupt flag */ +#define QEP_QFLG_QFLGLAT_Pos 16 /*!< Latches QFLG[11:0] on every QPOSCNT read */ + +/* Bit field masks: */ +#define QEP_QFLG_INT_Msk 0x00000001UL /*!< Global interrupt status flag */ +#define QEP_QFLG_PCE_Msk 0x00000002UL /*!< Position counter error interrupt flag */ +#define QEP_QFLG_QPE_Msk 0x00000004UL /*!< Quadrature phase error interrupt flag */ +#define QEP_QFLG_QDC_Msk 0x00000008UL /*!< Quadrature direction change interrupt flag */ +#define QEP_QFLG_WTO_Msk 0x00000010UL /*!< Watchdog timeout interrupt flag */ +#define QEP_QFLG_PCU_Msk 0x00000020UL /*!< Position counter underflow interrupt flag */ +#define QEP_QFLG_PCO_Msk 0x00000040UL /*!< Position counter overflow interrupt flag */ +#define QEP_QFLG_PCR_Msk 0x00000080UL /*!< Position-compare ready interrupt flag */ +#define QEP_QFLG_PCM_Msk 0x00000100UL /*!< QEP compare match event interrupt flag */ +#define QEP_QFLG_SEL_Msk 0x00000200UL /*!< Strobe event latch interrupt flag + */ +#define QEP_QFLG_IEL_Msk 0x00000400UL /*!< Index event latch interrupt flag */ +#define QEP_QFLG_UTO_Msk 0x00000800UL /*!< Unit time out interrupt flag */ +#define QEP_QFLG_QFLGLAT_Msk 0x0FFF0000UL /*!< Latches QFLG[11:0] on every QPOSCNT read */ + +/*-- QCLR: Interrupt Clear register --------------------------------------------------------------------------*/ +typedef struct { + uint32_t INT :1; /*!< Global interrupt clear flag */ + uint32_t PCE :1; /*!< Clear position counter error interrupt flag */ + uint32_t QPE :1; /*!< Clear quadrature phase error interrupt flag */ + uint32_t QDC :1; /*!< Clear quadrature direction change interrupt flag */ + uint32_t WTO :1; /*!< Clear watchdog timeout interrupt flag */ + uint32_t PCU :1; /*!< Clear position counter underflow interrupt flag */ + uint32_t PCO :1; /*!< Clear position counter overflow interrupt flag */ + uint32_t PCR :1; /*!< Clear position-compare ready interrupt flag */ + uint32_t PCM :1; /*!< Clear eQEP compare match event interrupt flag */ + uint32_t SEL :1; /*!< Clear strobe event latch interrupt flag */ + uint32_t IEL :1; /*!< Clear index event latch interrupt flag */ + uint32_t UTO :1; /*!< Clear unit time out interrupt flag */ +} _QEP_QCLR_bits; + +/* Bit field positions: */ +#define QEP_QCLR_INT_Pos 0 /*!< Global interrupt clear flag */ +#define QEP_QCLR_PCE_Pos 1 /*!< Clear position counter error interrupt flag */ +#define QEP_QCLR_QPE_Pos 2 /*!< Clear quadrature phase error interrupt flag */ +#define QEP_QCLR_QDC_Pos 3 /*!< Clear quadrature direction change interrupt flag */ +#define QEP_QCLR_WTO_Pos 4 /*!< Clear watchdog timeout interrupt flag */ +#define QEP_QCLR_PCU_Pos 5 /*!< Clear position counter underflow interrupt flag */ +#define QEP_QCLR_PCO_Pos 6 /*!< Clear position counter overflow interrupt flag */ +#define QEP_QCLR_PCR_Pos 7 /*!< Clear position-compare ready interrupt flag */ +#define QEP_QCLR_PCM_Pos 8 /*!< Clear eQEP compare match event interrupt flag */ +#define QEP_QCLR_SEL_Pos 9 /*!< Clear strobe event latch interrupt flag */ +#define QEP_QCLR_IEL_Pos 10 /*!< Clear index event latch interrupt flag */ +#define QEP_QCLR_UTO_Pos 11 /*!< Clear unit time out interrupt flag */ + +/* Bit field masks: */ +#define QEP_QCLR_INT_Msk 0x00000001UL /*!< Global interrupt clear flag */ +#define QEP_QCLR_PCE_Msk 0x00000002UL /*!< Clear position counter error interrupt flag */ +#define QEP_QCLR_QPE_Msk 0x00000004UL /*!< Clear quadrature phase error interrupt flag */ +#define QEP_QCLR_QDC_Msk 0x00000008UL /*!< Clear quadrature direction change interrupt flag */ +#define QEP_QCLR_WTO_Msk 0x00000010UL /*!< Clear watchdog timeout interrupt flag */ +#define QEP_QCLR_PCU_Msk 0x00000020UL /*!< Clear position counter underflow interrupt flag */ +#define QEP_QCLR_PCO_Msk 0x00000040UL /*!< Clear position counter overflow interrupt flag */ +#define QEP_QCLR_PCR_Msk 0x00000080UL /*!< Clear position-compare ready interrupt flag */ +#define QEP_QCLR_PCM_Msk 0x00000100UL /*!< Clear eQEP compare match event interrupt flag */ +#define QEP_QCLR_SEL_Msk 0x00000200UL /*!< Clear strobe event latch interrupt flag */ +#define QEP_QCLR_IEL_Msk 0x00000400UL /*!< Clear index event latch interrupt flag */ +#define QEP_QCLR_UTO_Msk 0x00000800UL /*!< Clear unit time out interrupt flag */ + +/*-- QFRC: Interrupt Force register --------------------------------------------------------------------------*/ +typedef struct { + uint32_t :1; /*!< RESERVED */ + uint32_t PCE :1; /*!< Force position counter error interrupt */ + uint32_t QPE :1; /*!< Force quadrature phase error interrupt */ + uint32_t QDC :1; /*!< Force quadrature direction change interrupt */ + uint32_t WTO :1; /*!< Force watchdog time out interrupt */ + uint32_t PCU :1; /*!< Force position counter underflow interrupt */ + uint32_t PCO :1; /*!< Force position counter overflow interrupt */ + uint32_t PCR :1; /*!< Force position-compare ready interrupt */ + uint32_t PCM :1; /*!< Force position-compare match interrupt */ + uint32_t SEL :1; /*!< Force strobe event latch interrupt */ + uint32_t IEL :1; /*!< Force index event latch interrupt */ + uint32_t UTO :1; /*!< Force unit time out interrupt */ +} _QEP_QFRC_bits; + +/* Bit field positions: */ +#define QEP_QFRC_PCE_Pos 1 /*!< Force position counter error interrupt */ +#define QEP_QFRC_QPE_Pos 2 /*!< Force quadrature phase error interrupt */ +#define QEP_QFRC_QDC_Pos 3 /*!< Force quadrature direction change interrupt */ +#define QEP_QFRC_WTO_Pos 4 /*!< Force watchdog time out interrupt */ +#define QEP_QFRC_PCU_Pos 5 /*!< Force position counter underflow interrupt */ +#define QEP_QFRC_PCO_Pos 6 /*!< Force position counter overflow interrupt */ +#define QEP_QFRC_PCR_Pos 7 /*!< Force position-compare ready interrupt */ +#define QEP_QFRC_PCM_Pos 8 /*!< Force position-compare match interrupt */ +#define QEP_QFRC_SEL_Pos 9 /*!< Force strobe event latch interrupt */ +#define QEP_QFRC_IEL_Pos 10 /*!< Force index event latch interrupt */ +#define QEP_QFRC_UTO_Pos 11 /*!< Force unit time out interrupt */ + +/* Bit field masks: */ +#define QEP_QFRC_PCE_Msk 0x00000002UL /*!< Force position counter error interrupt */ +#define QEP_QFRC_QPE_Msk 0x00000004UL /*!< Force quadrature phase error interrupt */ +#define QEP_QFRC_QDC_Msk 0x00000008UL /*!< Force quadrature direction change interrupt */ +#define QEP_QFRC_WTO_Msk 0x00000010UL /*!< Force watchdog time out interrupt */ +#define QEP_QFRC_PCU_Msk 0x00000020UL /*!< Force position counter underflow interrupt */ +#define QEP_QFRC_PCO_Msk 0x00000040UL /*!< Force position counter overflow interrupt */ +#define QEP_QFRC_PCR_Msk 0x00000080UL /*!< Force position-compare ready interrupt */ +#define QEP_QFRC_PCM_Msk 0x00000100UL /*!< Force position-compare match interrupt */ +#define QEP_QFRC_SEL_Msk 0x00000200UL /*!< Force strobe event latch interrupt */ +#define QEP_QFRC_IEL_Msk 0x00000400UL /*!< Force index event latch interrupt */ +#define QEP_QFRC_UTO_Msk 0x00000800UL /*!< Force unit time out interrupt */ + +/*-- QEPSTS: Status register ---------------------------------------------------------------------------------*/ +typedef struct { + uint32_t PCEF :1; /*!< Position counter error flag */ + uint32_t FIMF :1; /*!< First index marker flag */ + uint32_t CDEF :1; /*!< Capture direction error flag */ + uint32_t COEF :1; /*!< Capture overflow error flag */ + uint32_t QDLF :1; /*!< QEP direction latch flag */ + uint32_t QDF :1; /*!< Quadrature direction flag */ + uint32_t FIDF :1; /*!< Direction on the first index marker */ + uint32_t UPEVNT :1; /*!< Unit position event flag */ + uint32_t DCF :1; /*!< Direction change flag */ +} _QEP_QEPSTS_bits; + +/* Bit field positions: */ +#define QEP_QEPSTS_PCEF_Pos 0 /*!< Position counter error flag */ +#define QEP_QEPSTS_FIMF_Pos 1 /*!< First index marker flag */ +#define QEP_QEPSTS_CDEF_Pos 2 /*!< Capture direction error flag */ +#define QEP_QEPSTS_COEF_Pos 3 /*!< Capture overflow error flag */ +#define QEP_QEPSTS_QDLF_Pos 4 /*!< QEP direction latch flag */ +#define QEP_QEPSTS_QDF_Pos 5 /*!< Quadrature direction flag */ +#define QEP_QEPSTS_FIDF_Pos 6 /*!< Direction on the first index marker */ +#define QEP_QEPSTS_UPEVNT_Pos 7 /*!< Unit position event flag */ +#define QEP_QEPSTS_DCF_Pos 8 /*!< Direction change flag */ + +/* Bit field masks: */ +#define QEP_QEPSTS_PCEF_Msk 0x00000001UL /*!< Position counter error flag */ +#define QEP_QEPSTS_FIMF_Msk 0x00000002UL /*!< First index marker flag */ +#define QEP_QEPSTS_CDEF_Msk 0x00000004UL /*!< Capture direction error flag */ +#define QEP_QEPSTS_COEF_Msk 0x00000008UL /*!< Capture overflow error flag */ +#define QEP_QEPSTS_QDLF_Msk 0x00000010UL /*!< QEP direction latch flag */ +#define QEP_QEPSTS_QDF_Msk 0x00000020UL /*!< Quadrature direction flag */ +#define QEP_QEPSTS_FIDF_Msk 0x00000040UL /*!< Direction on the first index marker */ +#define QEP_QEPSTS_UPEVNT_Msk 0x00000080UL /*!< Unit position event flag */ +#define QEP_QEPSTS_DCF_Msk 0x00000100UL /*!< Direction change flag */ + +/*-- QCTMR: Capture Timer register ---------------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< */ +} _QEP_QCTMR_bits; + +/* Bit field positions: */ +#define QEP_QCTMR_VAL_Pos 0 /*!< */ + +/* Bit field masks: */ +#define QEP_QCTMR_VAL_Msk 0xFFFFFFFFUL /*!< */ + +/*-- QCPRD: Capture Period register --------------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< */ +} _QEP_QCPRD_bits; + +/* Bit field positions: */ +#define QEP_QCPRD_VAL_Pos 0 /*!< */ + +/* Bit field masks: */ +#define QEP_QCPRD_VAL_Msk 0xFFFFFFFFUL /*!< */ + +/*-- QCTMRLAT: Capture Timer Latch register ------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< */ +} _QEP_QCTMRLAT_bits; + +/* Bit field positions: */ +#define QEP_QCTMRLAT_VAL_Pos 0 /*!< */ + +/* Bit field masks: */ +#define QEP_QCTMRLAT_VAL_Msk 0xFFFFFFFFUL /*!< */ + +/*-- QCPRDLAT: Capture Period Latch register -----------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< */ +} _QEP_QCPRDLAT_bits; + +/* Bit field positions: */ +#define QEP_QCPRDLAT_VAL_Pos 0 /*!< */ + +/* Bit field masks: */ +#define QEP_QCPRDLAT_VAL_Msk 0xFFFFFFFFUL /*!< */ + +/*-- DMAREQ: DMA request register ----------------------------------------------------------------------------*/ +typedef struct { + uint32_t DMAEN :1; /*!< DMA request enable */ +} _QEP_DMAREQ_bits; + +/* Bit field positions: */ +#define QEP_DMAREQ_DMAEN_Pos 0 /*!< DMA request enable */ + +/* Bit field masks: */ +#define QEP_DMAREQ_DMAEN_Msk 0x00000001UL /*!< DMA request enable */ + +/*-- INTCLR: Clear active interrupt register -----------------------------------------------------------------*/ +typedef struct { + uint32_t INT :1; /*!< Active interrupt by read, write 1 to clear interrupt */ +} _QEP_INTCLR_bits; + +/* Bit field positions: */ +#define QEP_INTCLR_INT_Pos 0 /*!< Active interrupt by read, write 1 to clear interrupt */ + +/* Bit field masks: */ +#define QEP_INTCLR_INT_Msk 0x00000001UL /*!< Active interrupt by read, write 1 to clear interrupt */ + +typedef struct { + union { /*!< Position Counter register */ + __IO uint32_t QPOSCNT; /*!< QPOSCNT : type used for word access */ + __IO _QEP_QPOSCNT_bits QPOSCNT_bit; /*!< QPOSCNT_bit: structure used for bit access */ + }; + union { /*!< Position Counter Initialization register */ + __IO uint32_t QPOSINIT; /*!< QPOSINIT : type used for word access */ + __IO _QEP_QPOSINIT_bits QPOSINIT_bit; /*!< QPOSINIT_bit: structure used for bit access */ + }; + union { /*!< Maximum Position Count register */ + __IO uint32_t QPOSMAX; /*!< QPOSMAX : type used for word access */ + __IO _QEP_QPOSMAX_bits QPOSMAX_bit; /*!< QPOSMAX_bit: structure used for bit access */ + }; + union { /*!< Position-compare register */ + __IO uint32_t QPOSCMP; /*!< QPOSCMP : type used for word access */ + __IO _QEP_QPOSCMP_bits QPOSCMP_bit; /*!< QPOSCMP_bit: structure used for bit access */ + }; + union { /*!< Index Position Latch register */ + __I uint32_t QPOSILAT; /*!< QPOSILAT : type used for word access */ + __I _QEP_QPOSILAT_bits QPOSILAT_bit; /*!< QPOSILAT_bit: structure used for bit access */ + }; + union { /*!< Strobe Position Latch register */ + __I uint32_t QPOSSLAT; /*!< QPOSSLAT : type used for word access */ + __I _QEP_QPOSSLAT_bits QPOSSLAT_bit; /*!< QPOSSLAT_bit: structure used for bit access */ + }; + union { /*!< Position Counter Latch register */ + __I uint32_t QPOSLAT; /*!< QPOSLAT : type used for word access */ + __I _QEP_QPOSLAT_bits QPOSLAT_bit; /*!< QPOSLAT_bit: structure used for bit access */ + }; + union { /*!< Unit Timer register */ + __IO uint32_t QUTMR; /*!< QUTMR : type used for word access */ + __IO _QEP_QUTMR_bits QUTMR_bit; /*!< QUTMR_bit: structure used for bit access */ + }; + union { /*!< Unit Period register */ + __IO uint32_t QUPRD; /*!< QUPRD : type used for word access */ + __IO _QEP_QUPRD_bits QUPRD_bit; /*!< QUPRD_bit: structure used for bit access */ + }; + union { /*!< Watchdog Timer register */ + __IO uint32_t QWDTMR; /*!< QWDTMR : type used for word access */ + __IO _QEP_QWDTMR_bits QWDTMR_bit; /*!< QWDTMR_bit: structure used for bit access */ + }; + union { /*!< Watchdog Period register */ + __IO uint32_t QWDPRD; /*!< QWDPRD : type used for word access */ + __IO _QEP_QWDPRD_bits QWDPRD_bit; /*!< QWDPRD_bit: structure used for bit access */ + }; + union { /*!< Decoder Control register */ + __IO uint32_t QDECCTL; /*!< QDECCTL : type used for word access */ + __IO _QEP_QDECCTL_bits QDECCTL_bit; /*!< QDECCTL_bit: structure used for bit access */ + }; + union { /*!< Control register */ + __IO uint32_t QEPCTL; /*!< QEPCTL : type used for word access */ + __IO _QEP_QEPCTL_bits QEPCTL_bit; /*!< QEPCTL_bit: structure used for bit access */ + }; + union { /*!< Capture Control register */ + __IO uint32_t QCAPCTL; /*!< QCAPCTL : type used for word access */ + __IO _QEP_QCAPCTL_bits QCAPCTL_bit; /*!< QCAPCTL_bit: structure used for bit access */ + }; + union { /*!< Position-compare Control register */ + __IO uint32_t QPOSCTL; /*!< QPOSCTL : type used for word access */ + __IO _QEP_QPOSCTL_bits QPOSCTL_bit; /*!< QPOSCTL_bit: structure used for bit access */ + }; + union { /*!< Interrupt Enable register */ + __IO uint32_t QEINT; /*!< QEINT : type used for word access */ + __IO _QEP_QEINT_bits QEINT_bit; /*!< QEINT_bit: structure used for bit access */ + }; + union { /*!< Interrupt Flag register */ + __I uint32_t QFLG; /*!< QFLG : type used for word access */ + __I _QEP_QFLG_bits QFLG_bit; /*!< QFLG_bit: structure used for bit access */ + }; + union { /*!< Interrupt Clear register */ + __IO uint32_t QCLR; /*!< QCLR : type used for word access */ + __IO _QEP_QCLR_bits QCLR_bit; /*!< QCLR_bit: structure used for bit access */ + }; + union { /*!< Interrupt Force register */ + __IO uint32_t QFRC; /*!< QFRC : type used for word access */ + __IO _QEP_QFRC_bits QFRC_bit; /*!< QFRC_bit: structure used for bit access */ + }; + union { /*!< Status register */ + __IO uint32_t QEPSTS; /*!< QEPSTS : type used for word access */ + __IO _QEP_QEPSTS_bits QEPSTS_bit; /*!< QEPSTS_bit: structure used for bit access */ + }; + union { /*!< Capture Timer register */ + __IO uint32_t QCTMR; /*!< QCTMR : type used for word access */ + __IO _QEP_QCTMR_bits QCTMR_bit; /*!< QCTMR_bit: structure used for bit access */ + }; + union { /*!< Capture Period register */ + __IO uint32_t QCPRD; /*!< QCPRD : type used for word access */ + __IO _QEP_QCPRD_bits QCPRD_bit; /*!< QCPRD_bit: structure used for bit access */ + }; + union { /*!< Capture Timer Latch register */ + __I uint32_t QCTMRLAT; /*!< QCTMRLAT : type used for word access */ + __I _QEP_QCTMRLAT_bits QCTMRLAT_bit; /*!< QCTMRLAT_bit: structure used for bit access */ + }; + union { /*!< Capture Period Latch register */ + __I uint32_t QCPRDLAT; /*!< QCPRDLAT : type used for word access */ + __I _QEP_QCPRDLAT_bits QCPRDLAT_bit; /*!< QCPRDLAT_bit: structure used for bit access */ + }; + union { /*!< DMA request register */ + __IO uint32_t DMAREQ; /*!< DMAREQ : type used for word access */ + __IO _QEP_DMAREQ_bits DMAREQ_bit; /*!< DMAREQ_bit: structure used for bit access */ + }; + __IO uint32_t Reserved0[3]; + union { /*!< Clear active interrupt register */ + __IO uint32_t INTCLR; /*!< INTCLR : type used for word access */ + __IO _QEP_INTCLR_bits INTCLR_bit; /*!< INTCLR_bit: structure used for bit access */ + }; +} QEP_TypeDef; + + +/******************************************************************************/ +/* ECAP registers */ +/******************************************************************************/ + +/*-- TSCTR: Counter register ---------------------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< Counter value */ +} _ECAP_TSCTR_bits; + +/* Bit field positions: */ +#define ECAP_TSCTR_VAL_Pos 0 /*!< Counter value */ + +/* Bit field masks: */ +#define ECAP_TSCTR_VAL_Msk 0xFFFFFFFFUL /*!< Counter value */ + +/*-- CTRPHS: Counter Phase Sync register ---------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< */ +} _ECAP_CTRPHS_bits; + +/* Bit field positions: */ +#define ECAP_CTRPHS_VAL_Pos 0 /*!< */ + +/* Bit field masks: */ +#define ECAP_CTRPHS_VAL_Msk 0xFFFFFFFFUL /*!< */ + +/*-- CAP0: Capture register 0 --------------------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< Capture 0 value in CAP mode */ +} _ECAP_CAP0_bits; + +/* Bit field positions: */ +#define ECAP_CAP0_VAL_Pos 0 /*!< Capture 0 value in CAP mode */ + +/* Bit field masks: */ +#define ECAP_CAP0_VAL_Msk 0xFFFFFFFFUL /*!< Capture 0 value in CAP mode */ + +/*-- PRD: Period register ------------------------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< Period value in APWM mode */ +} _ECAP_PRD_bits; + +/* Bit field positions: */ +#define ECAP_PRD_VAL_Pos 0 /*!< Period value in APWM mode */ + +/* Bit field masks: */ +#define ECAP_PRD_VAL_Msk 0xFFFFFFFFUL /*!< Period value in APWM mode */ + +/*-- CAP1: Capture register 1 --------------------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< Capture 1 value in CAP mode */ +} _ECAP_CAP1_bits; + +/* Bit field positions: */ +#define ECAP_CAP1_VAL_Pos 0 /*!< Capture 1 value in CAP mode */ + +/* Bit field masks: */ +#define ECAP_CAP1_VAL_Msk 0xFFFFFFFFUL /*!< Capture 1 value in CAP mode */ + +/*-- CMP: Compare register -----------------------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< Compare value in APWM mode */ +} _ECAP_CMP_bits; + +/* Bit field positions: */ +#define ECAP_CMP_VAL_Pos 0 /*!< Compare value in APWM mode */ + +/* Bit field masks: */ +#define ECAP_CMP_VAL_Msk 0xFFFFFFFFUL /*!< Compare value in APWM mode */ + +/*-- CAP2: Capture register 2 --------------------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< Capture 2 value in CAP mode */ +} _ECAP_CAP2_bits; + +/* Bit field positions: */ +#define ECAP_CAP2_VAL_Pos 0 /*!< Capture 2 value in CAP mode */ + +/* Bit field masks: */ +#define ECAP_CAP2_VAL_Msk 0xFFFFFFFFUL /*!< Capture 2 value in CAP mode */ + +/*-- PRDSHDW: Period shadow register -------------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< Period shadow value in APWM mode */ +} _ECAP_PRDSHDW_bits; + +/* Bit field positions: */ +#define ECAP_PRDSHDW_VAL_Pos 0 /*!< Period shadow value in APWM mode */ + +/* Bit field masks: */ +#define ECAP_PRDSHDW_VAL_Msk 0xFFFFFFFFUL /*!< Period shadow value in APWM mode */ + +/*-- CAP3: Capture register 3 --------------------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< Capture 3 value in CAP mode */ +} _ECAP_CAP3_bits; + +/* Bit field positions: */ +#define ECAP_CAP3_VAL_Pos 0 /*!< Capture 3 value in CAP mode */ + +/* Bit field masks: */ +#define ECAP_CAP3_VAL_Msk 0xFFFFFFFFUL /*!< Capture 3 value in CAP mode */ + +/*-- CMPSHDW: Compare shadow register ------------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :32; /*!< Compare shadow value in APWM mode */ +} _ECAP_CMPSHDW_bits; + +/* Bit field positions: */ +#define ECAP_CMPSHDW_VAL_Pos 0 /*!< Compare shadow value in APWM mode */ + +/* Bit field masks: */ +#define ECAP_CMPSHDW_VAL_Msk 0xFFFFFFFFUL /*!< Compare shadow value in APWM mode */ + +/*-- ECCTL0: Capture control register 0 ---------------------------------------------------------------------*/ +typedef struct { + uint32_t CAP0POL :1; /*!< Polarity select for capture 0 */ + uint32_t CTRRST0 :1; /*!< Reset counter after event 0 */ + uint32_t CAP1POL :1; /*!< Polarity select for capture 1 */ + uint32_t CTRRST1 :1; /*!< Reset counter after event 1 */ + uint32_t CAP2POL :1; /*!< Polarity select for capture 2 */ + uint32_t CTRRST2 :1; /*!< Reset counter after event 2 */ + uint32_t CAP3POL :1; /*!< Polarity select for capture 3 */ + uint32_t CTRRST3 :1; /*!< Reset counter after event 3 */ + uint32_t CAPLDEN :1; /*!< enable capture */ + uint32_t PRESCALE :5; /*!< Prescaler value */ + uint32_t FREESOFT :2; /*!< Emulation mode control */ +} _ECAP_ECCTL0_bits; + +/* Bit field positions: */ +#define ECAP_ECCTL0_CAP0POL_Pos 0 /*!< Polarity select for capture 0 */ +#define ECAP_ECCTL0_CTRRST0_Pos 1 /*!< Reset counter after event 0 */ +#define ECAP_ECCTL0_CAP1POL_Pos 2 /*!< Polarity select for capture 1 */ +#define ECAP_ECCTL0_CTRRST1_Pos 3 /*!< Reset counter after event 1 */ +#define ECAP_ECCTL0_CAP2POL_Pos 4 /*!< Polarity select for capture 2 */ +#define ECAP_ECCTL0_CTRRST2_Pos 5 /*!< Reset counter after event 2 */ +#define ECAP_ECCTL0_CAP3POL_Pos 6 /*!< Polarity select for capture 3 */ +#define ECAP_ECCTL0_CTRRST3_Pos 7 /*!< Reset counter after event 3 */ +#define ECAP_ECCTL0_CAPLDEN_Pos 8 /*!< enable capture */ +#define ECAP_ECCTL0_PRESCALE_Pos 9 /*!< Prescaler value */ +#define ECAP_ECCTL0_FREESOFT_Pos 14 /*!< Emulation mode control */ + +/* Bit field masks: */ +#define ECAP_ECCTL0_CAP0POL_Msk 0x00000001UL /*!< Polarity select for capture 0 */ +#define ECAP_ECCTL0_CTRRST0_Msk 0x00000002UL /*!< Reset counter after event 0 */ +#define ECAP_ECCTL0_CAP1POL_Msk 0x00000004UL /*!< Polarity select for capture 1 */ +#define ECAP_ECCTL0_CTRRST1_Msk 0x00000008UL /*!< Reset counter after event 1 */ +#define ECAP_ECCTL0_CAP2POL_Msk 0x00000010UL /*!< Polarity select for capture 2 */ +#define ECAP_ECCTL0_CTRRST2_Msk 0x00000020UL /*!< Reset counter after event 2 */ +#define ECAP_ECCTL0_CAP3POL_Msk 0x00000040UL /*!< Polarity select for capture 3 */ +#define ECAP_ECCTL0_CTRRST3_Msk 0x00000080UL /*!< Reset counter after event 3 */ +#define ECAP_ECCTL0_CAPLDEN_Msk 0x00000100UL /*!< enable capture */ +#define ECAP_ECCTL0_PRESCALE_Msk 0x00003E00UL /*!< Prescaler value */ +#define ECAP_ECCTL0_FREESOFT_Msk 0x0000C000UL /*!< Emulation mode control */ + +/* Bit field enums: */ +typedef enum { + ECAP_ECCTL0_FREESOFT_Stop = 0x0UL, /*!< stop timer immedeatelly */ + ECAP_ECCTL0_FREESOFT_StopAtZero = 0x1UL, /*!< stop timer when reach zero */ + ECAP_ECCTL0_FREESOFT_Free = 0x2UL, /*!< normal work */ +} ECAP_ECCTL0_FREESOFT_Enum; + +/*-- ECCTL1: Capture control register 1 ----------------------------------------------------------------------*/ +typedef struct { + uint32_t CONTOST :1; /*!< Capture mode */ + uint32_t STOPWRAP :2; /*!< Stop compare value */ + uint32_t REARM :1; /*!< Reset and enable controller, capture reg load */ + uint32_t TSCTRSTOP :1; /*!< Enable Timer */ + uint32_t SYNCIEN :1; /*!< Sync in enable */ + uint32_t SYNCOSEL :2; /*!< SYNCO source selection */ + uint32_t SWSYNC :1; /*!< Software timers sync */ + uint32_t CAPAPWM :1; /*!< Capture mode or APWM mode */ + uint32_t APWMPOL :1; /*!< High/low level APWM */ +} _ECAP_ECCTL1_bits; + +/* Bit field positions: */ +#define ECAP_ECCTL1_CONTOST_Pos 0 /*!< Capture mode */ +#define ECAP_ECCTL1_STOPWRAP_Pos 1 /*!< Stop compare value */ +#define ECAP_ECCTL1_REARM_Pos 3 /*!< Reset and enable controller, capture reg load */ +#define ECAP_ECCTL1_TSCTRSTOP_Pos 4 /*!< Enable Timer */ +#define ECAP_ECCTL1_SYNCIEN_Pos 5 /*!< Sync in enable */ +#define ECAP_ECCTL1_SYNCOSEL_Pos 6 /*!< SYNCO source selection */ +#define ECAP_ECCTL1_SWSYNC_Pos 8 /*!< Software timers sync */ +#define ECAP_ECCTL1_CAPAPWM_Pos 9 /*!< Capture mode or APWM mode */ +#define ECAP_ECCTL1_APWMPOL_Pos 10 /*!< High/low level APWM */ + +/* Bit field masks: */ +#define ECAP_ECCTL1_CONTOST_Msk 0x00000001UL /*!< Capture mode */ +#define ECAP_ECCTL1_STOPWRAP_Msk 0x00000006UL /*!< Stop compare value */ +#define ECAP_ECCTL1_REARM_Msk 0x00000008UL /*!< Reset and enable controller, capture reg load */ +#define ECAP_ECCTL1_TSCTRSTOP_Msk 0x00000010UL /*!< Enable Timer */ +#define ECAP_ECCTL1_SYNCIEN_Msk 0x00000020UL /*!< Sync in enable */ +#define ECAP_ECCTL1_SYNCOSEL_Msk 0x000000C0UL /*!< SYNCO source selection */ +#define ECAP_ECCTL1_SWSYNC_Msk 0x00000100UL /*!< Software timers sync */ +#define ECAP_ECCTL1_CAPAPWM_Msk 0x00000200UL /*!< Capture mode or APWM mode */ +#define ECAP_ECCTL1_APWMPOL_Msk 0x00000400UL /*!< High/low level APWM */ + +/* Bit field enums: */ +typedef enum { + ECAP_ECCTL1_SYNCOSEL_Bypass = 0x0UL, /*!< sync in connected with sync out */ + ECAP_ECCTL1_SYNCOSEL_CTREqPrd = 0x1UL, /*!< sync out generated when CTR = PRD */ + ECAP_ECCTL1_SYNCOSEL_Disable = 0x2UL, /*!< sync out generate disabled */ +} ECAP_ECCTL1_SYNCOSEL_Enum; + +/*-- ECEINT: Interrupt mask register -------------------------------------------------------------------------*/ +typedef struct { + uint32_t :1; /*!< RESERVED */ + uint32_t CEVT0 :1; /*!< enable int CEVT0 */ + uint32_t CEVT1 :1; /*!< enable int CEVT1 */ + uint32_t CEVT2 :1; /*!< enable int CEVT2 */ + uint32_t CEVT3 :1; /*!< enable int CEVT3 */ + uint32_t CTROVF :1; /*!< enable int CTR_OVF */ + uint32_t CTRPRD :1; /*!< enable int CTR=PRD */ + uint32_t CTRCMP :1; /*!< enable int CTR=CMP */ +} _ECAP_ECEINT_bits; + +/* Bit field positions: */ +#define ECAP_ECEINT_CEVT0_Pos 1 /*!< enable int CEVT0 */ +#define ECAP_ECEINT_CEVT1_Pos 2 /*!< enable int CEVT1 */ +#define ECAP_ECEINT_CEVT2_Pos 3 /*!< enable int CEVT2 */ +#define ECAP_ECEINT_CEVT3_Pos 4 /*!< enable int CEVT3 */ +#define ECAP_ECEINT_CTROVF_Pos 5 /*!< enable int CTR_OVF */ +#define ECAP_ECEINT_CTRPRD_Pos 6 /*!< enable int CTR=PRD */ +#define ECAP_ECEINT_CTRCMP_Pos 7 /*!< enable int CTR=CMP */ + +/* Bit field masks: */ +#define ECAP_ECEINT_CEVT0_Msk 0x00000002UL /*!< enable int CEVT0 */ +#define ECAP_ECEINT_CEVT1_Msk 0x00000004UL /*!< enable int CEVT1 */ +#define ECAP_ECEINT_CEVT2_Msk 0x00000008UL /*!< enable int CEVT2 */ +#define ECAP_ECEINT_CEVT3_Msk 0x00000010UL /*!< enable int CEVT3 */ +#define ECAP_ECEINT_CTROVF_Msk 0x00000020UL /*!< enable int CTR_OVF */ +#define ECAP_ECEINT_CTRPRD_Msk 0x00000040UL /*!< enable int CTR=PRD */ +#define ECAP_ECEINT_CTRCMP_Msk 0x00000080UL /*!< enable int CTR=CMP */ + +/*-- ECFLG: Interrupt status register ------------------------------------------------------------------------*/ +typedef struct { + uint32_t INT :1; /*!< indicate global interrupt */ + uint32_t CEVT0 :1; /*!< Hap interrupt CEVT0 */ + uint32_t CEVT1 :1; /*!< Hap interrupt CEVT1 */ + uint32_t CEVT2 :1; /*!< Hap interrupt CEVT2 */ + uint32_t CEVT3 :1; /*!< Hap interrupt CEVT3 */ + uint32_t CTROVF :1; /*!< Hap interrupt CTROVF */ + uint32_t CTRPRD :1; /*!< Hap interrupt CTR=PRD */ + uint32_t CTRCMP :1; /*!< Hap interrupt CTR=CMP */ +} _ECAP_ECFLG_bits; + +/* Bit field positions: */ +#define ECAP_ECFLG_INT_Pos 0 /*!< indicate global interrupt */ +#define ECAP_ECFLG_CEVT0_Pos 1 /*!< Hap interrupt CEVT0 */ +#define ECAP_ECFLG_CEVT1_Pos 2 /*!< Hap interrupt CEVT1 */ +#define ECAP_ECFLG_CEVT2_Pos 3 /*!< Hap interrupt CEVT2 */ +#define ECAP_ECFLG_CEVT3_Pos 4 /*!< Hap interrupt CEVT3 */ +#define ECAP_ECFLG_CTROVF_Pos 5 /*!< Hap interrupt CTROVF */ +#define ECAP_ECFLG_CTRPRD_Pos 6 /*!< Hap interrupt CTR=PRD */ +#define ECAP_ECFLG_CTRCMP_Pos 7 /*!< Hap interrupt CTR=CMP */ + +/* Bit field masks: */ +#define ECAP_ECFLG_INT_Msk 0x00000001UL /*!< indicate global interrupt */ +#define ECAP_ECFLG_CEVT0_Msk 0x00000002UL /*!< Hap interrupt CEVT0 */ +#define ECAP_ECFLG_CEVT1_Msk 0x00000004UL /*!< Hap interrupt CEVT1 */ +#define ECAP_ECFLG_CEVT2_Msk 0x00000008UL /*!< Hap interrupt CEVT2 */ +#define ECAP_ECFLG_CEVT3_Msk 0x00000010UL /*!< Hap interrupt CEVT3 */ +#define ECAP_ECFLG_CTROVF_Msk 0x00000020UL /*!< Hap interrupt CTROVF */ +#define ECAP_ECFLG_CTRPRD_Msk 0x00000040UL /*!< Hap interrupt CTR=PRD */ +#define ECAP_ECFLG_CTRCMP_Msk 0x00000080UL /*!< Hap interrupt CTR=CMP */ + +/*-- ECCLR: Clear interrupt register -------------------------------------------------------------------------*/ +typedef struct { + uint32_t INT :1; /*!< reset global interrupt */ + uint32_t CEVT0 :1; /*!< reset intstatus */ + uint32_t CEVT1 :1; /*!< reset intstatus */ + uint32_t CEVT2 :1; /*!< reset intstatus */ + uint32_t CEVT3 :1; /*!< reset intstatus */ + uint32_t CTROVF :1; /*!< reset intstatus */ + uint32_t CTRPRD :1; /*!< reset intstatus */ + uint32_t CTRCMP :1; /*!< reset intstatus */ +} _ECAP_ECCLR_bits; + +/* Bit field positions: */ +#define ECAP_ECCLR_INT_Pos 0 /*!< reset global interrupt */ +#define ECAP_ECCLR_CEVT0_Pos 1 /*!< reset intstatus */ +#define ECAP_ECCLR_CEVT1_Pos 2 /*!< reset intstatus */ +#define ECAP_ECCLR_CEVT2_Pos 3 /*!< reset intstatus */ +#define ECAP_ECCLR_CEVT3_Pos 4 /*!< reset intstatus */ +#define ECAP_ECCLR_CTROVF_Pos 5 /*!< reset intstatus */ +#define ECAP_ECCLR_CTRPRD_Pos 6 /*!< reset intstatus */ +#define ECAP_ECCLR_CTRCMP_Pos 7 /*!< reset intstatus */ + +/* Bit field masks: */ +#define ECAP_ECCLR_INT_Msk 0x00000001UL /*!< reset global interrupt */ +#define ECAP_ECCLR_CEVT0_Msk 0x00000002UL /*!< reset intstatus */ +#define ECAP_ECCLR_CEVT1_Msk 0x00000004UL /*!< reset intstatus */ +#define ECAP_ECCLR_CEVT2_Msk 0x00000008UL /*!< reset intstatus */ +#define ECAP_ECCLR_CEVT3_Msk 0x00000010UL /*!< reset intstatus */ +#define ECAP_ECCLR_CTROVF_Msk 0x00000020UL /*!< reset intstatus */ +#define ECAP_ECCLR_CTRPRD_Msk 0x00000040UL /*!< reset intstatus */ +#define ECAP_ECCLR_CTRCMP_Msk 0x00000080UL /*!< reset intstatus */ + +/*-- ECFRC: Force interrupt register -------------------------------------------------------------------------*/ +typedef struct { + uint32_t :1; /*!< RESERVED */ + uint32_t CEVT0 :1; /*!< gen test interrupt */ + uint32_t CEVT1 :1; /*!< gen test interrupt */ + uint32_t CEVT2 :1; /*!< gen test interrupt */ + uint32_t CEVT3 :1; /*!< gen test interrupt */ + uint32_t CTROVF :1; /*!< gen test interrupt */ + uint32_t CTRPRD :1; /*!< gen test interrupt */ + uint32_t CTRCMP :1; /*!< gen test interrupt */ +} _ECAP_ECFRC_bits; + +/* Bit field positions: */ +#define ECAP_ECFRC_CEVT0_Pos 1 /*!< gen test interrupt */ +#define ECAP_ECFRC_CEVT1_Pos 2 /*!< gen test interrupt */ +#define ECAP_ECFRC_CEVT2_Pos 3 /*!< gen test interrupt */ +#define ECAP_ECFRC_CEVT3_Pos 4 /*!< gen test interrupt */ +#define ECAP_ECFRC_CTROVF_Pos 5 /*!< gen test interrupt */ +#define ECAP_ECFRC_CTRPRD_Pos 6 /*!< gen test interrupt */ +#define ECAP_ECFRC_CTRCMP_Pos 7 /*!< gen test interrupt */ + +/* Bit field masks: */ +#define ECAP_ECFRC_CEVT0_Msk 0x00000002UL /*!< gen test interrupt */ +#define ECAP_ECFRC_CEVT1_Msk 0x00000004UL /*!< gen test interrupt */ +#define ECAP_ECFRC_CEVT2_Msk 0x00000008UL /*!< gen test interrupt */ +#define ECAP_ECFRC_CEVT3_Msk 0x00000010UL /*!< gen test interrupt */ +#define ECAP_ECFRC_CTROVF_Msk 0x00000020UL /*!< gen test interrupt */ +#define ECAP_ECFRC_CTRPRD_Msk 0x00000040UL /*!< gen test interrupt */ +#define ECAP_ECFRC_CTRCMP_Msk 0x00000080UL /*!< gen test interrupt */ + +/*-- PEINT: Active interrupt status register -----------------------------------------------------------------*/ +typedef struct { + uint32_t PEINT :1; /*!< active interrupt flag */ +} _ECAP_PEINT_bits; + +/* Bit field positions: */ +#define ECAP_PEINT_PEINT_Pos 0 /*!< active interrupt flag */ + +/* Bit field masks: */ +#define ECAP_PEINT_PEINT_Msk 0x00000001UL /*!< active interrupt flag */ + +typedef struct { + union { /*!< Counter register */ + __IO uint32_t TSCTR; /*!< TSCTR : type used for word access */ + __IO _ECAP_TSCTR_bits TSCTR_bit; /*!< TSCTR_bit: structure used for bit access */ + }; + union { /*!< Counter Phase Sync register */ + __IO uint32_t CTRPHS; /*!< CTRPHS : type used for word access */ + __IO _ECAP_CTRPHS_bits CTRPHS_bit; /*!< CTRPHS_bit: structure used for bit access */ + }; + union { + union { /*!< Capture register 0 */ + __IO uint32_t CAP0; /*!< CAP0 : type used for word access */ + __IO _ECAP_CAP0_bits CAP0_bit; /*!< CAP0_bit: structure used for bit access */ + }; + struct { + union { /*!< Period register */ + __IO uint32_t PRD; /*!< PRD : type used for word access */ + __IO _ECAP_PRD_bits PRD_bit; /*!< PRD_bit: structure used for bit access */ + }; + }; + }; + union { + union { /*!< Capture register 1 */ + __IO uint32_t CAP1; /*!< CAP1 : type used for word access */ + __IO _ECAP_CAP1_bits CAP1_bit; /*!< CAP1_bit: structure used for bit access */ + }; + struct { + union { /*!< Compare register */ + __IO uint32_t CMP; /*!< CMP : type used for word access */ + __IO _ECAP_CMP_bits CMP_bit; /*!< CMP_bit: structure used for bit access */ + }; + }; + }; + union { + union { /*!< Capture register 2 */ + __IO uint32_t CAP2; /*!< CAP2 : type used for word access */ + __IO _ECAP_CAP2_bits CAP2_bit; /*!< CAP2_bit: structure used for bit access */ + }; + struct { + union { /*!< Period shadow register */ + __IO uint32_t PRDSHDW; /*!< PRDSHDW : type used for word access */ + __IO _ECAP_PRDSHDW_bits PRDSHDW_bit; /*!< PRDSHDW_bit: structure used for bit access */ + }; + }; + }; + union { + union { /*!< Capture register 3 */ + __IO uint32_t CAP3; /*!< CAP3 : type used for word access */ + __IO _ECAP_CAP3_bits CAP3_bit; /*!< CAP3_bit: structure used for bit access */ + }; + struct { + union { /*!< Compare shadow register */ + __IO uint32_t CMPSHDW; /*!< CMPSHDW : type used for word access */ + __IO _ECAP_CMPSHDW_bits CMPSHDW_bit; /*!< CMPSHDW_bit: structure used for bit access */ + }; + }; + }; + __IO uint32_t Reserved0[4]; + union { /*!< Capture control register 0 */ + __IO uint32_t ECCTL0; /*!< ECCTL0 : type used for word access */ + __IO _ECAP_ECCTL0_bits ECCTL0_bit; /*!< ECCTL0_bit: structure used for bit access */ + }; + union { /*!< Capture control register 1 */ + __IO uint32_t ECCTL1; /*!< ECCTL1 : type used for word access */ + __IO _ECAP_ECCTL1_bits ECCTL1_bit; /*!< ECCTL1_bit: structure used for bit access */ + }; + union { /*!< Interrupt mask register */ + __IO uint32_t ECEINT; /*!< ECEINT : type used for word access */ + __IO _ECAP_ECEINT_bits ECEINT_bit; /*!< ECEINT_bit: structure used for bit access */ + }; + union { /*!< Interrupt status register */ + __I uint32_t ECFLG; /*!< ECFLG : type used for word access */ + __I _ECAP_ECFLG_bits ECFLG_bit; /*!< ECFLG_bit: structure used for bit access */ + }; + union { /*!< Clear interrupt register */ + __IO uint32_t ECCLR; /*!< ECCLR : type used for word access */ + __IO _ECAP_ECCLR_bits ECCLR_bit; /*!< ECCLR_bit: structure used for bit access */ + }; + union { /*!< Force interrupt register */ + __IO uint32_t ECFRC; /*!< ECFRC : type used for word access */ + __IO _ECAP_ECFRC_bits ECFRC_bit; /*!< ECFRC_bit: structure used for bit access */ + }; + union { /*!< Active interrupt status register */ + __IO uint32_t PEINT; /*!< PEINT : type used for word access */ + __IO _ECAP_PEINT_bits PEINT_bit; /*!< PEINT_bit: structure used for bit access */ + }; +} ECAP_TypeDef; + + +/******************************************************************************/ +/* PWM registers */ +/******************************************************************************/ + +/*-- TBCTL: Time-Base Control Register -----------------------------------------------------------------------*/ +typedef struct { + uint32_t CTRMODE :2; /*!< Counter mode */ + uint32_t PHSEN :1; /*!< Counter register load from phase register enable */ + uint32_t PRDLD :1; /*!< Active period register load from shadow register select */ + uint32_t SYNCOSEL :2; /*!< Synchronization Output Select. These bits select the source of the PWM_SYNCO signal. */ + uint32_t SWFSYNC :1; /*!< Software forced synchronization pulse */ + uint32_t HSPCLKDIV :3; /*!< High speed time-base clock prescale bits */ + uint32_t CLKDIV :3; /*!< Time-base clock prescale bits */ + uint32_t PHSDIR :1; /*!< Phase direction bit */ + uint32_t FREESOFT :2; /*!< Emulation mode bits - select the behavior of the time-base counter during emulation events */ + uint32_t SHDWGLOB :1; /*!< Global enable for all shadow loads */ +} _PWM_TBCTL_bits; + +/* Bit field positions: */ +#define PWM_TBCTL_CTRMODE_Pos 0 /*!< Counter mode */ +#define PWM_TBCTL_PHSEN_Pos 2 /*!< Counter register load from phase register enable */ +#define PWM_TBCTL_PRDLD_Pos 3 /*!< Active period register load from shadow register select */ +#define PWM_TBCTL_SYNCOSEL_Pos 4 /*!< Synchronization Output Select. These bits select the source of the PWM_SYNCO signal. */ +#define PWM_TBCTL_SWFSYNC_Pos 6 /*!< Software forced synchronization pulse */ +#define PWM_TBCTL_HSPCLKDIV_Pos 7 /*!< High speed time-base clock prescale bits */ +#define PWM_TBCTL_CLKDIV_Pos 10 /*!< Time-base clock prescale bits */ +#define PWM_TBCTL_PHSDIR_Pos 13 /*!< Phase direction bit */ +#define PWM_TBCTL_FREESOFT_Pos 14 /*!< Emulation mode bits - select the behavior of the time-base counter during emulation events */ +#define PWM_TBCTL_SHDWGLOB_Pos 16 /*!< Global enable for all shadow loads */ + +/* Bit field masks: */ +#define PWM_TBCTL_CTRMODE_Msk 0x00000003UL /*!< Counter mode */ +#define PWM_TBCTL_PHSEN_Msk 0x00000004UL /*!< Counter register load from phase register enable */ +#define PWM_TBCTL_PRDLD_Msk 0x00000008UL /*!< Active period register load from shadow register select */ +#define PWM_TBCTL_SYNCOSEL_Msk 0x00000030UL /*!< Synchronization Output Select. These bits select the source of the PWM_SYNCO signal. */ +#define PWM_TBCTL_SWFSYNC_Msk 0x00000040UL /*!< Software forced synchronization pulse */ +#define PWM_TBCTL_HSPCLKDIV_Msk 0x00000380UL /*!< High speed time-base clock prescale bits */ +#define PWM_TBCTL_CLKDIV_Msk 0x00001C00UL /*!< Time-base clock prescale bits */ +#define PWM_TBCTL_PHSDIR_Msk 0x00002000UL /*!< Phase direction bit */ +#define PWM_TBCTL_FREESOFT_Msk 0x0000C000UL /*!< Emulation mode bits - select the behavior of the time-base counter during emulation events */ +#define PWM_TBCTL_SHDWGLOB_Msk 0x00010000UL /*!< Global enable for all shadow loads */ + +/* Bit field enums: */ +typedef enum { + PWM_TBCTL_CTRMODE_Up = 0x0UL, /*!< count direction up */ + PWM_TBCTL_CTRMODE_Down = 0x1UL, /*!< count direction down */ + PWM_TBCTL_CTRMODE_UpDown = 0x2UL, /*!< count direction up-down */ + PWM_TBCTL_CTRMODE_Stop = 0x3UL, /*!< counter stopped */ +} PWM_TBCTL_CTRMODE_Enum; + +typedef enum { + PWM_TBCTL_SYNCOSEL_SYNCI = 0x0UL, /*!< PWM_SYNCI is source for PWM_SYNCO */ + PWM_TBCTL_SYNCOSEL_CTREqZero = 0x1UL, /*!< CTR = 0000h is source for PWM_SYNCO */ + PWM_TBCTL_SYNCOSEL_CTREqCMPB = 0x2UL, /*!< CTR = CMPB is source for PWM_SYNCO */ + PWM_TBCTL_SYNCOSEL_Disable = 0x3UL, /*!< PWM_SYNCO generation disabled */ +} PWM_TBCTL_SYNCOSEL_Enum; + +typedef enum { + PWM_TBCTL_HSPCLKDIV_Div1 = 0x0UL, /*!< clock not divided */ + PWM_TBCTL_HSPCLKDIV_Div2 = 0x1UL, /*!< clock divided by 2 */ + PWM_TBCTL_HSPCLKDIV_Div4 = 0x2UL, /*!< clock divided by 4 */ + PWM_TBCTL_HSPCLKDIV_Div6 = 0x3UL, /*!< clock divided by 6 */ + PWM_TBCTL_HSPCLKDIV_Div8 = 0x4UL, /*!< clock divided by 8 */ + PWM_TBCTL_HSPCLKDIV_Div10 = 0x5UL, /*!< clock divided by 10 */ + PWM_TBCTL_HSPCLKDIV_Div12 = 0x6UL, /*!< clock divided by 12 */ + PWM_TBCTL_HSPCLKDIV_Div14 = 0x7UL, /*!< clock divided by 14 */ +} PWM_TBCTL_HSPCLKDIV_Enum; + +typedef enum { + PWM_TBCTL_CLKDIV_Div1 = 0x0UL, /*!< clock not divided */ + PWM_TBCTL_CLKDIV_Div2 = 0x1UL, /*!< clock divided by 2 */ + PWM_TBCTL_CLKDIV_Div4 = 0x2UL, /*!< clock divided by 4 */ + PWM_TBCTL_CLKDIV_Div8 = 0x3UL, /*!< clock divided by 8 */ + PWM_TBCTL_CLKDIV_Div16 = 0x4UL, /*!< clock divided by 16 */ + PWM_TBCTL_CLKDIV_Div32 = 0x5UL, /*!< clock divided by 32 */ + PWM_TBCTL_CLKDIV_Div64 = 0x6UL, /*!< clock divided by 64 */ + PWM_TBCTL_CLKDIV_Div128 = 0x7UL, /*!< clock divided by 128 */ +} PWM_TBCTL_CLKDIV_Enum; + +typedef enum { + PWM_TBCTL_FREESOFT_StopAtTBCLK = 0x0UL, /*!< stop timer at next TBCLK tact */ + PWM_TBCTL_FREESOFT_StopAtPeriod = 0x1UL, /*!< stop timer when period ends */ + PWM_TBCTL_FREESOFT_FreeRun = 0x2UL, /*!< free run mode */ +} PWM_TBCTL_FREESOFT_Enum; + +/*-- TBSTS: Time-Base Status Register ------------------------------------------------------------------------*/ +typedef struct { + uint32_t CTRDIR :1; /*!< Time-Base counter direction status bit */ + uint32_t SYNCI :1; /*!< Input synchronization latched status bit */ + uint32_t CTRMAX :1; /*!< Time-Base counter max latched status bit */ +} _PWM_TBSTS_bits; + +/* Bit field positions: */ +#define PWM_TBSTS_CTRDIR_Pos 0 /*!< Time-Base counter direction status bit */ +#define PWM_TBSTS_SYNCI_Pos 1 /*!< Input synchronization latched status bit */ +#define PWM_TBSTS_CTRMAX_Pos 2 /*!< Time-Base counter max latched status bit */ + +/* Bit field masks: */ +#define PWM_TBSTS_CTRDIR_Msk 0x00000001UL /*!< Time-Base counter direction status bit */ +#define PWM_TBSTS_SYNCI_Msk 0x00000002UL /*!< Input synchronization latched status bit */ +#define PWM_TBSTS_CTRMAX_Msk 0x00000004UL /*!< Time-Base counter max latched status bit */ + +/*-- TBPHS: Time-Base Phase Register -------------------------------------------------------------------------*/ +typedef struct { + uint32_t :16; /*!< RESERVED */ + uint32_t TBPHS :16; /*!< Time-base counter phase */ +} _PWM_TBPHS_bits; + +/* Bit field positions: */ +#define PWM_TBPHS_TBPHS_Pos 16 /*!< Time-base counter phase */ + +/* Bit field masks: */ +#define PWM_TBPHS_TBPHS_Msk 0xFFFF0000UL /*!< Time-base counter phase */ + +/*-- TBCTR: Time-Base Counter Register -----------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :16; /*!< Current time-base counter value */ +} _PWM_TBCTR_bits; + +/* Bit field positions: */ +#define PWM_TBCTR_VAL_Pos 0 /*!< Current time-base counter value */ + +/* Bit field masks: */ +#define PWM_TBCTR_VAL_Msk 0x0000FFFFUL /*!< Current time-base counter value */ + +/*-- TBPRD: Time-Base Period Register ------------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :16; /*!< Period of the time-base counter */ +} _PWM_TBPRD_bits; + +/* Bit field positions: */ +#define PWM_TBPRD_VAL_Pos 0 /*!< Period of the time-base counter */ + +/* Bit field masks: */ +#define PWM_TBPRD_VAL_Msk 0x0000FFFFUL /*!< Period of the time-base counter */ + +/*-- CMPCTL: Counter-Compare Control Register ----------------------------------------------------------------*/ +typedef struct { + uint32_t LOADAMODE :2; /*!< Active CMPA load from shadow select mode */ + uint32_t LOADBMODE :2; /*!< Active CMPB load from shadow select mode */ + uint32_t SHDWAMODE :1; /*!< CMPA register operating mode */ + uint32_t :1; /*!< RESERVED */ + uint32_t SHDWBMODE :1; /*!< CMPB register operating mode */ + uint32_t :1; /*!< RESERVED */ + uint32_t SHDWAFULL :1; /*!< CMPA shadow register full status flag */ + uint32_t SHDWBFULL :1; /*!< CMPB shadow register full status flag */ +} _PWM_CMPCTL_bits; + +/* Bit field positions: */ +#define PWM_CMPCTL_LOADAMODE_Pos 0 /*!< Active CMPA load from shadow select mode */ +#define PWM_CMPCTL_LOADBMODE_Pos 2 /*!< Active CMPB load from shadow select mode */ +#define PWM_CMPCTL_SHDWAMODE_Pos 4 /*!< CMPA register operating mode */ +#define PWM_CMPCTL_SHDWBMODE_Pos 6 /*!< CMPB register operating mode */ +#define PWM_CMPCTL_SHDWAFULL_Pos 8 /*!< CMPA shadow register full status flag */ +#define PWM_CMPCTL_SHDWBFULL_Pos 9 /*!< CMPB shadow register full status flag */ + +/* Bit field masks: */ +#define PWM_CMPCTL_LOADAMODE_Msk 0x00000003UL /*!< Active CMPA load from shadow select mode */ +#define PWM_CMPCTL_LOADBMODE_Msk 0x0000000CUL /*!< Active CMPB load from shadow select mode */ +#define PWM_CMPCTL_SHDWAMODE_Msk 0x00000010UL /*!< CMPA register operating mode */ +#define PWM_CMPCTL_SHDWBMODE_Msk 0x00000040UL /*!< CMPB register operating mode */ +#define PWM_CMPCTL_SHDWAFULL_Msk 0x00000100UL /*!< CMPA shadow register full status flag */ +#define PWM_CMPCTL_SHDWBFULL_Msk 0x00000200UL /*!< CMPB shadow register full status flag */ + +/* Bit field enums: */ +typedef enum { + PWM_CMPCTL_LOADAMODE_CTREqZero = 0x0UL, /*!< shadow load for CMPx (x=A,B) when CTR = 0 */ + PWM_CMPCTL_LOADAMODE_CTREqPRD = 0x1UL, /*!< shadow load for CMPx (x=A,B) when CTR = PRD */ + PWM_CMPCTL_LOADAMODE_CTREqZeroPRD = 0x2UL, /*!< shadow load for CMPx (x=A,B) when CTR = 0 or CTR = PRD */ + PWM_CMPCTL_LOADAMODE_Disable = 0x3UL, /*!< shadow load for CMPx (x=A,B) disabled */ +} PWM_CMPCTL_LOADAMODE_Enum; + +typedef enum { + PWM_CMPCTL_LOADBMODE_CTREqZero = 0x0UL, /*!< shadow load for CMPx (x=A,B) when CTR = 0 */ + PWM_CMPCTL_LOADBMODE_CTREqPRD = 0x1UL, /*!< shadow load for CMPx (x=A,B) when CTR = PRD */ + PWM_CMPCTL_LOADBMODE_CTREqZeroPRD = 0x2UL, /*!< shadow load for CMPx (x=A,B) when CTR = 0 or CTR = PRD */ + PWM_CMPCTL_LOADBMODE_Disable = 0x3UL, /*!< shadow load for CMPx (x=A,B) disabled */ +} PWM_CMPCTL_LOADBMODE_Enum; + +/*-- CMPA: Counter-Compare A Register ------------------------------------------------------------------------*/ +typedef struct { + uint32_t :16; /*!< RESERVED */ + uint32_t CMPA :16; /*!< The value compared to the time-base counter (TBCTR) */ +} _PWM_CMPA_bits; + +/* Bit field positions: */ +#define PWM_CMPA_CMPA_Pos 16 /*!< The value compared to the time-base counter (TBCTR) */ + +/* Bit field masks: */ +#define PWM_CMPA_CMPA_Msk 0xFFFF0000UL /*!< The value compared to the time-base counter (TBCTR) */ + +/*-- CMPB: Counter-Compare B Register ------------------------------------------------------------------------*/ +typedef struct { + uint32_t :16; /*!< RESERVED */ + uint32_t CMPB :16; /*!< The value compared to the time-base counter (TBCTR) */ +} _PWM_CMPB_bits; + +/* Bit field positions: */ +#define PWM_CMPB_CMPB_Pos 16 /*!< The value compared to the time-base counter (TBCTR) */ + +/* Bit field masks: */ +#define PWM_CMPB_CMPB_Msk 0xFFFF0000UL /*!< The value compared to the time-base counter (TBCTR) */ + +/*-- AQCTLA: Action-Qualifier Output A Control Register ------------------------------------------------------*/ +typedef struct { + uint32_t ZRO :2; /*!< Action when counter equals zero */ + uint32_t PRD :2; /*!< Action when the counter equals the period */ + uint32_t CAU :2; /*!< Action when the counter equals the active CMPA register and the counter is incrementing */ + uint32_t CAD :2; /*!< Action when the counter equals the active CMPA register and the counter is decrementing */ + uint32_t CBU :2; /*!< Action when the counter equals the active CMPB register and the counter is incrementing */ + uint32_t CBD :2; /*!< Action when the time-base counter equals the active CMPB register and the counter is decrementing + */ +} _PWM_AQCTLA_bits; + +/* Bit field positions: */ +#define PWM_AQCTLA_ZRO_Pos 0 /*!< Action when counter equals zero */ +#define PWM_AQCTLA_PRD_Pos 2 /*!< Action when the counter equals the period */ +#define PWM_AQCTLA_CAU_Pos 4 /*!< Action when the counter equals the active CMPA register and the counter is incrementing */ +#define PWM_AQCTLA_CAD_Pos 6 /*!< Action when the counter equals the active CMPA register and the counter is decrementing */ +#define PWM_AQCTLA_CBU_Pos 8 /*!< Action when the counter equals the active CMPB register and the counter is incrementing */ +#define PWM_AQCTLA_CBD_Pos 10 /*!< Action when the time-base counter equals the active CMPB register and the counter is decrementing + */ + +/* Bit field masks: */ +#define PWM_AQCTLA_ZRO_Msk 0x00000003UL /*!< Action when counter equals zero */ +#define PWM_AQCTLA_PRD_Msk 0x0000000CUL /*!< Action when the counter equals the period */ +#define PWM_AQCTLA_CAU_Msk 0x00000030UL /*!< Action when the counter equals the active CMPA register and the counter is incrementing */ +#define PWM_AQCTLA_CAD_Msk 0x000000C0UL /*!< Action when the counter equals the active CMPA register and the counter is decrementing */ +#define PWM_AQCTLA_CBU_Msk 0x00000300UL /*!< Action when the counter equals the active CMPB register and the counter is incrementing */ +#define PWM_AQCTLA_CBD_Msk 0x00000C00UL /*!< Action when the time-base counter equals the active CMPB register and the counter is decrementing + */ + +/* Bit field enums: */ +typedef enum { + PWM_AQCTLA_ZRO_NoAction = 0x0UL, /*!< no action */ + PWM_AQCTLA_ZRO_Clear = 0x1UL, /*!< clear PWMA/PWMB */ + PWM_AQCTLA_ZRO_Set = 0x2UL, /*!< set PWMA/PWMB */ + PWM_AQCTLA_ZRO_Toggle = 0x3UL, /*!< inverse PWMA/PWMB */ +} PWM_AQCTLA_ZRO_Enum; + +typedef enum { + PWM_AQCTLA_PRD_NoAction = 0x0UL, /*!< no action */ + PWM_AQCTLA_PRD_Clear = 0x1UL, /*!< clear PWMA/PWMB */ + PWM_AQCTLA_PRD_Set = 0x2UL, /*!< set PWMA/PWMB */ + PWM_AQCTLA_PRD_Toggle = 0x3UL, /*!< inverse PWMA/PWMB */ +} PWM_AQCTLA_PRD_Enum; + +typedef enum { + PWM_AQCTLA_CAU_NoAction = 0x0UL, /*!< no action */ + PWM_AQCTLA_CAU_Clear = 0x1UL, /*!< clear PWMA/PWMB */ + PWM_AQCTLA_CAU_Set = 0x2UL, /*!< set PWMA/PWMB */ + PWM_AQCTLA_CAU_Toggle = 0x3UL, /*!< inverse PWMA/PWMB */ +} PWM_AQCTLA_CAU_Enum; + +typedef enum { + PWM_AQCTLA_CAD_NoAction = 0x0UL, /*!< no action */ + PWM_AQCTLA_CAD_Clear = 0x1UL, /*!< clear PWMA/PWMB */ + PWM_AQCTLA_CAD_Set = 0x2UL, /*!< set PWMA/PWMB */ + PWM_AQCTLA_CAD_Toggle = 0x3UL, /*!< inverse PWMA/PWMB */ +} PWM_AQCTLA_CAD_Enum; + +typedef enum { + PWM_AQCTLA_CBU_NoAction = 0x0UL, /*!< no action */ + PWM_AQCTLA_CBU_Clear = 0x1UL, /*!< clear PWMA/PWMB */ + PWM_AQCTLA_CBU_Set = 0x2UL, /*!< set PWMA/PWMB */ + PWM_AQCTLA_CBU_Toggle = 0x3UL, /*!< inverse PWMA/PWMB */ +} PWM_AQCTLA_CBU_Enum; + +typedef enum { + PWM_AQCTLA_CBD_NoAction = 0x0UL, /*!< no action */ + PWM_AQCTLA_CBD_Clear = 0x1UL, /*!< clear PWMA/PWMB */ + PWM_AQCTLA_CBD_Set = 0x2UL, /*!< set PWMA/PWMB */ + PWM_AQCTLA_CBD_Toggle = 0x3UL, /*!< inverse PWMA/PWMB */ +} PWM_AQCTLA_CBD_Enum; + +/*-- AQCTLB: Action-Qualifier Output B Control Register ------------------------------------------------------*/ +typedef struct { + uint32_t ZRO :2; /*!< Action when counter equals zero */ + uint32_t PRD :2; /*!< Action when the counter equals the period */ + uint32_t CAU :2; /*!< Action when the counter equals the active CMPA register and the counter is incrementing */ + uint32_t CAD :2; /*!< Action when the counter equals the active CMPA register and the counter is decrementing */ + uint32_t CBU :2; /*!< Action when the counter equals the active CMPB register and the counter is incrementing */ + uint32_t CBD :2; /*!< Action when the time-base counter equals the active CMPB register and the counter is decrementing + */ +} _PWM_AQCTLB_bits; + +/* Bit field positions: */ +#define PWM_AQCTLB_ZRO_Pos 0 /*!< Action when counter equals zero */ +#define PWM_AQCTLB_PRD_Pos 2 /*!< Action when the counter equals the period */ +#define PWM_AQCTLB_CAU_Pos 4 /*!< Action when the counter equals the active CMPA register and the counter is incrementing */ +#define PWM_AQCTLB_CAD_Pos 6 /*!< Action when the counter equals the active CMPA register and the counter is decrementing */ +#define PWM_AQCTLB_CBU_Pos 8 /*!< Action when the counter equals the active CMPB register and the counter is incrementing */ +#define PWM_AQCTLB_CBD_Pos 10 /*!< Action when the time-base counter equals the active CMPB register and the counter is decrementing + */ + +/* Bit field masks: */ +#define PWM_AQCTLB_ZRO_Msk 0x00000003UL /*!< Action when counter equals zero */ +#define PWM_AQCTLB_PRD_Msk 0x0000000CUL /*!< Action when the counter equals the period */ +#define PWM_AQCTLB_CAU_Msk 0x00000030UL /*!< Action when the counter equals the active CMPA register and the counter is incrementing */ +#define PWM_AQCTLB_CAD_Msk 0x000000C0UL /*!< Action when the counter equals the active CMPA register and the counter is decrementing */ +#define PWM_AQCTLB_CBU_Msk 0x00000300UL /*!< Action when the counter equals the active CMPB register and the counter is incrementing */ +#define PWM_AQCTLB_CBD_Msk 0x00000C00UL /*!< Action when the time-base counter equals the active CMPB register and the counter is decrementing + */ + +/* Bit field enums: */ +typedef enum { + PWM_AQCTLB_ZRO_NoAction = 0x0UL, /*!< no action */ + PWM_AQCTLB_ZRO_Clear = 0x1UL, /*!< clear PWMA/PWMB */ + PWM_AQCTLB_ZRO_Set = 0x2UL, /*!< set PWMA/PWMB */ + PWM_AQCTLB_ZRO_Toggle = 0x3UL, /*!< inverse PWMA/PWMB */ +} PWM_AQCTLB_ZRO_Enum; + +typedef enum { + PWM_AQCTLB_PRD_NoAction = 0x0UL, /*!< no action */ + PWM_AQCTLB_PRD_Clear = 0x1UL, /*!< clear PWMA/PWMB */ + PWM_AQCTLB_PRD_Set = 0x2UL, /*!< set PWMA/PWMB */ + PWM_AQCTLB_PRD_Toggle = 0x3UL, /*!< inverse PWMA/PWMB */ +} PWM_AQCTLB_PRD_Enum; + +typedef enum { + PWM_AQCTLB_CAU_NoAction = 0x0UL, /*!< no action */ + PWM_AQCTLB_CAU_Clear = 0x1UL, /*!< clear PWMA/PWMB */ + PWM_AQCTLB_CAU_Set = 0x2UL, /*!< set PWMA/PWMB */ + PWM_AQCTLB_CAU_Toggle = 0x3UL, /*!< inverse PWMA/PWMB */ +} PWM_AQCTLB_CAU_Enum; + +typedef enum { + PWM_AQCTLB_CAD_NoAction = 0x0UL, /*!< no action */ + PWM_AQCTLB_CAD_Clear = 0x1UL, /*!< clear PWMA/PWMB */ + PWM_AQCTLB_CAD_Set = 0x2UL, /*!< set PWMA/PWMB */ + PWM_AQCTLB_CAD_Toggle = 0x3UL, /*!< inverse PWMA/PWMB */ +} PWM_AQCTLB_CAD_Enum; + +typedef enum { + PWM_AQCTLB_CBU_NoAction = 0x0UL, /*!< no action */ + PWM_AQCTLB_CBU_Clear = 0x1UL, /*!< clear PWMA/PWMB */ + PWM_AQCTLB_CBU_Set = 0x2UL, /*!< set PWMA/PWMB */ + PWM_AQCTLB_CBU_Toggle = 0x3UL, /*!< inverse PWMA/PWMB */ +} PWM_AQCTLB_CBU_Enum; + +typedef enum { + PWM_AQCTLB_CBD_NoAction = 0x0UL, /*!< no action */ + PWM_AQCTLB_CBD_Clear = 0x1UL, /*!< clear PWMA/PWMB */ + PWM_AQCTLB_CBD_Set = 0x2UL, /*!< set PWMA/PWMB */ + PWM_AQCTLB_CBD_Toggle = 0x3UL, /*!< inverse PWMA/PWMB */ +} PWM_AQCTLB_CBD_Enum; + +/*-- AQSFRC: Action-Qualifier Software Force Register --------------------------------------------------------*/ +typedef struct { + uint32_t ACTSFA :2; /*!< Action when one-time software force A is invoked */ + uint32_t OTSFA :1; /*!< One-time software forced event on output A */ + uint32_t ACTSFB :2; /*!< Action when one-time software force B is invoked */ + uint32_t OTSFB :1; /*!< One-time software forced event on output B */ + uint32_t RLDCSF :2; /*!< AQCSFRC active register reload from shadow options */ +} _PWM_AQSFRC_bits; + +/* Bit field positions: */ +#define PWM_AQSFRC_ACTSFA_Pos 0 /*!< Action when one-time software force A is invoked */ +#define PWM_AQSFRC_OTSFA_Pos 2 /*!< One-time software forced event on output A */ +#define PWM_AQSFRC_ACTSFB_Pos 3 /*!< Action when one-time software force B is invoked */ +#define PWM_AQSFRC_OTSFB_Pos 5 /*!< One-time software forced event on output B */ +#define PWM_AQSFRC_RLDCSF_Pos 6 /*!< AQCSFRC active register reload from shadow options */ + +/* Bit field masks: */ +#define PWM_AQSFRC_ACTSFA_Msk 0x00000003UL /*!< Action when one-time software force A is invoked */ +#define PWM_AQSFRC_OTSFA_Msk 0x00000004UL /*!< One-time software forced event on output A */ +#define PWM_AQSFRC_ACTSFB_Msk 0x00000018UL /*!< Action when one-time software force B is invoked */ +#define PWM_AQSFRC_OTSFB_Msk 0x00000020UL /*!< One-time software forced event on output B */ +#define PWM_AQSFRC_RLDCSF_Msk 0x000000C0UL /*!< AQCSFRC active register reload from shadow options */ + +/* Bit field enums: */ +typedef enum { + PWM_AQSFRC_ACTSFA_NoAction = 0x0UL, /*!< no action */ + PWM_AQSFRC_ACTSFA_Clear = 0x1UL, /*!< clear PWMA/PWMB */ + PWM_AQSFRC_ACTSFA_Set = 0x2UL, /*!< set PWMA/PWMB */ + PWM_AQSFRC_ACTSFA_Toggle = 0x3UL, /*!< inverse PWMA/PWMB */ +} PWM_AQSFRC_ACTSFA_Enum; + +typedef enum { + PWM_AQSFRC_ACTSFB_NoAction = 0x0UL, /*!< no action */ + PWM_AQSFRC_ACTSFB_Clear = 0x1UL, /*!< clear PWMA/PWMB */ + PWM_AQSFRC_ACTSFB_Set = 0x2UL, /*!< set PWMA/PWMB */ + PWM_AQSFRC_ACTSFB_Toggle = 0x3UL, /*!< inverse PWMA/PWMB */ +} PWM_AQSFRC_ACTSFB_Enum; + +typedef enum { + PWM_AQSFRC_RLDCSF_CTREqZero = 0x0UL, /*!< load when CTR = 0 */ + PWM_AQSFRC_RLDCSF_CTREqPRD = 0x1UL, /*!< load when CTR = PRD */ + PWM_AQSFRC_RLDCSF_CTREqZeroPRD = 0x2UL, /*!< load when CTR = 0 or CTR = PRD */ + PWM_AQSFRC_RLDCSF_NoShadow = 0x3UL, /*!< load immediatelly */ +} PWM_AQSFRC_RLDCSF_Enum; + +/*-- AQCSFRC: Action-Qualifier Continuous Software Force Register --------------------------------------------*/ +typedef struct { + uint32_t CSFA :2; /*!< Continuous software force on output A */ + uint32_t CSFB :2; /*!< Continuous software force on output B */ +} _PWM_AQCSFRC_bits; + +/* Bit field positions: */ +#define PWM_AQCSFRC_CSFA_Pos 0 /*!< Continuous software force on output A */ +#define PWM_AQCSFRC_CSFB_Pos 2 /*!< Continuous software force on output B */ + +/* Bit field masks: */ +#define PWM_AQCSFRC_CSFA_Msk 0x00000003UL /*!< Continuous software force on output A */ +#define PWM_AQCSFRC_CSFB_Msk 0x0000000CUL /*!< Continuous software force on output B */ + +/* Bit field enums: */ +typedef enum { + PWM_AQCSFRC_CSFA_NoAction = 0x0UL, /*!< no action */ + PWM_AQCSFRC_CSFA_Clear = 0x1UL, /*!< clear PWMA/PWMB */ + PWM_AQCSFRC_CSFA_Set = 0x2UL, /*!< set PWMA/PWMB */ +} PWM_AQCSFRC_CSFA_Enum; + +typedef enum { + PWM_AQCSFRC_CSFB_NoAction = 0x0UL, /*!< no action */ + PWM_AQCSFRC_CSFB_Clear = 0x1UL, /*!< clear PWMA/PWMB */ + PWM_AQCSFRC_CSFB_Set = 0x2UL, /*!< set PWMA/PWMB */ +} PWM_AQCSFRC_CSFB_Enum; + +/*-- DBCTL: Dead-Band Generator Control Register -------------------------------------------------------------*/ +typedef struct { + uint32_t OUTMODE :2; /*!< Dead-band output mode control */ + uint32_t POLSEL :2; /*!< Polarity select control */ + uint32_t INMODE :2; /*!< Dead band input mode control */ +} _PWM_DBCTL_bits; + +/* Bit field positions: */ +#define PWM_DBCTL_OUTMODE_Pos 0 /*!< Dead-band output mode control */ +#define PWM_DBCTL_POLSEL_Pos 2 /*!< Polarity select control */ +#define PWM_DBCTL_INMODE_Pos 4 /*!< Dead band input mode control */ + +/* Bit field masks: */ +#define PWM_DBCTL_OUTMODE_Msk 0x00000003UL /*!< Dead-band output mode control */ +#define PWM_DBCTL_POLSEL_Msk 0x0000000CUL /*!< Polarity select control */ +#define PWM_DBCTL_INMODE_Msk 0x00000030UL /*!< Dead band input mode control */ + +/* Bit field enums: */ +typedef enum { + PWM_DBCTL_OUTMODE_NoSpec = 0x0UL, /*!< edge for deadtime is no specified */ + PWM_DBCTL_OUTMODE_BNeg = 0x1UL, /*!< deadtime on PWMB negedge */ + PWM_DBCTL_OUTMODE_APos = 0x2UL, /*!< deadtime on PWMA posedge */ + PWM_DBCTL_OUTMODE_Apos_BNeg = 0x3UL, /*!< deadtime on PWMA posedge and PWMB negedge */ +} PWM_DBCTL_OUTMODE_Enum; + +typedef enum { + PWM_DBCTL_POLSEL_InvDisable = 0x0UL, /*!< inverse disabled */ + PWM_DBCTL_POLSEL_InvA = 0x1UL, /*!< inverse on PWMA */ + PWM_DBCTL_POLSEL_InvB = 0x2UL, /*!< inverse on PWMB */ + PWM_DBCTL_POLSEL_InvAB = 0x3UL, /*!< inverse on PWMA and PWMB */ +} PWM_DBCTL_POLSEL_Enum; + +typedef enum { + PWM_DBCTL_INMODE_APosNeg = 0x0UL, /*!< PWMA is used for posedge and negedge control */ + PWM_DBCTL_INMODE_ANeg_BPos = 0x1UL, /*!< PWMA is used for negedge and PWMB is used for posedge control */ + PWM_DBCTL_INMODE_APos_BNeg = 0x2UL, /*!< PWMA is used for posedge and PWMB is used for negedge control */ + PWM_DBCTL_INMODE_BPosNeg = 0x3UL, /*!< PWMB is used for posedge and negedge control */ +} PWM_DBCTL_INMODE_Enum; + +/*-- DBRED: Dead-Band Generator Rising Edge Delay Register ---------------------------------------------------*/ +typedef struct { + uint32_t DEL :10; /*!< Rising edge delay count */ +} _PWM_DBRED_bits; + +/* Bit field positions: */ +#define PWM_DBRED_DEL_Pos 0 /*!< Rising edge delay count */ + +/* Bit field masks: */ +#define PWM_DBRED_DEL_Msk 0x000003FFUL /*!< Rising edge delay count */ + +/*-- DBFED: Dead-Band Generator Falling Edge Delay Register --------------------------------------------------*/ +typedef struct { + uint32_t DEL :10; /*!< Falling edge delay count */ +} _PWM_DBFED_bits; + +/* Bit field positions: */ +#define PWM_DBFED_DEL_Pos 0 /*!< Falling edge delay count */ + +/* Bit field masks: */ +#define PWM_DBFED_DEL_Msk 0x000003FFUL /*!< Falling edge delay count */ + +/*-- TZSEL: Trip-Zone Select Register ------------------------------------------------------------------------*/ +typedef struct { + uint32_t CBC :1; /*!< Cycle-by-Cycle trip-zone 0 enable + */ + uint32_t :7; /*!< RESERVED */ + uint32_t OST :1; /*!< One-Shot trip-zone 0 enable */ +} _PWM_TZSEL_bits; + +/* Bit field positions: */ +#define PWM_TZSEL_CBC_Pos 0 /*!< Cycle-by-Cycle trip-zone 0 enable + */ +#define PWM_TZSEL_OST_Pos 8 /*!< One-Shot trip-zone 0 enable */ + +/* Bit field masks: */ +#define PWM_TZSEL_CBC_Msk 0x00000001UL /*!< Cycle-by-Cycle trip-zone 0 enable + */ +#define PWM_TZSEL_OST_Msk 0x00000100UL /*!< One-Shot trip-zone 0 enable */ + +/*-- TZCTL: Trip-Zone Control Register -----------------------------------------------------------------------*/ +typedef struct { + uint32_t TZA :2; /*!< When a trip event occurs the following action is taken on output A */ + uint32_t TZB :2; /*!< When a trip event occurs the following action is taken on output B */ +} _PWM_TZCTL_bits; + +/* Bit field positions: */ +#define PWM_TZCTL_TZA_Pos 0 /*!< When a trip event occurs the following action is taken on output A */ +#define PWM_TZCTL_TZB_Pos 2 /*!< When a trip event occurs the following action is taken on output B */ + +/* Bit field masks: */ +#define PWM_TZCTL_TZA_Msk 0x00000003UL /*!< When a trip event occurs the following action is taken on output A */ +#define PWM_TZCTL_TZB_Msk 0x0000000CUL /*!< When a trip event occurs the following action is taken on output B */ + +/* Bit field enums: */ +typedef enum { + PWM_TZCTL_TZA_Z = 0x0UL, /*!< PWMA/PWMB go to Z on failture */ + PWM_TZCTL_TZA_Set = 0x1UL, /*!< PWMA/PWMB go to 1 on failture */ + PWM_TZCTL_TZA_Clear = 0x2UL, /*!< PWMA/PWMB go to 0 on failture */ + PWM_TZCTL_TZA_NoAction = 0x3UL, /*!< no action on failture */ +} PWM_TZCTL_TZA_Enum; + +typedef enum { + PWM_TZCTL_TZB_Z = 0x0UL, /*!< PWMA/PWMB go to Z on failture */ + PWM_TZCTL_TZB_Set = 0x1UL, /*!< PWMA/PWMB go to 1 on failture */ + PWM_TZCTL_TZB_Clear = 0x2UL, /*!< PWMA/PWMB go to 0 on failture */ + PWM_TZCTL_TZB_NoAction = 0x3UL, /*!< no action on failture */ +} PWM_TZCTL_TZB_Enum; + +/*-- TZEINT: Trip-Zone Enable Interrupt Register -------------------------------------------------------------*/ +typedef struct { + uint32_t :1; /*!< RESERVED */ + uint32_t CBC :1; /*!< Trip-zone Cycle-by-Cycle interrupt enable */ + uint32_t OST :1; /*!< Trip-zone One-Shot interrupt enable */ +} _PWM_TZEINT_bits; + +/* Bit field positions: */ +#define PWM_TZEINT_CBC_Pos 1 /*!< Trip-zone Cycle-by-Cycle interrupt enable */ +#define PWM_TZEINT_OST_Pos 2 /*!< Trip-zone One-Shot interrupt enable */ + +/* Bit field masks: */ +#define PWM_TZEINT_CBC_Msk 0x00000002UL /*!< Trip-zone Cycle-by-Cycle interrupt enable */ +#define PWM_TZEINT_OST_Msk 0x00000004UL /*!< Trip-zone One-Shot interrupt enable */ + +/*-- TZFLG: Trip-Zone Flag Register --------------------------------------------------------------------------*/ +typedef struct { + uint32_t INT :1; /*!< Latched trip interrupt status flag */ + uint32_t CBC :1; /*!< Latched status flag for Cycle-By-Cycle trip event */ + uint32_t OST :1; /*!< Latched status flag for a One-Shot trip event */ +} _PWM_TZFLG_bits; + +/* Bit field positions: */ +#define PWM_TZFLG_INT_Pos 0 /*!< Latched trip interrupt status flag */ +#define PWM_TZFLG_CBC_Pos 1 /*!< Latched status flag for Cycle-By-Cycle trip event */ +#define PWM_TZFLG_OST_Pos 2 /*!< Latched status flag for a One-Shot trip event */ + +/* Bit field masks: */ +#define PWM_TZFLG_INT_Msk 0x00000001UL /*!< Latched trip interrupt status flag */ +#define PWM_TZFLG_CBC_Msk 0x00000002UL /*!< Latched status flag for Cycle-By-Cycle trip event */ +#define PWM_TZFLG_OST_Msk 0x00000004UL /*!< Latched status flag for a One-Shot trip event */ + +/*-- TZCLR: Trip-Zone Clear Register -------------------------------------------------------------------------*/ +typedef struct { + uint32_t INT :1; /*!< Clear trip-zone interrupt flag */ + uint32_t CBC :1; /*!< Clear flag for Cycle-By-Cycle trip latch + */ + uint32_t OST :1; /*!< Clear flag for One-Shot trip latch */ +} _PWM_TZCLR_bits; + +/* Bit field positions: */ +#define PWM_TZCLR_INT_Pos 0 /*!< Clear trip-zone interrupt flag */ +#define PWM_TZCLR_CBC_Pos 1 /*!< Clear flag for Cycle-By-Cycle trip latch + */ +#define PWM_TZCLR_OST_Pos 2 /*!< Clear flag for One-Shot trip latch */ + +/* Bit field masks: */ +#define PWM_TZCLR_INT_Msk 0x00000001UL /*!< Clear trip-zone interrupt flag */ +#define PWM_TZCLR_CBC_Msk 0x00000002UL /*!< Clear flag for Cycle-By-Cycle trip latch + */ +#define PWM_TZCLR_OST_Msk 0x00000004UL /*!< Clear flag for One-Shot trip latch */ + +/*-- TZFRC: Trip-Zone Force Register -------------------------------------------------------------------------*/ +typedef struct { + uint32_t :1; /*!< RESERVED */ + uint32_t CBC :1; /*!< Force a Cycle-by-Cycle trip event via software */ + uint32_t OST :1; /*!< Force a One-Shot trip event via software */ +} _PWM_TZFRC_bits; + +/* Bit field positions: */ +#define PWM_TZFRC_CBC_Pos 1 /*!< Force a Cycle-by-Cycle trip event via software */ +#define PWM_TZFRC_OST_Pos 2 /*!< Force a One-Shot trip event via software */ + +/* Bit field masks: */ +#define PWM_TZFRC_CBC_Msk 0x00000002UL /*!< Force a Cycle-by-Cycle trip event via software */ +#define PWM_TZFRC_OST_Msk 0x00000004UL /*!< Force a One-Shot trip event via software */ + +/*-- ETSEL: Event-Trigger Selection Register -----------------------------------------------------------------*/ +typedef struct { + uint32_t INTSEL :3; /*!< PWM_INT interrupt selection options */ + uint32_t INTEN :1; /*!< Enable PWM_INT interrupt generation */ + uint32_t :4; /*!< RESERVED */ + uint32_t SOCASEL :3; /*!< PWM_SOCA selection Options */ + uint32_t SOCAEN :1; /*!< Enable the ADC start of conversion A PWM_SOCA pulse */ + uint32_t SOCBSEL :3; /*!< PWM_SOCB selection Options */ + uint32_t SOCBEN :1; /*!< Enable the ADC start of conversion B PWM_SOCB pulse */ + uint32_t DRQASEL :3; /*!< PWM A DMA request event selection */ + uint32_t DRQAEN :1; /*!< Enable the DMA request from PWM A */ + uint32_t DRQBSEL :3; /*!< PWM B DMA request event selection */ + uint32_t DRQBEN :1; /*!< Enable the DMA request from PWM B */ +} _PWM_ETSEL_bits; + +/* Bit field positions: */ +#define PWM_ETSEL_INTSEL_Pos 0 /*!< PWM_INT interrupt selection options */ +#define PWM_ETSEL_INTEN_Pos 3 /*!< Enable PWM_INT interrupt generation */ +#define PWM_ETSEL_SOCASEL_Pos 8 /*!< PWM_SOCA selection Options */ +#define PWM_ETSEL_SOCAEN_Pos 11 /*!< Enable the ADC start of conversion A PWM_SOCA pulse */ +#define PWM_ETSEL_SOCBSEL_Pos 12 /*!< PWM_SOCB selection Options */ +#define PWM_ETSEL_SOCBEN_Pos 15 /*!< Enable the ADC start of conversion B PWM_SOCB pulse */ +#define PWM_ETSEL_DRQASEL_Pos 16 /*!< PWM A DMA request event selection */ +#define PWM_ETSEL_DRQAEN_Pos 19 /*!< Enable the DMA request from PWM A */ +#define PWM_ETSEL_DRQBSEL_Pos 20 /*!< PWM B DMA request event selection */ +#define PWM_ETSEL_DRQBEN_Pos 23 /*!< Enable the DMA request from PWM B */ + +/* Bit field masks: */ +#define PWM_ETSEL_INTSEL_Msk 0x00000007UL /*!< PWM_INT interrupt selection options */ +#define PWM_ETSEL_INTEN_Msk 0x00000008UL /*!< Enable PWM_INT interrupt generation */ +#define PWM_ETSEL_SOCASEL_Msk 0x00000700UL /*!< PWM_SOCA selection Options */ +#define PWM_ETSEL_SOCAEN_Msk 0x00000800UL /*!< Enable the ADC start of conversion A PWM_SOCA pulse */ +#define PWM_ETSEL_SOCBSEL_Msk 0x00007000UL /*!< PWM_SOCB selection Options */ +#define PWM_ETSEL_SOCBEN_Msk 0x00008000UL /*!< Enable the ADC start of conversion B PWM_SOCB pulse */ +#define PWM_ETSEL_DRQASEL_Msk 0x00070000UL /*!< PWM A DMA request event selection */ +#define PWM_ETSEL_DRQAEN_Msk 0x00080000UL /*!< Enable the DMA request from PWM A */ +#define PWM_ETSEL_DRQBSEL_Msk 0x00700000UL /*!< PWM B DMA request event selection */ +#define PWM_ETSEL_DRQBEN_Msk 0x00800000UL /*!< Enable the DMA request from PWM B */ + +/* Bit field enums: */ +typedef enum { + PWM_ETSEL_INTSEL_CTREqZero = 0x1UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = 0 */ + PWM_ETSEL_INTSEL_CTREqPRD = 0x2UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = PRD */ + PWM_ETSEL_INTSEL_CTREqCMPA_OnUp = 0x4UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count up */ + PWM_ETSEL_INTSEL_CTREqCMPA_OnDown = 0x5UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count down */ + PWM_ETSEL_INTSEL_CTREqCMPB_OnUp = 0x6UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count up */ + PWM_ETSEL_INTSEL_CTREqCMPB_OnDown = 0x7UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count down */ +} PWM_ETSEL_INTSEL_Enum; + +typedef enum { + PWM_ETSEL_SOCASEL_CTREqZero = 0x1UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = 0 */ + PWM_ETSEL_SOCASEL_CTREqPRD = 0x2UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = PRD */ + PWM_ETSEL_SOCASEL_CTREqCMPA_OnUp = 0x4UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count up */ + PWM_ETSEL_SOCASEL_CTREqCMPA_OnDown = 0x5UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count down */ + PWM_ETSEL_SOCASEL_CTREqCMPB_OnUp = 0x6UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count up */ + PWM_ETSEL_SOCASEL_CTREqCMPB_OnDown = 0x7UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count down */ +} PWM_ETSEL_SOCASEL_Enum; + +typedef enum { + PWM_ETSEL_SOCBSEL_CTREqZero = 0x1UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = 0 */ + PWM_ETSEL_SOCBSEL_CTREqPRD = 0x2UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = PRD */ + PWM_ETSEL_SOCBSEL_CTREqCMPA_OnUp = 0x4UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count up */ + PWM_ETSEL_SOCBSEL_CTREqCMPA_OnDown = 0x5UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count down */ + PWM_ETSEL_SOCBSEL_CTREqCMPB_OnUp = 0x6UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count up */ + PWM_ETSEL_SOCBSEL_CTREqCMPB_OnDown = 0x7UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count down */ +} PWM_ETSEL_SOCBSEL_Enum; + +typedef enum { + PWM_ETSEL_DRQASEL_CTREqZero = 0x1UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = 0 */ + PWM_ETSEL_DRQASEL_CTREqPRD = 0x2UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = PRD */ + PWM_ETSEL_DRQASEL_CTREqCMPA_OnUp = 0x4UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count up */ + PWM_ETSEL_DRQASEL_CTREqCMPA_OnDown = 0x5UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count down */ + PWM_ETSEL_DRQASEL_CTREqCMPB_OnUp = 0x6UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count up */ + PWM_ETSEL_DRQASEL_CTREqCMPB_OnDown = 0x7UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count down */ +} PWM_ETSEL_DRQASEL_Enum; + +typedef enum { + PWM_ETSEL_DRQBSEL_CTREqZero = 0x1UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = 0 */ + PWM_ETSEL_DRQBSEL_CTREqPRD = 0x2UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = PRD */ + PWM_ETSEL_DRQBSEL_CTREqCMPA_OnUp = 0x4UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count up */ + PWM_ETSEL_DRQBSEL_CTREqCMPA_OnDown = 0x5UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count down */ + PWM_ETSEL_DRQBSEL_CTREqCMPB_OnUp = 0x6UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count up */ + PWM_ETSEL_DRQBSEL_CTREqCMPB_OnDown = 0x7UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count down */ +} PWM_ETSEL_DRQBSEL_Enum; + +/*-- ETPS: Event-Trigger Prescale Register -------------------------------------------------------------------*/ +typedef struct { + uint32_t INTPRD :2; /*!< PWM interrupt (PWM_INT) period select */ + uint32_t INTCNT :2; /*!< PWM interrupt event (PWM_INT) counter register */ + uint32_t :4; /*!< RESERVED */ + uint32_t SOCAPRD :2; /*!< PWM ADC Start-of-Conversion A event (PWM_SOCA) period select */ + uint32_t SOCACNT :2; /*!< PWM ADC Start-of-Conversion A event (PWM_SOCA) counter register */ + uint32_t SOCBPRD :2; /*!< PWM ADC Start-of-Conversion B event (PWM_SOCB) period select */ + uint32_t SOCBCNT :2; /*!< PWM ADC Start-of-Conversion B event (PWM_SOCB) counter register */ + uint32_t DRQAPRD :2; /*!< PWM DMA request A period select */ + uint32_t DRQACNT :2; /*!< PWM DMA request event A counter */ + uint32_t DRQBPRD :2; /*!< PWM DMA request B period select */ + uint32_t DRQBCNT :2; /*!< PWM DMA request event B counter */ +} _PWM_ETPS_bits; + +/* Bit field positions: */ +#define PWM_ETPS_INTPRD_Pos 0 /*!< PWM interrupt (PWM_INT) period select */ +#define PWM_ETPS_INTCNT_Pos 2 /*!< PWM interrupt event (PWM_INT) counter register */ +#define PWM_ETPS_SOCAPRD_Pos 8 /*!< PWM ADC Start-of-Conversion A event (PWM_SOCA) period select */ +#define PWM_ETPS_SOCACNT_Pos 10 /*!< PWM ADC Start-of-Conversion A event (PWM_SOCA) counter register */ +#define PWM_ETPS_SOCBPRD_Pos 12 /*!< PWM ADC Start-of-Conversion B event (PWM_SOCB) period select */ +#define PWM_ETPS_SOCBCNT_Pos 14 /*!< PWM ADC Start-of-Conversion B event (PWM_SOCB) counter register */ +#define PWM_ETPS_DRQAPRD_Pos 16 /*!< PWM DMA request A period select */ +#define PWM_ETPS_DRQACNT_Pos 18 /*!< PWM DMA request event A counter */ +#define PWM_ETPS_DRQBPRD_Pos 20 /*!< PWM DMA request B period select */ +#define PWM_ETPS_DRQBCNT_Pos 22 /*!< PWM DMA request event B counter */ + +/* Bit field masks: */ +#define PWM_ETPS_INTPRD_Msk 0x00000003UL /*!< PWM interrupt (PWM_INT) period select */ +#define PWM_ETPS_INTCNT_Msk 0x0000000CUL /*!< PWM interrupt event (PWM_INT) counter register */ +#define PWM_ETPS_SOCAPRD_Msk 0x00000300UL /*!< PWM ADC Start-of-Conversion A event (PWM_SOCA) period select */ +#define PWM_ETPS_SOCACNT_Msk 0x00000C00UL /*!< PWM ADC Start-of-Conversion A event (PWM_SOCA) counter register */ +#define PWM_ETPS_SOCBPRD_Msk 0x00003000UL /*!< PWM ADC Start-of-Conversion B event (PWM_SOCB) period select */ +#define PWM_ETPS_SOCBCNT_Msk 0x0000C000UL /*!< PWM ADC Start-of-Conversion B event (PWM_SOCB) counter register */ +#define PWM_ETPS_DRQAPRD_Msk 0x00030000UL /*!< PWM DMA request A period select */ +#define PWM_ETPS_DRQACNT_Msk 0x000C0000UL /*!< PWM DMA request event A counter */ +#define PWM_ETPS_DRQBPRD_Msk 0x00300000UL /*!< PWM DMA request B period select */ +#define PWM_ETPS_DRQBCNT_Msk 0x00C00000UL /*!< PWM DMA request event B counter */ + +/*-- ETFLG: Event-Trigger Flag Register ----------------------------------------------------------------------*/ +typedef struct { + uint32_t INT :1; /*!< Latched PWM Interrupt (PWM_INT) status flag */ + uint32_t :1; /*!< RESERVED */ + uint32_t SOCA :1; /*!< Latched PWM ADC Start-of-Conversion A (PWM_SOCA) status flag */ + uint32_t SOCB :1; /*!< Latched PWM ADC Start-of-Conversion B (PWM_SOCB) status flag */ + uint32_t DRQA :1; /*!< Latched PWM DMA request A status flag */ + uint32_t DRQB :1; /*!< Latched PWM DMA request B status flag */ +} _PWM_ETFLG_bits; + +/* Bit field positions: */ +#define PWM_ETFLG_INT_Pos 0 /*!< Latched PWM Interrupt (PWM_INT) status flag */ +#define PWM_ETFLG_SOCA_Pos 2 /*!< Latched PWM ADC Start-of-Conversion A (PWM_SOCA) status flag */ +#define PWM_ETFLG_SOCB_Pos 3 /*!< Latched PWM ADC Start-of-Conversion B (PWM_SOCB) status flag */ +#define PWM_ETFLG_DRQA_Pos 4 /*!< Latched PWM DMA request A status flag */ +#define PWM_ETFLG_DRQB_Pos 5 /*!< Latched PWM DMA request B status flag */ + +/* Bit field masks: */ +#define PWM_ETFLG_INT_Msk 0x00000001UL /*!< Latched PWM Interrupt (PWM_INT) status flag */ +#define PWM_ETFLG_SOCA_Msk 0x00000004UL /*!< Latched PWM ADC Start-of-Conversion A (PWM_SOCA) status flag */ +#define PWM_ETFLG_SOCB_Msk 0x00000008UL /*!< Latched PWM ADC Start-of-Conversion B (PWM_SOCB) status flag */ +#define PWM_ETFLG_DRQA_Msk 0x00000010UL /*!< Latched PWM DMA request A status flag */ +#define PWM_ETFLG_DRQB_Msk 0x00000020UL /*!< Latched PWM DMA request B status flag */ + +/*-- ETCLR: Event-Trigger Clear Register ---------------------------------------------------------------------*/ +typedef struct { + uint32_t INT :1; /*!< Latched PWM Interrupt (PWM_INT) flag clear bit */ + uint32_t :1; /*!< RESERVED */ + uint32_t SOCA :1; /*!< Latched PWM ADC Start-of-Conversion A (PWM_SOCA) flag clear bit */ + uint32_t SOCB :1; /*!< Latched PWM ADC Start-of-Conversion B (PWM_SOCB) flag clear bit */ + uint32_t DRQA :1; /*!< Latched PWM DMA request A flag clear bit */ + uint32_t DRQB :1; /*!< Latched PWM DMA request B flag clear bit */ +} _PWM_ETCLR_bits; + +/* Bit field positions: */ +#define PWM_ETCLR_INT_Pos 0 /*!< Latched PWM Interrupt (PWM_INT) flag clear bit */ +#define PWM_ETCLR_SOCA_Pos 2 /*!< Latched PWM ADC Start-of-Conversion A (PWM_SOCA) flag clear bit */ +#define PWM_ETCLR_SOCB_Pos 3 /*!< Latched PWM ADC Start-of-Conversion B (PWM_SOCB) flag clear bit */ +#define PWM_ETCLR_DRQA_Pos 4 /*!< Latched PWM DMA request A flag clear bit */ +#define PWM_ETCLR_DRQB_Pos 5 /*!< Latched PWM DMA request B flag clear bit */ + +/* Bit field masks: */ +#define PWM_ETCLR_INT_Msk 0x00000001UL /*!< Latched PWM Interrupt (PWM_INT) flag clear bit */ +#define PWM_ETCLR_SOCA_Msk 0x00000004UL /*!< Latched PWM ADC Start-of-Conversion A (PWM_SOCA) flag clear bit */ +#define PWM_ETCLR_SOCB_Msk 0x00000008UL /*!< Latched PWM ADC Start-of-Conversion B (PWM_SOCB) flag clear bit */ +#define PWM_ETCLR_DRQA_Msk 0x00000010UL /*!< Latched PWM DMA request A flag clear bit */ +#define PWM_ETCLR_DRQB_Msk 0x00000020UL /*!< Latched PWM DMA request B flag clear bit */ + +/*-- ETFRC: Event-Trigger Force Register ---------------------------------------------------------------------*/ +typedef struct { + uint32_t INT :1; /*!< PWM_INT force bit. */ + uint32_t :1; /*!< RESERVED */ + uint32_t SOCA :1; /*!< PWM_SOCA force bit */ + uint32_t SOCB :1; /*!< PWM_SOCB force bit */ + uint32_t DRQA :1; /*!< PWM DMA request A force bit */ + uint32_t DRQB :1; /*!< PWM DMA request B force bit */ +} _PWM_ETFRC_bits; + +/* Bit field positions: */ +#define PWM_ETFRC_INT_Pos 0 /*!< PWM_INT force bit. */ +#define PWM_ETFRC_SOCA_Pos 2 /*!< PWM_SOCA force bit */ +#define PWM_ETFRC_SOCB_Pos 3 /*!< PWM_SOCB force bit */ +#define PWM_ETFRC_DRQA_Pos 4 /*!< PWM DMA request A force bit */ +#define PWM_ETFRC_DRQB_Pos 5 /*!< PWM DMA request B force bit */ + +/* Bit field masks: */ +#define PWM_ETFRC_INT_Msk 0x00000001UL /*!< PWM_INT force bit. */ +#define PWM_ETFRC_SOCA_Msk 0x00000004UL /*!< PWM_SOCA force bit */ +#define PWM_ETFRC_SOCB_Msk 0x00000008UL /*!< PWM_SOCB force bit */ +#define PWM_ETFRC_DRQA_Msk 0x00000010UL /*!< PWM DMA request A force bit */ +#define PWM_ETFRC_DRQB_Msk 0x00000020UL /*!< PWM DMA request B force bit */ + +/*-- PCCTL: PWM-Chopper Control Register ---------------------------------------------------------------------*/ +typedef struct { + uint32_t CHPEN :1; /*!< PWM-chopping enable */ + uint32_t OSTWTH :4; /*!< One-Shot pulse width */ + uint32_t CHPFREQ :3; /*!< Chopping clock frequency */ + uint32_t CHPDUTY :3; /*!< Chopping clock duty cycle */ +} _PWM_PCCTL_bits; + +/* Bit field positions: */ +#define PWM_PCCTL_CHPEN_Pos 0 /*!< PWM-chopping enable */ +#define PWM_PCCTL_OSTWTH_Pos 1 /*!< One-Shot pulse width */ +#define PWM_PCCTL_CHPFREQ_Pos 5 /*!< Chopping clock frequency */ +#define PWM_PCCTL_CHPDUTY_Pos 8 /*!< Chopping clock duty cycle */ + +/* Bit field masks: */ +#define PWM_PCCTL_CHPEN_Msk 0x00000001UL /*!< PWM-chopping enable */ +#define PWM_PCCTL_OSTWTH_Msk 0x0000001EUL /*!< One-Shot pulse width */ +#define PWM_PCCTL_CHPFREQ_Msk 0x000000E0UL /*!< Chopping clock frequency */ +#define PWM_PCCTL_CHPDUTY_Msk 0x00000700UL /*!< Chopping clock duty cycle */ + +/* Bit field enums: */ +typedef enum { + PWM_PCCTL_CHPFREQ_Div1 = 0x0UL, /*!< sync frequency divide by 1 */ + PWM_PCCTL_CHPFREQ_Div2 = 0x1UL, /*!< sync frequency divide by 2 */ + PWM_PCCTL_CHPFREQ_Div3 = 0x2UL, /*!< sync frequency divide by 3 */ + PWM_PCCTL_CHPFREQ_Div4 = 0x3UL, /*!< sync frequency divide by 4 */ + PWM_PCCTL_CHPFREQ_Div5 = 0x4UL, /*!< sync frequency divide by 5 */ + PWM_PCCTL_CHPFREQ_Div6 = 0x5UL, /*!< sync frequency divide by 6 */ + PWM_PCCTL_CHPFREQ_Div7 = 0x6UL, /*!< sync frequency divide by 7 */ + PWM_PCCTL_CHPFREQ_Div8 = 0x7UL, /*!< sync frequency divide by 8 */ +} PWM_PCCTL_CHPFREQ_Enum; + +typedef enum { + PWM_PCCTL_CHPDUTY_Duty_1_8 = 0x0UL, /*!< duty 1/8 */ + PWM_PCCTL_CHPDUTY_Duty_2_8 = 0x1UL, /*!< duty 2/8 */ + PWM_PCCTL_CHPDUTY_Duty_3_8 = 0x2UL, /*!< duty 3/8 */ + PWM_PCCTL_CHPDUTY_Duty_4_8 = 0x3UL, /*!< duty 4/8 */ + PWM_PCCTL_CHPDUTY_Duty_5_8 = 0x4UL, /*!< duty 5/8 */ + PWM_PCCTL_CHPDUTY_Duty_6_8 = 0x5UL, /*!< duty 6/8 */ + PWM_PCCTL_CHPDUTY_Duty_7_8 = 0x6UL, /*!< duty 7/8 */ +} PWM_PCCTL_CHPDUTY_Enum; + +/*-- FWDTH: Filter Width select Register ---------------------------------------------------------------------*/ +typedef struct { + uint32_t VAL :8; /*!< Pulse filter width selection */ +} _PWM_FWDTH_bits; + +/* Bit field positions: */ +#define PWM_FWDTH_VAL_Pos 0 /*!< Pulse filter width selection */ + +/* Bit field masks: */ +#define PWM_FWDTH_VAL_Msk 0x000000FFUL /*!< Pulse filter width selection */ + +/*-- HDSEL: Hold Detector event Select Register --------------------------------------------------------------*/ +typedef struct { + uint32_t ADCDC0 :1; /*!< Hold detector event by ADC Digital Comparator 0 enable */ + uint32_t ADCDC1 :1; /*!< Hold detector event by ADC Digital Comparator 1 enable */ + uint32_t ADCDC2 :1; /*!< Hold detector event by ADC Digital Comparator 2 enable */ + uint32_t ADCDC3 :1; /*!< Hold detector event by ADC Digital Comparator 3 enable */ + uint32_t :24; /*!< RESERVED */ + uint32_t CBC :1; /*!< Cycle-by-Cycle hold detector enable */ + uint32_t :2; /*!< RESERVED */ + uint32_t OST :1; /*!< One-Shot hold detector enable */ +} _PWM_HDSEL_bits; + +/* Bit field positions: */ +#define PWM_HDSEL_ADCDC0_Pos 0 /*!< Hold detector event by ADC Digital Comparator 0 enable */ +#define PWM_HDSEL_ADCDC1_Pos 1 /*!< Hold detector event by ADC Digital Comparator 1 enable */ +#define PWM_HDSEL_ADCDC2_Pos 2 /*!< Hold detector event by ADC Digital Comparator 2 enable */ +#define PWM_HDSEL_ADCDC3_Pos 3 /*!< Hold detector event by ADC Digital Comparator 3 enable */ +#define PWM_HDSEL_CBC_Pos 28 /*!< Cycle-by-Cycle hold detector enable */ +#define PWM_HDSEL_OST_Pos 31 /*!< One-Shot hold detector enable */ + +/* Bit field masks: */ +#define PWM_HDSEL_ADCDC0_Msk 0x00000001UL /*!< Hold detector event by ADC Digital Comparator 0 enable */ +#define PWM_HDSEL_ADCDC1_Msk 0x00000002UL /*!< Hold detector event by ADC Digital Comparator 1 enable */ +#define PWM_HDSEL_ADCDC2_Msk 0x00000004UL /*!< Hold detector event by ADC Digital Comparator 2 enable */ +#define PWM_HDSEL_ADCDC3_Msk 0x00000008UL /*!< Hold detector event by ADC Digital Comparator 3 enable */ +#define PWM_HDSEL_CBC_Msk 0x10000000UL /*!< Cycle-by-Cycle hold detector enable */ +#define PWM_HDSEL_OST_Msk 0x80000000UL /*!< One-Shot hold detector enable */ + +/*-- HDCTL: Hold Detector Control register -------------------------------------------------------------------*/ +typedef struct { + uint32_t HDA :2; /*!< Action when hold detection A is invoked */ + uint32_t HDB :2; /*!< Action when hold detection B is invoked */ +} _PWM_HDCTL_bits; + +/* Bit field positions: */ +#define PWM_HDCTL_HDA_Pos 0 /*!< Action when hold detection A is invoked */ +#define PWM_HDCTL_HDB_Pos 2 /*!< Action when hold detection B is invoked */ + +/* Bit field masks: */ +#define PWM_HDCTL_HDA_Msk 0x00000003UL /*!< Action when hold detection A is invoked */ +#define PWM_HDCTL_HDB_Msk 0x0000000CUL /*!< Action when hold detection B is invoked */ + +/* Bit field enums: */ +typedef enum { + PWM_HDCTL_HDA_Set = 0x1UL, /*!< PWMA/PWMB go to 1 on failture */ + PWM_HDCTL_HDA_Clear = 0x2UL, /*!< PWMA/PWMB go to 0 on failture */ + PWM_HDCTL_HDA_NoAction = 0x3UL, /*!< no action on failture */ +} PWM_HDCTL_HDA_Enum; + +typedef enum { + PWM_HDCTL_HDB_Set = 0x1UL, /*!< PWMA/PWMB go to 1 on failture */ + PWM_HDCTL_HDB_Clear = 0x2UL, /*!< PWMA/PWMB go to 0 on failture */ + PWM_HDCTL_HDB_NoAction = 0x3UL, /*!< no action on failture */ +} PWM_HDCTL_HDB_Enum; + +/*-- HDEINT: Hold Detector Enable Interrupt Register ---------------------------------------------------------*/ +typedef struct { + uint32_t :1; /*!< RESERVED */ + uint32_t CBC :1; /*!< Hold detector Cycle-by-Cycle interrupt enable */ + uint32_t OST :1; /*!< Hold detector One-Shot interrupt enable */ +} _PWM_HDEINT_bits; + +/* Bit field positions: */ +#define PWM_HDEINT_CBC_Pos 1 /*!< Hold detector Cycle-by-Cycle interrupt enable */ +#define PWM_HDEINT_OST_Pos 2 /*!< Hold detector One-Shot interrupt enable */ + +/* Bit field masks: */ +#define PWM_HDEINT_CBC_Msk 0x00000002UL /*!< Hold detector Cycle-by-Cycle interrupt enable */ +#define PWM_HDEINT_OST_Msk 0x00000004UL /*!< Hold detector One-Shot interrupt enable */ + +/*-- HDFLG: Hold Detector Flag Register ----------------------------------------------------------------------*/ +typedef struct { + uint32_t INT :1; /*!< Latched hold detector interrupt status flag */ + uint32_t CBC :1; /*!< Latched status flag for hold detector Cycle-by-Cycle event */ + uint32_t OST :1; /*!< Latched status flag for hold detector One-Shot event */ +} _PWM_HDFLG_bits; + +/* Bit field positions: */ +#define PWM_HDFLG_INT_Pos 0 /*!< Latched hold detector interrupt status flag */ +#define PWM_HDFLG_CBC_Pos 1 /*!< Latched status flag for hold detector Cycle-by-Cycle event */ +#define PWM_HDFLG_OST_Pos 2 /*!< Latched status flag for hold detector One-Shot event */ + +/* Bit field masks: */ +#define PWM_HDFLG_INT_Msk 0x00000001UL /*!< Latched hold detector interrupt status flag */ +#define PWM_HDFLG_CBC_Msk 0x00000002UL /*!< Latched status flag for hold detector Cycle-by-Cycle event */ +#define PWM_HDFLG_OST_Msk 0x00000004UL /*!< Latched status flag for hold detector One-Shot event */ + +/*-- HDCLR: Register clear HD flag ---------------------------------------------------------------------------*/ +typedef struct { + uint32_t INT :1; /*!< Clear hold detector interrupt flag */ + uint32_t CBC :1; /*!< Clear flag for Cycle-By-Cycle hold detector latch + */ + uint32_t OST :1; /*!< Clear flag for One-Shot hold detector latch */ +} _PWM_HDCLR_bits; + +/* Bit field positions: */ +#define PWM_HDCLR_INT_Pos 0 /*!< Clear hold detector interrupt flag */ +#define PWM_HDCLR_CBC_Pos 1 /*!< Clear flag for Cycle-By-Cycle hold detector latch + */ +#define PWM_HDCLR_OST_Pos 2 /*!< Clear flag for One-Shot hold detector latch */ + +/* Bit field masks: */ +#define PWM_HDCLR_INT_Msk 0x00000001UL /*!< Clear hold detector interrupt flag */ +#define PWM_HDCLR_CBC_Msk 0x00000002UL /*!< Clear flag for Cycle-By-Cycle hold detector latch + */ +#define PWM_HDCLR_OST_Msk 0x00000004UL /*!< Clear flag for One-Shot hold detector latch */ + +/*-- HDFRC: Hold Detector Force Register ---------------------------------------------------------------------*/ +typedef struct { + uint32_t :1; /*!< RESERVED */ + uint32_t CBC :1; /*!< Force a Cycle-by-Cycle hold detector event via software */ + uint32_t OST :1; /*!< Force a One-Shot hold detector event via software */ +} _PWM_HDFRC_bits; + +/* Bit field positions: */ +#define PWM_HDFRC_CBC_Pos 1 /*!< Force a Cycle-by-Cycle hold detector event via software */ +#define PWM_HDFRC_OST_Pos 2 /*!< Force a One-Shot hold detector event via software */ + +/* Bit field masks: */ +#define PWM_HDFRC_CBC_Msk 0x00000002UL /*!< Force a Cycle-by-Cycle hold detector event via software */ +#define PWM_HDFRC_OST_Msk 0x00000004UL /*!< Force a One-Shot hold detector event via software */ + +/*-- HDINTCLR: Hold Detector Interrupt pending Clear Register ------------------------------------------------*/ +typedef struct { + uint32_t INT :1; /*!< Clear HD interrupt pending */ +} _PWM_HDINTCLR_bits; + +/* Bit field positions: */ +#define PWM_HDINTCLR_INT_Pos 0 /*!< Clear HD interrupt pending */ + +/* Bit field masks: */ +#define PWM_HDINTCLR_INT_Msk 0x00000001UL /*!< Clear HD interrupt pending */ + +/*-- TZINTCLR: Trip-Zone Interrupt pending Clear Register ----------------------------------------------------*/ +typedef struct { + uint32_t INT :1; /*!< Clear TZ interrupt pending */ +} _PWM_TZINTCLR_bits; + +/* Bit field positions: */ +#define PWM_TZINTCLR_INT_Pos 0 /*!< Clear TZ interrupt pending */ + +/* Bit field masks: */ +#define PWM_TZINTCLR_INT_Msk 0x00000001UL /*!< Clear TZ interrupt pending */ + +/*-- INTCLR: PWM Interrupt pending Clear Register ------------------------------------------------------------*/ +typedef struct { + uint32_t INT :1; /*!< Clear interrupt pending */ +} _PWM_INTCLR_bits; + +/* Bit field positions: */ +#define PWM_INTCLR_INT_Pos 0 /*!< Clear interrupt pending */ + +/* Bit field masks: */ +#define PWM_INTCLR_INT_Msk 0x00000001UL /*!< Clear interrupt pending */ + +typedef struct { + union { /*!< Time-Base Control Register */ + __IO uint32_t TBCTL; /*!< TBCTL : type used for word access */ + __IO _PWM_TBCTL_bits TBCTL_bit; /*!< TBCTL_bit: structure used for bit access */ + }; + union { /*!< Time-Base Status Register */ + __IO uint32_t TBSTS; /*!< TBSTS : type used for word access */ + __IO _PWM_TBSTS_bits TBSTS_bit; /*!< TBSTS_bit: structure used for bit access */ + }; + union { /*!< Time-Base Phase Register */ + __IO uint32_t TBPHS; /*!< TBPHS : type used for word access */ + __IO _PWM_TBPHS_bits TBPHS_bit; /*!< TBPHS_bit: structure used for bit access */ + }; + union { /*!< Time-Base Counter Register */ + __IO uint32_t TBCTR; /*!< TBCTR : type used for word access */ + __IO _PWM_TBCTR_bits TBCTR_bit; /*!< TBCTR_bit: structure used for bit access */ + }; + union { /*!< Time-Base Period Register */ + __IO uint32_t TBPRD; /*!< TBPRD : type used for word access */ + __IO _PWM_TBPRD_bits TBPRD_bit; /*!< TBPRD_bit: structure used for bit access */ + }; + union { /*!< Counter-Compare Control Register */ + __IO uint32_t CMPCTL; /*!< CMPCTL : type used for word access */ + __IO _PWM_CMPCTL_bits CMPCTL_bit; /*!< CMPCTL_bit: structure used for bit access */ + }; + union { /*!< Counter-Compare A Register */ + __IO uint32_t CMPA; /*!< CMPA : type used for word access */ + __IO _PWM_CMPA_bits CMPA_bit; /*!< CMPA_bit: structure used for bit access */ + }; + union { /*!< Counter-Compare B Register */ + __IO uint32_t CMPB; /*!< CMPB : type used for word access */ + __IO _PWM_CMPB_bits CMPB_bit; /*!< CMPB_bit: structure used for bit access */ + }; + union { /*!< Action-Qualifier Output A Control Register */ + __IO uint32_t AQCTLA; /*!< AQCTLA : type used for word access */ + __IO _PWM_AQCTLA_bits AQCTLA_bit; /*!< AQCTLA_bit: structure used for bit access */ + }; + union { /*!< Action-Qualifier Output B Control Register */ + __IO uint32_t AQCTLB; /*!< AQCTLB : type used for word access */ + __IO _PWM_AQCTLB_bits AQCTLB_bit; /*!< AQCTLB_bit: structure used for bit access */ + }; + union { /*!< Action-Qualifier Software Force Register */ + __IO uint32_t AQSFRC; /*!< AQSFRC : type used for word access */ + __IO _PWM_AQSFRC_bits AQSFRC_bit; /*!< AQSFRC_bit: structure used for bit access */ + }; + union { /*!< Action-Qualifier Continuous Software Force Register */ + __IO uint32_t AQCSFRC; /*!< AQCSFRC : type used for word access */ + __IO _PWM_AQCSFRC_bits AQCSFRC_bit; /*!< AQCSFRC_bit: structure used for bit access */ + }; + union { /*!< Dead-Band Generator Control Register */ + __IO uint32_t DBCTL; /*!< DBCTL : type used for word access */ + __IO _PWM_DBCTL_bits DBCTL_bit; /*!< DBCTL_bit: structure used for bit access */ + }; + union { /*!< Dead-Band Generator Rising Edge Delay Register */ + __IO uint32_t DBRED; /*!< DBRED : type used for word access */ + __IO _PWM_DBRED_bits DBRED_bit; /*!< DBRED_bit: structure used for bit access */ + }; + union { /*!< Dead-Band Generator Falling Edge Delay Register */ + __IO uint32_t DBFED; /*!< DBFED : type used for word access */ + __IO _PWM_DBFED_bits DBFED_bit; /*!< DBFED_bit: structure used for bit access */ + }; + union { /*!< Trip-Zone Select Register */ + __IO uint32_t TZSEL; /*!< TZSEL : type used for word access */ + __IO _PWM_TZSEL_bits TZSEL_bit; /*!< TZSEL_bit: structure used for bit access */ + }; + union { /*!< Trip-Zone Control Register */ + __IO uint32_t TZCTL; /*!< TZCTL : type used for word access */ + __IO _PWM_TZCTL_bits TZCTL_bit; /*!< TZCTL_bit: structure used for bit access */ + }; + union { /*!< Trip-Zone Enable Interrupt Register */ + __IO uint32_t TZEINT; /*!< TZEINT : type used for word access */ + __IO _PWM_TZEINT_bits TZEINT_bit; /*!< TZEINT_bit: structure used for bit access */ + }; + union { /*!< Trip-Zone Flag Register */ + __I uint32_t TZFLG; /*!< TZFLG : type used for word access */ + __I _PWM_TZFLG_bits TZFLG_bit; /*!< TZFLG_bit: structure used for bit access */ + }; + union { /*!< Trip-Zone Clear Register */ + __IO uint32_t TZCLR; /*!< TZCLR : type used for word access */ + __IO _PWM_TZCLR_bits TZCLR_bit; /*!< TZCLR_bit: structure used for bit access */ + }; + union { /*!< Trip-Zone Force Register */ + __IO uint32_t TZFRC; /*!< TZFRC : type used for word access */ + __IO _PWM_TZFRC_bits TZFRC_bit; /*!< TZFRC_bit: structure used for bit access */ + }; + union { /*!< Event-Trigger Selection Register */ + __IO uint32_t ETSEL; /*!< ETSEL : type used for word access */ + __IO _PWM_ETSEL_bits ETSEL_bit; /*!< ETSEL_bit: structure used for bit access */ + }; + union { /*!< Event-Trigger Prescale Register */ + __IO uint32_t ETPS; /*!< ETPS : type used for word access */ + __IO _PWM_ETPS_bits ETPS_bit; /*!< ETPS_bit: structure used for bit access */ + }; + union { /*!< Event-Trigger Flag Register */ + __I uint32_t ETFLG; /*!< ETFLG : type used for word access */ + __I _PWM_ETFLG_bits ETFLG_bit; /*!< ETFLG_bit: structure used for bit access */ + }; + union { /*!< Event-Trigger Clear Register */ + __IO uint32_t ETCLR; /*!< ETCLR : type used for word access */ + __IO _PWM_ETCLR_bits ETCLR_bit; /*!< ETCLR_bit: structure used for bit access */ + }; + union { /*!< Event-Trigger Force Register */ + __IO uint32_t ETFRC; /*!< ETFRC : type used for word access */ + __IO _PWM_ETFRC_bits ETFRC_bit; /*!< ETFRC_bit: structure used for bit access */ + }; + union { /*!< PWM-Chopper Control Register */ + __IO uint32_t PCCTL; /*!< PCCTL : type used for word access */ + __IO _PWM_PCCTL_bits PCCTL_bit; /*!< PCCTL_bit: structure used for bit access */ + }; + __IO uint32_t Reserved0; + union { /*!< Filter Width select Register */ + __IO uint32_t FWDTH; /*!< FWDTH : type used for word access */ + __IO _PWM_FWDTH_bits FWDTH_bit; /*!< FWDTH_bit: structure used for bit access */ + }; + __IO uint32_t Reserved1[5]; + union { /*!< Hold Detector event Select Register */ + __IO uint32_t HDSEL; /*!< HDSEL : type used for word access */ + __IO _PWM_HDSEL_bits HDSEL_bit; /*!< HDSEL_bit: structure used for bit access */ + }; + union { /*!< Hold Detector Control register */ + __IO uint32_t HDCTL; /*!< HDCTL : type used for word access */ + __IO _PWM_HDCTL_bits HDCTL_bit; /*!< HDCTL_bit: structure used for bit access */ + }; + union { /*!< Hold Detector Enable Interrupt Register */ + __IO uint32_t HDEINT; /*!< HDEINT : type used for word access */ + __IO _PWM_HDEINT_bits HDEINT_bit; /*!< HDEINT_bit: structure used for bit access */ + }; + union { /*!< Hold Detector Flag Register */ + __I uint32_t HDFLG; /*!< HDFLG : type used for word access */ + __I _PWM_HDFLG_bits HDFLG_bit; /*!< HDFLG_bit: structure used for bit access */ + }; + union { /*!< Register clear HD flag */ + __IO uint32_t HDCLR; /*!< HDCLR : type used for word access */ + __IO _PWM_HDCLR_bits HDCLR_bit; /*!< HDCLR_bit: structure used for bit access */ + }; + union { /*!< Hold Detector Force Register */ + __IO uint32_t HDFRC; /*!< HDFRC : type used for word access */ + __IO _PWM_HDFRC_bits HDFRC_bit; /*!< HDFRC_bit: structure used for bit access */ + }; + union { /*!< Hold Detector Interrupt pending Clear Register */ + __O uint32_t HDINTCLR; /*!< HDINTCLR : type used for word access */ + __O _PWM_HDINTCLR_bits HDINTCLR_bit; /*!< HDINTCLR_bit: structure used for bit access */ + }; + union { /*!< Trip-Zone Interrupt pending Clear Register */ + __O uint32_t TZINTCLR; /*!< TZINTCLR : type used for word access */ + __O _PWM_TZINTCLR_bits TZINTCLR_bit; /*!< TZINTCLR_bit: structure used for bit access */ + }; + union { /*!< PWM Interrupt pending Clear Register */ + __O uint32_t INTCLR; /*!< INTCLR : type used for word access */ + __O _PWM_INTCLR_bits INTCLR_bit; /*!< INTCLR_bit: structure used for bit access */ + }; +} PWM_TypeDef; + + +/******************************************************************************/ +/* SPI registers */ +/******************************************************************************/ + +/*-- CR0: Control register 0 ---------------------------------------------------------------------------------*/ +typedef struct { + uint32_t DSS :4; /*!< Size of data */ + uint32_t FRF :2; /*!< Select protocol */ + uint32_t SPO :1; /*!< Polarity SSPCLKOUT */ + uint32_t SPH :1; /*!< Phase SSPCLKOUT */ + uint32_t SCR :8; /*!< Value divider */ +} _SPI_CR0_bits; + +/* Bit field positions: */ +#define SPI_CR0_DSS_Pos 0 /*!< Size of data */ +#define SPI_CR0_FRF_Pos 4 /*!< Select protocol */ +#define SPI_CR0_SPO_Pos 6 /*!< Polarity SSPCLKOUT */ +#define SPI_CR0_SPH_Pos 7 /*!< Phase SSPCLKOUT */ +#define SPI_CR0_SCR_Pos 8 /*!< Value divider */ + +/* Bit field masks: */ +#define SPI_CR0_DSS_Msk 0x0000000FUL /*!< Size of data */ +#define SPI_CR0_FRF_Msk 0x00000030UL /*!< Select protocol */ +#define SPI_CR0_SPO_Msk 0x00000040UL /*!< Polarity SSPCLKOUT */ +#define SPI_CR0_SPH_Msk 0x00000080UL /*!< Phase SSPCLKOUT */ +#define SPI_CR0_SCR_Msk 0x0000FF00UL /*!< Value divider */ + +/* Bit field enums: */ +typedef enum { + SPI_CR0_DSS_4bit = 0x3UL, /*!< data size 4 bit */ + SPI_CR0_DSS_5bit = 0x4UL, /*!< data size 5 bit */ + SPI_CR0_DSS_6bit = 0x5UL, /*!< data size 6 bit */ + SPI_CR0_DSS_7bit = 0x6UL, /*!< data size 7 bit */ + SPI_CR0_DSS_8bit = 0x7UL, /*!< data size 8 bit */ + SPI_CR0_DSS_9bit = 0x8UL, /*!< data size 9 bit */ + SPI_CR0_DSS_10bit = 0x9UL, /*!< data size 10 bit */ + SPI_CR0_DSS_11bit = 0xAUL, /*!< data size 11 bit */ + SPI_CR0_DSS_12bit = 0xBUL, /*!< data size 12 bit */ + SPI_CR0_DSS_13bit = 0xCUL, /*!< data size 13 bit */ + SPI_CR0_DSS_14bit = 0xDUL, /*!< data size 14 bit */ + SPI_CR0_DSS_15bit = 0xEUL, /*!< data size 15 bit */ + SPI_CR0_DSS_16bit = 0xFUL, /*!< data size 16 bit */ +} SPI_CR0_DSS_Enum; + +typedef enum { + SPI_CR0_FRF_SPI = 0x0UL, /*!< SPI of Motorola */ + SPI_CR0_FRF_SSI = 0x1UL, /*!< SSI of Texas Instruments */ + SPI_CR0_FRF_Microwire = 0x2UL, /*!< Microwire of National Semiconductor */ +} SPI_CR0_FRF_Enum; + +/*-- CR1: Control register 1 ---------------------------------------------------------------------------------*/ +typedef struct { + uint32_t :1; /*!< RESERVED */ + uint32_t SSE :1; /*!< Enable transceiver */ + uint32_t MS :1; /*!< Select mode */ + uint32_t SOD :1; /*!< Disable bit data */ + uint32_t :4; /*!< RESERVED */ + uint32_t RXIFLSEL :4; /*!< Receive interrupt FIFO level select */ + uint32_t TXIFLSEL :4; /*!< Transmit interrupt FIFO level select */ +} _SPI_CR1_bits; + +/* Bit field positions: */ +#define SPI_CR1_SSE_Pos 1 /*!< Enable transceiver */ +#define SPI_CR1_MS_Pos 2 /*!< Select mode */ +#define SPI_CR1_SOD_Pos 3 /*!< Disable bit data */ +#define SPI_CR1_RXIFLSEL_Pos 8 /*!< Receive interrupt FIFO level select */ +#define SPI_CR1_TXIFLSEL_Pos 12 /*!< Transmit interrupt FIFO level select */ + +/* Bit field masks: */ +#define SPI_CR1_SSE_Msk 0x00000002UL /*!< Enable transceiver */ +#define SPI_CR1_MS_Msk 0x00000004UL /*!< Select mode */ +#define SPI_CR1_SOD_Msk 0x00000008UL /*!< Disable bit data */ +#define SPI_CR1_RXIFLSEL_Msk 0x00000F00UL /*!< Receive interrupt FIFO level select */ +#define SPI_CR1_TXIFLSEL_Msk 0x0000F000UL /*!< Transmit interrupt FIFO level select */ + +/*-- DR: Data register ---------------------------------------------------------------------------------------*/ +typedef struct { + uint32_t DATA :16; /*!< */ +} _SPI_DR_bits; + +/* Bit field positions: */ +#define SPI_DR_DATA_Pos 0 /*!< */ + +/* Bit field masks: */ +#define SPI_DR_DATA_Msk 0x0000FFFFUL /*!< */ + +/*-- SR: State register --------------------------------------------------------------------------------------*/ +typedef struct { + uint32_t TFE :1; /*!< FIFO buffer empty flag transmitter */ + uint32_t TNF :1; /*!< Indicator the transmitter FIFO buffer is not full */ + uint32_t RNE :1; /*!< Indicate not empty receive buffer */ + uint32_t RFF :1; /*!< Indicate full receive buffer */ + uint32_t BSY :1; /*!< Activity flag */ +} _SPI_SR_bits; + +/* Bit field positions: */ +#define SPI_SR_TFE_Pos 0 /*!< FIFO buffer empty flag transmitter */ +#define SPI_SR_TNF_Pos 1 /*!< Indicator the transmitter FIFO buffer is not full */ +#define SPI_SR_RNE_Pos 2 /*!< Indicate not empty receive buffer */ +#define SPI_SR_RFF_Pos 3 /*!< Indicate full receive buffer */ +#define SPI_SR_BSY_Pos 4 /*!< Activity flag */ + +/* Bit field masks: */ +#define SPI_SR_TFE_Msk 0x00000001UL /*!< FIFO buffer empty flag transmitter */ +#define SPI_SR_TNF_Msk 0x00000002UL /*!< Indicator the transmitter FIFO buffer is not full */ +#define SPI_SR_RNE_Msk 0x00000004UL /*!< Indicate not empty receive buffer */ +#define SPI_SR_RFF_Msk 0x00000008UL /*!< Indicate full receive buffer */ +#define SPI_SR_BSY_Msk 0x00000010UL /*!< Activity flag */ + +/*-- CPSR: Clock division factor register --------------------------------------------------------------------*/ +typedef struct { + uint32_t CPSDVSR :8; /*!< Clock division factor. Bit0 always 0 */ +} _SPI_CPSR_bits; + +/* Bit field positions: */ +#define SPI_CPSR_CPSDVSR_Pos 0 /*!< Clock division factor. Bit0 always 0 */ + +/* Bit field masks: */ +#define SPI_CPSR_CPSDVSR_Msk 0x000000FFUL /*!< Clock division factor. Bit0 always 0 */ + +/*-- IMSC: Mask interrupt register ---------------------------------------------------------------------------*/ +typedef struct { + uint32_t RORIM :1; /*!< Interrupt mask bit SSPRORINTR buffer overflow receiver */ + uint32_t RTIM :1; /*!< Interrupt mask bit SSPRTINTR timeout receiver */ + uint32_t RXIM :1; /*!< SSPRXINTR interrupt mask bit to fill 50% or less of the receiver FIFO buffer */ + uint32_t TXIM :1; /*!< SSPTXINTR interrupt mask bit to fill 50% or less of the FIFO buffer of the transmitter */ +} _SPI_IMSC_bits; + +/* Bit field positions: */ +#define SPI_IMSC_RORIM_Pos 0 /*!< Interrupt mask bit SSPRORINTR buffer overflow receiver */ +#define SPI_IMSC_RTIM_Pos 1 /*!< Interrupt mask bit SSPRTINTR timeout receiver */ +#define SPI_IMSC_RXIM_Pos 2 /*!< SSPRXINTR interrupt mask bit to fill 50% or less of the receiver FIFO buffer */ +#define SPI_IMSC_TXIM_Pos 3 /*!< SSPTXINTR interrupt mask bit to fill 50% or less of the FIFO buffer of the transmitter */ + +/* Bit field masks: */ +#define SPI_IMSC_RORIM_Msk 0x00000001UL /*!< Interrupt mask bit SSPRORINTR buffer overflow receiver */ +#define SPI_IMSC_RTIM_Msk 0x00000002UL /*!< Interrupt mask bit SSPRTINTR timeout receiver */ +#define SPI_IMSC_RXIM_Msk 0x00000004UL /*!< SSPRXINTR interrupt mask bit to fill 50% or less of the receiver FIFO buffer */ +#define SPI_IMSC_TXIM_Msk 0x00000008UL /*!< SSPTXINTR interrupt mask bit to fill 50% or less of the FIFO buffer of the transmitter */ + +/*-- RIS: Status register interrupt without mask -------------------------------------------------------------*/ +typedef struct { + uint32_t RORRIS :1; /*!< Interrupt status before masking SSPRORINTR */ + uint32_t RTRIS :1; /*!< Interrupt status before masking SSPRTINTR */ + uint32_t RXRIS :1; /*!< Interrupt status before masking SSPRXINTR */ + uint32_t TXRIS :1; /*!< Interrupt status before masking SSPTXINTR */ +} _SPI_RIS_bits; + +/* Bit field positions: */ +#define SPI_RIS_RORRIS_Pos 0 /*!< Interrupt status before masking SSPRORINTR */ +#define SPI_RIS_RTRIS_Pos 1 /*!< Interrupt status before masking SSPRTINTR */ +#define SPI_RIS_RXRIS_Pos 2 /*!< Interrupt status before masking SSPRXINTR */ +#define SPI_RIS_TXRIS_Pos 3 /*!< Interrupt status before masking SSPTXINTR */ + +/* Bit field masks: */ +#define SPI_RIS_RORRIS_Msk 0x00000001UL /*!< Interrupt status before masking SSPRORINTR */ +#define SPI_RIS_RTRIS_Msk 0x00000002UL /*!< Interrupt status before masking SSPRTINTR */ +#define SPI_RIS_RXRIS_Msk 0x00000004UL /*!< Interrupt status before masking SSPRXINTR */ +#define SPI_RIS_TXRIS_Msk 0x00000008UL /*!< Interrupt status before masking SSPTXINTR */ + +/*-- MIS: Status register interrupt masking account ----------------------------------------------------------*/ +typedef struct { + uint32_t RORRIS :1; /*!< Masked interrupt status SSPRORINTR */ + uint32_t RTRIS :1; /*!< Masked interrupt status SSPRTINTR */ + uint32_t RXRIS :1; /*!< Masked interrupt status SSPRXINTR */ + uint32_t TXRIS :1; /*!< Masked interrupt status SSPTXINTR */ +} _SPI_MIS_bits; + +/* Bit field positions: */ +#define SPI_MIS_RORRIS_Pos 0 /*!< Masked interrupt status SSPRORINTR */ +#define SPI_MIS_RTRIS_Pos 1 /*!< Masked interrupt status SSPRTINTR */ +#define SPI_MIS_RXRIS_Pos 2 /*!< Masked interrupt status SSPRXINTR */ +#define SPI_MIS_TXRIS_Pos 3 /*!< Masked interrupt status SSPTXINTR */ + +/* Bit field masks: */ +#define SPI_MIS_RORRIS_Msk 0x00000001UL /*!< Masked interrupt status SSPRORINTR */ +#define SPI_MIS_RTRIS_Msk 0x00000002UL /*!< Masked interrupt status SSPRTINTR */ +#define SPI_MIS_RXRIS_Msk 0x00000004UL /*!< Masked interrupt status SSPRXINTR */ +#define SPI_MIS_TXRIS_Msk 0x00000008UL /*!< Masked interrupt status SSPTXINTR */ + +/*-- ICR: Register reset interrupt ---------------------------------------------------------------------------*/ +typedef struct { + uint32_t RORIC :1; /*!< Reset interrupt SSPRORINTR */ + uint32_t RTIC :1; /*!< Reset interrupt SSPRTINTR */ +} _SPI_ICR_bits; + +/* Bit field positions: */ +#define SPI_ICR_RORIC_Pos 0 /*!< Reset interrupt SSPRORINTR */ +#define SPI_ICR_RTIC_Pos 1 /*!< Reset interrupt SSPRTINTR */ + +/* Bit field masks: */ +#define SPI_ICR_RORIC_Msk 0x00000001UL /*!< Reset interrupt SSPRORINTR */ +#define SPI_ICR_RTIC_Msk 0x00000002UL /*!< Reset interrupt SSPRTINTR */ + +/*-- DMACR: Control register DMA -----------------------------------------------------------------------------*/ +typedef struct { + uint32_t RXDMAE :1; /*!< DMA enable bit at reception */ + uint32_t TXDMAE :1; /*!< DMA enable bit transmission */ +} _SPI_DMACR_bits; + +/* Bit field positions: */ +#define SPI_DMACR_RXDMAE_Pos 0 /*!< DMA enable bit at reception */ +#define SPI_DMACR_TXDMAE_Pos 1 /*!< DMA enable bit transmission */ + +/* Bit field masks: */ +#define SPI_DMACR_RXDMAE_Msk 0x00000001UL /*!< DMA enable bit at reception */ +#define SPI_DMACR_TXDMAE_Msk 0x00000002UL /*!< DMA enable bit transmission */ + +typedef struct { + union { /*!< Control register 0 */ + __IO uint32_t CR0; /*!< CR0 : type used for word access */ + __IO _SPI_CR0_bits CR0_bit; /*!< CR0_bit: structure used for bit access */ + }; + union { /*!< Control register 1 */ + __IO uint32_t CR1; /*!< CR1 : type used for word access */ + __IO _SPI_CR1_bits CR1_bit; /*!< CR1_bit: structure used for bit access */ + }; + union { /*!< Data register */ + __IO uint32_t DR; /*!< DR : type used for word access */ + __IO _SPI_DR_bits DR_bit; /*!< DR_bit: structure used for bit access */ + }; + union { /*!< State register */ + __I uint32_t SR; /*!< SR : type used for word access */ + __I _SPI_SR_bits SR_bit; /*!< SR_bit: structure used for bit access */ + }; + union { /*!< Clock division factor register */ + __IO uint32_t CPSR; /*!< CPSR : type used for word access */ + __IO _SPI_CPSR_bits CPSR_bit; /*!< CPSR_bit: structure used for bit access */ + }; + union { /*!< Mask interrupt register */ + __IO uint32_t IMSC; /*!< IMSC : type used for word access */ + __IO _SPI_IMSC_bits IMSC_bit; /*!< IMSC_bit: structure used for bit access */ + }; + union { /*!< Status register interrupt without mask */ + __I uint32_t RIS; /*!< RIS : type used for word access */ + __I _SPI_RIS_bits RIS_bit; /*!< RIS_bit: structure used for bit access */ + }; + union { /*!< Status register interrupt masking account */ + __I uint32_t MIS; /*!< MIS : type used for word access */ + __I _SPI_MIS_bits MIS_bit; /*!< MIS_bit: structure used for bit access */ + }; + union { /*!< Register reset interrupt */ + __O uint32_t ICR; /*!< ICR : type used for word access */ + __O _SPI_ICR_bits ICR_bit; /*!< ICR_bit: structure used for bit access */ + }; + union { /*!< Control register DMA */ + __IO uint32_t DMACR; /*!< DMACR : type used for word access */ + __IO _SPI_DMACR_bits DMACR_bit; /*!< DMACR_bit: structure used for bit access */ + }; +} SPI_TypeDef; + + +/******************************************************************************/ +/* I2C registers */ +/******************************************************************************/ + +/*-- SDA: Data register --------------------------------------------------------------------------------------*/ +typedef struct { + uint32_t DATA :8; /*!< Data field */ +} _I2C_SDA_bits; + +/* Bit field positions: */ +#define I2C_SDA_DATA_Pos 0 /*!< Data field */ + +/* Bit field masks: */ +#define I2C_SDA_DATA_Msk 0x000000FFUL /*!< Data field */ + +/*-- ST: Status register -------------------------------------------------------------------------------------*/ +typedef struct { + uint32_t MODE :6; /*!< Status code */ + uint32_t :1; /*!< RESERVED */ + uint32_t INT :1; /*!< Interrupt flag */ +} _I2C_ST_bits; + +/* Bit field positions: */ +#define I2C_ST_MODE_Pos 0 /*!< Status code */ +#define I2C_ST_INT_Pos 7 /*!< Interrupt flag */ + +/* Bit field masks: */ +#define I2C_ST_MODE_Msk 0x0000003FUL /*!< Status code */ +#define I2C_ST_INT_Msk 0x00000080UL /*!< Interrupt flag */ + +/* Bit field enums: */ +typedef enum { + I2C_ST_MODE_IDLE = 0x0UL, /*!< General - Idle, no valid status information available */ + I2C_ST_MODE_STDONE = 0x1UL, /*!< FS master - Start condition generated */ + I2C_ST_MODE_RSDONE = 0x2UL, /*!< FS master - Repeated start condition generated */ + I2C_ST_MODE_IDLARL = 0x3UL, /*!< FS master - Arbitration lost, unaddressed slave mode entered */ + I2C_ST_MODE_MTADPA = 0x4UL, /*!< FS master transmit - Slave address sent, positive ACK */ + I2C_ST_MODE_MTADNA = 0x5UL, /*!< FS master transmit - Slave address sent, negative ACK */ + I2C_ST_MODE_MTDAPA = 0x6UL, /*!< FS master transmit - Data byte sent, positive ACK */ + I2C_ST_MODE_MTDANA = 0x7UL, /*!< FS master transmit - Data byte sent, negative ACK */ + I2C_ST_MODE_MRADPA = 0x8UL, /*!< FS master receive - Slave addres sent, positive ACK */ + I2C_ST_MODE_MRADNA = 0x9UL, /*!< FS master receive - Slave addres sent, negative ACK */ + I2C_ST_MODE_MRDAPA = 0xAUL, /*!< FS master receive - Data byte received, positive ACK */ + I2C_ST_MODE_MRDANA = 0xBUL, /*!< FS master receive - Data byte received, negative ACK */ + I2C_ST_MODE_MTMCER = 0xCUL, /*!< FS master - Mastercode transmitted, error detected (positive ACK) */ + I2C_ST_MODE_SRADPA = 0x10UL, /*!< FS slave receive - Slave address received, positive ACK */ + I2C_ST_MODE_SRAAPA = 0x11UL, /*!< FS slave receive - Slave address received after arbitration loss, positive ACK */ + I2C_ST_MODE_SRDAPA = 0x12UL, /*!< FS slave receive - Data byte received, positive ACK */ + I2C_ST_MODE_SRDANA = 0x13UL, /*!< FS slave receive - Data byte received, negative ACK */ + I2C_ST_MODE_STADPA = 0x14UL, /*!< FS slave transmit - Slave address received, positive ACK */ + I2C_ST_MODE_STAAPA = 0x15UL, /*!< FS slave transmit - Slave address received, negative ACK */ + I2C_ST_MODE_STDAPA = 0x16UL, /*!< FS slave transmit - Data byte sent, positive ACK */ + I2C_ST_MODE_STDANA = 0x17UL, /*!< FS slave transmit - Data byte sent, negative ACK */ + I2C_ST_MODE_SATADP = 0x18UL, /*!< FS slave transmit alert response - Alert response address received, positive ACK */ + I2C_ST_MODE_SATAAP = 0x19UL, /*!< FS slave transmit alert response - Alert response address received after arbitration loss, positive ACK */ + I2C_ST_MODE_SATDAP = 0x1AUL, /*!< FS slave transmit alert response - Alert response data byte sent, positive ACK */ + I2C_ST_MODE_SATDAN = 0x1BUL, /*!< FS slave transmit alert response - Alert response data byte sent, negative ACK */ + I2C_ST_MODE_SSTOP = 0x1CUL, /*!< FS slave - Slave mode stop condition detected */ + I2C_ST_MODE_SGADPA = 0x1DUL, /*!< FS slave - Global call address received, positive ACK */ + I2C_ST_MODE_SDAAPA = 0x1EUL, /*!< FS slave - Global call address received after arbitration loss, positive ACK */ + I2C_ST_MODE_BERROR = 0x1FUL, /*!< General - Bus error detected (invalid start or stop condition */ + I2C_ST_MODE_HMTMCOK = 0x21UL, /*!< HS master - Master code transmitted OK - switched to HS mode */ + I2C_ST_MODE_HRSDONE = 0x22UL, /*!< HS master - Repeated start condition generated */ + I2C_ST_MODE_HIDLARL = 0x23UL, /*!< HS master - Arbitration lost, HS unaddressed slave mode entered */ + I2C_ST_MODE_HMTADPA = 0x24UL, /*!< HS master transmit - Slave address sent, positive ACK */ + I2C_ST_MODE_HMTADNA = 0x25UL, /*!< HS master transmit - Slave address sent, negative ACK */ + I2C_ST_MODE_HMTDAPA = 0x26UL, /*!< HS master transmit - Data byte sent, positive ACK */ + I2C_ST_MODE_HMTDANA = 0x27UL, /*!< HS master transmit - Data byte sent, negative ACK */ + I2C_ST_MODE_HMRADPA = 0x28UL, /*!< HS master receive - Slave address sent, positive ACK */ + I2C_ST_MODE_HMRADNA = 0x29UL, /*!< HS master receive - Slave address sent, negative ACK */ + I2C_ST_MODE_HMRDAPA = 0x2AUL, /*!< HS master receive - Data byte received, positive ACK */ + I2C_ST_MODE_HMRDANA = 0x2BUL, /*!< HS master receive - Data byte received, negative ACK */ + I2C_ST_MODE_HSRADPA = 0x30UL, /*!< HS slave receive - Slave address received, positive ACK */ + I2C_ST_MODE_HSRDAPA = 0x32UL, /*!< HS slave receive - Data byte received, positive ACK */ + I2C_ST_MODE_HSRDANA = 0x33UL, /*!< HS slave receive - Data byte received, negative ACK */ + I2C_ST_MODE_HSTADPA = 0x34UL, /*!< HS slave transmit - Slave address received, positive ACK */ + I2C_ST_MODE_HSTDAPA = 0x36UL, /*!< HS slave transmit - Data byte sent, positive ACK */ + I2C_ST_MODE_HSTDANA = 0x37UL, /*!< HS slave transmit - Data byte sent, negative ACK */ +} I2C_ST_MODE_Enum; + +/*-- CST: Status and control register ------------------------------------------------------------------------*/ +typedef struct { + uint32_t BB :1; /*!< Bus Busy */ + uint32_t TOCDIV :2; /*!< SMBus Timeout Divider */ + uint32_t TOERR :1; /*!< SMBus Timeout Error */ + uint32_t TSDA :1; /*!< Bit test SDA */ + uint32_t TGSCL :1; /*!< Toggle SCL */ + uint32_t PECNEXT :1; /*!< PEC Next */ + uint32_t PECFAULT :1; /*!< Packet Error Fault */ +} _I2C_CST_bits; + +/* Bit field positions: */ +#define I2C_CST_BB_Pos 0 /*!< Bus Busy */ +#define I2C_CST_TOCDIV_Pos 1 /*!< SMBus Timeout Divider */ +#define I2C_CST_TOERR_Pos 3 /*!< SMBus Timeout Error */ +#define I2C_CST_TSDA_Pos 4 /*!< Bit test SDA */ +#define I2C_CST_TGSCL_Pos 5 /*!< Toggle SCL */ +#define I2C_CST_PECNEXT_Pos 6 /*!< PEC Next */ +#define I2C_CST_PECFAULT_Pos 7 /*!< Packet Error Fault */ + +/* Bit field masks: */ +#define I2C_CST_BB_Msk 0x00000001UL /*!< Bus Busy */ +#define I2C_CST_TOCDIV_Msk 0x00000006UL /*!< SMBus Timeout Divider */ +#define I2C_CST_TOERR_Msk 0x00000008UL /*!< SMBus Timeout Error */ +#define I2C_CST_TSDA_Msk 0x00000010UL /*!< Bit test SDA */ +#define I2C_CST_TGSCL_Msk 0x00000020UL /*!< Toggle SCL */ +#define I2C_CST_PECNEXT_Msk 0x00000040UL /*!< PEC Next */ +#define I2C_CST_PECFAULT_Msk 0x00000080UL /*!< Packet Error Fault */ + +/* Bit field enums: */ +typedef enum { + I2C_CST_TOCDIV_Disable = 0x0UL, /*!< disable clock */ + I2C_CST_TOCDIV_Div4 = 0x1UL, /*!< clock divided by 4 */ + I2C_CST_TOCDIV_Div8 = 0x2UL, /*!< clock divided by 8 */ + I2C_CST_TOCDIV_Div16 = 0x3UL, /*!< clock divided by 16 */ +} I2C_CST_TOCDIV_Enum; + +/*-- CTL0: Control register 0 --------------------------------------------------------------------------------*/ +typedef struct { + uint32_t START :1; /*!< Start bit */ + uint32_t STOP :1; /*!< Stop bit */ + uint32_t INTEN :1; /*!< Interrupt enable bit */ + uint32_t :1; /*!< RESERVED */ + uint32_t ACK :1; /*!< Acknowledge bit */ + uint32_t GCMEN :1; /*!< Global call match enable */ + uint32_t SMBARE :1; /*!< SMBus Alert Response Match Enable */ + uint32_t CLRST :1; /*!< Clear interrupt status */ +} _I2C_CTL0_bits; + +/* Bit field positions: */ +#define I2C_CTL0_START_Pos 0 /*!< Start bit */ +#define I2C_CTL0_STOP_Pos 1 /*!< Stop bit */ +#define I2C_CTL0_INTEN_Pos 2 /*!< Interrupt enable bit */ +#define I2C_CTL0_ACK_Pos 4 /*!< Acknowledge bit */ +#define I2C_CTL0_GCMEN_Pos 5 /*!< Global call match enable */ +#define I2C_CTL0_SMBARE_Pos 6 /*!< SMBus Alert Response Match Enable */ +#define I2C_CTL0_CLRST_Pos 7 /*!< Clear interrupt status */ + +/* Bit field masks: */ +#define I2C_CTL0_START_Msk 0x00000001UL /*!< Start bit */ +#define I2C_CTL0_STOP_Msk 0x00000002UL /*!< Stop bit */ +#define I2C_CTL0_INTEN_Msk 0x00000004UL /*!< Interrupt enable bit */ +#define I2C_CTL0_ACK_Msk 0x00000010UL /*!< Acknowledge bit */ +#define I2C_CTL0_GCMEN_Msk 0x00000020UL /*!< Global call match enable */ +#define I2C_CTL0_SMBARE_Msk 0x00000040UL /*!< SMBus Alert Response Match Enable */ +#define I2C_CTL0_CLRST_Msk 0x00000080UL /*!< Clear interrupt status */ + +/*-- ADDR: Register own address ------------------------------------------------------------------------------*/ +typedef struct { + uint32_t ADDR :7; /*!< Own 7-bit address */ + uint32_t SAEN :1; /*!< Enable address recognition */ +} _I2C_ADDR_bits; + +/* Bit field positions: */ +#define I2C_ADDR_ADDR_Pos 0 /*!< Own 7-bit address */ +#define I2C_ADDR_SAEN_Pos 7 /*!< Enable address recognition */ + +/* Bit field masks: */ +#define I2C_ADDR_ADDR_Msk 0x0000007FUL /*!< Own 7-bit address */ +#define I2C_ADDR_SAEN_Msk 0x00000080UL /*!< Enable address recognition */ + +/*-- CTL1: Control register 1 --------------------------------------------------------------------------------*/ +typedef struct { + uint32_t ENABLE :1; /*!< Enable I2C */ + uint32_t SCLFRQ :7; /*!< SCL frequency (bits [6:0]) */ +} _I2C_CTL1_bits; + +/* Bit field positions: */ +#define I2C_CTL1_ENABLE_Pos 0 /*!< Enable I2C */ +#define I2C_CTL1_SCLFRQ_Pos 1 /*!< SCL frequency (bits [6:0]) */ + +/* Bit field masks: */ +#define I2C_CTL1_ENABLE_Msk 0x00000001UL /*!< Enable I2C */ +#define I2C_CTL1_SCLFRQ_Msk 0x000000FEUL /*!< SCL frequency (bits [6:0]) */ + +/*-- TOPR: Prescaler load register ---------------------------------------------------------------------------*/ +typedef struct { + uint32_t SMBTOPR :8; /*!< Prescaler reload value */ +} _I2C_TOPR_bits; + +/* Bit field positions: */ +#define I2C_TOPR_SMBTOPR_Pos 0 /*!< Prescaler reload value */ + +/* Bit field masks: */ +#define I2C_TOPR_SMBTOPR_Msk 0x000000FFUL /*!< Prescaler reload value */ + +/*-- CTL2: Control register 2 --------------------------------------------------------------------------------*/ +typedef struct { + uint32_t S10ADR :3; /*!< Upper bits of 10-bit slave address */ + uint32_t S10EN :1; /*!< Enabled 10-bit slave address */ + uint32_t HSDIV :4; /*!< SCL frequency select in HS master mode (bits [3:0]) */ +} _I2C_CTL2_bits; + +/* Bit field positions: */ +#define I2C_CTL2_S10ADR_Pos 0 /*!< Upper bits of 10-bit slave address */ +#define I2C_CTL2_S10EN_Pos 3 /*!< Enabled 10-bit slave address */ +#define I2C_CTL2_HSDIV_Pos 4 /*!< SCL frequency select in HS master mode (bits [3:0]) */ + +/* Bit field masks: */ +#define I2C_CTL2_S10ADR_Msk 0x00000007UL /*!< Upper bits of 10-bit slave address */ +#define I2C_CTL2_S10EN_Msk 0x00000008UL /*!< Enabled 10-bit slave address */ +#define I2C_CTL2_HSDIV_Msk 0x000000F0UL /*!< SCL frequency select in HS master mode (bits [3:0]) */ + +/*-- CTL3: Control register 3 --------------------------------------------------------------------------------*/ +typedef struct { + uint32_t SCLFRQ :8; /*!< SCL frequency (bits [14:7]) */ +} _I2C_CTL3_bits; + +/* Bit field positions: */ +#define I2C_CTL3_SCLFRQ_Pos 0 /*!< SCL frequency (bits [14:7]) */ + +/* Bit field masks: */ +#define I2C_CTL3_SCLFRQ_Msk 0x000000FFUL /*!< SCL frequency (bits [14:7]) */ + +/*-- CTL4: Control Register 4 --------------------------------------------------------------------------------*/ +typedef struct { + uint32_t HSDIV :8; /*!< SCL frequency select in HS master mode (bits [11:4]) */ +} _I2C_CTL4_bits; + +/* Bit field positions: */ +#define I2C_CTL4_HSDIV_Pos 0 /*!< SCL frequency select in HS master mode (bits [11:4]) */ + +/* Bit field masks: */ +#define I2C_CTL4_HSDIV_Msk 0x000000FFUL /*!< SCL frequency select in HS master mode (bits [11:4]) */ + +typedef struct { + union { /*!< Data register */ + __IO uint32_t SDA; /*!< SDA : type used for word access */ + __IO _I2C_SDA_bits SDA_bit; /*!< SDA_bit: structure used for bit access */ + }; + union { /*!< Status register */ + __I uint32_t ST; /*!< ST : type used for word access */ + __I _I2C_ST_bits ST_bit; /*!< ST_bit: structure used for bit access */ + }; + union { /*!< Status and control register */ + __IO uint32_t CST; /*!< CST : type used for word access */ + __IO _I2C_CST_bits CST_bit; /*!< CST_bit: structure used for bit access */ + }; + union { /*!< Control register 0 */ + __IO uint32_t CTL0; /*!< CTL0 : type used for word access */ + __IO _I2C_CTL0_bits CTL0_bit; /*!< CTL0_bit: structure used for bit access */ + }; + union { /*!< Register own address */ + __IO uint32_t ADDR; /*!< ADDR : type used for word access */ + __IO _I2C_ADDR_bits ADDR_bit; /*!< ADDR_bit: structure used for bit access */ + }; + union { /*!< Control register 1 */ + __IO uint32_t CTL1; /*!< CTL1 : type used for word access */ + __IO _I2C_CTL1_bits CTL1_bit; /*!< CTL1_bit: structure used for bit access */ + }; + union { /*!< Prescaler load register */ + __IO uint32_t TOPR; /*!< TOPR : type used for word access */ + __IO _I2C_TOPR_bits TOPR_bit; /*!< TOPR_bit: structure used for bit access */ + }; + union { /*!< Control register 2 */ + __IO uint32_t CTL2; /*!< CTL2 : type used for word access */ + __IO _I2C_CTL2_bits CTL2_bit; /*!< CTL2_bit: structure used for bit access */ + }; + union { /*!< Control register 3 */ + __IO uint32_t CTL3; /*!< CTL3 : type used for word access */ + __IO _I2C_CTL3_bits CTL3_bit; /*!< CTL3_bit: structure used for bit access */ + }; + union { /*!< Control Register 4 */ + __IO uint32_t CTL4; /*!< CTL4 : type used for word access */ + __IO _I2C_CTL4_bits CTL4_bit; /*!< CTL4_bit: structure used for bit access */ + }; +} I2C_TypeDef; + + +/******************************************************************************/ +/* CAN registers */ +/******************************************************************************/ + +/*-- CLC: CAN Clock Control Register -------------------------------------------------------------------------*/ +typedef struct { + uint32_t DISR :1; /*!< Module Disable Request bit */ + uint32_t DISS :1; /*!< Module Disable Status Bit */ +} _CAN_CLC_bits; + +/* Bit field positions: */ +#define CAN_CLC_DISR_Pos 0 /*!< Module Disable Request bit */ +#define CAN_CLC_DISS_Pos 1 /*!< Module Disable Status Bit */ + +/* Bit field masks: */ +#define CAN_CLC_DISR_Msk 0x00000001UL /*!< Module Disable Request bit */ +#define CAN_CLC_DISS_Msk 0x00000002UL /*!< Module Disable Status Bit */ + +/*-- ID: Module Identification Register ----------------------------------------------------------------------*/ +typedef struct { + uint32_t MODREV :8; /*!< Module Revision Number */ + uint32_t MODTYPE :8; /*!< Module type */ + uint32_t MODNUM :16; /*!< Module Number Value */ +} _CAN_ID_bits; + +/* Bit field positions: */ +#define CAN_ID_MODREV_Pos 0 /*!< Module Revision Number */ +#define CAN_ID_MODTYPE_Pos 8 /*!< Module type */ +#define CAN_ID_MODNUM_Pos 16 /*!< Module Number Value */ + +/* Bit field masks: */ +#define CAN_ID_MODREV_Msk 0x000000FFUL /*!< Module Revision Number */ +#define CAN_ID_MODTYPE_Msk 0x0000FF00UL /*!< Module type */ +#define CAN_ID_MODNUM_Msk 0xFFFF0000UL /*!< Module Number Value */ + +/*-- FDR: Fractional Divider Register ------------------------------------------------------------------------*/ +typedef struct { + uint32_t STEP :10; /*!< Step Value */ + uint32_t :1; /*!< RESERVED */ + uint32_t SM :1; /*!< Suspend Mode */ + uint32_t SC :2; /*!< Suspend Control */ + uint32_t DM :2; /*!< Divider Mode */ + uint32_t RESULT :10; /*!< Result Value */ + uint32_t :2; /*!< RESERVED */ + uint32_t SUSACK :1; /*!< Suspend Mode Acknowledge */ + uint32_t SUSREQ :1; /*!< Suspend Mode Request */ + uint32_t ENHW :1; /*!< Enable Hardware Clock Control */ + uint32_t DISCLK :1; /*!< Disable Clock */ +} _CAN_FDR_bits; + +/* Bit field positions: */ +#define CAN_FDR_STEP_Pos 0 /*!< Step Value */ +#define CAN_FDR_SM_Pos 11 /*!< Suspend Mode */ +#define CAN_FDR_SC_Pos 12 /*!< Suspend Control */ +#define CAN_FDR_DM_Pos 14 /*!< Divider Mode */ +#define CAN_FDR_RESULT_Pos 16 /*!< Result Value */ +#define CAN_FDR_SUSACK_Pos 28 /*!< Suspend Mode Acknowledge */ +#define CAN_FDR_SUSREQ_Pos 29 /*!< Suspend Mode Request */ +#define CAN_FDR_ENHW_Pos 30 /*!< Enable Hardware Clock Control */ +#define CAN_FDR_DISCLK_Pos 31 /*!< Disable Clock */ + +/* Bit field masks: */ +#define CAN_FDR_STEP_Msk 0x000003FFUL /*!< Step Value */ +#define CAN_FDR_SM_Msk 0x00000800UL /*!< Suspend Mode */ +#define CAN_FDR_SC_Msk 0x00003000UL /*!< Suspend Control */ +#define CAN_FDR_DM_Msk 0x0000C000UL /*!< Divider Mode */ +#define CAN_FDR_RESULT_Msk 0x03FF0000UL /*!< Result Value */ +#define CAN_FDR_SUSACK_Msk 0x10000000UL /*!< Suspend Mode Acknowledge */ +#define CAN_FDR_SUSREQ_Msk 0x20000000UL /*!< Suspend Mode Request */ +#define CAN_FDR_ENHW_Msk 0x40000000UL /*!< Enable Hardware Clock Control */ +#define CAN_FDR_DISCLK_Msk 0x80000000UL /*!< Disable Clock */ + +/* Bit field enums: */ +typedef enum { + CAN_FDR_DM_Disable = 0x0UL, /*!< counter disabled */ + CAN_FDR_DM_NormalMode = 0x1UL, /*!< normal operation mode */ + CAN_FDR_DM_DividerMode = 0x2UL, /*!< divider operation mode */ +} CAN_FDR_DM_Enum; + +/*-- LIST: LIST: List Register0 -------------------------------------------------------------------------------*/ +typedef struct { + uint32_t BEGIN :8; /*!< List Begin */ + uint32_t END :8; /*!< List End */ + uint32_t SIZE :8; /*!< List Size */ + uint32_t EMPTY :1; /*!< List Empty Indication */ +} _CAN_LIST_LIST_bits; + +/* Bit field positions: */ +#define CAN_LIST_LIST_BEGIN_Pos 0 /*!< List Begin */ +#define CAN_LIST_LIST_END_Pos 8 /*!< List End */ +#define CAN_LIST_LIST_SIZE_Pos 16 /*!< List Size */ +#define CAN_LIST_LIST_EMPTY_Pos 24 /*!< List Empty Indication */ + +/* Bit field masks: */ +#define CAN_LIST_LIST_BEGIN_Msk 0x000000FFUL /*!< List Begin */ +#define CAN_LIST_LIST_END_Msk 0x0000FF00UL /*!< List End */ +#define CAN_LIST_LIST_SIZE_Msk 0x00FF0000UL /*!< List Size */ +#define CAN_LIST_LIST_EMPTY_Msk 0x01000000UL /*!< List Empty Indication */ + +/*-- MSPND: MSPND: Message Pending Register0 ------------------------------------------------------------------*/ +typedef struct { + uint32_t PND :32; /*!< Message Pending */ +} _CAN_MSPND_MSPND_bits; + +/* Bit field positions: */ +#define CAN_MSPND_MSPND_PND_Pos 0 /*!< Message Pending */ + +/* Bit field masks: */ +#define CAN_MSPND_MSPND_PND_Msk 0xFFFFFFFFUL /*!< Message Pending */ + +/*-- MSID: MSID: Message Index Register0 ----------------------------------------------------------------------*/ +typedef struct { + uint32_t INDEX :8; /*!< Message Pending Index */ +} _CAN_MSID_MSID_bits; + +/* Bit field positions: */ +#define CAN_MSID_MSID_INDEX_Pos 0 /*!< Message Pending Index */ + +/* Bit field masks: */ +#define CAN_MSID_MSID_INDEX_Msk 0x000000FFUL /*!< Message Pending Index */ + +/*-- MSIMASK: Message Index Mask Register --------------------------------------------------------------------*/ +typedef struct { + uint32_t IM :32; /*!< Message Index Mask */ +} _CAN_MSIMASK_bits; + +/* Bit field positions: */ +#define CAN_MSIMASK_IM_Pos 0 /*!< Message Index Mask */ + +/* Bit field masks: */ +#define CAN_MSIMASK_IM_Msk 0xFFFFFFFFUL /*!< Message Index Mask */ + +/*-- PANCTR: Panel Control Register --------------------------------------------------------------------------*/ +typedef struct { + uint32_t PANCMD :8; /*!< Panel Command */ + uint32_t BUSY :1; /*!< Panel Busy Flag */ + uint32_t RBUSY :1; /*!< Result Busy Flag */ + uint32_t :6; /*!< RESERVED */ + uint32_t PANAR1 :8; /*!< Panel argument 1 */ + uint32_t PANAR2 :8; /*!< Panel argument 2 */ +} _CAN_PANCTR_bits; + +/* Bit field positions: */ +#define CAN_PANCTR_PANCMD_Pos 0 /*!< Panel Command */ +#define CAN_PANCTR_BUSY_Pos 8 /*!< Panel Busy Flag */ +#define CAN_PANCTR_RBUSY_Pos 9 /*!< Result Busy Flag */ +#define CAN_PANCTR_PANAR1_Pos 16 /*!< Panel argument 1 */ +#define CAN_PANCTR_PANAR2_Pos 24 /*!< Panel argument 2 */ + +/* Bit field masks: */ +#define CAN_PANCTR_PANCMD_Msk 0x000000FFUL /*!< Panel Command */ +#define CAN_PANCTR_BUSY_Msk 0x00000100UL /*!< Panel Busy Flag */ +#define CAN_PANCTR_RBUSY_Msk 0x00000200UL /*!< Result Busy Flag */ +#define CAN_PANCTR_PANAR1_Msk 0x00FF0000UL /*!< Panel argument 1 */ +#define CAN_PANCTR_PANAR2_Msk 0xFF000000UL /*!< Panel argument 2 */ + +/*-- MCR: ---------------------------------------------------------------------------------------------------*/ +typedef struct { + uint32_t :12; /*!< RESERVED */ + uint32_t MPSEL :4; /*!< Message Pending Selector */ +} _CAN_MCR_bits; + +/* Bit field positions: */ +#define CAN_MCR_MPSEL_Pos 12 /*!< Message Pending Selector */ + +/* Bit field masks: */ +#define CAN_MCR_MPSEL_Msk 0x0000F000UL /*!< Message Pending Selector */ + +/*-- MITR: Module Interrupt Trigger Register -----------------------------------------------------------------*/ +typedef struct { + uint32_t IT :16; /*!< Interrupt Trigger */ +} _CAN_MITR_bits; + +/* Bit field positions: */ +#define CAN_MITR_IT_Pos 0 /*!< Interrupt Trigger */ + +/* Bit field masks: */ +#define CAN_MITR_IT_Msk 0x0000FFFFUL /*!< Interrupt Trigger */ + +/*-- Node: NCR: Node control register0 ------------------------------------------------------------------------*/ +typedef struct { + uint32_t INIT :1; /*!< Node Initialization */ + uint32_t TRIE :1; /*!< Transfer Interrupt Enable */ + uint32_t LECIE :1; /*!< LEC Indicated Error Interrupt Enable */ + uint32_t ALIE :1; /*!< Alert Interrupt Enable */ + uint32_t CANDIS :1; /*!< CAN Disable */ + uint32_t :1; /*!< RESERVED */ + uint32_t CCE :1; /*!< Configuration Change Enable */ + uint32_t CALM :1; /*!< CAN Analyzer Mode */ + uint32_t SUSEN :1; /*!< Suspend Enable */ +} _CAN_Node_NCR_bits; + +/* Bit field positions: */ +#define CAN_Node_NCR_INIT_Pos 0 /*!< Node Initialization */ +#define CAN_Node_NCR_TRIE_Pos 1 /*!< Transfer Interrupt Enable */ +#define CAN_Node_NCR_LECIE_Pos 2 /*!< LEC Indicated Error Interrupt Enable */ +#define CAN_Node_NCR_ALIE_Pos 3 /*!< Alert Interrupt Enable */ +#define CAN_Node_NCR_CANDIS_Pos 4 /*!< CAN Disable */ +#define CAN_Node_NCR_CCE_Pos 6 /*!< Configuration Change Enable */ +#define CAN_Node_NCR_CALM_Pos 7 /*!< CAN Analyzer Mode */ +#define CAN_Node_NCR_SUSEN_Pos 8 /*!< Suspend Enable */ + +/* Bit field masks: */ +#define CAN_Node_NCR_INIT_Msk 0x00000001UL /*!< Node Initialization */ +#define CAN_Node_NCR_TRIE_Msk 0x00000002UL /*!< Transfer Interrupt Enable */ +#define CAN_Node_NCR_LECIE_Msk 0x00000004UL /*!< LEC Indicated Error Interrupt Enable */ +#define CAN_Node_NCR_ALIE_Msk 0x00000008UL /*!< Alert Interrupt Enable */ +#define CAN_Node_NCR_CANDIS_Msk 0x00000010UL /*!< CAN Disable */ +#define CAN_Node_NCR_CCE_Msk 0x00000040UL /*!< Configuration Change Enable */ +#define CAN_Node_NCR_CALM_Msk 0x00000080UL /*!< CAN Analyzer Mode */ +#define CAN_Node_NCR_SUSEN_Msk 0x00000100UL /*!< Suspend Enable */ + +/*-- Node: NSR: Node Status Register0 -------------------------------------------------------------------------*/ +typedef struct { + uint32_t LEC :3; /*!< Last Error Code */ + uint32_t TXOK :1; /*!< Message Transmitted Successfully */ + uint32_t RXOK :1; /*!< Message Received Successfully */ + uint32_t ALERT :1; /*!< Alert Warning */ + uint32_t EWRN :1; /*!< Error Warning Status */ + uint32_t BOFF :1; /*!< Bus-Off Status */ + uint32_t LLE :1; /*!< List Length Error */ + uint32_t LOE :1; /*!< List Object Error */ + uint32_t SUSACK :1; /*!< Suspend Acknowledge */ +} _CAN_Node_NSR_bits; + +/* Bit field positions: */ +#define CAN_Node_NSR_LEC_Pos 0 /*!< Last Error Code */ +#define CAN_Node_NSR_TXOK_Pos 3 /*!< Message Transmitted Successfully */ +#define CAN_Node_NSR_RXOK_Pos 4 /*!< Message Received Successfully */ +#define CAN_Node_NSR_ALERT_Pos 5 /*!< Alert Warning */ +#define CAN_Node_NSR_EWRN_Pos 6 /*!< Error Warning Status */ +#define CAN_Node_NSR_BOFF_Pos 7 /*!< Bus-Off Status */ +#define CAN_Node_NSR_LLE_Pos 8 /*!< List Length Error */ +#define CAN_Node_NSR_LOE_Pos 9 /*!< List Object Error */ +#define CAN_Node_NSR_SUSACK_Pos 10 /*!< Suspend Acknowledge */ + +/* Bit field masks: */ +#define CAN_Node_NSR_LEC_Msk 0x00000007UL /*!< Last Error Code */ +#define CAN_Node_NSR_TXOK_Msk 0x00000008UL /*!< Message Transmitted Successfully */ +#define CAN_Node_NSR_RXOK_Msk 0x00000010UL /*!< Message Received Successfully */ +#define CAN_Node_NSR_ALERT_Msk 0x00000020UL /*!< Alert Warning */ +#define CAN_Node_NSR_EWRN_Msk 0x00000040UL /*!< Error Warning Status */ +#define CAN_Node_NSR_BOFF_Msk 0x00000080UL /*!< Bus-Off Status */ +#define CAN_Node_NSR_LLE_Msk 0x00000100UL /*!< List Length Error */ +#define CAN_Node_NSR_LOE_Msk 0x00000200UL /*!< List Object Error */ +#define CAN_Node_NSR_SUSACK_Msk 0x00000400UL /*!< Suspend Acknowledge */ + +/* Bit field enums: */ +typedef enum { + CAN_Node_NSR_LEC_NoErr = 0x0UL, /*!< no error */ + CAN_Node_NSR_LEC_StuffErr = 0x1UL, /*!< stuff error */ + CAN_Node_NSR_LEC_FormErr = 0x2UL, /*!< form error */ + CAN_Node_NSR_LEC_AckErr = 0x3UL, /*!< acknowlegment error */ + CAN_Node_NSR_LEC_Bit1Err = 0x4UL, /*!< bit 1 error */ + CAN_Node_NSR_LEC_Bit0Err = 0x5UL, /*!< bit 0 error */ + CAN_Node_NSR_LEC_CRCErr = 0x6UL, /*!< CRC error */ + CAN_Node_NSR_LEC_WriteEn = 0x7UL, /*!< enable hardware write */ +} CAN_Node_NSR_LEC_Enum; + +/*-- Node: NIPR: Node Interrupt Pointer Register0 -------------------------------------------------------------*/ +typedef struct { + uint32_t ALINP :4; /*!< Alert Interrupt Node Pointer */ + uint32_t LECINP :4; /*!< Last Error Code Interrupt Node Pointer */ + uint32_t TRINP :4; /*!< Transfer OK Interrupt Node Pointer */ + uint32_t CFCINP :4; /*!< Frame Counter Interrupt Node Pointer */ +} _CAN_Node_NIPR_bits; + +/* Bit field positions: */ +#define CAN_Node_NIPR_ALINP_Pos 0 /*!< Alert Interrupt Node Pointer */ +#define CAN_Node_NIPR_LECINP_Pos 4 /*!< Last Error Code Interrupt Node Pointer */ +#define CAN_Node_NIPR_TRINP_Pos 8 /*!< Transfer OK Interrupt Node Pointer */ +#define CAN_Node_NIPR_CFCINP_Pos 12 /*!< Frame Counter Interrupt Node Pointer */ + +/* Bit field masks: */ +#define CAN_Node_NIPR_ALINP_Msk 0x0000000FUL /*!< Alert Interrupt Node Pointer */ +#define CAN_Node_NIPR_LECINP_Msk 0x000000F0UL /*!< Last Error Code Interrupt Node Pointer */ +#define CAN_Node_NIPR_TRINP_Msk 0x00000F00UL /*!< Transfer OK Interrupt Node Pointer */ +#define CAN_Node_NIPR_CFCINP_Msk 0x0000F000UL /*!< Frame Counter Interrupt Node Pointer */ + +/*-- Node: NPCR: Node Port Control Register0 ------------------------------------------------------------------*/ +typedef struct { + uint32_t RXSEL :3; /*!< Receive Select */ + uint32_t :5; /*!< RESERVED */ + uint32_t LBM :1; /*!< Loop-Back Mode */ +} _CAN_Node_NPCR_bits; + +/* Bit field positions: */ +#define CAN_Node_NPCR_RXSEL_Pos 0 /*!< Receive Select */ +#define CAN_Node_NPCR_LBM_Pos 8 /*!< Loop-Back Mode */ + +/* Bit field masks: */ +#define CAN_Node_NPCR_RXSEL_Msk 0x00000007UL /*!< Receive Select */ +#define CAN_Node_NPCR_LBM_Msk 0x00000100UL /*!< Loop-Back Mode */ + +/*-- Node: NBTR: Node Bit Timing Register0 --------------------------------------------------------------------*/ +typedef struct { + uint32_t BRP :6; /*!< Baud Rate Prescaler */ + uint32_t SJW :2; /*!< Synchronization Jump Width */ + uint32_t TSEG1 :4; /*!< Time Segment Before Sample Point */ + uint32_t TSEG2 :3; /*!< Time Segment After Sample Point */ + uint32_t DIV8 :1; /*!< Divide Prescaler Clock by 8 */ +} _CAN_Node_NBTR_bits; + +/* Bit field positions: */ +#define CAN_Node_NBTR_BRP_Pos 0 /*!< Baud Rate Prescaler */ +#define CAN_Node_NBTR_SJW_Pos 6 /*!< Synchronization Jump Width */ +#define CAN_Node_NBTR_TSEG1_Pos 8 /*!< Time Segment Before Sample Point */ +#define CAN_Node_NBTR_TSEG2_Pos 12 /*!< Time Segment After Sample Point */ +#define CAN_Node_NBTR_DIV8_Pos 15 /*!< Divide Prescaler Clock by 8 */ + +/* Bit field masks: */ +#define CAN_Node_NBTR_BRP_Msk 0x0000003FUL /*!< Baud Rate Prescaler */ +#define CAN_Node_NBTR_SJW_Msk 0x000000C0UL /*!< Synchronization Jump Width */ +#define CAN_Node_NBTR_TSEG1_Msk 0x00000F00UL /*!< Time Segment Before Sample Point */ +#define CAN_Node_NBTR_TSEG2_Msk 0x00007000UL /*!< Time Segment After Sample Point */ +#define CAN_Node_NBTR_DIV8_Msk 0x00008000UL /*!< Divide Prescaler Clock by 8 */ + +/*-- Node: NECNT: Node Error Counter Register0 ----------------------------------------------------------------*/ +typedef struct { + uint32_t REC :8; /*!< Receive Error Counter */ + uint32_t TEC :8; /*!< Transmit Error Counter */ + uint32_t EWRNLVL :8; /*!< Error Warning Level */ + uint32_t LETD :1; /*!< Last Error Transfer Direction */ + uint32_t LEINC :1; /*!< Last Error Increment */ +} _CAN_Node_NECNT_bits; + +/* Bit field positions: */ +#define CAN_Node_NECNT_REC_Pos 0 /*!< Receive Error Counter */ +#define CAN_Node_NECNT_TEC_Pos 8 /*!< Transmit Error Counter */ +#define CAN_Node_NECNT_EWRNLVL_Pos 16 /*!< Error Warning Level */ +#define CAN_Node_NECNT_LETD_Pos 24 /*!< Last Error Transfer Direction */ +#define CAN_Node_NECNT_LEINC_Pos 25 /*!< Last Error Increment */ + +/* Bit field masks: */ +#define CAN_Node_NECNT_REC_Msk 0x000000FFUL /*!< Receive Error Counter */ +#define CAN_Node_NECNT_TEC_Msk 0x0000FF00UL /*!< Transmit Error Counter */ +#define CAN_Node_NECNT_EWRNLVL_Msk 0x00FF0000UL /*!< Error Warning Level */ +#define CAN_Node_NECNT_LETD_Msk 0x01000000UL /*!< Last Error Transfer Direction */ +#define CAN_Node_NECNT_LEINC_Msk 0x02000000UL /*!< Last Error Increment */ + +/*-- Node: NFCR: Node Frame Counter Register0 -----------------------------------------------------------------*/ +typedef struct { + uint32_t CFC :16; /*!< CAN Frame Counter */ + uint32_t CFSEL :3; /*!< CAN Frame Count Selection */ + uint32_t CFMOD :2; /*!< CAN Frame Counter Mode */ + uint32_t :1; /*!< RESERVED */ + uint32_t CFCIE :1; /*!< CAN Frame Counter Interrupt Enable */ + uint32_t CFCOV :1; /*!< CAN Frame Counter Overflow Flag */ +} _CAN_Node_NFCR_bits; + +/* Bit field positions: */ +#define CAN_Node_NFCR_CFC_Pos 0 /*!< CAN Frame Counter */ +#define CAN_Node_NFCR_CFSEL_Pos 16 /*!< CAN Frame Count Selection */ +#define CAN_Node_NFCR_CFMOD_Pos 19 /*!< CAN Frame Counter Mode */ +#define CAN_Node_NFCR_CFCIE_Pos 22 /*!< CAN Frame Counter Interrupt Enable */ +#define CAN_Node_NFCR_CFCOV_Pos 23 /*!< CAN Frame Counter Overflow Flag */ + +/* Bit field masks: */ +#define CAN_Node_NFCR_CFC_Msk 0x0000FFFFUL /*!< CAN Frame Counter */ +#define CAN_Node_NFCR_CFSEL_Msk 0x00070000UL /*!< CAN Frame Count Selection */ +#define CAN_Node_NFCR_CFMOD_Msk 0x00180000UL /*!< CAN Frame Counter Mode */ +#define CAN_Node_NFCR_CFCIE_Msk 0x00400000UL /*!< CAN Frame Counter Interrupt Enable */ +#define CAN_Node_NFCR_CFCOV_Msk 0x00800000UL /*!< CAN Frame Counter Overflow Flag */ + +//Cluster LIST: +typedef struct { + union { + /*!< List Register0 */ + __I uint32_t LIST; /*!< LIST : type used for word access */ + __I _CAN_LIST_LIST_bits LIST_bit; /*!< LIST_bit: structure used for bit access */ + }; +} _CAN_LIST_TypeDef; +//Cluster MSPND: +typedef struct { + union { + /*!< Message Pending Register0 */ + __IO uint32_t MSPND; /*!< MSPND : type used for word access */ + __IO _CAN_MSPND_MSPND_bits MSPND_bit; /*!< MSPND_bit: structure used for bit access */ + }; +} _CAN_MSPND_TypeDef; +//Cluster MSID: +typedef struct { + union { + /*!< Message Index Register0 */ + __I uint32_t MSID; /*!< MSID : type used for word access */ + __I _CAN_MSID_MSID_bits MSID_bit; /*!< MSID_bit: structure used for bit access */ + }; +} _CAN_MSID_TypeDef; +//Cluster Node: +typedef struct { + union { + /*!< Node control register0 */ + __IO uint32_t NCR; /*!< NCR : type used for word access */ + __IO _CAN_Node_NCR_bits NCR_bit; /*!< NCR_bit: structure used for bit access */ + }; + union { + /*!< Node Status Register0 */ + __IO uint32_t NSR; /*!< NSR : type used for word access */ + __IO _CAN_Node_NSR_bits NSR_bit; /*!< NSR_bit: structure used for bit access */ + }; + union { + /*!< Node Interrupt Pointer Register0 */ + __IO uint32_t NIPR; /*!< NIPR : type used for word access */ + __IO _CAN_Node_NIPR_bits NIPR_bit; /*!< NIPR_bit: structure used for bit access */ + }; + union { + /*!< Node Port Control Register0 */ + __IO uint32_t NPCR; /*!< NPCR : type used for word access */ + __IO _CAN_Node_NPCR_bits NPCR_bit; /*!< NPCR_bit: structure used for bit access */ + }; + union { + /*!< Node Bit Timing Register0 */ + __IO uint32_t NBTR; /*!< NBTR : type used for word access */ + __IO _CAN_Node_NBTR_bits NBTR_bit; /*!< NBTR_bit: structure used for bit access */ + }; + union { + /*!< Node Error Counter Register0 */ + __IO uint32_t NECNT; /*!< NECNT : type used for word access */ + __IO _CAN_Node_NECNT_bits NECNT_bit; /*!< NECNT_bit: structure used for bit access */ + }; + union { + /*!< Node Frame Counter Register0 */ + __IO uint32_t NFCR; /*!< NFCR : type used for word access */ + __IO _CAN_Node_NFCR_bits NFCR_bit; /*!< NFCR_bit: structure used for bit access */ + }; + __IO uint32_t Reserved0[57]; +} _CAN_Node_TypeDef; +typedef struct { + union { /*!< CAN Clock Control Register */ + __IO uint32_t CLC; /*!< CLC : type used for word access */ + __IO _CAN_CLC_bits CLC_bit; /*!< CLC_bit: structure used for bit access */ + }; + __IO uint32_t Reserved0; + union { /*!< Module Identification Register */ + __IO uint32_t ID; /*!< ID : type used for word access */ + __IO _CAN_ID_bits ID_bit; /*!< ID_bit: structure used for bit access */ + }; + union { /*!< Fractional Divider Register */ + __IO uint32_t FDR; /*!< FDR : type used for word access */ + __IO _CAN_FDR_bits FDR_bit; /*!< FDR_bit: structure used for bit access */ + }; + __IO uint32_t Reserved1[60]; + _CAN_LIST_TypeDef LIST[8]; + __IO uint32_t Reserved2[8]; + _CAN_MSPND_TypeDef MSPND[4]; + __IO uint32_t Reserved3[12]; + _CAN_MSID_TypeDef MSID[4]; + __IO uint32_t Reserved4[12]; + union { /*!< Message Index Mask Register */ + __IO uint32_t MSIMASK; /*!< MSIMASK : type used for word access */ + __IO _CAN_MSIMASK_bits MSIMASK_bit; /*!< MSIMASK_bit: structure used for bit access */ + }; + union { /*!< Panel Control Register */ + __IO uint32_t PANCTR; /*!< PANCTR : type used for word access */ + __IO _CAN_PANCTR_bits PANCTR_bit; /*!< PANCTR_bit: structure used for bit access */ + }; + union { /*!< */ + __IO uint32_t MCR; /*!< MCR : type used for word access */ + __IO _CAN_MCR_bits MCR_bit; /*!< MCR_bit: structure used for bit access */ + }; + union { /*!< Module Interrupt Trigger Register */ + __O uint32_t MITR; /*!< MITR : type used for word access */ + __O _CAN_MITR_bits MITR_bit; /*!< MITR_bit: structure used for bit access */ + }; + __IO uint32_t Reserved5[12]; + _CAN_Node_TypeDef Node[2]; +} CAN_TypeDef; + + +/******************************************************************************/ +/* CANMSG registers */ +/******************************************************************************/ + +/*-- Msg: MOFCR: Message Object Function Control Register0 ----------------------------------------------------*/ +typedef struct { + uint32_t MMC :4; /*!< Message Mode Control */ + uint32_t :4; /*!< RESERVED */ + uint32_t GDFS :1; /*!< Gateway Data Frame Selected */ + uint32_t IDC :1; /*!< Identifier Copy */ + uint32_t DLCC :1; /*!< Data Lengh Code Copy */ + uint32_t DATC :1; /*!< Data Copy */ + uint32_t :4; /*!< RESERVED */ + uint32_t RXIE :1; /*!< Receive Interrupt Enable */ + uint32_t TXIE :1; /*!< Transmit Interrupt Enable */ + uint32_t OVIE :1; /*!< Overflow Interrupt Enable */ + uint32_t :1; /*!< RESERVED */ + uint32_t FRREN :1; /*!< Foreign Remote Request Enable */ + uint32_t RMM :1; /*!< Transmit Object Remote Monitoring */ + uint32_t SDT :1; /*!< Single Data Transfer */ + uint32_t STT :1; /*!< Single Transmit Trial */ + uint32_t DLC :4; /*!< Data Length Code */ +} _CANMSG_Msg_MOFCR_bits; + +/* Bit field positions: */ +#define CANMSG_Msg_MOFCR_MMC_Pos 0 /*!< Message Mode Control */ +#define CANMSG_Msg_MOFCR_GDFS_Pos 8 /*!< Gateway Data Frame Selected */ +#define CANMSG_Msg_MOFCR_IDC_Pos 9 /*!< Identifier Copy */ +#define CANMSG_Msg_MOFCR_DLCC_Pos 10 /*!< Data Lengh Code Copy */ +#define CANMSG_Msg_MOFCR_DATC_Pos 11 /*!< Data Copy */ +#define CANMSG_Msg_MOFCR_RXIE_Pos 16 /*!< Receive Interrupt Enable */ +#define CANMSG_Msg_MOFCR_TXIE_Pos 17 /*!< Transmit Interrupt Enable */ +#define CANMSG_Msg_MOFCR_OVIE_Pos 18 /*!< Overflow Interrupt Enable */ +#define CANMSG_Msg_MOFCR_FRREN_Pos 20 /*!< Foreign Remote Request Enable */ +#define CANMSG_Msg_MOFCR_RMM_Pos 21 /*!< Transmit Object Remote Monitoring */ +#define CANMSG_Msg_MOFCR_SDT_Pos 22 /*!< Single Data Transfer */ +#define CANMSG_Msg_MOFCR_STT_Pos 23 /*!< Single Transmit Trial */ +#define CANMSG_Msg_MOFCR_DLC_Pos 24 /*!< Data Length Code */ + +/* Bit field masks: */ +#define CANMSG_Msg_MOFCR_MMC_Msk 0x0000000FUL /*!< Message Mode Control */ +#define CANMSG_Msg_MOFCR_GDFS_Msk 0x00000100UL /*!< Gateway Data Frame Selected */ +#define CANMSG_Msg_MOFCR_IDC_Msk 0x00000200UL /*!< Identifier Copy */ +#define CANMSG_Msg_MOFCR_DLCC_Msk 0x00000400UL /*!< Data Lengh Code Copy */ +#define CANMSG_Msg_MOFCR_DATC_Msk 0x00000800UL /*!< Data Copy */ +#define CANMSG_Msg_MOFCR_RXIE_Msk 0x00010000UL /*!< Receive Interrupt Enable */ +#define CANMSG_Msg_MOFCR_TXIE_Msk 0x00020000UL /*!< Transmit Interrupt Enable */ +#define CANMSG_Msg_MOFCR_OVIE_Msk 0x00040000UL /*!< Overflow Interrupt Enable */ +#define CANMSG_Msg_MOFCR_FRREN_Msk 0x00100000UL /*!< Foreign Remote Request Enable */ +#define CANMSG_Msg_MOFCR_RMM_Msk 0x00200000UL /*!< Transmit Object Remote Monitoring */ +#define CANMSG_Msg_MOFCR_SDT_Msk 0x00400000UL /*!< Single Data Transfer */ +#define CANMSG_Msg_MOFCR_STT_Msk 0x00800000UL /*!< Single Transmit Trial */ +#define CANMSG_Msg_MOFCR_DLC_Msk 0x0F000000UL /*!< Data Length Code */ + +/* Bit field enums: */ +typedef enum { + CANMSG_Msg_MOFCR_MMC_MsgObj = 0x0UL, /*!< message object */ + CANMSG_Msg_MOFCR_MMC_RXObj = 0x1UL, /*!< receiver FIFO structure object */ + CANMSG_Msg_MOFCR_MMC_TXObj = 0x2UL, /*!< transmitter FIFO structure object */ + CANMSG_Msg_MOFCR_MMC_SlaveTXObj = 0x3UL, /*!< transmitter FIFO structure slave object */ + CANMSG_Msg_MOFCR_MMC_SrcObj = 0x4UL, /*!< gateway source object */ +} CANMSG_Msg_MOFCR_MMC_Enum; + +/*-- Msg: MOFGPR: Message Object FIFO/Gateway Pointer Register0 -----------------------------------------------*/ +typedef struct { + uint32_t BOT :8; /*!< Botom Pointer */ + uint32_t TOP :8; /*!< Top Pointer */ + uint32_t CUR :8; /*!< Current Object Pointer */ + uint32_t SEL :8; /*!< Object Select Pointer */ +} _CANMSG_Msg_MOFGPR_bits; + +/* Bit field positions: */ +#define CANMSG_Msg_MOFGPR_BOT_Pos 0 /*!< Botom Pointer */ +#define CANMSG_Msg_MOFGPR_TOP_Pos 8 /*!< Top Pointer */ +#define CANMSG_Msg_MOFGPR_CUR_Pos 16 /*!< Current Object Pointer */ +#define CANMSG_Msg_MOFGPR_SEL_Pos 24 /*!< Object Select Pointer */ + +/* Bit field masks: */ +#define CANMSG_Msg_MOFGPR_BOT_Msk 0x000000FFUL /*!< Botom Pointer */ +#define CANMSG_Msg_MOFGPR_TOP_Msk 0x0000FF00UL /*!< Top Pointer */ +#define CANMSG_Msg_MOFGPR_CUR_Msk 0x00FF0000UL /*!< Current Object Pointer */ +#define CANMSG_Msg_MOFGPR_SEL_Msk 0xFF000000UL /*!< Object Select Pointer */ + +/*-- Msg: MOIPR: Message Object Interrupt Pointer Register0 ---------------------------------------------------*/ +typedef struct { + uint32_t RXINP :4; /*!< Receive Interrupt Node Pointer */ + uint32_t TXINP :4; /*!< Transmit Interrupt Node Pointer */ + uint32_t MPN :8; /*!< Message Pending Number */ + uint32_t CFCVAL :16; /*!< CAN Frame Counter Value */ +} _CANMSG_Msg_MOIPR_bits; + +/* Bit field positions: */ +#define CANMSG_Msg_MOIPR_RXINP_Pos 0 /*!< Receive Interrupt Node Pointer */ +#define CANMSG_Msg_MOIPR_TXINP_Pos 4 /*!< Transmit Interrupt Node Pointer */ +#define CANMSG_Msg_MOIPR_MPN_Pos 8 /*!< Message Pending Number */ +#define CANMSG_Msg_MOIPR_CFCVAL_Pos 16 /*!< CAN Frame Counter Value */ + +/* Bit field masks: */ +#define CANMSG_Msg_MOIPR_RXINP_Msk 0x0000000FUL /*!< Receive Interrupt Node Pointer */ +#define CANMSG_Msg_MOIPR_TXINP_Msk 0x000000F0UL /*!< Transmit Interrupt Node Pointer */ +#define CANMSG_Msg_MOIPR_MPN_Msk 0x0000FF00UL /*!< Message Pending Number */ +#define CANMSG_Msg_MOIPR_CFCVAL_Msk 0xFFFF0000UL /*!< CAN Frame Counter Value */ + +/*-- Msg: MOAMR: Message Object Acceptance Mask Register0 -----------------------------------------------------*/ +typedef struct { + uint32_t AM :29; /*!< Acceptance Mask for Message Identifier */ + uint32_t MIDE :1; /*!< Acceptance Mask Bit for Message IDE Bit */ +} _CANMSG_Msg_MOAMR_bits; + +/* Bit field positions: */ +#define CANMSG_Msg_MOAMR_AM_Pos 0 /*!< Acceptance Mask for Message Identifier */ +#define CANMSG_Msg_MOAMR_MIDE_Pos 29 /*!< Acceptance Mask Bit for Message IDE Bit */ + +/* Bit field masks: */ +#define CANMSG_Msg_MOAMR_AM_Msk 0x1FFFFFFFUL /*!< Acceptance Mask for Message Identifier */ +#define CANMSG_Msg_MOAMR_MIDE_Msk 0x20000000UL /*!< Acceptance Mask Bit for Message IDE Bit */ + +/*-- Msg: MODATAL: Message Object Data Register Low0 ----------------------------------------------------------*/ +typedef struct { + uint32_t DB0 :8; /*!< Data byte 0 of message object */ + uint32_t DB1 :8; /*!< Data byte 1 of message object */ + uint32_t DB2 :8; /*!< Data byte 2 of message object */ + uint32_t DB3 :8; /*!< Data byte 3 of message object */ +} _CANMSG_Msg_MODATAL_bits; + +/* Bit field positions: */ +#define CANMSG_Msg_MODATAL_DB0_Pos 0 /*!< Data byte 0 of message object */ +#define CANMSG_Msg_MODATAL_DB1_Pos 8 /*!< Data byte 1 of message object */ +#define CANMSG_Msg_MODATAL_DB2_Pos 16 /*!< Data byte 2 of message object */ +#define CANMSG_Msg_MODATAL_DB3_Pos 24 /*!< Data byte 3 of message object */ + +/* Bit field masks: */ +#define CANMSG_Msg_MODATAL_DB0_Msk 0x000000FFUL /*!< Data byte 0 of message object */ +#define CANMSG_Msg_MODATAL_DB1_Msk 0x0000FF00UL /*!< Data byte 1 of message object */ +#define CANMSG_Msg_MODATAL_DB2_Msk 0x00FF0000UL /*!< Data byte 2 of message object */ +#define CANMSG_Msg_MODATAL_DB3_Msk 0xFF000000UL /*!< Data byte 3 of message object */ + +/*-- Msg: MODATAH: Message Object Data Register High0 ---------------------------------------------------------*/ +typedef struct { + uint32_t DB4 :8; /*!< Data byte 4 of message object */ + uint32_t DB5 :8; /*!< Data byte 5 of message object */ + uint32_t DB6 :8; /*!< Data byte 6 of message object */ + uint32_t DB7 :8; /*!< Data byte 7 of message object */ +} _CANMSG_Msg_MODATAH_bits; + +/* Bit field positions: */ +#define CANMSG_Msg_MODATAH_DB4_Pos 0 /*!< Data byte 4 of message object */ +#define CANMSG_Msg_MODATAH_DB5_Pos 8 /*!< Data byte 5 of message object */ +#define CANMSG_Msg_MODATAH_DB6_Pos 16 /*!< Data byte 6 of message object */ +#define CANMSG_Msg_MODATAH_DB7_Pos 24 /*!< Data byte 7 of message object */ + +/* Bit field masks: */ +#define CANMSG_Msg_MODATAH_DB4_Msk 0x000000FFUL /*!< Data byte 4 of message object */ +#define CANMSG_Msg_MODATAH_DB5_Msk 0x0000FF00UL /*!< Data byte 5 of message object */ +#define CANMSG_Msg_MODATAH_DB6_Msk 0x00FF0000UL /*!< Data byte 6 of message object */ +#define CANMSG_Msg_MODATAH_DB7_Msk 0xFF000000UL /*!< Data byte 7 of message object */ + +/*-- Msg: MOAR: Message Object Arbitration Register0 ----------------------------------------------------------*/ +typedef struct { + uint32_t ID :29; /*!< CAN identifier of Message Object */ + uint32_t IDE :1; /*!< Identifier Extension Bit of Messgae Object */ + uint32_t PRI :2; /*!< Priority Class */ +} _CANMSG_Msg_MOAR_bits; + +/* Bit field positions: */ +#define CANMSG_Msg_MOAR_ID_Pos 0 /*!< CAN identifier of Message Object */ +#define CANMSG_Msg_MOAR_IDE_Pos 29 /*!< Identifier Extension Bit of Messgae Object */ +#define CANMSG_Msg_MOAR_PRI_Pos 30 /*!< Priority Class */ + +/* Bit field masks: */ +#define CANMSG_Msg_MOAR_ID_Msk 0x1FFFFFFFUL /*!< CAN identifier of Message Object */ +#define CANMSG_Msg_MOAR_IDE_Msk 0x20000000UL /*!< Identifier Extension Bit of Messgae Object */ +#define CANMSG_Msg_MOAR_PRI_Msk 0xC0000000UL /*!< Priority Class */ + +/*-- Msg: MOCTR: Message Object Control Register0 -------------------------------------------------------------*/ +typedef struct { + uint32_t RESRXPND :1; /*!< Reset Receive Pending */ + uint32_t RESTXPND :1; /*!< Reset Transmit Pending */ + uint32_t RESRXUPD :1; /*!< Reset Receive Updating */ + uint32_t RESNEWDAT :1; /*!< Reset New Data */ + uint32_t RESMSGLST :1; /*!< Reset Message Lost */ + uint32_t RESMSGVAL :1; /*!< Reset Message Valid */ + uint32_t RESRTSEL :1; /*!< Reset Receive/Transmit Selected */ + uint32_t RESRXEN :1; /*!< Reset Receive Enable */ + uint32_t RESTXRQ :1; /*!< Reset Transmit Request */ + uint32_t RESTXEN0 :1; /*!< Reset Transmit Enable 0 */ + uint32_t RESTXEN1 :1; /*!< Reset Transmit Enable 1 */ + uint32_t RESDIR :1; /*!< Reset Message Direction */ + uint32_t :4; /*!< RESERVED */ + uint32_t SETRXPND :1; /*!< Set Receive Pending */ + uint32_t SETTXPND :1; /*!< Set Transmit Pending */ + uint32_t SETRXUPD :1; /*!< Set Receive Updating */ + uint32_t SETNEWDAT :1; /*!< Set New Data */ + uint32_t SETMSGLST :1; /*!< Set Message Lost */ + uint32_t SETMSGVAL :1; /*!< Set Message Valid */ + uint32_t SETRTSEL :1; /*!< Set Receive/Transmit Selected */ + uint32_t SETRXEN :1; /*!< Set Receive Enable */ + uint32_t SETTXRQ :1; /*!< Set Transmit Request */ + uint32_t SETTXEN0 :1; /*!< Set Transmit Enable 0 */ + uint32_t SETTXEN1 :1; /*!< Set Transmit Enable 1 */ + uint32_t SETDIR :1; /*!< Set Message Direction */ +} _CANMSG_Msg_MOCTR_bits; + +/* Bit field positions: */ +#define CANMSG_Msg_MOCTR_RESRXPND_Pos 0 /*!< Reset Receive Pending */ +#define CANMSG_Msg_MOCTR_RESTXPND_Pos 1 /*!< Reset Transmit Pending */ +#define CANMSG_Msg_MOCTR_RESRXUPD_Pos 2 /*!< Reset Receive Updating */ +#define CANMSG_Msg_MOCTR_RESNEWDAT_Pos 3 /*!< Reset New Data */ +#define CANMSG_Msg_MOCTR_RESMSGLST_Pos 4 /*!< Reset Message Lost */ +#define CANMSG_Msg_MOCTR_RESMSGVAL_Pos 5 /*!< Reset Message Valid */ +#define CANMSG_Msg_MOCTR_RESRTSEL_Pos 6 /*!< Reset Receive/Transmit Selected */ +#define CANMSG_Msg_MOCTR_RESRXEN_Pos 7 /*!< Reset Receive Enable */ +#define CANMSG_Msg_MOCTR_RESTXRQ_Pos 8 /*!< Reset Transmit Request */ +#define CANMSG_Msg_MOCTR_RESTXEN0_Pos 9 /*!< Reset Transmit Enable 0 */ +#define CANMSG_Msg_MOCTR_RESTXEN1_Pos 10 /*!< Reset Transmit Enable 1 */ +#define CANMSG_Msg_MOCTR_RESDIR_Pos 11 /*!< Reset Message Direction */ +#define CANMSG_Msg_MOCTR_SETRXPND_Pos 16 /*!< Set Receive Pending */ +#define CANMSG_Msg_MOCTR_SETTXPND_Pos 17 /*!< Set Transmit Pending */ +#define CANMSG_Msg_MOCTR_SETRXUPD_Pos 18 /*!< Set Receive Updating */ +#define CANMSG_Msg_MOCTR_SETNEWDAT_Pos 19 /*!< Set New Data */ +#define CANMSG_Msg_MOCTR_SETMSGLST_Pos 20 /*!< Set Message Lost */ +#define CANMSG_Msg_MOCTR_SETMSGVAL_Pos 21 /*!< Set Message Valid */ +#define CANMSG_Msg_MOCTR_SETRTSEL_Pos 22 /*!< Set Receive/Transmit Selected */ +#define CANMSG_Msg_MOCTR_SETRXEN_Pos 23 /*!< Set Receive Enable */ +#define CANMSG_Msg_MOCTR_SETTXRQ_Pos 24 /*!< Set Transmit Request */ +#define CANMSG_Msg_MOCTR_SETTXEN0_Pos 25 /*!< Set Transmit Enable 0 */ +#define CANMSG_Msg_MOCTR_SETTXEN1_Pos 26 /*!< Set Transmit Enable 1 */ +#define CANMSG_Msg_MOCTR_SETDIR_Pos 27 /*!< Set Message Direction */ + +/* Bit field masks: */ +#define CANMSG_Msg_MOCTR_RESRXPND_Msk 0x00000001UL /*!< Reset Receive Pending */ +#define CANMSG_Msg_MOCTR_RESTXPND_Msk 0x00000002UL /*!< Reset Transmit Pending */ +#define CANMSG_Msg_MOCTR_RESRXUPD_Msk 0x00000004UL /*!< Reset Receive Updating */ +#define CANMSG_Msg_MOCTR_RESNEWDAT_Msk 0x00000008UL /*!< Reset New Data */ +#define CANMSG_Msg_MOCTR_RESMSGLST_Msk 0x00000010UL /*!< Reset Message Lost */ +#define CANMSG_Msg_MOCTR_RESMSGVAL_Msk 0x00000020UL /*!< Reset Message Valid */ +#define CANMSG_Msg_MOCTR_RESRTSEL_Msk 0x00000040UL /*!< Reset Receive/Transmit Selected */ +#define CANMSG_Msg_MOCTR_RESRXEN_Msk 0x00000080UL /*!< Reset Receive Enable */ +#define CANMSG_Msg_MOCTR_RESTXRQ_Msk 0x00000100UL /*!< Reset Transmit Request */ +#define CANMSG_Msg_MOCTR_RESTXEN0_Msk 0x00000200UL /*!< Reset Transmit Enable 0 */ +#define CANMSG_Msg_MOCTR_RESTXEN1_Msk 0x00000400UL /*!< Reset Transmit Enable 1 */ +#define CANMSG_Msg_MOCTR_RESDIR_Msk 0x00000800UL /*!< Reset Message Direction */ +#define CANMSG_Msg_MOCTR_SETRXPND_Msk 0x00010000UL /*!< Set Receive Pending */ +#define CANMSG_Msg_MOCTR_SETTXPND_Msk 0x00020000UL /*!< Set Transmit Pending */ +#define CANMSG_Msg_MOCTR_SETRXUPD_Msk 0x00040000UL /*!< Set Receive Updating */ +#define CANMSG_Msg_MOCTR_SETNEWDAT_Msk 0x00080000UL /*!< Set New Data */ +#define CANMSG_Msg_MOCTR_SETMSGLST_Msk 0x00100000UL /*!< Set Message Lost */ +#define CANMSG_Msg_MOCTR_SETMSGVAL_Msk 0x00200000UL /*!< Set Message Valid */ +#define CANMSG_Msg_MOCTR_SETRTSEL_Msk 0x00400000UL /*!< Set Receive/Transmit Selected */ +#define CANMSG_Msg_MOCTR_SETRXEN_Msk 0x00800000UL /*!< Set Receive Enable */ +#define CANMSG_Msg_MOCTR_SETTXRQ_Msk 0x01000000UL /*!< Set Transmit Request */ +#define CANMSG_Msg_MOCTR_SETTXEN0_Msk 0x02000000UL /*!< Set Transmit Enable 0 */ +#define CANMSG_Msg_MOCTR_SETTXEN1_Msk 0x04000000UL /*!< Set Transmit Enable 1 */ +#define CANMSG_Msg_MOCTR_SETDIR_Msk 0x08000000UL /*!< Set Message Direction */ + +/*-- Msg: MOSTAT: Message Object Status Register 0 ------------------------------------------------------------*/ +typedef struct { + uint32_t RXPND :1; /*!< Receive Pending */ + uint32_t TXPND :1; /*!< Transmit Pending */ + uint32_t RXUPD :1; /*!< Receive Updating */ + uint32_t NEWDAT :1; /*!< New Data */ + uint32_t MSGLST :1; /*!< Message Lost */ + uint32_t MSGVAL :1; /*!< Message Valid */ + uint32_t RTSEL :1; /*!< Receive/Transmit Selected */ + uint32_t RXEN :1; /*!< Receive Enable */ + uint32_t TXRQ :1; /*!< Transmit Request */ + uint32_t TXEN0 :1; /*!< Transmit Enable 0 */ + uint32_t TXEN1 :1; /*!< Transmit Enable 1 */ + uint32_t DIR :1; /*!< Message Direction */ + uint32_t LIST :4; /*!< List Allocation */ + uint32_t PPREV :8; /*!< Pointer To Previous Message Object */ + uint32_t PNEXT :8; /*!< Pointer to Next Message Object */ +} _CANMSG_Msg_MOSTAT_bits; + +/* Bit field positions: */ +#define CANMSG_Msg_MOSTAT_RXPND_Pos 0 /*!< Receive Pending */ +#define CANMSG_Msg_MOSTAT_TXPND_Pos 1 /*!< Transmit Pending */ +#define CANMSG_Msg_MOSTAT_RXUPD_Pos 2 /*!< Receive Updating */ +#define CANMSG_Msg_MOSTAT_NEWDAT_Pos 3 /*!< New Data */ +#define CANMSG_Msg_MOSTAT_MSGLST_Pos 4 /*!< Message Lost */ +#define CANMSG_Msg_MOSTAT_MSGVAL_Pos 5 /*!< Message Valid */ +#define CANMSG_Msg_MOSTAT_RTSEL_Pos 6 /*!< Receive/Transmit Selected */ +#define CANMSG_Msg_MOSTAT_RXEN_Pos 7 /*!< Receive Enable */ +#define CANMSG_Msg_MOSTAT_TXRQ_Pos 8 /*!< Transmit Request */ +#define CANMSG_Msg_MOSTAT_TXEN0_Pos 9 /*!< Transmit Enable 0 */ +#define CANMSG_Msg_MOSTAT_TXEN1_Pos 10 /*!< Transmit Enable 1 */ +#define CANMSG_Msg_MOSTAT_DIR_Pos 11 /*!< Message Direction */ +#define CANMSG_Msg_MOSTAT_LIST_Pos 12 /*!< List Allocation */ +#define CANMSG_Msg_MOSTAT_PPREV_Pos 16 /*!< Pointer To Previous Message Object */ +#define CANMSG_Msg_MOSTAT_PNEXT_Pos 24 /*!< Pointer to Next Message Object */ + +/* Bit field masks: */ +#define CANMSG_Msg_MOSTAT_RXPND_Msk 0x00000001UL /*!< Receive Pending */ +#define CANMSG_Msg_MOSTAT_TXPND_Msk 0x00000002UL /*!< Transmit Pending */ +#define CANMSG_Msg_MOSTAT_RXUPD_Msk 0x00000004UL /*!< Receive Updating */ +#define CANMSG_Msg_MOSTAT_NEWDAT_Msk 0x00000008UL /*!< New Data */ +#define CANMSG_Msg_MOSTAT_MSGLST_Msk 0x00000010UL /*!< Message Lost */ +#define CANMSG_Msg_MOSTAT_MSGVAL_Msk 0x00000020UL /*!< Message Valid */ +#define CANMSG_Msg_MOSTAT_RTSEL_Msk 0x00000040UL /*!< Receive/Transmit Selected */ +#define CANMSG_Msg_MOSTAT_RXEN_Msk 0x00000080UL /*!< Receive Enable */ +#define CANMSG_Msg_MOSTAT_TXRQ_Msk 0x00000100UL /*!< Transmit Request */ +#define CANMSG_Msg_MOSTAT_TXEN0_Msk 0x00000200UL /*!< Transmit Enable 0 */ +#define CANMSG_Msg_MOSTAT_TXEN1_Msk 0x00000400UL /*!< Transmit Enable 1 */ +#define CANMSG_Msg_MOSTAT_DIR_Msk 0x00000800UL /*!< Message Direction */ +#define CANMSG_Msg_MOSTAT_LIST_Msk 0x0000F000UL /*!< List Allocation */ +#define CANMSG_Msg_MOSTAT_PPREV_Msk 0x00FF0000UL /*!< Pointer To Previous Message Object */ +#define CANMSG_Msg_MOSTAT_PNEXT_Msk 0xFF000000UL /*!< Pointer to Next Message Object */ + +//Cluster Msg: +typedef struct { + union { + /*!< Message Object Function Control Register0 */ + __IO uint32_t MOFCR; /*!< MOFCR : type used for word access */ + __IO _CANMSG_Msg_MOFCR_bits MOFCR_bit; /*!< MOFCR_bit: structure used for bit access */ + }; + union { + /*!< Message Object FIFO/Gateway Pointer Register0 */ + __IO uint32_t MOFGPR; /*!< MOFGPR : type used for word access */ + __IO _CANMSG_Msg_MOFGPR_bits MOFGPR_bit; /*!< MOFGPR_bit: structure used for bit access */ + }; + union { + /*!< Message Object Interrupt Pointer Register0 */ + __IO uint32_t MOIPR; /*!< MOIPR : type used for word access */ + __IO _CANMSG_Msg_MOIPR_bits MOIPR_bit; /*!< MOIPR_bit: structure used for bit access */ + }; + union { + /*!< Message Object Acceptance Mask Register0 */ + __IO uint32_t MOAMR; /*!< MOAMR : type used for word access */ + __IO _CANMSG_Msg_MOAMR_bits MOAMR_bit; /*!< MOAMR_bit: structure used for bit access */ + }; + union { + /*!< Message Object Data Register Low0 */ + __IO uint32_t MODATAL; /*!< MODATAL : type used for word access */ + __IO _CANMSG_Msg_MODATAL_bits MODATAL_bit; /*!< MODATAL_bit: structure used for bit access */ + }; + union { + /*!< Message Object Data Register High0 */ + __IO uint32_t MODATAH; /*!< MODATAH : type used for word access */ + __IO _CANMSG_Msg_MODATAH_bits MODATAH_bit; /*!< MODATAH_bit: structure used for bit access */ + }; + union { + /*!< Message Object Arbitration Register0 */ + __IO uint32_t MOAR; /*!< MOAR : type used for word access */ + __IO _CANMSG_Msg_MOAR_bits MOAR_bit; /*!< MOAR_bit: structure used for bit access */ + }; + union { + union { + /*!< Message Object Control Register0 */ + __O uint32_t MOCTR; /*!< MOCTR : type used for word access */ + __O _CANMSG_Msg_MOCTR_bits MOCTR_bit; /*!< MOCTR_bit: structure used for bit access */ + }; + union { + /*!< Message Object Status Register 0 */ + __I uint32_t MOSTAT; /*!< MOSTAT : type used for word access */ + __I _CANMSG_Msg_MOSTAT_bits MOSTAT_bit; /*!< MOSTAT_bit: structure used for bit access */ + }; + }; +} _CANMSG_Msg_TypeDef; +typedef struct { + _CANMSG_Msg_TypeDef Msg[64]; +} CANMSG_TypeDef; + + +/* ----------------- End of section using anonymous unions ---------------- */ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning restore +#elif defined (__CMCPPARM__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +#define ADC_BASE 0x40000000UL +#define GPIOA_BASE 0x40010000UL +#define GPIOB_BASE 0x40011000UL +#define CAN_BASE 0x40020000UL +#define CANMSG_BASE 0x40021000UL +#define MFLASH_BASE 0x40030000UL +#define SIU_BASE 0x40040000UL +#define RCU_BASE 0x40041000UL +#define PMU_BASE 0x40042000UL +#define WDT_BASE 0x40043000UL +#define DMA_BASE 0x40044000UL +#define UART0_BASE 0x40045000UL +#define UART1_BASE 0x40046000UL +#define SPI_BASE 0x40047000UL +#define TMR0_BASE 0x40048000UL +#define TMR1_BASE 0x40049000UL +#define TMR2_BASE 0x4004A000UL +#define TMR3_BASE 0x4004B000UL +#define PWM0_BASE 0x4004C000UL +#define PWM1_BASE 0x4004D000UL +#define PWM2_BASE 0x4004E000UL +#define QEP_BASE 0x4004F000UL +#define I2C_BASE 0x40050000UL +#define ECAP0_BASE 0x40051000UL +#define ECAP1_BASE 0x40052000UL +#define ECAP2_BASE 0x40053000UL + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +#define ADC ((ADC_TypeDef *) ADC_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define CAN ((CAN_TypeDef *) CAN_BASE) +#define CANMSG ((CANMSG_TypeDef *) CANMSG_BASE) +#define MFLASH ((MFLASH_TypeDef *) MFLASH_BASE) +#define SIU ((SIU_TypeDef *) SIU_BASE) +#define RCU ((RCU_TypeDef *) RCU_BASE) +#define PMU ((PMU_TypeDef *) PMU_BASE) +#define WDT ((WDT_TypeDef *) WDT_BASE) +#define DMA ((DMA_TypeDef *) DMA_BASE) +#define UART0 ((UART_TypeDef *) UART0_BASE) +#define UART1 ((UART_TypeDef *) UART1_BASE) +#define SPI ((SPI_TypeDef *) SPI_BASE) +#define TMR0 ((TMR_TypeDef *) TMR0_BASE) +#define TMR1 ((TMR_TypeDef *) TMR1_BASE) +#define TMR2 ((TMR_TypeDef *) TMR2_BASE) +#define TMR3 ((TMR_TypeDef *) TMR3_BASE) +#define PWM0 ((PWM_TypeDef *) PWM0_BASE) +#define PWM1 ((PWM_TypeDef *) PWM1_BASE) +#define PWM2 ((PWM_TypeDef *) PWM2_BASE) +#define QEP ((QEP_TypeDef *) QEP_BASE) +#define I2C ((I2C_TypeDef *) I2C_BASE) +#define ECAP0 ((ECAP_TypeDef *) ECAP0_BASE) +#define ECAP1 ((ECAP_TypeDef *) ECAP1_BASE) +#define ECAP2 ((ECAP_TypeDef *) ECAP2_BASE) + +/******************************************************************************/ +/* Peripheral capabilities */ +/******************************************************************************/ +#define ADC_PRESENT +#define ADC_TOTAL 1 +typedef enum { + ADC_Num +} ADC_Num_TypeDef; + +#define GPIO_PRESENT +#define GPIO_TOTAL 2 +typedef enum { + GPIOA_Num, + GPIOB_Num +} GPIO_Num_TypeDef; + +#define CAN_PRESENT +#define CAN_TOTAL 1 +typedef enum { + CAN_Num +} CAN_Num_TypeDef; + +#define CANMSG_PRESENT +#define CANMSG_TOTAL 1 +typedef enum { + CANMSG_Num +} CANMSG_Num_TypeDef; + +#define MFLASH_PRESENT +#define MFLASH_TOTAL 1 +typedef enum { + MFLASH_Num +} MFLASH_Num_TypeDef; + +#define SIU_PRESENT +#define SIU_TOTAL 1 +typedef enum { + SIU_Num +} SIU_Num_TypeDef; + +#define RCU_PRESENT +#define RCU_TOTAL 1 +typedef enum { + RCU_Num +} RCU_Num_TypeDef; + +#define PMU_PRESENT +#define PMU_TOTAL 1 +typedef enum { + PMU_Num +} PMU_Num_TypeDef; + +#define WDT_PRESENT +#define WDT_TOTAL 1 +typedef enum { + WDT_Num +} WDT_Num_TypeDef; + +#define DMA_PRESENT +#define DMA_TOTAL 1 +typedef enum { + DMA_Num +} DMA_Num_TypeDef; + +#define UART_PRESENT +#define UART_TOTAL 2 +typedef enum { + UART0_Num, + UART1_Num +} UART_Num_TypeDef; + +#define SPI_PRESENT +#define SPI_TOTAL 1 +typedef enum { + SPI_Num +} SPI_Num_TypeDef; + +#define TMR_PRESENT +#define TMR_TOTAL 4 +typedef enum { + TMR0_Num, + TMR1_Num, + TMR2_Num, + TMR3_Num +} TMR_Num_TypeDef; + +#define PWM_PRESENT +#define PWM_TOTAL 3 +typedef enum { + PWM0_Num, + PWM1_Num, + PWM2_Num +} PWM_Num_TypeDef; + +#define QEP_PRESENT +#define QEP_TOTAL 1 +typedef enum { + QEP_Num +} QEP_Num_TypeDef; + +#define I2C_PRESENT +#define I2C_TOTAL 1 +typedef enum { + I2C_Num +} I2C_Num_TypeDef; + +#define ECAP_PRESENT +#define ECAP_TOTAL 3 +typedef enum { + ECAP0_Num, + ECAP1_Num, + ECAP2_Num +} ECAP_Num_TypeDef; + +/******************************************************************************/ +/* Peripheral assertions */ +/******************************************************************************/ +#define IS_ADC_PERIPH(PERIPH) (((PERIPH) == ADC)) +#define IS_GPIO_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ + ((PERIPH) == GPIOB)) +#define IS_CAN_PERIPH(PERIPH) (((PERIPH) == CAN)) +#define IS_CANMSG_PERIPH(PERIPH) (((PERIPH) == CANMSG)) +#define IS_MFLASH_PERIPH(PERIPH) (((PERIPH) == MFLASH)) +#define IS_SIU_PERIPH(PERIPH) (((PERIPH) == SIU)) +#define IS_RCU_PERIPH(PERIPH) (((PERIPH) == RCU)) +#define IS_PMU_PERIPH(PERIPH) (((PERIPH) == PMU)) +#define IS_WDT_PERIPH(PERIPH) (((PERIPH) == WDT)) +#define IS_DMA_PERIPH(PERIPH) (((PERIPH) == DMA)) +#define IS_UART_PERIPH(PERIPH) (((PERIPH) == UART0) || \ + ((PERIPH) == UART1)) +#define IS_SPI_PERIPH(PERIPH) (((PERIPH) == SPI)) +#define IS_TMR_PERIPH(PERIPH) (((PERIPH) == TMR0) || \ + ((PERIPH) == TMR1) || \ + ((PERIPH) == TMR2) || \ + ((PERIPH) == TMR3)) +#define IS_PWM_PERIPH(PERIPH) (((PERIPH) == PWM0) || \ + ((PERIPH) == PWM1) || \ + ((PERIPH) == PWM2)) +#define IS_QEP_PERIPH(PERIPH) (((PERIPH) == QEP)) +#define IS_I2C_PERIPH(PERIPH) (((PERIPH) == I2C)) +#define IS_ECAP_PERIPH(PERIPH) (((PERIPH) == ECAP0) || \ + ((PERIPH) == ECAP1) || \ + ((PERIPH) == ECAP2)) + +#ifdef __cplusplus +} +#endif + +#endif /* __K1921VK035_H */ + +/************************** (C) COPYRIGHT 2019 NIIET ************************* +* +* END OF FILE K1921VK035.h */ diff --git a/platform/Device/NIIET/K1921VK035/Include/system_K1921VK035.h b/platform/Device/NIIET/K1921VK035/Include/system_K1921VK035.h new file mode 100644 index 0000000..829ee17 --- /dev/null +++ b/platform/Device/NIIET/K1921VK035/Include/system_K1921VK035.h @@ -0,0 +1,52 @@ +/*============================================================================== + * Инициализация К1921ВК035 + *------------------------------------------------------------------------------ + * НИИЭТ, Богдан Колбов + *============================================================================== + * ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ ПРЕДОСТАВЛЯЕТСЯ «КАК ЕСТЬ», БЕЗ КАКИХ-ЛИБО + * ГАРАНТИЙ, ЯВНО ВЫРАЖЕННЫХ ИЛИ ПОДРАЗУМЕВАЕМЫХ, ВКЛЮЧАЯ ГАРАНТИИ ТОВАРНОЙ + * ПРИГОДНОСТИ, СООТВЕТСТВИЯ ПО ЕГО КОНКРЕТНОМУ НАЗНАЧЕНИЮ И ОТСУТСТВИЯ + * НАРУШЕНИЙ, НО НЕ ОГРАНИЧИВАЯСЬ ИМИ. ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ + * ПРЕДНАЗНАЧЕНО ДЛЯ ОЗНАКОМИТЕЛЬНЫХ ЦЕЛЕЙ И НАПРАВЛЕНО ТОЛЬКО НА + * ПРЕДОСТАВЛЕНИЕ ДОПОЛНИТЕЛЬНОЙ ИНФОРМАЦИИ О ПРОДУКТЕ, С ЦЕЛЬЮ СОХРАНИТЬ ВРЕМЯ + * ПОТРЕБИТЕЛЮ. НИ В КАКОМ СЛУЧАЕ АВТОРЫ ИЛИ ПРАВООБЛАДАТЕЛИ НЕ НЕСУТ + * ОТВЕТСТВЕННОСТИ ПО КАКИМ-ЛИБО ИСКАМ, ЗА ПРЯМОЙ ИЛИ КОСВЕННЫЙ УЩЕРБ, ИЛИ + * ПО ИНЫМ ТРЕБОВАНИЯМ, ВОЗНИКШИМ ИЗ-ЗА ИСПОЛЬЗОВАНИЯ ПРОГРАММНОГО ОБЕСПЕЧЕНИЯ + * ИЛИ ИНЫХ ДЕЙСТВИЙ С ПРОГРАММНЫМ ОБЕСПЕЧЕНИЕМ. + * + * 2018 АО "НИИЭТ" + *============================================================================== + */ + +#ifndef SYSTEM_K1921VK035_H +#define SYSTEM_K1921VK035_H + +#ifdef __cplusplus +extern "C" { +#endif + +//-- Includes ------------------------------------------------------------------ +#include + +//-- Defines ------------------------------------------------------------------- +#define OSICLK_VAL 8000000 +#ifndef OSECLK_VAL +#define OSECLK_VAL 0 +#endif +#define OSECLK_STARTUP_TIMEOUT 0x100000 +#define SYSCLK_SWITCH_TIMEOUT 0x100000 + +//-- Variables ----------------------------------------------------------------- +extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) +extern uint32_t uwTick; +//-- Functions ----------------------------------------------------------------- +// Initialize the System +extern void SystemInit(void); +// Updates the SystemCoreClock with current core Clock retrieved from registers +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif // SYSTEM_K1921VK035_H diff --git a/platform/Device/NIIET/K1921VK035/Source/ARM/startup_K1921VK035.s b/platform/Device/NIIET/K1921VK035/Source/ARM/startup_K1921VK035.s new file mode 100644 index 0000000..efcf387 --- /dev/null +++ b/platform/Device/NIIET/K1921VK035/Source/ARM/startup_K1921VK035.s @@ -0,0 +1,393 @@ +;******************** (C) COPYRIGHT 2018 NIIET ******************** +;* File Name : startup_K1921VK035.s +;* Author : NIIET +;* Version : V1.7 +;* Date : 02.05.2018 +;* Description : K1921VK035 vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, NIIET SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; Watchdog timer interrupt + DCD RCU_IRQHandler ; Reset and clock unit interrupt + DCD MFLASH_IRQHandler ; MFLASH interrupt + DCD GPIOA_IRQHandler ; GPIO A interrupt + DCD GPIOB_IRQHandler ; GPIO B interrupt + DCD DMA_CH0_IRQHandler ; DMA channel 0 interrupt + DCD DMA_CH1_IRQHandler ; DMA channel 1 interrupt + DCD DMA_CH2_IRQHandler ; DMA channel 2 interrupt + DCD DMA_CH3_IRQHandler ; DMA channel 3 interrupt + DCD DMA_CH4_IRQHandler ; DMA channel 4 interrupt + DCD DMA_CH5_IRQHandler ; DMA channel 5 interrupt + DCD DMA_CH6_IRQHandler ; DMA channel 6 interrupt + DCD DMA_CH7_IRQHandler ; DMA channel 7 interrupt + DCD DMA_CH8_IRQHandler ; DMA channel 8 interrupt + DCD DMA_CH9_IRQHandler ; DMA channel 9 interrupt + DCD DMA_CH10_IRQHandler ; DMA channel 10 interrupt + DCD DMA_CH11_IRQHandler ; DMA channel 11 interrupt + DCD DMA_CH12_IRQHandler ; DMA channel 12 interrupt + DCD DMA_CH13_IRQHandler ; DMA channel 13 interrupt + DCD DMA_CH14_IRQHandler ; DMA channel 14 interrupt + DCD DMA_CH15_IRQHandler ; DMA channel 15 interrupt + DCD TMR0_IRQHandler ; Timer 0 interrupt + DCD TMR1_IRQHandler ; Timer 1 interrupt + DCD TMR2_IRQHandler ; Timer 2 interrupt + DCD TMR3_IRQHandler ; Timer 3 interrupt + DCD UART0_TD_IRQHandler ; UART0 Transmit Done interrupt + DCD UART0_RX_IRQHandler ; UART0 Recieve interrupt + DCD UART0_TX_IRQHandler ; UART0 Transmit interrupt + DCD UART0_E_RT_IRQHandler ; UART0 Error and Receive Timeout interrupt + DCD UART1_TD_IRQHandler ; UART1 Transmit Done interrupt + DCD UART1_RX_IRQHandler ; UART1 Recieve interrupt + DCD UART1_TX_IRQHandler ; UART1 Transmit interrupt + DCD UART1_E_RT_IRQHandler ; UART1 Error and Receive Timeout interrupt + DCD SPI_RO_RT_IRQHandler ; SPI RX FIFO overrun and Receive Timeout interrupt + DCD SPI_RX_IRQHandler ; SPI Receive interrupt + DCD SPI_TX_IRQHandler ; SPI Transmit interrupt + DCD I2C_IRQHandler ; I2C interrupt + DCD ECAP0_IRQHandler ; ECAP0 interrupt + DCD ECAP1_IRQHandler ; ECAP1 interrupt + DCD ECAP2_IRQHandler ; ECAP2 interrupt + DCD PWM0_IRQHandler ; PWM0 interrupt + DCD PWM0_HD_IRQHandler ; PWM0 HD interrupt + DCD PWM0_TZ_IRQHandler ; PWM0 TZ interrupt + DCD PWM1_IRQHandler ; PWM1 interrupt + DCD PWM1_HD_IRQHandler ; PWM1 HD interrupt + DCD PWM1_TZ_IRQHandler ; PWM1 TZ interrupt + DCD PWM2_IRQHandler ; PWM2 interrupt + DCD PWM2_HD_IRQHandler ; PWM2 HD interrupt + DCD PWM2_TZ_IRQHandler ; PWM2 TZ interrupt + DCD QEP_IRQHandler ; QEP interrupt + DCD ADC_SEQ0_IRQHandler ; ADC Sequencer 0 interrupt + DCD ADC_SEQ1_IRQHandler ; ADC Sequencer 1 interrupt + DCD ADC_DC_IRQHandler ; ADC Digital Comparator interrupt + DCD CAN0_IRQHandler ; CAN0 interrupt + DCD CAN1_IRQHandler ; CAN1 interrupt + DCD CAN2_IRQHandler ; CAN2 interrupt + DCD CAN3_IRQHandler ; CAN3 interrupt + DCD CAN4_IRQHandler ; CAN4 interrupt + DCD CAN5_IRQHandler ; CAN5 interrupt + DCD CAN6_IRQHandler ; CAN6 interrupt + DCD CAN7_IRQHandler ; CAN7 interrupt + DCD CAN8_IRQHandler ; CAN8 interrupt + DCD CAN9_IRQHandler ; CAN9 interrupt + DCD CAN10_IRQHandler ; CAN10 interrupt + DCD CAN11_IRQHandler ; CAN11 interrupt + DCD CAN12_IRQHandler ; CAN12 interrupt + DCD CAN13_IRQHandler ; CAN13 interrupt + DCD CAN14_IRQHandler ; CAN14 interrupt + DCD CAN15_IRQHandler ; CAN15 interrupt + DCD FPU_IRQHandler ; FPU exception interrupt + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RCU_IRQHandler [WEAK] + EXPORT MFLASH_IRQHandler [WEAK] + EXPORT GPIOA_IRQHandler [WEAK] + EXPORT GPIOB_IRQHandler [WEAK] + EXPORT DMA_CH0_IRQHandler [WEAK] + EXPORT DMA_CH1_IRQHandler [WEAK] + EXPORT DMA_CH2_IRQHandler [WEAK] + EXPORT DMA_CH3_IRQHandler [WEAK] + EXPORT DMA_CH4_IRQHandler [WEAK] + EXPORT DMA_CH5_IRQHandler [WEAK] + EXPORT DMA_CH6_IRQHandler [WEAK] + EXPORT DMA_CH7_IRQHandler [WEAK] + EXPORT DMA_CH8_IRQHandler [WEAK] + EXPORT DMA_CH9_IRQHandler [WEAK] + EXPORT DMA_CH10_IRQHandler [WEAK] + EXPORT DMA_CH11_IRQHandler [WEAK] + EXPORT DMA_CH12_IRQHandler [WEAK] + EXPORT DMA_CH13_IRQHandler [WEAK] + EXPORT DMA_CH14_IRQHandler [WEAK] + EXPORT DMA_CH15_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT UART0_TD_IRQHandler [WEAK] + EXPORT UART0_RX_IRQHandler [WEAK] + EXPORT UART0_TX_IRQHandler [WEAK] + EXPORT UART0_E_RT_IRQHandler [WEAK] + EXPORT UART1_TD_IRQHandler [WEAK] + EXPORT UART1_RX_IRQHandler [WEAK] + EXPORT UART1_TX_IRQHandler [WEAK] + EXPORT UART1_E_RT_IRQHandler [WEAK] + EXPORT SPI_RO_RT_IRQHandler [WEAK] + EXPORT SPI_RX_IRQHandler [WEAK] + EXPORT SPI_TX_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT ECAP0_IRQHandler [WEAK] + EXPORT ECAP1_IRQHandler [WEAK] + EXPORT ECAP2_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM0_HD_IRQHandler [WEAK] + EXPORT PWM0_TZ_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM1_HD_IRQHandler [WEAK] + EXPORT PWM1_TZ_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM2_HD_IRQHandler [WEAK] + EXPORT PWM2_TZ_IRQHandler [WEAK] + EXPORT QEP_IRQHandler [WEAK] + EXPORT ADC_SEQ0_IRQHandler [WEAK] + EXPORT ADC_SEQ1_IRQHandler [WEAK] + EXPORT ADC_DC_IRQHandler [WEAK] + EXPORT CAN0_IRQHandler [WEAK] + EXPORT CAN1_IRQHandler [WEAK] + EXPORT CAN2_IRQHandler [WEAK] + EXPORT CAN3_IRQHandler [WEAK] + EXPORT CAN4_IRQHandler [WEAK] + EXPORT CAN5_IRQHandler [WEAK] + EXPORT CAN6_IRQHandler [WEAK] + EXPORT CAN7_IRQHandler [WEAK] + EXPORT CAN8_IRQHandler [WEAK] + EXPORT CAN9_IRQHandler [WEAK] + EXPORT CAN10_IRQHandler [WEAK] + EXPORT CAN11_IRQHandler [WEAK] + EXPORT CAN12_IRQHandler [WEAK] + EXPORT CAN13_IRQHandler [WEAK] + EXPORT CAN14_IRQHandler [WEAK] + EXPORT CAN15_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + + + +WDT_IRQHandler +RCU_IRQHandler +MFLASH_IRQHandler +GPIOA_IRQHandler +GPIOB_IRQHandler +DMA_CH0_IRQHandler +DMA_CH1_IRQHandler +DMA_CH2_IRQHandler +DMA_CH3_IRQHandler +DMA_CH4_IRQHandler +DMA_CH5_IRQHandler +DMA_CH6_IRQHandler +DMA_CH7_IRQHandler +DMA_CH8_IRQHandler +DMA_CH9_IRQHandler +DMA_CH10_IRQHandler +DMA_CH11_IRQHandler +DMA_CH12_IRQHandler +DMA_CH13_IRQHandler +DMA_CH14_IRQHandler +DMA_CH15_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +UART0_TD_IRQHandler +UART0_RX_IRQHandler +UART0_TX_IRQHandler +UART0_E_RT_IRQHandler +UART1_TD_IRQHandler +UART1_RX_IRQHandler +UART1_TX_IRQHandler +UART1_E_RT_IRQHandler +SPI_RO_RT_IRQHandler +SPI_RX_IRQHandler +SPI_TX_IRQHandler +I2C_IRQHandler +ECAP0_IRQHandler +ECAP1_IRQHandler +ECAP2_IRQHandler +PWM0_IRQHandler +PWM0_HD_IRQHandler +PWM0_TZ_IRQHandler +PWM1_IRQHandler +PWM1_HD_IRQHandler +PWM1_TZ_IRQHandler +PWM2_IRQHandler +PWM2_HD_IRQHandler +PWM2_TZ_IRQHandler +QEP_IRQHandler +ADC_SEQ0_IRQHandler +ADC_SEQ1_IRQHandler +ADC_DC_IRQHandler +CAN0_IRQHandler +CAN1_IRQHandler +CAN2_IRQHandler +CAN3_IRQHandler +CAN4_IRQHandler +CAN5_IRQHandler +CAN6_IRQHandler +CAN7_IRQHandler +CAN8_IRQHandler +CAN9_IRQHandler +CAN10_IRQHandler +CAN11_IRQHandler +CAN12_IRQHandler +CAN13_IRQHandler +CAN14_IRQHandler +CAN15_IRQHandler +FPU_IRQHandler + + + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2018 NIIET *****END OF FILE***** diff --git a/platform/Device/NIIET/K1921VK035/Source/system_K1921VK035.c b/platform/Device/NIIET/K1921VK035/Source/system_K1921VK035.c new file mode 100644 index 0000000..dae457a --- /dev/null +++ b/platform/Device/NIIET/K1921VK035/Source/system_K1921VK035.c @@ -0,0 +1,167 @@ +/*============================================================================== + * Инициализация К1921ВК035 + *------------------------------------------------------------------------------ + * НИИЭТ, Богдан Колбов + *============================================================================== + * ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ ПРЕДОСТАВЛЯЕТСЯ «КАК ЕСТЬ», БЕЗ КАКИХ-ЛИБО + * ГАРАНТИЙ, ЯВНО ВЫРАЖЕННЫХ ИЛИ ПОДРАЗУМЕВАЕМЫХ, ВКЛЮЧАЯ ГАРАНТИИ ТОВАРНОЙ + * ПРИГОДНОСТИ, СООТВЕТСТВИЯ ПО ЕГО КОНКРЕТНОМУ НАЗНАЧЕНИЮ И ОТСУТСТВИЯ + * НАРУШЕНИЙ, НО НЕ ОГРАНИЧИВАЯСЬ ИМИ. ДАННОЕ ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ + * ПРЕДНАЗНАЧЕНО ДЛЯ ОЗНАКОМИТЕЛЬНЫХ ЦЕЛЕЙ И НАПРАВЛЕНО ТОЛЬКО НА + * ПРЕДОСТАВЛЕНИЕ ДОПОЛНИТЕЛЬНОЙ ИНФОРМАЦИИ О ПРОДУКТЕ, С ЦЕЛЬЮ СОХРАНИТЬ ВРЕМЯ + * ПОТРЕБИТЕЛЮ. НИ В КАКОМ СЛУЧАЕ АВТОРЫ ИЛИ ПРАВООБЛАДАТЕЛИ НЕ НЕСУТ + * ОТВЕТСТВЕННОСТИ ПО КАКИМ-ЛИБО ИСКАМ, ЗА ПРЯМОЙ ИЛИ КОСВЕННЫЙ УЩЕРБ, ИЛИ + * ПО ИНЫМ ТРЕБОВАНИЯМ, ВОЗНИКШИМ ИЗ-ЗА ИСПОЛЬЗОВАНИЯ ПРОГРАММНОГО ОБЕСПЕЧЕНИЯ + * ИЛИ ИНЫХ ДЕЙСТВИЙ С ПРОГРАММНЫМ ОБЕСПЕЧЕНИЕМ. + * + * 2018 АО "НИИЭТ" + *============================================================================== + */ + +//-- Includes ------------------------------------------------------------------ +#include "system_K1921VK035.h" +#include "K1921VK035.h" + +//-- Variables ----------------------------------------------------------------- +uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) +uint32_t uwTick; // Milliseconds ticks + +//-- Functions ----------------------------------------------------------------- +void SystemCoreClockUpdate(void) +{ + uint32_t current_sysclk; + uint32_t pll_n, pll_m, pll_od, pll_refclk, pll_div = 1; + + current_sysclk = RCU->SYSCLKSTAT_bit.SYSSTAT; + + switch (current_sysclk) { + case RCU_SYSCLKSTAT_SYSSTAT_OSICLK: + SystemCoreClock = OSICLK_VAL; + break; + case RCU_SYSCLKSTAT_SYSSTAT_OSECLK: + SystemCoreClock = OSECLK_VAL; + break; + case RCU_SYSCLKSTAT_SYSSTAT_PLLDIVCLK: + case RCU_SYSCLKSTAT_SYSSTAT_PLLCLK: + if (current_sysclk == RCU_SYSCLKSTAT_SYSSTAT_PLLDIVCLK) + pll_div = RCU->PLLDIV_bit.DIV + 1; + pll_n = RCU->PLLCFG_bit.N; + pll_m = RCU->PLLCFG_bit.M; + pll_od = RCU->PLLCFG_bit.OD; + if (RCU->PLLCFG_bit.REFSRC == RCU_PLLCFG_REFSRC_OSICLK) + pll_refclk = OSICLK_VAL; + else // RCU->PLLCFG_bit.REFSRC == RCU_PLLCFG_REFSRC_OSECLK + pll_refclk = OSECLK_VAL; + SystemCoreClock = (pll_refclk * pll_m) / (pll_n * (1 << pll_od) * pll_div); + break; + } +} + +void ClkInit() +{ + uint32_t timeout_counter = 0; + uint32_t sysclk_source; + +//clockout control +#if defined CKO_OSI + SIU->CLKOUTCTL = SIU_CLKOUTCTL_CLKOUTEN_Msk; + RCU->CLKOUTCFG = (RCU_CLKOUTCFG_CLKSEL_OSICLK << RCU_CLKOUTCFG_CLKSEL_Pos) | + (RCU_CLKOUTCFG_CLKEN_Msk); //CKO = OSICLK +#elif defined CKO_OSE && (OSECLK_VAL != 0) + SIU->CLKOUTCTL = SIU_CLKOUTCTL_CLKOUTEN_Msk; + RCU->CLKOUTCFG = (RCU_CLKOUTCFG_CLKSEL_OSECLK << RCU_CLKOUTCFG_CLKSEL_Pos) | + (RCU_CLKOUTCFG_CLKEN_Msk); //CKO = OSECLK +#elif defined CKO_PLL + SIU->CLKOUTCTL = SIU_CLKOUTCTL_CLKOUTEN_Msk; + RCU->CLKOUTCFG = (RCU_CLKOUTCFG_CLKSEL_PLLCLK << RCU_CLKOUTCFG_CLKSEL_Pos) | + (1 << RCU_CLKOUTCFG_DIVN_Pos) | + (RCU_CLKOUTCFG_DIVEN_Msk) | + (RCU_CLKOUTCFG_CLKEN_Msk); //CKO = PLLCLK/4 +#endif + +//wait till external oscillator is ready +#if defined OSECLK_VAL && (OSECLK_VAL != 0) + while ((!RCU->SYSCLKSTAT_bit.OSECLKOK) && (timeout_counter < OSECLK_STARTUP_TIMEOUT)) + timeout_counter++; + if (timeout_counter == OSECLK_STARTUP_TIMEOUT) //OSE failed to startup + while (1) { + }; +#endif + +//select system clock +#ifdef SYSCLK_PLL +//PLLCLK = REFSRC * (M/N) * (1/(2^OD)) +#if (OSECLK_VAL == 8000000) + RCU->PLLCFG = (RCU_PLLCFG_REFSRC_OSECLK << RCU_PLLCFG_REFSRC_Pos) | + (1 << RCU_PLLCFG_N_Pos) | + (25 << RCU_PLLCFG_M_Pos); +#elif (OSECLK_VAL == 12000000) + RCU->PLLCFG = (RCU_PLLCFG_REFSRC_OSECLK << RCU_PLLCFG_REFSRC_Pos) | + (3 << RCU_PLLCFG_N_Pos) | + (50 << RCU_PLLCFG_M_Pos); +#elif (OSECLK_VAL == 16000000) + RCU->PLLCFG = (RCU_PLLCFG_REFSRC_OSECLK << RCU_PLLCFG_REFSRC_Pos) | + (2 << RCU_PLLCFG_N_Pos) | + (25 << RCU_PLLCFG_M_Pos); +#elif (OSECLK_VAL == 20000000) + RCU->PLLCFG = (RCU_PLLCFG_REFSRC_OSECLK << RCU_PLLCFG_REFSRC_Pos) | + (2 << RCU_PLLCFG_N_Pos) | + (20 << RCU_PLLCFG_M_Pos); +#elif (OSECLK_VAL == 24000000) + RCU->PLLCFG = (RCU_PLLCFG_REFSRC_OSECLK << RCU_PLLCFG_REFSRC_Pos) | + (3 << RCU_PLLCFG_N_Pos) | + (25 << RCU_PLLCFG_M_Pos); +#elif defined OSICLK_VAL + RCU->PLLCFG = (RCU_PLLCFG_REFSRC_OSICLK << RCU_PLLCFG_REFSRC_Pos) | + (1 << RCU_PLLCFG_N_Pos) | + (25 << RCU_PLLCFG_M_Pos); +#else +#error "Please define OSICLK_VAL and OSECLK_VAL with correct values!" +#endif + RCU->PLLCFG |= (1 << RCU_PLLCFG_OD_Pos) | + (RCU_PLLCFG_OUTEN_Msk); + while (!RCU->PLLCFG_bit.LOCK) { + }; + // additional waitstates + MFLASH->CTRL = (3 << MFLASH_CTRL_LAT_Pos); + //select PLL as source system clock + sysclk_source = RCU_SYSCLKCFG_SYSSEL_PLLCLK; +#elif defined SYSCLK_OSI + sysclk_source = RCU_SYSCLKCFG_SYSSEL_OSICLK; +#elif defined SYSCLK_OSE + sysclk_source = RCU_SYSCLKCFG_SYSSEL_OSECLK; +#else +#error "Please define SYSCLK source (SYSCLK_PLL | SYSCLK_OSI | SYSCLK_OSE)!" +#endif + + //switch sysclk + RCU->SYSCLKCFG = (sysclk_source << RCU_SYSCLKCFG_SYSSEL_Pos); + // Wait switching done + timeout_counter = 0; + while ((RCU->SYSCLKSTAT_bit.SYSSTAT != RCU->SYSCLKCFG_bit.SYSSEL) && (timeout_counter < SYSCLK_SWITCH_TIMEOUT)) + timeout_counter++; + if (timeout_counter == SYSCLK_SWITCH_TIMEOUT) //SYSCLK failed to switch + while (1) { + }; + + //flush and enable cache + MFLASH->CTRL_bit.IFLUSH = 1; + while (MFLASH->ICSTAT_bit.BUSY) { + }; + MFLASH->CTRL_bit.DFLUSH = 1; + while (MFLASH->DCSTAT_bit.BUSY) { + }; + MFLASH->CTRL |= (MFLASH_CTRL_DCEN_Msk) | (MFLASH_CTRL_ICEN_Msk) | (MFLASH_CTRL_PEN_Msk); +} + +void FPUInit() +{ + SCB->CPACR = 0x00F00000; + __DSB(); + __ISB(); +} +void SystemInit(void) +{ + ClkInit(); + FPUInit(); +} diff --git a/platform/Device/NIIET/K1921VK035/РП_1921ВК035_201219.pdf b/platform/Device/NIIET/K1921VK035/РП_1921ВК035_201219.pdf new file mode 100644 index 0000000000000000000000000000000000000000..ac78e7774436086ec80334f443110b49044fcf93 GIT binary patch literal 7685928 zcmdpf2|SeF_rLa1XwgC{Dv1iuGFz*V5GsU{N|L3JHPTKh?Vl_qE!tID(W-q<8%0rC zkSNkdrSiY?Ja=%%jAWkC_xJz2UQ?fH#&hSK_u0=qM}3^3(I8BlB`2$%1pbqg#Z+}w zy{5a%$qpT=V;wZdS;xT9&vCYwi_SPl7iV8p9Q?DTj+vvUOMf5#L6#FVRduZVeEgmK ztbLrFExo+_R532WrrtEx-*2{?C-@9T=n~Z5m^=E+GVz@01%5RDf1PKjf{!{62mi^* zI(yEb9?O3K@_g#KItE_;o_?wXm!~tvZHBMCD)j?ZasFv7RdEje8<+l#NBu_7|3=X7 zq|c;E(C;MZcM|kFN&1~6_1#oSlKMDFzlEhs{fR~YC5uJ>iT)g${x>%LIX3+uHudFI z+4RRb^jkReTR8Mj;m|*YL%)+lABjVMfJ=XXOMie%|4c6Z0WSRkF8u*6`~ZCx9{o8U z{Z)AM$9eR}dGup>^iSc@ALr4Z!*uBnV!HGvFcnpW{gY3Zw_&fr>kAOcHG7N(p!ywBr$Se$U3xn*!NO%qs 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