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Dimas
2026-07-09 14:50:52 +03:00
parent 88ddb37225
commit fc2788881f
66 changed files with 19517 additions and 237 deletions
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242
v120/DSP2833x_headers/include/DSP2833x_EQep.h Normal file
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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:52:13 $
//###########################################################################
//
// FILE: DSP2833x_EQep.h
//
// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module
// Register Bit Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_EQEP_H
#define DSP2833x_EQEP_H
#ifdef __cplusplus
extern "C" {
#endif
//----------------------------------------------------
// Capture decoder control register bit definitions */
struct QDECCTL_BITS { // bits description
Uint16 rsvd1:5; // 4:0 reserved
Uint16 QSP:1; // 5 QEPS input polarity
Uint16 QIP:1; // 6 QEPI input polarity
Uint16 QBP:1; // 7 QEPB input polarity
Uint16 QAP:1; // 8 QEPA input polarity
Uint16 IGATE:1; // 9 Index pulse gating option
Uint16 SWAP:1; // 10 CLK/DIR signal source for Position Counter
Uint16 XCR:1; // 11 External clock rate
Uint16 SPSEL:1; // 12 Sync output pin select
Uint16 SOEN:1; // 13 Enable position compare sync
Uint16 QSRC:2; // 15:14 Position counter source
};
union QDECCTL_REG {
Uint16 all;
struct QDECCTL_BITS bit;
};
//----------------------------------------------------
// QEP control register bit definitions */
struct QEPCTL_BITS { // bits description
Uint16 WDE:1; // 0 QEP watchdog enable
Uint16 UTE:1; // 1 QEP unit timer enable
Uint16 QCLM:1; // 2 QEP capture latch mode
Uint16 QPEN:1; // 3 Quadrature position counter enable
Uint16 IEL:2; // 5:4 Index event latch
Uint16 SEL:1; // 6 Strobe event latch
Uint16 SWI:1; // 7 Software init position counter
Uint16 IEI:2; // 9:8 Index event init of position count
Uint16 SEI:2; // 11:10 Strobe event init
Uint16 PCRM:2; // 13:12 Position counter reset
Uint16 FREE_SOFT:2; // 15:14 Emulation mode
};
union QEPCTL_REG {
Uint16 all;
struct QEPCTL_BITS bit;
};
//----------------------------------------------------
// Quadrature capture control register bit definitions */
struct QCAPCTL_BITS { // bits description
Uint16 UPPS:4; // 3:0 Unit position pre-scale
Uint16 CCPS:3; // 6:4 QEP capture timer pre-scale
Uint16 rsvd1:8; // 14:7 reserved
Uint16 CEN:1; // 15 Enable QEP capture
};
union QCAPCTL_REG {
Uint16 all;
struct QCAPCTL_BITS bit;
};
//----------------------------------------------------
// Position compare control register bit definitions */
struct QPOSCTL_BITS { // bits description
Uint16 PCSPW:12; // 11:0 Position compare sync pulse width
Uint16 PCE:1; // 12 Position compare enable/disable
Uint16 PCPOL:1; // 13 Polarity of sync output
Uint16 PCLOAD:1; // 14 Position compare of shadow load
Uint16 PCSHDW:1; // 15 Position compare shadow enable
};
union QPOSCTL_REG {
Uint16 all;
struct QPOSCTL_BITS bit;
};
//----------------------------------------------------
// QEP interrupt control register bit definitions */
struct QEINT_BITS { // bits description
Uint16 rsvd1:1; // 0 reserved
Uint16 PCE:1; // 1 Position counter error
Uint16 QPE:1; // 2 Quadrature phase error
Uint16 QDC:1; // 3 Quadrature dir change
Uint16 WTO:1; // 4 Watchdog timeout
Uint16 PCU:1; // 5 Position counter underflow
Uint16 PCO:1; // 6 Position counter overflow
Uint16 PCR:1; // 7 Position compare ready
Uint16 PCM:1; // 8 Position compare match
Uint16 SEL:1; // 9 Strobe event latch
Uint16 IEL:1; // 10 Event latch
Uint16 UTO:1; // 11 Unit timeout
Uint16 rsvd2:4; // 15:12 reserved
};
union QEINT_REG {
Uint16 all;
struct QEINT_BITS bit;
};
//----------------------------------------------------
// QEP interrupt status register bit definitions */
struct QFLG_BITS { // bits description
Uint16 INT:1; // 0 Global interrupt
Uint16 PCE:1; // 1 Position counter error
Uint16 PHE:1; // 2 Quadrature phase error
Uint16 QDC:1; // 3 Quadrature dir change
Uint16 WTO:1; // 4 Watchdog timeout
Uint16 PCU:1; // 5 Position counter underflow
Uint16 PCO:1; // 6 Position counter overflow
Uint16 PCR:1; // 7 Position compare ready
Uint16 PCM:1; // 8 Position compare match
Uint16 SEL:1; // 9 Strobe event latch
Uint16 IEL:1; // 10 Event latch
Uint16 UTO:1; // 11 Unit timeout
Uint16 rsvd2:4; // 15:12 reserved
};
union QFLG_REG {
Uint16 all;
struct QFLG_BITS bit;
};
//----------------------------------------------------
// QEP interrupt force register bit definitions */
struct QFRC_BITS { // bits description
Uint16 reserved:1; // 0 Reserved
Uint16 PCE:1; // 1 Position counter error
Uint16 PHE:1; // 2 Quadrature phase error
Uint16 QDC:1; // 3 Quadrature dir change
Uint16 WTO:1; // 4 Watchdog timeout
Uint16 PCU:1; // 5 Position counter underflow
Uint16 PCO:1; // 6 Position counter overflow
Uint16 PCR:1; // 7 Position compare ready
Uint16 PCM:1; // 8 Position compare match
Uint16 SEL:1; // 9 Strobe event latch
Uint16 IEL:1; // 10 Event latch
Uint16 UTO:1; // 11 Unit timeout
Uint16 rsvd2:4; // 15:12 reserved
};
union QFRC_REG {
Uint16 all;
struct QFRC_BITS bit;
};
// V1.1 Added UPEVNT (bit 7) This reflects changes
// made as of F2833x Rev A devices
//----------------------------------------------------
// QEP status register bit definitions */
struct QEPSTS_BITS { // bits description
Uint16 PCEF:1; // 0 Position counter error
Uint16 FIMF:1; // 1 First index marker
Uint16 CDEF:1; // 2 Capture direction error
Uint16 COEF:1; // 3 Capture overflow error
Uint16 QDLF:1; // 4 QEP direction latch
Uint16 QDF:1; // 5 Quadrature direction
Uint16 FIDF:1; // 6 Direction on first index marker
Uint16 UPEVNT:1; // 7 Unit position event flag
Uint16 rsvd1:8; // 15:8 reserved
};
union QEPSTS_REG {
Uint16 all;
struct QEPSTS_BITS bit;
};
//----------------------------------------------------
struct EQEP_REGS {
Uint32 QPOSCNT; // Position counter
Uint32 QPOSINIT; // Position counter init
Uint32 QPOSMAX; // Maximum position count
Uint32 QPOSCMP; // Position compare
Uint32 QPOSILAT; // Index position latch
Uint32 QPOSSLAT; // Strobe position latch
Uint32 QPOSLAT; // Position latch
Uint32 QUTMR; // Unit timer
Uint32 QUPRD; // Unit period
Uint16 QWDTMR; // QEP watchdog timer
Uint16 QWDPRD; // QEP watchdog period
union QDECCTL_REG QDECCTL; // Quadrature decoder control
union QEPCTL_REG QEPCTL; // QEP control
union QCAPCTL_REG QCAPCTL; // Quadrature capture control
union QPOSCTL_REG QPOSCTL; // Position compare control
union QEINT_REG QEINT; // QEP interrupt control
union QFLG_REG QFLG; // QEP interrupt flag
union QFLG_REG QCLR; // QEP interrupt clear
union QFRC_REG QFRC; // QEP interrupt force
union QEPSTS_REG QEPSTS; // QEP status
Uint16 QCTMR; // QEP capture timer
Uint16 QCPRD; // QEP capture period
Uint16 QCTMRLAT; // QEP capture latch
Uint16 QCPRDLAT; // QEP capture period latch
Uint16 rsvd1[30]; // reserved
};
//---------------------------------------------------------------------------
// GPI/O External References & Function Declarations:
//
extern volatile struct EQEP_REGS EQep1Regs;
extern volatile struct EQEP_REGS EQep2Regs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_EQEP_H definition
//===========================================================================
// End of file.
//===========================================================================

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v120/DSP2833x_headers/include/DSP2833x_Gpio.h Normal file
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// TI File $Revision: /main/4 $
// Checkin $Date: November 15, 2007 09:58:53 $
//###########################################################################
//
// FILE: DSP2833x_Gpio.h
//
// TITLE: DSP2833x General Purpose I/O Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_GPIO_H
#define DSP2833x_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
//----------------------------------------------------
// GPIO A control register bit definitions */
struct GPACTRL_BITS { // bits description
Uint16 QUALPRD0:8; // 7:0 Qual period
Uint16 QUALPRD1:8; // 15:8 Qual period
Uint16 QUALPRD2:8; // 23:16 Qual period
Uint16 QUALPRD3:8; // 31:24 Qual period
};
union GPACTRL_REG {
Uint32 all;
struct GPACTRL_BITS bit;
};
//----------------------------------------------------
// GPIO B control register bit definitions */
struct GPBCTRL_BITS { // bits description
Uint16 QUALPRD0:8; // 7:0 Qual period
Uint16 QUALPRD1:8; // 15:8 Qual period
Uint16 QUALPRD2:8; // 23:16 Qual period
Uint16 QUALPRD3:8; // 31:24
};
union GPBCTRL_REG {
Uint32 all;
struct GPBCTRL_BITS bit;
};
//----------------------------------------------------
// GPIO A Qual/MUX select register bit definitions */
struct GPA1_BITS { // bits description
Uint16 GPIO0:2; // 1:0 GPIO0
Uint16 GPIO1:2; // 3:2 GPIO1
Uint16 GPIO2:2; // 5:4 GPIO2
Uint16 GPIO3:2; // 7:6 GPIO3
Uint16 GPIO4:2; // 9:8 GPIO4
Uint16 GPIO5:2; // 11:10 GPIO5
Uint16 GPIO6:2; // 13:12 GPIO6
Uint16 GPIO7:2; // 15:14 GPIO7
Uint16 GPIO8:2; // 17:16 GPIO8
Uint16 GPIO9:2; // 19:18 GPIO9
Uint16 GPIO10:2; // 21:20 GPIO10
Uint16 GPIO11:2; // 23:22 GPIO11
Uint16 GPIO12:2; // 25:24 GPIO12
Uint16 GPIO13:2; // 27:26 GPIO13
Uint16 GPIO14:2; // 29:28 GPIO14
Uint16 GPIO15:2; // 31:30 GPIO15
};
struct GPA2_BITS { // bits description
Uint16 GPIO16:2; // 1:0 GPIO16
Uint16 GPIO17:2; // 3:2 GPIO17
Uint16 GPIO18:2; // 5:4 GPIO18
Uint16 GPIO19:2; // 7:6 GPIO19
Uint16 GPIO20:2; // 9:8 GPIO20
Uint16 GPIO21:2; // 11:10 GPIO21
Uint16 GPIO22:2; // 13:12 GPIO22
Uint16 GPIO23:2; // 15:14 GPIO23
Uint16 GPIO24:2; // 17:16 GPIO24
Uint16 GPIO25:2; // 19:18 GPIO25
Uint16 GPIO26:2; // 21:20 GPIO26
Uint16 GPIO27:2; // 23:22 GPIO27
Uint16 GPIO28:2; // 25:24 GPIO28
Uint16 GPIO29:2; // 27:26 GPIO29
Uint16 GPIO30:2; // 29:28 GPIO30
Uint16 GPIO31:2; // 31:30 GPIO31
};
struct GPB1_BITS { // bits description
Uint16 GPIO32:2; // 1:0 GPIO32
Uint16 GPIO33:2; // 3:2 GPIO33
Uint16 GPIO34:2; // 5:4 GPIO34
Uint16 GPIO35:2; // 7:6 GPIO35
Uint16 GPIO36:2; // 9:8 GPIO36
Uint16 GPIO37:2; // 11:10 GPIO37
Uint16 GPIO38:2; // 13:12 GPIO38
Uint16 GPIO39:2; // 15:14 GPIO39
Uint16 GPIO40:2; // 17:16 GPIO40
Uint16 GPIO41:2; // 19:16 GPIO41
Uint16 GPIO42:2; // 21:20 GPIO42
Uint16 GPIO43:2; // 23:22 GPIO43
Uint16 GPIO44:2; // 25:24 GPIO44
Uint16 GPIO45:2; // 27:26 GPIO45
Uint16 GPIO46:2; // 29:28 GPIO46
Uint16 GPIO47:2; // 31:30 GPIO47
};
struct GPB2_BITS { // bits description
Uint16 GPIO48:2; // 1:0 GPIO48
Uint16 GPIO49:2; // 3:2 GPIO49
Uint16 GPIO50:2; // 5:4 GPIO50
Uint16 GPIO51:2; // 7:6 GPIO51
Uint16 GPIO52:2; // 9:8 GPIO52
Uint16 GPIO53:2; // 11:10 GPIO53
Uint16 GPIO54:2; // 13:12 GPIO54
Uint16 GPIO55:2; // 15:14 GPIO55
Uint16 GPIO56:2; // 17:16 GPIO56
Uint16 GPIO57:2; // 19:18 GPIO57
Uint16 GPIO58:2; // 21:20 GPIO58
Uint16 GPIO59:2; // 23:22 GPIO59
Uint16 GPIO60:2; // 25:24 GPIO60
Uint16 GPIO61:2; // 27:26 GPIO61
Uint16 GPIO62:2; // 29:28 GPIO62
Uint16 GPIO63:2; // 31:30 GPIO63
};
struct GPC1_BITS { // bits description
Uint16 GPIO64:2; // 1:0 GPIO64
Uint16 GPIO65:2; // 3:2 GPIO65
Uint16 GPIO66:2; // 5:4 GPIO66
Uint16 GPIO67:2; // 7:6 GPIO67
Uint16 GPIO68:2; // 9:8 GPIO68
Uint16 GPIO69:2; // 11:10 GPIO69
Uint16 GPIO70:2; // 13:12 GPIO70
Uint16 GPIO71:2; // 15:14 GPIO71
Uint16 GPIO72:2; // 17:16 GPIO72
Uint16 GPIO73:2; // 19:18 GPIO73
Uint16 GPIO74:2; // 21:20 GPIO74
Uint16 GPIO75:2; // 23:22 GPIO75
Uint16 GPIO76:2; // 25:24 GPIO76
Uint16 GPIO77:2; // 27:26 GPIO77
Uint16 GPIO78:2; // 29:28 GPIO78
Uint16 GPIO79:2; // 31:30 GPIO79
};
struct GPC2_BITS { // bits description
Uint16 GPIO80:2; // 1:0 GPIO80
Uint16 GPIO81:2; // 3:2 GPIO81
Uint16 GPIO82:2; // 5:4 GPIO82
Uint16 GPIO83:2; // 7:6 GPIO83
Uint16 GPIO84:2; // 9:8 GPIO84
Uint16 GPIO85:2; // 11:10 GPIO85
Uint16 GPIO86:2; // 13:12 GPIO86
Uint16 GPIO87:2; // 15:14 GPIO87
Uint16 rsvd:16; // 31:16 reserved
};
union GPA1_REG {
Uint32 all;
struct GPA1_BITS bit;
};
union GPA2_REG {
Uint32 all;
struct GPA2_BITS bit;
};
union GPB1_REG {
Uint32 all;
struct GPB1_BITS bit;
};
union GPB2_REG {
Uint32 all;
struct GPB2_BITS bit;
};
union GPC1_REG {
Uint32 all;
struct GPC1_BITS bit;
};
union GPC2_REG {
Uint32 all;
struct GPC2_BITS bit;
};
//----------------------------------------------------
// GPIO A DIR/TOGGLE/SET/CLEAR register bit definitions */
struct GPADAT_BITS { // bits description
Uint16 GPIO0:1; // 0 GPIO0
Uint16 GPIO1:1; // 1 GPIO1
Uint16 GPIO2:1; // 2 GPIO2
Uint16 GPIO3:1; // 3 GPIO3
Uint16 GPIO4:1; // 4 GPIO4
Uint16 GPIO5:1; // 5 GPIO5
Uint16 GPIO6:1; // 6 GPIO6
Uint16 GPIO7:1; // 7 GPIO7
Uint16 GPIO8:1; // 8 GPIO8
Uint16 GPIO9:1; // 9 GPIO9
Uint16 GPIO10:1; // 10 GPIO10
Uint16 GPIO11:1; // 11 GPIO11
Uint16 GPIO12:1; // 12 GPIO12
Uint16 GPIO13:1; // 13 GPIO13
Uint16 GPIO14:1; // 14 GPIO14
Uint16 GPIO15:1; // 15 GPIO15
Uint16 GPIO16:1; // 16 GPIO16
Uint16 GPIO17:1; // 17 GPIO17
Uint16 GPIO18:1; // 18 GPIO18
Uint16 GPIO19:1; // 19 GPIO19
Uint16 GPIO20:1; // 20 GPIO20
Uint16 GPIO21:1; // 21 GPIO21
Uint16 GPIO22:1; // 22 GPIO22
Uint16 GPIO23:1; // 23 GPIO23
Uint16 GPIO24:1; // 24 GPIO24
Uint16 GPIO25:1; // 25 GPIO25
Uint16 GPIO26:1; // 26 GPIO26
Uint16 GPIO27:1; // 27 GPIO27
Uint16 GPIO28:1; // 28 GPIO28
Uint16 GPIO29:1; // 29 GPIO29
Uint16 GPIO30:1; // 30 GPIO30
Uint16 GPIO31:1; // 31 GPIO31
};
struct GPBDAT_BITS { // bits description
Uint16 GPIO32:1; // 0 GPIO32
Uint16 GPIO33:1; // 1 GPIO33
Uint16 GPIO34:1; // 2 GPIO34
Uint16 GPIO35:1; // 3 GPIO35
Uint16 GPIO36:1; // 4 GPIO36
Uint16 GPIO37:1; // 5 GPIO37
Uint16 GPIO38:1; // 6 GPIO38
Uint16 GPIO39:1; // 7 GPIO39
Uint16 GPIO40:1; // 8 GPIO40
Uint16 GPIO41:1; // 9 GPIO41
Uint16 GPIO42:1; // 10 GPIO42
Uint16 GPIO43:1; // 11 GPIO43
Uint16 GPIO44:1; // 12 GPIO44
Uint16 GPIO45:1; // 13 GPIO45
Uint16 GPIO46:1; // 14 GPIO46
Uint16 GPIO47:1; // 15 GPIO47
Uint16 GPIO48:1; // 16 GPIO48
Uint16 GPIO49:1; // 17 GPIO49
Uint16 GPIO50:1; // 18 GPIO50
Uint16 GPIO51:1; // 19 GPIO51
Uint16 GPIO52:1; // 20 GPIO52
Uint16 GPIO53:1; // 21 GPIO53
Uint16 GPIO54:1; // 22 GPIO54
Uint16 GPIO55:1; // 23 GPIO55
Uint16 GPIO56:1; // 24 GPIO56
Uint16 GPIO57:1; // 25 GPIO57
Uint16 GPIO58:1; // 26 GPIO58
Uint16 GPIO59:1; // 27 GPIO59
Uint16 GPIO60:1; // 28 GPIO60
Uint16 GPIO61:1; // 29 GPIO61
Uint16 GPIO62:1; // 30 GPIO62
Uint16 GPIO63:1; // 31 GPIO63
};
struct GPCDAT_BITS { // bits description
Uint16 GPIO64:1; // 0 GPIO64
Uint16 GPIO65:1; // 1 GPIO65
Uint16 GPIO66:1; // 2 GPIO66
Uint16 GPIO67:1; // 3 GPIO67
Uint16 GPIO68:1; // 4 GPIO68
Uint16 GPIO69:1; // 5 GPIO69
Uint16 GPIO70:1; // 6 GPIO70
Uint16 GPIO71:1; // 7 GPIO71
Uint16 GPIO72:1; // 8 GPIO72
Uint16 GPIO73:1; // 9 GPIO73
Uint16 GPIO74:1; // 10 GPIO74
Uint16 GPIO75:1; // 11 GPIO75
Uint16 GPIO76:1; // 12 GPIO76
Uint16 GPIO77:1; // 13 GPIO77
Uint16 GPIO78:1; // 14 GPIO78
Uint16 GPIO79:1; // 15 GPIO79
Uint16 GPIO80:1; // 16 GPIO80
Uint16 GPIO81:1; // 17 GPIO81
Uint16 GPIO82:1; // 18 GPIO82
Uint16 GPIO83:1; // 19 GPIO83
Uint16 GPIO84:1; // 20 GPIO84
Uint16 GPIO85:1; // 21 GPIO85
Uint16 GPIO86:1; // 22 GPIO86
Uint16 GPIO87:1; // 23 GPIO87
Uint16 rsvd1:8; // 31:24 reserved
};
union GPADAT_REG {
Uint32 all;
struct GPADAT_BITS bit;
};
union GPBDAT_REG {
Uint32 all;
struct GPBDAT_BITS bit;
};
union GPCDAT_REG {
Uint32 all;
struct GPCDAT_BITS bit;
};
//----------------------------------------------------
// GPIO Xint1/XINT2/XNMI select register bit definitions */
struct GPIOXINT_BITS { // bits description
Uint16 GPIOSEL:5; // 4:0 Select GPIO interrupt input source
Uint16 rsvd1:11; // 15:5 reserved
};
union GPIOXINT_REG {
Uint16 all;
struct GPIOXINT_BITS bit;
};
struct GPIO_CTRL_REGS {
union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31)
union GPA1_REG GPAQSEL1; // GPIO A Qualifier Select 1 Register (GPIO0 to 15)
union GPA2_REG GPAQSEL2; // GPIO A Qualifier Select 2 Register (GPIO16 to 31)
union GPA1_REG GPAMUX1; // GPIO A Mux 1 Register (GPIO0 to 15)
union GPA2_REG GPAMUX2; // GPIO A Mux 2 Register (GPIO16 to 31)
union GPADAT_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31)
union GPADAT_REG GPAPUD; // GPIO A Pull Up Disable Register (GPIO0 to 31)
Uint32 rsvd1;
union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 63)
union GPB1_REG GPBQSEL1; // GPIO B Qualifier Select 1 Register (GPIO32 to 47)
union GPB2_REG GPBQSEL2; // GPIO B Qualifier Select 2 Register (GPIO48 to 63)
union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47)
union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63)
union GPBDAT_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63)
union GPBDAT_REG GPBPUD; // GPIO B Pull Up Disable Register (GPIO32 to 63)
Uint16 rsvd2[8];
union GPC1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79)
union GPC2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95)
union GPCDAT_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95)
union GPCDAT_REG GPCPUD; // GPIO C Pull Up Disable Register (GPIO64 to 95)
};
struct GPIO_DATA_REGS {
union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31)
union GPADAT_REG GPASET; // GPIO Data Set Register (GPIO0 to 31)
union GPADAT_REG GPACLEAR; // GPIO Data Clear Register (GPIO0 to 31)
union GPADAT_REG GPATOGGLE; // GPIO Data Toggle Register (GPIO0 to 31)
union GPBDAT_REG GPBDAT; // GPIO Data Register (GPIO32 to 63)
union GPBDAT_REG GPBSET; // GPIO Data Set Register (GPIO32 to 63)
union GPBDAT_REG GPBCLEAR; // GPIO Data Clear Register (GPIO32 to 63)
union GPBDAT_REG GPBTOGGLE; // GPIO Data Toggle Register (GPIO32 to 63)
union GPCDAT_REG GPCDAT; // GPIO Data Register (GPIO64 to 95)
union GPCDAT_REG GPCSET; // GPIO Data Set Register (GPIO64 to 95)
union GPCDAT_REG GPCCLEAR; // GPIO Data Clear Register (GPIO64 to 95)
union GPCDAT_REG GPCTOGGLE; // GPIO Data Toggle Register (GPIO64 to 95)
Uint16 rsvd1[8];
};
struct GPIO_INT_REGS {
union GPIOXINT_REG GPIOXINT1SEL; // XINT1 GPIO Input Selection
union GPIOXINT_REG GPIOXINT2SEL; // XINT2 GPIO Input Selection
union GPIOXINT_REG GPIOXNMISEL; // XNMI_Xint13 GPIO Input Selection
union GPIOXINT_REG GPIOXINT3SEL; // XINT3 GPIO Input Selection
union GPIOXINT_REG GPIOXINT4SEL; // XINT4 GPIO Input Selection
union GPIOXINT_REG GPIOXINT5SEL; // XINT5 GPIO Input Selection
union GPIOXINT_REG GPIOXINT6SEL; // XINT6 GPIO Input Selection
union GPIOXINT_REG GPIOXINT7SEL; // XINT7 GPIO Input Selection
union GPADAT_REG GPIOLPMSEL; // Low power modes GP I/O input select
};
//---------------------------------------------------------------------------
// GPI/O External References & Function Declarations:
//
extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs;
extern volatile struct GPIO_DATA_REGS GpioDataRegs;
extern volatile struct GPIO_INT_REGS GpioIntRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_GPIO_H definition
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/2 $
// Checkin $Date: March 22, 2007 10:40:22 $
//###########################################################################
//
// FILE: DSP2833x_I2c.h
//
// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module
// Register Bit Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_I2C_H
#define DSP2833x_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
//----------------------------------------------------
// I2C interrupt vector register bit definitions */
struct I2CISRC_BITS { // bits description
Uint16 INTCODE:3; // 2:0 Interrupt code
Uint16 rsvd1:13; // 15:3 reserved
};
union I2CISRC_REG {
Uint16 all;
struct I2CISRC_BITS bit;
};
//----------------------------------------------------
// I2C interrupt mask register bit definitions */
struct I2CIER_BITS { // bits description
Uint16 ARBL:1; // 0 Arbitration lost interrupt
Uint16 NACK:1; // 1 No ack interrupt
Uint16 ARDY:1; // 2 Register access ready interrupt
Uint16 RRDY:1; // 3 Recieve data ready interrupt
Uint16 XRDY:1; // 4 Transmit data ready interrupt
Uint16 SCD:1; // 5 Stop condition detection
Uint16 AAS:1; // 6 Address as slave
Uint16 rsvd:9; // 15:7 reserved
};
union I2CIER_REG {
Uint16 all;
struct I2CIER_BITS bit;
};
//----------------------------------------------------
// I2C status register bit definitions */
struct I2CSTR_BITS { // bits description
Uint16 ARBL:1; // 0 Arbitration lost interrupt
Uint16 NACK:1; // 1 No ack interrupt
Uint16 ARDY:1; // 2 Register access ready interrupt
Uint16 RRDY:1; // 3 Recieve data ready interrupt
Uint16 XRDY:1; // 4 Transmit data ready interrupt
Uint16 SCD:1; // 5 Stop condition detection
Uint16 rsvd1:2; // 7:6 reserved
Uint16 AD0:1; // 8 Address Zero
Uint16 AAS:1; // 9 Address as slave
Uint16 XSMT:1; // 10 XMIT shift empty
Uint16 RSFULL:1; // 11 Recieve shift full
Uint16 BB:1; // 12 Bus busy
Uint16 NACKSNT:1; // 13 A no ack sent
Uint16 SDIR:1; // 14 Slave direction
Uint16 rsvd2:1; // 15 reserved
};
union I2CSTR_REG {
Uint16 all;
struct I2CSTR_BITS bit;
};
//----------------------------------------------------
// I2C mode control register bit definitions */
struct I2CMDR_BITS { // bits description
Uint16 BC:3; // 2:0 Bit count
Uint16 FDF:1; // 3 Free data format
Uint16 STB:1; // 4 Start byte
Uint16 IRS:1; // 5 I2C Reset not
Uint16 DLB:1; // 6 Digital loopback
Uint16 RM:1; // 7 Repeat mode
Uint16 XA:1; // 8 Expand address
Uint16 TRX:1; // 9 Transmitter/reciever
Uint16 MST:1; // 10 Master/slave
Uint16 STP:1; // 11 Stop condition
Uint16 rsvd1:1; // 12 reserved
Uint16 STT:1; // 13 Start condition
Uint16 FREE:1; // 14 Emulation mode
Uint16 NACKMOD:1; // 15 No Ack mode
};
union I2CMDR_REG {
Uint16 all;
struct I2CMDR_BITS bit;
};
//----------------------------------------------------
// I2C pre-scaler register bit definitions */
struct I2CPSC_BITS { // bits description
Uint16 IPSC:8; // 7:0 pre-scaler
Uint16 rsvd1:8; // 15:8 reserved
};
union I2CPSC_REG {
Uint16 all;
struct I2CPSC_BITS bit;
};
//----------------------------------------------------
// TX FIFO control register bit definitions */
struct I2CFFTX_BITS { // bits description
Uint16 TXFFIL:5; // 4:0 FIFO interrupt level
Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable
Uint16 TXFFINTCLR:1; // 6 FIFO clear
Uint16 TXFFINT:1; // 7 FIFO interrupt flag
Uint16 TXFFST:5; // 12:8 FIFO level status
Uint16 TXFFRST:1; // 13 FIFO reset
Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs
Uint16 rsvd1:1; // 15 reserved
};
union I2CFFTX_REG {
Uint16 all;
struct I2CFFTX_BITS bit;
};
//----------------------------------------------------
// RX FIFO control register bit definitions */
struct I2CFFRX_BITS { // bits description
Uint16 RXFFIL:5; // 4:0 FIFO interrupt level
Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable
Uint16 RXFFINTCLR:1; // 6 FIFO clear
Uint16 RXFFINT:1; // 7 FIFO interrupt flag
Uint16 RXFFST:5; // 12:8 FIFO level
Uint16 RXFFRST:1; // 13 FIFO reset
Uint16 rsvd1:2; // 15:14 reserved
};
union I2CFFRX_REG {
Uint16 all;
struct I2CFFRX_BITS bit;
};
//----------------------------------------------------
struct I2C_REGS {
Uint16 I2COAR; // Own address register
union I2CIER_REG I2CIER; // Interrupt enable
union I2CSTR_REG I2CSTR; // Interrupt status
Uint16 I2CCLKL; // Clock divider low
Uint16 I2CCLKH; // Clock divider high
Uint16 I2CCNT; // Data count
Uint16 I2CDRR; // Data recieve
Uint16 I2CSAR; // Slave address
Uint16 I2CDXR; // Data transmit
union I2CMDR_REG I2CMDR; // Mode
union I2CISRC_REG I2CISRC; // Interrupt source
Uint16 rsvd1; // reserved
union I2CPSC_REG I2CPSC; // Pre-scaler
Uint16 rsvd2[19]; // reserved
union I2CFFTX_REG I2CFFTX; // Transmit FIFO
union I2CFFRX_REG I2CFFRX; // Recieve FIFO
};
//---------------------------------------------------------------------------
// External References & Function Declarations:
//
extern volatile struct I2C_REGS I2caRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_I2C_H definition
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/5 $
// Checkin $Date: May 14, 2008 16:30:31 $
//###########################################################################
//
// FILE: DSP2833x_Mcbsp.h
//
// TITLE: DSP2833x Device McBSP Register Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_MCBSP_H
#define DSP2833x_MCBSP_H
#ifdef __cplusplus
extern "C" {
#endif
//---------------------------------------------------------------------------
// McBSP Individual Register Bit Definitions:
//
// McBSP DRR2 register bit definitions:
struct DRR2_BITS { // bit description
Uint16 HWLB:8; // 16:23 High word low byte
Uint16 HWHB:8; // 24:31 High word high byte
};
union DRR2_REG {
Uint16 all;
struct DRR2_BITS bit;
};
// McBSP DRR1 register bit definitions:
struct DRR1_BITS { // bit description
Uint16 LWLB:8; // 16:23 Low word low byte
Uint16 LWHB:8; // 24:31 low word high byte
};
union DRR1_REG {
Uint16 all;
struct DRR1_BITS bit;
};
// McBSP DXR2 register bit definitions:
struct DXR2_BITS { // bit description
Uint16 HWLB:8; // 16:23 High word low byte
Uint16 HWHB:8; // 24:31 High word high byte
};
union DXR2_REG {
Uint16 all;
struct DXR2_BITS bit;
};
// McBSP DXR1 register bit definitions:
struct DXR1_BITS { // bit description
Uint16 LWLB:8; // 16:23 Low word low byte
Uint16 LWHB:8; // 24:31 low word high byte
};
union DXR1_REG {
Uint16 all;
struct DXR1_BITS bit;
};
// SPCR2 control register bit definitions:
struct SPCR2_BITS { // bit description
Uint16 XRST:1; // 0 transmit reset
Uint16 XRDY:1; // 1 transmit ready
Uint16 XEMPTY:1; // 2 Transmit empty
Uint16 XSYNCERR:1; // 3 Transmit syn errorINT flag
Uint16 XINTM:2; // 5:4 Transmit interrupt types
Uint16 GRST:1; // 6 CLKG reset
Uint16 FRST:1; // 7 Frame sync reset
Uint16 SOFT:1; // 8 SOFT bit
Uint16 FREE:1; // 9 FREE bit
Uint16 rsvd:6; // 15:10 reserved
};
union SPCR2_REG {
Uint16 all;
struct SPCR2_BITS bit;
};
// SPCR1 control register bit definitions:
struct SPCR1_BITS { // bit description
Uint16 RRST:1; // 0 Receive reset
Uint16 RRDY:1; // 1 Receive ready
Uint16 RFULL:1; // 2 Receive full
Uint16 RSYNCERR:1; // 7 Receive syn error
Uint16 RINTM:2; // 5:4 Receive interrupt types
Uint16 ABIS:1; // 6 ABIS mode select
Uint16 DXENA:1; // 7 DX hi-z enable
Uint16 rsvd:3; // 10:8 reserved
Uint16 CLKSTP:2; // 12:11 CLKSTOP mode bit
Uint16 RJUST:2; // 13:14 Right justified
Uint16 DLB:1; // 15 Digital loop back
};
union SPCR1_REG {
Uint16 all;
struct SPCR1_BITS bit;
};
// RCR2 control register bit definitions:
struct RCR2_BITS { // bit description
Uint16 RDATDLY:2; // 1:0 Receive data delay
Uint16 RFIG:1; // 2 Receive frame sync ignore
Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects
Uint16 RWDLEN2:3; // 7:5 Receive word length
Uint16 RFRLEN2:7; // 14:8 Receive Frame sync
Uint16 RPHASE:1; // 15 Receive Phase
};
union RCR2_REG {
Uint16 all;
struct RCR2_BITS bit;
};
// RCR1 control register bit definitions:
struct RCR1_BITS { // bit description
Uint16 rsvd1:5; // 4:0 reserved
Uint16 RWDLEN1:3; // 7:5 Receive word length
Uint16 RFRLEN1:7; // 14:8 Receive frame length
Uint16 rsvd2:1; // 15 reserved
};
union RCR1_REG {
Uint16 all;
struct RCR1_BITS bit;
};
// XCR2 control register bit definitions:
struct XCR2_BITS { // bit description
Uint16 XDATDLY:2; // 1:0 Transmit data delay
Uint16 XFIG:1; // 2 Transmit frame sync ignore
Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects
Uint16 XWDLEN2:3; // 7:5 Transmit word length
Uint16 XFRLEN2:7; // 14:8 Transmit Frame sync
Uint16 XPHASE:1; // 15 Transmit Phase
};
union XCR2_REG {
Uint16 all;
struct XCR2_BITS bit;
};
// XCR1 control register bit definitions:
struct XCR1_BITS { // bit description
Uint16 rsvd1:5; // 4:0 reserved
Uint16 XWDLEN1:3; // 7:5 Transmit word length
Uint16 XFRLEN1:7; // 14:8 Transmit frame length
Uint16 rsvd2:1; // 15 reserved
};
union XCR1_REG {
Uint16 all;
struct XCR1_BITS bit;
};
// SRGR2 Sample rate generator control register bit definitions:
struct SRGR2_BITS { // bit description
Uint16 FPER:12; // 11:0 Frame period
Uint16 FSGM:1; // 12 Frame sync generator mode
Uint16 CLKSM:1; // 13 Sample rate generator mode
Uint16 rsvd:1; // 14 reserved
Uint16 GSYNC:1; // 15 CLKG sync
};
union SRGR2_REG {
Uint16 all;
struct SRGR2_BITS bit;
};
// SRGR1 control register bit definitions:
struct SRGR1_BITS { // bit description
Uint16 CLKGDV:8; // 7:0 CLKG divider
Uint16 FWID:8; // 15:8 Frame width
};
union SRGR1_REG {
Uint16 all;
struct SRGR1_BITS bit;
};
// MCR2 Multichannel control register bit definitions:
struct MCR2_BITS { // bit description
Uint16 XMCM:2; // 1:0 Transmit multichannel mode
Uint16 XCBLK:3; // 2:4 Transmit current block
Uint16 XPABLK:2; // 5:6 Transmit partition A Block
Uint16 XPBBLK:2; // 7:8 Transmit partition B Block
Uint16 XMCME:1; // 9 Transmit multi-channel enhance mode
Uint16 rsvd:6; // 15:10 reserved
};
union MCR2_REG {
Uint16 all;
struct MCR2_BITS bit;
};
// MCR1 Multichannel control register bit definitions:
struct MCR1_BITS { // bit description
Uint16 RMCM:1; // 0 Receive multichannel mode
Uint16 rsvd:1; // 1 reserved
Uint16 RCBLK:3; // 4:2 Receive current block
Uint16 RPABLK:2; // 6:5 Receive partition A Block
Uint16 RPBBLK:2; // 7:8 Receive partition B Block
Uint16 RMCME:1; // 9 Receive multi-channel enhance mode
Uint16 rsvd1:6; // 15:10 reserved
};
union MCR1_REG {
Uint16 all;
struct MCR1_BITS bit;
};
// RCERA control register bit definitions:
struct RCERA_BITS { // bit description
Uint16 RCEA0:1; // 0 Receive Channel enable bit
Uint16 RCEA1:1; // 1 Receive Channel enable bit
Uint16 RCEA2:1; // 2 Receive Channel enable bit
Uint16 RCEA3:1; // 3 Receive Channel enable bit
Uint16 RCEA4:1; // 4 Receive Channel enable bit
Uint16 RCEA5:1; // 5 Receive Channel enable bit
Uint16 RCEA6:1; // 6 Receive Channel enable bit
Uint16 RCEA7:1; // 7 Receive Channel enable bit
Uint16 RCEA8:1; // 8 Receive Channel enable bit
Uint16 RCEA9:1; // 9 Receive Channel enable bit
Uint16 RCEA10:1; // 10 Receive Channel enable bit
Uint16 RCEA11:1; // 11 Receive Channel enable bit
Uint16 RCEA12:1; // 12 Receive Channel enable bit
Uint16 RCEA13:1; // 13 Receive Channel enable bit
Uint16 RCEA14:1; // 14 Receive Channel enable bit
Uint16 RCEA15:1; // 15 Receive Channel enable bit
};
union RCERA_REG {
Uint16 all;
struct RCERA_BITS bit;
};
// RCERB control register bit definitions:
struct RCERB_BITS { // bit description
Uint16 RCEB0:1; // 0 Receive Channel enable bit
Uint16 RCEB1:1; // 1 Receive Channel enable bit
Uint16 RCEB2:1; // 2 Receive Channel enable bit
Uint16 RCEB3:1; // 3 Receive Channel enable bit
Uint16 RCEB4:1; // 4 Receive Channel enable bit
Uint16 RCEB5:1; // 5 Receive Channel enable bit
Uint16 RCEB6:1; // 6 Receive Channel enable bit
Uint16 RCEB7:1; // 7 Receive Channel enable bit
Uint16 RCEB8:1; // 8 Receive Channel enable bit
Uint16 RCEB9:1; // 9 Receive Channel enable bit
Uint16 RCEB10:1; // 10 Receive Channel enable bit
Uint16 RCEB11:1; // 11 Receive Channel enable bit
Uint16 RCEB12:1; // 12 Receive Channel enable bit
Uint16 RCEB13:1; // 13 Receive Channel enable bit
Uint16 RCEB14:1; // 14 Receive Channel enable bit
Uint16 RCEB15:1; // 15 Receive Channel enable bit
};
union RCERB_REG {
Uint16 all;
struct RCERB_BITS bit;
};
// XCERA control register bit definitions:
struct XCERA_BITS { // bit description
Uint16 XCERA0:1; // 0 Receive Channel enable bit
Uint16 XCERA1:1; // 1 Receive Channel enable bit
Uint16 XCERA2:1; // 2 Receive Channel enable bit
Uint16 XCERA3:1; // 3 Receive Channel enable bit
Uint16 XCERA4:1; // 4 Receive Channel enable bit
Uint16 XCERA5:1; // 5 Receive Channel enable bit
Uint16 XCERA6:1; // 6 Receive Channel enable bit
Uint16 XCERA7:1; // 7 Receive Channel enable bit
Uint16 XCERA8:1; // 8 Receive Channel enable bit
Uint16 XCERA9:1; // 9 Receive Channel enable bit
Uint16 XCERA10:1; // 10 Receive Channel enable bit
Uint16 XCERA11:1; // 11 Receive Channel enable bit
Uint16 XCERA12:1; // 12 Receive Channel enable bit
Uint16 XCERA13:1; // 13 Receive Channel enable bit
Uint16 XCERA14:1; // 14 Receive Channel enable bit
Uint16 XCERA15:1; // 15 Receive Channel enable bit
};
union XCERA_REG {
Uint16 all;
struct XCERA_BITS bit;
};
// XCERB control register bit definitions:
struct XCERB_BITS { // bit description
Uint16 XCERB0:1; // 0 Receive Channel enable bit
Uint16 XCERB1:1; // 1 Receive Channel enable bit
Uint16 XCERB2:1; // 2 Receive Channel enable bit
Uint16 XCERB3:1; // 3 Receive Channel enable bit
Uint16 XCERB4:1; // 4 Receive Channel enable bit
Uint16 XCERB5:1; // 5 Receive Channel enable bit
Uint16 XCERB6:1; // 6 Receive Channel enable bit
Uint16 XCERB7:1; // 7 Receive Channel enable bit
Uint16 XCERB8:1; // 8 Receive Channel enable bit
Uint16 XCERB9:1; // 9 Receive Channel enable bit
Uint16 XCERB10:1; // 10 Receive Channel enable bit
Uint16 XCERB11:1; // 11 Receive Channel enable bit
Uint16 XCERB12:1; // 12 Receive Channel enable bit
Uint16 XCERB13:1; // 13 Receive Channel enable bit
Uint16 XCERB14:1; // 14 Receive Channel enable bit
Uint16 XCERB15:1; // 15 Receive Channel enable bit
};
union XCERB_REG {
Uint16 all;
struct XCERB_BITS bit;
};
// PCR control register bit definitions:
struct PCR_BITS { // bit description
Uint16 CLKRP:1; // 0 Receive Clock polarity
Uint16 CLKXP:1; // 1 Transmit clock polarity
Uint16 FSRP:1; // 2 Receive Frame synchronization polarity
Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity
Uint16 DR_STAT:1; // 4 DR pin status - reserved for this McBSP
Uint16 DX_STAT:1; // 5 DX pin status - reserved for this McBSP
Uint16 CLKS_STAT:1; // 6 CLKS pin status - reserved for 28x -McBSP
Uint16 SCLKME:1; // 7 Enhanced sample clock mode selection bit.
Uint16 CLKRM:1; // 8 Receiver Clock Mode
Uint16 CLKXM:1; // 9 Transmitter Clock Mode.
Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode
Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode
Uint16 RIOEN:1; // 12 General Purpose I/O Mode - reserved in this 28x-McBSP
Uint16 XIOEN:1; // 13 General Purpose I/O Mode - reserved in this 28x-McBSP
Uint16 IDEL_EN:1; // 14 reserved in this 28x-McBSP
Uint16 rsvd:1 ; // 15 reserved
};
union PCR_REG {
Uint16 all;
struct PCR_BITS bit;
};
// RCERC control register bit definitions:
struct RCERC_BITS { // bit description
Uint16 RCEC0:1; // 0 Receive Channel enable bit
Uint16 RCEC1:1; // 1 Receive Channel enable bit
Uint16 RCEC2:1; // 2 Receive Channel enable bit
Uint16 RCEC3:1; // 3 Receive Channel enable bit
Uint16 RCEC4:1; // 4 Receive Channel enable bit
Uint16 RCEC5:1; // 5 Receive Channel enable bit
Uint16 RCEC6:1; // 6 Receive Channel enable bit
Uint16 RCEC7:1; // 7 Receive Channel enable bit
Uint16 RCEC8:1; // 8 Receive Channel enable bit
Uint16 RCEC9:1; // 9 Receive Channel enable bit
Uint16 RCEC10:1; // 10 Receive Channel enable bit
Uint16 RCEC11:1; // 11 Receive Channel enable bit
Uint16 RCEC12:1; // 12 Receive Channel enable bit
Uint16 RCEC13:1; // 13 Receive Channel enable bit
Uint16 RCEC14:1; // 14 Receive Channel enable bit
Uint16 RCEC15:1; // 15 Receive Channel enable bit
};
union RCERC_REG {
Uint16 all;
struct RCERC_BITS bit;
};
// RCERD control register bit definitions:
struct RCERD_BITS { // bit description
Uint16 RCED0:1; // 0 Receive Channel enable bit
Uint16 RCED1:1; // 1 Receive Channel enable bit
Uint16 RCED2:1; // 2 Receive Channel enable bit
Uint16 RCED3:1; // 3 Receive Channel enable bit
Uint16 RCED4:1; // 4 Receive Channel enable bit
Uint16 RCED5:1; // 5 Receive Channel enable bit
Uint16 RCED6:1; // 6 Receive Channel enable bit
Uint16 RCED7:1; // 7 Receive Channel enable bit
Uint16 RCED8:1; // 8 Receive Channel enable bit
Uint16 RCED9:1; // 9 Receive Channel enable bit
Uint16 RCED10:1; // 10 Receive Channel enable bit
Uint16 RCED11:1; // 11 Receive Channel enable bit
Uint16 RCED12:1; // 12 Receive Channel enable bit
Uint16 RCED13:1; // 13 Receive Channel enable bit
Uint16 RCED14:1; // 14 Receive Channel enable bit
Uint16 RCED15:1; // 15 Receive Channel enable bit
};
union RCERD_REG {
Uint16 all;
struct RCERD_BITS bit;
};
// XCERC control register bit definitions:
struct XCERC_BITS { // bit description
Uint16 XCERC0:1; // 0 Receive Channel enable bit
Uint16 XCERC1:1; // 1 Receive Channel enable bit
Uint16 XCERC2:1; // 2 Receive Channel enable bit
Uint16 XCERC3:1; // 3 Receive Channel enable bit
Uint16 XCERC4:1; // 4 Receive Channel enable bit
Uint16 XCERC5:1; // 5 Receive Channel enable bit
Uint16 XCERC6:1; // 6 Receive Channel enable bit
Uint16 XCERC7:1; // 7 Receive Channel enable bit
Uint16 XCERC8:1; // 8 Receive Channel enable bit
Uint16 XCERC9:1; // 9 Receive Channel enable bit
Uint16 XCERC10:1; // 10 Receive Channel enable bit
Uint16 XCERC11:1; // 11 Receive Channel enable bit
Uint16 XCERC12:1; // 12 Receive Channel enable bit
Uint16 XCERC13:1; // 13 Receive Channel enable bit
Uint16 XCERC14:1; // 14 Receive Channel enable bit
Uint16 XCERC15:1; // 15 Receive Channel enable bit
};
union XCERC_REG {
Uint16 all;
struct XCERC_BITS bit;
};
// XCERD control register bit definitions:
struct XCERD_BITS { // bit description
Uint16 XCERD0:1; // 0 Receive Channel enable bit
Uint16 XCERD1:1; // 1 Receive Channel enable bit
Uint16 XCERD2:1; // 2 Receive Channel enable bit
Uint16 XCERD3:1; // 3 Receive Channel enable bit
Uint16 XCERD4:1; // 4 Receive Channel enable bit
Uint16 XCERD5:1; // 5 Receive Channel enable bit
Uint16 XCERD6:1; // 6 Receive Channel enable bit
Uint16 XCERD7:1; // 7 Receive Channel enable bit
Uint16 XCERD8:1; // 8 Receive Channel enable bit
Uint16 XCERD9:1; // 9 Receive Channel enable bit
Uint16 XCERD10:1; // 10 Receive Channel enable bit
Uint16 XCERD11:1; // 11 Receive Channel enable bit
Uint16 XCERD12:1; // 12 Receive Channel enable bit
Uint16 XCERD13:1; // 13 Receive Channel enable bit
Uint16 XCERD14:1; // 14 Receive Channel enable bit
Uint16 XCERD15:1; // 15 Receive Channel enable bit
};
union XCERD_REG {
Uint16 all;
struct XCERD_BITS bit;
};
// RCERE control register bit definitions:
struct RCERE_BITS { // bit description
Uint16 RCEE0:1; // 0 Receive Channel enable bit
Uint16 RCEE1:1; // 1 Receive Channel enable bit
Uint16 RCEE2:1; // 2 Receive Channel enable bit
Uint16 RCEE3:1; // 3 Receive Channel enable bit
Uint16 RCEE4:1; // 4 Receive Channel enable bit
Uint16 RCEE5:1; // 5 Receive Channel enable bit
Uint16 RCEE6:1; // 6 Receive Channel enable bit
Uint16 RCEE7:1; // 7 Receive Channel enable bit
Uint16 RCEE8:1; // 8 Receive Channel enable bit
Uint16 RCEE9:1; // 9 Receive Channel enable bit
Uint16 RCEE10:1; // 10 Receive Channel enable bit
Uint16 RCEE11:1; // 11 Receive Channel enable bit
Uint16 RCEE12:1; // 12 Receive Channel enable bit
Uint16 RCEE13:1; // 13 Receive Channel enable bit
Uint16 RCEE14:1; // 14 Receive Channel enable bit
Uint16 RCEE15:1; // 15 Receive Channel enable bit
};
union RCERE_REG {
Uint16 all;
struct RCERE_BITS bit;
};
// RCERF control register bit definitions:
struct RCERF_BITS { // bit description
Uint16 RCEF0:1; // 0 Receive Channel enable bit
Uint16 RCEF1:1; // 1 Receive Channel enable bit
Uint16 RCEF2:1; // 2 Receive Channel enable bit
Uint16 RCEF3:1; // 3 Receive Channel enable bit
Uint16 RCEF4:1; // 4 Receive Channel enable bit
Uint16 RCEF5:1; // 5 Receive Channel enable bit
Uint16 RCEF6:1; // 6 Receive Channel enable bit
Uint16 RCEF7:1; // 7 Receive Channel enable bit
Uint16 RCEF8:1; // 8 Receive Channel enable bit
Uint16 RCEF9:1; // 9 Receive Channel enable bit
Uint16 RCEF10:1; // 10 Receive Channel enable bit
Uint16 RCEF11:1; // 11 Receive Channel enable bit
Uint16 RCEF12:1; // 12 Receive Channel enable bit
Uint16 RCEF13:1; // 13 Receive Channel enable bit
Uint16 RCEF14:1; // 14 Receive Channel enable bit
Uint16 RCEF15:1; // 15 Receive Channel enable bit
};
union RCERF_REG {
Uint16 all;
struct RCERF_BITS bit;
};
// XCERE control register bit definitions:
struct XCERE_BITS { // bit description
Uint16 XCERE0:1; // 0 Receive Channel enable bit
Uint16 XCERE1:1; // 1 Receive Channel enable bit
Uint16 XCERE2:1; // 2 Receive Channel enable bit
Uint16 XCERE3:1; // 3 Receive Channel enable bit
Uint16 XCERE4:1; // 4 Receive Channel enable bit
Uint16 XCERE5:1; // 5 Receive Channel enable bit
Uint16 XCERE6:1; // 6 Receive Channel enable bit
Uint16 XCERE7:1; // 7 Receive Channel enable bit
Uint16 XCERE8:1; // 8 Receive Channel enable bit
Uint16 XCERE9:1; // 9 Receive Channel enable bit
Uint16 XCERE10:1; // 10 Receive Channel enable bit
Uint16 XCERE11:1; // 11 Receive Channel enable bit
Uint16 XCERE12:1; // 12 Receive Channel enable bit
Uint16 XCERE13:1; // 13 Receive Channel enable bit
Uint16 XCERE14:1; // 14 Receive Channel enable bit
Uint16 XCERE15:1; // 15 Receive Channel enable bit
};
union XCERE_REG {
Uint16 all;
struct XCERE_BITS bit;
};
// XCERF control register bit definitions:
struct XCERF_BITS { // bit description
Uint16 XCERF0:1; // 0 Receive Channel enable bit
Uint16 XCERF1:1; // 1 Receive Channel enable bit
Uint16 XCERF2:1; // 2 Receive Channel enable bit
Uint16 XCERF3:1; // 3 Receive Channel enable bit
Uint16 XCERF4:1; // 4 Receive Channel enable bit
Uint16 XCERF5:1; // 5 Receive Channel enable bit
Uint16 XCERF6:1; // 6 Receive Channel enable bit
Uint16 XCERF7:1; // 7 Receive Channel enable bit
Uint16 XCERF8:1; // 8 Receive Channel enable bit
Uint16 XCERF9:1; // 9 Receive Channel enable bit
Uint16 XCERF10:1; // 10 Receive Channel enable bit
Uint16 XCERF11:1; // 11 Receive Channel enable bit
Uint16 XCERF12:1; // 12 Receive Channel enable bit
Uint16 XCERF13:1; // 13 Receive Channel enable bit
Uint16 XCERF14:1; // 14 Receive Channel enable bit
Uint16 XCERF15:1; // 15 Receive Channel enable bit
};
union XCERF_REG {
Uint16 all;
struct XCERF_BITS bit;
};
// RCERG control register bit definitions:
struct RCERG_BITS { // bit description
Uint16 RCEG0:1; // 0 Receive Channel enable bit
Uint16 RCEG1:1; // 1 Receive Channel enable bit
Uint16 RCEG2:1; // 2 Receive Channel enable bit
Uint16 RCEG3:1; // 3 Receive Channel enable bit
Uint16 RCEG4:1; // 4 Receive Channel enable bit
Uint16 RCEG5:1; // 5 Receive Channel enable bit
Uint16 RCEG6:1; // 6 Receive Channel enable bit
Uint16 RCEG7:1; // 7 Receive Channel enable bit
Uint16 RCEG8:1; // 8 Receive Channel enable bit
Uint16 RCEG9:1; // 9 Receive Channel enable bit
Uint16 RCEG10:1; // 10 Receive Channel enable bit
Uint16 RCEG11:1; // 11 Receive Channel enable bit
Uint16 RCEG12:1; // 12 Receive Channel enable bit
Uint16 RCEG13:1; // 13 Receive Channel enable bit
Uint16 RCEG14:1; // 14 Receive Channel enable bit
Uint16 RCEG15:1; // 15 Receive Channel enable bit
};
union RCERG_REG {
Uint16 all;
struct RCERG_BITS bit;
};
// RCERH control register bit definitions:
struct RCERH_BITS { // bit description
Uint16 RCEH0:1; // 0 Receive Channel enable bit
Uint16 RCEH1:1; // 1 Receive Channel enable bit
Uint16 RCEH2:1; // 2 Receive Channel enable bit
Uint16 RCEH3:1; // 3 Receive Channel enable bit
Uint16 RCEH4:1; // 4 Receive Channel enable bit
Uint16 RCEH5:1; // 5 Receive Channel enable bit
Uint16 RCEH6:1; // 6 Receive Channel enable bit
Uint16 RCEH7:1; // 7 Receive Channel enable bit
Uint16 RCEH8:1; // 8 Receive Channel enable bit
Uint16 RCEH9:1; // 9 Receive Channel enable bit
Uint16 RCEH10:1; // 10 Receive Channel enable bit
Uint16 RCEH11:1; // 11 Receive Channel enable bit
Uint16 RCEH12:1; // 12 Receive Channel enable bit
Uint16 RCEH13:1; // 13 Receive Channel enable bit
Uint16 RCEH14:1; // 14 Receive Channel enable bit
Uint16 RCEH15:1; // 15 Receive Channel enable bit
};
union RCERH_REG {
Uint16 all;
struct RCERH_BITS bit;
};
// XCERG control register bit definitions:
struct XCERG_BITS { // bit description
Uint16 XCERG0:1; // 0 Receive Channel enable bit
Uint16 XCERG1:1; // 1 Receive Channel enable bit
Uint16 XCERG2:1; // 2 Receive Channel enable bit
Uint16 XCERG3:1; // 3 Receive Channel enable bit
Uint16 XCERG4:1; // 4 Receive Channel enable bit
Uint16 XCERG5:1; // 5 Receive Channel enable bit
Uint16 XCERG6:1; // 6 Receive Channel enable bit
Uint16 XCERG7:1; // 7 Receive Channel enable bit
Uint16 XCERG8:1; // 8 Receive Channel enable bit
Uint16 XCERG9:1; // 9 Receive Channel enable bit
Uint16 XCERG10:1; // 10 Receive Channel enable bit
Uint16 XCERG11:1; // 11 Receive Channel enable bit
Uint16 XCERG12:1; // 12 Receive Channel enable bit
Uint16 XCERG13:1; // 13 Receive Channel enable bit
Uint16 XCERG14:1; // 14 Receive Channel enable bit
Uint16 XCERG15:1; // 15 Receive Channel enable bit
};
union XCERG_REG {
Uint16 all;
struct XCERG_BITS bit;
};
// XCERH control register bit definitions:
struct XCERH_BITS { // bit description
Uint16 XCEH0:1; // 0 Receive Channel enable bit
Uint16 XCEH1:1; // 1 Receive Channel enable bit
Uint16 XCEH2:1; // 2 Receive Channel enable bit
Uint16 XCEH3:1; // 3 Receive Channel enable bit
Uint16 XCEH4:1; // 4 Receive Channel enable bit
Uint16 XCEH5:1; // 5 Receive Channel enable bit
Uint16 XCEH6:1; // 6 Receive Channel enable bit
Uint16 XCEH7:1; // 7 Receive Channel enable bit
Uint16 XCEH8:1; // 8 Receive Channel enable bit
Uint16 XCEH9:1; // 9 Receive Channel enable bit
Uint16 XCEH10:1; // 10 Receive Channel enable bit
Uint16 XCEH11:1; // 11 Receive Channel enable bit
Uint16 XCEH12:1; // 12 Receive Channel enable bit
Uint16 XCEH13:1; // 13 Receive Channel enable bit
Uint16 XCEH14:1; // 14 Receive Channel enable bit
Uint16 XCEH15:1; // 15 Receive Channel enable bit
};
union XCERH_REG {
Uint16 all;
struct XCERH_BITS bit;
};
// McBSP Interrupt enable register for RINT/XINT
struct MFFINT_BITS { // bits description
Uint16 XINT:1; // 0 XINT interrupt enable
Uint16 rsvd1:1; // 1 reserved
Uint16 RINT:1; // 2 RINT interrupt enable
Uint16 rsvd2:13; // 15:3 reserved
};
union MFFINT_REG {
Uint16 all;
struct MFFINT_BITS bit;
};
//---------------------------------------------------------------------------
// McBSP Register File:
//
struct MCBSP_REGS {
union DRR2_REG DRR2; // MCBSP Data receive register bits 31-16
union DRR1_REG DRR1; // MCBSP Data receive register bits 15-0
union DXR2_REG DXR2; // MCBSP Data transmit register bits 31-16
union DXR1_REG DXR1; // MCBSP Data transmit register bits 15-0
union SPCR2_REG SPCR2; // MCBSP control register bits 31-16
union SPCR1_REG SPCR1; // MCBSP control register bits 15-0
union RCR2_REG RCR2; // MCBSP receive control register bits 31-16
union RCR1_REG RCR1; // MCBSP receive control register bits 15-0
union XCR2_REG XCR2; // MCBSP transmit control register bits 31-16
union XCR1_REG XCR1; // MCBSP transmit control register bits 15-0
union SRGR2_REG SRGR2; // MCBSP sample rate gen register bits 31-16
union SRGR1_REG SRGR1; // MCBSP sample rate gen register bits 15-0
union MCR2_REG MCR2; // MCBSP multichannel register bits 31-16
union MCR1_REG MCR1; // MCBSP multichannel register bits 15-0
union RCERA_REG RCERA; // MCBSP Receive channel enable partition A
union RCERB_REG RCERB; // MCBSP Receive channel enable partition B
union XCERA_REG XCERA; // MCBSP Transmit channel enable partition A
union XCERB_REG XCERB; // MCBSP Transmit channel enable partition B
union PCR_REG PCR; // MCBSP Pin control register bits 15-0
union RCERC_REG RCERC; // MCBSP Receive channel enable partition C
union RCERD_REG RCERD; // MCBSP Receive channel enable partition D
union XCERC_REG XCERC; // MCBSP Transmit channel enable partition C
union XCERD_REG XCERD; // MCBSP Transmit channel enable partition D
union RCERE_REG RCERE; // MCBSP Receive channel enable partition E
union RCERF_REG RCERF; // MCBSP Receive channel enable partition F
union XCERE_REG XCERE; // MCBSP Transmit channel enable partition E
union XCERF_REG XCERF; // MCBSP Transmit channel enable partition F
union RCERG_REG RCERG; // MCBSP Receive channel enable partition G
union RCERH_REG RCERH; // MCBSP Receive channel enable partition H
union XCERG_REG XCERG; // MCBSP Transmit channel enable partition G
union XCERH_REG XCERH; // MCBSP Transmit channel enable partition H
Uint16 rsvd1[4]; // reserved
union MFFINT_REG MFFINT; // MCBSP Interrupt enable register for RINT/XINT
Uint16 rsvd2; // reserved
};
//---------------------------------------------------------------------------
// McBSP External References & Function Declarations:
//
extern volatile struct MCBSP_REGS McbspaRegs;
extern volatile struct MCBSP_REGS McbspbRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_MCBSP_H definition
//===========================================================================
// No more.
//===========================================================================

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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:52:24 $
//###########################################################################
//
// FILE: DSP2833x_PieCtrl.h
//
// TITLE: DSP2833x Device PIE Control Register Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_PIE_CTRL_H
#define DSP2833x_PIE_CTRL_H
#ifdef __cplusplus
extern "C" {
#endif
//---------------------------------------------------------------------------
// PIE Control Register Bit Definitions:
//
// PIECTRL: Register bit definitions:
struct PIECTRL_BITS { // bits description
Uint16 ENPIE:1; // 0 Enable PIE block
Uint16 PIEVECT:15; // 15:1 Fetched vector address
};
union PIECTRL_REG {
Uint16 all;
struct PIECTRL_BITS bit;
};
// PIEIER: Register bit definitions:
struct PIEIER_BITS { // bits description
Uint16 INTx1:1; // 0 INTx.1
Uint16 INTx2:1; // 1 INTx.2
Uint16 INTx3:1; // 2 INTx.3
Uint16 INTx4:1; // 3 INTx.4
Uint16 INTx5:1; // 4 INTx.5
Uint16 INTx6:1; // 5 INTx.6
Uint16 INTx7:1; // 6 INTx.7
Uint16 INTx8:1; // 7 INTx.8
Uint16 rsvd:8; // 15:8 reserved
};
union PIEIER_REG {
Uint16 all;
struct PIEIER_BITS bit;
};
// PIEIFR: Register bit definitions:
struct PIEIFR_BITS { // bits description
Uint16 INTx1:1; // 0 INTx.1
Uint16 INTx2:1; // 1 INTx.2
Uint16 INTx3:1; // 2 INTx.3
Uint16 INTx4:1; // 3 INTx.4
Uint16 INTx5:1; // 4 INTx.5
Uint16 INTx6:1; // 5 INTx.6
Uint16 INTx7:1; // 6 INTx.7
Uint16 INTx8:1; // 7 INTx.8
Uint16 rsvd:8; // 15:8 reserved
};
union PIEIFR_REG {
Uint16 all;
struct PIEIFR_BITS bit;
};
// PIEACK: Register bit definitions:
struct PIEACK_BITS { // bits description
Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1
Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2
Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3
Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4
Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5
Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6
Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7
Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8
Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9
Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10
Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11
Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12
Uint16 rsvd:4; // 15:12 reserved
};
union PIEACK_REG {
Uint16 all;
struct PIEACK_BITS bit;
};
//---------------------------------------------------------------------------
// PIE Control Register File:
//
struct PIE_CTRL_REGS {
union PIECTRL_REG PIECTRL; // PIE control register
union PIEACK_REG PIEACK; // PIE acknowledge
union PIEIER_REG PIEIER1; // PIE int1 IER register
union PIEIFR_REG PIEIFR1; // PIE int1 IFR register
union PIEIER_REG PIEIER2; // PIE INT2 IER register
union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register
union PIEIER_REG PIEIER3; // PIE INT3 IER register
union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register
union PIEIER_REG PIEIER4; // PIE INT4 IER register
union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register
union PIEIER_REG PIEIER5; // PIE INT5 IER register
union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register
union PIEIER_REG PIEIER6; // PIE INT6 IER register
union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register
union PIEIER_REG PIEIER7; // PIE INT7 IER register
union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register
union PIEIER_REG PIEIER8; // PIE INT8 IER register
union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register
union PIEIER_REG PIEIER9; // PIE INT9 IER register
union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register
union PIEIER_REG PIEIER10; // PIE int10 IER register
union PIEIFR_REG PIEIFR10; // PIE int10 IFR register
union PIEIER_REG PIEIER11; // PIE int11 IER register
union PIEIFR_REG PIEIFR11; // PIE int11 IFR register
union PIEIER_REG PIEIER12; // PIE int12 IER register
union PIEIFR_REG PIEIFR12; // PIE int12 IFR register
};
#define PIEACK_GROUP1 0x0001
#define PIEACK_GROUP2 0x0002
#define PIEACK_GROUP3 0x0004
#define PIEACK_GROUP4 0x0008
#define PIEACK_GROUP5 0x0010
#define PIEACK_GROUP6 0x0020
#define PIEACK_GROUP7 0x0040
#define PIEACK_GROUP8 0x0080
#define PIEACK_GROUP9 0x0100
#define PIEACK_GROUP10 0x0200
#define PIEACK_GROUP11 0x0400
#define PIEACK_GROUP12 0x0800
//---------------------------------------------------------------------------
// PIE Control Registers External References & Function Declarations:
//
extern volatile struct PIE_CTRL_REGS PieCtrlRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_PIE_CTRL_H definition
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/2 $
// Checkin $Date: March 16, 2007 09:00:21 $
//###########################################################################
//
// FILE: DSP2833x_PieVect.h
//
// TITLE: DSP2833x Devices PIE Vector Table Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_PIE_VECT_H
#define DSP2833x_PIE_VECT_H
#ifdef __cplusplus
extern "C" {
#endif
//---------------------------------------------------------------------------
// PIE Interrupt Vector Table Definition:
//
// Create a user type called PINT (pointer to interrupt):
typedef interrupt void(*PINT)(void);
// Define Vector Table:
struct PIE_VECT_TABLE {
// Reset is never fetched from this table.
// It will always be fetched from 0x3FFFC0 in
// boot ROM
PINT PIE1_RESERVED;
PINT PIE2_RESERVED;
PINT PIE3_RESERVED;
PINT PIE4_RESERVED;
PINT PIE5_RESERVED;
PINT PIE6_RESERVED;
PINT PIE7_RESERVED;
PINT PIE8_RESERVED;
PINT PIE9_RESERVED;
PINT PIE10_RESERVED;
PINT PIE11_RESERVED;
PINT PIE12_RESERVED;
PINT PIE13_RESERVED;
// Non-Peripheral Interrupts:
PINT XINT13; // XINT13 / CPU-Timer1
PINT TINT2; // CPU-Timer2
PINT DATALOG; // Datalogging interrupt
PINT RTOSINT; // RTOS interrupt
PINT EMUINT; // Emulation interrupt
PINT XNMI; // Non-maskable interrupt
PINT ILLEGAL; // Illegal operation TRAP
PINT USER1; // User Defined trap 1
PINT USER2; // User Defined trap 2
PINT USER3; // User Defined trap 3
PINT USER4; // User Defined trap 4
PINT USER5; // User Defined trap 5
PINT USER6; // User Defined trap 6
PINT USER7; // User Defined trap 7
PINT USER8; // User Defined trap 8
PINT USER9; // User Defined trap 9
PINT USER10; // User Defined trap 10
PINT USER11; // User Defined trap 11
PINT USER12; // User Defined trap 12
// Group 1 PIE Peripheral Vectors:
PINT SEQ1INT;
PINT SEQ2INT;
PINT rsvd1_3;
PINT XINT1;
PINT XINT2;
PINT ADCINT; // ADC
PINT TINT0; // Timer 0
PINT WAKEINT; // WD
// Group 2 PIE Peripheral Vectors:
PINT EPWM1_TZINT; // EPWM-1
PINT EPWM2_TZINT; // EPWM-2
PINT EPWM3_TZINT; // EPWM-3
PINT EPWM4_TZINT; // EPWM-4
PINT EPWM5_TZINT; // EPWM-5
PINT EPWM6_TZINT; // EPWM-6
PINT rsvd2_7;
PINT rsvd2_8;
// Group 3 PIE Peripheral Vectors:
PINT EPWM1_INT; // EPWM-1
PINT EPWM2_INT; // EPWM-2
PINT EPWM3_INT; // EPWM-3
PINT EPWM4_INT; // EPWM-4
PINT EPWM5_INT; // EPWM-5
PINT EPWM6_INT; // EPWM-6
PINT rsvd3_7;
PINT rsvd3_8;
// Group 4 PIE Peripheral Vectors:
PINT ECAP1_INT; // ECAP-1
PINT ECAP2_INT; // ECAP-2
PINT ECAP3_INT; // ECAP-3
PINT ECAP4_INT; // ECAP-4
PINT ECAP5_INT; // ECAP-5
PINT ECAP6_INT; // ECAP-6
PINT rsvd4_7;
PINT rsvd4_8;
// Group 5 PIE Peripheral Vectors:
PINT EQEP1_INT; // EQEP-1
PINT EQEP2_INT; // EQEP-2
PINT rsvd5_3;
PINT rsvd5_4;
PINT rsvd5_5;
PINT rsvd5_6;
PINT rsvd5_7;
PINT rsvd5_8;
// Group 6 PIE Peripheral Vectors:
PINT SPIRXINTA; // SPI-A
PINT SPITXINTA; // SPI-A
PINT MRINTB; // McBSP-B
PINT MXINTB; // McBSP-B
PINT MRINTA; // McBSP-A
PINT MXINTA; // McBSP-A
PINT rsvd6_7;
PINT rsvd6_8;
// Group 7 PIE Peripheral Vectors:
PINT DINTCH1; // DMA
PINT DINTCH2; // DMA
PINT DINTCH3; // DMA
PINT DINTCH4; // DMA
PINT DINTCH5; // DMA
PINT DINTCH6; // DMA
PINT rsvd7_7;
PINT rsvd7_8;
// Group 8 PIE Peripheral Vectors:
PINT I2CINT1A; // I2C-A
PINT I2CINT2A; // I2C-A
PINT rsvd8_3;
PINT rsvd8_4;
PINT SCIRXINTC; // SCI-C
PINT SCITXINTC; // SCI-C
PINT rsvd8_7;
PINT rsvd8_8;
// Group 9 PIE Peripheral Vectors:
PINT SCIRXINTA; // SCI-A
PINT SCITXINTA; // SCI-A
PINT SCIRXINTB; // SCI-B
PINT SCITXINTB; // SCI-B
PINT ECAN0INTA; // eCAN-A
PINT ECAN1INTA; // eCAN-A
PINT ECAN0INTB; // eCAN-B
PINT ECAN1INTB; // eCAN-B
// Group 10 PIE Peripheral Vectors:
PINT rsvd10_1;
PINT rsvd10_2;
PINT rsvd10_3;
PINT rsvd10_4;
PINT rsvd10_5;
PINT rsvd10_6;
PINT rsvd10_7;
PINT rsvd10_8;
// Group 11 PIE Peripheral Vectors:
PINT rsvd11_1;
PINT rsvd11_2;
PINT rsvd11_3;
PINT rsvd11_4;
PINT rsvd11_5;
PINT rsvd11_6;
PINT rsvd11_7;
PINT rsvd11_8;
// Group 12 PIE Peripheral Vectors:
PINT XINT3; // External interrupt
PINT XINT4;
PINT XINT5;
PINT XINT6;
PINT XINT7;
PINT rsvd12_6;
PINT LVF; // Latched overflow
PINT LUF; // Latched underflow
};
//---------------------------------------------------------------------------
// PIE Interrupt Vector Table External References & Function Declarations:
//
extern struct PIE_VECT_TABLE PieVectTable;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_PIE_VECT_H definition
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/2 $
// Checkin $Date: March 1, 2007 15:57:02 $
//###########################################################################
//
// FILE: DSP2833x_Sci.h
//
// TITLE: DSP2833x Device SCI Register Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_SCI_H
#define DSP2833x_SCI_H
#ifdef __cplusplus
extern "C" {
#endif
//---------------------------------------------------------------------------
// SCI Individual Register Bit Definitions
//----------------------------------------------------------
// SCICCR communication control register bit definitions:
//
struct SCICCR_BITS { // bit description
Uint16 SCICHAR:3; // 2:0 Character length control
Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control
Uint16 LOOPBKENA:1; // 4 Loop Back enable
Uint16 PARITYENA:1; // 5 Parity enable
Uint16 PARITY:1; // 6 Even or Odd Parity
Uint16 STOPBITS:1; // 7 Number of Stop Bits
Uint16 rsvd1:8; // 15:8 reserved
};
union SCICCR_REG {
Uint16 all;
struct SCICCR_BITS bit;
};
//-------------------------------------------
// SCICTL1 control register 1 bit definitions:
//
struct SCICTL1_BITS { // bit description
Uint16 RXENA:1; // 0 SCI receiver enable
Uint16 TXENA:1; // 1 SCI transmitter enable
Uint16 SLEEP:1; // 2 SCI sleep
Uint16 TXWAKE:1; // 3 Transmitter wakeup method
Uint16 rsvd:1; // 4 reserved
Uint16 SWRESET:1; // 5 Software reset
Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable
Uint16 rsvd1:9; // 15:7 reserved
};
union SCICTL1_REG {
Uint16 all;
struct SCICTL1_BITS bit;
};
//---------------------------------------------
// SCICTL2 control register 2 bit definitions:
//
struct SCICTL2_BITS { // bit description
Uint16 TXINTENA:1; // 0 Transmit interrupt enable
Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable
Uint16 rsvd:4; // 5:2 reserved
Uint16 TXEMPTY:1; // 6 Transmitter empty flag
Uint16 TXRDY:1; // 7 Transmitter ready flag
Uint16 rsvd1:8; // 15:8 reserved
};
union SCICTL2_REG {
Uint16 all;
struct SCICTL2_BITS bit;
};
//---------------------------------------------------
// SCIRXST Receiver status register bit definitions:
//
struct SCIRXST_BITS { // bit description
Uint16 rsvd:1; // 0 reserved
Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag
Uint16 PE:1; // 2 Parity error flag
Uint16 OE:1; // 3 Overrun error flag
Uint16 FE:1; // 4 Framing error flag
Uint16 BRKDT:1; // 5 Break-detect flag
Uint16 RXRDY:1; // 6 Receiver ready flag
Uint16 RXERROR:1; // 7 Receiver error flag
};
union SCIRXST_REG {
Uint16 all;
struct SCIRXST_BITS bit;
};
//----------------------------------------------------
// SCIRXBUF Receiver Data Buffer with FIFO bit definitions:
//
struct SCIRXBUF_BITS { // bits description
Uint16 RXDT:8; // 7:0 Receive word
Uint16 rsvd:6; // 13:8 reserved
Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode
Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode
};
union SCIRXBUF_REG {
Uint16 all;
struct SCIRXBUF_BITS bit;
};
//--------------------------------------------------
// SCIPRI Priority control register bit definitions:
//
//
struct SCIPRI_BITS { // bit description
Uint16 rsvd:3; // 2:0 reserved
Uint16 FREE:1; // 3 Free emulation suspend mode
Uint16 SOFT:1; // 4 Soft emulation suspend mode
Uint16 rsvd1:3; // 7:5 reserved
};
union SCIPRI_REG {
Uint16 all;
struct SCIPRI_BITS bit;
};
//-------------------------------------------------
// SCI FIFO Transmit register bit definitions:
//
//
struct SCIFFTX_BITS { // bit description
Uint16 TXFFIL:5; // 4:0 Interrupt level
Uint16 TXFFIENA:1; // 5 Interrupt enable
Uint16 TXFFINTCLR:1; // 6 Clear INT flag
Uint16 TXFFINT:1; // 7 INT flag
Uint16 TXFFST:5; // 12:8 FIFO status
Uint16 TXFIFOXRESET:1; // 13 FIFO reset
Uint16 SCIFFENA:1; // 14 Enhancement enable
Uint16 SCIRST:1; // 15 SCI reset rx/tx channels
};
union SCIFFTX_REG {
Uint16 all;
struct SCIFFTX_BITS bit;
};
//------------------------------------------------
// SCI FIFO recieve register bit definitions:
//
//
struct SCIFFRX_BITS { // bits description
Uint16 RXFFIL:5; // 4:0 Interrupt level
Uint16 RXFFIENA:1; // 5 Interrupt enable
Uint16 RXFFINTCLR:1; // 6 Clear INT flag
Uint16 RXFFINT:1; // 7 INT flag
Uint16 RXFFST:5; // 12:8 FIFO status
Uint16 RXFIFORESET:1; // 13 FIFO reset
Uint16 RXFFOVRCLR:1; // 14 Clear overflow
Uint16 RXFFOVF:1; // 15 FIFO overflow
};
union SCIFFRX_REG {
Uint16 all;
struct SCIFFRX_BITS bit;
};
// SCI FIFO control register bit definitions:
struct SCIFFCT_BITS { // bits description
Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay
Uint16 rsvd:5; // 12:8 reserved
Uint16 CDC:1; // 13 Auto baud mode enable
Uint16 ABDCLR:1; // 14 Auto baud clear
Uint16 ABD:1; // 15 Auto baud detect
};
union SCIFFCT_REG {
Uint16 all;
struct SCIFFCT_BITS bit;
};
//---------------------------------------------------------------------------
// SCI Register File:
//
struct SCI_REGS {
union SCICCR_REG SCICCR; // Communications control register
union SCICTL1_REG SCICTL1; // Control register 1
Uint16 SCIHBAUD; // Baud rate (high) register
Uint16 SCILBAUD; // Baud rate (low) register
union SCICTL2_REG SCICTL2; // Control register 2
union SCIRXST_REG SCIRXST; // Recieve status register
Uint16 SCIRXEMU; // Recieve emulation buffer register
union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer
Uint16 rsvd1; // reserved
Uint16 SCITXBUF; // Transmit data buffer
union SCIFFTX_REG SCIFFTX; // FIFO transmit register
union SCIFFRX_REG SCIFFRX; // FIFO recieve register
union SCIFFCT_REG SCIFFCT; // FIFO control register
Uint16 rsvd2; // reserved
Uint16 rsvd3; // reserved
union SCIPRI_REG SCIPRI; // FIFO Priority control
};
//---------------------------------------------------------------------------
// SCI External References & Function Declarations:
//
extern volatile struct SCI_REGS SciaRegs;
extern volatile struct SCI_REGS ScibRegs;
extern volatile struct SCI_REGS ScicRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_SCI_H definition
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/3 $
// Checkin $Date: April 17, 2008 11:08:27 $
//###########################################################################
//
// FILE: DSP2833x_Spi.h
//
// TITLE: DSP2833x Device SPI Register Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_SPI_H
#define DSP2833x_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
//---------------------------------------------------------------------------
// SPI Individual Register Bit Definitions:
//
// SPI FIFO Transmit register bit definitions:
struct SPIFFTX_BITS { // bit description
Uint16 TXFFIL:5; // 4:0 Interrupt level
Uint16 TXFFIENA:1; // 5 Interrupt enable
Uint16 TXFFINTCLR:1; // 6 Clear INT flag
Uint16 TXFFINT:1; // 7 INT flag
Uint16 TXFFST:5; // 12:8 FIFO status
Uint16 TXFIFO:1; // 13 FIFO reset
Uint16 SPIFFENA:1; // 14 Enhancement enable
Uint16 SPIRST:1; // 15 Reset SPI
};
union SPIFFTX_REG {
Uint16 all;
struct SPIFFTX_BITS bit;
};
//--------------------------------------------
// SPI FIFO recieve register bit definitions:
//
//
struct SPIFFRX_BITS { // bits description
Uint16 RXFFIL:5; // 4:0 Interrupt level
Uint16 RXFFIENA:1; // 5 Interrupt enable
Uint16 RXFFINTCLR:1; // 6 Clear INT flag
Uint16 RXFFINT:1; // 7 INT flag
Uint16 RXFFST:5; // 12:8 FIFO status
Uint16 RXFIFORESET:1; // 13 FIFO reset
Uint16 RXFFOVFCLR:1; // 14 Clear overflow
Uint16 RXFFOVF:1; // 15 FIFO overflow
};
union SPIFFRX_REG {
Uint16 all;
struct SPIFFRX_BITS bit;
};
//--------------------------------------------
// SPI FIFO control register bit definitions:
//
//
struct SPIFFCT_BITS { // bits description
Uint16 TXDLY:8; // 7:0 FIFO transmit delay
Uint16 rsvd:8; // 15:8 reserved
};
union SPIFFCT_REG {
Uint16 all;
struct SPIFFCT_BITS bit;
};
//---------------------------------------------
// SPI configuration register bit definitions:
//
//
struct SPICCR_BITS { // bits description
Uint16 SPICHAR:4; // 3:0 Character length control
Uint16 SPILBK:1; // 4 Loop-back enable/disable
Uint16 rsvd1:1; // 5 reserved
Uint16 CLKPOLARITY:1; // 6 Clock polarity
Uint16 SPISWRESET:1; // 7 SPI SW Reset
Uint16 rsvd2:8; // 15:8 reserved
};
union SPICCR_REG {
Uint16 all;
struct SPICCR_BITS bit;
};
//-------------------------------------------------
// SPI operation control register bit definitions:
//
//
struct SPICTL_BITS { // bits description
Uint16 SPIINTENA:1; // 0 Interrupt enable
Uint16 TALK:1; // 1 Master/Slave transmit enable
Uint16 MASTER_SLAVE:1; // 2 Network control mode
Uint16 CLK_PHASE:1; // 3 Clock phase select
Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable
Uint16 rsvd:11; // 15:5 reserved
};
union SPICTL_REG {
Uint16 all;
struct SPICTL_BITS bit;
};
//--------------------------------------
// SPI status register bit definitions:
//
//
struct SPISTS_BITS { // bits description
Uint16 rsvd1:5; // 4:0 reserved
Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag
Uint16 INT_FLAG:1; // 6 SPI interrupt flag
Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag
Uint16 rsvd2:8; // 15:8 reserved
};
union SPISTS_REG {
Uint16 all;
struct SPISTS_BITS bit;
};
//------------------------------------------------
// SPI priority control register bit definitions:
//
//
struct SPIPRI_BITS { // bits description
Uint16 rsvd1:4; // 3:0 reserved
Uint16 FREE:1; // 4 Free emulation mode control
Uint16 SOFT:1; // 5 Soft emulation mode control
Uint16 rsvd2:1; // 6 reserved
Uint16 rsvd3:9; // 15:7 reserved
};
union SPIPRI_REG {
Uint16 all;
struct SPIPRI_BITS bit;
};
//---------------------------------------------------------------------------
// SPI Register File:
//
struct SPI_REGS {
union SPICCR_REG SPICCR; // Configuration register
union SPICTL_REG SPICTL; // Operation control register
union SPISTS_REG SPISTS; // Status register
Uint16 rsvd1; // reserved
Uint16 SPIBRR; // Baud Rate
Uint16 rsvd2; // reserved
Uint16 SPIRXEMU; // Emulation buffer
Uint16 SPIRXBUF; // Serial input buffer
Uint16 SPITXBUF; // Serial output buffer
Uint16 SPIDAT; // Serial data
union SPIFFTX_REG SPIFFTX; // FIFO transmit register
union SPIFFRX_REG SPIFFRX; // FIFO recieve register
union SPIFFCT_REG SPIFFCT; // FIFO control register
Uint16 rsvd3[2]; // reserved
union SPIPRI_REG SPIPRI; // FIFO Priority control
};
//---------------------------------------------------------------------------
// SPI External References & Function Declarations:
//
extern volatile struct SPI_REGS SpiaRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_SPI_H definition
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/5 $
// Checkin $Date: May 12, 2008 09:34:58 $
//###########################################################################
//
// FILE: DSP2833x_SysCtrl.h
//
// TITLE: DSP2833x Device System Control Register Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_SYS_CTRL_H
#define DSP2833x_SYS_CTRL_H
#ifdef __cplusplus
extern "C" {
#endif
//---------------------------------------------------------------------------
// System Control Individual Register Bit Definitions:
//
// PLL Status Register
struct PLLSTS_BITS { // bits description
Uint16 PLLLOCKS:1; // 0 PLL lock status
Uint16 rsvd1:1; // 1 reserved
Uint16 PLLOFF:1; // 2 PLL off bit
Uint16 MCLKSTS:1; // 3 Missing clock status bit
Uint16 MCLKCLR:1; // 4 Missing clock clear bit
Uint16 OSCOFF:1; // 5 Oscillator clock off
Uint16 MCLKOFF:1; // 6 Missing clock detect
Uint16 DIVSEL:2; // 7 Divide Select
Uint16 rsvd2:7; // 15:7 reserved
};
union PLLSTS_REG {
Uint16 all;
struct PLLSTS_BITS bit;
};
// High speed peripheral clock register bit definitions:
struct HISPCP_BITS { // bits description
Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT
Uint16 rsvd1:13; // 15:3 reserved
};
union HISPCP_REG {
Uint16 all;
struct HISPCP_BITS bit;
};
// Low speed peripheral clock register bit definitions:
struct LOSPCP_BITS { // bits description
Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT
Uint16 rsvd1:13; // 15:3 reserved
};
union LOSPCP_REG {
Uint16 all;
struct LOSPCP_BITS bit;
};
// Peripheral clock control register 0 bit definitions:
struct PCLKCR0_BITS { // bits description
Uint16 rsvd1:2; // 1:0 reserved
Uint16 TBCLKSYNC:1; // 2 EWPM Module TBCLK enable/sync
Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC
Uint16 I2CAENCLK:1; // 4 Enable SYSCLKOUT to I2C-A
Uint16 SCICENCLK:1; // 5 Enalbe low speed clk to SCI-C
Uint16 rsvd2:2; // 7:6 reserved
Uint16 SPIAENCLK:1; // 8 Enable low speed clk to SPI-A
Uint16 rsvd3:1; // 9 reserved
Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A
Uint16 SCIBENCLK:1; // 11 Enable low speed clk to SCI-B
Uint16 MCBSPAENCLK:1; // 12 Enable low speed clk to McBSP-A
Uint16 MCBSPBENCLK:1; // 13 Enable low speed clk to McBSP-B
Uint16 ECANAENCLK:1; // 14 Enable system clk to eCAN-A
Uint16 ECANBENCLK:1; // 15 Enable system clk to eCAN-B
};
union PCLKCR0_REG {
Uint16 all;
struct PCLKCR0_BITS bit;
};
// Peripheral clock control register 1 bit definitions:
struct PCLKCR1_BITS { // bits description
Uint16 EPWM1ENCLK:1; // 0 Enable SYSCLKOUT to EPWM1
Uint16 EPWM2ENCLK:1; // 1 Enable SYSCLKOUT to EPWM2
Uint16 EPWM3ENCLK:1; // 2 Enable SYSCLKOUT to EPWM3
Uint16 EPWM4ENCLK:1; // 3 Enable SYSCLKOUT to EPWM4
Uint16 EPWM5ENCLK:1; // 4 Enable SYSCLKOUT to EPWM5
Uint16 EPWM6ENCLK:1; // 5 Enable SYSCLKOUT to EPWM6
Uint16 rsvd1:2; // 7:6 reserved
Uint16 ECAP1ENCLK:1; // 8 Enable SYSCLKOUT to ECAP1
Uint16 ECAP2ENCLK:1; // 9 Enable SYSCLKOUT to ECAP2
Uint16 ECAP3ENCLK:1; // 10 Enable SYSCLKOUT to ECAP3
Uint16 ECAP4ENCLK:1; // 11 Enable SYSCLKOUT to ECAP4
Uint16 ECAP5ENCLK:1; // 12 Enable SYSCLKOUT to ECAP5
Uint16 ECAP6ENCLK:1; // 13 Enable SYSCLKOUT to ECAP6
Uint16 EQEP1ENCLK:1; // 14 Enable SYSCLKOUT to EQEP1
Uint16 EQEP2ENCLK:1; // 15 Enable SYSCLKOUT to EQEP2
};
union PCLKCR1_REG {
Uint16 all;
struct PCLKCR1_BITS bit;
};
// Peripheral clock control register 2 bit definitions:
struct PCLKCR3_BITS { // bits description
Uint16 rsvd1:8; // 7:0 reserved
Uint16 CPUTIMER0ENCLK:1; // 8 Enable SYSCLKOUT to CPU-Timer 0
Uint16 CPUTIMER1ENCLK:1; // 9 Enable SYSCLKOUT to CPU-Timer 1
Uint16 CPUTIMER2ENCLK:1; // 10 Enable SYSCLKOUT to CPU-Timer 2
Uint16 DMAENCLK:1; // 11 Enable the DMA clock
Uint16 XINTFENCLK:1; // 12 Enable SYSCLKOUT to XINTF
Uint16 GPIOINENCLK:1; // Enable GPIO input clock
Uint16 rsvd2:2; // 15:14 reserved
};
union PCLKCR3_REG {
Uint16 all;
struct PCLKCR3_BITS bit;
};
// PLL control register bit definitions:
struct PLLCR_BITS { // bits description
Uint16 DIV:4; // 3:0 Set clock ratio for the PLL
Uint16 rsvd1:12; // 15:4 reserved
};
union PLLCR_REG {
Uint16 all;
struct PLLCR_BITS bit;
};
// Low Power Mode 0 control register bit definitions:
struct LPMCR0_BITS { // bits description
Uint16 LPM:2; // 1:0 Set the low power mode
Uint16 QUALSTDBY:6; // 7:2 Qualification
Uint16 rsvd1:7; // 14:8 reserved
Uint16 WDINTE:1; // 15 Enables WD to wake the device from STANDBY
};
union LPMCR0_REG {
Uint16 all;
struct LPMCR0_BITS bit;
};
// Dual-mapping configuration register bit definitions:
struct MAPCNF_BITS { // bits description
Uint16 MAPEPWM:1; // 0 EPWM dual-map enable
Uint16 rsvd1:15; // 15:1 reserved
};
union MAPCNF_REG {
Uint16 all;
struct MAPCNF_BITS bit;
};
//---------------------------------------------------------------------------
// System Control Register File:
//
struct SYS_CTRL_REGS {
Uint16 rsvd1; // 0
union PLLSTS_REG PLLSTS; // 1
Uint16 rsvd2[8]; // 2-9
union HISPCP_REG HISPCP; // 10: High-speed peripheral clock pre-scaler
union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler
union PCLKCR0_REG PCLKCR0; // 12: Peripheral clock control register
union PCLKCR1_REG PCLKCR1; // 13: Peripheral clock control register
union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0
Uint16 rsvd3; // 15: reserved
union PCLKCR3_REG PCLKCR3; // 16: Peripheral clock control register
union PLLCR_REG PLLCR; // 17: PLL control register
// No bit definitions are defined for SCSR because
// a read-modify-write instruction can clear the WDOVERRIDE bit
Uint16 SCSR; // 18: System control and status register
Uint16 WDCNTR; // 19: WD counter register
Uint16 rsvd4; // 20
Uint16 WDKEY; // 21: WD reset key register
Uint16 rsvd5[3]; // 22-24
// No bit definitions are defined for WDCR because
// the proper value must be written to the WDCHK field
// whenever writing to this register.
Uint16 WDCR; // 25: WD timer control register
Uint16 rsvd6[4]; // 26-29
union MAPCNF_REG MAPCNF; // 30: Dual-mapping configuration register
Uint16 rsvd7[1]; // 31
};
/* --------------------------------------------------- */
/* CSM Registers */
/* */
/* ----------------------------------------------------*/
/* CSM Status & Control register bit definitions */
struct CSMSCR_BITS { // bit description
Uint16 SECURE:1; // 0 Secure flag
Uint16 rsvd1:14; // 14-1 reserved
Uint16 FORCESEC:1; // 15 Force Secure control bit
};
/* Allow access to the bit fields or entire register */
union CSMSCR_REG {
Uint16 all;
struct CSMSCR_BITS bit;
};
/* CSM Register File */
struct CSM_REGS {
Uint16 KEY0; // KEY reg bits 15-0
Uint16 KEY1; // KEY reg bits 31-16
Uint16 KEY2; // KEY reg bits 47-32
Uint16 KEY3; // KEY reg bits 63-48
Uint16 KEY4; // KEY reg bits 79-64
Uint16 KEY5; // KEY reg bits 95-80
Uint16 KEY6; // KEY reg bits 111-96
Uint16 KEY7; // KEY reg bits 127-112
Uint16 rsvd1; // reserved
Uint16 rsvd2; // reserved
Uint16 rsvd3; // reserved
Uint16 rsvd4; // reserved
Uint16 rsvd5; // reserved
Uint16 rsvd6; // reserved
Uint16 rsvd7; // reserved
union CSMSCR_REG CSMSCR; // CSM Status & Control register
};
/* Password locations */
struct CSM_PWL {
Uint16 PSWD0; // PSWD bits 15-0
Uint16 PSWD1; // PSWD bits 31-16
Uint16 PSWD2; // PSWD bits 47-32
Uint16 PSWD3; // PSWD bits 63-48
Uint16 PSWD4; // PSWD bits 79-64
Uint16 PSWD5; // PSWD bits 95-80
Uint16 PSWD6; // PSWD bits 111-96
Uint16 PSWD7; // PSWD bits 127-112
};
/* Flash Registers */
#define FLASH_SLEEP 0x0000;
#define FLASH_STANDBY 0x0001;
#define FLASH_ACTIVE 0x0003;
/* Flash Option Register bit definitions */
struct FOPT_BITS { // bit description
Uint16 ENPIPE:1; // 0 Enable Pipeline Mode
Uint16 rsvd:15; // 1-15 reserved
};
/* Allow access to the bit fields or entire register */
union FOPT_REG {
Uint16 all;
struct FOPT_BITS bit;
};
/* Flash Power Modes Register bit definitions */
struct FPWR_BITS { // bit description
Uint16 PWR:2; // 0-1 Power Mode bits
Uint16 rsvd:14; // 2-15 reserved
};
/* Allow access to the bit fields or entire register */
union FPWR_REG {
Uint16 all;
struct FPWR_BITS bit;
};
/* Flash Status Register bit definitions */
struct FSTATUS_BITS { // bit description
Uint16 PWRS:2; // 0-1 Power Mode Status bits
Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits
Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits
Uint16 rsvd1:4; // 4-7 reserved
Uint16 V3STAT:1; // 8 VDD3V Status Latch bit
Uint16 rsvd2:7; // 9-15 reserved
};
/* Allow access to the bit fields or entire register */
union FSTATUS_REG {
Uint16 all;
struct FSTATUS_BITS bit;
};
/* Flash Sleep to Standby Wait Counter Register bit definitions */
struct FSTDBYWAIT_BITS { // bit description
Uint16 STDBYWAIT:9; // 0-8 Bank/Pump Sleep to Standby Wait Count bits
Uint16 rsvd:7; // 9-15 reserved
};
/* Allow access to the bit fields or entire register */
union FSTDBYWAIT_REG {
Uint16 all;
struct FSTDBYWAIT_BITS bit;
};
/* Flash Standby to Active Wait Counter Register bit definitions */
struct FACTIVEWAIT_BITS { // bit description
Uint16 ACTIVEWAIT:9; // 0-8 Bank/Pump Standby to Active Wait Count bits
Uint16 rsvd:7; // 9-15 reserved
};
/* Allow access to the bit fields or entire register */
union FACTIVEWAIT_REG {
Uint16 all;
struct FACTIVEWAIT_BITS bit;
};
/* Bank Read Access Wait State Register bit definitions */
struct FBANKWAIT_BITS { // bit description
Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits
Uint16 rsvd1:4; // 4-7 reserved
Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits
Uint16 rsvd2:4; // 12-15 reserved
};
/* Allow access to the bit fields or entire register */
union FBANKWAIT_REG {
Uint16 all;
struct FBANKWAIT_BITS bit;
};
/* OTP Read Access Wait State Register bit definitions */
struct FOTPWAIT_BITS { // bit description
Uint16 OTPWAIT:5; // 0-4 OTP Read Wait State bits
Uint16 rsvd:11; // 5-15 reserved
};
/* Allow access to the bit fields or entire register */
union FOTPWAIT_REG {
Uint16 all;
struct FOTPWAIT_BITS bit;
};
struct FLASH_REGS {
union FOPT_REG FOPT; // Option Register
Uint16 rsvd1; // reserved
union FPWR_REG FPWR; // Power Modes Register
union FSTATUS_REG FSTATUS; // Status Register
union FSTDBYWAIT_REG FSTDBYWAIT; // Pump/Bank Sleep to Standby Wait State Register
union FACTIVEWAIT_REG FACTIVEWAIT; // Pump/Bank Standby to Active Wait State Register
union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register
union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register
};
//---------------------------------------------------------------------------
// System Control External References & Function Declarations:
//
extern volatile struct SYS_CTRL_REGS SysCtrlRegs;
extern volatile struct CSM_REGS CsmRegs;
extern volatile struct CSM_PWL CsmPwl;
extern volatile struct FLASH_REGS FlashRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_SYS_CTRL_H definition
//===========================================================================
// End of file.
//===========================================================================

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v120/DSP2833x_headers/include/DSP2833x_XIntrupt.h Normal file
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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:52:39 $
//###########################################################################
//
// FILE: DSP2833x_XIntrupt.h
//
// TITLE: DSP2833x Device External Interrupt Register Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_XINTRUPT_H
#define DSP2833x_XINTRUPT_H
#ifdef __cplusplus
extern "C" {
#endif
//---------------------------------------------------------------------------
struct XINTCR_BITS {
Uint16 ENABLE:1; // 0 enable/disable
Uint16 rsvd1:1; // 1 reserved
Uint16 POLARITY:2; // 3:2 pos/neg, both triggered
Uint16 rsvd2:12; //15:4 reserved
};
union XINTCR_REG {
Uint16 all;
struct XINTCR_BITS bit;
};
struct XNMICR_BITS {
Uint16 ENABLE:1; // 0 enable/disable
Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to int13
Uint16 POLARITY:2; // 3:2 pos/neg, or both triggered
Uint16 rsvd2:12; // 15:4 reserved
};
union XNMICR_REG {
Uint16 all;
struct XNMICR_BITS bit;
};
//---------------------------------------------------------------------------
// External Interrupt Register File:
//
struct XINTRUPT_REGS {
union XINTCR_REG XINT1CR;
union XINTCR_REG XINT2CR;
union XINTCR_REG XINT3CR;
union XINTCR_REG XINT4CR;
union XINTCR_REG XINT5CR;
union XINTCR_REG XINT6CR;
union XINTCR_REG XINT7CR;
union XNMICR_REG XNMICR;
Uint16 XINT1CTR;
Uint16 XINT2CTR;
Uint16 rsvd[5];
Uint16 XNMICTR;
};
//---------------------------------------------------------------------------
// External Interrupt References & Function Declarations:
//
extern volatile struct XINTRUPT_REGS XIntruptRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_XINTF_H definition
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/3 $
// Checkin $Date: March 20, 2007 16:34:08 $
//###########################################################################
//
// FILE: DSP2833x_Xintf.h
//
// TITLE: DSP2833x Device External Interface Register Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_XINTF_H
#define DSP2833x_XINTF_H
#ifdef __cplusplus
extern "C" {
#endif
// XINTF timing register bit definitions:
struct XTIMING_BITS { // bits description
Uint16 XWRTRAIL:2; // 1:0 Write access trail timing
Uint16 XWRACTIVE:3; // 4:2 Write access active timing
Uint16 XWRLEAD:2; // 6:5 Write access lead timing
Uint16 XRDTRAIL:2; // 8:7 Read access trail timing
Uint16 XRDACTIVE:3; // 11:9 Read access active timing
Uint16 XRDLEAD:2; // 13:12 Read access lead timing
Uint16 USEREADY:1; // 14 Extend access using HW waitstates
Uint16 READYMODE:1; // 15 Ready mode
Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b
Uint16 rsvd1:4; // 21:18 reserved
Uint16 X2TIMING:1; // 22 Double lead/active/trail timing
Uint16 rsvd3:9; // 31:23 reserved
};
union XTIMING_REG {
Uint32 all;
struct XTIMING_BITS bit;
};
// XINTF control register bit definitions:
struct XINTCNF2_BITS { // bits description
Uint16 WRBUFF:2; // 1:0 Write buffer depth
Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK
Uint16 CLKOFF:1; // 3 Disable XCLKOUT
Uint16 rsvd1:2; // 5:4 reserved
Uint16 WLEVEL:2; // 7:6 Current level of the write buffer
Uint16 rsvd2:1; // 8 reserved
Uint16 HOLD:1; // 9 Hold enable/disable
Uint16 HOLDS:1; // 10 Current state of HOLDn input
Uint16 HOLDAS:1; // 11 Current state of HOLDAn output
Uint16 rsvd3:4; // 15:12 reserved
Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK
Uint16 rsvd4:13; // 31:19 reserved
};
union XINTCNF2_REG {
Uint32 all;
struct XINTCNF2_BITS bit;
};
// XINTF bank switching register bit definitions:
struct XBANK_BITS { // bits description
Uint16 BANK:3; // 2:0 Zone for which banking is enabled
Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add
Uint16 rsvd:10; // 15:6 reserved
};
union XBANK_REG {
Uint16 all;
struct XBANK_BITS bit;
};
struct XRESET_BITS {
Uint16 XHARDRESET:1;
Uint16 rsvd1:15;
};
union XRESET_REG {
Uint16 all;
struct XBANK_BITS bit;
};
//---------------------------------------------------------------------------
// XINTF Register File:
//
struct XINTF_REGS {
union XTIMING_REG XTIMING0;
Uint32 rsvd1[5];
union XTIMING_REG XTIMING6;
union XTIMING_REG XTIMING7;
Uint32 rsvd2[2];
union XINTCNF2_REG XINTCNF2;
Uint32 rsvd3;
union XBANK_REG XBANK;
Uint16 rsvd4;
Uint16 XREVISION;
Uint16 rsvd5[2];
union XRESET_REG XRESET;
};
//---------------------------------------------------------------------------
// XINTF External References & Function Declarations:
//
extern volatile struct XINTF_REGS XintfRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_XINTF_H definition
//===========================================================================
// No more.
//===========================================================================