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Dimas
2026-07-09 14:50:52 +03:00
parent 88ddb37225
commit fc2788881f
66 changed files with 19517 additions and 237 deletions
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164
v120/DSP2833x_common/include/DSP2833x_EPwm_defines.h Normal file
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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:45:39 $
//###########################################################################
//
// FILE: DSP2833x_EPwm_defines.h
//
// TITLE: #defines used in ePWM examples examples
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_EPWM_DEFINES_H
#define DSP2833x_EPWM_DEFINES_H
#ifdef __cplusplus
extern "C" {
#endif
// TBCTL (Time-Base Control)
//==========================
// CTRMODE bits
#define TB_COUNT_UP 0x0
#define TB_COUNT_DOWN 0x1
#define TB_COUNT_UPDOWN 0x2
#define TB_FREEZE 0x3
// PHSEN bit
#define TB_DISABLE 0x0
#define TB_ENABLE 0x1
// PRDLD bit
#define TB_SHADOW 0x0
#define TB_IMMEDIATE 0x1
// SYNCOSEL bits
#define TB_SYNC_IN 0x0
#define TB_CTR_ZERO 0x1
#define TB_CTR_CMPB 0x2
#define TB_SYNC_DISABLE 0x3
// HSPCLKDIV and CLKDIV bits
#define TB_DIV1 0x0
#define TB_DIV2 0x1
#define TB_DIV4 0x2
// PHSDIR bit
#define TB_DOWN 0x0
#define TB_UP 0x1
// CMPCTL (Compare Control)
//==========================
// LOADAMODE and LOADBMODE bits
#define CC_CTR_ZERO 0x0
#define CC_CTR_PRD 0x1
#define CC_CTR_ZERO_PRD 0x2
#define CC_LD_DISABLE 0x3
// SHDWAMODE and SHDWBMODE bits
#define CC_SHADOW 0x0
#define CC_IMMEDIATE 0x1
// AQCTLA and AQCTLB (Action Qualifier Control)
//=============================================
// ZRO, PRD, CAU, CAD, CBU, CBD bits
#define AQ_NO_ACTION 0x0
#define AQ_CLEAR 0x1
#define AQ_SET 0x2
#define AQ_TOGGLE 0x3
// DBCTL (Dead-Band Control)
//==========================
// OUT MODE bits
#define DB_DISABLE 0x0
#define DBA_ENABLE 0x1
#define DBB_ENABLE 0x2
#define DB_FULL_ENABLE 0x3
// POLSEL bits
#define DB_ACTV_HI 0x0
#define DB_ACTV_LOC 0x1
#define DB_ACTV_HIC 0x2
#define DB_ACTV_LO 0x3
// IN MODE
#define DBA_ALL 0x0
#define DBB_RED_DBA_FED 0x1
#define DBA_RED_DBB_FED 0x2
#define DBB_ALL 0x3
// CHPCTL (chopper control)
//==========================
// CHPEN bit
#define CHP_DISABLE 0x0
#define CHP_ENABLE 0x1
// CHPFREQ bits
#define CHP_DIV1 0x0
#define CHP_DIV2 0x1
#define CHP_DIV3 0x2
#define CHP_DIV4 0x3
#define CHP_DIV5 0x4
#define CHP_DIV6 0x5
#define CHP_DIV7 0x6
#define CHP_DIV8 0x7
// CHPDUTY bits
#define CHP1_8TH 0x0
#define CHP2_8TH 0x1
#define CHP3_8TH 0x2
#define CHP4_8TH 0x3
#define CHP5_8TH 0x4
#define CHP6_8TH 0x5
#define CHP7_8TH 0x6
// TZSEL (Trip Zone Select)
//==========================
// CBCn and OSHTn bits
#define TZ_DISABLE 0x0
#define TZ_ENABLE 0x1
// TZCTL (Trip Zone Control)
//==========================
// TZA and TZB bits
#define TZ_HIZ 0x0
#define TZ_FORCE_HI 0x1
#define TZ_FORCE_LO 0x2
#define TZ_NO_CHANGE 0x3
// ETSEL (Event Trigger Select)
//=============================
#define ET_CTR_ZERO 0x1
#define ET_CTR_PRD 0x2
#define ET_CTRU_CMPA 0x4
#define ET_CTRD_CMPA 0x5
#define ET_CTRU_CMPB 0x6
#define ET_CTRD_CMPB 0x7
// ETPS (Event Trigger Pre-scale)
//===============================
// INTPRD, SOCAPRD, SOCBPRD bits
#define ET_DISABLE 0x0
#define ET_1ST 0x1
#define ET_2ND 0x2
#define ET_3RD 0x3
//--------------------------------
// HRPWM (High Resolution PWM)
//================================
// HRCNFG
#define HR_Disable 0x0
#define HR_REP 0x1
#define HR_FEP 0x2
#define HR_BEP 0x3
#define HR_CMP 0x0
#define HR_PHS 0x1
#define HR_CTR_ZERO 0x0
#define HR_CTR_PRD 0x1
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // - end of DSP2833x_EPWM_DEFINES_H
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/9 $
// Checkin $Date: July 2, 2008 14:31:12 $
//###########################################################################
//
// FILE: DSP2833x_Examples.h
//
// TITLE: DSP2833x Device Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_EXAMPLES_H
#define DSP2833x_EXAMPLES_H
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------------------------
Specify the PLL control register (PLLCR) and divide select (DIVSEL) value.
-----------------------------------------------------------------------------*/
//#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT
//#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT
#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT
//#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT
#define DSP28_PLLCR CLKMULT*2
//#define DSP28_PLLCR 10
//#define DSP28_PLLCR 9
//#define DSP28_PLLCR 8
//#define DSP28_PLLCR 7
//#define DSP28_PLLCR 6
//#define DSP28_PLLCR 5
//#define DSP28_PLLCR 4
//#define DSP28_PLLCR 3
//#define DSP28_PLLCR 2
//#define DSP28_PLLCR 1
//#define DSP28_PLLCR 0 // PLL is bypassed in this mode
//----------------------------------------------------------------------------
/*-----------------------------------------------------------------------------
Specify the clock rate of the CPU (SYSCLKOUT) in nS.
Take into account the input clock frequency and the PLL multiplier
selected in step 1.
Use one of the values provided, or define your own.
The trailing L is required tells the compiler to treat
the number as a 64-bit value.
Only one statement should be uncommented.
Example 1:150 MHz devices:
CLKIN is a 30MHz crystal.
In step 1 the user specified PLLCR = 0xA for a
150Mhz CPU clock (SYSCLKOUT = 150MHz).
In this case, the CPU_RATE will be 6.667L
Uncomment the line: #define CPU_RATE 6.667L
Example 2: 100 MHz devices:
CLKIN is a 20MHz crystal.
In step 1 the user specified PLLCR = 0xA for a
100Mhz CPU clock (SYSCLKOUT = 100MHz).
In this case, the CPU_RATE will be 10.000L
Uncomment the line: #define CPU_RATE 10.000L
-----------------------------------------------------------------------------*/
#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT)
//----------------------------------------------------------------------------
/*-----------------------------------------------------------------------------
Target device (in DSP2833x_Device.h) determines CPU frequency
(for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz
(for 28332). User does not have to change anything here.
-----------------------------------------------------------------------------*/
#if DSP28_28332 // DSP28_28332 device only
#define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq)
#define CPU_FRQ_150MHZ 0
#else
#define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334
#define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT
#endif
//---------------------------------------------------------------------------
// Include Example Header Files:
//
#include "DSP2833x_GlobalPrototypes.h" // Prototypes for global functions within the
// .c files.
#include "DSP2833x_ePwm_defines.h" // Macros used for PWM examples.
#include "DSP2833x_Dma_defines.h" // Macros used for DMA examples.
#include "DSP2833x_I2C_defines.h" // Macros used for I2C examples.
#define PARTNO_28335 0xEF
#define PARTNO_28334 0xEE
#define PARTNO_28332 0xED
#define PARTNO_28235 0xE8
#define PARTNO_28234 0xE7
#define PARTNO_28232 0xE6
// Include files not used with DSP/BIOS
#ifndef DSP28_BIOS
#include "DSP2833x_DefaultISR.h"
#endif
// DO NOT MODIFY THIS LINE.
#define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / (long double)CPU_RATE) - 9.0L) / 5.0L)
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_EXAMPLES_H definition
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/11 $
// Checkin $Date: May 12, 2008 14:30:08 $
//###########################################################################
//
// FILE: DSP2833x_GlobalPrototypes.h
//
// TITLE: Global prototypes for DSP2833x Examples
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_GLOBALPROTOTYPES_H
#define DSP2833x_GLOBALPROTOTYPES_H
#ifdef __cplusplus
extern "C" {
#endif
/*---- shared global function prototypes -----------------------------------*/
extern void InitAdc(void);
extern void DMAInitialize(void);
// DMA Channel 1
extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
extern void StartDMACH1(void);
// DMA Channel 2
extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
extern void StartDMACH2(void);
// DMA Channel 3
extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
extern void StartDMACH3(void);
// DMA Channel 4
extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
extern void StartDMACH4(void);
// DMA Channel 5
extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
extern void StartDMACH5(void);
// DMA Channel 6
extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
extern void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep);
extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
extern void StartDMACH6(void);
extern void InitPeripherals(void);
#if DSP28_ECANA
extern void InitECan(void);
extern void InitECana(void);
extern void InitECanGpio(void);
extern void InitECanaGpio(void);
#endif // endif DSP28_ECANA
#if DSP28_ECANB
extern void InitECanb(void);
extern void InitECanbGpio(void);
#endif // endif DSP28_ECANB
extern void InitECap(void);
extern void InitECapGpio(void);
extern void InitECap1Gpio(void);
extern void InitECap2Gpio(void);
#if DSP28_ECAP3
extern void InitECap3Gpio(void);
#endif // endif DSP28_ECAP3
#if DSP28_ECAP4
extern void InitECap4Gpio(void);
#endif // endif DSP28_ECAP4
#if DSP28_ECAP5
extern void InitECap5Gpio(void);
#endif // endif DSP28_ECAP5
#if DSP28_ECAP6
extern void InitECap6Gpio(void);
#endif // endif DSP28_ECAP6
extern void InitEPwm(void);
extern void InitEPwmGpio(void);
extern void InitEPwm1Gpio(void);
extern void InitEPwm2Gpio(void);
extern void InitEPwm3Gpio(void);
#if DSP28_EPWM4
extern void InitEPwm4Gpio(void);
#endif // endif DSP28_EPWM4
#if DSP28_EPWM5
extern void InitEPwm5Gpio(void);
#endif // endif DSP28_EPWM5
#if DSP28_EPWM6
extern void InitEPwm6Gpio(void);
#endif // endif DSP28_EPWM6
#if DSP28_EQEP1
extern void InitEQep(void);
extern void InitEQepGpio(void);
extern void InitEQep1Gpio(void);
#endif // if DSP28_EQEP1
#if DSP28_EQEP2
extern void InitEQep2Gpio(void);
#endif // endif DSP28_EQEP2
extern void InitGpio(void);
extern void InitI2CGpio(void);
extern void InitMcbsp(void);
extern void InitMcbspa(void);
extern void delay_loop(void);
extern void InitMcbspaGpio(void);
extern void InitMcbspa8bit(void);
extern void InitMcbspa12bit(void);
extern void InitMcbspa16bit(void);
extern void InitMcbspa20bit(void);
extern void InitMcbspa24bit(void);
extern void InitMcbspa32bit(void);
#if DSP28_MCBSPB
extern void InitMcbspb(void);
extern void InitMcbspbGpio(void);
extern void InitMcbspb8bit(void);
extern void InitMcbspb12bit(void);
extern void InitMcbspb16bit(void);
extern void InitMcbspb20bit(void);
extern void InitMcbspb24bit(void);
extern void InitMcbspb32bit(void);
#endif // endif DSP28_MCBSPB
extern void InitPieCtrl(void);
extern void InitPieVectTable(void);
extern void InitSci(void);
extern void InitSciGpio(void);
extern void InitSciaGpio(void);
#if DSP28_SCIB
extern void InitScibGpio(void);
#endif // endif DSP28_SCIB
#if DSP28_SCIC
extern void InitScicGpio(void);
#endif
extern void InitSpi(void);
extern void InitSpiGpio(void);
extern void InitSpiaGpio(void);
extern void InitSysCtrl(void);
extern void InitTzGpio(void);
extern void InitXIntrupt(void);
extern void XintfInit(void);
extern void InitXintf16Gpio();
extern void InitXintf32Gpio();
extern void InitPll(Uint16 pllcr, Uint16 clkindiv);
extern void InitPeripheralClocks(void);
extern void EnableInterrupts(void);
extern void DSP28x_usDelay(Uint32 Count);
extern void ADC_cal (void);
#define KickDog ServiceDog // For compatiblity with previous versions
extern void ServiceDog(void);
extern void DisableDog(void);
extern Uint16 CsmUnlock(void);
// DSP28_DBGIER.asm
extern void SetDBGIER(Uint16 dbgier);
// CAUTION
// This function MUST be executed out of RAM. Executing it
// out of OTP/Flash will yield unpredictable results
extern void InitFlash(void);
void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr);
//---------------------------------------------------------------------------
// External symbols created by the linker cmd file
// DSP28 examples will use these to relocate code from one LOAD location
// in either Flash or XINTF to a different RUN location in internal
// RAM
extern Uint16 RamfuncsLoadStart;
extern Uint16 RamfuncsLoadEnd;
extern Uint16 RamfuncsRunStart;
extern Uint16 XintffuncsLoadStart;
extern Uint16 XintffuncsLoadEnd;
extern Uint16 XintffuncsRunStart;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // - end of DSP2833x_GLOBALPROTOTYPES_H
//===========================================================================
// End of file.
//===========================================================================

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v120/DSP2833x_common/include/DSP2833x_I2c_defines.h Normal file
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// TI File $Revision: /main/2 $
// Checkin $Date: April 16, 2008 17:16:47 $
//###########################################################################
//
// FILE: DSP2833x_I2cExample.h
//
// TITLE: 2833x I2C Example Code Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_I2C_DEFINES_H
#define DSP2833x_I2C_DEFINES_H
//--------------------------------------------
// Defines
//--------------------------------------------
// Error Messages
#define I2C_ERROR 0xFFFF
#define I2C_ARB_LOST_ERROR 0x0001
#define I2C_NACK_ERROR 0x0002
#define I2C_BUS_BUSY_ERROR 0x1000
#define I2C_STP_NOT_READY_ERROR 0x5555
#define I2C_NO_FLAGS 0xAAAA
#define I2C_SUCCESS 0x0000
// Clear Status Flags
#define I2C_CLR_AL_BIT 0x0001
#define I2C_CLR_NACK_BIT 0x0002
#define I2C_CLR_ARDY_BIT 0x0004
#define I2C_CLR_RRDY_BIT 0x0008
#define I2C_CLR_SCD_BIT 0x0020
// Interrupt Source Messages
#define I2C_NO_ISRC 0x0000
#define I2C_ARB_ISRC 0x0001
#define I2C_NACK_ISRC 0x0002
#define I2C_ARDY_ISRC 0x0003
#define I2C_RX_ISRC 0x0004
#define I2C_TX_ISRC 0x0005
#define I2C_SCD_ISRC 0x0006
#define I2C_AAS_ISRC 0x0007
// I2CMSG structure defines
#define I2C_NO_STOP 0
#define I2C_YES_STOP 1
#define I2C_RECEIVE 0
#define I2C_TRANSMIT 1
#define I2C_MAX_BUFFER_SIZE 16
// I2C Slave State defines
#define I2C_NOTSLAVE 0
#define I2C_ADDR_AS_SLAVE 1
#define I2C_ST_MSG_READY 2
// I2C Slave Receiver messages defines
#define I2C_SND_MSG1 1
#define I2C_SND_MSG2 2
// I2C State defines
#define I2C_IDLE 0
#define I2C_SLAVE_RECEIVER 1
#define I2C_SLAVE_TRANSMITTER 2
#define I2C_MASTER_RECEIVER 3
#define I2C_MASTER_TRANSMITTER 4
// I2C Message Commands for I2CMSG struct
#define I2C_MSGSTAT_INACTIVE 0x0000
#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010
#define I2C_MSGSTAT_WRITE_BUSY 0x0011
#define I2C_MSGSTAT_SEND_NOSTOP 0x0020
#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021
#define I2C_MSGSTAT_RESTART 0x0022
#define I2C_MSGSTAT_READ_BUSY 0x0023
// Generic defines
#define I2C_TRUE 1
#define I2C_FALSE 0
#define I2C_YES 1
#define I2C_NO 0
#define I2C_DUMMY_BYTE 0
//--------------------------------------------
// Structures
//--------------------------------------------
// I2C Message Structure
struct I2CMSG {
Uint16 MsgStatus; // Word stating what state msg is in:
// I2C_MSGCMD_INACTIVE = do not send msg
// I2C_MSGCMD_BUSY = msg start has been sent,
// awaiting stop
// I2C_MSGCMD_SEND_WITHSTOP = command to send
// master trans msg complete with a stop bit
// I2C_MSGCMD_SEND_NOSTOP = command to send
// master trans msg without the stop bit
// I2C_MSGCMD_RESTART = command to send a restart
// as a master receiver with a stop bit
Uint16 SlaveAddress; // I2C address of slave msg is intended for
Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer)
Uint16 MemoryHighAddr; // EEPROM address of data associated with msg (high byte)
Uint16 MemoryLowAddr; // EEPROM address of data associated with msg (low byte)
Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; // Array holding msg data - max that
// MAX_BUFFER_SIZE can be is 16 due to
// the FIFO's
};
#endif // end of DSP2833x_I2C_DEFINES_H definition
//===========================================================================
// End of file.
//===========================================================================

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v120/DSP2833x_common/include/DSP2833x_SWPrioritizedIsrLevels.h Normal file
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v120/DSP2833x_common/source/DSP2833x_PieCtrl.c Normal file
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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:46:35 $
//###########################################################################
//
// FILE: DSP2833x_PieCtrl.c
//
// TITLE: DSP2833x Device PIE Control Register Initialization Functions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
//---------------------------------------------------------------------------
// InitPieCtrl:
//---------------------------------------------------------------------------
// This function initializes the PIE control registers to a known state.
//
void InitPieCtrl(void)
{
// Disable Interrupts at the CPU level:
DINT;
// Disable the PIE
PieCtrlRegs.PIECTRL.bit.ENPIE = 0;
// Clear all PIEIER registers:
PieCtrlRegs.PIEIER1.all = 0;
PieCtrlRegs.PIEIER2.all = 0;
PieCtrlRegs.PIEIER3.all = 0;
PieCtrlRegs.PIEIER4.all = 0;
PieCtrlRegs.PIEIER5.all = 0;
PieCtrlRegs.PIEIER6.all = 0;
PieCtrlRegs.PIEIER7.all = 0;
PieCtrlRegs.PIEIER8.all = 0;
PieCtrlRegs.PIEIER9.all = 0;
PieCtrlRegs.PIEIER10.all = 0;
PieCtrlRegs.PIEIER11.all = 0;
PieCtrlRegs.PIEIER12.all = 0;
// Clear all PIEIFR registers:
PieCtrlRegs.PIEIFR1.all = 0;
PieCtrlRegs.PIEIFR2.all = 0;
PieCtrlRegs.PIEIFR3.all = 0;
PieCtrlRegs.PIEIFR4.all = 0;
PieCtrlRegs.PIEIFR5.all = 0;
PieCtrlRegs.PIEIFR6.all = 0;
PieCtrlRegs.PIEIFR7.all = 0;
PieCtrlRegs.PIEIFR8.all = 0;
PieCtrlRegs.PIEIFR9.all = 0;
PieCtrlRegs.PIEIFR10.all = 0;
PieCtrlRegs.PIEIFR11.all = 0;
PieCtrlRegs.PIEIFR12.all = 0;
}
//---------------------------------------------------------------------------
// EnableInterrupts:
//---------------------------------------------------------------------------
// This function enables the PIE module and CPU interrupts
//
void EnableInterrupts()
{
// Enable the PIE
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
// Enables PIE to drive a pulse into the CPU
PieCtrlRegs.PIEACK.all = 0xFFFF;
// Enable Interrupts at the CPU level
EINT;
}
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:46:38 $
//###########################################################################
//
// FILE: DSP2833x_PieVect.c
//
// TITLE: DSP2833x Devices PIE Vector Table Initialization Functions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
const struct PIE_VECT_TABLE PieVectTableInit = {
PIE_RESERVED, // 0 Reserved space
PIE_RESERVED, // 1 Reserved space
PIE_RESERVED, // 2 Reserved space
PIE_RESERVED, // 3 Reserved space
PIE_RESERVED, // 4 Reserved space
PIE_RESERVED, // 5 Reserved space
PIE_RESERVED, // 6 Reserved space
PIE_RESERVED, // 7 Reserved space
PIE_RESERVED, // 8 Reserved space
PIE_RESERVED, // 9 Reserved space
PIE_RESERVED, // 10 Reserved space
PIE_RESERVED, // 11 Reserved space
PIE_RESERVED, // 12 Reserved space
// Non-Peripheral Interrupts
INT13_ISR, // XINT13 or CPU-Timer 1
INT14_ISR, // CPU-Timer2
DATALOG_ISR, // Datalogging interrupt
RTOSINT_ISR, // RTOS interrupt
EMUINT_ISR, // Emulation interrupt
NMI_ISR, // Non-maskable interrupt
ILLEGAL_ISR, // Illegal operation TRAP
USER1_ISR, // User Defined trap 1
USER2_ISR, // User Defined trap 2
USER3_ISR, // User Defined trap 3
USER4_ISR, // User Defined trap 4
USER5_ISR, // User Defined trap 5
USER6_ISR, // User Defined trap 6
USER7_ISR, // User Defined trap 7
USER8_ISR, // User Defined trap 8
USER9_ISR, // User Defined trap 9
USER10_ISR, // User Defined trap 10
USER11_ISR, // User Defined trap 11
USER12_ISR, // User Defined trap 12
// Group 1 PIE Vectors
SEQ1INT_ISR, // 1.1 ADC
SEQ2INT_ISR, // 1.2 ADC
rsvd_ISR, // 1.3
XINT1_ISR, // 1.4
XINT2_ISR, // 1.5
ADCINT_ISR, // 1.6 ADC
TINT0_ISR, // 1.7 Timer 0
WAKEINT_ISR, // 1.8 WD, Low Power
// Group 2 PIE Vectors
EPWM1_TZINT_ISR, // 2.1 EPWM-1 Trip Zone
EPWM2_TZINT_ISR, // 2.2 EPWM-2 Trip Zone
EPWM3_TZINT_ISR, // 2.3 EPWM-3 Trip Zone
EPWM4_TZINT_ISR, // 2.4 EPWM-4 Trip Zone
EPWM5_TZINT_ISR, // 2.5 EPWM-5 Trip Zone
EPWM6_TZINT_ISR, // 2.6 EPWM-6 Trip Zone
rsvd_ISR, // 2.7
rsvd_ISR, // 2.8
// Group 3 PIE Vectors
EPWM1_INT_ISR, // 3.1 EPWM-1 Interrupt
EPWM2_INT_ISR, // 3.2 EPWM-2 Interrupt
EPWM3_INT_ISR, // 3.3 EPWM-3 Interrupt
EPWM4_INT_ISR, // 3.4 EPWM-4 Interrupt
EPWM5_INT_ISR, // 3.5 EPWM-5 Interrupt
EPWM6_INT_ISR, // 3.6 EPWM-6 Interrupt
rsvd_ISR, // 3.7
rsvd_ISR, // 3.8
// Group 4 PIE Vectors
ECAP1_INT_ISR, // 4.1 ECAP-1
ECAP2_INT_ISR, // 4.2 ECAP-2
ECAP3_INT_ISR, // 4.3 ECAP-3
ECAP4_INT_ISR, // 4.4 ECAP-4
ECAP5_INT_ISR, // 4.5 ECAP-5
ECAP6_INT_ISR, // 4.6 ECAP-6
rsvd_ISR, // 4.7
rsvd_ISR, // 4.8
// Group 5 PIE Vectors
EQEP1_INT_ISR, // 5.1 EQEP-1
EQEP2_INT_ISR, // 5.2 EQEP-2
rsvd_ISR, // 5.3
rsvd_ISR, // 5.4
rsvd_ISR, // 5.5
rsvd_ISR, // 5.6
rsvd_ISR, // 5.7
rsvd_ISR, // 5.8
// Group 6 PIE Vectors
SPIRXINTA_ISR, // 6.1 SPI-A
SPITXINTA_ISR, // 6.2 SPI-A
MRINTA_ISR, // 6.3 McBSP-A
MXINTA_ISR, // 6.4 McBSP-A
MRINTB_ISR, // 6.5 McBSP-B
MXINTB_ISR, // 6.6 McBSP-B
rsvd_ISR, // 6.7
rsvd_ISR, // 6.8
// Group 7 PIE Vectors
DINTCH1_ISR, // 7.1 DMA channel 1
DINTCH2_ISR, // 7.2 DMA channel 2
DINTCH3_ISR, // 7.3 DMA channel 3
DINTCH4_ISR, // 7.4 DMA channel 4
DINTCH5_ISR, // 7.5 DMA channel 5
DINTCH6_ISR, // 7.6 DMA channel 6
rsvd_ISR, // 7.7
rsvd_ISR, // 7.8
// Group 8 PIE Vectors
I2CINT1A_ISR, // 8.1 I2C
I2CINT2A_ISR, // 8.2 I2C
rsvd_ISR, // 8.3
rsvd_ISR, // 8.4
SCIRXINTC_ISR, // 8.5 SCI-C
SCITXINTC_ISR, // 8.6 SCI-C
rsvd_ISR, // 8.7
rsvd_ISR, // 8.8
// Group 9 PIE Vectors
SCIRXINTA_ISR, // 9.1 SCI-A
SCITXINTA_ISR, // 9.2 SCI-A
SCIRXINTB_ISR, // 9.3 SCI-B
SCITXINTB_ISR, // 9.4 SCI-B
ECAN0INTA_ISR, // 9.5 eCAN-A
ECAN1INTA_ISR, // 9.6 eCAN-A
ECAN0INTB_ISR, // 9.7 eCAN-B
ECAN1INTB_ISR, // 9.8 eCAN-B
// Group 10 PIE Vectors
rsvd_ISR, // 10.1
rsvd_ISR, // 10.2
rsvd_ISR, // 10.3
rsvd_ISR, // 10.4
rsvd_ISR, // 10.5
rsvd_ISR, // 10.6
rsvd_ISR, // 10.7
rsvd_ISR, // 10.8
// Group 11 PIE Vectors
rsvd_ISR, // 11.1
rsvd_ISR, // 11.2
rsvd_ISR, // 11.3
rsvd_ISR, // 11.4
rsvd_ISR, // 11.5
rsvd_ISR, // 11.6
rsvd_ISR, // 11.7
rsvd_ISR, // 11.8
// Group 12 PIE Vectors
XINT3_ISR, // 12.1
XINT4_ISR, // 12.2
XINT5_ISR, // 12.3
XINT6_ISR, // 12.4
XINT7_ISR, // 12.5
rsvd_ISR, // 12.6
LVF_ISR, // 12.7
LUF_ISR, // 12.8
};
//---------------------------------------------------------------------------
// InitPieVectTable:
//---------------------------------------------------------------------------
// This function initializes the PIE vector table to a known state.
// This function must be executed after boot time.
//
void InitPieVectTable(void)
{
int16 i;
Uint32 *Source = (void *) &PieVectTableInit;
Uint32 *Dest = (void *) &PieVectTable;
EALLOW;
for(i=0; i < 128; i++)
*Dest++ = *Source++;
EDIS;
// Enable the PIE Vector Table
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
}
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/5 $
// Checkin $Date: January 14, 2008 11:28:12 $
//###########################################################################
//
// FILE: DSP2833x_SWPrioritizedDefaultIsr.c
//
// TITLE: DSP2833x Device Default Software Prioritized Interrupt Service Routines.
//
//###########################################################################
//
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
#include "DSP2833x_SWPrioritizedIsrLevels.h"
// Connected to INT13 of CPU (use MINT13 mask):
// Note CPU-Timer1 is reserved for TI use, however XINT13
// ISR can be used by the user.
#if (INT13PL != 0)
interrupt void INT13_ISR(void) // INT13 or CPU-Timer1
{
IER |= MINT13; // Set "global" priority
EINT;
// Insert ISR Code here
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to INT14 of CPU (use MINT14 mask):
#if (INT14PL != 0)
interrupt void INT14_ISR(void) // CPU-Timer2
{
IER |= MINT14; // Set "global" priority
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to INT15 of CPU (use MINT15 mask):
#if (INT15PL != 0)
interrupt void DATALOG_ISR(void) // Datalogging interrupt
{
IER |= MINT15; // Set "global" priority
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to INT16 of CPU (use MINT16 mask):
#if (INT16PL != 0)
interrupt void RTOSINT_ISR(void) // RTOS interrupt
{
IER |= MINT16; // Set "global" priority
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to EMUINT of CPU (non-maskable):
interrupt void EMUINT_ISR(void) // Emulation interrupt
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// Connected to NMI of CPU (non-maskable):
interrupt void NMI_ISR(void) // Non-maskable interrupt
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void ILLEGAL_ISR(void) // Illegal operation TRAP
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER1_ISR(void) // User Defined trap 1
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER2_ISR(void) // User Defined trap 2
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER3_ISR(void) // User Defined trap 3
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER4_ISR(void) // User Defined trap 4
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER5_ISR(void) // User Defined trap 5
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER6_ISR(void) // User Defined trap 6
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER7_ISR(void) // User Defined trap 7
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER8_ISR(void) // User Defined trap 8
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER9_ISR(void) // User Defined trap 9
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER10_ISR(void) // User Defined trap 10
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER11_ISR(void) // User Defined trap 11
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER12_ISR(void) // User Defined trap 12
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// -----------------------------------------------------------
// PIE Group 1 - MUXed into CPU INT1
// -----------------------------------------------------------
// Connected to PIEIER1_1 (use MINT1 and MG11 masks):
#if (G11PL != 0)
interrupt void SEQ1INT_ISR( void ) // ADC
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
IER |= M_INT1;
IER &= MINT1; // Set "global" priority
PieCtrlRegs.PIEIER1.all &= MG11; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER1.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER1_2 (use MINT1 and MG12 masks):
#if (G12PL != 0)
interrupt void SEQ2INT_ISR( void ) // ADC
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
IER |= M_INT1;
IER &= MINT1; // Set "global" priority
PieCtrlRegs.PIEIER1.all &= MG12; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER1.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER1_4 (use MINT1 and MG14 masks):
#if (G14PL != 0)
interrupt void XINT1_ISR(void)
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
IER |= MINT1; // Set "global" priority
PieCtrlRegs.PIEIER1.all &= MG14; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER1.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER1_5 (use MINT1 and MG15 masks):
#if (G15PL != 0)
interrupt void XINT2_ISR(void)
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
IER |= MINT1; // Set "global" priority
PieCtrlRegs.PIEIER1.all &= MG15; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER1.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER1_6 (use MINT1 and MG16 masks):
#if (G16PL != 0)
interrupt void ADCINT_ISR(void) // ADC
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
IER |= M_INT1;
IER &= MINT1; // Set "global" priority
PieCtrlRegs.PIEIER1.all &= MG16; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER1.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER1_7 (use MINT1 and MG17 masks):
#if (G17PL != 0)
interrupt void TINT0_ISR(void) // CPU-Timer 0
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
IER |= M_INT1;
IER &= MINT1; // Set "global" priority
PieCtrlRegs.PIEIER1.all &= MG17; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER1.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER1_8 (use MINT1 and MG18 masks):
#if (G18PL != 0)
interrupt void WAKEINT_ISR(void) // WD/LPM
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
IER |= M_INT1;
IER &= MINT1; // Set "global" priority
PieCtrlRegs.PIEIER1.all &= MG18; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER1.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// -----------------------------------------------------------
// PIE Group 2 - MUXed into CPU INT2
// -----------------------------------------------------------
// Connected to PIEIER2_1 (use MINT2 and MG21 masks):
#if (G21PL != 0)
interrupt void EPWM1_TZINT_ISR(void) // ePWM1 Trip Zone
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
IER |= M_INT2;
IER &= MINT2; // Set "global" priority
PieCtrlRegs.PIEIER2.all &= MG21; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER2.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER2_2 (use MINT2 and MG22 masks):
#if (G22PL != 0)
interrupt void EPWM2_TZINT_ISR(void) // ePWM2 Trip Zone
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
IER |= M_INT2;
IER &= MINT2; // Set "global" priority
PieCtrlRegs.PIEIER2.all &= MG22; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER2.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER2_3 (use MINT2 and MG23 masks):
#if (G23PL != 0)
interrupt void EPWM3_TZINT_ISR(void) // ePWM3 Trip Zone
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
IER |= M_INT2;
IER &= MINT2; // Set "global" priority
PieCtrlRegs.PIEIER2.all &= MG23; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER2.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER2_4 (use MINT2 and MG24 masks):
#if (G24PL != 0)
interrupt void EPWM4_TZINT_ISR(void) // ePWM4 Trip Zone
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
IER |= M_INT2;
IER &= MINT2; // Set "global" priority
PieCtrlRegs.PIEIER2.all &= MG24; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER2.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER2_5 (use MINT2 and MG25 masks):
#if (G25PL != 0)
interrupt void EPWM5_TZINT_ISR(void) // ePWM5 Trip Zone
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
IER |= M_INT2;
IER &= MINT2; // Set "global" priority
PieCtrlRegs.PIEIER2.all &= MG25; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER2.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER2_6 (use MINT2 and MG26 masks):
#if (G26PL != 0)
interrupt void EPWM6_TZINT_ISR(void) // ePWM6 Trip Zone
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
IER |= M_INT2;
IER &= MINT2; // Set "global" priority
PieCtrlRegs.PIEIER2.all &= MG26; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER2.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// -----------------------------------------------------------
// PIE Group 3 - MUXed into CPU INT3
// -----------------------------------------------------------
// Connected to PIEIER3_1 (use MINT3 and MG31 masks):
#if (G31PL != 0)
interrupt void EPWM1_INT_ISR(void) // ePWM1 Interrupt
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
IER |= M_INT3;
IER &= MINT3; // Set "global" priority
PieCtrlRegs.PIEIER3.all &= MG31; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER3.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER3_2 (use MINT3 and MG32 masks):
#if (G32PL != 0)
interrupt void EPWM2_INT_ISR(void) // ePWM2 Interrupt
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
IER |= M_INT3;
IER &= MINT3; // Set "global" priority
PieCtrlRegs.PIEIER3.all &= MG32; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER3.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER3_3 (use MINT3 and MG33 masks):
#if (G33PL != 0)
interrupt void EPWM3_INT_ISR(void) // ePWM3 Interrupt
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
IER |= M_INT3;
IER &= MINT3; // Set "global" priority
PieCtrlRegs.PIEIER3.all &= MG33; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER3.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER3_4 (use MINT3 and MG34 masks):
#if (G34PL != 0)
interrupt void EPWM4_INT_ISR(void) // ePWM4 Interrupt
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
IER |= M_INT3;
IER &= MINT3; // Set "global" priority
PieCtrlRegs.PIEIER3.all &= MG34; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER3.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER3_5 (use MINT3 and MG35 masks):
#if (G35PL != 0)
interrupt void EPWM5_INT_ISR(void) // ePWM5 Interrupt
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
IER |= M_INT3;
IER &= MINT3; // Set "global" priority
PieCtrlRegs.PIEIER3.all &= MG35; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER3.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER3_6 (use MINT3 and MG36 masks):
#if (G36PL != 0)
interrupt void EPWM6_INT_ISR(void) // ePWM6 Interrupt
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
IER |= M_INT3;
IER &= MINT3; // Set "global" priority
PieCtrlRegs.PIEIER3.all &= MG36; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER3.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// -----------------------------------------------------------
// PIE Group 4 - MUXed into CPU INT4
// -----------------------------------------------------------
// Connected to PIEIER4_1 (use MINT4 and MG41 masks):
#if (G41PL != 0)
interrupt void ECAP1_INT_ISR(void) // eCAP1 Interrupt
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
IER |= M_INT4;
IER &= MINT4; // Set "global" priority
PieCtrlRegs.PIEIER4.all &= MG41; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER4.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER4_2 (use MINT4 and MG42 masks):
#if (G42PL != 0)
interrupt void ECAP2_INT_ISR(void) // eCAP2 Interrupt
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all;
IER |= M_INT4;
IER &= MINT4; // Set "global" priority
PieCtrlRegs.PIEIER4.all &= MG42; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER4.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER4_3 (use MINT4 and MG43 masks):
#if (G43PL != 0)
interrupt void ECAP3_INT_ISR(void) // eCAP3 Interrupt
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
IER |= M_INT4;
IER &= MINT4; // Set "global" priority
PieCtrlRegs.PIEIER4.all &= MG43; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER4.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER4_4 (use MINT4 and MG44 masks):
#if (G44PL != 0)
interrupt void ECAP4_INT_ISR(void) // eCAP4 Interrupt
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
IER |= M_INT4;
IER &= MINT4; // Set "global" priority
PieCtrlRegs.PIEIER4.all &= MG44; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER4.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER4_5 (use MINT4 and MG45 masks):
#if (G45PL != 0)
interrupt void ECAP5_INT_ISR(void) // eCAP5 Interrupt
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
IER |= M_INT4;
IER &= MINT4; // Set "global" priority
PieCtrlRegs.PIEIER4.all &= MG45; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER4.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER4_6 (use MINT4 and MG46 masks):
#if (G46PL != 0)
interrupt void ECAP6_INT_ISR(void) // eCAP6 Interrupt
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
IER |= M_INT4;
IER &= MINT4; // Set "global" priority
PieCtrlRegs.PIEIER4.all &= MG46; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER4.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// -----------------------------------------------------------
// PIE Group 5 - MUXed into CPU INT5
// -----------------------------------------------------------
// Connected to PIEIER5_1 (use MINT5 and MG51 masks):
#if (G51PL != 0)
interrupt void EQEP1_INT_ISR(void) // eQEP1 Interrupt
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all;
IER |= M_INT5;
IER &= MINT5; // Set "global" priority
PieCtrlRegs.PIEIER5.all &= MG51; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER5.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER5_2 (use MINT5 and MG52 masks):
#if (G52PL != 0)
interrupt void EQEP2_INT_ISR(void) // eQEP2 Interrupt
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all;
IER |= M_INT5;
IER &= MINT5; // Set "global" priority
PieCtrlRegs.PIEIER5.all &= MG52; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER5.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// -----------------------------------------------------------
// PIE Group 6 - MUXed into CPU INT6
// -----------------------------------------------------------
// Connected to PIEIER6_1 (use MINT6 and MG61 masks):
#if (G61PL != 0)
interrupt void SPIRXINTA_ISR(void) // SPI-A
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
IER |= M_INT6;
IER &= MINT6; // Set "global" priority
PieCtrlRegs.PIEIER6.all &= MG61; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER6.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER6_2 (use MINT6 and MG62 masks):
#if (G62PL != 0)
interrupt void SPITXINTA_ISR(void) // SPI-A
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
IER |= M_INT6;
IER &= MINT6; // Set "global" priority
PieCtrlRegs.PIEIER6.all &= MG62; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER6.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER6_3 (use MINT6 and MG63 masks):
#if (G63PL != 0)
interrupt void MRINTB_ISR(void) // McBSP-B
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
IER |= M_INT6;
IER &= MINT6; // Set "global" priority
PieCtrlRegs.PIEIER6.all &= MG63; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER6.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER6_4 (use MINT6 and MG64 masks):
#if (G64PL != 0)
interrupt void MXINTB_ISR(void) // McBSP-B
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
IER |= M_INT6;
IER &= MINT6; // Set "global" priority
PieCtrlRegs.PIEIER6.all &= MG64; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER6.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER6_5 (use MINT6 and MG65 masks):
#if (G65PL != 0)
interrupt void MRINTA_ISR(void) // McBSP-A
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
IER |= M_INT6;
IER &= MINT6; // Set "global" priority
PieCtrlRegs.PIEIER6.all &= MG65; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER6.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER6_6 (use MINT6 and MG66 masks):
#if (G66PL != 0)
interrupt void MXINTA_ISR(void) // McBSP-A
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
IER |= M_INT6;
IER &= MINT6; // Set "global" priority
PieCtrlRegs.PIEIER6.all &= MG66; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER6.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// -----------------------------------------------------------
// PIE Group 7 - MUXed into CPU INT7
// -----------------------------------------------------------
// Connected to PIEIER7_1 (use MINT7 and MG71 masks):
#if (G71PL != 0)
interrupt void DINTCH1_ISR(void) // DMA
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
IER |= M_INT7;
IER &= MINT7; // Set "global" priority
PieCtrlRegs.PIEIER7.all &= MG71; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER7.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER7_2 (use MINT7 and MG72 masks):
#if (G72PL != 0)
interrupt void DINTCH2_ISR(void) // DMA
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
IER |= M_INT7;
IER &= MINT7; // Set "global" priority
PieCtrlRegs.PIEIER7.all &= MG72; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER7.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER7_3 (use MINT7 and MG73 masks):
#if (G73PL != 0)
interrupt void DINTCH3_ISR(void) // DMA
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
IER |= M_INT7;
IER &= MINT7; // Set "global" priority
PieCtrlRegs.PIEIER7.all &= MG73; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER7.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER7_4 (use MINT7 and MG74 masks):
#if (G74PL != 0)
interrupt void DINTCH4_ISR(void) // DMA
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
IER |= M_INT7;
IER &= MINT7; // Set "global" priority
PieCtrlRegs.PIEIER7.all &= MG74; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER7.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER7_5 (use MINT7 and MG75 masks):
#if (G75PL != 0)
interrupt void DINTCH5_ISR(void) // DMA
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
IER |= M_INT7;
IER &= MINT7; // Set "global" priority
PieCtrlRegs.PIEIER7.all &= MG75; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER7.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER7_6 (use MINT7 and MG76 masks):
#if (G76PL != 0)
interrupt void DINTCH6_ISR(void) // DMA
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
IER |= M_INT7;
IER &= MINT7; // Set "global" priority
PieCtrlRegs.PIEIER7.all &= MG76; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER7.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// -----------------------------------------------------------
// PIE Group 8 - MUXed into CPU INT8
// -----------------------------------------------------------
// Connected to PIEIER8_1 (use MINT8 and MG81 masks):
#if (G81PL != 0)
interrupt void I2CINT1A_ISR(void) // I2C-A
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all;
IER |= M_INT8;
IER &= MINT8; // Set "global" priority
PieCtrlRegs.PIEIER6.all &= MG81; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER8.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER8_2 (use MINT8 and MG82 masks):
#if (G82PL != 0)
interrupt void I2CINT2A_ISR(void) // I2C-A
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all;
IER |= M_INT8;
IER &= MINT8; // Set "global" priority
PieCtrlRegs.PIEIER8.all &= MG82; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER8.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER8_5 (use MINT8 and MG85 masks):
#if (G85PL != 0)
interrupt void SCIRXINTC_ISR(void) // SCI-C
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all;
IER |= M_INT8;
IER &= MINT8; // Set "global" priority
PieCtrlRegs.PIEIER6.all &= MG85; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER8.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER8_6 (use MINT8 and MG86 masks):
#if (G82PL != 0)
interrupt void SCITXINTC_ISR(void) // SCI-C
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all;
IER |= M_INT8;
IER &= MINT8; // Set "global" priority
PieCtrlRegs.PIEIER8.all &= MG86; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER8.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// -----------------------------------------------------------
// PIE Group 9 - MUXed into CPU INT9
// -----------------------------------------------------------
// Connected to PIEIER9_1 (use MINT9 and MG91 masks):
#if (G91PL != 0)
interrupt void SCIRXINTA_ISR(void) // SCI-A
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
IER |= M_INT9;
IER &= MINT9; // Set "global" priority
PieCtrlRegs.PIEIER9.all &= MG91; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER9.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER9_2 (use MINT9 and MG92 masks):
#if (G92PL != 0)
interrupt void SCITXINTA_ISR(void) // SCI-A
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
IER |= M_INT9;
IER &= MINT9; // Set "global" priority
PieCtrlRegs.PIEIER9.all &= MG92; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER9.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER9_3 (use MINT9 and MG93 masks):
#if (G93PL != 0)
interrupt void SCIRXINTB_ISR(void) // SCI-B
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
IER |= M_INT9;
IER &= MINT9; // Set "global" priority
PieCtrlRegs.PIEIER9.all &= MG93; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER9.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER9_4 (use MINT9 and MG94 masks):
#if (G94PL != 0)
interrupt void SCITXINTB_ISR(void) // SCI-B
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
IER |= M_INT9;
IER &= MINT9; // Set "global" priority
PieCtrlRegs.PIEIER9.all &= MG94; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER9.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER9_5 (use MINT9 and MG95 masks):
#if (G95PL != 0)
interrupt void ECAN0INTA_ISR(void) // eCAN-A
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
IER |= M_INT9;
IER &= MINT9; // Set "global" priority
PieCtrlRegs.PIEIER9.all &= MG95; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER9.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER9_6 (use MINT9 and MG96 masks):
#if (G96PL != 0)
interrupt void ECAN1INTA_ISR(void) // eCAN-A
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
IER |= M_INT9;
IER &= MINT9; // Set "global" priority
PieCtrlRegs.PIEIER9.all &= MG96; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER9.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER9_7 (use MINT9 and MG97 masks):
#if (G97PL != 0)
interrupt void ECAN0INTB_ISR(void) // eCAN-B
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
IER |= M_INT9;
IER &= MINT9; // Set "global" priority
PieCtrlRegs.PIEIER9.all &= MG97; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER9.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER9_8 (use MINT9 and MG98 masks):
#if (G98PL != 0)
interrupt void ECAN1INTB_ISR(void) // eCAN-B
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
IER |= M_INT9;
IER &= MINT9; // Set "global" priority
PieCtrlRegs.PIEIER9.all &= MG98; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER9.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// -----------------------------------------------------------
// PIE Group 10 - MUXed into CPU INT10
// -----------------------------------------------------------
// -----------------------------------------------------------
// PIE Group 11 - MUXed into CPU INT11
// -----------------------------------------------------------
// -----------------------------------------------------------
// PIE Group 12 - MUXed into CPU INT12
// -----------------------------------------------------------
// Connected to PIEIER9_1 (use MINT12 and MG121 masks):
#if (G121PL != 0)
interrupt void XINT3_ISR(void)
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
IER |= M_INT12;
IER &= MINT12; // Set "global" priority
PieCtrlRegs.PIEIER12.all &= MG121; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER12.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER12_2 (use MINT12 and MG122 masks):
#if (G122PL != 0)
interrupt void XINT4_ISR(void)
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
IER |= M_INT12;
IER &= MINT12; // Set "global" priority
PieCtrlRegs.PIEIER12.all &= MG122; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER12.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER12_3 (use MINT12 and MG123 masks):
#if (G123PL != 0)
interrupt void XINT5_ISR(void) // SCI-B
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
IER |= M_INT12;
IER &= MINT12; // Set "global" priority
PieCtrlRegs.PIEIER12.all &= MG123; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER12.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER12_4 (use MINT12 and MG124 masks):
#if (G124PL != 0)
interrupt void XINT6_ISR(void) // SCI-B
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
IER |= M_INT12;
IER &= MINT12; // Set "global" priority
PieCtrlRegs.PIEIER12.all &= MG124; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER12.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER12_5 (use MINT12 and MG125 masks):
#if (G125PL != 0)
interrupt void XINT7_ISR(void) // eCAN-A
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
IER |= M_INT12;
IER &= MINT12; // Set "global" priority
PieCtrlRegs.PIEIER12.all &= MG125; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER12.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER12_7 (use MINT12 and MG127 masks):
#if (G127PL != 0)
interrupt void LVF_ISR(void) // FPU
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
IER |= M_INT12;
IER &= MINT12; // Set "global" priority
PieCtrlRegs.PIEIER12.all &= MG127; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER12.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER12_8 (use MINT12 and MG128 masks):
#if (G128PL != 0)
interrupt void LUF_ISR(void) // FPU
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
IER |= M_INT12;
IER &= MINT12; // Set "global" priority
PieCtrlRegs.PIEIER12.all &= MG128; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER12.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
//---------------------------------------------------------------------------
// Catch All Default ISRs:
//
interrupt void PIE_RESERVED(void) // Reserved space. For test.
{
asm (" ESTOP0");
for(;;);
}
interrupt void INT_NOTUSED_ISR(void) // Reserved space. For test.
{
asm (" ESTOP0");
for(;;);
}
interrupt void rsvd_ISR(void) // For test
{
asm (" ESTOP0");
for(;;);
}
//===========================================================================
// No more.
//===========================================================================

511
v120/DSP2833x_common/source/DSP2833x_SWPrioritizedPieVect.c Normal file
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// TI File $Revision: /main/2 $
// Checkin $Date: April 4, 2007 14:25:31 $
//###########################################################################
//
// FILE: DSP2833x_SWPiroritizedPieVect.c
//
// TITLE: DSP2833x Devices SW Prioritized PIE Vector Table Initialization.
//
//###########################################################################
//
// Original Source by A.T.
//
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
#include "DSP2833x_SWPrioritizedIsrLevels.h"
const struct PIE_VECT_TABLE PieVectTableInit = {
PIE_RESERVED, // Reserved space
PIE_RESERVED, // reserved
PIE_RESERVED, // reserved
PIE_RESERVED, // reserved
PIE_RESERVED, // reserved
PIE_RESERVED, // reserved
PIE_RESERVED, // reserved
PIE_RESERVED, // reserved
PIE_RESERVED, // reserved
PIE_RESERVED, // reserved
PIE_RESERVED, // reserved
PIE_RESERVED, // reserved
PIE_RESERVED, // reserved
// Non-Peripheral Interrupts:
#if (INT13PL != 0)
INT13_ISR, // XINT13
#else
INT_NOTUSED_ISR,
#endif
#if (INT14PL != 0)
INT14_ISR, // CPU-Timer2
#else
INT_NOTUSED_ISR,
#endif
#if (INT15PL != 0)
DATALOG_ISR, // Datalogging interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (INT16PL != 0)
RTOSINT_ISR, // RTOS interrupt
#else
INT_NOTUSED_ISR,
#endif
rsvd_ISR, // reserved interrupt
NMI_ISR, // Non-maskable interrupt
ILLEGAL_ISR, // Illegal operation TRAP
USER1_ISR, // User Defined trap 1
USER2_ISR, // User Defined trap 2
USER3_ISR, // User Defined trap 3
USER4_ISR, // User Defined trap 4
USER5_ISR, // User Defined trap 5
USER6_ISR, // User Defined trap 6
USER7_ISR, // User Defined trap 7
USER8_ISR, // User Defined trap 8
USER9_ISR, // User Defined trap 9
USER10_ISR, // User Defined trap 10
USER11_ISR, // User Defined trap 11
USER12_ISR, // User Defined trap 12
// Group 1 PIE Vectors:
#if (G11PL != 0)
SEQ1INT_ISR, // ADC
#else
INT_NOTUSED_ISR,
#endif
#if (G12PL != 0)
SEQ2INT_ISR, // ADC
#else
INT_NOTUSED_ISR,
#endif
rsvd_ISR,
#if (G14PL != 0)
XINT1_ISR, // External
#else
INT_NOTUSED_ISR,
#endif
#if (G15PL != 0)
XINT2_ISR, // External
#else
INT_NOTUSED_ISR,
#endif
#if (G16PL != 0)
ADCINT_ISR, // ADC
#else
INT_NOTUSED_ISR,
#endif
#if (G17PL != 0)
TINT0_ISR, // Timer 0
#else
INT_NOTUSED_ISR,
#endif
#if (G18PL != 0)
WAKEINT_ISR, // WD & Low Power
#else
INT_NOTUSED_ISR,
#endif
// Group 2 PIE Vectors:
#if (G21PL != 0)
EPWM1_TZINT_ISR, // ePWM1 Trip Zone
#else
INT_NOTUSED_ISR,
#endif
#if (G22PL != 0)
EPWM2_TZINT_ISR, // ePWM2 Trip Zone
#else
INT_NOTUSED_ISR,
#endif
#if (G23PL != 0)
EPWM3_TZINT_ISR, // ePWM3 Trip Zone
#else
INT_NOTUSED_ISR,
#endif
#if (G24PL != 0)
EPWM4_TZINT_ISR, // ePWM4 Trip Zone
#else
INT_NOTUSED_ISR,
#endif
#if (G25PL != 0)
EPWM5_TZINT_ISR, // ePWM5 Trip Zone
#else
INT_NOTUSED_ISR,
#endif
#if (G26PL != 0)
EPWM6_TZINT_ISR, // ePWM6 Trip Zone
#else
INT_NOTUSED_ISR,
#endif
rsvd_ISR,
rsvd_ISR,
// Group 3 PIE Vectors:
#if (G31PL != 0)
EPWM1_INT_ISR, // ePWM1 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G32PL != 0)
EPWM2_INT_ISR, // ePWM2 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G33PL != 0)
EPWM3_INT_ISR, // ePWM3 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G34PL != 0)
EPWM4_INT_ISR, // ePWM4 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G35PL != 0)
EPWM5_INT_ISR, // ePWM5 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G36PL != 0)
EPWM6_INT_ISR, // ePWM6 Interrupt
#else
INT_NOTUSED_ISR,
#endif
rsvd_ISR,
rsvd_ISR,
// Group 4 PIE Vectors:
#if (G41PL != 0)
ECAP1_INT_ISR, // eCAP1 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G42PL != 0)
ECAP2_INT_ISR, // eCAP2 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G43PL != 0)
ECAP3_INT_ISR, // eCAP3 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G44PL != 0)
ECAP4_INT_ISR, // eCAP4 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G45PL != 0)
ECAP5_INT_ISR, // eCAP5 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G46PL != 0)
ECAP6_INT_ISR, // eCAP6 Interrupt
#else
INT_NOTUSED_ISR,
#endif
rsvd_ISR,
rsvd_ISR,
// Group 5 PIE Vectors:
#if (G51PL != 0)
EQEP1_INT_ISR, // eQEP1 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G52PL != 0)
EQEP2_INT_ISR, // eQEP2 Interrupt
#else
INT_NOTUSED_ISR,
#endif
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
// Group 6 PIE Vectors:
#if (G61PL != 0)
SPIRXINTA_ISR, // SPI-A
#else
INT_NOTUSED_ISR,
#endif
#if (G62PL != 0)
SPITXINTA_ISR, // SPI-A
#else
INT_NOTUSED_ISR,
#endif
#if (G63PL != 0)
MRINTB_ISR, // McBSP-B
#else
INT_NOTUSED_ISR,
#endif
#if (G64PL != 0)
MXINTB_ISR, // McBSP-B
#else
INT_NOTUSED_ISR,
#endif
#if (G65PL != 0)
MRINTA_ISR, // McBSP-A
#else
INT_NOTUSED_ISR,
#endif
#if (G66PL != 0)
MXINTA_ISR, // McBSP-A
#else
INT_NOTUSED_ISR,
#endif
rsvd_ISR,
rsvd_ISR,
// Group 7 PIE Vectors:
#if (G71PL != 0)
DINTCH1_ISR, // DMA-Channel 1 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G72PL != 0)
DINTCH2_ISR, // DMA-Channel 2 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G73PL != 0)
DINTCH3_ISR, // DMA-Channel 3 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G74PL != 0)
DINTCH4_ISR, // DMA-Channel 4 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G75PL != 0)
DINTCH5_ISR, // DMA-Channel 5 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G76PL != 0)
DINTCH6_ISR, // DMA-Channel 6 Interrupt
#else
INT_NOTUSED_ISR,
#endif
rsvd_ISR,
rsvd_ISR,
// Group 8 PIE Vectors:
#if (G81PL != 0)
I2CINT1A_ISR, // I2C-A
#else
INT_NOTUSED_ISR,
#endif
#if (G82PL != 0)
I2CINT2A_ISR, // I2C-A
#else
INT_NOTUSED_ISR,
#endif
rsvd_ISR,
rsvd_ISR,
#if (G85PL != 0)
SCIRXINTC_ISR, // SCI-C
#else
INT_NOTUSED_ISR,
#endif
#if (G86PL != 0)
SCITXINTC_ISR, // SCI-C
#else
INT_NOTUSED_ISR,
#endif
rsvd_ISR,
rsvd_ISR,
// Group 9 PIE Vectors:
#if (G91PL != 0)
SCIRXINTA_ISR, // SCI-A
#else
INT_NOTUSED_ISR,
#endif
#if (G92PL != 0)
SCITXINTA_ISR, // SCI-A
#else
INT_NOTUSED_ISR,
#endif
#if (G93PL != 0)
SCIRXINTB_ISR, // SCI-B
#else
INT_NOTUSED_ISR,
#endif
#if (G94PL != 0)
SCITXINTB_ISR, // SCI-B
#else
INT_NOTUSED_ISR,
#endif
#if (G95PL != 0)
ECAN0INTA_ISR, // eCAN-A
#else
INT_NOTUSED_ISR,
#endif
#if (G96PL != 0)
ECAN1INTA_ISR, // eCAN-A
#else
INT_NOTUSED_ISR,
#endif
#if (G97PL != 0)
ECAN0INTB_ISR, // eCAN-B
#else
INT_NOTUSED_ISR,
#endif
#if (G98PL != 0)
ECAN1INTB_ISR, // eCAN-B
#else
INT_NOTUSED_ISR,
#endif
// Group 10 PIE Vectors
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
// Group 11 PIE Vectors
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
// Group 12 PIE Vectors
#if (G121PL != 0)
XINT3_ISR, // External interrupt 3
#else
INT_NOTUSED_ISR,
#endif
#if (G122PL != 0)
XINT4_ISR, // External interrupt 4
#else
INT_NOTUSED_ISR,
#endif
#if (G123PL != 0)
XINT5_ISR, // External interrupt 5
#else
INT_NOTUSED_ISR,
#endif
#if (G124PL != 0)
XINT6_ISR, // External interrupt 6
#else
INT_NOTUSED_ISR,
#endif
#if (G125PL != 0)
XINT7_ISR, // External interrupt 7
#else
INT_NOTUSED_ISR,
#endif
rsvd_ISR,
#if (G127PL != 0)
LVF_ISR, // Latched overflow flag
#else
INT_NOTUSED_ISR,
#endif
#if (G128PL != 0)
LUF_ISR, // Latched underflow flag
#else
INT_NOTUSED_ISR,
#endif
};
//---------------------------------------------------------------------------
// InitPieVectTable:
//---------------------------------------------------------------------------
// This function initializes the PIE vector table to a known state.
// This function must be executed after boot time.
//
void InitPieVectTable(void)
{
int16 i;
Uint32 *Source = (void *) &PieVectTableInit;
Uint32 *Dest = (void *) &PieVectTable;
EALLOW;
for(i=0; i < 128; i++) {
*Dest++ = *Source++;
}
EDIS;
}
//===========================================================================
// No more.
//===========================================================================

415
v120/DSP2833x_common/source/DSP2833x_SysCtrl.c Normal file
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// TI File $Revision: /main/7 $
// Checkin $Date: September 20, 2007 13:30:31 $
//###########################################################################
//
// FILE: DSP2833x_SysCtrl.c
//
// TITLE: DSP2833x Device System Control Initialization & Support Functions.
//
// DESCRIPTION:
//
// Example initialization of system resources.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP2833x_Device.h" // Headerfile Include File
#include "DSP2833x_Examples.h" // Examples Include File
//#include "RS485.h"
//#include "message.h"
// Functions that will be run from RAM need to be assigned to
// a different section. This section will then be mapped to a load and
// run address using the linker cmd file.
#pragma CODE_SECTION(InitFlash, "ramfuncs");
//---------------------------------------------------------------------------
// InitSysCtrl:
//---------------------------------------------------------------------------
// This function initializes the System Control registers to a known state.
// - Disables the watchdog
// - Set the PLLCR for proper SYSCLKOUT frequency
// - Set the pre-scaler for the high and low frequency peripheral clocks
// - Enable the clocks to the peripherals
long SYSCLKOUT, LSPCLK, HSPCLK;
void InitSysCtrl(void)
{
// Disable the watchdog
DisableDog();
// Initialize the PLL control: PLLCR and DIVSEL
// DSP28_PLLCR and DSP28_DIVSEL are defined in DSP2833x_Examples.h
InitPll(DSP28_PLLCR,DSP28_DIVSEL);
// Initialize the peripheral clocks
InitPeripheralClocks();
}
//---------------------------------------------------------------------------
// Example: InitFlash:
//---------------------------------------------------------------------------
// This function initializes the Flash Control registers
// CAUTION
// This function MUST be executed out of RAM. Executing it
// out of OTP/Flash will yield unpredictable results
void InitFlash(void)
{
EALLOW;
//Enable Flash Pipeline mode to improve performance
//of code executed from Flash.
FlashRegs.FOPT.bit.ENPIPE = 1;
// CAUTION
//Minimum waitstates required for the flash operating
//at a given CPU rate must be characterized by TI.
//Refer to the datasheet for the latest information.
#if CPU_FRQ_150MHZ
//Set the Paged Waitstate for the Flash
FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5;
//Set the Random Waitstate for the Flash
FlashRegs.FBANKWAIT.bit.RANDWAIT = 5;
//Set the Waitstate for the OTP
FlashRegs.FOTPWAIT.bit.OTPWAIT = 8;
#endif
#if CPU_FRQ_100MHZ
//Set the Paged Waitstate for the Flash
FlashRegs.FBANKWAIT.bit.PAGEWAIT = 3;
//Set the Random Waitstate for the Flash
FlashRegs.FBANKWAIT.bit.RANDWAIT = 3;
//Set the Waitstate for the OTP
FlashRegs.FOTPWAIT.bit.OTPWAIT = 5;
#endif
// CAUTION
//ONLY THE DEFAULT VALUE FOR THESE 2 REGISTERS SHOULD BE USED
FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF;
FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF;
EDIS;
//Force a pipeline flush to ensure that the write to
//the last register configured occurs before returning.
asm(" RPT #7 || NOP");
}
//---------------------------------------------------------------------------
// Example: ServiceDog:
//---------------------------------------------------------------------------
// This function resets the watchdog timer.
// Enable this function for using ServiceDog in the application
void ServiceDog(void)
{
if(SysCtrlRegs.PLLCR.bit.DIV == DSP28_PLLCR)
if(SysCtrlRegs.PLLSTS.bit.DIVSEL == DSP28_DIVSEL)
{
EALLOW;
SysCtrlRegs.WDKEY = 0x0055;
SysCtrlRegs.WDKEY = 0x00AA;
EDIS;
return;
} }
//---------------------------------------------------------------------------
// Example: DisableDog:
//---------------------------------------------------------------------------
// This function disables the watchdog timer.
void DisableDog(void)
{
EALLOW;
SysCtrlRegs.WDCR= 0x0068;
EDIS;
}
//---------------------------------------------------------------------------
// Example: InitPll:
//---------------------------------------------------------------------------
// This function initializes the PLLCR register.
void InitPll(Uint16 divval, Uint16 divsel)
{
long clkVal;
// Make sure the PLL is not running in limp mode
if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0)
{
// Missing external clock has been detected
// Replace this line with a call to an appropriate
// SystemShutdown(); function.
asm(" ESTOP0");
}
// DIVSEL MUST be 0 before PLLCR can be changed from
// 0x0000. It is set to 0 by an external reset XRSn
// This puts us in 1/4
if (SysCtrlRegs.PLLSTS.bit.DIVSEL != 0)
{
EALLOW;
SysCtrlRegs.PLLSTS.bit.DIVSEL = 0;
EDIS;
}
// Change the PLLCR
// if (SysCtrlRegs.PLLCR.bit.DIV != val)
{
EALLOW;
// Before setting PLLCR turn off missing clock detect logic
SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1;
SysCtrlRegs.PLLCR.bit.DIV = divval;
EDIS;
clkVal = (divval)?divval:1;
clkVal = XCLKIN * clkVal;
// Optional: Wait for PLL to lock.
// During this time the CPU will switch to OSCCLK/2 until
// the PLL is stable. Once the PLL is stable the CPU will
// switch to the new PLL value.
//
// This time-to-lock is monitored by a PLL lock counter.
//
// Code is not required to sit and wait for the PLL to lock.
// However, if the code does anything that is timing critical,
// and requires the correct clock be locked, then it is best to
// wait until this switching has completed.
// Wait for the PLL lock bit to be set.
// The watchdog should be disabled before this loop, or fed within
// the loop via ServiceDog().
// Uncomment to disable the watchdog
DisableDog();
while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1)
{
// Uncomment to service the watchdog
// ServiceDog();
}
EALLOW;
SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0;
EDIS;
}
// If switching to 1/2
if((divsel == 1)||(divsel == 2))
{
EALLOW;
SysCtrlRegs.PLLSTS.bit.DIVSEL = divsel;
EDIS;
}
if(divsel == 0) clkVal /= 4;
if(divsel == 1) clkVal /= 4;
if(divsel == 2) clkVal /= 2;
// If switching to 1/1
// * First go to 1/2 and let the power settle
// The time required will depend on the system, this is only an example
// * Then switch to 1/1
if((divval == 0) && (divsel == 3))
{
EALLOW;
SysCtrlRegs.PLLSTS.bit.DIVSEL = 2;
DELAY_US(50L);
// pause_us(50L);
SysCtrlRegs.PLLSTS.bit.DIVSEL = 3;
EDIS;
}
SYSCLKOUT = clkVal;
}
//--------------------------------------------------------------------------
// Example: InitPeripheralClocks:
//---------------------------------------------------------------------------
// This function initializes the clocks to the peripheral modules.
// First the high and low clock prescalers are set
// Second the clocks are enabled to each peripheral.
// To reduce power, leave clocks to unused peripherals disabled
//
// Note: If a peripherals clock is not enabled then you cannot
// read or write to the registers for that peripheral
void InitPeripheralClocks(void)
{
long Val;
EALLOW;
// HISPCP/LOSPCP prescale register settings, normally it will be set to default values
#if CLKMULT == 0
SysCtrlRegs.HISPCP.all = 0x0000;
#endif
#if CLKMULT == 1
SysCtrlRegs.HISPCP.all = 0x0000;
#endif
#if CLKMULT == 2
SysCtrlRegs.HISPCP.all = 0x0001;
#endif
#if CLKMULT == 3
SysCtrlRegs.HISPCP.all = 0x0002;
#endif
#if CLKMULT == 4
SysCtrlRegs.HISPCP.all = 0x0002;
#endif
#if CLKMULT == 5
SysCtrlRegs.HISPCP.all = 0x0003;
#endif
SysCtrlRegs.LOSPCP.all = 0x0000;
Val = (SysCtrlRegs.HISPCP.all)?
SysCtrlRegs.HISPCP.all*2 : 1;
Val = SYSCLKOUT / Val;
HSPCLK = Val;
Val = (SysCtrlRegs.LOSPCP.all)?
SysCtrlRegs.LOSPCP.all*2 : 1;
Val = SYSCLKOUT / Val;
LSPCLK = Val;
// XCLKOUT to SYSCLKOUT ratio. By default XCLKOUT = 1/4 SYSCLKOUT
// XTIMCLK = SYSCLKOUT/2
XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
// XCLKOUT = XTIMCLK/2
XintfRegs.XINTCNF2.bit.CLKMODE = 1;
// Enable XCLKOUT
XintfRegs.XINTCNF2.bit.CLKOFF = 0;
// Peripheral clock enables set for the selected peripherals.
// If you are not using a peripheral leave the clock off
// to save on power.
//
// Note: not all peripherals are available on all 2833x derivates.
// Refer to the datasheet for your particular device.
//
// This function is not written to be an example of efficient code.
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // ADC
// *IMPORTANT*
// The ADC_cal function, which copies the ADC calibration values from TI reserved
// OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs automatically in the
// Boot ROM. If the boot ROM code is bypassed during the debug process, the
// following function MUST be called for the ADC to function according
// to specification. The clocks to the ADC MUST be enabled before calling this
// function.
// See the device data manual and/or the ADC Reference
// Manual for more information.
ADC_cal();
SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 1; // I2C
SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 1; // SCI-A
SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 1; // SCI-B
SysCtrlRegs.PCLKCR0.bit.SCICENCLK = 1; // SCI-C
SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 1; // SPI-A
SysCtrlRegs.PCLKCR0.bit.MCBSPAENCLK = 1; // McBSP-A
SysCtrlRegs.PCLKCR0.bit.MCBSPBENCLK = 1; // McBSP-B
SysCtrlRegs.PCLKCR0.bit.ECANAENCLK=1; // eCAN-A
SysCtrlRegs.PCLKCR0.bit.ECANBENCLK=1; // eCAN-B
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the ePWM
SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1; // ePWM1
SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1; // ePWM2
SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1; // ePWM3
SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1; // ePWM4
SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1; // ePWM5
SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 1; // ePWM6
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the ePWM
SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 1; // eCAP3
SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 1; // eCAP4
SysCtrlRegs.PCLKCR1.bit.ECAP5ENCLK = 1; // eCAP5
SysCtrlRegs.PCLKCR1.bit.ECAP6ENCLK = 1; // eCAP6
SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 1; // eCAP1
SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 1; // eCAP2
SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 1; // eQEP1
SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 1; // eQEP2
SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 1; // CPU Timer 0
SysCtrlRegs.PCLKCR3.bit.CPUTIMER1ENCLK = 1; // CPU Timer 1
SysCtrlRegs.PCLKCR3.bit.CPUTIMER2ENCLK = 1; // CPU Timer 2
SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1; // DMA Clock
SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; // XTIMCLK
SysCtrlRegs.PCLKCR3.bit.GPIOINENCLK = 1; // GPIO input clock
EDIS;
}
//---------------------------------------------------------------------------
// Example: CsmUnlock:
//---------------------------------------------------------------------------
// This function unlocks the CSM. User must replace 0xFFFF's with current
// password for the DSP. Returns 1 if unlock is successful.
#define STATUS_FAIL 0
#define STATUS_SUCCESS 1
Uint16 CsmUnlock()
{
volatile Uint16 temp;
// Load the key registers with the current password. The 0xFFFF's are dummy
// passwords. User should replace them with the correct password for the DSP.
EALLOW;
CsmRegs.KEY0 = 0xFFFF;
CsmRegs.KEY1 = 0xFFFF;
CsmRegs.KEY2 = 0xFFFF;
CsmRegs.KEY3 = 0xFFFF;
CsmRegs.KEY4 = 0xFFFF;
CsmRegs.KEY5 = 0xFFFF;
CsmRegs.KEY6 = 0xFFFF;
CsmRegs.KEY7 = 0xFFFF;
EDIS;
// Perform a dummy read of the password locations
// if they match the key values, the CSM will unlock
temp = CsmPwl.PSWD0;
temp = CsmPwl.PSWD1;
temp = CsmPwl.PSWD2;
temp = CsmPwl.PSWD3;
temp = CsmPwl.PSWD4;
temp = CsmPwl.PSWD5;
temp = CsmPwl.PSWD6;
temp = CsmPwl.PSWD7;
// If the CSM unlocked, return succes, otherwise return
// failure.
if (CsmRegs.CSMSCR.bit.SECURE == 0) return STATUS_SUCCESS;
else return STATUS_FAIL;
}
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/5 $
// Checkin $Date: August 16, 2007 11:06:26 $
//###########################################################################
//
// FILE: DSP2833x_Xintf.c
//
// TITLE: DSP2833x Device External Interface Init & Support Functions.
//
// DESCRIPTION:
//
// Example initialization function for the external interface (XINTF).
// This example configures the XINTF to its default state. For an
// example of how this function being used refer to the
// examples/run_from_xintf project.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
//---------------------------------------------------------------------------
// InitXINTF:
//---------------------------------------------------------------------------
// This function initializes the External Interface the default reset state.
//
// Do not modify the timings of the XINTF while running from the XINTF. Doing
// so can yield unpredictable results
void InitXintf(void)
{
// This shows how to write to the XINTF registers. The
// values used here are the default state after reset.
// Different hardware will require a different configuration.
// For an example of an XINTF configuration used with the
// F28335 eZdsp, refer to the examples/run_from_xintf project.
// Any changes to XINTF timing should only be made by code
// running outside of the XINTF.
// All Zones---------------------------------
// Timing for all zones based on XTIMCLK = 1/2 SYSCLKOUT
EALLOW;
XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
// No write buffering
XintfRegs.XINTCNF2.bit.WRBUFF = 0;
// XCLKOUT is enabled
XintfRegs.XINTCNF2.bit.CLKOFF = 0;
// XCLKOUT = XTIMCLK/2
XintfRegs.XINTCNF2.bit.CLKMODE = 1;
// Zone 0------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING0.bit.XWRLEAD = 3;
XintfRegs.XTIMING0.bit.XWRACTIVE = 7;
XintfRegs.XTIMING0.bit.XWRTRAIL = 3;
// Zone read timing
XintfRegs.XTIMING0.bit.XRDLEAD = 3;
XintfRegs.XTIMING0.bit.XRDACTIVE = 7;
XintfRegs.XTIMING0.bit.XRDTRAIL = 3;
// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING0.bit.X2TIMING = 1;
// Zone will sample XREADY signal
XintfRegs.XTIMING0.bit.USEREADY = 1;
XintfRegs.XTIMING0.bit.READYMODE = 1; // sample asynchronous
// Size must be either:
// 0,1 = x32 or
// 1,1 = x16 other values are reserved
XintfRegs.XTIMING0.bit.XSIZE = 3;
// Zone 6------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING6.bit.XWRLEAD = 3;
XintfRegs.XTIMING6.bit.XWRACTIVE = 7;
XintfRegs.XTIMING6.bit.XWRTRAIL = 3;
// Zone read timing
XintfRegs.XTIMING6.bit.XRDLEAD = 3;
XintfRegs.XTIMING6.bit.XRDACTIVE = 7;
XintfRegs.XTIMING6.bit.XRDTRAIL = 3;
// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING6.bit.X2TIMING = 1;
// Zone will sample XREADY signal
XintfRegs.XTIMING6.bit.USEREADY = 1;
XintfRegs.XTIMING6.bit.READYMODE = 1; // sample asynchronous
// Size must be either:
// 0,1 = x32 or
// 1,1 = x16 other values are reserved
XintfRegs.XTIMING6.bit.XSIZE = 3;
// Zone 7------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING7.bit.XWRLEAD = 3;
XintfRegs.XTIMING7.bit.XWRACTIVE = 7;
XintfRegs.XTIMING7.bit.XWRTRAIL = 3;
// Zone read timing
XintfRegs.XTIMING7.bit.XRDLEAD = 3;
XintfRegs.XTIMING7.bit.XRDACTIVE = 7;
XintfRegs.XTIMING7.bit.XRDTRAIL = 3;
// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING7.bit.X2TIMING = 1;
// Zone will sample XREADY signal
XintfRegs.XTIMING7.bit.USEREADY = 1;
XintfRegs.XTIMING7.bit.READYMODE = 1; // sample asynchronous
// Size must be either:
// 0,1 = x32 or
// 1,1 = x16 other values are reserved
XintfRegs.XTIMING7.bit.XSIZE = 3;
// Bank switching
// Assume Zone 7 is slow, so add additional BCYC cycles
// when ever switching from Zone 7 to another Zone.
// This will help avoid bus contention.
XintfRegs.XBANK.bit.BANK = 7;
XintfRegs.XBANK.bit.BCYC = 7;
EDIS;
//Force a pipeline flush to ensure that the write to
//the last register configured occurs before returning.
InitXintf16Gpio();
// InitXintf32Gpio();
asm(" RPT #7 || NOP");
}
void InitXintf32Gpio()
{
EALLOW;
GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 3; // XD31
GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 3; // XD30
GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 3; // XD29
GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 3; // XD28
GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 3; // XD27
GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 3; // XD26
GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 3; // XD25
GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 3; // XD24
GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 3; // XD23
GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 3; // XD22
GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 3; // XD21
GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 3; // XD20
GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 3; // XD19
GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 3; // XD18
GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 3; // XD17
GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 3; // XD16
GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 3; // XD31 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 3; // XD30 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 3; // XD29 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 3; // XD28 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 3; // XD27 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 3; // XD26 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // XD25 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // XD24 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // XD23 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // XD22 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // XD21 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // XD20 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // XD19 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // XD18 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // XD17 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 3; // XD16 asynchronous input
InitXintf16Gpio();
}
void InitXintf16Gpio()
{
EALLOW;
GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 3; // XD15
GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 3; // XD14
GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 3; // XD13
GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 3; // XD12
GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 3; // XD11
GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 3; // XD10
GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 3; // XD19
GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 3; // XD8
GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // XD7
GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // XD6
GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // XD5
GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // XD4
GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // XD3
GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // XD2
GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // XD1
GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // XD0
GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // XA0/XWE1n
GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 3; // XA1
GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3; // XA2
GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3; // XA3
GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 3; // XA4
GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 3; // XA5
GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 3; // XA6
GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 3; // XA7
GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 3; // XA8
GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 3; // XA9
GpioCtrlRegs.GPCMUX2.bit.GPIO82 = 3; // XA10
GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 3; // XA11
GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3; // XA12
GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3; // XA13
GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3; // XA14
GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3; // XA15
GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3; // XA16
// GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 3; // XA17
// GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 3; // XA18
// GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3; // XA19
// GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // XREADY
GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // XRNW
GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // XWE0
// GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 3; // XZCS0
GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // XZCS7
// GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // XZCS6
EDIS;
}
//===========================================================================
// No more.
//===========================================================================

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;// TI File $Revision: /main/4 $
;// Checkin $Date: July 30, 2007 10:28:57 $
;//###########################################################################
;//
;// FILE: DSP2833x_usDelay.asm
;//
;// TITLE: Simple delay function
;//
;// DESCRIPTION:
;//
;// This is a simple delay function that can be used to insert a specified
;// delay into code.
;//
;// This function is only accurate if executed from internal zero-waitstate
;// SARAM. If it is executed from waitstate memory then the delay will be
;// longer then specified.
;//
;// To use this function:
;//
;// 1 - update the CPU clock speed in the DSP2833x_Examples.h
;// file. For example:
;// #define CPU_RATE 6.667L // for a 150MHz CPU clock speed
;// or #define CPU_RATE 10.000L // for a 100MHz CPU clock speed
;//
;// 2 - Call this function by using the DELAY_US(A) macro
;// that is defined in the DSP2833x_Examples.h file. This macro
;// will convert the number of microseconds specified
;// into a loop count for use with this function.
;// This count will be based on the CPU frequency you specify.
;//
;// 3 - For the most accurate delay
;// - Execute this function in 0 waitstate RAM.
;// - Disable interrupts before calling the function
;// If you do not disable interrupts, then think of
;// this as an "at least" delay function as the actual
;// delay may be longer.
;//
;// The C assembly call from the DELAY_US(time) macro will
;// look as follows:
;//
;// extern void Delay(long LoopCount);
;//
;// MOV AL,#LowLoopCount
;// MOV AH,#HighLoopCount
;// LCR _Delay
;//
;// Or as follows (if count is less then 16-bits):
;//
;// MOV ACC,#LoopCount
;// LCR _Delay
;//
;//
;//###########################################################################
;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
;// $Release Date: August 1, 2008 $
;//###########################################################################
.def _DSP28x_usDelay
.sect ".text"
.global __DSP28x_usDelay
_DSP28x_usDelay:
SUB ACC,#1
BF _DSP28x_usDelay,GEQ ;; Loop if ACC >= 0
LRETR
;There is a 9/10 cycle overhead and each loop
;takes five cycles. The LoopCount is given by
;the following formula:
; DELAY_CPU_CYCLES = 9 + 5*LoopCount
; LoopCount = (DELAY_CPU_CYCLES - 9) / 5
; The macro DELAY_US(A) performs this calculation for you
;
;//===========================================================================
;// End of file.
;//===========================================================================