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Dimas
2026-07-09 14:50:52 +03:00
parent 88ddb37225
commit fc2788881f
66 changed files with 19517 additions and 237 deletions
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164
v120/DSP2833x_common/include/DSP2833x_EPwm_defines.h Normal file
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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:45:39 $
//###########################################################################
//
// FILE: DSP2833x_EPwm_defines.h
//
// TITLE: #defines used in ePWM examples examples
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_EPWM_DEFINES_H
#define DSP2833x_EPWM_DEFINES_H
#ifdef __cplusplus
extern "C" {
#endif
// TBCTL (Time-Base Control)
//==========================
// CTRMODE bits
#define TB_COUNT_UP 0x0
#define TB_COUNT_DOWN 0x1
#define TB_COUNT_UPDOWN 0x2
#define TB_FREEZE 0x3
// PHSEN bit
#define TB_DISABLE 0x0
#define TB_ENABLE 0x1
// PRDLD bit
#define TB_SHADOW 0x0
#define TB_IMMEDIATE 0x1
// SYNCOSEL bits
#define TB_SYNC_IN 0x0
#define TB_CTR_ZERO 0x1
#define TB_CTR_CMPB 0x2
#define TB_SYNC_DISABLE 0x3
// HSPCLKDIV and CLKDIV bits
#define TB_DIV1 0x0
#define TB_DIV2 0x1
#define TB_DIV4 0x2
// PHSDIR bit
#define TB_DOWN 0x0
#define TB_UP 0x1
// CMPCTL (Compare Control)
//==========================
// LOADAMODE and LOADBMODE bits
#define CC_CTR_ZERO 0x0
#define CC_CTR_PRD 0x1
#define CC_CTR_ZERO_PRD 0x2
#define CC_LD_DISABLE 0x3
// SHDWAMODE and SHDWBMODE bits
#define CC_SHADOW 0x0
#define CC_IMMEDIATE 0x1
// AQCTLA and AQCTLB (Action Qualifier Control)
//=============================================
// ZRO, PRD, CAU, CAD, CBU, CBD bits
#define AQ_NO_ACTION 0x0
#define AQ_CLEAR 0x1
#define AQ_SET 0x2
#define AQ_TOGGLE 0x3
// DBCTL (Dead-Band Control)
//==========================
// OUT MODE bits
#define DB_DISABLE 0x0
#define DBA_ENABLE 0x1
#define DBB_ENABLE 0x2
#define DB_FULL_ENABLE 0x3
// POLSEL bits
#define DB_ACTV_HI 0x0
#define DB_ACTV_LOC 0x1
#define DB_ACTV_HIC 0x2
#define DB_ACTV_LO 0x3
// IN MODE
#define DBA_ALL 0x0
#define DBB_RED_DBA_FED 0x1
#define DBA_RED_DBB_FED 0x2
#define DBB_ALL 0x3
// CHPCTL (chopper control)
//==========================
// CHPEN bit
#define CHP_DISABLE 0x0
#define CHP_ENABLE 0x1
// CHPFREQ bits
#define CHP_DIV1 0x0
#define CHP_DIV2 0x1
#define CHP_DIV3 0x2
#define CHP_DIV4 0x3
#define CHP_DIV5 0x4
#define CHP_DIV6 0x5
#define CHP_DIV7 0x6
#define CHP_DIV8 0x7
// CHPDUTY bits
#define CHP1_8TH 0x0
#define CHP2_8TH 0x1
#define CHP3_8TH 0x2
#define CHP4_8TH 0x3
#define CHP5_8TH 0x4
#define CHP6_8TH 0x5
#define CHP7_8TH 0x6
// TZSEL (Trip Zone Select)
//==========================
// CBCn and OSHTn bits
#define TZ_DISABLE 0x0
#define TZ_ENABLE 0x1
// TZCTL (Trip Zone Control)
//==========================
// TZA and TZB bits
#define TZ_HIZ 0x0
#define TZ_FORCE_HI 0x1
#define TZ_FORCE_LO 0x2
#define TZ_NO_CHANGE 0x3
// ETSEL (Event Trigger Select)
//=============================
#define ET_CTR_ZERO 0x1
#define ET_CTR_PRD 0x2
#define ET_CTRU_CMPA 0x4
#define ET_CTRD_CMPA 0x5
#define ET_CTRU_CMPB 0x6
#define ET_CTRD_CMPB 0x7
// ETPS (Event Trigger Pre-scale)
//===============================
// INTPRD, SOCAPRD, SOCBPRD bits
#define ET_DISABLE 0x0
#define ET_1ST 0x1
#define ET_2ND 0x2
#define ET_3RD 0x3
//--------------------------------
// HRPWM (High Resolution PWM)
//================================
// HRCNFG
#define HR_Disable 0x0
#define HR_REP 0x1
#define HR_FEP 0x2
#define HR_BEP 0x3
#define HR_CMP 0x0
#define HR_PHS 0x1
#define HR_CTR_ZERO 0x0
#define HR_CTR_PRD 0x1
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // - end of DSP2833x_EPWM_DEFINES_H
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/9 $
// Checkin $Date: July 2, 2008 14:31:12 $
//###########################################################################
//
// FILE: DSP2833x_Examples.h
//
// TITLE: DSP2833x Device Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_EXAMPLES_H
#define DSP2833x_EXAMPLES_H
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------------------------
Specify the PLL control register (PLLCR) and divide select (DIVSEL) value.
-----------------------------------------------------------------------------*/
//#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT
//#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT
#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT
//#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT
#define DSP28_PLLCR CLKMULT*2
//#define DSP28_PLLCR 10
//#define DSP28_PLLCR 9
//#define DSP28_PLLCR 8
//#define DSP28_PLLCR 7
//#define DSP28_PLLCR 6
//#define DSP28_PLLCR 5
//#define DSP28_PLLCR 4
//#define DSP28_PLLCR 3
//#define DSP28_PLLCR 2
//#define DSP28_PLLCR 1
//#define DSP28_PLLCR 0 // PLL is bypassed in this mode
//----------------------------------------------------------------------------
/*-----------------------------------------------------------------------------
Specify the clock rate of the CPU (SYSCLKOUT) in nS.
Take into account the input clock frequency and the PLL multiplier
selected in step 1.
Use one of the values provided, or define your own.
The trailing L is required tells the compiler to treat
the number as a 64-bit value.
Only one statement should be uncommented.
Example 1:150 MHz devices:
CLKIN is a 30MHz crystal.
In step 1 the user specified PLLCR = 0xA for a
150Mhz CPU clock (SYSCLKOUT = 150MHz).
In this case, the CPU_RATE will be 6.667L
Uncomment the line: #define CPU_RATE 6.667L
Example 2: 100 MHz devices:
CLKIN is a 20MHz crystal.
In step 1 the user specified PLLCR = 0xA for a
100Mhz CPU clock (SYSCLKOUT = 100MHz).
In this case, the CPU_RATE will be 10.000L
Uncomment the line: #define CPU_RATE 10.000L
-----------------------------------------------------------------------------*/
#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT)
//----------------------------------------------------------------------------
/*-----------------------------------------------------------------------------
Target device (in DSP2833x_Device.h) determines CPU frequency
(for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz
(for 28332). User does not have to change anything here.
-----------------------------------------------------------------------------*/
#if DSP28_28332 // DSP28_28332 device only
#define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq)
#define CPU_FRQ_150MHZ 0
#else
#define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334
#define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT
#endif
//---------------------------------------------------------------------------
// Include Example Header Files:
//
#include "DSP2833x_GlobalPrototypes.h" // Prototypes for global functions within the
// .c files.
#include "DSP2833x_ePwm_defines.h" // Macros used for PWM examples.
#include "DSP2833x_Dma_defines.h" // Macros used for DMA examples.
#include "DSP2833x_I2C_defines.h" // Macros used for I2C examples.
#define PARTNO_28335 0xEF
#define PARTNO_28334 0xEE
#define PARTNO_28332 0xED
#define PARTNO_28235 0xE8
#define PARTNO_28234 0xE7
#define PARTNO_28232 0xE6
// Include files not used with DSP/BIOS
#ifndef DSP28_BIOS
#include "DSP2833x_DefaultISR.h"
#endif
// DO NOT MODIFY THIS LINE.
#define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / (long double)CPU_RATE) - 9.0L) / 5.0L)
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_EXAMPLES_H definition
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/11 $
// Checkin $Date: May 12, 2008 14:30:08 $
//###########################################################################
//
// FILE: DSP2833x_GlobalPrototypes.h
//
// TITLE: Global prototypes for DSP2833x Examples
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_GLOBALPROTOTYPES_H
#define DSP2833x_GLOBALPROTOTYPES_H
#ifdef __cplusplus
extern "C" {
#endif
/*---- shared global function prototypes -----------------------------------*/
extern void InitAdc(void);
extern void DMAInitialize(void);
// DMA Channel 1
extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
extern void StartDMACH1(void);
// DMA Channel 2
extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
extern void StartDMACH2(void);
// DMA Channel 3
extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
extern void StartDMACH3(void);
// DMA Channel 4
extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
extern void StartDMACH4(void);
// DMA Channel 5
extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
extern void StartDMACH5(void);
// DMA Channel 6
extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
extern void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep);
extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
extern void StartDMACH6(void);
extern void InitPeripherals(void);
#if DSP28_ECANA
extern void InitECan(void);
extern void InitECana(void);
extern void InitECanGpio(void);
extern void InitECanaGpio(void);
#endif // endif DSP28_ECANA
#if DSP28_ECANB
extern void InitECanb(void);
extern void InitECanbGpio(void);
#endif // endif DSP28_ECANB
extern void InitECap(void);
extern void InitECapGpio(void);
extern void InitECap1Gpio(void);
extern void InitECap2Gpio(void);
#if DSP28_ECAP3
extern void InitECap3Gpio(void);
#endif // endif DSP28_ECAP3
#if DSP28_ECAP4
extern void InitECap4Gpio(void);
#endif // endif DSP28_ECAP4
#if DSP28_ECAP5
extern void InitECap5Gpio(void);
#endif // endif DSP28_ECAP5
#if DSP28_ECAP6
extern void InitECap6Gpio(void);
#endif // endif DSP28_ECAP6
extern void InitEPwm(void);
extern void InitEPwmGpio(void);
extern void InitEPwm1Gpio(void);
extern void InitEPwm2Gpio(void);
extern void InitEPwm3Gpio(void);
#if DSP28_EPWM4
extern void InitEPwm4Gpio(void);
#endif // endif DSP28_EPWM4
#if DSP28_EPWM5
extern void InitEPwm5Gpio(void);
#endif // endif DSP28_EPWM5
#if DSP28_EPWM6
extern void InitEPwm6Gpio(void);
#endif // endif DSP28_EPWM6
#if DSP28_EQEP1
extern void InitEQep(void);
extern void InitEQepGpio(void);
extern void InitEQep1Gpio(void);
#endif // if DSP28_EQEP1
#if DSP28_EQEP2
extern void InitEQep2Gpio(void);
#endif // endif DSP28_EQEP2
extern void InitGpio(void);
extern void InitI2CGpio(void);
extern void InitMcbsp(void);
extern void InitMcbspa(void);
extern void delay_loop(void);
extern void InitMcbspaGpio(void);
extern void InitMcbspa8bit(void);
extern void InitMcbspa12bit(void);
extern void InitMcbspa16bit(void);
extern void InitMcbspa20bit(void);
extern void InitMcbspa24bit(void);
extern void InitMcbspa32bit(void);
#if DSP28_MCBSPB
extern void InitMcbspb(void);
extern void InitMcbspbGpio(void);
extern void InitMcbspb8bit(void);
extern void InitMcbspb12bit(void);
extern void InitMcbspb16bit(void);
extern void InitMcbspb20bit(void);
extern void InitMcbspb24bit(void);
extern void InitMcbspb32bit(void);
#endif // endif DSP28_MCBSPB
extern void InitPieCtrl(void);
extern void InitPieVectTable(void);
extern void InitSci(void);
extern void InitSciGpio(void);
extern void InitSciaGpio(void);
#if DSP28_SCIB
extern void InitScibGpio(void);
#endif // endif DSP28_SCIB
#if DSP28_SCIC
extern void InitScicGpio(void);
#endif
extern void InitSpi(void);
extern void InitSpiGpio(void);
extern void InitSpiaGpio(void);
extern void InitSysCtrl(void);
extern void InitTzGpio(void);
extern void InitXIntrupt(void);
extern void XintfInit(void);
extern void InitXintf16Gpio();
extern void InitXintf32Gpio();
extern void InitPll(Uint16 pllcr, Uint16 clkindiv);
extern void InitPeripheralClocks(void);
extern void EnableInterrupts(void);
extern void DSP28x_usDelay(Uint32 Count);
extern void ADC_cal (void);
#define KickDog ServiceDog // For compatiblity with previous versions
extern void ServiceDog(void);
extern void DisableDog(void);
extern Uint16 CsmUnlock(void);
// DSP28_DBGIER.asm
extern void SetDBGIER(Uint16 dbgier);
// CAUTION
// This function MUST be executed out of RAM. Executing it
// out of OTP/Flash will yield unpredictable results
extern void InitFlash(void);
void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr);
//---------------------------------------------------------------------------
// External symbols created by the linker cmd file
// DSP28 examples will use these to relocate code from one LOAD location
// in either Flash or XINTF to a different RUN location in internal
// RAM
extern Uint16 RamfuncsLoadStart;
extern Uint16 RamfuncsLoadEnd;
extern Uint16 RamfuncsRunStart;
extern Uint16 XintffuncsLoadStart;
extern Uint16 XintffuncsLoadEnd;
extern Uint16 XintffuncsRunStart;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // - end of DSP2833x_GLOBALPROTOTYPES_H
//===========================================================================
// End of file.
//===========================================================================

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v120/DSP2833x_common/include/DSP2833x_I2c_defines.h Normal file
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// TI File $Revision: /main/2 $
// Checkin $Date: April 16, 2008 17:16:47 $
//###########################################################################
//
// FILE: DSP2833x_I2cExample.h
//
// TITLE: 2833x I2C Example Code Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_I2C_DEFINES_H
#define DSP2833x_I2C_DEFINES_H
//--------------------------------------------
// Defines
//--------------------------------------------
// Error Messages
#define I2C_ERROR 0xFFFF
#define I2C_ARB_LOST_ERROR 0x0001
#define I2C_NACK_ERROR 0x0002
#define I2C_BUS_BUSY_ERROR 0x1000
#define I2C_STP_NOT_READY_ERROR 0x5555
#define I2C_NO_FLAGS 0xAAAA
#define I2C_SUCCESS 0x0000
// Clear Status Flags
#define I2C_CLR_AL_BIT 0x0001
#define I2C_CLR_NACK_BIT 0x0002
#define I2C_CLR_ARDY_BIT 0x0004
#define I2C_CLR_RRDY_BIT 0x0008
#define I2C_CLR_SCD_BIT 0x0020
// Interrupt Source Messages
#define I2C_NO_ISRC 0x0000
#define I2C_ARB_ISRC 0x0001
#define I2C_NACK_ISRC 0x0002
#define I2C_ARDY_ISRC 0x0003
#define I2C_RX_ISRC 0x0004
#define I2C_TX_ISRC 0x0005
#define I2C_SCD_ISRC 0x0006
#define I2C_AAS_ISRC 0x0007
// I2CMSG structure defines
#define I2C_NO_STOP 0
#define I2C_YES_STOP 1
#define I2C_RECEIVE 0
#define I2C_TRANSMIT 1
#define I2C_MAX_BUFFER_SIZE 16
// I2C Slave State defines
#define I2C_NOTSLAVE 0
#define I2C_ADDR_AS_SLAVE 1
#define I2C_ST_MSG_READY 2
// I2C Slave Receiver messages defines
#define I2C_SND_MSG1 1
#define I2C_SND_MSG2 2
// I2C State defines
#define I2C_IDLE 0
#define I2C_SLAVE_RECEIVER 1
#define I2C_SLAVE_TRANSMITTER 2
#define I2C_MASTER_RECEIVER 3
#define I2C_MASTER_TRANSMITTER 4
// I2C Message Commands for I2CMSG struct
#define I2C_MSGSTAT_INACTIVE 0x0000
#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010
#define I2C_MSGSTAT_WRITE_BUSY 0x0011
#define I2C_MSGSTAT_SEND_NOSTOP 0x0020
#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021
#define I2C_MSGSTAT_RESTART 0x0022
#define I2C_MSGSTAT_READ_BUSY 0x0023
// Generic defines
#define I2C_TRUE 1
#define I2C_FALSE 0
#define I2C_YES 1
#define I2C_NO 0
#define I2C_DUMMY_BYTE 0
//--------------------------------------------
// Structures
//--------------------------------------------
// I2C Message Structure
struct I2CMSG {
Uint16 MsgStatus; // Word stating what state msg is in:
// I2C_MSGCMD_INACTIVE = do not send msg
// I2C_MSGCMD_BUSY = msg start has been sent,
// awaiting stop
// I2C_MSGCMD_SEND_WITHSTOP = command to send
// master trans msg complete with a stop bit
// I2C_MSGCMD_SEND_NOSTOP = command to send
// master trans msg without the stop bit
// I2C_MSGCMD_RESTART = command to send a restart
// as a master receiver with a stop bit
Uint16 SlaveAddress; // I2C address of slave msg is intended for
Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer)
Uint16 MemoryHighAddr; // EEPROM address of data associated with msg (high byte)
Uint16 MemoryLowAddr; // EEPROM address of data associated with msg (low byte)
Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; // Array holding msg data - max that
// MAX_BUFFER_SIZE can be is 16 due to
// the FIFO's
};
#endif // end of DSP2833x_I2C_DEFINES_H definition
//===========================================================================
// End of file.
//===========================================================================

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v120/DSP2833x_common/include/DSP2833x_SWPrioritizedIsrLevels.h Normal file
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v120/DSP2833x_common/source/DSP2833x_PieCtrl.c Normal file
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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:46:35 $
//###########################################################################
//
// FILE: DSP2833x_PieCtrl.c
//
// TITLE: DSP2833x Device PIE Control Register Initialization Functions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
//---------------------------------------------------------------------------
// InitPieCtrl:
//---------------------------------------------------------------------------
// This function initializes the PIE control registers to a known state.
//
void InitPieCtrl(void)
{
// Disable Interrupts at the CPU level:
DINT;
// Disable the PIE
PieCtrlRegs.PIECTRL.bit.ENPIE = 0;
// Clear all PIEIER registers:
PieCtrlRegs.PIEIER1.all = 0;
PieCtrlRegs.PIEIER2.all = 0;
PieCtrlRegs.PIEIER3.all = 0;
PieCtrlRegs.PIEIER4.all = 0;
PieCtrlRegs.PIEIER5.all = 0;
PieCtrlRegs.PIEIER6.all = 0;
PieCtrlRegs.PIEIER7.all = 0;
PieCtrlRegs.PIEIER8.all = 0;
PieCtrlRegs.PIEIER9.all = 0;
PieCtrlRegs.PIEIER10.all = 0;
PieCtrlRegs.PIEIER11.all = 0;
PieCtrlRegs.PIEIER12.all = 0;
// Clear all PIEIFR registers:
PieCtrlRegs.PIEIFR1.all = 0;
PieCtrlRegs.PIEIFR2.all = 0;
PieCtrlRegs.PIEIFR3.all = 0;
PieCtrlRegs.PIEIFR4.all = 0;
PieCtrlRegs.PIEIFR5.all = 0;
PieCtrlRegs.PIEIFR6.all = 0;
PieCtrlRegs.PIEIFR7.all = 0;
PieCtrlRegs.PIEIFR8.all = 0;
PieCtrlRegs.PIEIFR9.all = 0;
PieCtrlRegs.PIEIFR10.all = 0;
PieCtrlRegs.PIEIFR11.all = 0;
PieCtrlRegs.PIEIFR12.all = 0;
}
//---------------------------------------------------------------------------
// EnableInterrupts:
//---------------------------------------------------------------------------
// This function enables the PIE module and CPU interrupts
//
void EnableInterrupts()
{
// Enable the PIE
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
// Enables PIE to drive a pulse into the CPU
PieCtrlRegs.PIEACK.all = 0xFFFF;
// Enable Interrupts at the CPU level
EINT;
}
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:46:38 $
//###########################################################################
//
// FILE: DSP2833x_PieVect.c
//
// TITLE: DSP2833x Devices PIE Vector Table Initialization Functions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
const struct PIE_VECT_TABLE PieVectTableInit = {
PIE_RESERVED, // 0 Reserved space
PIE_RESERVED, // 1 Reserved space
PIE_RESERVED, // 2 Reserved space
PIE_RESERVED, // 3 Reserved space
PIE_RESERVED, // 4 Reserved space
PIE_RESERVED, // 5 Reserved space
PIE_RESERVED, // 6 Reserved space
PIE_RESERVED, // 7 Reserved space
PIE_RESERVED, // 8 Reserved space
PIE_RESERVED, // 9 Reserved space
PIE_RESERVED, // 10 Reserved space
PIE_RESERVED, // 11 Reserved space
PIE_RESERVED, // 12 Reserved space
// Non-Peripheral Interrupts
INT13_ISR, // XINT13 or CPU-Timer 1
INT14_ISR, // CPU-Timer2
DATALOG_ISR, // Datalogging interrupt
RTOSINT_ISR, // RTOS interrupt
EMUINT_ISR, // Emulation interrupt
NMI_ISR, // Non-maskable interrupt
ILLEGAL_ISR, // Illegal operation TRAP
USER1_ISR, // User Defined trap 1
USER2_ISR, // User Defined trap 2
USER3_ISR, // User Defined trap 3
USER4_ISR, // User Defined trap 4
USER5_ISR, // User Defined trap 5
USER6_ISR, // User Defined trap 6
USER7_ISR, // User Defined trap 7
USER8_ISR, // User Defined trap 8
USER9_ISR, // User Defined trap 9
USER10_ISR, // User Defined trap 10
USER11_ISR, // User Defined trap 11
USER12_ISR, // User Defined trap 12
// Group 1 PIE Vectors
SEQ1INT_ISR, // 1.1 ADC
SEQ2INT_ISR, // 1.2 ADC
rsvd_ISR, // 1.3
XINT1_ISR, // 1.4
XINT2_ISR, // 1.5
ADCINT_ISR, // 1.6 ADC
TINT0_ISR, // 1.7 Timer 0
WAKEINT_ISR, // 1.8 WD, Low Power
// Group 2 PIE Vectors
EPWM1_TZINT_ISR, // 2.1 EPWM-1 Trip Zone
EPWM2_TZINT_ISR, // 2.2 EPWM-2 Trip Zone
EPWM3_TZINT_ISR, // 2.3 EPWM-3 Trip Zone
EPWM4_TZINT_ISR, // 2.4 EPWM-4 Trip Zone
EPWM5_TZINT_ISR, // 2.5 EPWM-5 Trip Zone
EPWM6_TZINT_ISR, // 2.6 EPWM-6 Trip Zone
rsvd_ISR, // 2.7
rsvd_ISR, // 2.8
// Group 3 PIE Vectors
EPWM1_INT_ISR, // 3.1 EPWM-1 Interrupt
EPWM2_INT_ISR, // 3.2 EPWM-2 Interrupt
EPWM3_INT_ISR, // 3.3 EPWM-3 Interrupt
EPWM4_INT_ISR, // 3.4 EPWM-4 Interrupt
EPWM5_INT_ISR, // 3.5 EPWM-5 Interrupt
EPWM6_INT_ISR, // 3.6 EPWM-6 Interrupt
rsvd_ISR, // 3.7
rsvd_ISR, // 3.8
// Group 4 PIE Vectors
ECAP1_INT_ISR, // 4.1 ECAP-1
ECAP2_INT_ISR, // 4.2 ECAP-2
ECAP3_INT_ISR, // 4.3 ECAP-3
ECAP4_INT_ISR, // 4.4 ECAP-4
ECAP5_INT_ISR, // 4.5 ECAP-5
ECAP6_INT_ISR, // 4.6 ECAP-6
rsvd_ISR, // 4.7
rsvd_ISR, // 4.8
// Group 5 PIE Vectors
EQEP1_INT_ISR, // 5.1 EQEP-1
EQEP2_INT_ISR, // 5.2 EQEP-2
rsvd_ISR, // 5.3
rsvd_ISR, // 5.4
rsvd_ISR, // 5.5
rsvd_ISR, // 5.6
rsvd_ISR, // 5.7
rsvd_ISR, // 5.8
// Group 6 PIE Vectors
SPIRXINTA_ISR, // 6.1 SPI-A
SPITXINTA_ISR, // 6.2 SPI-A
MRINTA_ISR, // 6.3 McBSP-A
MXINTA_ISR, // 6.4 McBSP-A
MRINTB_ISR, // 6.5 McBSP-B
MXINTB_ISR, // 6.6 McBSP-B
rsvd_ISR, // 6.7
rsvd_ISR, // 6.8
// Group 7 PIE Vectors
DINTCH1_ISR, // 7.1 DMA channel 1
DINTCH2_ISR, // 7.2 DMA channel 2
DINTCH3_ISR, // 7.3 DMA channel 3
DINTCH4_ISR, // 7.4 DMA channel 4
DINTCH5_ISR, // 7.5 DMA channel 5
DINTCH6_ISR, // 7.6 DMA channel 6
rsvd_ISR, // 7.7
rsvd_ISR, // 7.8
// Group 8 PIE Vectors
I2CINT1A_ISR, // 8.1 I2C
I2CINT2A_ISR, // 8.2 I2C
rsvd_ISR, // 8.3
rsvd_ISR, // 8.4
SCIRXINTC_ISR, // 8.5 SCI-C
SCITXINTC_ISR, // 8.6 SCI-C
rsvd_ISR, // 8.7
rsvd_ISR, // 8.8
// Group 9 PIE Vectors
SCIRXINTA_ISR, // 9.1 SCI-A
SCITXINTA_ISR, // 9.2 SCI-A
SCIRXINTB_ISR, // 9.3 SCI-B
SCITXINTB_ISR, // 9.4 SCI-B
ECAN0INTA_ISR, // 9.5 eCAN-A
ECAN1INTA_ISR, // 9.6 eCAN-A
ECAN0INTB_ISR, // 9.7 eCAN-B
ECAN1INTB_ISR, // 9.8 eCAN-B
// Group 10 PIE Vectors
rsvd_ISR, // 10.1
rsvd_ISR, // 10.2
rsvd_ISR, // 10.3
rsvd_ISR, // 10.4
rsvd_ISR, // 10.5
rsvd_ISR, // 10.6
rsvd_ISR, // 10.7
rsvd_ISR, // 10.8
// Group 11 PIE Vectors
rsvd_ISR, // 11.1
rsvd_ISR, // 11.2
rsvd_ISR, // 11.3
rsvd_ISR, // 11.4
rsvd_ISR, // 11.5
rsvd_ISR, // 11.6
rsvd_ISR, // 11.7
rsvd_ISR, // 11.8
// Group 12 PIE Vectors
XINT3_ISR, // 12.1
XINT4_ISR, // 12.2
XINT5_ISR, // 12.3
XINT6_ISR, // 12.4
XINT7_ISR, // 12.5
rsvd_ISR, // 12.6
LVF_ISR, // 12.7
LUF_ISR, // 12.8
};
//---------------------------------------------------------------------------
// InitPieVectTable:
//---------------------------------------------------------------------------
// This function initializes the PIE vector table to a known state.
// This function must be executed after boot time.
//
void InitPieVectTable(void)
{
int16 i;
Uint32 *Source = (void *) &PieVectTableInit;
Uint32 *Dest = (void *) &PieVectTable;
EALLOW;
for(i=0; i < 128; i++)
*Dest++ = *Source++;
EDIS;
// Enable the PIE Vector Table
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
}
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/5 $
// Checkin $Date: January 14, 2008 11:28:12 $
//###########################################################################
//
// FILE: DSP2833x_SWPrioritizedDefaultIsr.c
//
// TITLE: DSP2833x Device Default Software Prioritized Interrupt Service Routines.
//
//###########################################################################
//
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
#include "DSP2833x_SWPrioritizedIsrLevels.h"
// Connected to INT13 of CPU (use MINT13 mask):
// Note CPU-Timer1 is reserved for TI use, however XINT13
// ISR can be used by the user.
#if (INT13PL != 0)
interrupt void INT13_ISR(void) // INT13 or CPU-Timer1
{
IER |= MINT13; // Set "global" priority
EINT;
// Insert ISR Code here
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to INT14 of CPU (use MINT14 mask):
#if (INT14PL != 0)
interrupt void INT14_ISR(void) // CPU-Timer2
{
IER |= MINT14; // Set "global" priority
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to INT15 of CPU (use MINT15 mask):
#if (INT15PL != 0)
interrupt void DATALOG_ISR(void) // Datalogging interrupt
{
IER |= MINT15; // Set "global" priority
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to INT16 of CPU (use MINT16 mask):
#if (INT16PL != 0)
interrupt void RTOSINT_ISR(void) // RTOS interrupt
{
IER |= MINT16; // Set "global" priority
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to EMUINT of CPU (non-maskable):
interrupt void EMUINT_ISR(void) // Emulation interrupt
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// Connected to NMI of CPU (non-maskable):
interrupt void NMI_ISR(void) // Non-maskable interrupt
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void ILLEGAL_ISR(void) // Illegal operation TRAP
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER1_ISR(void) // User Defined trap 1
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER2_ISR(void) // User Defined trap 2
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER3_ISR(void) // User Defined trap 3
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER4_ISR(void) // User Defined trap 4
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER5_ISR(void) // User Defined trap 5
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER6_ISR(void) // User Defined trap 6
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER7_ISR(void) // User Defined trap 7
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER8_ISR(void) // User Defined trap 8
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER9_ISR(void) // User Defined trap 9
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER10_ISR(void) // User Defined trap 10
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER11_ISR(void) // User Defined trap 11
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER12_ISR(void) // User Defined trap 12
{
EINT;
// Insert ISR Code here.......
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// -----------------------------------------------------------
// PIE Group 1 - MUXed into CPU INT1
// -----------------------------------------------------------
// Connected to PIEIER1_1 (use MINT1 and MG11 masks):
#if (G11PL != 0)
interrupt void SEQ1INT_ISR( void ) // ADC
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
IER |= M_INT1;
IER &= MINT1; // Set "global" priority
PieCtrlRegs.PIEIER1.all &= MG11; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER1.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER1_2 (use MINT1 and MG12 masks):
#if (G12PL != 0)
interrupt void SEQ2INT_ISR( void ) // ADC
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
IER |= M_INT1;
IER &= MINT1; // Set "global" priority
PieCtrlRegs.PIEIER1.all &= MG12; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER1.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER1_4 (use MINT1 and MG14 masks):
#if (G14PL != 0)
interrupt void XINT1_ISR(void)
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
IER |= MINT1; // Set "global" priority
PieCtrlRegs.PIEIER1.all &= MG14; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER1.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER1_5 (use MINT1 and MG15 masks):
#if (G15PL != 0)
interrupt void XINT2_ISR(void)
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
IER |= MINT1; // Set "global" priority
PieCtrlRegs.PIEIER1.all &= MG15; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER1.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER1_6 (use MINT1 and MG16 masks):
#if (G16PL != 0)
interrupt void ADCINT_ISR(void) // ADC
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
IER |= M_INT1;
IER &= MINT1; // Set "global" priority
PieCtrlRegs.PIEIER1.all &= MG16; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER1.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER1_7 (use MINT1 and MG17 masks):
#if (G17PL != 0)
interrupt void TINT0_ISR(void) // CPU-Timer 0
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
IER |= M_INT1;
IER &= MINT1; // Set "global" priority
PieCtrlRegs.PIEIER1.all &= MG17; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER1.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER1_8 (use MINT1 and MG18 masks):
#if (G18PL != 0)
interrupt void WAKEINT_ISR(void) // WD/LPM
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
IER |= M_INT1;
IER &= MINT1; // Set "global" priority
PieCtrlRegs.PIEIER1.all &= MG18; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER1.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// -----------------------------------------------------------
// PIE Group 2 - MUXed into CPU INT2
// -----------------------------------------------------------
// Connected to PIEIER2_1 (use MINT2 and MG21 masks):
#if (G21PL != 0)
interrupt void EPWM1_TZINT_ISR(void) // ePWM1 Trip Zone
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
IER |= M_INT2;
IER &= MINT2; // Set "global" priority
PieCtrlRegs.PIEIER2.all &= MG21; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER2.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER2_2 (use MINT2 and MG22 masks):
#if (G22PL != 0)
interrupt void EPWM2_TZINT_ISR(void) // ePWM2 Trip Zone
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
IER |= M_INT2;
IER &= MINT2; // Set "global" priority
PieCtrlRegs.PIEIER2.all &= MG22; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER2.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER2_3 (use MINT2 and MG23 masks):
#if (G23PL != 0)
interrupt void EPWM3_TZINT_ISR(void) // ePWM3 Trip Zone
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
IER |= M_INT2;
IER &= MINT2; // Set "global" priority
PieCtrlRegs.PIEIER2.all &= MG23; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER2.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER2_4 (use MINT2 and MG24 masks):
#if (G24PL != 0)
interrupt void EPWM4_TZINT_ISR(void) // ePWM4 Trip Zone
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
IER |= M_INT2;
IER &= MINT2; // Set "global" priority
PieCtrlRegs.PIEIER2.all &= MG24; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER2.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER2_5 (use MINT2 and MG25 masks):
#if (G25PL != 0)
interrupt void EPWM5_TZINT_ISR(void) // ePWM5 Trip Zone
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
IER |= M_INT2;
IER &= MINT2; // Set "global" priority
PieCtrlRegs.PIEIER2.all &= MG25; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER2.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER2_6 (use MINT2 and MG26 masks):
#if (G26PL != 0)
interrupt void EPWM6_TZINT_ISR(void) // ePWM6 Trip Zone
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
IER |= M_INT2;
IER &= MINT2; // Set "global" priority
PieCtrlRegs.PIEIER2.all &= MG26; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER2.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// -----------------------------------------------------------
// PIE Group 3 - MUXed into CPU INT3
// -----------------------------------------------------------
// Connected to PIEIER3_1 (use MINT3 and MG31 masks):
#if (G31PL != 0)
interrupt void EPWM1_INT_ISR(void) // ePWM1 Interrupt
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
IER |= M_INT3;
IER &= MINT3; // Set "global" priority
PieCtrlRegs.PIEIER3.all &= MG31; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER3.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER3_2 (use MINT3 and MG32 masks):
#if (G32PL != 0)
interrupt void EPWM2_INT_ISR(void) // ePWM2 Interrupt
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
IER |= M_INT3;
IER &= MINT3; // Set "global" priority
PieCtrlRegs.PIEIER3.all &= MG32; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER3.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER3_3 (use MINT3 and MG33 masks):
#if (G33PL != 0)
interrupt void EPWM3_INT_ISR(void) // ePWM3 Interrupt
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
IER |= M_INT3;
IER &= MINT3; // Set "global" priority
PieCtrlRegs.PIEIER3.all &= MG33; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER3.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER3_4 (use MINT3 and MG34 masks):
#if (G34PL != 0)
interrupt void EPWM4_INT_ISR(void) // ePWM4 Interrupt
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
IER |= M_INT3;
IER &= MINT3; // Set "global" priority
PieCtrlRegs.PIEIER3.all &= MG34; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER3.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER3_5 (use MINT3 and MG35 masks):
#if (G35PL != 0)
interrupt void EPWM5_INT_ISR(void) // ePWM5 Interrupt
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
IER |= M_INT3;
IER &= MINT3; // Set "global" priority
PieCtrlRegs.PIEIER3.all &= MG35; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER3.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER3_6 (use MINT3 and MG36 masks):
#if (G36PL != 0)
interrupt void EPWM6_INT_ISR(void) // ePWM6 Interrupt
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
IER |= M_INT3;
IER &= MINT3; // Set "global" priority
PieCtrlRegs.PIEIER3.all &= MG36; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER3.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// -----------------------------------------------------------
// PIE Group 4 - MUXed into CPU INT4
// -----------------------------------------------------------
// Connected to PIEIER4_1 (use MINT4 and MG41 masks):
#if (G41PL != 0)
interrupt void ECAP1_INT_ISR(void) // eCAP1 Interrupt
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
IER |= M_INT4;
IER &= MINT4; // Set "global" priority
PieCtrlRegs.PIEIER4.all &= MG41; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER4.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER4_2 (use MINT4 and MG42 masks):
#if (G42PL != 0)
interrupt void ECAP2_INT_ISR(void) // eCAP2 Interrupt
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all;
IER |= M_INT4;
IER &= MINT4; // Set "global" priority
PieCtrlRegs.PIEIER4.all &= MG42; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER4.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER4_3 (use MINT4 and MG43 masks):
#if (G43PL != 0)
interrupt void ECAP3_INT_ISR(void) // eCAP3 Interrupt
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
IER |= M_INT4;
IER &= MINT4; // Set "global" priority
PieCtrlRegs.PIEIER4.all &= MG43; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER4.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER4_4 (use MINT4 and MG44 masks):
#if (G44PL != 0)
interrupt void ECAP4_INT_ISR(void) // eCAP4 Interrupt
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
IER |= M_INT4;
IER &= MINT4; // Set "global" priority
PieCtrlRegs.PIEIER4.all &= MG44; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER4.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER4_5 (use MINT4 and MG45 masks):
#if (G45PL != 0)
interrupt void ECAP5_INT_ISR(void) // eCAP5 Interrupt
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
IER |= M_INT4;
IER &= MINT4; // Set "global" priority
PieCtrlRegs.PIEIER4.all &= MG45; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER4.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER4_6 (use MINT4 and MG46 masks):
#if (G46PL != 0)
interrupt void ECAP6_INT_ISR(void) // eCAP6 Interrupt
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
IER |= M_INT4;
IER &= MINT4; // Set "global" priority
PieCtrlRegs.PIEIER4.all &= MG46; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER4.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// -----------------------------------------------------------
// PIE Group 5 - MUXed into CPU INT5
// -----------------------------------------------------------
// Connected to PIEIER5_1 (use MINT5 and MG51 masks):
#if (G51PL != 0)
interrupt void EQEP1_INT_ISR(void) // eQEP1 Interrupt
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all;
IER |= M_INT5;
IER &= MINT5; // Set "global" priority
PieCtrlRegs.PIEIER5.all &= MG51; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER5.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER5_2 (use MINT5 and MG52 masks):
#if (G52PL != 0)
interrupt void EQEP2_INT_ISR(void) // eQEP2 Interrupt
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all;
IER |= M_INT5;
IER &= MINT5; // Set "global" priority
PieCtrlRegs.PIEIER5.all &= MG52; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER5.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// -----------------------------------------------------------
// PIE Group 6 - MUXed into CPU INT6
// -----------------------------------------------------------
// Connected to PIEIER6_1 (use MINT6 and MG61 masks):
#if (G61PL != 0)
interrupt void SPIRXINTA_ISR(void) // SPI-A
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
IER |= M_INT6;
IER &= MINT6; // Set "global" priority
PieCtrlRegs.PIEIER6.all &= MG61; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER6.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER6_2 (use MINT6 and MG62 masks):
#if (G62PL != 0)
interrupt void SPITXINTA_ISR(void) // SPI-A
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
IER |= M_INT6;
IER &= MINT6; // Set "global" priority
PieCtrlRegs.PIEIER6.all &= MG62; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER6.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER6_3 (use MINT6 and MG63 masks):
#if (G63PL != 0)
interrupt void MRINTB_ISR(void) // McBSP-B
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
IER |= M_INT6;
IER &= MINT6; // Set "global" priority
PieCtrlRegs.PIEIER6.all &= MG63; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER6.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER6_4 (use MINT6 and MG64 masks):
#if (G64PL != 0)
interrupt void MXINTB_ISR(void) // McBSP-B
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
IER |= M_INT6;
IER &= MINT6; // Set "global" priority
PieCtrlRegs.PIEIER6.all &= MG64; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER6.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER6_5 (use MINT6 and MG65 masks):
#if (G65PL != 0)
interrupt void MRINTA_ISR(void) // McBSP-A
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
IER |= M_INT6;
IER &= MINT6; // Set "global" priority
PieCtrlRegs.PIEIER6.all &= MG65; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER6.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER6_6 (use MINT6 and MG66 masks):
#if (G66PL != 0)
interrupt void MXINTA_ISR(void) // McBSP-A
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
IER |= M_INT6;
IER &= MINT6; // Set "global" priority
PieCtrlRegs.PIEIER6.all &= MG66; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER6.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// -----------------------------------------------------------
// PIE Group 7 - MUXed into CPU INT7
// -----------------------------------------------------------
// Connected to PIEIER7_1 (use MINT7 and MG71 masks):
#if (G71PL != 0)
interrupt void DINTCH1_ISR(void) // DMA
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
IER |= M_INT7;
IER &= MINT7; // Set "global" priority
PieCtrlRegs.PIEIER7.all &= MG71; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER7.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER7_2 (use MINT7 and MG72 masks):
#if (G72PL != 0)
interrupt void DINTCH2_ISR(void) // DMA
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
IER |= M_INT7;
IER &= MINT7; // Set "global" priority
PieCtrlRegs.PIEIER7.all &= MG72; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER7.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER7_3 (use MINT7 and MG73 masks):
#if (G73PL != 0)
interrupt void DINTCH3_ISR(void) // DMA
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
IER |= M_INT7;
IER &= MINT7; // Set "global" priority
PieCtrlRegs.PIEIER7.all &= MG73; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER7.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER7_4 (use MINT7 and MG74 masks):
#if (G74PL != 0)
interrupt void DINTCH4_ISR(void) // DMA
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
IER |= M_INT7;
IER &= MINT7; // Set "global" priority
PieCtrlRegs.PIEIER7.all &= MG74; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER7.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER7_5 (use MINT7 and MG75 masks):
#if (G75PL != 0)
interrupt void DINTCH5_ISR(void) // DMA
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
IER |= M_INT7;
IER &= MINT7; // Set "global" priority
PieCtrlRegs.PIEIER7.all &= MG75; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER7.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER7_6 (use MINT7 and MG76 masks):
#if (G76PL != 0)
interrupt void DINTCH6_ISR(void) // DMA
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
IER |= M_INT7;
IER &= MINT7; // Set "global" priority
PieCtrlRegs.PIEIER7.all &= MG76; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER7.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// -----------------------------------------------------------
// PIE Group 8 - MUXed into CPU INT8
// -----------------------------------------------------------
// Connected to PIEIER8_1 (use MINT8 and MG81 masks):
#if (G81PL != 0)
interrupt void I2CINT1A_ISR(void) // I2C-A
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all;
IER |= M_INT8;
IER &= MINT8; // Set "global" priority
PieCtrlRegs.PIEIER6.all &= MG81; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER8.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER8_2 (use MINT8 and MG82 masks):
#if (G82PL != 0)
interrupt void I2CINT2A_ISR(void) // I2C-A
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all;
IER |= M_INT8;
IER &= MINT8; // Set "global" priority
PieCtrlRegs.PIEIER8.all &= MG82; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER8.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER8_5 (use MINT8 and MG85 masks):
#if (G85PL != 0)
interrupt void SCIRXINTC_ISR(void) // SCI-C
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all;
IER |= M_INT8;
IER &= MINT8; // Set "global" priority
PieCtrlRegs.PIEIER6.all &= MG85; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER8.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER8_6 (use MINT8 and MG86 masks):
#if (G82PL != 0)
interrupt void SCITXINTC_ISR(void) // SCI-C
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all;
IER |= M_INT8;
IER &= MINT8; // Set "global" priority
PieCtrlRegs.PIEIER8.all &= MG86; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER8.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// -----------------------------------------------------------
// PIE Group 9 - MUXed into CPU INT9
// -----------------------------------------------------------
// Connected to PIEIER9_1 (use MINT9 and MG91 masks):
#if (G91PL != 0)
interrupt void SCIRXINTA_ISR(void) // SCI-A
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
IER |= M_INT9;
IER &= MINT9; // Set "global" priority
PieCtrlRegs.PIEIER9.all &= MG91; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER9.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER9_2 (use MINT9 and MG92 masks):
#if (G92PL != 0)
interrupt void SCITXINTA_ISR(void) // SCI-A
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
IER |= M_INT9;
IER &= MINT9; // Set "global" priority
PieCtrlRegs.PIEIER9.all &= MG92; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER9.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER9_3 (use MINT9 and MG93 masks):
#if (G93PL != 0)
interrupt void SCIRXINTB_ISR(void) // SCI-B
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
IER |= M_INT9;
IER &= MINT9; // Set "global" priority
PieCtrlRegs.PIEIER9.all &= MG93; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER9.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER9_4 (use MINT9 and MG94 masks):
#if (G94PL != 0)
interrupt void SCITXINTB_ISR(void) // SCI-B
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
IER |= M_INT9;
IER &= MINT9; // Set "global" priority
PieCtrlRegs.PIEIER9.all &= MG94; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER9.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER9_5 (use MINT9 and MG95 masks):
#if (G95PL != 0)
interrupt void ECAN0INTA_ISR(void) // eCAN-A
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
IER |= M_INT9;
IER &= MINT9; // Set "global" priority
PieCtrlRegs.PIEIER9.all &= MG95; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER9.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER9_6 (use MINT9 and MG96 masks):
#if (G96PL != 0)
interrupt void ECAN1INTA_ISR(void) // eCAN-A
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
IER |= M_INT9;
IER &= MINT9; // Set "global" priority
PieCtrlRegs.PIEIER9.all &= MG96; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER9.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER9_7 (use MINT9 and MG97 masks):
#if (G97PL != 0)
interrupt void ECAN0INTB_ISR(void) // eCAN-B
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
IER |= M_INT9;
IER &= MINT9; // Set "global" priority
PieCtrlRegs.PIEIER9.all &= MG97; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER9.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER9_8 (use MINT9 and MG98 masks):
#if (G98PL != 0)
interrupt void ECAN1INTB_ISR(void) // eCAN-B
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
IER |= M_INT9;
IER &= MINT9; // Set "global" priority
PieCtrlRegs.PIEIER9.all &= MG98; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER9.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// -----------------------------------------------------------
// PIE Group 10 - MUXed into CPU INT10
// -----------------------------------------------------------
// -----------------------------------------------------------
// PIE Group 11 - MUXed into CPU INT11
// -----------------------------------------------------------
// -----------------------------------------------------------
// PIE Group 12 - MUXed into CPU INT12
// -----------------------------------------------------------
// Connected to PIEIER9_1 (use MINT12 and MG121 masks):
#if (G121PL != 0)
interrupt void XINT3_ISR(void)
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
IER |= M_INT12;
IER &= MINT12; // Set "global" priority
PieCtrlRegs.PIEIER12.all &= MG121; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER12.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER12_2 (use MINT12 and MG122 masks):
#if (G122PL != 0)
interrupt void XINT4_ISR(void)
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
IER |= M_INT12;
IER &= MINT12; // Set "global" priority
PieCtrlRegs.PIEIER12.all &= MG122; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER12.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER12_3 (use MINT12 and MG123 masks):
#if (G123PL != 0)
interrupt void XINT5_ISR(void) // SCI-B
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
IER |= M_INT12;
IER &= MINT12; // Set "global" priority
PieCtrlRegs.PIEIER12.all &= MG123; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER12.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER12_4 (use MINT12 and MG124 masks):
#if (G124PL != 0)
interrupt void XINT6_ISR(void) // SCI-B
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
IER |= M_INT12;
IER &= MINT12; // Set "global" priority
PieCtrlRegs.PIEIER12.all &= MG124; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER12.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER12_5 (use MINT12 and MG125 masks):
#if (G125PL != 0)
interrupt void XINT7_ISR(void) // eCAN-A
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
IER |= M_INT12;
IER &= MINT12; // Set "global" priority
PieCtrlRegs.PIEIER12.all &= MG125; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER12.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER12_7 (use MINT12 and MG127 masks):
#if (G127PL != 0)
interrupt void LVF_ISR(void) // FPU
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
IER |= M_INT12;
IER &= MINT12; // Set "global" priority
PieCtrlRegs.PIEIER12.all &= MG127; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER12.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
// Connected to PIEIER12_8 (use MINT12 and MG128 masks):
#if (G128PL != 0)
interrupt void LUF_ISR(void) // FPU
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
IER |= M_INT12;
IER &= MINT12; // Set "global" priority
PieCtrlRegs.PIEIER12.all &= MG128; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
// Insert ISR Code here.......
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER12.all = TempPIEIER;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
#endif
//---------------------------------------------------------------------------
// Catch All Default ISRs:
//
interrupt void PIE_RESERVED(void) // Reserved space. For test.
{
asm (" ESTOP0");
for(;;);
}
interrupt void INT_NOTUSED_ISR(void) // Reserved space. For test.
{
asm (" ESTOP0");
for(;;);
}
interrupt void rsvd_ISR(void) // For test
{
asm (" ESTOP0");
for(;;);
}
//===========================================================================
// No more.
//===========================================================================

511
v120/DSP2833x_common/source/DSP2833x_SWPrioritizedPieVect.c Normal file
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// TI File $Revision: /main/2 $
// Checkin $Date: April 4, 2007 14:25:31 $
//###########################################################################
//
// FILE: DSP2833x_SWPiroritizedPieVect.c
//
// TITLE: DSP2833x Devices SW Prioritized PIE Vector Table Initialization.
//
//###########################################################################
//
// Original Source by A.T.
//
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
#include "DSP2833x_SWPrioritizedIsrLevels.h"
const struct PIE_VECT_TABLE PieVectTableInit = {
PIE_RESERVED, // Reserved space
PIE_RESERVED, // reserved
PIE_RESERVED, // reserved
PIE_RESERVED, // reserved
PIE_RESERVED, // reserved
PIE_RESERVED, // reserved
PIE_RESERVED, // reserved
PIE_RESERVED, // reserved
PIE_RESERVED, // reserved
PIE_RESERVED, // reserved
PIE_RESERVED, // reserved
PIE_RESERVED, // reserved
PIE_RESERVED, // reserved
// Non-Peripheral Interrupts:
#if (INT13PL != 0)
INT13_ISR, // XINT13
#else
INT_NOTUSED_ISR,
#endif
#if (INT14PL != 0)
INT14_ISR, // CPU-Timer2
#else
INT_NOTUSED_ISR,
#endif
#if (INT15PL != 0)
DATALOG_ISR, // Datalogging interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (INT16PL != 0)
RTOSINT_ISR, // RTOS interrupt
#else
INT_NOTUSED_ISR,
#endif
rsvd_ISR, // reserved interrupt
NMI_ISR, // Non-maskable interrupt
ILLEGAL_ISR, // Illegal operation TRAP
USER1_ISR, // User Defined trap 1
USER2_ISR, // User Defined trap 2
USER3_ISR, // User Defined trap 3
USER4_ISR, // User Defined trap 4
USER5_ISR, // User Defined trap 5
USER6_ISR, // User Defined trap 6
USER7_ISR, // User Defined trap 7
USER8_ISR, // User Defined trap 8
USER9_ISR, // User Defined trap 9
USER10_ISR, // User Defined trap 10
USER11_ISR, // User Defined trap 11
USER12_ISR, // User Defined trap 12
// Group 1 PIE Vectors:
#if (G11PL != 0)
SEQ1INT_ISR, // ADC
#else
INT_NOTUSED_ISR,
#endif
#if (G12PL != 0)
SEQ2INT_ISR, // ADC
#else
INT_NOTUSED_ISR,
#endif
rsvd_ISR,
#if (G14PL != 0)
XINT1_ISR, // External
#else
INT_NOTUSED_ISR,
#endif
#if (G15PL != 0)
XINT2_ISR, // External
#else
INT_NOTUSED_ISR,
#endif
#if (G16PL != 0)
ADCINT_ISR, // ADC
#else
INT_NOTUSED_ISR,
#endif
#if (G17PL != 0)
TINT0_ISR, // Timer 0
#else
INT_NOTUSED_ISR,
#endif
#if (G18PL != 0)
WAKEINT_ISR, // WD & Low Power
#else
INT_NOTUSED_ISR,
#endif
// Group 2 PIE Vectors:
#if (G21PL != 0)
EPWM1_TZINT_ISR, // ePWM1 Trip Zone
#else
INT_NOTUSED_ISR,
#endif
#if (G22PL != 0)
EPWM2_TZINT_ISR, // ePWM2 Trip Zone
#else
INT_NOTUSED_ISR,
#endif
#if (G23PL != 0)
EPWM3_TZINT_ISR, // ePWM3 Trip Zone
#else
INT_NOTUSED_ISR,
#endif
#if (G24PL != 0)
EPWM4_TZINT_ISR, // ePWM4 Trip Zone
#else
INT_NOTUSED_ISR,
#endif
#if (G25PL != 0)
EPWM5_TZINT_ISR, // ePWM5 Trip Zone
#else
INT_NOTUSED_ISR,
#endif
#if (G26PL != 0)
EPWM6_TZINT_ISR, // ePWM6 Trip Zone
#else
INT_NOTUSED_ISR,
#endif
rsvd_ISR,
rsvd_ISR,
// Group 3 PIE Vectors:
#if (G31PL != 0)
EPWM1_INT_ISR, // ePWM1 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G32PL != 0)
EPWM2_INT_ISR, // ePWM2 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G33PL != 0)
EPWM3_INT_ISR, // ePWM3 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G34PL != 0)
EPWM4_INT_ISR, // ePWM4 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G35PL != 0)
EPWM5_INT_ISR, // ePWM5 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G36PL != 0)
EPWM6_INT_ISR, // ePWM6 Interrupt
#else
INT_NOTUSED_ISR,
#endif
rsvd_ISR,
rsvd_ISR,
// Group 4 PIE Vectors:
#if (G41PL != 0)
ECAP1_INT_ISR, // eCAP1 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G42PL != 0)
ECAP2_INT_ISR, // eCAP2 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G43PL != 0)
ECAP3_INT_ISR, // eCAP3 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G44PL != 0)
ECAP4_INT_ISR, // eCAP4 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G45PL != 0)
ECAP5_INT_ISR, // eCAP5 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G46PL != 0)
ECAP6_INT_ISR, // eCAP6 Interrupt
#else
INT_NOTUSED_ISR,
#endif
rsvd_ISR,
rsvd_ISR,
// Group 5 PIE Vectors:
#if (G51PL != 0)
EQEP1_INT_ISR, // eQEP1 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G52PL != 0)
EQEP2_INT_ISR, // eQEP2 Interrupt
#else
INT_NOTUSED_ISR,
#endif
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
// Group 6 PIE Vectors:
#if (G61PL != 0)
SPIRXINTA_ISR, // SPI-A
#else
INT_NOTUSED_ISR,
#endif
#if (G62PL != 0)
SPITXINTA_ISR, // SPI-A
#else
INT_NOTUSED_ISR,
#endif
#if (G63PL != 0)
MRINTB_ISR, // McBSP-B
#else
INT_NOTUSED_ISR,
#endif
#if (G64PL != 0)
MXINTB_ISR, // McBSP-B
#else
INT_NOTUSED_ISR,
#endif
#if (G65PL != 0)
MRINTA_ISR, // McBSP-A
#else
INT_NOTUSED_ISR,
#endif
#if (G66PL != 0)
MXINTA_ISR, // McBSP-A
#else
INT_NOTUSED_ISR,
#endif
rsvd_ISR,
rsvd_ISR,
// Group 7 PIE Vectors:
#if (G71PL != 0)
DINTCH1_ISR, // DMA-Channel 1 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G72PL != 0)
DINTCH2_ISR, // DMA-Channel 2 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G73PL != 0)
DINTCH3_ISR, // DMA-Channel 3 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G74PL != 0)
DINTCH4_ISR, // DMA-Channel 4 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G75PL != 0)
DINTCH5_ISR, // DMA-Channel 5 Interrupt
#else
INT_NOTUSED_ISR,
#endif
#if (G76PL != 0)
DINTCH6_ISR, // DMA-Channel 6 Interrupt
#else
INT_NOTUSED_ISR,
#endif
rsvd_ISR,
rsvd_ISR,
// Group 8 PIE Vectors:
#if (G81PL != 0)
I2CINT1A_ISR, // I2C-A
#else
INT_NOTUSED_ISR,
#endif
#if (G82PL != 0)
I2CINT2A_ISR, // I2C-A
#else
INT_NOTUSED_ISR,
#endif
rsvd_ISR,
rsvd_ISR,
#if (G85PL != 0)
SCIRXINTC_ISR, // SCI-C
#else
INT_NOTUSED_ISR,
#endif
#if (G86PL != 0)
SCITXINTC_ISR, // SCI-C
#else
INT_NOTUSED_ISR,
#endif
rsvd_ISR,
rsvd_ISR,
// Group 9 PIE Vectors:
#if (G91PL != 0)
SCIRXINTA_ISR, // SCI-A
#else
INT_NOTUSED_ISR,
#endif
#if (G92PL != 0)
SCITXINTA_ISR, // SCI-A
#else
INT_NOTUSED_ISR,
#endif
#if (G93PL != 0)
SCIRXINTB_ISR, // SCI-B
#else
INT_NOTUSED_ISR,
#endif
#if (G94PL != 0)
SCITXINTB_ISR, // SCI-B
#else
INT_NOTUSED_ISR,
#endif
#if (G95PL != 0)
ECAN0INTA_ISR, // eCAN-A
#else
INT_NOTUSED_ISR,
#endif
#if (G96PL != 0)
ECAN1INTA_ISR, // eCAN-A
#else
INT_NOTUSED_ISR,
#endif
#if (G97PL != 0)
ECAN0INTB_ISR, // eCAN-B
#else
INT_NOTUSED_ISR,
#endif
#if (G98PL != 0)
ECAN1INTB_ISR, // eCAN-B
#else
INT_NOTUSED_ISR,
#endif
// Group 10 PIE Vectors
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
// Group 11 PIE Vectors
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
// Group 12 PIE Vectors
#if (G121PL != 0)
XINT3_ISR, // External interrupt 3
#else
INT_NOTUSED_ISR,
#endif
#if (G122PL != 0)
XINT4_ISR, // External interrupt 4
#else
INT_NOTUSED_ISR,
#endif
#if (G123PL != 0)
XINT5_ISR, // External interrupt 5
#else
INT_NOTUSED_ISR,
#endif
#if (G124PL != 0)
XINT6_ISR, // External interrupt 6
#else
INT_NOTUSED_ISR,
#endif
#if (G125PL != 0)
XINT7_ISR, // External interrupt 7
#else
INT_NOTUSED_ISR,
#endif
rsvd_ISR,
#if (G127PL != 0)
LVF_ISR, // Latched overflow flag
#else
INT_NOTUSED_ISR,
#endif
#if (G128PL != 0)
LUF_ISR, // Latched underflow flag
#else
INT_NOTUSED_ISR,
#endif
};
//---------------------------------------------------------------------------
// InitPieVectTable:
//---------------------------------------------------------------------------
// This function initializes the PIE vector table to a known state.
// This function must be executed after boot time.
//
void InitPieVectTable(void)
{
int16 i;
Uint32 *Source = (void *) &PieVectTableInit;
Uint32 *Dest = (void *) &PieVectTable;
EALLOW;
for(i=0; i < 128; i++) {
*Dest++ = *Source++;
}
EDIS;
}
//===========================================================================
// No more.
//===========================================================================

415
v120/DSP2833x_common/source/DSP2833x_SysCtrl.c Normal file
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// TI File $Revision: /main/7 $
// Checkin $Date: September 20, 2007 13:30:31 $
//###########################################################################
//
// FILE: DSP2833x_SysCtrl.c
//
// TITLE: DSP2833x Device System Control Initialization & Support Functions.
//
// DESCRIPTION:
//
// Example initialization of system resources.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP2833x_Device.h" // Headerfile Include File
#include "DSP2833x_Examples.h" // Examples Include File
//#include "RS485.h"
//#include "message.h"
// Functions that will be run from RAM need to be assigned to
// a different section. This section will then be mapped to a load and
// run address using the linker cmd file.
#pragma CODE_SECTION(InitFlash, "ramfuncs");
//---------------------------------------------------------------------------
// InitSysCtrl:
//---------------------------------------------------------------------------
// This function initializes the System Control registers to a known state.
// - Disables the watchdog
// - Set the PLLCR for proper SYSCLKOUT frequency
// - Set the pre-scaler for the high and low frequency peripheral clocks
// - Enable the clocks to the peripherals
long SYSCLKOUT, LSPCLK, HSPCLK;
void InitSysCtrl(void)
{
// Disable the watchdog
DisableDog();
// Initialize the PLL control: PLLCR and DIVSEL
// DSP28_PLLCR and DSP28_DIVSEL are defined in DSP2833x_Examples.h
InitPll(DSP28_PLLCR,DSP28_DIVSEL);
// Initialize the peripheral clocks
InitPeripheralClocks();
}
//---------------------------------------------------------------------------
// Example: InitFlash:
//---------------------------------------------------------------------------
// This function initializes the Flash Control registers
// CAUTION
// This function MUST be executed out of RAM. Executing it
// out of OTP/Flash will yield unpredictable results
void InitFlash(void)
{
EALLOW;
//Enable Flash Pipeline mode to improve performance
//of code executed from Flash.
FlashRegs.FOPT.bit.ENPIPE = 1;
// CAUTION
//Minimum waitstates required for the flash operating
//at a given CPU rate must be characterized by TI.
//Refer to the datasheet for the latest information.
#if CPU_FRQ_150MHZ
//Set the Paged Waitstate for the Flash
FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5;
//Set the Random Waitstate for the Flash
FlashRegs.FBANKWAIT.bit.RANDWAIT = 5;
//Set the Waitstate for the OTP
FlashRegs.FOTPWAIT.bit.OTPWAIT = 8;
#endif
#if CPU_FRQ_100MHZ
//Set the Paged Waitstate for the Flash
FlashRegs.FBANKWAIT.bit.PAGEWAIT = 3;
//Set the Random Waitstate for the Flash
FlashRegs.FBANKWAIT.bit.RANDWAIT = 3;
//Set the Waitstate for the OTP
FlashRegs.FOTPWAIT.bit.OTPWAIT = 5;
#endif
// CAUTION
//ONLY THE DEFAULT VALUE FOR THESE 2 REGISTERS SHOULD BE USED
FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF;
FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF;
EDIS;
//Force a pipeline flush to ensure that the write to
//the last register configured occurs before returning.
asm(" RPT #7 || NOP");
}
//---------------------------------------------------------------------------
// Example: ServiceDog:
//---------------------------------------------------------------------------
// This function resets the watchdog timer.
// Enable this function for using ServiceDog in the application
void ServiceDog(void)
{
if(SysCtrlRegs.PLLCR.bit.DIV == DSP28_PLLCR)
if(SysCtrlRegs.PLLSTS.bit.DIVSEL == DSP28_DIVSEL)
{
EALLOW;
SysCtrlRegs.WDKEY = 0x0055;
SysCtrlRegs.WDKEY = 0x00AA;
EDIS;
return;
} }
//---------------------------------------------------------------------------
// Example: DisableDog:
//---------------------------------------------------------------------------
// This function disables the watchdog timer.
void DisableDog(void)
{
EALLOW;
SysCtrlRegs.WDCR= 0x0068;
EDIS;
}
//---------------------------------------------------------------------------
// Example: InitPll:
//---------------------------------------------------------------------------
// This function initializes the PLLCR register.
void InitPll(Uint16 divval, Uint16 divsel)
{
long clkVal;
// Make sure the PLL is not running in limp mode
if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0)
{
// Missing external clock has been detected
// Replace this line with a call to an appropriate
// SystemShutdown(); function.
asm(" ESTOP0");
}
// DIVSEL MUST be 0 before PLLCR can be changed from
// 0x0000. It is set to 0 by an external reset XRSn
// This puts us in 1/4
if (SysCtrlRegs.PLLSTS.bit.DIVSEL != 0)
{
EALLOW;
SysCtrlRegs.PLLSTS.bit.DIVSEL = 0;
EDIS;
}
// Change the PLLCR
// if (SysCtrlRegs.PLLCR.bit.DIV != val)
{
EALLOW;
// Before setting PLLCR turn off missing clock detect logic
SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1;
SysCtrlRegs.PLLCR.bit.DIV = divval;
EDIS;
clkVal = (divval)?divval:1;
clkVal = XCLKIN * clkVal;
// Optional: Wait for PLL to lock.
// During this time the CPU will switch to OSCCLK/2 until
// the PLL is stable. Once the PLL is stable the CPU will
// switch to the new PLL value.
//
// This time-to-lock is monitored by a PLL lock counter.
//
// Code is not required to sit and wait for the PLL to lock.
// However, if the code does anything that is timing critical,
// and requires the correct clock be locked, then it is best to
// wait until this switching has completed.
// Wait for the PLL lock bit to be set.
// The watchdog should be disabled before this loop, or fed within
// the loop via ServiceDog().
// Uncomment to disable the watchdog
DisableDog();
while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1)
{
// Uncomment to service the watchdog
// ServiceDog();
}
EALLOW;
SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0;
EDIS;
}
// If switching to 1/2
if((divsel == 1)||(divsel == 2))
{
EALLOW;
SysCtrlRegs.PLLSTS.bit.DIVSEL = divsel;
EDIS;
}
if(divsel == 0) clkVal /= 4;
if(divsel == 1) clkVal /= 4;
if(divsel == 2) clkVal /= 2;
// If switching to 1/1
// * First go to 1/2 and let the power settle
// The time required will depend on the system, this is only an example
// * Then switch to 1/1
if((divval == 0) && (divsel == 3))
{
EALLOW;
SysCtrlRegs.PLLSTS.bit.DIVSEL = 2;
DELAY_US(50L);
// pause_us(50L);
SysCtrlRegs.PLLSTS.bit.DIVSEL = 3;
EDIS;
}
SYSCLKOUT = clkVal;
}
//--------------------------------------------------------------------------
// Example: InitPeripheralClocks:
//---------------------------------------------------------------------------
// This function initializes the clocks to the peripheral modules.
// First the high and low clock prescalers are set
// Second the clocks are enabled to each peripheral.
// To reduce power, leave clocks to unused peripherals disabled
//
// Note: If a peripherals clock is not enabled then you cannot
// read or write to the registers for that peripheral
void InitPeripheralClocks(void)
{
long Val;
EALLOW;
// HISPCP/LOSPCP prescale register settings, normally it will be set to default values
#if CLKMULT == 0
SysCtrlRegs.HISPCP.all = 0x0000;
#endif
#if CLKMULT == 1
SysCtrlRegs.HISPCP.all = 0x0000;
#endif
#if CLKMULT == 2
SysCtrlRegs.HISPCP.all = 0x0001;
#endif
#if CLKMULT == 3
SysCtrlRegs.HISPCP.all = 0x0002;
#endif
#if CLKMULT == 4
SysCtrlRegs.HISPCP.all = 0x0002;
#endif
#if CLKMULT == 5
SysCtrlRegs.HISPCP.all = 0x0003;
#endif
SysCtrlRegs.LOSPCP.all = 0x0000;
Val = (SysCtrlRegs.HISPCP.all)?
SysCtrlRegs.HISPCP.all*2 : 1;
Val = SYSCLKOUT / Val;
HSPCLK = Val;
Val = (SysCtrlRegs.LOSPCP.all)?
SysCtrlRegs.LOSPCP.all*2 : 1;
Val = SYSCLKOUT / Val;
LSPCLK = Val;
// XCLKOUT to SYSCLKOUT ratio. By default XCLKOUT = 1/4 SYSCLKOUT
// XTIMCLK = SYSCLKOUT/2
XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
// XCLKOUT = XTIMCLK/2
XintfRegs.XINTCNF2.bit.CLKMODE = 1;
// Enable XCLKOUT
XintfRegs.XINTCNF2.bit.CLKOFF = 0;
// Peripheral clock enables set for the selected peripherals.
// If you are not using a peripheral leave the clock off
// to save on power.
//
// Note: not all peripherals are available on all 2833x derivates.
// Refer to the datasheet for your particular device.
//
// This function is not written to be an example of efficient code.
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // ADC
// *IMPORTANT*
// The ADC_cal function, which copies the ADC calibration values from TI reserved
// OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs automatically in the
// Boot ROM. If the boot ROM code is bypassed during the debug process, the
// following function MUST be called for the ADC to function according
// to specification. The clocks to the ADC MUST be enabled before calling this
// function.
// See the device data manual and/or the ADC Reference
// Manual for more information.
ADC_cal();
SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 1; // I2C
SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 1; // SCI-A
SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 1; // SCI-B
SysCtrlRegs.PCLKCR0.bit.SCICENCLK = 1; // SCI-C
SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 1; // SPI-A
SysCtrlRegs.PCLKCR0.bit.MCBSPAENCLK = 1; // McBSP-A
SysCtrlRegs.PCLKCR0.bit.MCBSPBENCLK = 1; // McBSP-B
SysCtrlRegs.PCLKCR0.bit.ECANAENCLK=1; // eCAN-A
SysCtrlRegs.PCLKCR0.bit.ECANBENCLK=1; // eCAN-B
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the ePWM
SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1; // ePWM1
SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1; // ePWM2
SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1; // ePWM3
SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1; // ePWM4
SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1; // ePWM5
SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 1; // ePWM6
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the ePWM
SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 1; // eCAP3
SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 1; // eCAP4
SysCtrlRegs.PCLKCR1.bit.ECAP5ENCLK = 1; // eCAP5
SysCtrlRegs.PCLKCR1.bit.ECAP6ENCLK = 1; // eCAP6
SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 1; // eCAP1
SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 1; // eCAP2
SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 1; // eQEP1
SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 1; // eQEP2
SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 1; // CPU Timer 0
SysCtrlRegs.PCLKCR3.bit.CPUTIMER1ENCLK = 1; // CPU Timer 1
SysCtrlRegs.PCLKCR3.bit.CPUTIMER2ENCLK = 1; // CPU Timer 2
SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1; // DMA Clock
SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; // XTIMCLK
SysCtrlRegs.PCLKCR3.bit.GPIOINENCLK = 1; // GPIO input clock
EDIS;
}
//---------------------------------------------------------------------------
// Example: CsmUnlock:
//---------------------------------------------------------------------------
// This function unlocks the CSM. User must replace 0xFFFF's with current
// password for the DSP. Returns 1 if unlock is successful.
#define STATUS_FAIL 0
#define STATUS_SUCCESS 1
Uint16 CsmUnlock()
{
volatile Uint16 temp;
// Load the key registers with the current password. The 0xFFFF's are dummy
// passwords. User should replace them with the correct password for the DSP.
EALLOW;
CsmRegs.KEY0 = 0xFFFF;
CsmRegs.KEY1 = 0xFFFF;
CsmRegs.KEY2 = 0xFFFF;
CsmRegs.KEY3 = 0xFFFF;
CsmRegs.KEY4 = 0xFFFF;
CsmRegs.KEY5 = 0xFFFF;
CsmRegs.KEY6 = 0xFFFF;
CsmRegs.KEY7 = 0xFFFF;
EDIS;
// Perform a dummy read of the password locations
// if they match the key values, the CSM will unlock
temp = CsmPwl.PSWD0;
temp = CsmPwl.PSWD1;
temp = CsmPwl.PSWD2;
temp = CsmPwl.PSWD3;
temp = CsmPwl.PSWD4;
temp = CsmPwl.PSWD5;
temp = CsmPwl.PSWD6;
temp = CsmPwl.PSWD7;
// If the CSM unlocked, return succes, otherwise return
// failure.
if (CsmRegs.CSMSCR.bit.SECURE == 0) return STATUS_SUCCESS;
else return STATUS_FAIL;
}
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/5 $
// Checkin $Date: August 16, 2007 11:06:26 $
//###########################################################################
//
// FILE: DSP2833x_Xintf.c
//
// TITLE: DSP2833x Device External Interface Init & Support Functions.
//
// DESCRIPTION:
//
// Example initialization function for the external interface (XINTF).
// This example configures the XINTF to its default state. For an
// example of how this function being used refer to the
// examples/run_from_xintf project.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
//---------------------------------------------------------------------------
// InitXINTF:
//---------------------------------------------------------------------------
// This function initializes the External Interface the default reset state.
//
// Do not modify the timings of the XINTF while running from the XINTF. Doing
// so can yield unpredictable results
void InitXintf(void)
{
// This shows how to write to the XINTF registers. The
// values used here are the default state after reset.
// Different hardware will require a different configuration.
// For an example of an XINTF configuration used with the
// F28335 eZdsp, refer to the examples/run_from_xintf project.
// Any changes to XINTF timing should only be made by code
// running outside of the XINTF.
// All Zones---------------------------------
// Timing for all zones based on XTIMCLK = 1/2 SYSCLKOUT
EALLOW;
XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
// No write buffering
XintfRegs.XINTCNF2.bit.WRBUFF = 0;
// XCLKOUT is enabled
XintfRegs.XINTCNF2.bit.CLKOFF = 0;
// XCLKOUT = XTIMCLK/2
XintfRegs.XINTCNF2.bit.CLKMODE = 1;
// Zone 0------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING0.bit.XWRLEAD = 3;
XintfRegs.XTIMING0.bit.XWRACTIVE = 7;
XintfRegs.XTIMING0.bit.XWRTRAIL = 3;
// Zone read timing
XintfRegs.XTIMING0.bit.XRDLEAD = 3;
XintfRegs.XTIMING0.bit.XRDACTIVE = 7;
XintfRegs.XTIMING0.bit.XRDTRAIL = 3;
// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING0.bit.X2TIMING = 1;
// Zone will sample XREADY signal
XintfRegs.XTIMING0.bit.USEREADY = 1;
XintfRegs.XTIMING0.bit.READYMODE = 1; // sample asynchronous
// Size must be either:
// 0,1 = x32 or
// 1,1 = x16 other values are reserved
XintfRegs.XTIMING0.bit.XSIZE = 3;
// Zone 6------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING6.bit.XWRLEAD = 3;
XintfRegs.XTIMING6.bit.XWRACTIVE = 7;
XintfRegs.XTIMING6.bit.XWRTRAIL = 3;
// Zone read timing
XintfRegs.XTIMING6.bit.XRDLEAD = 3;
XintfRegs.XTIMING6.bit.XRDACTIVE = 7;
XintfRegs.XTIMING6.bit.XRDTRAIL = 3;
// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING6.bit.X2TIMING = 1;
// Zone will sample XREADY signal
XintfRegs.XTIMING6.bit.USEREADY = 1;
XintfRegs.XTIMING6.bit.READYMODE = 1; // sample asynchronous
// Size must be either:
// 0,1 = x32 or
// 1,1 = x16 other values are reserved
XintfRegs.XTIMING6.bit.XSIZE = 3;
// Zone 7------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING7.bit.XWRLEAD = 3;
XintfRegs.XTIMING7.bit.XWRACTIVE = 7;
XintfRegs.XTIMING7.bit.XWRTRAIL = 3;
// Zone read timing
XintfRegs.XTIMING7.bit.XRDLEAD = 3;
XintfRegs.XTIMING7.bit.XRDACTIVE = 7;
XintfRegs.XTIMING7.bit.XRDTRAIL = 3;
// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING7.bit.X2TIMING = 1;
// Zone will sample XREADY signal
XintfRegs.XTIMING7.bit.USEREADY = 1;
XintfRegs.XTIMING7.bit.READYMODE = 1; // sample asynchronous
// Size must be either:
// 0,1 = x32 or
// 1,1 = x16 other values are reserved
XintfRegs.XTIMING7.bit.XSIZE = 3;
// Bank switching
// Assume Zone 7 is slow, so add additional BCYC cycles
// when ever switching from Zone 7 to another Zone.
// This will help avoid bus contention.
XintfRegs.XBANK.bit.BANK = 7;
XintfRegs.XBANK.bit.BCYC = 7;
EDIS;
//Force a pipeline flush to ensure that the write to
//the last register configured occurs before returning.
InitXintf16Gpio();
// InitXintf32Gpio();
asm(" RPT #7 || NOP");
}
void InitXintf32Gpio()
{
EALLOW;
GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 3; // XD31
GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 3; // XD30
GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 3; // XD29
GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 3; // XD28
GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 3; // XD27
GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 3; // XD26
GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 3; // XD25
GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 3; // XD24
GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 3; // XD23
GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 3; // XD22
GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 3; // XD21
GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 3; // XD20
GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 3; // XD19
GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 3; // XD18
GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 3; // XD17
GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 3; // XD16
GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 3; // XD31 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 3; // XD30 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 3; // XD29 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 3; // XD28 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 3; // XD27 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 3; // XD26 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // XD25 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // XD24 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // XD23 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // XD22 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // XD21 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // XD20 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // XD19 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // XD18 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // XD17 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 3; // XD16 asynchronous input
InitXintf16Gpio();
}
void InitXintf16Gpio()
{
EALLOW;
GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 3; // XD15
GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 3; // XD14
GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 3; // XD13
GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 3; // XD12
GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 3; // XD11
GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 3; // XD10
GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 3; // XD19
GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 3; // XD8
GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // XD7
GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // XD6
GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // XD5
GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // XD4
GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // XD3
GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // XD2
GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // XD1
GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // XD0
GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // XA0/XWE1n
GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 3; // XA1
GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3; // XA2
GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3; // XA3
GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 3; // XA4
GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 3; // XA5
GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 3; // XA6
GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 3; // XA7
GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 3; // XA8
GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 3; // XA9
GpioCtrlRegs.GPCMUX2.bit.GPIO82 = 3; // XA10
GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 3; // XA11
GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3; // XA12
GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3; // XA13
GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3; // XA14
GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3; // XA15
GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3; // XA16
// GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 3; // XA17
// GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 3; // XA18
// GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3; // XA19
// GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // XREADY
GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // XRNW
GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // XWE0
// GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 3; // XZCS0
GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // XZCS7
// GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // XZCS6
EDIS;
}
//===========================================================================
// No more.
//===========================================================================

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;// TI File $Revision: /main/4 $
;// Checkin $Date: July 30, 2007 10:28:57 $
;//###########################################################################
;//
;// FILE: DSP2833x_usDelay.asm
;//
;// TITLE: Simple delay function
;//
;// DESCRIPTION:
;//
;// This is a simple delay function that can be used to insert a specified
;// delay into code.
;//
;// This function is only accurate if executed from internal zero-waitstate
;// SARAM. If it is executed from waitstate memory then the delay will be
;// longer then specified.
;//
;// To use this function:
;//
;// 1 - update the CPU clock speed in the DSP2833x_Examples.h
;// file. For example:
;// #define CPU_RATE 6.667L // for a 150MHz CPU clock speed
;// or #define CPU_RATE 10.000L // for a 100MHz CPU clock speed
;//
;// 2 - Call this function by using the DELAY_US(A) macro
;// that is defined in the DSP2833x_Examples.h file. This macro
;// will convert the number of microseconds specified
;// into a loop count for use with this function.
;// This count will be based on the CPU frequency you specify.
;//
;// 3 - For the most accurate delay
;// - Execute this function in 0 waitstate RAM.
;// - Disable interrupts before calling the function
;// If you do not disable interrupts, then think of
;// this as an "at least" delay function as the actual
;// delay may be longer.
;//
;// The C assembly call from the DELAY_US(time) macro will
;// look as follows:
;//
;// extern void Delay(long LoopCount);
;//
;// MOV AL,#LowLoopCount
;// MOV AH,#HighLoopCount
;// LCR _Delay
;//
;// Or as follows (if count is less then 16-bits):
;//
;// MOV ACC,#LoopCount
;// LCR _Delay
;//
;//
;//###########################################################################
;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
;// $Release Date: August 1, 2008 $
;//###########################################################################
.def _DSP28x_usDelay
.sect ".text"
.global __DSP28x_usDelay
_DSP28x_usDelay:
SUB ACC,#1
BF _DSP28x_usDelay,GEQ ;; Loop if ACC >= 0
LRETR
;There is a 9/10 cycle overhead and each loop
;takes five cycles. The LoopCount is given by
;the following formula:
; DELAY_CPU_CYCLES = 9 + 5*LoopCount
; LoopCount = (DELAY_CPU_CYCLES - 9) / 5
; The macro DELAY_US(A) performs this calculation for you
;
;//===========================================================================
;// End of file.
;//===========================================================================

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v120/DSP2833x_headers/cmd/DSP2833x_Headers_BIOS.cmd Normal file
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/*
// TI File $Revision: /main/9 $
// Checkin $Date: August 8, 2008 11:09:25 $
//###########################################################################
//
// FILE: DSP2833x_Headers_BIOS.cmd
//
// TITLE: DSP2833x Peripheral registers linker command file
//
// DESCRIPTION:
//
// This file is for use in BIOS applications.
//
// Linker command file to place the peripheral structures
// used within the DSP2833x headerfiles into the correct memory
// mapped locations.
//
// This version of the file does not include the PieVectorTable structure.
// For non-BIOS applications, please use the DSP2833x_Headers_nonBIOS.cmd
// file which includes the PieVectorTable structure.
//
//#####################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//#####################################################################
*/
MEMORY
{
PAGE 0: /* Program Memory */
PAGE 1: /* Data Memory */
DEV_EMU : origin = 0x000880, length = 0x000180 /* device emulation registers */
FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */
CSM : origin = 0x000AE0, length = 0x000010 /* code security module registers */
ADC_MIRROR : origin = 0x000B00, length = 0x000010 /* ADC Results register mirror */
XINTF : origin = 0x000B20, length = 0x000020 /* external interface registers */
CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */
CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/
CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/
PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */
DMA : origin = 0x001000, length = 0x000200 /* DMA registers */
MCBSPA : origin = 0x005000, length = 0x000040 /* McBSP-A registers */
MCBSPB : origin = 0x005040, length = 0x000040 /* McBSP-B registers */
ECANA : origin = 0x006000, length = 0x000040 /* eCAN-A control and status registers */
ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN-A local acceptance masks */
ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN-A message object time stamps */
ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN-A object time-out registers */
ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN-A mailboxes */
ECANB : origin = 0x006200, length = 0x000040 /* eCAN-B control and status registers */
ECANB_LAM : origin = 0x006240, length = 0x000040 /* eCAN-B local acceptance masks */
ECANB_MOTS : origin = 0x006280, length = 0x000040 /* eCAN-B message object time stamps */
ECANB_MOTO : origin = 0x0062C0, length = 0x000040 /* eCAN-B object time-out registers */
ECANB_MBOX : origin = 0x006300, length = 0x000100 /* eCAN-B mailboxes */
EPWM1 : origin = 0x006800, length = 0x000022 /* Enhanced PWM 1 registers */
EPWM2 : origin = 0x006840, length = 0x000022 /* Enhanced PWM 2 registers */
EPWM3 : origin = 0x006880, length = 0x000022 /* Enhanced PWM 3 registers */
EPWM4 : origin = 0x0068C0, length = 0x000022 /* Enhanced PWM 4 registers */
EPWM5 : origin = 0x006900, length = 0x000022 /* Enhanced PWM 5 registers */
EPWM6 : origin = 0x006940, length = 0x000022 /* Enhanced PWM 6 registers */
ECAP1 : origin = 0x006A00, length = 0x000020 /* Enhanced Capture 1 registers */
ECAP2 : origin = 0x006A20, length = 0x000020 /* Enhanced Capture 2 registers */
ECAP3 : origin = 0x006A40, length = 0x000020 /* Enhanced Capture 3 registers */
ECAP4 : origin = 0x006A60, length = 0x000020 /* Enhanced Capture 4 registers */
ECAP5 : origin = 0x006A80, length = 0x000020 /* Enhanced Capture 5 registers */
ECAP6 : origin = 0x006AA0, length = 0x000020 /* Enhanced Capture 6 registers */
EQEP1 : origin = 0x006B00, length = 0x000040 /* Enhanced QEP 1 registers */
EQEP2 : origin = 0x006B40, length = 0x000040 /* Enhanced QEP 2 registers */
GPIOCTRL : origin = 0x006F80, length = 0x000040 /* GPIO control registers */
GPIODAT : origin = 0x006FC0, length = 0x000020 /* GPIO data registers */
GPIOINT : origin = 0x006FE0, length = 0x000020 /* GPIO interrupt/LPM registers */
SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */
SPIA : origin = 0x007040, length = 0x000010 /* SPI-A registers */
SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */
XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */
ADC : origin = 0x007100, length = 0x000020 /* ADC registers */
SCIB : origin = 0x007750, length = 0x000010 /* SCI-B registers */
SCIC : origin = 0x007770, length = 0x000010 /* SCI-C registers */
I2CA : origin = 0x007900, length = 0x000040 /* I2C-A registers */
CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */
PARTID : origin = 0x380090, length = 0x000001 /* Part ID register location */
}
SECTIONS
{
/*** The PIE Vector table is called PIEVECT by DSP/BIOS ***/
PieVectTableFile : > PIEVECT, PAGE = 1, TYPE = DSECT
/*** Peripheral Frame 0 Register Structures ***/
DevEmuRegsFile : > DEV_EMU, PAGE = 1
FlashRegsFile : > FLASH_REGS, PAGE = 1
CsmRegsFile : > CSM, PAGE = 1
AdcMirrorFile : > ADC_MIRROR, PAGE = 1
XintfRegsFile : > XINTF, PAGE = 1
CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1
CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1
CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1
PieCtrlRegsFile : > PIE_CTRL, PAGE = 1
DmaRegsFile : > DMA, PAGE = 1
/*** Peripheral Frame 3 Register Structures ***/
McbspaRegsFile : > MCBSPA, PAGE = 1
McbspbRegsFile : > MCBSPB, PAGE = 1
/*** Peripheral Frame 1 Register Structures ***/
ECanaRegsFile : > ECANA, PAGE = 1
ECanaLAMRegsFile : > ECANA_LAM PAGE = 1
ECanaMboxesFile : > ECANA_MBOX PAGE = 1
ECanaMOTSRegsFile : > ECANA_MOTS PAGE = 1
ECanaMOTORegsFile : > ECANA_MOTO PAGE = 1
ECanbRegsFile : > ECANB, PAGE = 1
ECanbLAMRegsFile : > ECANB_LAM PAGE = 1
ECanbMboxesFile : > ECANB_MBOX PAGE = 1
ECanbMOTSRegsFile : > ECANB_MOTS PAGE = 1
ECanbMOTORegsFile : > ECANB_MOTO PAGE = 1
EPwm1RegsFile : > EPWM1 PAGE = 1
EPwm2RegsFile : > EPWM2 PAGE = 1
EPwm3RegsFile : > EPWM3 PAGE = 1
EPwm4RegsFile : > EPWM4 PAGE = 1
EPwm5RegsFile : > EPWM5 PAGE = 1
EPwm6RegsFile : > EPWM6 PAGE = 1
ECap1RegsFile : > ECAP1 PAGE = 1
ECap2RegsFile : > ECAP2 PAGE = 1
ECap3RegsFile : > ECAP3 PAGE = 1
ECap4RegsFile : > ECAP4 PAGE = 1
ECap5RegsFile : > ECAP5 PAGE = 1
ECap6RegsFile : > ECAP6 PAGE = 1
EQep1RegsFile : > EQEP1 PAGE = 1
EQep2RegsFile : > EQEP2 PAGE = 1
GpioCtrlRegsFile : > GPIOCTRL PAGE = 1
GpioDataRegsFile : > GPIODAT PAGE = 1
GpioIntRegsFile : > GPIOINT PAGE = 1
/*** Peripheral Frame 2 Register Structures ***/
SysCtrlRegsFile : > SYSTEM, PAGE = 1
SpiaRegsFile : > SPIA, PAGE = 1
SciaRegsFile : > SCIA, PAGE = 1
XIntruptRegsFile : > XINTRUPT, PAGE = 1
AdcRegsFile : > ADC, PAGE = 1
ScibRegsFile : > SCIB, PAGE = 1
ScicRegsFile : > SCIC, PAGE = 1
I2caRegsFile : > I2CA, PAGE = 1
/*** Code Security Module Register Structures ***/
CsmPwlFile : > CSM_PWL, PAGE = 1
/*** Device Part ID Register Structures ***/
PartIdRegsFile : > PARTID, PAGE = 1
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/

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/*
// TI File $Revision: /main/8 $
// Checkin $Date: June 2, 2008 11:12:24 $
//###########################################################################
//
// FILE: DSP2833x_Headers_nonBIOS.cmd
//
// TITLE: DSP2833x Peripheral registers linker command file
//
// DESCRIPTION:
//
// This file is for use in Non-BIOS applications.
//
// Linker command file to place the peripheral structures
// used within the DSP2833x headerfiles into the correct memory
// mapped locations.
//
// This version of the file includes the PieVectorTable structure.
// For BIOS applications, please use the DSP2833x_Headers_BIOS.cmd file
// which does not include the PieVectorTable structure.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
*/
MEMORY
{
PAGE 0: /* Program Memory */
PAGE 1: /* Data Memory */
DEV_EMU : origin = 0x000880, length = 0x000180 /* device emulation registers */
FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */
CSM : origin = 0x000AE0, length = 0x000010 /* code security module registers */
ADC_MIRROR : origin = 0x000B00, length = 0x000010 /* ADC Results register mirror */
XINTF : origin = 0x000B20, length = 0x000020 /* external interface registers */
CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */
CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/
CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/
PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */
PIE_VECT : origin = 0x000D00, length = 0x000100 /* PIE Vector Table */
DMA : origin = 0x001000, length = 0x000200 /* DMA registers */
MCBSPA : origin = 0x005000, length = 0x000040 /* McBSP-A registers */
MCBSPB : origin = 0x005040, length = 0x000040 /* McBSP-B registers */
ECANA : origin = 0x006000, length = 0x000040 /* eCAN-A control and status registers */
ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN-A local acceptance masks */
ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN-A message object time stamps */
ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN-A object time-out registers */
ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN-A mailboxes */
ECANB : origin = 0x006200, length = 0x000040 /* eCAN-B control and status registers */
ECANB_LAM : origin = 0x006240, length = 0x000040 /* eCAN-B local acceptance masks */
ECANB_MOTS : origin = 0x006280, length = 0x000040 /* eCAN-B message object time stamps */
ECANB_MOTO : origin = 0x0062C0, length = 0x000040 /* eCAN-B object time-out registers */
ECANB_MBOX : origin = 0x006300, length = 0x000100 /* eCAN-B mailboxes */
EPWM1 : origin = 0x006800, length = 0x000022 /* Enhanced PWM 1 registers */
EPWM2 : origin = 0x006840, length = 0x000022 /* Enhanced PWM 2 registers */
EPWM3 : origin = 0x006880, length = 0x000022 /* Enhanced PWM 3 registers */
EPWM4 : origin = 0x0068C0, length = 0x000022 /* Enhanced PWM 4 registers */
EPWM5 : origin = 0x006900, length = 0x000022 /* Enhanced PWM 5 registers */
EPWM6 : origin = 0x006940, length = 0x000022 /* Enhanced PWM 6 registers */
ECAP1 : origin = 0x006A00, length = 0x000020 /* Enhanced Capture 1 registers */
ECAP2 : origin = 0x006A20, length = 0x000020 /* Enhanced Capture 2 registers */
ECAP3 : origin = 0x006A40, length = 0x000020 /* Enhanced Capture 3 registers */
ECAP4 : origin = 0x006A60, length = 0x000020 /* Enhanced Capture 4 registers */
ECAP5 : origin = 0x006A80, length = 0x000020 /* Enhanced Capture 5 registers */
ECAP6 : origin = 0x006AA0, length = 0x000020 /* Enhanced Capture 6 registers */
EQEP1 : origin = 0x006B00, length = 0x000040 /* Enhanced QEP 1 registers */
EQEP2 : origin = 0x006B40, length = 0x000040 /* Enhanced QEP 2 registers */
GPIOCTRL : origin = 0x006F80, length = 0x000040 /* GPIO control registers */
GPIODAT : origin = 0x006FC0, length = 0x000020 /* GPIO data registers */
GPIOINT : origin = 0x006FE0, length = 0x000020 /* GPIO interrupt/LPM registers */
SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */
SPIA : origin = 0x007040, length = 0x000010 /* SPI-A registers */
SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */
XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */
ADC : origin = 0x007100, length = 0x000020 /* ADC registers */
SCIB : origin = 0x007750, length = 0x000010 /* SCI-B registers */
SCIC : origin = 0x007770, length = 0x000010 /* SCI-C registers */
I2CA : origin = 0x007900, length = 0x000040 /* I2C-A registers */
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */
PARTID : origin = 0x380090, length = 0x000001 /* Part ID register location */
}
SECTIONS
{
PieVectTableFile : > PIE_VECT, PAGE = 1
/*** Peripheral Frame 0 Register Structures ***/
DevEmuRegsFile : > DEV_EMU, PAGE = 1
FlashRegsFile : > FLASH_REGS, PAGE = 1
CsmRegsFile : > CSM, PAGE = 1
AdcMirrorFile : > ADC_MIRROR, PAGE = 1
XintfRegsFile : > XINTF, PAGE = 1
CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1
CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1
CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1
PieCtrlRegsFile : > PIE_CTRL, PAGE = 1
DmaRegsFile : > DMA, PAGE = 1
/*** Peripheral Frame 3 Register Structures ***/
McbspaRegsFile : > MCBSPA, PAGE = 1
McbspbRegsFile : > MCBSPB, PAGE = 1
/*** Peripheral Frame 1 Register Structures ***/
ECanaRegsFile : > ECANA, PAGE = 1
ECanaLAMRegsFile : > ECANA_LAM PAGE = 1
ECanaMboxesFile : > ECANA_MBOX PAGE = 1
ECanaMOTSRegsFile : > ECANA_MOTS PAGE = 1
ECanaMOTORegsFile : > ECANA_MOTO PAGE = 1
ECanbRegsFile : > ECANB, PAGE = 1
ECanbLAMRegsFile : > ECANB_LAM PAGE = 1
ECanbMboxesFile : > ECANB_MBOX PAGE = 1
ECanbMOTSRegsFile : > ECANB_MOTS PAGE = 1
ECanbMOTORegsFile : > ECANB_MOTO PAGE = 1
EPwm1RegsFile : > EPWM1 PAGE = 1
EPwm2RegsFile : > EPWM2 PAGE = 1
EPwm3RegsFile : > EPWM3 PAGE = 1
EPwm4RegsFile : > EPWM4 PAGE = 1
EPwm5RegsFile : > EPWM5 PAGE = 1
EPwm6RegsFile : > EPWM6 PAGE = 1
ECap1RegsFile : > ECAP1 PAGE = 1
ECap2RegsFile : > ECAP2 PAGE = 1
ECap3RegsFile : > ECAP3 PAGE = 1
ECap4RegsFile : > ECAP4 PAGE = 1
ECap5RegsFile : > ECAP5 PAGE = 1
ECap6RegsFile : > ECAP6 PAGE = 1
EQep1RegsFile : > EQEP1 PAGE = 1
EQep2RegsFile : > EQEP2 PAGE = 1
GpioCtrlRegsFile : > GPIOCTRL PAGE = 1
GpioDataRegsFile : > GPIODAT PAGE = 1
GpioIntRegsFile : > GPIOINT PAGE = 1
/*** Peripheral Frame 2 Register Structures ***/
SysCtrlRegsFile : > SYSTEM, PAGE = 1
SpiaRegsFile : > SPIA, PAGE = 1
SciaRegsFile : > SCIA, PAGE = 1
XIntruptRegsFile : > XINTRUPT, PAGE = 1
AdcRegsFile : > ADC, PAGE = 1
ScibRegsFile : > SCIB, PAGE = 1
ScicRegsFile : > SCIC, PAGE = 1
I2caRegsFile : > I2CA, PAGE = 1
/*** Code Security Module Register Structures ***/
CsmPwlFile : > CSM_PWL, PAGE = 1
/*** Device Part ID Register Structures ***/
PartIdRegsFile : > PARTID, PAGE = 1
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/

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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:52:13 $
//###########################################################################
//
// FILE: DSP2833x_EQep.h
//
// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module
// Register Bit Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_EQEP_H
#define DSP2833x_EQEP_H
#ifdef __cplusplus
extern "C" {
#endif
//----------------------------------------------------
// Capture decoder control register bit definitions */
struct QDECCTL_BITS { // bits description
Uint16 rsvd1:5; // 4:0 reserved
Uint16 QSP:1; // 5 QEPS input polarity
Uint16 QIP:1; // 6 QEPI input polarity
Uint16 QBP:1; // 7 QEPB input polarity
Uint16 QAP:1; // 8 QEPA input polarity
Uint16 IGATE:1; // 9 Index pulse gating option
Uint16 SWAP:1; // 10 CLK/DIR signal source for Position Counter
Uint16 XCR:1; // 11 External clock rate
Uint16 SPSEL:1; // 12 Sync output pin select
Uint16 SOEN:1; // 13 Enable position compare sync
Uint16 QSRC:2; // 15:14 Position counter source
};
union QDECCTL_REG {
Uint16 all;
struct QDECCTL_BITS bit;
};
//----------------------------------------------------
// QEP control register bit definitions */
struct QEPCTL_BITS { // bits description
Uint16 WDE:1; // 0 QEP watchdog enable
Uint16 UTE:1; // 1 QEP unit timer enable
Uint16 QCLM:1; // 2 QEP capture latch mode
Uint16 QPEN:1; // 3 Quadrature position counter enable
Uint16 IEL:2; // 5:4 Index event latch
Uint16 SEL:1; // 6 Strobe event latch
Uint16 SWI:1; // 7 Software init position counter
Uint16 IEI:2; // 9:8 Index event init of position count
Uint16 SEI:2; // 11:10 Strobe event init
Uint16 PCRM:2; // 13:12 Position counter reset
Uint16 FREE_SOFT:2; // 15:14 Emulation mode
};
union QEPCTL_REG {
Uint16 all;
struct QEPCTL_BITS bit;
};
//----------------------------------------------------
// Quadrature capture control register bit definitions */
struct QCAPCTL_BITS { // bits description
Uint16 UPPS:4; // 3:0 Unit position pre-scale
Uint16 CCPS:3; // 6:4 QEP capture timer pre-scale
Uint16 rsvd1:8; // 14:7 reserved
Uint16 CEN:1; // 15 Enable QEP capture
};
union QCAPCTL_REG {
Uint16 all;
struct QCAPCTL_BITS bit;
};
//----------------------------------------------------
// Position compare control register bit definitions */
struct QPOSCTL_BITS { // bits description
Uint16 PCSPW:12; // 11:0 Position compare sync pulse width
Uint16 PCE:1; // 12 Position compare enable/disable
Uint16 PCPOL:1; // 13 Polarity of sync output
Uint16 PCLOAD:1; // 14 Position compare of shadow load
Uint16 PCSHDW:1; // 15 Position compare shadow enable
};
union QPOSCTL_REG {
Uint16 all;
struct QPOSCTL_BITS bit;
};
//----------------------------------------------------
// QEP interrupt control register bit definitions */
struct QEINT_BITS { // bits description
Uint16 rsvd1:1; // 0 reserved
Uint16 PCE:1; // 1 Position counter error
Uint16 QPE:1; // 2 Quadrature phase error
Uint16 QDC:1; // 3 Quadrature dir change
Uint16 WTO:1; // 4 Watchdog timeout
Uint16 PCU:1; // 5 Position counter underflow
Uint16 PCO:1; // 6 Position counter overflow
Uint16 PCR:1; // 7 Position compare ready
Uint16 PCM:1; // 8 Position compare match
Uint16 SEL:1; // 9 Strobe event latch
Uint16 IEL:1; // 10 Event latch
Uint16 UTO:1; // 11 Unit timeout
Uint16 rsvd2:4; // 15:12 reserved
};
union QEINT_REG {
Uint16 all;
struct QEINT_BITS bit;
};
//----------------------------------------------------
// QEP interrupt status register bit definitions */
struct QFLG_BITS { // bits description
Uint16 INT:1; // 0 Global interrupt
Uint16 PCE:1; // 1 Position counter error
Uint16 PHE:1; // 2 Quadrature phase error
Uint16 QDC:1; // 3 Quadrature dir change
Uint16 WTO:1; // 4 Watchdog timeout
Uint16 PCU:1; // 5 Position counter underflow
Uint16 PCO:1; // 6 Position counter overflow
Uint16 PCR:1; // 7 Position compare ready
Uint16 PCM:1; // 8 Position compare match
Uint16 SEL:1; // 9 Strobe event latch
Uint16 IEL:1; // 10 Event latch
Uint16 UTO:1; // 11 Unit timeout
Uint16 rsvd2:4; // 15:12 reserved
};
union QFLG_REG {
Uint16 all;
struct QFLG_BITS bit;
};
//----------------------------------------------------
// QEP interrupt force register bit definitions */
struct QFRC_BITS { // bits description
Uint16 reserved:1; // 0 Reserved
Uint16 PCE:1; // 1 Position counter error
Uint16 PHE:1; // 2 Quadrature phase error
Uint16 QDC:1; // 3 Quadrature dir change
Uint16 WTO:1; // 4 Watchdog timeout
Uint16 PCU:1; // 5 Position counter underflow
Uint16 PCO:1; // 6 Position counter overflow
Uint16 PCR:1; // 7 Position compare ready
Uint16 PCM:1; // 8 Position compare match
Uint16 SEL:1; // 9 Strobe event latch
Uint16 IEL:1; // 10 Event latch
Uint16 UTO:1; // 11 Unit timeout
Uint16 rsvd2:4; // 15:12 reserved
};
union QFRC_REG {
Uint16 all;
struct QFRC_BITS bit;
};
// V1.1 Added UPEVNT (bit 7) This reflects changes
// made as of F2833x Rev A devices
//----------------------------------------------------
// QEP status register bit definitions */
struct QEPSTS_BITS { // bits description
Uint16 PCEF:1; // 0 Position counter error
Uint16 FIMF:1; // 1 First index marker
Uint16 CDEF:1; // 2 Capture direction error
Uint16 COEF:1; // 3 Capture overflow error
Uint16 QDLF:1; // 4 QEP direction latch
Uint16 QDF:1; // 5 Quadrature direction
Uint16 FIDF:1; // 6 Direction on first index marker
Uint16 UPEVNT:1; // 7 Unit position event flag
Uint16 rsvd1:8; // 15:8 reserved
};
union QEPSTS_REG {
Uint16 all;
struct QEPSTS_BITS bit;
};
//----------------------------------------------------
struct EQEP_REGS {
Uint32 QPOSCNT; // Position counter
Uint32 QPOSINIT; // Position counter init
Uint32 QPOSMAX; // Maximum position count
Uint32 QPOSCMP; // Position compare
Uint32 QPOSILAT; // Index position latch
Uint32 QPOSSLAT; // Strobe position latch
Uint32 QPOSLAT; // Position latch
Uint32 QUTMR; // Unit timer
Uint32 QUPRD; // Unit period
Uint16 QWDTMR; // QEP watchdog timer
Uint16 QWDPRD; // QEP watchdog period
union QDECCTL_REG QDECCTL; // Quadrature decoder control
union QEPCTL_REG QEPCTL; // QEP control
union QCAPCTL_REG QCAPCTL; // Quadrature capture control
union QPOSCTL_REG QPOSCTL; // Position compare control
union QEINT_REG QEINT; // QEP interrupt control
union QFLG_REG QFLG; // QEP interrupt flag
union QFLG_REG QCLR; // QEP interrupt clear
union QFRC_REG QFRC; // QEP interrupt force
union QEPSTS_REG QEPSTS; // QEP status
Uint16 QCTMR; // QEP capture timer
Uint16 QCPRD; // QEP capture period
Uint16 QCTMRLAT; // QEP capture latch
Uint16 QCPRDLAT; // QEP capture period latch
Uint16 rsvd1[30]; // reserved
};
//---------------------------------------------------------------------------
// GPI/O External References & Function Declarations:
//
extern volatile struct EQEP_REGS EQep1Regs;
extern volatile struct EQEP_REGS EQep2Regs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_EQEP_H definition
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/4 $
// Checkin $Date: November 15, 2007 09:58:53 $
//###########################################################################
//
// FILE: DSP2833x_Gpio.h
//
// TITLE: DSP2833x General Purpose I/O Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_GPIO_H
#define DSP2833x_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
//----------------------------------------------------
// GPIO A control register bit definitions */
struct GPACTRL_BITS { // bits description
Uint16 QUALPRD0:8; // 7:0 Qual period
Uint16 QUALPRD1:8; // 15:8 Qual period
Uint16 QUALPRD2:8; // 23:16 Qual period
Uint16 QUALPRD3:8; // 31:24 Qual period
};
union GPACTRL_REG {
Uint32 all;
struct GPACTRL_BITS bit;
};
//----------------------------------------------------
// GPIO B control register bit definitions */
struct GPBCTRL_BITS { // bits description
Uint16 QUALPRD0:8; // 7:0 Qual period
Uint16 QUALPRD1:8; // 15:8 Qual period
Uint16 QUALPRD2:8; // 23:16 Qual period
Uint16 QUALPRD3:8; // 31:24
};
union GPBCTRL_REG {
Uint32 all;
struct GPBCTRL_BITS bit;
};
//----------------------------------------------------
// GPIO A Qual/MUX select register bit definitions */
struct GPA1_BITS { // bits description
Uint16 GPIO0:2; // 1:0 GPIO0
Uint16 GPIO1:2; // 3:2 GPIO1
Uint16 GPIO2:2; // 5:4 GPIO2
Uint16 GPIO3:2; // 7:6 GPIO3
Uint16 GPIO4:2; // 9:8 GPIO4
Uint16 GPIO5:2; // 11:10 GPIO5
Uint16 GPIO6:2; // 13:12 GPIO6
Uint16 GPIO7:2; // 15:14 GPIO7
Uint16 GPIO8:2; // 17:16 GPIO8
Uint16 GPIO9:2; // 19:18 GPIO9
Uint16 GPIO10:2; // 21:20 GPIO10
Uint16 GPIO11:2; // 23:22 GPIO11
Uint16 GPIO12:2; // 25:24 GPIO12
Uint16 GPIO13:2; // 27:26 GPIO13
Uint16 GPIO14:2; // 29:28 GPIO14
Uint16 GPIO15:2; // 31:30 GPIO15
};
struct GPA2_BITS { // bits description
Uint16 GPIO16:2; // 1:0 GPIO16
Uint16 GPIO17:2; // 3:2 GPIO17
Uint16 GPIO18:2; // 5:4 GPIO18
Uint16 GPIO19:2; // 7:6 GPIO19
Uint16 GPIO20:2; // 9:8 GPIO20
Uint16 GPIO21:2; // 11:10 GPIO21
Uint16 GPIO22:2; // 13:12 GPIO22
Uint16 GPIO23:2; // 15:14 GPIO23
Uint16 GPIO24:2; // 17:16 GPIO24
Uint16 GPIO25:2; // 19:18 GPIO25
Uint16 GPIO26:2; // 21:20 GPIO26
Uint16 GPIO27:2; // 23:22 GPIO27
Uint16 GPIO28:2; // 25:24 GPIO28
Uint16 GPIO29:2; // 27:26 GPIO29
Uint16 GPIO30:2; // 29:28 GPIO30
Uint16 GPIO31:2; // 31:30 GPIO31
};
struct GPB1_BITS { // bits description
Uint16 GPIO32:2; // 1:0 GPIO32
Uint16 GPIO33:2; // 3:2 GPIO33
Uint16 GPIO34:2; // 5:4 GPIO34
Uint16 GPIO35:2; // 7:6 GPIO35
Uint16 GPIO36:2; // 9:8 GPIO36
Uint16 GPIO37:2; // 11:10 GPIO37
Uint16 GPIO38:2; // 13:12 GPIO38
Uint16 GPIO39:2; // 15:14 GPIO39
Uint16 GPIO40:2; // 17:16 GPIO40
Uint16 GPIO41:2; // 19:16 GPIO41
Uint16 GPIO42:2; // 21:20 GPIO42
Uint16 GPIO43:2; // 23:22 GPIO43
Uint16 GPIO44:2; // 25:24 GPIO44
Uint16 GPIO45:2; // 27:26 GPIO45
Uint16 GPIO46:2; // 29:28 GPIO46
Uint16 GPIO47:2; // 31:30 GPIO47
};
struct GPB2_BITS { // bits description
Uint16 GPIO48:2; // 1:0 GPIO48
Uint16 GPIO49:2; // 3:2 GPIO49
Uint16 GPIO50:2; // 5:4 GPIO50
Uint16 GPIO51:2; // 7:6 GPIO51
Uint16 GPIO52:2; // 9:8 GPIO52
Uint16 GPIO53:2; // 11:10 GPIO53
Uint16 GPIO54:2; // 13:12 GPIO54
Uint16 GPIO55:2; // 15:14 GPIO55
Uint16 GPIO56:2; // 17:16 GPIO56
Uint16 GPIO57:2; // 19:18 GPIO57
Uint16 GPIO58:2; // 21:20 GPIO58
Uint16 GPIO59:2; // 23:22 GPIO59
Uint16 GPIO60:2; // 25:24 GPIO60
Uint16 GPIO61:2; // 27:26 GPIO61
Uint16 GPIO62:2; // 29:28 GPIO62
Uint16 GPIO63:2; // 31:30 GPIO63
};
struct GPC1_BITS { // bits description
Uint16 GPIO64:2; // 1:0 GPIO64
Uint16 GPIO65:2; // 3:2 GPIO65
Uint16 GPIO66:2; // 5:4 GPIO66
Uint16 GPIO67:2; // 7:6 GPIO67
Uint16 GPIO68:2; // 9:8 GPIO68
Uint16 GPIO69:2; // 11:10 GPIO69
Uint16 GPIO70:2; // 13:12 GPIO70
Uint16 GPIO71:2; // 15:14 GPIO71
Uint16 GPIO72:2; // 17:16 GPIO72
Uint16 GPIO73:2; // 19:18 GPIO73
Uint16 GPIO74:2; // 21:20 GPIO74
Uint16 GPIO75:2; // 23:22 GPIO75
Uint16 GPIO76:2; // 25:24 GPIO76
Uint16 GPIO77:2; // 27:26 GPIO77
Uint16 GPIO78:2; // 29:28 GPIO78
Uint16 GPIO79:2; // 31:30 GPIO79
};
struct GPC2_BITS { // bits description
Uint16 GPIO80:2; // 1:0 GPIO80
Uint16 GPIO81:2; // 3:2 GPIO81
Uint16 GPIO82:2; // 5:4 GPIO82
Uint16 GPIO83:2; // 7:6 GPIO83
Uint16 GPIO84:2; // 9:8 GPIO84
Uint16 GPIO85:2; // 11:10 GPIO85
Uint16 GPIO86:2; // 13:12 GPIO86
Uint16 GPIO87:2; // 15:14 GPIO87
Uint16 rsvd:16; // 31:16 reserved
};
union GPA1_REG {
Uint32 all;
struct GPA1_BITS bit;
};
union GPA2_REG {
Uint32 all;
struct GPA2_BITS bit;
};
union GPB1_REG {
Uint32 all;
struct GPB1_BITS bit;
};
union GPB2_REG {
Uint32 all;
struct GPB2_BITS bit;
};
union GPC1_REG {
Uint32 all;
struct GPC1_BITS bit;
};
union GPC2_REG {
Uint32 all;
struct GPC2_BITS bit;
};
//----------------------------------------------------
// GPIO A DIR/TOGGLE/SET/CLEAR register bit definitions */
struct GPADAT_BITS { // bits description
Uint16 GPIO0:1; // 0 GPIO0
Uint16 GPIO1:1; // 1 GPIO1
Uint16 GPIO2:1; // 2 GPIO2
Uint16 GPIO3:1; // 3 GPIO3
Uint16 GPIO4:1; // 4 GPIO4
Uint16 GPIO5:1; // 5 GPIO5
Uint16 GPIO6:1; // 6 GPIO6
Uint16 GPIO7:1; // 7 GPIO7
Uint16 GPIO8:1; // 8 GPIO8
Uint16 GPIO9:1; // 9 GPIO9
Uint16 GPIO10:1; // 10 GPIO10
Uint16 GPIO11:1; // 11 GPIO11
Uint16 GPIO12:1; // 12 GPIO12
Uint16 GPIO13:1; // 13 GPIO13
Uint16 GPIO14:1; // 14 GPIO14
Uint16 GPIO15:1; // 15 GPIO15
Uint16 GPIO16:1; // 16 GPIO16
Uint16 GPIO17:1; // 17 GPIO17
Uint16 GPIO18:1; // 18 GPIO18
Uint16 GPIO19:1; // 19 GPIO19
Uint16 GPIO20:1; // 20 GPIO20
Uint16 GPIO21:1; // 21 GPIO21
Uint16 GPIO22:1; // 22 GPIO22
Uint16 GPIO23:1; // 23 GPIO23
Uint16 GPIO24:1; // 24 GPIO24
Uint16 GPIO25:1; // 25 GPIO25
Uint16 GPIO26:1; // 26 GPIO26
Uint16 GPIO27:1; // 27 GPIO27
Uint16 GPIO28:1; // 28 GPIO28
Uint16 GPIO29:1; // 29 GPIO29
Uint16 GPIO30:1; // 30 GPIO30
Uint16 GPIO31:1; // 31 GPIO31
};
struct GPBDAT_BITS { // bits description
Uint16 GPIO32:1; // 0 GPIO32
Uint16 GPIO33:1; // 1 GPIO33
Uint16 GPIO34:1; // 2 GPIO34
Uint16 GPIO35:1; // 3 GPIO35
Uint16 GPIO36:1; // 4 GPIO36
Uint16 GPIO37:1; // 5 GPIO37
Uint16 GPIO38:1; // 6 GPIO38
Uint16 GPIO39:1; // 7 GPIO39
Uint16 GPIO40:1; // 8 GPIO40
Uint16 GPIO41:1; // 9 GPIO41
Uint16 GPIO42:1; // 10 GPIO42
Uint16 GPIO43:1; // 11 GPIO43
Uint16 GPIO44:1; // 12 GPIO44
Uint16 GPIO45:1; // 13 GPIO45
Uint16 GPIO46:1; // 14 GPIO46
Uint16 GPIO47:1; // 15 GPIO47
Uint16 GPIO48:1; // 16 GPIO48
Uint16 GPIO49:1; // 17 GPIO49
Uint16 GPIO50:1; // 18 GPIO50
Uint16 GPIO51:1; // 19 GPIO51
Uint16 GPIO52:1; // 20 GPIO52
Uint16 GPIO53:1; // 21 GPIO53
Uint16 GPIO54:1; // 22 GPIO54
Uint16 GPIO55:1; // 23 GPIO55
Uint16 GPIO56:1; // 24 GPIO56
Uint16 GPIO57:1; // 25 GPIO57
Uint16 GPIO58:1; // 26 GPIO58
Uint16 GPIO59:1; // 27 GPIO59
Uint16 GPIO60:1; // 28 GPIO60
Uint16 GPIO61:1; // 29 GPIO61
Uint16 GPIO62:1; // 30 GPIO62
Uint16 GPIO63:1; // 31 GPIO63
};
struct GPCDAT_BITS { // bits description
Uint16 GPIO64:1; // 0 GPIO64
Uint16 GPIO65:1; // 1 GPIO65
Uint16 GPIO66:1; // 2 GPIO66
Uint16 GPIO67:1; // 3 GPIO67
Uint16 GPIO68:1; // 4 GPIO68
Uint16 GPIO69:1; // 5 GPIO69
Uint16 GPIO70:1; // 6 GPIO70
Uint16 GPIO71:1; // 7 GPIO71
Uint16 GPIO72:1; // 8 GPIO72
Uint16 GPIO73:1; // 9 GPIO73
Uint16 GPIO74:1; // 10 GPIO74
Uint16 GPIO75:1; // 11 GPIO75
Uint16 GPIO76:1; // 12 GPIO76
Uint16 GPIO77:1; // 13 GPIO77
Uint16 GPIO78:1; // 14 GPIO78
Uint16 GPIO79:1; // 15 GPIO79
Uint16 GPIO80:1; // 16 GPIO80
Uint16 GPIO81:1; // 17 GPIO81
Uint16 GPIO82:1; // 18 GPIO82
Uint16 GPIO83:1; // 19 GPIO83
Uint16 GPIO84:1; // 20 GPIO84
Uint16 GPIO85:1; // 21 GPIO85
Uint16 GPIO86:1; // 22 GPIO86
Uint16 GPIO87:1; // 23 GPIO87
Uint16 rsvd1:8; // 31:24 reserved
};
union GPADAT_REG {
Uint32 all;
struct GPADAT_BITS bit;
};
union GPBDAT_REG {
Uint32 all;
struct GPBDAT_BITS bit;
};
union GPCDAT_REG {
Uint32 all;
struct GPCDAT_BITS bit;
};
//----------------------------------------------------
// GPIO Xint1/XINT2/XNMI select register bit definitions */
struct GPIOXINT_BITS { // bits description
Uint16 GPIOSEL:5; // 4:0 Select GPIO interrupt input source
Uint16 rsvd1:11; // 15:5 reserved
};
union GPIOXINT_REG {
Uint16 all;
struct GPIOXINT_BITS bit;
};
struct GPIO_CTRL_REGS {
union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31)
union GPA1_REG GPAQSEL1; // GPIO A Qualifier Select 1 Register (GPIO0 to 15)
union GPA2_REG GPAQSEL2; // GPIO A Qualifier Select 2 Register (GPIO16 to 31)
union GPA1_REG GPAMUX1; // GPIO A Mux 1 Register (GPIO0 to 15)
union GPA2_REG GPAMUX2; // GPIO A Mux 2 Register (GPIO16 to 31)
union GPADAT_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31)
union GPADAT_REG GPAPUD; // GPIO A Pull Up Disable Register (GPIO0 to 31)
Uint32 rsvd1;
union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 63)
union GPB1_REG GPBQSEL1; // GPIO B Qualifier Select 1 Register (GPIO32 to 47)
union GPB2_REG GPBQSEL2; // GPIO B Qualifier Select 2 Register (GPIO48 to 63)
union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47)
union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63)
union GPBDAT_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63)
union GPBDAT_REG GPBPUD; // GPIO B Pull Up Disable Register (GPIO32 to 63)
Uint16 rsvd2[8];
union GPC1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79)
union GPC2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95)
union GPCDAT_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95)
union GPCDAT_REG GPCPUD; // GPIO C Pull Up Disable Register (GPIO64 to 95)
};
struct GPIO_DATA_REGS {
union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31)
union GPADAT_REG GPASET; // GPIO Data Set Register (GPIO0 to 31)
union GPADAT_REG GPACLEAR; // GPIO Data Clear Register (GPIO0 to 31)
union GPADAT_REG GPATOGGLE; // GPIO Data Toggle Register (GPIO0 to 31)
union GPBDAT_REG GPBDAT; // GPIO Data Register (GPIO32 to 63)
union GPBDAT_REG GPBSET; // GPIO Data Set Register (GPIO32 to 63)
union GPBDAT_REG GPBCLEAR; // GPIO Data Clear Register (GPIO32 to 63)
union GPBDAT_REG GPBTOGGLE; // GPIO Data Toggle Register (GPIO32 to 63)
union GPCDAT_REG GPCDAT; // GPIO Data Register (GPIO64 to 95)
union GPCDAT_REG GPCSET; // GPIO Data Set Register (GPIO64 to 95)
union GPCDAT_REG GPCCLEAR; // GPIO Data Clear Register (GPIO64 to 95)
union GPCDAT_REG GPCTOGGLE; // GPIO Data Toggle Register (GPIO64 to 95)
Uint16 rsvd1[8];
};
struct GPIO_INT_REGS {
union GPIOXINT_REG GPIOXINT1SEL; // XINT1 GPIO Input Selection
union GPIOXINT_REG GPIOXINT2SEL; // XINT2 GPIO Input Selection
union GPIOXINT_REG GPIOXNMISEL; // XNMI_Xint13 GPIO Input Selection
union GPIOXINT_REG GPIOXINT3SEL; // XINT3 GPIO Input Selection
union GPIOXINT_REG GPIOXINT4SEL; // XINT4 GPIO Input Selection
union GPIOXINT_REG GPIOXINT5SEL; // XINT5 GPIO Input Selection
union GPIOXINT_REG GPIOXINT6SEL; // XINT6 GPIO Input Selection
union GPIOXINT_REG GPIOXINT7SEL; // XINT7 GPIO Input Selection
union GPADAT_REG GPIOLPMSEL; // Low power modes GP I/O input select
};
//---------------------------------------------------------------------------
// GPI/O External References & Function Declarations:
//
extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs;
extern volatile struct GPIO_DATA_REGS GpioDataRegs;
extern volatile struct GPIO_INT_REGS GpioIntRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_GPIO_H definition
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/2 $
// Checkin $Date: March 22, 2007 10:40:22 $
//###########################################################################
//
// FILE: DSP2833x_I2c.h
//
// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module
// Register Bit Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_I2C_H
#define DSP2833x_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
//----------------------------------------------------
// I2C interrupt vector register bit definitions */
struct I2CISRC_BITS { // bits description
Uint16 INTCODE:3; // 2:0 Interrupt code
Uint16 rsvd1:13; // 15:3 reserved
};
union I2CISRC_REG {
Uint16 all;
struct I2CISRC_BITS bit;
};
//----------------------------------------------------
// I2C interrupt mask register bit definitions */
struct I2CIER_BITS { // bits description
Uint16 ARBL:1; // 0 Arbitration lost interrupt
Uint16 NACK:1; // 1 No ack interrupt
Uint16 ARDY:1; // 2 Register access ready interrupt
Uint16 RRDY:1; // 3 Recieve data ready interrupt
Uint16 XRDY:1; // 4 Transmit data ready interrupt
Uint16 SCD:1; // 5 Stop condition detection
Uint16 AAS:1; // 6 Address as slave
Uint16 rsvd:9; // 15:7 reserved
};
union I2CIER_REG {
Uint16 all;
struct I2CIER_BITS bit;
};
//----------------------------------------------------
// I2C status register bit definitions */
struct I2CSTR_BITS { // bits description
Uint16 ARBL:1; // 0 Arbitration lost interrupt
Uint16 NACK:1; // 1 No ack interrupt
Uint16 ARDY:1; // 2 Register access ready interrupt
Uint16 RRDY:1; // 3 Recieve data ready interrupt
Uint16 XRDY:1; // 4 Transmit data ready interrupt
Uint16 SCD:1; // 5 Stop condition detection
Uint16 rsvd1:2; // 7:6 reserved
Uint16 AD0:1; // 8 Address Zero
Uint16 AAS:1; // 9 Address as slave
Uint16 XSMT:1; // 10 XMIT shift empty
Uint16 RSFULL:1; // 11 Recieve shift full
Uint16 BB:1; // 12 Bus busy
Uint16 NACKSNT:1; // 13 A no ack sent
Uint16 SDIR:1; // 14 Slave direction
Uint16 rsvd2:1; // 15 reserved
};
union I2CSTR_REG {
Uint16 all;
struct I2CSTR_BITS bit;
};
//----------------------------------------------------
// I2C mode control register bit definitions */
struct I2CMDR_BITS { // bits description
Uint16 BC:3; // 2:0 Bit count
Uint16 FDF:1; // 3 Free data format
Uint16 STB:1; // 4 Start byte
Uint16 IRS:1; // 5 I2C Reset not
Uint16 DLB:1; // 6 Digital loopback
Uint16 RM:1; // 7 Repeat mode
Uint16 XA:1; // 8 Expand address
Uint16 TRX:1; // 9 Transmitter/reciever
Uint16 MST:1; // 10 Master/slave
Uint16 STP:1; // 11 Stop condition
Uint16 rsvd1:1; // 12 reserved
Uint16 STT:1; // 13 Start condition
Uint16 FREE:1; // 14 Emulation mode
Uint16 NACKMOD:1; // 15 No Ack mode
};
union I2CMDR_REG {
Uint16 all;
struct I2CMDR_BITS bit;
};
//----------------------------------------------------
// I2C pre-scaler register bit definitions */
struct I2CPSC_BITS { // bits description
Uint16 IPSC:8; // 7:0 pre-scaler
Uint16 rsvd1:8; // 15:8 reserved
};
union I2CPSC_REG {
Uint16 all;
struct I2CPSC_BITS bit;
};
//----------------------------------------------------
// TX FIFO control register bit definitions */
struct I2CFFTX_BITS { // bits description
Uint16 TXFFIL:5; // 4:0 FIFO interrupt level
Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable
Uint16 TXFFINTCLR:1; // 6 FIFO clear
Uint16 TXFFINT:1; // 7 FIFO interrupt flag
Uint16 TXFFST:5; // 12:8 FIFO level status
Uint16 TXFFRST:1; // 13 FIFO reset
Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs
Uint16 rsvd1:1; // 15 reserved
};
union I2CFFTX_REG {
Uint16 all;
struct I2CFFTX_BITS bit;
};
//----------------------------------------------------
// RX FIFO control register bit definitions */
struct I2CFFRX_BITS { // bits description
Uint16 RXFFIL:5; // 4:0 FIFO interrupt level
Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable
Uint16 RXFFINTCLR:1; // 6 FIFO clear
Uint16 RXFFINT:1; // 7 FIFO interrupt flag
Uint16 RXFFST:5; // 12:8 FIFO level
Uint16 RXFFRST:1; // 13 FIFO reset
Uint16 rsvd1:2; // 15:14 reserved
};
union I2CFFRX_REG {
Uint16 all;
struct I2CFFRX_BITS bit;
};
//----------------------------------------------------
struct I2C_REGS {
Uint16 I2COAR; // Own address register
union I2CIER_REG I2CIER; // Interrupt enable
union I2CSTR_REG I2CSTR; // Interrupt status
Uint16 I2CCLKL; // Clock divider low
Uint16 I2CCLKH; // Clock divider high
Uint16 I2CCNT; // Data count
Uint16 I2CDRR; // Data recieve
Uint16 I2CSAR; // Slave address
Uint16 I2CDXR; // Data transmit
union I2CMDR_REG I2CMDR; // Mode
union I2CISRC_REG I2CISRC; // Interrupt source
Uint16 rsvd1; // reserved
union I2CPSC_REG I2CPSC; // Pre-scaler
Uint16 rsvd2[19]; // reserved
union I2CFFTX_REG I2CFFTX; // Transmit FIFO
union I2CFFRX_REG I2CFFRX; // Recieve FIFO
};
//---------------------------------------------------------------------------
// External References & Function Declarations:
//
extern volatile struct I2C_REGS I2caRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_I2C_H definition
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/5 $
// Checkin $Date: May 14, 2008 16:30:31 $
//###########################################################################
//
// FILE: DSP2833x_Mcbsp.h
//
// TITLE: DSP2833x Device McBSP Register Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_MCBSP_H
#define DSP2833x_MCBSP_H
#ifdef __cplusplus
extern "C" {
#endif
//---------------------------------------------------------------------------
// McBSP Individual Register Bit Definitions:
//
// McBSP DRR2 register bit definitions:
struct DRR2_BITS { // bit description
Uint16 HWLB:8; // 16:23 High word low byte
Uint16 HWHB:8; // 24:31 High word high byte
};
union DRR2_REG {
Uint16 all;
struct DRR2_BITS bit;
};
// McBSP DRR1 register bit definitions:
struct DRR1_BITS { // bit description
Uint16 LWLB:8; // 16:23 Low word low byte
Uint16 LWHB:8; // 24:31 low word high byte
};
union DRR1_REG {
Uint16 all;
struct DRR1_BITS bit;
};
// McBSP DXR2 register bit definitions:
struct DXR2_BITS { // bit description
Uint16 HWLB:8; // 16:23 High word low byte
Uint16 HWHB:8; // 24:31 High word high byte
};
union DXR2_REG {
Uint16 all;
struct DXR2_BITS bit;
};
// McBSP DXR1 register bit definitions:
struct DXR1_BITS { // bit description
Uint16 LWLB:8; // 16:23 Low word low byte
Uint16 LWHB:8; // 24:31 low word high byte
};
union DXR1_REG {
Uint16 all;
struct DXR1_BITS bit;
};
// SPCR2 control register bit definitions:
struct SPCR2_BITS { // bit description
Uint16 XRST:1; // 0 transmit reset
Uint16 XRDY:1; // 1 transmit ready
Uint16 XEMPTY:1; // 2 Transmit empty
Uint16 XSYNCERR:1; // 3 Transmit syn errorINT flag
Uint16 XINTM:2; // 5:4 Transmit interrupt types
Uint16 GRST:1; // 6 CLKG reset
Uint16 FRST:1; // 7 Frame sync reset
Uint16 SOFT:1; // 8 SOFT bit
Uint16 FREE:1; // 9 FREE bit
Uint16 rsvd:6; // 15:10 reserved
};
union SPCR2_REG {
Uint16 all;
struct SPCR2_BITS bit;
};
// SPCR1 control register bit definitions:
struct SPCR1_BITS { // bit description
Uint16 RRST:1; // 0 Receive reset
Uint16 RRDY:1; // 1 Receive ready
Uint16 RFULL:1; // 2 Receive full
Uint16 RSYNCERR:1; // 7 Receive syn error
Uint16 RINTM:2; // 5:4 Receive interrupt types
Uint16 ABIS:1; // 6 ABIS mode select
Uint16 DXENA:1; // 7 DX hi-z enable
Uint16 rsvd:3; // 10:8 reserved
Uint16 CLKSTP:2; // 12:11 CLKSTOP mode bit
Uint16 RJUST:2; // 13:14 Right justified
Uint16 DLB:1; // 15 Digital loop back
};
union SPCR1_REG {
Uint16 all;
struct SPCR1_BITS bit;
};
// RCR2 control register bit definitions:
struct RCR2_BITS { // bit description
Uint16 RDATDLY:2; // 1:0 Receive data delay
Uint16 RFIG:1; // 2 Receive frame sync ignore
Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects
Uint16 RWDLEN2:3; // 7:5 Receive word length
Uint16 RFRLEN2:7; // 14:8 Receive Frame sync
Uint16 RPHASE:1; // 15 Receive Phase
};
union RCR2_REG {
Uint16 all;
struct RCR2_BITS bit;
};
// RCR1 control register bit definitions:
struct RCR1_BITS { // bit description
Uint16 rsvd1:5; // 4:0 reserved
Uint16 RWDLEN1:3; // 7:5 Receive word length
Uint16 RFRLEN1:7; // 14:8 Receive frame length
Uint16 rsvd2:1; // 15 reserved
};
union RCR1_REG {
Uint16 all;
struct RCR1_BITS bit;
};
// XCR2 control register bit definitions:
struct XCR2_BITS { // bit description
Uint16 XDATDLY:2; // 1:0 Transmit data delay
Uint16 XFIG:1; // 2 Transmit frame sync ignore
Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects
Uint16 XWDLEN2:3; // 7:5 Transmit word length
Uint16 XFRLEN2:7; // 14:8 Transmit Frame sync
Uint16 XPHASE:1; // 15 Transmit Phase
};
union XCR2_REG {
Uint16 all;
struct XCR2_BITS bit;
};
// XCR1 control register bit definitions:
struct XCR1_BITS { // bit description
Uint16 rsvd1:5; // 4:0 reserved
Uint16 XWDLEN1:3; // 7:5 Transmit word length
Uint16 XFRLEN1:7; // 14:8 Transmit frame length
Uint16 rsvd2:1; // 15 reserved
};
union XCR1_REG {
Uint16 all;
struct XCR1_BITS bit;
};
// SRGR2 Sample rate generator control register bit definitions:
struct SRGR2_BITS { // bit description
Uint16 FPER:12; // 11:0 Frame period
Uint16 FSGM:1; // 12 Frame sync generator mode
Uint16 CLKSM:1; // 13 Sample rate generator mode
Uint16 rsvd:1; // 14 reserved
Uint16 GSYNC:1; // 15 CLKG sync
};
union SRGR2_REG {
Uint16 all;
struct SRGR2_BITS bit;
};
// SRGR1 control register bit definitions:
struct SRGR1_BITS { // bit description
Uint16 CLKGDV:8; // 7:0 CLKG divider
Uint16 FWID:8; // 15:8 Frame width
};
union SRGR1_REG {
Uint16 all;
struct SRGR1_BITS bit;
};
// MCR2 Multichannel control register bit definitions:
struct MCR2_BITS { // bit description
Uint16 XMCM:2; // 1:0 Transmit multichannel mode
Uint16 XCBLK:3; // 2:4 Transmit current block
Uint16 XPABLK:2; // 5:6 Transmit partition A Block
Uint16 XPBBLK:2; // 7:8 Transmit partition B Block
Uint16 XMCME:1; // 9 Transmit multi-channel enhance mode
Uint16 rsvd:6; // 15:10 reserved
};
union MCR2_REG {
Uint16 all;
struct MCR2_BITS bit;
};
// MCR1 Multichannel control register bit definitions:
struct MCR1_BITS { // bit description
Uint16 RMCM:1; // 0 Receive multichannel mode
Uint16 rsvd:1; // 1 reserved
Uint16 RCBLK:3; // 4:2 Receive current block
Uint16 RPABLK:2; // 6:5 Receive partition A Block
Uint16 RPBBLK:2; // 7:8 Receive partition B Block
Uint16 RMCME:1; // 9 Receive multi-channel enhance mode
Uint16 rsvd1:6; // 15:10 reserved
};
union MCR1_REG {
Uint16 all;
struct MCR1_BITS bit;
};
// RCERA control register bit definitions:
struct RCERA_BITS { // bit description
Uint16 RCEA0:1; // 0 Receive Channel enable bit
Uint16 RCEA1:1; // 1 Receive Channel enable bit
Uint16 RCEA2:1; // 2 Receive Channel enable bit
Uint16 RCEA3:1; // 3 Receive Channel enable bit
Uint16 RCEA4:1; // 4 Receive Channel enable bit
Uint16 RCEA5:1; // 5 Receive Channel enable bit
Uint16 RCEA6:1; // 6 Receive Channel enable bit
Uint16 RCEA7:1; // 7 Receive Channel enable bit
Uint16 RCEA8:1; // 8 Receive Channel enable bit
Uint16 RCEA9:1; // 9 Receive Channel enable bit
Uint16 RCEA10:1; // 10 Receive Channel enable bit
Uint16 RCEA11:1; // 11 Receive Channel enable bit
Uint16 RCEA12:1; // 12 Receive Channel enable bit
Uint16 RCEA13:1; // 13 Receive Channel enable bit
Uint16 RCEA14:1; // 14 Receive Channel enable bit
Uint16 RCEA15:1; // 15 Receive Channel enable bit
};
union RCERA_REG {
Uint16 all;
struct RCERA_BITS bit;
};
// RCERB control register bit definitions:
struct RCERB_BITS { // bit description
Uint16 RCEB0:1; // 0 Receive Channel enable bit
Uint16 RCEB1:1; // 1 Receive Channel enable bit
Uint16 RCEB2:1; // 2 Receive Channel enable bit
Uint16 RCEB3:1; // 3 Receive Channel enable bit
Uint16 RCEB4:1; // 4 Receive Channel enable bit
Uint16 RCEB5:1; // 5 Receive Channel enable bit
Uint16 RCEB6:1; // 6 Receive Channel enable bit
Uint16 RCEB7:1; // 7 Receive Channel enable bit
Uint16 RCEB8:1; // 8 Receive Channel enable bit
Uint16 RCEB9:1; // 9 Receive Channel enable bit
Uint16 RCEB10:1; // 10 Receive Channel enable bit
Uint16 RCEB11:1; // 11 Receive Channel enable bit
Uint16 RCEB12:1; // 12 Receive Channel enable bit
Uint16 RCEB13:1; // 13 Receive Channel enable bit
Uint16 RCEB14:1; // 14 Receive Channel enable bit
Uint16 RCEB15:1; // 15 Receive Channel enable bit
};
union RCERB_REG {
Uint16 all;
struct RCERB_BITS bit;
};
// XCERA control register bit definitions:
struct XCERA_BITS { // bit description
Uint16 XCERA0:1; // 0 Receive Channel enable bit
Uint16 XCERA1:1; // 1 Receive Channel enable bit
Uint16 XCERA2:1; // 2 Receive Channel enable bit
Uint16 XCERA3:1; // 3 Receive Channel enable bit
Uint16 XCERA4:1; // 4 Receive Channel enable bit
Uint16 XCERA5:1; // 5 Receive Channel enable bit
Uint16 XCERA6:1; // 6 Receive Channel enable bit
Uint16 XCERA7:1; // 7 Receive Channel enable bit
Uint16 XCERA8:1; // 8 Receive Channel enable bit
Uint16 XCERA9:1; // 9 Receive Channel enable bit
Uint16 XCERA10:1; // 10 Receive Channel enable bit
Uint16 XCERA11:1; // 11 Receive Channel enable bit
Uint16 XCERA12:1; // 12 Receive Channel enable bit
Uint16 XCERA13:1; // 13 Receive Channel enable bit
Uint16 XCERA14:1; // 14 Receive Channel enable bit
Uint16 XCERA15:1; // 15 Receive Channel enable bit
};
union XCERA_REG {
Uint16 all;
struct XCERA_BITS bit;
};
// XCERB control register bit definitions:
struct XCERB_BITS { // bit description
Uint16 XCERB0:1; // 0 Receive Channel enable bit
Uint16 XCERB1:1; // 1 Receive Channel enable bit
Uint16 XCERB2:1; // 2 Receive Channel enable bit
Uint16 XCERB3:1; // 3 Receive Channel enable bit
Uint16 XCERB4:1; // 4 Receive Channel enable bit
Uint16 XCERB5:1; // 5 Receive Channel enable bit
Uint16 XCERB6:1; // 6 Receive Channel enable bit
Uint16 XCERB7:1; // 7 Receive Channel enable bit
Uint16 XCERB8:1; // 8 Receive Channel enable bit
Uint16 XCERB9:1; // 9 Receive Channel enable bit
Uint16 XCERB10:1; // 10 Receive Channel enable bit
Uint16 XCERB11:1; // 11 Receive Channel enable bit
Uint16 XCERB12:1; // 12 Receive Channel enable bit
Uint16 XCERB13:1; // 13 Receive Channel enable bit
Uint16 XCERB14:1; // 14 Receive Channel enable bit
Uint16 XCERB15:1; // 15 Receive Channel enable bit
};
union XCERB_REG {
Uint16 all;
struct XCERB_BITS bit;
};
// PCR control register bit definitions:
struct PCR_BITS { // bit description
Uint16 CLKRP:1; // 0 Receive Clock polarity
Uint16 CLKXP:1; // 1 Transmit clock polarity
Uint16 FSRP:1; // 2 Receive Frame synchronization polarity
Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity
Uint16 DR_STAT:1; // 4 DR pin status - reserved for this McBSP
Uint16 DX_STAT:1; // 5 DX pin status - reserved for this McBSP
Uint16 CLKS_STAT:1; // 6 CLKS pin status - reserved for 28x -McBSP
Uint16 SCLKME:1; // 7 Enhanced sample clock mode selection bit.
Uint16 CLKRM:1; // 8 Receiver Clock Mode
Uint16 CLKXM:1; // 9 Transmitter Clock Mode.
Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode
Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode
Uint16 RIOEN:1; // 12 General Purpose I/O Mode - reserved in this 28x-McBSP
Uint16 XIOEN:1; // 13 General Purpose I/O Mode - reserved in this 28x-McBSP
Uint16 IDEL_EN:1; // 14 reserved in this 28x-McBSP
Uint16 rsvd:1 ; // 15 reserved
};
union PCR_REG {
Uint16 all;
struct PCR_BITS bit;
};
// RCERC control register bit definitions:
struct RCERC_BITS { // bit description
Uint16 RCEC0:1; // 0 Receive Channel enable bit
Uint16 RCEC1:1; // 1 Receive Channel enable bit
Uint16 RCEC2:1; // 2 Receive Channel enable bit
Uint16 RCEC3:1; // 3 Receive Channel enable bit
Uint16 RCEC4:1; // 4 Receive Channel enable bit
Uint16 RCEC5:1; // 5 Receive Channel enable bit
Uint16 RCEC6:1; // 6 Receive Channel enable bit
Uint16 RCEC7:1; // 7 Receive Channel enable bit
Uint16 RCEC8:1; // 8 Receive Channel enable bit
Uint16 RCEC9:1; // 9 Receive Channel enable bit
Uint16 RCEC10:1; // 10 Receive Channel enable bit
Uint16 RCEC11:1; // 11 Receive Channel enable bit
Uint16 RCEC12:1; // 12 Receive Channel enable bit
Uint16 RCEC13:1; // 13 Receive Channel enable bit
Uint16 RCEC14:1; // 14 Receive Channel enable bit
Uint16 RCEC15:1; // 15 Receive Channel enable bit
};
union RCERC_REG {
Uint16 all;
struct RCERC_BITS bit;
};
// RCERD control register bit definitions:
struct RCERD_BITS { // bit description
Uint16 RCED0:1; // 0 Receive Channel enable bit
Uint16 RCED1:1; // 1 Receive Channel enable bit
Uint16 RCED2:1; // 2 Receive Channel enable bit
Uint16 RCED3:1; // 3 Receive Channel enable bit
Uint16 RCED4:1; // 4 Receive Channel enable bit
Uint16 RCED5:1; // 5 Receive Channel enable bit
Uint16 RCED6:1; // 6 Receive Channel enable bit
Uint16 RCED7:1; // 7 Receive Channel enable bit
Uint16 RCED8:1; // 8 Receive Channel enable bit
Uint16 RCED9:1; // 9 Receive Channel enable bit
Uint16 RCED10:1; // 10 Receive Channel enable bit
Uint16 RCED11:1; // 11 Receive Channel enable bit
Uint16 RCED12:1; // 12 Receive Channel enable bit
Uint16 RCED13:1; // 13 Receive Channel enable bit
Uint16 RCED14:1; // 14 Receive Channel enable bit
Uint16 RCED15:1; // 15 Receive Channel enable bit
};
union RCERD_REG {
Uint16 all;
struct RCERD_BITS bit;
};
// XCERC control register bit definitions:
struct XCERC_BITS { // bit description
Uint16 XCERC0:1; // 0 Receive Channel enable bit
Uint16 XCERC1:1; // 1 Receive Channel enable bit
Uint16 XCERC2:1; // 2 Receive Channel enable bit
Uint16 XCERC3:1; // 3 Receive Channel enable bit
Uint16 XCERC4:1; // 4 Receive Channel enable bit
Uint16 XCERC5:1; // 5 Receive Channel enable bit
Uint16 XCERC6:1; // 6 Receive Channel enable bit
Uint16 XCERC7:1; // 7 Receive Channel enable bit
Uint16 XCERC8:1; // 8 Receive Channel enable bit
Uint16 XCERC9:1; // 9 Receive Channel enable bit
Uint16 XCERC10:1; // 10 Receive Channel enable bit
Uint16 XCERC11:1; // 11 Receive Channel enable bit
Uint16 XCERC12:1; // 12 Receive Channel enable bit
Uint16 XCERC13:1; // 13 Receive Channel enable bit
Uint16 XCERC14:1; // 14 Receive Channel enable bit
Uint16 XCERC15:1; // 15 Receive Channel enable bit
};
union XCERC_REG {
Uint16 all;
struct XCERC_BITS bit;
};
// XCERD control register bit definitions:
struct XCERD_BITS { // bit description
Uint16 XCERD0:1; // 0 Receive Channel enable bit
Uint16 XCERD1:1; // 1 Receive Channel enable bit
Uint16 XCERD2:1; // 2 Receive Channel enable bit
Uint16 XCERD3:1; // 3 Receive Channel enable bit
Uint16 XCERD4:1; // 4 Receive Channel enable bit
Uint16 XCERD5:1; // 5 Receive Channel enable bit
Uint16 XCERD6:1; // 6 Receive Channel enable bit
Uint16 XCERD7:1; // 7 Receive Channel enable bit
Uint16 XCERD8:1; // 8 Receive Channel enable bit
Uint16 XCERD9:1; // 9 Receive Channel enable bit
Uint16 XCERD10:1; // 10 Receive Channel enable bit
Uint16 XCERD11:1; // 11 Receive Channel enable bit
Uint16 XCERD12:1; // 12 Receive Channel enable bit
Uint16 XCERD13:1; // 13 Receive Channel enable bit
Uint16 XCERD14:1; // 14 Receive Channel enable bit
Uint16 XCERD15:1; // 15 Receive Channel enable bit
};
union XCERD_REG {
Uint16 all;
struct XCERD_BITS bit;
};
// RCERE control register bit definitions:
struct RCERE_BITS { // bit description
Uint16 RCEE0:1; // 0 Receive Channel enable bit
Uint16 RCEE1:1; // 1 Receive Channel enable bit
Uint16 RCEE2:1; // 2 Receive Channel enable bit
Uint16 RCEE3:1; // 3 Receive Channel enable bit
Uint16 RCEE4:1; // 4 Receive Channel enable bit
Uint16 RCEE5:1; // 5 Receive Channel enable bit
Uint16 RCEE6:1; // 6 Receive Channel enable bit
Uint16 RCEE7:1; // 7 Receive Channel enable bit
Uint16 RCEE8:1; // 8 Receive Channel enable bit
Uint16 RCEE9:1; // 9 Receive Channel enable bit
Uint16 RCEE10:1; // 10 Receive Channel enable bit
Uint16 RCEE11:1; // 11 Receive Channel enable bit
Uint16 RCEE12:1; // 12 Receive Channel enable bit
Uint16 RCEE13:1; // 13 Receive Channel enable bit
Uint16 RCEE14:1; // 14 Receive Channel enable bit
Uint16 RCEE15:1; // 15 Receive Channel enable bit
};
union RCERE_REG {
Uint16 all;
struct RCERE_BITS bit;
};
// RCERF control register bit definitions:
struct RCERF_BITS { // bit description
Uint16 RCEF0:1; // 0 Receive Channel enable bit
Uint16 RCEF1:1; // 1 Receive Channel enable bit
Uint16 RCEF2:1; // 2 Receive Channel enable bit
Uint16 RCEF3:1; // 3 Receive Channel enable bit
Uint16 RCEF4:1; // 4 Receive Channel enable bit
Uint16 RCEF5:1; // 5 Receive Channel enable bit
Uint16 RCEF6:1; // 6 Receive Channel enable bit
Uint16 RCEF7:1; // 7 Receive Channel enable bit
Uint16 RCEF8:1; // 8 Receive Channel enable bit
Uint16 RCEF9:1; // 9 Receive Channel enable bit
Uint16 RCEF10:1; // 10 Receive Channel enable bit
Uint16 RCEF11:1; // 11 Receive Channel enable bit
Uint16 RCEF12:1; // 12 Receive Channel enable bit
Uint16 RCEF13:1; // 13 Receive Channel enable bit
Uint16 RCEF14:1; // 14 Receive Channel enable bit
Uint16 RCEF15:1; // 15 Receive Channel enable bit
};
union RCERF_REG {
Uint16 all;
struct RCERF_BITS bit;
};
// XCERE control register bit definitions:
struct XCERE_BITS { // bit description
Uint16 XCERE0:1; // 0 Receive Channel enable bit
Uint16 XCERE1:1; // 1 Receive Channel enable bit
Uint16 XCERE2:1; // 2 Receive Channel enable bit
Uint16 XCERE3:1; // 3 Receive Channel enable bit
Uint16 XCERE4:1; // 4 Receive Channel enable bit
Uint16 XCERE5:1; // 5 Receive Channel enable bit
Uint16 XCERE6:1; // 6 Receive Channel enable bit
Uint16 XCERE7:1; // 7 Receive Channel enable bit
Uint16 XCERE8:1; // 8 Receive Channel enable bit
Uint16 XCERE9:1; // 9 Receive Channel enable bit
Uint16 XCERE10:1; // 10 Receive Channel enable bit
Uint16 XCERE11:1; // 11 Receive Channel enable bit
Uint16 XCERE12:1; // 12 Receive Channel enable bit
Uint16 XCERE13:1; // 13 Receive Channel enable bit
Uint16 XCERE14:1; // 14 Receive Channel enable bit
Uint16 XCERE15:1; // 15 Receive Channel enable bit
};
union XCERE_REG {
Uint16 all;
struct XCERE_BITS bit;
};
// XCERF control register bit definitions:
struct XCERF_BITS { // bit description
Uint16 XCERF0:1; // 0 Receive Channel enable bit
Uint16 XCERF1:1; // 1 Receive Channel enable bit
Uint16 XCERF2:1; // 2 Receive Channel enable bit
Uint16 XCERF3:1; // 3 Receive Channel enable bit
Uint16 XCERF4:1; // 4 Receive Channel enable bit
Uint16 XCERF5:1; // 5 Receive Channel enable bit
Uint16 XCERF6:1; // 6 Receive Channel enable bit
Uint16 XCERF7:1; // 7 Receive Channel enable bit
Uint16 XCERF8:1; // 8 Receive Channel enable bit
Uint16 XCERF9:1; // 9 Receive Channel enable bit
Uint16 XCERF10:1; // 10 Receive Channel enable bit
Uint16 XCERF11:1; // 11 Receive Channel enable bit
Uint16 XCERF12:1; // 12 Receive Channel enable bit
Uint16 XCERF13:1; // 13 Receive Channel enable bit
Uint16 XCERF14:1; // 14 Receive Channel enable bit
Uint16 XCERF15:1; // 15 Receive Channel enable bit
};
union XCERF_REG {
Uint16 all;
struct XCERF_BITS bit;
};
// RCERG control register bit definitions:
struct RCERG_BITS { // bit description
Uint16 RCEG0:1; // 0 Receive Channel enable bit
Uint16 RCEG1:1; // 1 Receive Channel enable bit
Uint16 RCEG2:1; // 2 Receive Channel enable bit
Uint16 RCEG3:1; // 3 Receive Channel enable bit
Uint16 RCEG4:1; // 4 Receive Channel enable bit
Uint16 RCEG5:1; // 5 Receive Channel enable bit
Uint16 RCEG6:1; // 6 Receive Channel enable bit
Uint16 RCEG7:1; // 7 Receive Channel enable bit
Uint16 RCEG8:1; // 8 Receive Channel enable bit
Uint16 RCEG9:1; // 9 Receive Channel enable bit
Uint16 RCEG10:1; // 10 Receive Channel enable bit
Uint16 RCEG11:1; // 11 Receive Channel enable bit
Uint16 RCEG12:1; // 12 Receive Channel enable bit
Uint16 RCEG13:1; // 13 Receive Channel enable bit
Uint16 RCEG14:1; // 14 Receive Channel enable bit
Uint16 RCEG15:1; // 15 Receive Channel enable bit
};
union RCERG_REG {
Uint16 all;
struct RCERG_BITS bit;
};
// RCERH control register bit definitions:
struct RCERH_BITS { // bit description
Uint16 RCEH0:1; // 0 Receive Channel enable bit
Uint16 RCEH1:1; // 1 Receive Channel enable bit
Uint16 RCEH2:1; // 2 Receive Channel enable bit
Uint16 RCEH3:1; // 3 Receive Channel enable bit
Uint16 RCEH4:1; // 4 Receive Channel enable bit
Uint16 RCEH5:1; // 5 Receive Channel enable bit
Uint16 RCEH6:1; // 6 Receive Channel enable bit
Uint16 RCEH7:1; // 7 Receive Channel enable bit
Uint16 RCEH8:1; // 8 Receive Channel enable bit
Uint16 RCEH9:1; // 9 Receive Channel enable bit
Uint16 RCEH10:1; // 10 Receive Channel enable bit
Uint16 RCEH11:1; // 11 Receive Channel enable bit
Uint16 RCEH12:1; // 12 Receive Channel enable bit
Uint16 RCEH13:1; // 13 Receive Channel enable bit
Uint16 RCEH14:1; // 14 Receive Channel enable bit
Uint16 RCEH15:1; // 15 Receive Channel enable bit
};
union RCERH_REG {
Uint16 all;
struct RCERH_BITS bit;
};
// XCERG control register bit definitions:
struct XCERG_BITS { // bit description
Uint16 XCERG0:1; // 0 Receive Channel enable bit
Uint16 XCERG1:1; // 1 Receive Channel enable bit
Uint16 XCERG2:1; // 2 Receive Channel enable bit
Uint16 XCERG3:1; // 3 Receive Channel enable bit
Uint16 XCERG4:1; // 4 Receive Channel enable bit
Uint16 XCERG5:1; // 5 Receive Channel enable bit
Uint16 XCERG6:1; // 6 Receive Channel enable bit
Uint16 XCERG7:1; // 7 Receive Channel enable bit
Uint16 XCERG8:1; // 8 Receive Channel enable bit
Uint16 XCERG9:1; // 9 Receive Channel enable bit
Uint16 XCERG10:1; // 10 Receive Channel enable bit
Uint16 XCERG11:1; // 11 Receive Channel enable bit
Uint16 XCERG12:1; // 12 Receive Channel enable bit
Uint16 XCERG13:1; // 13 Receive Channel enable bit
Uint16 XCERG14:1; // 14 Receive Channel enable bit
Uint16 XCERG15:1; // 15 Receive Channel enable bit
};
union XCERG_REG {
Uint16 all;
struct XCERG_BITS bit;
};
// XCERH control register bit definitions:
struct XCERH_BITS { // bit description
Uint16 XCEH0:1; // 0 Receive Channel enable bit
Uint16 XCEH1:1; // 1 Receive Channel enable bit
Uint16 XCEH2:1; // 2 Receive Channel enable bit
Uint16 XCEH3:1; // 3 Receive Channel enable bit
Uint16 XCEH4:1; // 4 Receive Channel enable bit
Uint16 XCEH5:1; // 5 Receive Channel enable bit
Uint16 XCEH6:1; // 6 Receive Channel enable bit
Uint16 XCEH7:1; // 7 Receive Channel enable bit
Uint16 XCEH8:1; // 8 Receive Channel enable bit
Uint16 XCEH9:1; // 9 Receive Channel enable bit
Uint16 XCEH10:1; // 10 Receive Channel enable bit
Uint16 XCEH11:1; // 11 Receive Channel enable bit
Uint16 XCEH12:1; // 12 Receive Channel enable bit
Uint16 XCEH13:1; // 13 Receive Channel enable bit
Uint16 XCEH14:1; // 14 Receive Channel enable bit
Uint16 XCEH15:1; // 15 Receive Channel enable bit
};
union XCERH_REG {
Uint16 all;
struct XCERH_BITS bit;
};
// McBSP Interrupt enable register for RINT/XINT
struct MFFINT_BITS { // bits description
Uint16 XINT:1; // 0 XINT interrupt enable
Uint16 rsvd1:1; // 1 reserved
Uint16 RINT:1; // 2 RINT interrupt enable
Uint16 rsvd2:13; // 15:3 reserved
};
union MFFINT_REG {
Uint16 all;
struct MFFINT_BITS bit;
};
//---------------------------------------------------------------------------
// McBSP Register File:
//
struct MCBSP_REGS {
union DRR2_REG DRR2; // MCBSP Data receive register bits 31-16
union DRR1_REG DRR1; // MCBSP Data receive register bits 15-0
union DXR2_REG DXR2; // MCBSP Data transmit register bits 31-16
union DXR1_REG DXR1; // MCBSP Data transmit register bits 15-0
union SPCR2_REG SPCR2; // MCBSP control register bits 31-16
union SPCR1_REG SPCR1; // MCBSP control register bits 15-0
union RCR2_REG RCR2; // MCBSP receive control register bits 31-16
union RCR1_REG RCR1; // MCBSP receive control register bits 15-0
union XCR2_REG XCR2; // MCBSP transmit control register bits 31-16
union XCR1_REG XCR1; // MCBSP transmit control register bits 15-0
union SRGR2_REG SRGR2; // MCBSP sample rate gen register bits 31-16
union SRGR1_REG SRGR1; // MCBSP sample rate gen register bits 15-0
union MCR2_REG MCR2; // MCBSP multichannel register bits 31-16
union MCR1_REG MCR1; // MCBSP multichannel register bits 15-0
union RCERA_REG RCERA; // MCBSP Receive channel enable partition A
union RCERB_REG RCERB; // MCBSP Receive channel enable partition B
union XCERA_REG XCERA; // MCBSP Transmit channel enable partition A
union XCERB_REG XCERB; // MCBSP Transmit channel enable partition B
union PCR_REG PCR; // MCBSP Pin control register bits 15-0
union RCERC_REG RCERC; // MCBSP Receive channel enable partition C
union RCERD_REG RCERD; // MCBSP Receive channel enable partition D
union XCERC_REG XCERC; // MCBSP Transmit channel enable partition C
union XCERD_REG XCERD; // MCBSP Transmit channel enable partition D
union RCERE_REG RCERE; // MCBSP Receive channel enable partition E
union RCERF_REG RCERF; // MCBSP Receive channel enable partition F
union XCERE_REG XCERE; // MCBSP Transmit channel enable partition E
union XCERF_REG XCERF; // MCBSP Transmit channel enable partition F
union RCERG_REG RCERG; // MCBSP Receive channel enable partition G
union RCERH_REG RCERH; // MCBSP Receive channel enable partition H
union XCERG_REG XCERG; // MCBSP Transmit channel enable partition G
union XCERH_REG XCERH; // MCBSP Transmit channel enable partition H
Uint16 rsvd1[4]; // reserved
union MFFINT_REG MFFINT; // MCBSP Interrupt enable register for RINT/XINT
Uint16 rsvd2; // reserved
};
//---------------------------------------------------------------------------
// McBSP External References & Function Declarations:
//
extern volatile struct MCBSP_REGS McbspaRegs;
extern volatile struct MCBSP_REGS McbspbRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_MCBSP_H definition
//===========================================================================
// No more.
//===========================================================================

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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:52:24 $
//###########################################################################
//
// FILE: DSP2833x_PieCtrl.h
//
// TITLE: DSP2833x Device PIE Control Register Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_PIE_CTRL_H
#define DSP2833x_PIE_CTRL_H
#ifdef __cplusplus
extern "C" {
#endif
//---------------------------------------------------------------------------
// PIE Control Register Bit Definitions:
//
// PIECTRL: Register bit definitions:
struct PIECTRL_BITS { // bits description
Uint16 ENPIE:1; // 0 Enable PIE block
Uint16 PIEVECT:15; // 15:1 Fetched vector address
};
union PIECTRL_REG {
Uint16 all;
struct PIECTRL_BITS bit;
};
// PIEIER: Register bit definitions:
struct PIEIER_BITS { // bits description
Uint16 INTx1:1; // 0 INTx.1
Uint16 INTx2:1; // 1 INTx.2
Uint16 INTx3:1; // 2 INTx.3
Uint16 INTx4:1; // 3 INTx.4
Uint16 INTx5:1; // 4 INTx.5
Uint16 INTx6:1; // 5 INTx.6
Uint16 INTx7:1; // 6 INTx.7
Uint16 INTx8:1; // 7 INTx.8
Uint16 rsvd:8; // 15:8 reserved
};
union PIEIER_REG {
Uint16 all;
struct PIEIER_BITS bit;
};
// PIEIFR: Register bit definitions:
struct PIEIFR_BITS { // bits description
Uint16 INTx1:1; // 0 INTx.1
Uint16 INTx2:1; // 1 INTx.2
Uint16 INTx3:1; // 2 INTx.3
Uint16 INTx4:1; // 3 INTx.4
Uint16 INTx5:1; // 4 INTx.5
Uint16 INTx6:1; // 5 INTx.6
Uint16 INTx7:1; // 6 INTx.7
Uint16 INTx8:1; // 7 INTx.8
Uint16 rsvd:8; // 15:8 reserved
};
union PIEIFR_REG {
Uint16 all;
struct PIEIFR_BITS bit;
};
// PIEACK: Register bit definitions:
struct PIEACK_BITS { // bits description
Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1
Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2
Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3
Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4
Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5
Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6
Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7
Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8
Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9
Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10
Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11
Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12
Uint16 rsvd:4; // 15:12 reserved
};
union PIEACK_REG {
Uint16 all;
struct PIEACK_BITS bit;
};
//---------------------------------------------------------------------------
// PIE Control Register File:
//
struct PIE_CTRL_REGS {
union PIECTRL_REG PIECTRL; // PIE control register
union PIEACK_REG PIEACK; // PIE acknowledge
union PIEIER_REG PIEIER1; // PIE int1 IER register
union PIEIFR_REG PIEIFR1; // PIE int1 IFR register
union PIEIER_REG PIEIER2; // PIE INT2 IER register
union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register
union PIEIER_REG PIEIER3; // PIE INT3 IER register
union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register
union PIEIER_REG PIEIER4; // PIE INT4 IER register
union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register
union PIEIER_REG PIEIER5; // PIE INT5 IER register
union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register
union PIEIER_REG PIEIER6; // PIE INT6 IER register
union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register
union PIEIER_REG PIEIER7; // PIE INT7 IER register
union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register
union PIEIER_REG PIEIER8; // PIE INT8 IER register
union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register
union PIEIER_REG PIEIER9; // PIE INT9 IER register
union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register
union PIEIER_REG PIEIER10; // PIE int10 IER register
union PIEIFR_REG PIEIFR10; // PIE int10 IFR register
union PIEIER_REG PIEIER11; // PIE int11 IER register
union PIEIFR_REG PIEIFR11; // PIE int11 IFR register
union PIEIER_REG PIEIER12; // PIE int12 IER register
union PIEIFR_REG PIEIFR12; // PIE int12 IFR register
};
#define PIEACK_GROUP1 0x0001
#define PIEACK_GROUP2 0x0002
#define PIEACK_GROUP3 0x0004
#define PIEACK_GROUP4 0x0008
#define PIEACK_GROUP5 0x0010
#define PIEACK_GROUP6 0x0020
#define PIEACK_GROUP7 0x0040
#define PIEACK_GROUP8 0x0080
#define PIEACK_GROUP9 0x0100
#define PIEACK_GROUP10 0x0200
#define PIEACK_GROUP11 0x0400
#define PIEACK_GROUP12 0x0800
//---------------------------------------------------------------------------
// PIE Control Registers External References & Function Declarations:
//
extern volatile struct PIE_CTRL_REGS PieCtrlRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_PIE_CTRL_H definition
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/2 $
// Checkin $Date: March 16, 2007 09:00:21 $
//###########################################################################
//
// FILE: DSP2833x_PieVect.h
//
// TITLE: DSP2833x Devices PIE Vector Table Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_PIE_VECT_H
#define DSP2833x_PIE_VECT_H
#ifdef __cplusplus
extern "C" {
#endif
//---------------------------------------------------------------------------
// PIE Interrupt Vector Table Definition:
//
// Create a user type called PINT (pointer to interrupt):
typedef interrupt void(*PINT)(void);
// Define Vector Table:
struct PIE_VECT_TABLE {
// Reset is never fetched from this table.
// It will always be fetched from 0x3FFFC0 in
// boot ROM
PINT PIE1_RESERVED;
PINT PIE2_RESERVED;
PINT PIE3_RESERVED;
PINT PIE4_RESERVED;
PINT PIE5_RESERVED;
PINT PIE6_RESERVED;
PINT PIE7_RESERVED;
PINT PIE8_RESERVED;
PINT PIE9_RESERVED;
PINT PIE10_RESERVED;
PINT PIE11_RESERVED;
PINT PIE12_RESERVED;
PINT PIE13_RESERVED;
// Non-Peripheral Interrupts:
PINT XINT13; // XINT13 / CPU-Timer1
PINT TINT2; // CPU-Timer2
PINT DATALOG; // Datalogging interrupt
PINT RTOSINT; // RTOS interrupt
PINT EMUINT; // Emulation interrupt
PINT XNMI; // Non-maskable interrupt
PINT ILLEGAL; // Illegal operation TRAP
PINT USER1; // User Defined trap 1
PINT USER2; // User Defined trap 2
PINT USER3; // User Defined trap 3
PINT USER4; // User Defined trap 4
PINT USER5; // User Defined trap 5
PINT USER6; // User Defined trap 6
PINT USER7; // User Defined trap 7
PINT USER8; // User Defined trap 8
PINT USER9; // User Defined trap 9
PINT USER10; // User Defined trap 10
PINT USER11; // User Defined trap 11
PINT USER12; // User Defined trap 12
// Group 1 PIE Peripheral Vectors:
PINT SEQ1INT;
PINT SEQ2INT;
PINT rsvd1_3;
PINT XINT1;
PINT XINT2;
PINT ADCINT; // ADC
PINT TINT0; // Timer 0
PINT WAKEINT; // WD
// Group 2 PIE Peripheral Vectors:
PINT EPWM1_TZINT; // EPWM-1
PINT EPWM2_TZINT; // EPWM-2
PINT EPWM3_TZINT; // EPWM-3
PINT EPWM4_TZINT; // EPWM-4
PINT EPWM5_TZINT; // EPWM-5
PINT EPWM6_TZINT; // EPWM-6
PINT rsvd2_7;
PINT rsvd2_8;
// Group 3 PIE Peripheral Vectors:
PINT EPWM1_INT; // EPWM-1
PINT EPWM2_INT; // EPWM-2
PINT EPWM3_INT; // EPWM-3
PINT EPWM4_INT; // EPWM-4
PINT EPWM5_INT; // EPWM-5
PINT EPWM6_INT; // EPWM-6
PINT rsvd3_7;
PINT rsvd3_8;
// Group 4 PIE Peripheral Vectors:
PINT ECAP1_INT; // ECAP-1
PINT ECAP2_INT; // ECAP-2
PINT ECAP3_INT; // ECAP-3
PINT ECAP4_INT; // ECAP-4
PINT ECAP5_INT; // ECAP-5
PINT ECAP6_INT; // ECAP-6
PINT rsvd4_7;
PINT rsvd4_8;
// Group 5 PIE Peripheral Vectors:
PINT EQEP1_INT; // EQEP-1
PINT EQEP2_INT; // EQEP-2
PINT rsvd5_3;
PINT rsvd5_4;
PINT rsvd5_5;
PINT rsvd5_6;
PINT rsvd5_7;
PINT rsvd5_8;
// Group 6 PIE Peripheral Vectors:
PINT SPIRXINTA; // SPI-A
PINT SPITXINTA; // SPI-A
PINT MRINTB; // McBSP-B
PINT MXINTB; // McBSP-B
PINT MRINTA; // McBSP-A
PINT MXINTA; // McBSP-A
PINT rsvd6_7;
PINT rsvd6_8;
// Group 7 PIE Peripheral Vectors:
PINT DINTCH1; // DMA
PINT DINTCH2; // DMA
PINT DINTCH3; // DMA
PINT DINTCH4; // DMA
PINT DINTCH5; // DMA
PINT DINTCH6; // DMA
PINT rsvd7_7;
PINT rsvd7_8;
// Group 8 PIE Peripheral Vectors:
PINT I2CINT1A; // I2C-A
PINT I2CINT2A; // I2C-A
PINT rsvd8_3;
PINT rsvd8_4;
PINT SCIRXINTC; // SCI-C
PINT SCITXINTC; // SCI-C
PINT rsvd8_7;
PINT rsvd8_8;
// Group 9 PIE Peripheral Vectors:
PINT SCIRXINTA; // SCI-A
PINT SCITXINTA; // SCI-A
PINT SCIRXINTB; // SCI-B
PINT SCITXINTB; // SCI-B
PINT ECAN0INTA; // eCAN-A
PINT ECAN1INTA; // eCAN-A
PINT ECAN0INTB; // eCAN-B
PINT ECAN1INTB; // eCAN-B
// Group 10 PIE Peripheral Vectors:
PINT rsvd10_1;
PINT rsvd10_2;
PINT rsvd10_3;
PINT rsvd10_4;
PINT rsvd10_5;
PINT rsvd10_6;
PINT rsvd10_7;
PINT rsvd10_8;
// Group 11 PIE Peripheral Vectors:
PINT rsvd11_1;
PINT rsvd11_2;
PINT rsvd11_3;
PINT rsvd11_4;
PINT rsvd11_5;
PINT rsvd11_6;
PINT rsvd11_7;
PINT rsvd11_8;
// Group 12 PIE Peripheral Vectors:
PINT XINT3; // External interrupt
PINT XINT4;
PINT XINT5;
PINT XINT6;
PINT XINT7;
PINT rsvd12_6;
PINT LVF; // Latched overflow
PINT LUF; // Latched underflow
};
//---------------------------------------------------------------------------
// PIE Interrupt Vector Table External References & Function Declarations:
//
extern struct PIE_VECT_TABLE PieVectTable;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_PIE_VECT_H definition
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/2 $
// Checkin $Date: March 1, 2007 15:57:02 $
//###########################################################################
//
// FILE: DSP2833x_Sci.h
//
// TITLE: DSP2833x Device SCI Register Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_SCI_H
#define DSP2833x_SCI_H
#ifdef __cplusplus
extern "C" {
#endif
//---------------------------------------------------------------------------
// SCI Individual Register Bit Definitions
//----------------------------------------------------------
// SCICCR communication control register bit definitions:
//
struct SCICCR_BITS { // bit description
Uint16 SCICHAR:3; // 2:0 Character length control
Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control
Uint16 LOOPBKENA:1; // 4 Loop Back enable
Uint16 PARITYENA:1; // 5 Parity enable
Uint16 PARITY:1; // 6 Even or Odd Parity
Uint16 STOPBITS:1; // 7 Number of Stop Bits
Uint16 rsvd1:8; // 15:8 reserved
};
union SCICCR_REG {
Uint16 all;
struct SCICCR_BITS bit;
};
//-------------------------------------------
// SCICTL1 control register 1 bit definitions:
//
struct SCICTL1_BITS { // bit description
Uint16 RXENA:1; // 0 SCI receiver enable
Uint16 TXENA:1; // 1 SCI transmitter enable
Uint16 SLEEP:1; // 2 SCI sleep
Uint16 TXWAKE:1; // 3 Transmitter wakeup method
Uint16 rsvd:1; // 4 reserved
Uint16 SWRESET:1; // 5 Software reset
Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable
Uint16 rsvd1:9; // 15:7 reserved
};
union SCICTL1_REG {
Uint16 all;
struct SCICTL1_BITS bit;
};
//---------------------------------------------
// SCICTL2 control register 2 bit definitions:
//
struct SCICTL2_BITS { // bit description
Uint16 TXINTENA:1; // 0 Transmit interrupt enable
Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable
Uint16 rsvd:4; // 5:2 reserved
Uint16 TXEMPTY:1; // 6 Transmitter empty flag
Uint16 TXRDY:1; // 7 Transmitter ready flag
Uint16 rsvd1:8; // 15:8 reserved
};
union SCICTL2_REG {
Uint16 all;
struct SCICTL2_BITS bit;
};
//---------------------------------------------------
// SCIRXST Receiver status register bit definitions:
//
struct SCIRXST_BITS { // bit description
Uint16 rsvd:1; // 0 reserved
Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag
Uint16 PE:1; // 2 Parity error flag
Uint16 OE:1; // 3 Overrun error flag
Uint16 FE:1; // 4 Framing error flag
Uint16 BRKDT:1; // 5 Break-detect flag
Uint16 RXRDY:1; // 6 Receiver ready flag
Uint16 RXERROR:1; // 7 Receiver error flag
};
union SCIRXST_REG {
Uint16 all;
struct SCIRXST_BITS bit;
};
//----------------------------------------------------
// SCIRXBUF Receiver Data Buffer with FIFO bit definitions:
//
struct SCIRXBUF_BITS { // bits description
Uint16 RXDT:8; // 7:0 Receive word
Uint16 rsvd:6; // 13:8 reserved
Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode
Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode
};
union SCIRXBUF_REG {
Uint16 all;
struct SCIRXBUF_BITS bit;
};
//--------------------------------------------------
// SCIPRI Priority control register bit definitions:
//
//
struct SCIPRI_BITS { // bit description
Uint16 rsvd:3; // 2:0 reserved
Uint16 FREE:1; // 3 Free emulation suspend mode
Uint16 SOFT:1; // 4 Soft emulation suspend mode
Uint16 rsvd1:3; // 7:5 reserved
};
union SCIPRI_REG {
Uint16 all;
struct SCIPRI_BITS bit;
};
//-------------------------------------------------
// SCI FIFO Transmit register bit definitions:
//
//
struct SCIFFTX_BITS { // bit description
Uint16 TXFFIL:5; // 4:0 Interrupt level
Uint16 TXFFIENA:1; // 5 Interrupt enable
Uint16 TXFFINTCLR:1; // 6 Clear INT flag
Uint16 TXFFINT:1; // 7 INT flag
Uint16 TXFFST:5; // 12:8 FIFO status
Uint16 TXFIFOXRESET:1; // 13 FIFO reset
Uint16 SCIFFENA:1; // 14 Enhancement enable
Uint16 SCIRST:1; // 15 SCI reset rx/tx channels
};
union SCIFFTX_REG {
Uint16 all;
struct SCIFFTX_BITS bit;
};
//------------------------------------------------
// SCI FIFO recieve register bit definitions:
//
//
struct SCIFFRX_BITS { // bits description
Uint16 RXFFIL:5; // 4:0 Interrupt level
Uint16 RXFFIENA:1; // 5 Interrupt enable
Uint16 RXFFINTCLR:1; // 6 Clear INT flag
Uint16 RXFFINT:1; // 7 INT flag
Uint16 RXFFST:5; // 12:8 FIFO status
Uint16 RXFIFORESET:1; // 13 FIFO reset
Uint16 RXFFOVRCLR:1; // 14 Clear overflow
Uint16 RXFFOVF:1; // 15 FIFO overflow
};
union SCIFFRX_REG {
Uint16 all;
struct SCIFFRX_BITS bit;
};
// SCI FIFO control register bit definitions:
struct SCIFFCT_BITS { // bits description
Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay
Uint16 rsvd:5; // 12:8 reserved
Uint16 CDC:1; // 13 Auto baud mode enable
Uint16 ABDCLR:1; // 14 Auto baud clear
Uint16 ABD:1; // 15 Auto baud detect
};
union SCIFFCT_REG {
Uint16 all;
struct SCIFFCT_BITS bit;
};
//---------------------------------------------------------------------------
// SCI Register File:
//
struct SCI_REGS {
union SCICCR_REG SCICCR; // Communications control register
union SCICTL1_REG SCICTL1; // Control register 1
Uint16 SCIHBAUD; // Baud rate (high) register
Uint16 SCILBAUD; // Baud rate (low) register
union SCICTL2_REG SCICTL2; // Control register 2
union SCIRXST_REG SCIRXST; // Recieve status register
Uint16 SCIRXEMU; // Recieve emulation buffer register
union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer
Uint16 rsvd1; // reserved
Uint16 SCITXBUF; // Transmit data buffer
union SCIFFTX_REG SCIFFTX; // FIFO transmit register
union SCIFFRX_REG SCIFFRX; // FIFO recieve register
union SCIFFCT_REG SCIFFCT; // FIFO control register
Uint16 rsvd2; // reserved
Uint16 rsvd3; // reserved
union SCIPRI_REG SCIPRI; // FIFO Priority control
};
//---------------------------------------------------------------------------
// SCI External References & Function Declarations:
//
extern volatile struct SCI_REGS SciaRegs;
extern volatile struct SCI_REGS ScibRegs;
extern volatile struct SCI_REGS ScicRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_SCI_H definition
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/3 $
// Checkin $Date: April 17, 2008 11:08:27 $
//###########################################################################
//
// FILE: DSP2833x_Spi.h
//
// TITLE: DSP2833x Device SPI Register Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_SPI_H
#define DSP2833x_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
//---------------------------------------------------------------------------
// SPI Individual Register Bit Definitions:
//
// SPI FIFO Transmit register bit definitions:
struct SPIFFTX_BITS { // bit description
Uint16 TXFFIL:5; // 4:0 Interrupt level
Uint16 TXFFIENA:1; // 5 Interrupt enable
Uint16 TXFFINTCLR:1; // 6 Clear INT flag
Uint16 TXFFINT:1; // 7 INT flag
Uint16 TXFFST:5; // 12:8 FIFO status
Uint16 TXFIFO:1; // 13 FIFO reset
Uint16 SPIFFENA:1; // 14 Enhancement enable
Uint16 SPIRST:1; // 15 Reset SPI
};
union SPIFFTX_REG {
Uint16 all;
struct SPIFFTX_BITS bit;
};
//--------------------------------------------
// SPI FIFO recieve register bit definitions:
//
//
struct SPIFFRX_BITS { // bits description
Uint16 RXFFIL:5; // 4:0 Interrupt level
Uint16 RXFFIENA:1; // 5 Interrupt enable
Uint16 RXFFINTCLR:1; // 6 Clear INT flag
Uint16 RXFFINT:1; // 7 INT flag
Uint16 RXFFST:5; // 12:8 FIFO status
Uint16 RXFIFORESET:1; // 13 FIFO reset
Uint16 RXFFOVFCLR:1; // 14 Clear overflow
Uint16 RXFFOVF:1; // 15 FIFO overflow
};
union SPIFFRX_REG {
Uint16 all;
struct SPIFFRX_BITS bit;
};
//--------------------------------------------
// SPI FIFO control register bit definitions:
//
//
struct SPIFFCT_BITS { // bits description
Uint16 TXDLY:8; // 7:0 FIFO transmit delay
Uint16 rsvd:8; // 15:8 reserved
};
union SPIFFCT_REG {
Uint16 all;
struct SPIFFCT_BITS bit;
};
//---------------------------------------------
// SPI configuration register bit definitions:
//
//
struct SPICCR_BITS { // bits description
Uint16 SPICHAR:4; // 3:0 Character length control
Uint16 SPILBK:1; // 4 Loop-back enable/disable
Uint16 rsvd1:1; // 5 reserved
Uint16 CLKPOLARITY:1; // 6 Clock polarity
Uint16 SPISWRESET:1; // 7 SPI SW Reset
Uint16 rsvd2:8; // 15:8 reserved
};
union SPICCR_REG {
Uint16 all;
struct SPICCR_BITS bit;
};
//-------------------------------------------------
// SPI operation control register bit definitions:
//
//
struct SPICTL_BITS { // bits description
Uint16 SPIINTENA:1; // 0 Interrupt enable
Uint16 TALK:1; // 1 Master/Slave transmit enable
Uint16 MASTER_SLAVE:1; // 2 Network control mode
Uint16 CLK_PHASE:1; // 3 Clock phase select
Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable
Uint16 rsvd:11; // 15:5 reserved
};
union SPICTL_REG {
Uint16 all;
struct SPICTL_BITS bit;
};
//--------------------------------------
// SPI status register bit definitions:
//
//
struct SPISTS_BITS { // bits description
Uint16 rsvd1:5; // 4:0 reserved
Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag
Uint16 INT_FLAG:1; // 6 SPI interrupt flag
Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag
Uint16 rsvd2:8; // 15:8 reserved
};
union SPISTS_REG {
Uint16 all;
struct SPISTS_BITS bit;
};
//------------------------------------------------
// SPI priority control register bit definitions:
//
//
struct SPIPRI_BITS { // bits description
Uint16 rsvd1:4; // 3:0 reserved
Uint16 FREE:1; // 4 Free emulation mode control
Uint16 SOFT:1; // 5 Soft emulation mode control
Uint16 rsvd2:1; // 6 reserved
Uint16 rsvd3:9; // 15:7 reserved
};
union SPIPRI_REG {
Uint16 all;
struct SPIPRI_BITS bit;
};
//---------------------------------------------------------------------------
// SPI Register File:
//
struct SPI_REGS {
union SPICCR_REG SPICCR; // Configuration register
union SPICTL_REG SPICTL; // Operation control register
union SPISTS_REG SPISTS; // Status register
Uint16 rsvd1; // reserved
Uint16 SPIBRR; // Baud Rate
Uint16 rsvd2; // reserved
Uint16 SPIRXEMU; // Emulation buffer
Uint16 SPIRXBUF; // Serial input buffer
Uint16 SPITXBUF; // Serial output buffer
Uint16 SPIDAT; // Serial data
union SPIFFTX_REG SPIFFTX; // FIFO transmit register
union SPIFFRX_REG SPIFFRX; // FIFO recieve register
union SPIFFCT_REG SPIFFCT; // FIFO control register
Uint16 rsvd3[2]; // reserved
union SPIPRI_REG SPIPRI; // FIFO Priority control
};
//---------------------------------------------------------------------------
// SPI External References & Function Declarations:
//
extern volatile struct SPI_REGS SpiaRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_SPI_H definition
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/5 $
// Checkin $Date: May 12, 2008 09:34:58 $
//###########################################################################
//
// FILE: DSP2833x_SysCtrl.h
//
// TITLE: DSP2833x Device System Control Register Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_SYS_CTRL_H
#define DSP2833x_SYS_CTRL_H
#ifdef __cplusplus
extern "C" {
#endif
//---------------------------------------------------------------------------
// System Control Individual Register Bit Definitions:
//
// PLL Status Register
struct PLLSTS_BITS { // bits description
Uint16 PLLLOCKS:1; // 0 PLL lock status
Uint16 rsvd1:1; // 1 reserved
Uint16 PLLOFF:1; // 2 PLL off bit
Uint16 MCLKSTS:1; // 3 Missing clock status bit
Uint16 MCLKCLR:1; // 4 Missing clock clear bit
Uint16 OSCOFF:1; // 5 Oscillator clock off
Uint16 MCLKOFF:1; // 6 Missing clock detect
Uint16 DIVSEL:2; // 7 Divide Select
Uint16 rsvd2:7; // 15:7 reserved
};
union PLLSTS_REG {
Uint16 all;
struct PLLSTS_BITS bit;
};
// High speed peripheral clock register bit definitions:
struct HISPCP_BITS { // bits description
Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT
Uint16 rsvd1:13; // 15:3 reserved
};
union HISPCP_REG {
Uint16 all;
struct HISPCP_BITS bit;
};
// Low speed peripheral clock register bit definitions:
struct LOSPCP_BITS { // bits description
Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT
Uint16 rsvd1:13; // 15:3 reserved
};
union LOSPCP_REG {
Uint16 all;
struct LOSPCP_BITS bit;
};
// Peripheral clock control register 0 bit definitions:
struct PCLKCR0_BITS { // bits description
Uint16 rsvd1:2; // 1:0 reserved
Uint16 TBCLKSYNC:1; // 2 EWPM Module TBCLK enable/sync
Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC
Uint16 I2CAENCLK:1; // 4 Enable SYSCLKOUT to I2C-A
Uint16 SCICENCLK:1; // 5 Enalbe low speed clk to SCI-C
Uint16 rsvd2:2; // 7:6 reserved
Uint16 SPIAENCLK:1; // 8 Enable low speed clk to SPI-A
Uint16 rsvd3:1; // 9 reserved
Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A
Uint16 SCIBENCLK:1; // 11 Enable low speed clk to SCI-B
Uint16 MCBSPAENCLK:1; // 12 Enable low speed clk to McBSP-A
Uint16 MCBSPBENCLK:1; // 13 Enable low speed clk to McBSP-B
Uint16 ECANAENCLK:1; // 14 Enable system clk to eCAN-A
Uint16 ECANBENCLK:1; // 15 Enable system clk to eCAN-B
};
union PCLKCR0_REG {
Uint16 all;
struct PCLKCR0_BITS bit;
};
// Peripheral clock control register 1 bit definitions:
struct PCLKCR1_BITS { // bits description
Uint16 EPWM1ENCLK:1; // 0 Enable SYSCLKOUT to EPWM1
Uint16 EPWM2ENCLK:1; // 1 Enable SYSCLKOUT to EPWM2
Uint16 EPWM3ENCLK:1; // 2 Enable SYSCLKOUT to EPWM3
Uint16 EPWM4ENCLK:1; // 3 Enable SYSCLKOUT to EPWM4
Uint16 EPWM5ENCLK:1; // 4 Enable SYSCLKOUT to EPWM5
Uint16 EPWM6ENCLK:1; // 5 Enable SYSCLKOUT to EPWM6
Uint16 rsvd1:2; // 7:6 reserved
Uint16 ECAP1ENCLK:1; // 8 Enable SYSCLKOUT to ECAP1
Uint16 ECAP2ENCLK:1; // 9 Enable SYSCLKOUT to ECAP2
Uint16 ECAP3ENCLK:1; // 10 Enable SYSCLKOUT to ECAP3
Uint16 ECAP4ENCLK:1; // 11 Enable SYSCLKOUT to ECAP4
Uint16 ECAP5ENCLK:1; // 12 Enable SYSCLKOUT to ECAP5
Uint16 ECAP6ENCLK:1; // 13 Enable SYSCLKOUT to ECAP6
Uint16 EQEP1ENCLK:1; // 14 Enable SYSCLKOUT to EQEP1
Uint16 EQEP2ENCLK:1; // 15 Enable SYSCLKOUT to EQEP2
};
union PCLKCR1_REG {
Uint16 all;
struct PCLKCR1_BITS bit;
};
// Peripheral clock control register 2 bit definitions:
struct PCLKCR3_BITS { // bits description
Uint16 rsvd1:8; // 7:0 reserved
Uint16 CPUTIMER0ENCLK:1; // 8 Enable SYSCLKOUT to CPU-Timer 0
Uint16 CPUTIMER1ENCLK:1; // 9 Enable SYSCLKOUT to CPU-Timer 1
Uint16 CPUTIMER2ENCLK:1; // 10 Enable SYSCLKOUT to CPU-Timer 2
Uint16 DMAENCLK:1; // 11 Enable the DMA clock
Uint16 XINTFENCLK:1; // 12 Enable SYSCLKOUT to XINTF
Uint16 GPIOINENCLK:1; // Enable GPIO input clock
Uint16 rsvd2:2; // 15:14 reserved
};
union PCLKCR3_REG {
Uint16 all;
struct PCLKCR3_BITS bit;
};
// PLL control register bit definitions:
struct PLLCR_BITS { // bits description
Uint16 DIV:4; // 3:0 Set clock ratio for the PLL
Uint16 rsvd1:12; // 15:4 reserved
};
union PLLCR_REG {
Uint16 all;
struct PLLCR_BITS bit;
};
// Low Power Mode 0 control register bit definitions:
struct LPMCR0_BITS { // bits description
Uint16 LPM:2; // 1:0 Set the low power mode
Uint16 QUALSTDBY:6; // 7:2 Qualification
Uint16 rsvd1:7; // 14:8 reserved
Uint16 WDINTE:1; // 15 Enables WD to wake the device from STANDBY
};
union LPMCR0_REG {
Uint16 all;
struct LPMCR0_BITS bit;
};
// Dual-mapping configuration register bit definitions:
struct MAPCNF_BITS { // bits description
Uint16 MAPEPWM:1; // 0 EPWM dual-map enable
Uint16 rsvd1:15; // 15:1 reserved
};
union MAPCNF_REG {
Uint16 all;
struct MAPCNF_BITS bit;
};
//---------------------------------------------------------------------------
// System Control Register File:
//
struct SYS_CTRL_REGS {
Uint16 rsvd1; // 0
union PLLSTS_REG PLLSTS; // 1
Uint16 rsvd2[8]; // 2-9
union HISPCP_REG HISPCP; // 10: High-speed peripheral clock pre-scaler
union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler
union PCLKCR0_REG PCLKCR0; // 12: Peripheral clock control register
union PCLKCR1_REG PCLKCR1; // 13: Peripheral clock control register
union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0
Uint16 rsvd3; // 15: reserved
union PCLKCR3_REG PCLKCR3; // 16: Peripheral clock control register
union PLLCR_REG PLLCR; // 17: PLL control register
// No bit definitions are defined for SCSR because
// a read-modify-write instruction can clear the WDOVERRIDE bit
Uint16 SCSR; // 18: System control and status register
Uint16 WDCNTR; // 19: WD counter register
Uint16 rsvd4; // 20
Uint16 WDKEY; // 21: WD reset key register
Uint16 rsvd5[3]; // 22-24
// No bit definitions are defined for WDCR because
// the proper value must be written to the WDCHK field
// whenever writing to this register.
Uint16 WDCR; // 25: WD timer control register
Uint16 rsvd6[4]; // 26-29
union MAPCNF_REG MAPCNF; // 30: Dual-mapping configuration register
Uint16 rsvd7[1]; // 31
};
/* --------------------------------------------------- */
/* CSM Registers */
/* */
/* ----------------------------------------------------*/
/* CSM Status & Control register bit definitions */
struct CSMSCR_BITS { // bit description
Uint16 SECURE:1; // 0 Secure flag
Uint16 rsvd1:14; // 14-1 reserved
Uint16 FORCESEC:1; // 15 Force Secure control bit
};
/* Allow access to the bit fields or entire register */
union CSMSCR_REG {
Uint16 all;
struct CSMSCR_BITS bit;
};
/* CSM Register File */
struct CSM_REGS {
Uint16 KEY0; // KEY reg bits 15-0
Uint16 KEY1; // KEY reg bits 31-16
Uint16 KEY2; // KEY reg bits 47-32
Uint16 KEY3; // KEY reg bits 63-48
Uint16 KEY4; // KEY reg bits 79-64
Uint16 KEY5; // KEY reg bits 95-80
Uint16 KEY6; // KEY reg bits 111-96
Uint16 KEY7; // KEY reg bits 127-112
Uint16 rsvd1; // reserved
Uint16 rsvd2; // reserved
Uint16 rsvd3; // reserved
Uint16 rsvd4; // reserved
Uint16 rsvd5; // reserved
Uint16 rsvd6; // reserved
Uint16 rsvd7; // reserved
union CSMSCR_REG CSMSCR; // CSM Status & Control register
};
/* Password locations */
struct CSM_PWL {
Uint16 PSWD0; // PSWD bits 15-0
Uint16 PSWD1; // PSWD bits 31-16
Uint16 PSWD2; // PSWD bits 47-32
Uint16 PSWD3; // PSWD bits 63-48
Uint16 PSWD4; // PSWD bits 79-64
Uint16 PSWD5; // PSWD bits 95-80
Uint16 PSWD6; // PSWD bits 111-96
Uint16 PSWD7; // PSWD bits 127-112
};
/* Flash Registers */
#define FLASH_SLEEP 0x0000;
#define FLASH_STANDBY 0x0001;
#define FLASH_ACTIVE 0x0003;
/* Flash Option Register bit definitions */
struct FOPT_BITS { // bit description
Uint16 ENPIPE:1; // 0 Enable Pipeline Mode
Uint16 rsvd:15; // 1-15 reserved
};
/* Allow access to the bit fields or entire register */
union FOPT_REG {
Uint16 all;
struct FOPT_BITS bit;
};
/* Flash Power Modes Register bit definitions */
struct FPWR_BITS { // bit description
Uint16 PWR:2; // 0-1 Power Mode bits
Uint16 rsvd:14; // 2-15 reserved
};
/* Allow access to the bit fields or entire register */
union FPWR_REG {
Uint16 all;
struct FPWR_BITS bit;
};
/* Flash Status Register bit definitions */
struct FSTATUS_BITS { // bit description
Uint16 PWRS:2; // 0-1 Power Mode Status bits
Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits
Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits
Uint16 rsvd1:4; // 4-7 reserved
Uint16 V3STAT:1; // 8 VDD3V Status Latch bit
Uint16 rsvd2:7; // 9-15 reserved
};
/* Allow access to the bit fields or entire register */
union FSTATUS_REG {
Uint16 all;
struct FSTATUS_BITS bit;
};
/* Flash Sleep to Standby Wait Counter Register bit definitions */
struct FSTDBYWAIT_BITS { // bit description
Uint16 STDBYWAIT:9; // 0-8 Bank/Pump Sleep to Standby Wait Count bits
Uint16 rsvd:7; // 9-15 reserved
};
/* Allow access to the bit fields or entire register */
union FSTDBYWAIT_REG {
Uint16 all;
struct FSTDBYWAIT_BITS bit;
};
/* Flash Standby to Active Wait Counter Register bit definitions */
struct FACTIVEWAIT_BITS { // bit description
Uint16 ACTIVEWAIT:9; // 0-8 Bank/Pump Standby to Active Wait Count bits
Uint16 rsvd:7; // 9-15 reserved
};
/* Allow access to the bit fields or entire register */
union FACTIVEWAIT_REG {
Uint16 all;
struct FACTIVEWAIT_BITS bit;
};
/* Bank Read Access Wait State Register bit definitions */
struct FBANKWAIT_BITS { // bit description
Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits
Uint16 rsvd1:4; // 4-7 reserved
Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits
Uint16 rsvd2:4; // 12-15 reserved
};
/* Allow access to the bit fields or entire register */
union FBANKWAIT_REG {
Uint16 all;
struct FBANKWAIT_BITS bit;
};
/* OTP Read Access Wait State Register bit definitions */
struct FOTPWAIT_BITS { // bit description
Uint16 OTPWAIT:5; // 0-4 OTP Read Wait State bits
Uint16 rsvd:11; // 5-15 reserved
};
/* Allow access to the bit fields or entire register */
union FOTPWAIT_REG {
Uint16 all;
struct FOTPWAIT_BITS bit;
};
struct FLASH_REGS {
union FOPT_REG FOPT; // Option Register
Uint16 rsvd1; // reserved
union FPWR_REG FPWR; // Power Modes Register
union FSTATUS_REG FSTATUS; // Status Register
union FSTDBYWAIT_REG FSTDBYWAIT; // Pump/Bank Sleep to Standby Wait State Register
union FACTIVEWAIT_REG FACTIVEWAIT; // Pump/Bank Standby to Active Wait State Register
union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register
union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register
};
//---------------------------------------------------------------------------
// System Control External References & Function Declarations:
//
extern volatile struct SYS_CTRL_REGS SysCtrlRegs;
extern volatile struct CSM_REGS CsmRegs;
extern volatile struct CSM_PWL CsmPwl;
extern volatile struct FLASH_REGS FlashRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_SYS_CTRL_H definition
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:52:39 $
//###########################################################################
//
// FILE: DSP2833x_XIntrupt.h
//
// TITLE: DSP2833x Device External Interrupt Register Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_XINTRUPT_H
#define DSP2833x_XINTRUPT_H
#ifdef __cplusplus
extern "C" {
#endif
//---------------------------------------------------------------------------
struct XINTCR_BITS {
Uint16 ENABLE:1; // 0 enable/disable
Uint16 rsvd1:1; // 1 reserved
Uint16 POLARITY:2; // 3:2 pos/neg, both triggered
Uint16 rsvd2:12; //15:4 reserved
};
union XINTCR_REG {
Uint16 all;
struct XINTCR_BITS bit;
};
struct XNMICR_BITS {
Uint16 ENABLE:1; // 0 enable/disable
Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to int13
Uint16 POLARITY:2; // 3:2 pos/neg, or both triggered
Uint16 rsvd2:12; // 15:4 reserved
};
union XNMICR_REG {
Uint16 all;
struct XNMICR_BITS bit;
};
//---------------------------------------------------------------------------
// External Interrupt Register File:
//
struct XINTRUPT_REGS {
union XINTCR_REG XINT1CR;
union XINTCR_REG XINT2CR;
union XINTCR_REG XINT3CR;
union XINTCR_REG XINT4CR;
union XINTCR_REG XINT5CR;
union XINTCR_REG XINT6CR;
union XINTCR_REG XINT7CR;
union XNMICR_REG XNMICR;
Uint16 XINT1CTR;
Uint16 XINT2CTR;
Uint16 rsvd[5];
Uint16 XNMICTR;
};
//---------------------------------------------------------------------------
// External Interrupt References & Function Declarations:
//
extern volatile struct XINTRUPT_REGS XIntruptRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_XINTF_H definition
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/3 $
// Checkin $Date: March 20, 2007 16:34:08 $
//###########################################################################
//
// FILE: DSP2833x_Xintf.h
//
// TITLE: DSP2833x Device External Interface Register Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_XINTF_H
#define DSP2833x_XINTF_H
#ifdef __cplusplus
extern "C" {
#endif
// XINTF timing register bit definitions:
struct XTIMING_BITS { // bits description
Uint16 XWRTRAIL:2; // 1:0 Write access trail timing
Uint16 XWRACTIVE:3; // 4:2 Write access active timing
Uint16 XWRLEAD:2; // 6:5 Write access lead timing
Uint16 XRDTRAIL:2; // 8:7 Read access trail timing
Uint16 XRDACTIVE:3; // 11:9 Read access active timing
Uint16 XRDLEAD:2; // 13:12 Read access lead timing
Uint16 USEREADY:1; // 14 Extend access using HW waitstates
Uint16 READYMODE:1; // 15 Ready mode
Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b
Uint16 rsvd1:4; // 21:18 reserved
Uint16 X2TIMING:1; // 22 Double lead/active/trail timing
Uint16 rsvd3:9; // 31:23 reserved
};
union XTIMING_REG {
Uint32 all;
struct XTIMING_BITS bit;
};
// XINTF control register bit definitions:
struct XINTCNF2_BITS { // bits description
Uint16 WRBUFF:2; // 1:0 Write buffer depth
Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK
Uint16 CLKOFF:1; // 3 Disable XCLKOUT
Uint16 rsvd1:2; // 5:4 reserved
Uint16 WLEVEL:2; // 7:6 Current level of the write buffer
Uint16 rsvd2:1; // 8 reserved
Uint16 HOLD:1; // 9 Hold enable/disable
Uint16 HOLDS:1; // 10 Current state of HOLDn input
Uint16 HOLDAS:1; // 11 Current state of HOLDAn output
Uint16 rsvd3:4; // 15:12 reserved
Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK
Uint16 rsvd4:13; // 31:19 reserved
};
union XINTCNF2_REG {
Uint32 all;
struct XINTCNF2_BITS bit;
};
// XINTF bank switching register bit definitions:
struct XBANK_BITS { // bits description
Uint16 BANK:3; // 2:0 Zone for which banking is enabled
Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add
Uint16 rsvd:10; // 15:6 reserved
};
union XBANK_REG {
Uint16 all;
struct XBANK_BITS bit;
};
struct XRESET_BITS {
Uint16 XHARDRESET:1;
Uint16 rsvd1:15;
};
union XRESET_REG {
Uint16 all;
struct XBANK_BITS bit;
};
//---------------------------------------------------------------------------
// XINTF Register File:
//
struct XINTF_REGS {
union XTIMING_REG XTIMING0;
Uint32 rsvd1[5];
union XTIMING_REG XTIMING6;
union XTIMING_REG XTIMING7;
Uint32 rsvd2[2];
union XINTCNF2_REG XINTCNF2;
Uint32 rsvd3;
union XBANK_REG XBANK;
Uint16 rsvd4;
Uint16 XREVISION;
Uint16 rsvd5[2];
union XRESET_REG XRESET;
};
//---------------------------------------------------------------------------
// XINTF External References & Function Declarations:
//
extern volatile struct XINTF_REGS XintfRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_XINTF_H definition
//===========================================================================
// No more.
//===========================================================================

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// TI File $Revision: /main/4 $
// Checkin $Date: June 2, 2008 11:12:33 $
//###########################################################################
//
// FILE: DSP2833x_GlobalVariableDefs.c
//
// TITLE: DSP2833x Global Variables and Data Section Pragmas.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
//---------------------------------------------------------------------------
// Define Global Peripheral Variables:
//
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("AdcRegsFile")
#else
#pragma DATA_SECTION(AdcRegs,"AdcRegsFile");
#endif
volatile struct ADC_REGS AdcRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("AdcMirrorFile")
#else
#pragma DATA_SECTION(AdcMirror,"AdcMirrorFile");
#endif
volatile struct ADC_RESULT_MIRROR_REGS AdcMirror;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("CpuTimer0RegsFile")
#else
#pragma DATA_SECTION(CpuTimer0Regs,"CpuTimer0RegsFile");
#endif
volatile struct CPUTIMER_REGS CpuTimer0Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("CpuTimer1RegsFile")
#else
#pragma DATA_SECTION(CpuTimer1Regs,"CpuTimer1RegsFile");
#endif
volatile struct CPUTIMER_REGS CpuTimer1Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("CpuTimer2RegsFile")
#else
#pragma DATA_SECTION(CpuTimer2Regs,"CpuTimer2RegsFile");
#endif
volatile struct CPUTIMER_REGS CpuTimer2Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("CsmPwlFile")
#else
#pragma DATA_SECTION(CsmPwl,"CsmPwlFile");
#endif
volatile struct CSM_PWL CsmPwl;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("CsmRegsFile")
#else
#pragma DATA_SECTION(CsmRegs,"CsmRegsFile");
#endif
volatile struct CSM_REGS CsmRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("DevEmuRegsFile")
#else
#pragma DATA_SECTION(DevEmuRegs,"DevEmuRegsFile");
#endif
volatile struct DEV_EMU_REGS DevEmuRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("DmaRegsFile")
#else
#pragma DATA_SECTION(DmaRegs,"DmaRegsFile");
#endif
volatile struct DMA_REGS DmaRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("ECanaRegsFile")
#else
#pragma DATA_SECTION(ECanaRegs,"ECanaRegsFile");
#endif
volatile struct ECAN_REGS ECanaRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("ECanaMboxesFile")
#else
#pragma DATA_SECTION(ECanaMboxes,"ECanaMboxesFile");
#endif
volatile struct ECAN_MBOXES ECanaMboxes;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("ECanaLAMRegsFile")
#else
#pragma DATA_SECTION(ECanaLAMRegs,"ECanaLAMRegsFile");
#endif
volatile struct LAM_REGS ECanaLAMRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("ECanaMOTSRegsFile")
#else
#pragma DATA_SECTION(ECanaMOTSRegs,"ECanaMOTSRegsFile");
#endif
volatile struct MOTS_REGS ECanaMOTSRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("ECanaMOTORegsFile")
#else
#pragma DATA_SECTION(ECanaMOTORegs,"ECanaMOTORegsFile");
#endif
volatile struct MOTO_REGS ECanaMOTORegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("ECanbRegsFile")
#else
#pragma DATA_SECTION(ECanbRegs,"ECanbRegsFile");
#endif
volatile struct ECAN_REGS ECanbRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("ECanbMboxesFile")
#else
#pragma DATA_SECTION(ECanbMboxes,"ECanbMboxesFile");
#endif
volatile struct ECAN_MBOXES ECanbMboxes;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("ECanbLAMRegsFile")
#else
#pragma DATA_SECTION(ECanbLAMRegs,"ECanbLAMRegsFile");
#endif
volatile struct LAM_REGS ECanbLAMRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("ECanbMOTSRegsFile")
#else
#pragma DATA_SECTION(ECanbMOTSRegs,"ECanbMOTSRegsFile");
#endif
volatile struct MOTS_REGS ECanbMOTSRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("ECanbMOTORegsFile")
#else
#pragma DATA_SECTION(ECanbMOTORegs,"ECanbMOTORegsFile");
#endif
volatile struct MOTO_REGS ECanbMOTORegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("EPwm1RegsFile")
#else
#pragma DATA_SECTION(EPwm1Regs,"EPwm1RegsFile");
#endif
volatile struct EPWM_REGS EPwm1Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("EPwm2RegsFile")
#else
#pragma DATA_SECTION(EPwm2Regs,"EPwm2RegsFile");
#endif
volatile struct EPWM_REGS EPwm2Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("EPwm3RegsFile")
#else
#pragma DATA_SECTION(EPwm3Regs,"EPwm3RegsFile");
#endif
volatile struct EPWM_REGS EPwm3Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("EPwm4RegsFile")
#else
#pragma DATA_SECTION(EPwm4Regs,"EPwm4RegsFile");
#endif
volatile struct EPWM_REGS EPwm4Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("EPwm5RegsFile")
#else
#pragma DATA_SECTION(EPwm5Regs,"EPwm5RegsFile");
#endif
volatile struct EPWM_REGS EPwm5Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("EPwm6RegsFile")
#else
#pragma DATA_SECTION(EPwm6Regs,"EPwm6RegsFile");
#endif
volatile struct EPWM_REGS EPwm6Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("ECap1RegsFile")
#else
#pragma DATA_SECTION(ECap1Regs,"ECap1RegsFile");
#endif
volatile struct ECAP_REGS ECap1Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("ECap2RegsFile")
#else
#pragma DATA_SECTION(ECap2Regs,"ECap2RegsFile");
#endif
volatile struct ECAP_REGS ECap2Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("ECap3RegsFile")
#else
#pragma DATA_SECTION(ECap3Regs,"ECap3RegsFile");
#endif
volatile struct ECAP_REGS ECap3Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("ECap4RegsFile")
#else
#pragma DATA_SECTION(ECap4Regs,"ECap4RegsFile");
#endif
volatile struct ECAP_REGS ECap4Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("ECap5RegsFile")
#else
#pragma DATA_SECTION(ECap5Regs,"ECap5RegsFile");
#endif
volatile struct ECAP_REGS ECap5Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("ECap6RegsFile")
#else
#pragma DATA_SECTION(ECap6Regs,"ECap6RegsFile");
#endif
volatile struct ECAP_REGS ECap6Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("EQep1RegsFile")
#else
#pragma DATA_SECTION(EQep1Regs,"EQep1RegsFile");
#endif
volatile struct EQEP_REGS EQep1Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("EQep2RegsFile")
#else
#pragma DATA_SECTION(EQep2Regs,"EQep2RegsFile");
#endif
volatile struct EQEP_REGS EQep2Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("GpioCtrlRegsFile")
#else
#pragma DATA_SECTION(GpioCtrlRegs,"GpioCtrlRegsFile");
#endif
volatile struct GPIO_CTRL_REGS GpioCtrlRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("GpioDataRegsFile")
#else
#pragma DATA_SECTION(GpioDataRegs,"GpioDataRegsFile");
#endif
volatile struct GPIO_DATA_REGS GpioDataRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("GpioIntRegsFile")
#else
#pragma DATA_SECTION(GpioIntRegs,"GpioIntRegsFile");
#endif
volatile struct GPIO_INT_REGS GpioIntRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("I2caRegsFile")
#else
#pragma DATA_SECTION(I2caRegs,"I2caRegsFile");
#endif
volatile struct I2C_REGS I2caRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("McbspaRegsFile")
#else
#pragma DATA_SECTION(McbspaRegs,"McbspaRegsFile");
#endif
volatile struct MCBSP_REGS McbspaRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("McbspbRegsFile")
#else
#pragma DATA_SECTION(McbspbRegs,"McbspbRegsFile");
#endif
volatile struct MCBSP_REGS McbspbRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("PartIdRegsFile")
#else
#pragma DATA_SECTION(PartIdRegs,"PartIdRegsFile");
#endif
volatile struct PARTID_REGS PartIdRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("PieCtrlRegsFile")
#else
#pragma DATA_SECTION(PieCtrlRegs,"PieCtrlRegsFile");
#endif
volatile struct PIE_CTRL_REGS PieCtrlRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("PieVectTableFile")
#else
#pragma DATA_SECTION(PieVectTable,"PieVectTableFile");
#endif
struct PIE_VECT_TABLE PieVectTable;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("SciaRegsFile")
#else
#pragma DATA_SECTION(SciaRegs,"SciaRegsFile");
#endif
volatile struct SCI_REGS SciaRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("ScibRegsFile")
#else
#pragma DATA_SECTION(ScibRegs,"ScibRegsFile");
#endif
volatile struct SCI_REGS ScibRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("ScicRegsFile")
#else
#pragma DATA_SECTION(ScicRegs,"ScicRegsFile");
#endif
volatile struct SCI_REGS ScicRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("SpiaRegsFile")
#else
#pragma DATA_SECTION(SpiaRegs,"SpiaRegsFile");
#endif
volatile struct SPI_REGS SpiaRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("SysCtrlRegsFile")
#else
#pragma DATA_SECTION(SysCtrlRegs,"SysCtrlRegsFile");
#endif
volatile struct SYS_CTRL_REGS SysCtrlRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("FlashRegsFile")
#else
#pragma DATA_SECTION(FlashRegs,"FlashRegsFile");
#endif
volatile struct FLASH_REGS FlashRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("XIntruptRegsFile")
#else
#pragma DATA_SECTION(XIntruptRegs,"XIntruptRegsFile");
#endif
volatile struct XINTRUPT_REGS XIntruptRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("XintfRegsFile")
#else
#pragma DATA_SECTION(XintfRegs,"XintfRegsFile");
#endif
volatile struct XINTF_REGS XintfRegs;
//===========================================================================
// End of file.
//===========================================================================