911 lines
41 KiB
XML
911 lines
41 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>setcorp</spirit:vendor>
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<spirit:library>user</spirit:library>
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<spirit:name>IP_AXI_Inputs</spirit:name>
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<spirit:version>1.0</spirit:version>
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<spirit:busInterfaces>
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<spirit:busInterface>
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<spirit:name>S00_AXI</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
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<spirit:slave>
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<spirit:memoryMapRef spirit:memoryMapRef="S00_AXI"/>
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</spirit:slave>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWADDR</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axi_awaddr</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWPROT</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axi_awprot</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axi_awvalid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axi_awready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>WDATA</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axi_wdata</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>WSTRB</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axi_wstrb</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>WVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axi_wvalid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>WREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axi_wready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>BRESP</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axi_bresp</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>BVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axi_bvalid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>BREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axi_bready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARADDR</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axi_araddr</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARPROT</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axi_arprot</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axi_arvalid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axi_arready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RDATA</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axi_rdata</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RRESP</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axi_rresp</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axi_rvalid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axi_rready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>WIZ_DATA_WIDTH</spirit:name>
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<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>WIZ_NUM_REG</spirit:name>
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<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ_NUM_REG" spirit:minimum="4" spirit:maximum="512" spirit:rangeType="long">4</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
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<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_pairs_ce1226b1">0</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>S00_AXI_RST</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RST</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axi_aresetn</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>POLARITY</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_RST.POLARITY" spirit:choiceRef="choice_list_74b5137e">ACTIVE_LOW</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>S00_AXI_CLK</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axi_aclk</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_BUSIF</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_BUSIF">S00_AXI</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_RESET</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_RESET">s00_axi_aresetn</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>interrupt</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
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<spirit:master/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>INTERRUPT</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>interrupt</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>SENSITIVITY</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY" spirit:choiceRef="choice_list_9ca20931">LEVEL_HIGH</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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</spirit:busInterfaces>
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<spirit:memoryMaps>
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<spirit:memoryMap>
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<spirit:name>S00_AXI</spirit:name>
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<spirit:addressBlock>
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<spirit:name>S00_AXI_reg</spirit:name>
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<spirit:baseAddress spirit:format="long" spirit:resolve="user">0</spirit:baseAddress>
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<spirit:range spirit:format="long">4096</spirit:range>
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<spirit:width spirit:format="long">32</spirit:width>
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<spirit:usage>register</spirit:usage>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>OFFSET_BASE_PARAM</spirit:name>
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<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S00_AXI.S00_AXI_REG.OFFSET_BASE_PARAM">C_S00_AXI_BASEADDR</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>OFFSET_HIGH_PARAM</spirit:name>
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<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S00_AXI.S00_AXI_REG.OFFSET_HIGH_PARAM">C_S00_AXI_HIGHADDR</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:addressBlock>
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</spirit:memoryMap>
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</spirit:memoryMaps>
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<spirit:model>
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<spirit:views>
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<spirit:view>
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<spirit:name>xilinx_vhdlsynthesis</spirit:name>
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<spirit:displayName>VHDL Synthesis</spirit:displayName>
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<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
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<spirit:language>vhdl</spirit:language>
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<spirit:modelName>IP_AXI_Inputs_v1_0</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_vhdlsynthesis_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>72615f2e</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_vhdlbehavioralsimulation</spirit:name>
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<spirit:displayName>VHDL Simulation</spirit:displayName>
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<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
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<spirit:language>vhdl</spirit:language>
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<spirit:modelName>IP_AXI_Inputs_v1_0</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>72615f2e</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_softwaredriver</spirit:name>
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<spirit:displayName>Software Driver</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:sw.driver</spirit:envIdentifier>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_softwaredriver_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>1d8bf0ce</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_xpgui</spirit:name>
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<spirit:displayName>UI Layout</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>dda4df14</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>bd_tcl</spirit:name>
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<spirit:displayName>Block Diagram</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:block.diagram</spirit:envIdentifier>
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<spirit:fileSetRef>
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<spirit:localName>bd_tcl_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>16328387</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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</spirit:views>
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<spirit:ports>
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<spirit:port>
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<spirit:name>data</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long">31</spirit:left>
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<spirit:right spirit:format="long">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>interrupt</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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<spirit:driver>
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<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
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</spirit:driver>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>s00_axi_awaddr</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH')) - 1)">3</spirit:left>
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<spirit:right spirit:format="long">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>s00_axi_awprot</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long">2</spirit:left>
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<spirit:right spirit:format="long">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>s00_axi_awvalid</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
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</xilinx:enablement>
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</xilinx:parameterInfo>
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</spirit:vendorExtensions>
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</spirit:parameter>
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<spirit:parameter>
|
|
<spirit:name>C_S00_AXI_BASEADDR</spirit:name>
|
|
<spirit:displayName>C S00 AXI BASEADDR</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_BASEADDR" spirit:order="5" spirit:bitStringLength="32">0xFFFFFFFF</spirit:value>
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<spirit:vendorExtensions>
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<xilinx:parameterInfo>
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<xilinx:enablement>
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|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_BASEADDR">false</xilinx:isEnabled>
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|
</xilinx:enablement>
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|
</xilinx:parameterInfo>
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|
</spirit:vendorExtensions>
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|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>C_S00_AXI_HIGHADDR</spirit:name>
|
|
<spirit:displayName>C S00 AXI HIGHADDR</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_HIGHADDR" spirit:order="6" spirit:bitStringLength="32">0x00000000</spirit:value>
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<spirit:vendorExtensions>
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<xilinx:parameterInfo>
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<xilinx:enablement>
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|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_HIGHADDR">false</xilinx:isEnabled>
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</xilinx:enablement>
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</xilinx:parameterInfo>
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</spirit:parameter>
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<spirit:parameter>
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|
<spirit:name>Component_Name</spirit:name>
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|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">IP_AXI_Inputs_v1_0</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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<spirit:vendorExtensions>
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<xilinx:coreExtensions>
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<xilinx:supportedFamilies>
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<xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family>
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|
</xilinx:supportedFamilies>
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|
<xilinx:taxonomies>
|
|
<xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
|
|
</xilinx:taxonomies>
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|
<xilinx:displayName>IP_AXI_Inputs_v1.0</xilinx:displayName>
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|
<xilinx:coreRevision>2</xilinx:coreRevision>
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|
<xilinx:coreCreationDateTime>2025-12-03T12:29:19Z</xilinx:coreCreationDateTime>
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<xilinx:tags>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@4c092df8_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@78be6866_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@5e113bca_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@3bfafcfd_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@371adb6e_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@50e818a3_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@2792b76e_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@77bd5c84_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@1a144cf9_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@167935c5_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@a758d5b_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@569fe838_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@3f0b6c7d_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@2bb08de2_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@368d98ea_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@248c575d_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@5cc2a279_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@5b299fc9_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@59cfb47a_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0</xilinx:tag>
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|
<xilinx:tag xilinx:name="ui.data.coregen.dd@3a45353d_ARCHIVE_LOCATION">d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0</xilinx:tag>
|
|
</xilinx:tags>
|
|
</xilinx:coreExtensions>
|
|
<xilinx:packagingInfo>
|
|
<xilinx:xilinxVersion>2019.1</xilinx:xilinxVersion>
|
|
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="e91f485b"/>
|
|
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="ed1368d5"/>
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|
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="3d382d21"/>
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<xilinx:checksum xilinx:scope="ports" xilinx:value="6bdbe319"/>
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<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="6992ea72"/>
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<xilinx:checksum xilinx:scope="parameters" xilinx:value="cbc4d680"/>
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</xilinx:packagingInfo>
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