setcorp user IP_AXI_Inputs 1.0 S00_AXI AWADDR s00_axi_awaddr AWPROT s00_axi_awprot AWVALID s00_axi_awvalid AWREADY s00_axi_awready WDATA s00_axi_wdata WSTRB s00_axi_wstrb WVALID s00_axi_wvalid WREADY s00_axi_wready BRESP s00_axi_bresp BVALID s00_axi_bvalid BREADY s00_axi_bready ARADDR s00_axi_araddr ARPROT s00_axi_arprot ARVALID s00_axi_arvalid ARREADY s00_axi_arready RDATA s00_axi_rdata RRESP s00_axi_rresp RVALID s00_axi_rvalid RREADY s00_axi_rready WIZ_DATA_WIDTH 32 WIZ_NUM_REG 4 SUPPORTS_NARROW_BURST 0 S00_AXI_RST RST s00_axi_aresetn POLARITY ACTIVE_LOW S00_AXI_CLK CLK s00_axi_aclk ASSOCIATED_BUSIF S00_AXI ASSOCIATED_RESET s00_axi_aresetn interrupt INTERRUPT interrupt SENSITIVITY LEVEL_HIGH S00_AXI S00_AXI_reg 0 4096 32 register OFFSET_BASE_PARAM C_S00_AXI_BASEADDR OFFSET_HIGH_PARAM C_S00_AXI_HIGHADDR xilinx_vhdlsynthesis VHDL Synthesis vhdlSource:vivado.xilinx.com:synthesis vhdl IP_AXI_Inputs_v1_0 xilinx_vhdlsynthesis_view_fileset viewChecksum 72615f2e xilinx_vhdlbehavioralsimulation VHDL Simulation vhdlSource:vivado.xilinx.com:simulation vhdl IP_AXI_Inputs_v1_0 xilinx_vhdlbehavioralsimulation_view_fileset viewChecksum 72615f2e xilinx_softwaredriver Software Driver :vivado.xilinx.com:sw.driver xilinx_softwaredriver_view_fileset viewChecksum 1d8bf0ce xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum dda4df14 bd_tcl Block Diagram :vivado.xilinx.com:block.diagram bd_tcl_view_fileset viewChecksum 16328387 data in 31 0 std_logic_vector xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation interrupt out std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation 0x0 s00_axi_awaddr in 3 0 std_logic_vector xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_awprot in 2 0 std_logic_vector xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_awvalid in std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_awready out std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_wdata in 31 0 std_logic_vector xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_wstrb in 3 0 std_logic_vector xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_wvalid in std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_wready out std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_bresp out 1 0 std_logic_vector xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_bvalid out std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_bready in std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_araddr in 3 0 std_logic_vector xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_arprot in 2 0 std_logic_vector xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_arvalid in std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_arready out std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_rdata out 31 0 std_logic_vector xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_rresp out 1 0 std_logic_vector xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_rvalid out std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_rready in std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_aclk in std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_aresetn in std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation C_S00_AXI_DATA_WIDTH C S00 AXI DATA WIDTH Width of S_AXI data bus 32 C_S00_AXI_ADDR_WIDTH C S00 AXI ADDR WIDTH Width of S_AXI address bus 4 choice_list_6fc15197 32 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW choice_list_9ca20931 LEVEL_HIGH LEVEL_LOW EDGE_RISING EDGE_FALLING choice_pairs_ce1226b1 1 0 xilinx_vhdlsynthesis_view_fileset hdl/IP_AXI_Inputs_v1_0_S00_AXI.vhd vhdlSource hdl/IP_AXI_Inputs_v1_0.vhd vhdlSource CHECKSUM_f1f0aa53 xilinx_vhdlbehavioralsimulation_view_fileset hdl/IP_AXI_Inputs_v1_0_S00_AXI.vhd vhdlSource hdl/IP_AXI_Inputs_v1_0.vhd vhdlSource xilinx_softwaredriver_view_fileset drivers/IP_AXI_Inputs_v1_0/data/IP_AXI_Inputs.mdd mdd driver_mdd drivers/IP_AXI_Inputs_v1_0/data/IP_AXI_Inputs.tcl tclSource driver_tcl drivers/IP_AXI_Inputs_v1_0/src/Makefile driver_src drivers/IP_AXI_Inputs_v1_0/src/IP_AXI_Inputs.h cSource driver_src drivers/IP_AXI_Inputs_v1_0/src/IP_AXI_Inputs.c cSource driver_src drivers/IP_AXI_Inputs_v1_0/src/IP_AXI_Inputs_selftest.c cSource driver_src xilinx_xpgui_view_fileset xgui/IP_AXI_Inputs_v1_0.tcl tclSource CHECKSUM_dda4df14 XGUI_VERSION_2 bd_tcl_view_fileset bd/bd.tcl tclSource My new AXI IP C_S00_AXI_DATA_WIDTH C S00 AXI DATA WIDTH Width of S_AXI data bus 32 false C_S00_AXI_ADDR_WIDTH C S00 AXI ADDR WIDTH Width of S_AXI address bus 4 false C_S00_AXI_BASEADDR C S00 AXI BASEADDR 0xFFFFFFFF false C_S00_AXI_HIGHADDR C S00 AXI HIGHADDR 0x00000000 false Component_Name IP_AXI_Inputs_v1_0 zynq AXI_Peripheral IP_AXI_Inputs_v1.0 2 2025-12-03T12:29:19Z d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 2019.1