24 lines
869 B
Markdown
24 lines
869 B
Markdown
# Logic-analyzer capture memory
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`rtl/la_capture_buffer.v` is a portable Verilog-2001 true dual-port capture
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buffer. It deliberately contains no Altera/Intel primitive, board pin, UART,
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or trigger logic. Quartus infers Cyclone IV M9K memory from the registered
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read and synchronous write ports.
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Parameters:
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| Parameter | Meaning | Default |
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| `SAMPLE_WIDTH` | Number of simultaneously captured digital inputs | 16 |
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| `ADDR_WIDTH` | Buffer depth as `2**ADDR_WIDTH` | 12 (4096 samples) |
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The write and read clocks may be different. The caller owns clock-domain
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crossing for addresses/status and must keep a read address stable until the
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registered `rd_data` is valid on the following `rd_clk` edge.
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Example Quartus source assignment:
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```tcl
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set_global_assignment -name VERILOG_FILE path/to/templates/hdl/logic-analyzer/rtl/la_capture_buffer.v
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```
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