# Logic-analyzer capture memory

`rtl/la_capture_buffer.v` is a portable Verilog-2001 true dual-port capture
buffer.  It deliberately contains no Altera/Intel primitive, board pin, UART,
or trigger logic.  Quartus infers Cyclone IV M9K memory from the registered
read and synchronous write ports.

Parameters:

| Parameter | Meaning | Default |
|---|---|---:|
| `SAMPLE_WIDTH` | Number of simultaneously captured digital inputs | 16 |
| `ADDR_WIDTH` | Buffer depth as `2**ADDR_WIDTH` | 12 (4096 samples) |

The write and read clocks may be different.  The caller owns clock-domain
crossing for addresses/status and must keep a read address stable until the
registered `rd_data` is valid on the following `rd_clk` edge.

Example Quartus source assignment:

```tcl
set_global_assignment -name VERILOG_FILE path/to/templates/hdl/logic-analyzer/rtl/la_capture_buffer.v
```