init commit.
Проект каким он достался от Димы.
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// TI File $Revision: /main/10 $
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// Checkin $Date: April 21, 2008 15:43:45 $
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//###########################################################################
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//
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// FILE: Example_2833xSWPrioritizedInterrupts.c
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//
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// TITLE: DSP2833x Software Prioritized Interrupt Example.
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//
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// ASSUMPTIONS:
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//
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// This program requires the DSP2833x header files.
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//
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// As supplied, this project is configured for "boot to SARAM"
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// operation. The 2833x Boot Mode table is shown below.
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// For information on configuring the boot mode of an eZdsp,
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// please refer to the documentation included with the eZdsp,
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//
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// $Boot_Table:
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//
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// GPIO87 GPIO86 GPIO85 GPIO84
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// XA15 XA14 XA13 XA12
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// PU PU PU PU
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// ==========================================
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// 1 1 1 1 Jump to Flash
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// 1 1 1 0 SCI-A boot
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// 1 1 0 1 SPI-A boot
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// 1 1 0 0 I2C-A boot
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// 1 0 1 1 eCAN-A boot
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// 1 0 1 0 McBSP-A boot
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// 1 0 0 1 Jump to XINTF x16
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// 1 0 0 0 Jump to XINTF x32
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// 0 1 1 1 Jump to OTP
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// 0 1 1 0 Parallel GPIO I/O boot
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// 0 1 0 1 Parallel XINTF boot
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// 0 1 0 0 Jump to SARAM <- "boot to SARAM"
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// 0 0 1 1 Branch to check boot mode
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// 0 0 1 0 Boot to flash, bypass ADC cal
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// 0 0 0 1 Boot to SARAM, bypass ADC cal
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// 0 0 0 0 Boot to SCI-A, bypass ADC cal
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// Boot_Table_End$
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//
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// DESCRIPTION:
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//
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// For most applications, the hardware prioritization of the
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// the PIE module is sufficient. For applications that need custom
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// prioritization, this example illustrates an example of
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// how this can be done through software.
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//
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// For more information on F2833x interrupt priorities, refer to the
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// Example_2833xISRPriorities.pdf file included with the DSP2833x/doc directory.
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//
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// This program simulates interrupt conflicts by writing to the
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// PIEIFR registers. This will simulate multiple interrupts coming into
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// the PIE block at the same time.
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//
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// The interrupt service routine routines are software prioritized
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// by the table found in the DSP2833x_SWPrioritizedIsrLevels.h file.
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//
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// 1) Before compiling you must set the Global and Group interrupt priorities
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// in the DSP2833x_SWPrioritizedIsrLevels.h file.
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//
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// 2) Then select which test you want to run with the #define TEST directive
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// at the top of this file (select a test between 1 and 10)
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//
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// 3) Compile the code, load, and run
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//
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// 4) At the end of each test there is a hard coded breakpoint (ESTOP0). When code
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// stops at the breakpoint, examine the ISRTrace buffer to see the order
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// in which the ISR's completed. All PIE interrupts will add to the
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// ISRTrace.
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//
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// The ISRTrace will consist of a list of hex values as shown:
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//
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// 0x00wx <- PIE Group w interrup x finished first
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// 0x00yz <- PIE Group y interrupt z finished next
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//
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// 5) If desired, set a new set of Global and Group interrupt priorites
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// and repeat the test to see the change.
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//
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//
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// Watch Variables:
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// ISRTrace[50] Trace of ISR's in the order they complete
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// After each test, examine this buffer
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// to determine if the ISR's completed in
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// the order desired.
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//
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//###########################################################################
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// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
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// $Release Date: August 1, 2008 $
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//###########################################################################
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#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
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#include "DSP2833x_SWPrioritizedIsrLevels.h"
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#define TEST 1 // Select a test number: 1 through 10
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// Define which interrupts are used in the PIE for each group.
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#define ISRS_GROUP1 (M_INT1|M_INT2|M_INT4|M_INT5|M_INT6|M_INT7|M_INT8)
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#define ISRS_GROUP2 (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6)
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#define ISRS_GROUP3 (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6)
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#define ISRS_GROUP4 (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6)
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#define ISRS_GROUP5 (M_INT1|M_INT2)
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#define ISRS_GROUP6 (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6)
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#define ISRS_GROUP7 (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6)
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#define ISRS_GROUP8 (M_INT1|M_INT2|M_INT5|M_INT6)
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#define ISRS_GROUP9 (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6|M_INT7|M_INT8)
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#define ISRS_GROUP12 (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT7|M_INT8)
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// This array will be used as a trace to check the order that the
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// interrupts were serviced
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Uint16 ISRTrace[50];
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Uint16 ISRTraceIndex; // used to update an element in the trace buffer
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void main(void)
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{
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Uint16 i;
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// Step 1. Initialize System Control:
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// PLL, WatchDog, enable Peripheral Clocks
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// This example function is found in the DSP2833x_SysCtrl.c file.
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InitSysCtrl();
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// Step 2. Initalize GPIO:
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// This example function is found in the DSP2833x_Gpio.c file and
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// illustrates how to set the GPIO to it's default state.
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// InitGpio(); // Skipped for this example
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// Step 3. Clear all interrupts and initialize PIE vector table:
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// Disable CPU interrupts
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DINT;
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// Initialize PIE control registers to their default state.
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// The default state is all PIE interrupts disabled and flags
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// are cleared.
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// This function is found in the DSP2833x_PieCtrl.c file.
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InitPieCtrl();
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// Disable CPU interrupts and clear all CPU interrupt flags:
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IER = 0x0000;
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IFR = 0x0000;
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// Initialize the PIE vector table with pointers to the shell Interrupt
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// Service Routines (ISR).
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// This will populate the entire table, even if the interrupt
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// is not used in this example. This is useful for debug purposes.
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// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
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// This function is found in DSP2833x_PieVect.c.
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InitPieVectTable();
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// Step 4. Initialize all the Device Peripherals:
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// This function is found in DSP2833x_InitPeripherals.c
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// InitPeripherals(); // Not required for this example
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// Step 5. User specific code, enable interrupts:
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#if (TEST==1)
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// Force all group 1 interrupts at once by writing to the PIEIFR1 register
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// Prepare for the test:
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// Disable interrupts
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// Clear the trace buffer, PIE Control Register, CPU IER and IFR registers
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DINT;
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for(i = 0; i < 50; i++) ISRTrace[i] = 0;
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ISRTraceIndex = 0;
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InitPieCtrl();
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IER = 0;
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IFR &= 0;
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// Enable the PIE block
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PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
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// Enable PIE group 1 interrupt 1-8
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PieCtrlRegs.PIEIER1.all = 0x00FF;
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// Make sure PIEACK for group 1 is clear (default after reset)
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PieCtrlRegs.PIEACK.all = M_INT1;
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// Enable CPU INT1
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IER |= M_INT1;
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// Force all valid interrupts for Group 1
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PieCtrlRegs.PIEIFR1.all = ISRS_GROUP1;
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// Enable global Interrupts CPU level:
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EINT; // Enable Global interrupt INTM
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// Wait for all Group 1 interrupts to be serviced
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while(PieCtrlRegs.PIEIFR1.all != 0x0000 ){}
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// Stop here and check the ISRTrace to determine which order the
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// ISR Routines completed. The order is dependant on the priority
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// assigned in the DSP2833x_SWPrioritizedIsrLevels.h file
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//
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// The ISRTrace will contain a list of values corresponding to the
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// interrupts serviced in the order they were serviced.
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// For example if the ISRTrace looks like this
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// 0x0014 ISR Group 1 interrupt 4
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// 0x0017 ISR Group 1 interrupt 7
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// 0x0016 ISR Group 1 interrupt 6
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// 0x0015 ISR Group 1 interrupt 5
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// 0x0018 ISR Group 1 interrupt 8
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// 0x0012 ISR Group 1 interrupt 2
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// 0x0011 ISR Group 1 interrupt 1
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// 0x0000 end of trace
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asm(" ESTOP0");
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#endif
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#if (TEST == 2)
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// CASE 2:
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// Force all group 2 interrupts at once by writing to the PIEIFR2 register
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// Prepare for the test:
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// Disable interrupts
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// Clear the trace buffer, PIE Control Register, CPU IER and IFR registers
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DINT;
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for(i = 0; i < 50; i++) ISRTrace[i] = 0;
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ISRTraceIndex = 0;
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InitPieCtrl();
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IER = 0;
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IFR &= 0;
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// Enable the PIE block
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PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
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// Enable PIE group 2 interrupts 1-8
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PieCtrlRegs.PIEIER2.all = 0x00FF;
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// Enable CPU INT2
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IER |= (M_INT2);
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// Make sure PIEACK for group 2 is clear (default after reset)
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PieCtrlRegs.PIEACK.all = M_INT2;
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// Force all valid interrupts for Group 2
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PieCtrlRegs.PIEIFR2.all = ISRS_GROUP2;
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// Enable Global interrupts
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EINT;
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// Wait for all group 2 interrupts to be serviced
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while(PieCtrlRegs.PIEIFR2.all != 0x0000 ){}
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// Stop here and check the order the ISR's were serviced in the
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// ISRTrace
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asm(" ESTOP0");
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#endif
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#if (TEST == 3)
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// CASE 3:
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// Force all group 3 interrupts at once by writing to the PIEIFR3 register
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// Prepare for the test:
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// Disable interrupts
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// Clear the trace buffer, PIE Control Register, CPU IER and IFR registers
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DINT;
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for(i = 0; i < 50; i++) ISRTrace[i] = 0;
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ISRTraceIndex = 0;
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InitPieCtrl();
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IER = 0;
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IFR &= 0;
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// Enable the PIE block
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PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
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// Enable PIE group 3 interrupts 1-8
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PieCtrlRegs.PIEIER3.all = 0x00FF;
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// Make sure PIEACK for group 3 is clear (default after reset)
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PieCtrlRegs.PIEACK.all = M_INT3;
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// Enable CPU INT3
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IER |= (M_INT3);
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// Force all valid interrupts for Group 3
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PieCtrlRegs.PIEIFR3.all = ISRS_GROUP3;
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// Enable Global interrupts
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EINT;
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// Wait for all group 3 interrupts to be serviced
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while(PieCtrlRegs.PIEIFR3.all != 0x0000 ){}
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// Stop here and check the order the ISR's were serviced in the
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// ISRTrace
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asm(" ESTOP0");
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#endif
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#if (TEST == 4)
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// CASE 4:
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// Force all group 4 interrupts at once by writing to the PIEIFR4 register
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||||
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// Prepare for the test:
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// Disable interrupts
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// Clear the trace buffer, PIE Control Register, CPU IER and IFR registers
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DINT;
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for(i = 0; i < 50; i++) ISRTrace[i] = 0;
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ISRTraceIndex = 0;
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||||
InitPieCtrl();
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||||
IER = 0;
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||||
IFR &= 0;
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||||
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// Enable the PIE block
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PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
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// Enable PIE group 4 interrupts 1-8
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PieCtrlRegs.PIEIER4.all = 0x00FF;
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||||
// Make sure PIEACK for group 3 is clear (default after reset)
|
||||
PieCtrlRegs.PIEACK.all = M_INT4;
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||||
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||||
// Enable CPU INT4
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||||
IER |= (M_INT4);
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||||
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||||
// Force all valid interrupts for Group 4
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||||
PieCtrlRegs.PIEIFR4.all = ISRS_GROUP4;
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||||
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// Enable Global interrupts
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EINT;
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// Wait for all group 4 interrupts to be serviced
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while(PieCtrlRegs.PIEIFR4.all != 0x0000 ){}
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||||
|
||||
// Stop here and check the order the ISR's were serviced in the
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// ISRTrace
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asm(" ESTOP0");
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#endif
|
||||
#if (TEST == 5)
|
||||
// CASE 5:
|
||||
// Force all group 5 interrupts at once by writing to the PIEIFR5 register
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||||
|
||||
// Prepare for the test:
|
||||
// Disable interrupts
|
||||
// Clear the trace buffer, PIE Control Register, CPU IER and IFR registers
|
||||
DINT;
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||||
for(i = 0; i < 50; i++) ISRTrace[i] = 0;
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||||
ISRTraceIndex = 0;
|
||||
InitPieCtrl();
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||||
IER = 0;
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||||
IFR &= 0;
|
||||
|
||||
// Enable the PIE block
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
|
||||
|
||||
// Enable PIE group 5 interrupts 1-8
|
||||
PieCtrlRegs.PIEIER5.all = 0x00FF;
|
||||
|
||||
// Make sure PIEACK for group 5 is clear (default after reset)
|
||||
PieCtrlRegs.PIEACK.all = M_INT5;
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||||
|
||||
// Enable CPU INT5
|
||||
IER |= (M_INT5);
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||||
|
||||
// Force all valid interrupts for Group 5
|
||||
PieCtrlRegs.PIEIFR5.all = ISRS_GROUP5;
|
||||
|
||||
// Enable Global interrupts
|
||||
EINT;
|
||||
|
||||
// Wait for all group 5 interrupts to be serviced
|
||||
while(PieCtrlRegs.PIEIFR5.all != 0x0000 ){}
|
||||
|
||||
// Stop here and check the order the ISR's were serviced in the
|
||||
// ISRTrace
|
||||
asm(" ESTOP0");
|
||||
#endif
|
||||
#if (TEST == 6)
|
||||
|
||||
// CASE 6:
|
||||
// Force all group 6 interrupts at once by writing to the PIEIFR6 register
|
||||
|
||||
// Prepare for the test:
|
||||
// Disable interrupts
|
||||
// Clear the trace buffer, PIE Control Register, CPU IER and IFR registers
|
||||
DINT;
|
||||
for(i = 0; i < 50; i++) ISRTrace[i] = 0;
|
||||
ISRTraceIndex = 0;
|
||||
InitPieCtrl();
|
||||
IER = 0;
|
||||
IFR &= 0;
|
||||
|
||||
// Enable the PIE block
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
|
||||
|
||||
// Enable PIE group 6 interrupts 1-8
|
||||
PieCtrlRegs.PIEIER6.all = 0x00FF;
|
||||
|
||||
// Make sure PIEACK for group 6 is clear (default after reset)
|
||||
PieCtrlRegs.PIEACK.all = M_INT6;
|
||||
|
||||
// Enable CPU INT6
|
||||
IER |= (M_INT6);
|
||||
|
||||
// Force all valid interrupts for Group 6
|
||||
PieCtrlRegs.PIEIFR6.all = ISRS_GROUP6;
|
||||
|
||||
// Enable Global interrupts
|
||||
EINT;
|
||||
|
||||
|
||||
// Wait for all group 6 interrupts to be serviced
|
||||
while(PieCtrlRegs.PIEIFR6.all != 0x0000 ){}
|
||||
|
||||
// Stop here and check the order the ISR's were serviced in the
|
||||
// ISRTrace
|
||||
asm(" ESTOP0");
|
||||
|
||||
#endif
|
||||
#if (TEST == 7)
|
||||
// CASE 7:
|
||||
// Force all group 9 interrupts at once by writing to the PIEIFR4 register
|
||||
|
||||
// Prepare for the test:
|
||||
// Disable interrupts
|
||||
// Clear the trace buffer, PIE Control Register, CPU IER and IFR registers
|
||||
DINT;
|
||||
for(i = 0; i < 50; i++) ISRTrace[i] = 0;
|
||||
ISRTraceIndex = 0;
|
||||
InitPieCtrl();
|
||||
IER = 0;
|
||||
IFR &= 0;
|
||||
|
||||
// Enable the PIE block
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
|
||||
|
||||
// Enable PIE group 9 interrupts 1-8
|
||||
PieCtrlRegs.PIEIER9.all = 0x00FF;
|
||||
|
||||
// Make sure PIEACK for group 9 is clear (default after reset)
|
||||
PieCtrlRegs.PIEACK.all = M_INT9;
|
||||
|
||||
// Enable CPU INT9
|
||||
IER |= (M_INT9);
|
||||
|
||||
// Force all valid interrupts for Group 9
|
||||
PieCtrlRegs.PIEIFR9.all = ISRS_GROUP9;
|
||||
|
||||
// Enable Global interrupts
|
||||
EINT;
|
||||
|
||||
// Wait for all group 9 interrupts to be serviced
|
||||
while(PieCtrlRegs.PIEIFR9.all != 0x0000 ){}
|
||||
|
||||
// Stop here and check the order the ISR's were serviced in the
|
||||
// ISRTrace
|
||||
asm(" ESTOP0");
|
||||
|
||||
#endif
|
||||
#if (TEST == 8)
|
||||
// CASE 8:
|
||||
// Force all group 1 and group 2 interrupts at once
|
||||
|
||||
// Setup next test - fire interrupts from Group 1 and Group 2
|
||||
|
||||
// Prepare for the test:
|
||||
// Disable interrupts
|
||||
// Clear the trace buffer, PIE Control Register, CPU IER and IFR registers
|
||||
DINT;
|
||||
for(i = 0; i < 50; i++) ISRTrace[i] = 0;
|
||||
ISRTraceIndex = 0;
|
||||
InitPieCtrl();
|
||||
IER = 0;
|
||||
IFR &= 0;
|
||||
|
||||
// Enable the PIE block
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
|
||||
|
||||
// Enable PIE group 1 and group 2 interrupts 1-8
|
||||
PieCtrlRegs.PIEIER1.all = 0x00FF;
|
||||
PieCtrlRegs.PIEIER2.all = 0x00FF;
|
||||
|
||||
// Make sure PIEACK for group 1 & 2 are clear (default after reset)
|
||||
PieCtrlRegs.PIEACK.all = (M_INT3 | M_INT2);
|
||||
|
||||
// Enable CPU INT1 and INT2
|
||||
IER |= (M_INT1|M_INT2);
|
||||
|
||||
// Force all valid interrupts for Group 1 and from Group 2
|
||||
PieCtrlRegs.PIEIFR1.all = ISRS_GROUP1;
|
||||
PieCtrlRegs.PIEIFR2.all = ISRS_GROUP2;
|
||||
|
||||
// Enable Global interrupts
|
||||
EINT;
|
||||
|
||||
// Wait for all group 1 and group 2 interrupts to be serviced
|
||||
while(PieCtrlRegs.PIEIFR1.all != 0x0000
|
||||
|| PieCtrlRegs.PIEIFR2.all != 0x0000 ){}
|
||||
|
||||
// Check the ISRTrace to determine which order the ISR Routines completed
|
||||
asm(" ESTOP0");
|
||||
|
||||
#endif
|
||||
#if (TEST == 9)
|
||||
// CASE 9:
|
||||
// Force all group 1 and group 2 and group 3 interrupts at once
|
||||
|
||||
// Prepare for the test:
|
||||
// Disable interrupts
|
||||
// Clear the trace buffer, PIE Control Register, CPU IER and IFR registers
|
||||
DINT;
|
||||
for(i = 0; i < 50; i++) ISRTrace[i] = 0;
|
||||
ISRTraceIndex = 0;
|
||||
InitPieCtrl();
|
||||
IER = 0;
|
||||
IFR &= 0;
|
||||
|
||||
// Enable the PIE block
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
|
||||
|
||||
// Enable PIE group 1, 2 and 3 interrupts 1-8
|
||||
PieCtrlRegs.PIEIER1.all = 0x00FF;
|
||||
PieCtrlRegs.PIEIER2.all = 0x00FF;
|
||||
PieCtrlRegs.PIEIER3.all = 0x00FF;
|
||||
|
||||
// Make sure PIEACK for group 1, 2 & 3 are clear (default after reset)
|
||||
PieCtrlRegs.PIEACK.all = (M_INT3|M_INT2|M_INT3);
|
||||
|
||||
// Enable CPU INT1, INT2 & INT3
|
||||
IER |= (M_INT1|M_INT2|M_INT3);
|
||||
|
||||
// Force all valid interrupts for Group1, 2 and 3
|
||||
PieCtrlRegs.PIEIFR1.all = ISRS_GROUP1;
|
||||
PieCtrlRegs.PIEIFR2.all = ISRS_GROUP2;
|
||||
PieCtrlRegs.PIEIFR3.all = ISRS_GROUP3;
|
||||
|
||||
// Enable Global interrupts
|
||||
EINT;
|
||||
|
||||
// Wait for all group 1 and group 2 and group 3 interrupts to be serviced
|
||||
while(PieCtrlRegs.PIEIFR1.all != 0x0000
|
||||
|| PieCtrlRegs.PIEIFR2.all != 0x0000
|
||||
|| PieCtrlRegs.PIEIFR3.all != 0x0000 ) {}
|
||||
|
||||
// Check the ISRTrace to determine which order the ISR Routines completed
|
||||
asm(" ESTOP0");
|
||||
|
||||
#endif
|
||||
#if (TEST == 10)
|
||||
// CASE 10:
|
||||
// Force all used PIE interrupts at once
|
||||
|
||||
// Prepare for the test:
|
||||
// Disable interrupts
|
||||
// Clear the trace buffer, PIE Control Register, CPU IER and IFR registers
|
||||
DINT;
|
||||
for(i = 0; i < 50; i++) ISRTrace[i] = 0;
|
||||
ISRTraceIndex = 0;
|
||||
InitPieCtrl();
|
||||
IER = 0;
|
||||
IFR &= 0;
|
||||
|
||||
// Enable the PIE block
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
|
||||
|
||||
// Enable all PIE group interrupts 1-8
|
||||
PieCtrlRegs.PIEIER1.all = 0x00FF;
|
||||
PieCtrlRegs.PIEIER2.all = 0x00FF;
|
||||
PieCtrlRegs.PIEIER3.all = 0x00FF;
|
||||
PieCtrlRegs.PIEIER4.all = 0x00FF;
|
||||
PieCtrlRegs.PIEIER5.all = 0x00FF;
|
||||
PieCtrlRegs.PIEIER6.all = 0x00FF;
|
||||
PieCtrlRegs.PIEIER9.all = 0x00FF;
|
||||
|
||||
// Make sure PIEACK for group 1, 2, 3, 4, 5, 6 and 9 are clear (default after reset)
|
||||
PieCtrlRegs.PIEACK.all = (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6|M_INT9);
|
||||
|
||||
// Enable CPU INT1, INT2, INT3, INT4, INT5, INT6 and INT9
|
||||
IER |= (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6|M_INT9);
|
||||
|
||||
// Force all valid interrupts for all PIE groups
|
||||
PieCtrlRegs.PIEIFR1.all = ISRS_GROUP1;
|
||||
PieCtrlRegs.PIEIFR2.all = ISRS_GROUP2;
|
||||
PieCtrlRegs.PIEIFR3.all = ISRS_GROUP3;
|
||||
PieCtrlRegs.PIEIFR4.all = ISRS_GROUP4;
|
||||
PieCtrlRegs.PIEIFR5.all = ISRS_GROUP5;
|
||||
PieCtrlRegs.PIEIFR6.all = ISRS_GROUP6;
|
||||
PieCtrlRegs.PIEIFR9.all = ISRS_GROUP9;
|
||||
|
||||
// Enable Global interrupts - CPU level
|
||||
EINT;
|
||||
|
||||
// Wait for all group interrupts to be serviced
|
||||
while(PieCtrlRegs.PIEIFR1.all != 0x0000
|
||||
|| PieCtrlRegs.PIEIFR2.all != 0x0000
|
||||
|| PieCtrlRegs.PIEIFR3.all != 0x0000
|
||||
|| PieCtrlRegs.PIEIFR4.all != 0x0000
|
||||
|| PieCtrlRegs.PIEIFR5.all != 0x0000
|
||||
|| PieCtrlRegs.PIEIFR6.all != 0x0000
|
||||
|| PieCtrlRegs.PIEIFR9.all != 0x0000 ) {}
|
||||
|
||||
// Check the ISRTrace to determine which order the ISR Routines completed
|
||||
asm(" ESTOP0");
|
||||
#endif
|
||||
}
|
||||
//===========================================================================
|
||||
// No more.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,37 @@
|
||||
/*
|
||||
// TI File $Revision: /main/5 $
|
||||
// Checkin $Date: August 9, 2007 17:23:56 $
|
||||
//###########################################################################
|
||||
//
|
||||
// This .gel file can be used to help load and build the example project.
|
||||
// It should be unloaded from Code Composer Studio before loading another
|
||||
// project.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
*/
|
||||
|
||||
menuitem "DSP2833x Software Prioritized Interrupts"
|
||||
|
||||
hotmenu Load_and_Build_Project()
|
||||
{
|
||||
GEL_ProjectLoad("Example_2833xSWPrioritizedInterrupts.pjt");
|
||||
GEL_ProjectBuild("Example_2833xSWPrioritizedInterrupts.pjt");
|
||||
Setup_WatchWindow();
|
||||
}
|
||||
|
||||
hotmenu Load_Code()
|
||||
{
|
||||
GEL_Load(".\\debug\\Example_2833xSWPrioritizedInterrupts.out");
|
||||
Setup_WatchWindow();
|
||||
}
|
||||
|
||||
hotmenu Setup_WatchWindow()
|
||||
{
|
||||
GEL_WatchReset();
|
||||
GEL_WatchAdd("ISRTrace,x");
|
||||
GEL_WatchAdd("TempPIEIER,x");
|
||||
GEL_WatchAdd("PieCtrlRegs,x");
|
||||
}
|
||||
@@ -0,0 +1,44 @@
|
||||
; Code Composer Project File, Version 2.0 (do not modify or remove this line)
|
||||
|
||||
[Project Settings]
|
||||
ProjectName="DSP2833x"
|
||||
ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\sw_prioritized_interrupts\"
|
||||
ProjectType=Executable
|
||||
CPUFamily=TMS320C28XX
|
||||
Tool="Compiler"
|
||||
Tool="DspBiosBuilder"
|
||||
Tool="Linker"
|
||||
Config="Debug"
|
||||
Config="Release"
|
||||
|
||||
[Source Files]
|
||||
Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm"
|
||||
Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm"
|
||||
Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c"
|
||||
Source="..\..\DSP2833x_common\source\DSP2833x_SWPrioritizedPieVect.c"
|
||||
Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c"
|
||||
Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm"
|
||||
Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c"
|
||||
Source="Example_2833xSWPrioritizedDefaultIsr.c"
|
||||
Source="Example_2833xSWPrioritizedInterrupts.c"
|
||||
Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd"
|
||||
Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd"
|
||||
|
||||
["Compiler" Settings: "Debug"]
|
||||
Options=-g -q -pdr -o2 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\sw_prioritized_interrupts\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\sw_prioritized_interrupts\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28
|
||||
|
||||
["Compiler" Settings: "Release"]
|
||||
Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\sw_prioritized_interrupts\Release" -d"LARGE_MODEL" -ml -v28
|
||||
|
||||
["DspBiosBuilder" Settings: "Debug"]
|
||||
Options=-v28
|
||||
|
||||
["DspBiosBuilder" Settings: "Release"]
|
||||
Options=-v28
|
||||
|
||||
["Linker" Settings: "Debug"]
|
||||
Options=-q -c -m".\Debug\Example_2833xSWPrioritizedInterrupts.map" -o".\Debug\Example_2833xSWPrioritizedInterrupts.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib"
|
||||
|
||||
["Linker" Settings: "Release"]
|
||||
Options=-q -c -o".\Release\Example_2833xSWPrioritizedInterrupts.out" -x
|
||||
|
||||
Reference in New Issue
Block a user