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264
v120/DSP2833x_headers/include/DSP2833x_Adc.h Normal file
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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:51:50 $
//###########################################################################
//
// FILE: DSP2833x_Adc.h
//
// TITLE: DSP2833x Device ADC Register Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_ADC_H
#define DSP2833x_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
//---------------------------------------------------------------------------
// ADC Individual Register Bit Definitions:
struct ADCTRL1_BITS { // bits description
Uint16 rsvd1:4; // 3:0 reserved
Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode
Uint16 SEQ_OVRD:1; // 5 Sequencer override
Uint16 CONT_RUN:1; // 6 Continuous run
Uint16 CPS:1; // 7 ADC core clock pre-scalar
Uint16 ACQ_PS:4; // 11:8 Acquisition window size
Uint16 SUSMOD:2; // 13:12 Emulation suspend mode
Uint16 RESET:1; // 14 ADC reset
Uint16 rsvd2:1; // 15 reserved
};
union ADCTRL1_REG {
Uint16 all;
struct ADCTRL1_BITS bit;
};
struct ADCTRL2_BITS { // bits description
Uint16 EPWM_SOCB_SEQ2:1; // 0 EPWM compare B SOC mask for SEQ2
Uint16 rsvd1:1; // 1 reserved
Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode
Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable
Uint16 rsvd2:1; // 4 reserved
Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2
Uint16 RST_SEQ2:1; // 6 Reset SEQ2
Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1
Uint16 EPWM_SOCA_SEQ1:1; // 8 EPWM compare B SOC mask for SEQ1
Uint16 rsvd3:1; // 9 reserved
Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode
Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable
Uint16 rsvd4:1; // 12 reserved
Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1
Uint16 RST_SEQ1:1; // 14 Restart sequencer 1
Uint16 EPWM_SOCB_SEQ:1; // 15 EPWM compare B SOC enable
};
union ADCTRL2_REG {
Uint16 all;
struct ADCTRL2_BITS bit;
};
struct ADCASEQSR_BITS { // bits description
Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state
Uint16 SEQ2_STATE:3; // 6:4 SEQ2 state
Uint16 rsvd1:1; // 7 reserved
Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status
Uint16 rsvd2:4; // 15:12 reserved
};
union ADCASEQSR_REG {
Uint16 all;
struct ADCASEQSR_BITS bit;
};
struct ADCMAXCONV_BITS { // bits description
Uint16 MAX_CONV1:4; // 3:0 Max number of conversions
Uint16 MAX_CONV2:3; // 6:4 Max number of conversions
Uint16 rsvd1:9; // 15:7 reserved
};
union ADCMAXCONV_REG {
Uint16 all;
struct ADCMAXCONV_BITS bit;
};
struct ADCCHSELSEQ1_BITS { // bits description
Uint16 CONV00:4; // 3:0 Conversion selection 00
Uint16 CONV01:4; // 7:4 Conversion selection 01
Uint16 CONV02:4; // 11:8 Conversion selection 02
Uint16 CONV03:4; // 15:12 Conversion selection 03
};
union ADCCHSELSEQ1_REG{
Uint16 all;
struct ADCCHSELSEQ1_BITS bit;
};
struct ADCCHSELSEQ2_BITS { // bits description
Uint16 CONV04:4; // 3:0 Conversion selection 04
Uint16 CONV05:4; // 7:4 Conversion selection 05
Uint16 CONV06:4; // 11:8 Conversion selection 06
Uint16 CONV07:4; // 15:12 Conversion selection 07
};
union ADCCHSELSEQ2_REG{
Uint16 all;
struct ADCCHSELSEQ2_BITS bit;
};
struct ADCCHSELSEQ3_BITS { // bits description
Uint16 CONV08:4; // 3:0 Conversion selection 08
Uint16 CONV09:4; // 7:4 Conversion selection 09
Uint16 CONV10:4; // 11:8 Conversion selection 10
Uint16 CONV11:4; // 15:12 Conversion selection 11
};
union ADCCHSELSEQ3_REG{
Uint16 all;
struct ADCCHSELSEQ3_BITS bit;
};
struct ADCCHSELSEQ4_BITS { // bits description
Uint16 CONV12:4; // 3:0 Conversion selection 12
Uint16 CONV13:4; // 7:4 Conversion selection 13
Uint16 CONV14:4; // 11:8 Conversion selection 14
Uint16 CONV15:4; // 15:12 Conversion selection 15
};
union ADCCHSELSEQ4_REG {
Uint16 all;
struct ADCCHSELSEQ4_BITS bit;
};
struct ADCTRL3_BITS { // bits description
Uint16 SMODE_SEL:1; // 0 Sampling mode select
Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider
Uint16 ADCPWDN:1; // 5 ADC powerdown
Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down
Uint16 rsvd1:8; // 15:8 reserved
};
union ADCTRL3_REG {
Uint16 all;
struct ADCTRL3_BITS bit;
};
struct ADCST_BITS { // bits description
Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag
Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag
Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status
Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status
Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear
Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear
Uint16 EOS_BUF1:1; // 6 End of sequence buffer1
Uint16 EOS_BUF2:1; // 7 End of sequence buffer2
Uint16 rsvd1:8; // 15:8 reserved
};
union ADCST_REG {
Uint16 all;
struct ADCST_BITS bit;
};
struct ADCREFSEL_BITS { // bits description
Uint16 rsvd1:14; // 13:0 reserved
Uint16 REF_SEL:2; // 15:14 Reference select
};
union ADCREFSEL_REG {
Uint16 all;
struct ADCREFSEL_BITS bit;
};
struct ADCOFFTRIM_BITS{ // bits description
int16 OFFSET_TRIM:9; // 8:0 Offset Trim
Uint16 rsvd1:7; // 15:9 reserved
};
union ADCOFFTRIM_REG{
Uint16 all;
struct ADCOFFTRIM_BITS bit;
};
struct ADC_REGS {
union ADCTRL1_REG ADCTRL1; // ADC Control 1
union ADCTRL2_REG ADCTRL2; // ADC Control 2
union ADCMAXCONV_REG ADCMAXCONV; // Max conversions
union ADCCHSELSEQ1_REG ADCCHSELSEQ1; // Channel select sequencing control 1
union ADCCHSELSEQ2_REG ADCCHSELSEQ2; // Channel select sequencing control 2
union ADCCHSELSEQ3_REG ADCCHSELSEQ3; // Channel select sequencing control 3
union ADCCHSELSEQ4_REG ADCCHSELSEQ4; // Channel select sequencing control 4
union ADCASEQSR_REG ADCASEQSR; // Autosequence status register
Uint16 ADCRESULT0; // Conversion Result Buffer 0
Uint16 ADCRESULT1; // Conversion Result Buffer 1
Uint16 ADCRESULT2; // Conversion Result Buffer 2
Uint16 ADCRESULT3; // Conversion Result Buffer 3
Uint16 ADCRESULT4; // Conversion Result Buffer 4
Uint16 ADCRESULT5; // Conversion Result Buffer 5
Uint16 ADCRESULT6; // Conversion Result Buffer 6
Uint16 ADCRESULT7; // Conversion Result Buffer 7
Uint16 ADCRESULT8; // Conversion Result Buffer 8
Uint16 ADCRESULT9; // Conversion Result Buffer 9
Uint16 ADCRESULT10; // Conversion Result Buffer 10
Uint16 ADCRESULT11; // Conversion Result Buffer 11
Uint16 ADCRESULT12; // Conversion Result Buffer 12
Uint16 ADCRESULT13; // Conversion Result Buffer 13
Uint16 ADCRESULT14; // Conversion Result Buffer 14
Uint16 ADCRESULT15; // Conversion Result Buffer 15
union ADCTRL3_REG ADCTRL3; // ADC Control 3
union ADCST_REG ADCST; // ADC Status Register
Uint16 rsvd1;
Uint16 rsvd2;
union ADCREFSEL_REG ADCREFSEL; // Reference Select Register
union ADCOFFTRIM_REG ADCOFFTRIM; // Offset Trim Register
};
struct ADC_RESULT_MIRROR_REGS
{
Uint16 ADCRESULT0; // Conversion Result Buffer 0
Uint16 ADCRESULT1; // Conversion Result Buffer 1
Uint16 ADCRESULT2; // Conversion Result Buffer 2
Uint16 ADCRESULT3; // Conversion Result Buffer 3
Uint16 ADCRESULT4; // Conversion Result Buffer 4
Uint16 ADCRESULT5; // Conversion Result Buffer 5
Uint16 ADCRESULT6; // Conversion Result Buffer 6
Uint16 ADCRESULT7; // Conversion Result Buffer 7
Uint16 ADCRESULT8; // Conversion Result Buffer 8
Uint16 ADCRESULT9; // Conversion Result Buffer 9
Uint16 ADCRESULT10; // Conversion Result Buffer 10
Uint16 ADCRESULT11; // Conversion Result Buffer 11
Uint16 ADCRESULT12; // Conversion Result Buffer 12
Uint16 ADCRESULT13; // Conversion Result Buffer 13
Uint16 ADCRESULT14; // Conversion Result Buffer 14
Uint16 ADCRESULT15; // Conversion Result Buffer 15
};
//---------------------------------------------------------------------------
// ADC External References & Function Declarations:
//
extern volatile struct ADC_REGS AdcRegs;
extern volatile struct ADC_RESULT_MIRROR_REGS AdcMirror;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_ADC_H definition
//===========================================================================
// End of file.
//===========================================================================

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v120/DSP2833x_headers/include/DSP2833x_CpuTimers.h Normal file
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// TI File $Revision: /main/4 $
// Checkin $Date: March 20, 2007 15:33:42 $
//###########################################################################
//
// FILE: DSP2833x_CpuTimers.h
//
// TITLE: DSP2833x CPU 32-bit Timers Register Definitions.
//
// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and
// other realtime operating systems.
//
// Do not use these two timers in your application if you ever plan
// on integrating DSP-BIOS or another realtime OS.
//
// For this reason, comment out the code to manipulate these two timers
// if using DSP-BIOS or another realtime OS.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_CPU_TIMERS_H
#define DSP2833x_CPU_TIMERS_H
#ifdef __cplusplus
extern "C" {
#endif
//---------------------------------------------------------------------------
// CPU Timer Register Bit Definitions:
//
//
// TCR: Control register bit definitions:
struct TCR_BITS { // bits description
Uint16 rsvd1:4; // 3:0 reserved
Uint16 TSS:1; // 4 Timer Start/Stop
Uint16 TRB:1; // 5 Timer reload
Uint16 rsvd2:4; // 9:6 reserved
Uint16 SOFT:1; // 10 Emulation modes
Uint16 FREE:1; // 11
Uint16 rsvd3:2; // 12:13 reserved
Uint16 TIE:1; // 14 Output enable
Uint16 TIF:1; // 15 Interrupt flag
};
union TCR_REG {
Uint16 all;
struct TCR_BITS bit;
};
// TPR: Pre-scale low bit definitions:
struct TPR_BITS { // bits description
Uint16 TDDR:8; // 7:0 Divide-down low
Uint16 PSC:8; // 15:8 Prescale counter low
};
union TPR_REG {
Uint16 all;
struct TPR_BITS bit;
};
// TPRH: Pre-scale high bit definitions:
struct TPRH_BITS { // bits description
Uint16 TDDRH:8; // 7:0 Divide-down high
Uint16 PSCH:8; // 15:8 Prescale counter high
};
union TPRH_REG {
Uint16 all;
struct TPRH_BITS bit;
};
// TIM, TIMH: Timer register definitions:
struct TIM_REG {
Uint16 LSW;
Uint16 MSW;
};
union TIM_GROUP {
Uint32 all;
struct TIM_REG half;
};
// PRD, PRDH: Period register definitions:
struct PRD_REG {
Uint16 LSW;
Uint16 MSW;
};
union PRD_GROUP {
Uint32 all;
struct PRD_REG half;
};
//---------------------------------------------------------------------------
// CPU Timer Register File:
//
struct CPUTIMER_REGS {
union TIM_GROUP TIM; // Timer counter register
union PRD_GROUP PRD; // Period register
union TCR_REG TCR; // Timer control register
Uint16 rsvd1; // reserved
union TPR_REG TPR; // Timer pre-scale low
union TPRH_REG TPRH; // Timer pre-scale high
};
//---------------------------------------------------------------------------
// CPU Timer Support Variables:
//
struct CPUTIMER_VARS {
volatile struct CPUTIMER_REGS *RegsAddr;
Uint32 InterruptCount;
float CPUFreqInMHz;
float PeriodInUSec;
};
//---------------------------------------------------------------------------
// Function prototypes and external definitions:
//
void InitCpuTimers(void);
void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period);
extern volatile struct CPUTIMER_REGS CpuTimer0Regs;
extern struct CPUTIMER_VARS CpuTimer0;
// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS. Comment out CpuTimer1 and CpuTimer2 if using DSP BIOS or other RTOS
extern volatile struct CPUTIMER_REGS CpuTimer1Regs;
extern volatile struct CPUTIMER_REGS CpuTimer2Regs;
extern struct CPUTIMER_VARS CpuTimer1;
extern struct CPUTIMER_VARS CpuTimer2;
//---------------------------------------------------------------------------
// Usefull Timer Operations:
//
// Start Timer:
#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0
// Stop Timer:
#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1
// Reload Timer With period Value:
#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1
// Read 32-Bit Timer Value:
#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all
// Read 32-Bit Period Value:
#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all
// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS
// Do not use these two timers if you ever plan on integrating
// DSP-BIOS or another realtime OS.
//
// For this reason, comment out the code to manipulate these two timers
// if using DSP-BIOS or another realtime OS.
// Start Timer:
#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0
#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0
// Stop Timer:
#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1
#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1
// Reload Timer With period Value:
#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1
#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1
// Read 32-Bit Timer Value:
#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all
#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all
// Read 32-Bit Period Value:
#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all
#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_CPU_TIMERS_H definition
//===========================================================================
// End of file.
//===========================================================================

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v120/DSP2833x_headers/include/DSP2833x_DMA.h Normal file
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// TI File $Revision: /main/11 $
// Checkin $Date: June 23, 2008 11:34:15 $
//###########################################################################
//
// FILE: DSP2833x_DMA.h
//
// TITLE: DSP2833x DMA Module Register Bit Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_DMA_H
#define DSP2833x_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
//----------------------------------------------------
// Channel MODE register bit definitions:
struct MODE_BITS { // bits description
Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select Bits (R/W):
// 0 no interrupt
// 1 SEQ1INT & ADCSYNC
// 2 SEQ2INT
// 3 XINT1
// 4 XINT2
// 5 XINT3
// 6 XINT4
// 7 XINT5
// 8 XINT6
// 9 XINT7
// 10 XINT13
// 11 TINT0
// 12 TINT1
// 13 TINT2
// 14 MXEVTA & MXSYNCA
// 15 MREVTA & MRSYNCA
// 16 MXEVTB & MXSYNCB
// 17 MREVTB & MRSYNCB
// 18 ePWM1SOCA
// 19 ePWM1SOCB
// 20 ePWM2SOCA
// 21 ePWM2SOCB
// 22 ePWM3SOCA
// 23 ePWM3SOCB
// 24 ePWM4SOCA
// 25 ePWM4SOCB
// 26 ePWM5SOCA
// 27 ePWM5SOCB
// 28 ePWM6SOCA
// 29 ePWM6SOCB
// 30:31 no interrupt
Uint16 rsvd1:2; // 6:5 (R=0:0)
Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable (R/W):
// 0 overflow interrupt disabled
// 1 overflow interrupt enabled
Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable Bit (R/W):
// 0 peripheral interrupt disabled
// 1 peripheral interrupt enabled
Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode Bit (R/W):
// 0 generate interrupt at beginning of new transfer
// 1 generate interrupt at end of transfer
Uint16 ONESHOT:1; // 10 One Shot Mode Bit (R/W):
// 0 only interrupt event triggers single burst transfer
// 1 first interrupt triggers burst, continue until transfer count is zero
Uint16 CONTINUOUS:1; // 11 Continous Mode Bit (R/W):
// 0 stop when transfer count is zero
// 1 re-initialize when transfer count is zero
Uint16 SYNCE:1; // 12 Sync Enable Bit (R/W):
// 0 ignore selected interrupt sync signal
// 1 enable selected interrupt sync signal
Uint16 SYNCSEL:1; // 13 Sync Select Bit (R/W):
// 0 sync signal controls source wrap counter
// 1 sync signal controls destination wrap counter
Uint16 DATASIZE:1; // 14 Data Size Mode Bit (R/W):
// 0 16-bit data transfer size
// 1 32-bit data transfer size
Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit (R/W):
// 0 channel interrupt disabled
// 1 channel interrupt enabled
};
union MODE_REG {
Uint16 all;
struct MODE_BITS bit;
};
//----------------------------------------------------
// Channel CONTROL register bit definitions:
struct CONTROL_BITS { // bits description
Uint16 RUN:1; // 0 Run Bit (R=0/W=1)
Uint16 HALT:1; // 1 Halt Bit (R=0/W=1)
Uint16 SOFTRESET:1; // 2 Soft Reset Bit (R=0/W=1)
Uint16 PERINTFRC:1; // 3 Interrupt Force Bit (R=0/W=1)
Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit (R=0/W=1)
Uint16 SYNCFRC:1; // 5 Sync Force Bit (R=0/W=1)
Uint16 SYNCCLR:1; // 6 Sync Clear Bit (R=0/W=1)
Uint16 ERRCLR:1; // 7 Error Clear Bit (R=0/W=1)
Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit (R):
// 0 no interrupt pending
// 1 interrupt pending
Uint16 SYNCFLG:1; // 9 Sync Flag Bit (R):
// 0 no sync pending
// 1 sync pending
Uint16 SYNCERR:1; // 10 Sync Error Flag Bit (R):
// 0 no sync error
// 1 sync error detected
Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit (R):
// 0 no transfer in progress or pending
// 1 transfer in progress or pending
Uint16 BURSTSTS:1; // 12 Burst Status Bit (R):
// 0 no burst in progress or pending
// 1 burst in progress or pending
Uint16 RUNSTS:1; // 13 Run Status Bit (R):
// 0 channel not running or halted
// 1 channel running
Uint16 OVRFLG:1; // 14 Overflow Flag Bit(R)
// 0 no overflow event
// 1 overflow event
Uint16 rsvd1:1; // 15 (R=0)
};
union CONTROL_REG {
Uint16 all;
struct CONTROL_BITS bit;
};
//----------------------------------------------------
// DMACTRL register bit definitions:
struct DMACTRL_BITS { // bits description
Uint16 HARDRESET:1; // 0 Hard Reset Bit (R=0/W=1)
Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit (R=0/W=1)
Uint16 rsvd1:14; // 15:2 (R=0:0)
};
union DMACTRL_REG {
Uint16 all;
struct DMACTRL_BITS bit;
};
//----------------------------------------------------
// DEBUGCTRL register bit definitions:
struct DEBUGCTRL_BITS { // bits description
Uint16 rsvd1:15; // 14:0 (R=0:0)
Uint16 FREE:1; // 15 Debug Mode Bit (R/W):
// 0 halt after current read-write operation
// 1 continue running
};
union DEBUGCTRL_REG {
Uint16 all;
struct DEBUGCTRL_BITS bit;
};
//----------------------------------------------------
// PRIORITYCTRL1 register bit definitions:
struct PRIORITYCTRL1_BITS { // bits description
Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit (R/W):
// 0 same priority as all other channels
// 1 highest priority channel
Uint16 rsvd1:15; // 15:1 (R=0:0)
};
union PRIORITYCTRL1_REG {
Uint16 all;
struct PRIORITYCTRL1_BITS bit;
};
//----------------------------------------------------
// PRIORITYSTAT register bit definitions:
struct PRIORITYSTAT_BITS { // bits description
Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits (R):
// 0,0,0 no channel active
// 0,0,1 Ch1 channel active
// 0,1,0 Ch2 channel active
// 0,1,1 Ch3 channel active
// 1,0,0 Ch4 channel active
// 1,0,1 Ch5 channel active
// 1,1,0 Ch6 channel active
Uint16 rsvd1:1; // 3 (R=0)
Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits (R):
// 0,0,0 no channel active and interrupted by Ch1
// 0,0,1 cannot occur
// 0,1,0 Ch2 was active and interrupted by Ch1
// 0,1,1 Ch3 was active and interrupted by Ch1
// 1,0,0 Ch4 was active and interrupted by Ch1
// 1,0,1 Ch5 was active and interrupted by Ch1
// 1,1,0 Ch6 was active and interrupted by Ch1
Uint16 rsvd2:9; // 15:7 (R=0:0)
};
union PRIORITYSTAT_REG {
Uint16 all;
struct PRIORITYSTAT_BITS bit;
};
// Burst Size
struct BURST_SIZE_BITS { // bits description
Uint16 BURSTSIZE:5; // 4:0 Burst transfer size
Uint16 rsvd1:11; // 15:5 reserved
};
union BURST_SIZE_REG {
Uint16 all;
struct BURST_SIZE_BITS bit;
};
// Burst Count
struct BURST_COUNT_BITS { // bits description
Uint16 BURSTCOUNT:5; // 4:0 Burst transfer size
Uint16 rsvd1:11; // 15:5 reserved
};
union BURST_COUNT_REG {
Uint16 all;
struct BURST_COUNT_BITS bit;
};
//----------------------------------------------------
// DMA Channel Registers:
struct CH_REGS {
union MODE_REG MODE; // Mode Register
union CONTROL_REG CONTROL; // Control Register
union BURST_SIZE_REG BURST_SIZE; // Burst Size Register
union BURST_COUNT_REG BURST_COUNT; // Burst Count Register
int16 SRC_BURST_STEP; // Source Burst Step Register
int16 DST_BURST_STEP; // Destination Burst Step Register
Uint16 TRANSFER_SIZE; // Transfer Size Register
Uint16 TRANSFER_COUNT; // Transfer Count Register
int16 SRC_TRANSFER_STEP; // Source Transfer Step Register
int16 DST_TRANSFER_STEP; // Destination Transfer Step Register
Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register
Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register
int16 SRC_WRAP_STEP; // Source Wrap Step Register
Uint16 DST_WRAP_SIZE; // Destination Wrap Size Register
Uint16 DST_WRAP_COUNT; // Destination Wrap Count Register
int16 DST_WRAP_STEP; // Destination Wrap Step Register
Uint32 SRC_BEG_ADDR_SHADOW; // Source Begin Address Shadow Register
Uint32 SRC_ADDR_SHADOW; // Source Address Shadow Register
Uint32 SRC_BEG_ADDR_ACTIVE; // Source Begin Address Active Register
Uint32 SRC_ADDR_ACTIVE; // Source Address Active Register
Uint32 DST_BEG_ADDR_SHADOW; // Destination Begin Address Shadow Register
Uint32 DST_ADDR_SHADOW; // Destination Address Shadow Register
Uint32 DST_BEG_ADDR_ACTIVE; // Destination Begin Address Active Register
Uint32 DST_ADDR_ACTIVE; // Destination Address Active Register
};
//----------------------------------------------------
// DMA Registers:
struct DMA_REGS {
union DMACTRL_REG DMACTRL; // DMA Control Register
union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register
Uint16 rsvd0; // reserved
Uint16 rsvd1; //
union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register
Uint16 rsvd2; //
union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register
Uint16 rsvd3[25]; //
struct CH_REGS CH1; // DMA Channel 1 Registers
struct CH_REGS CH2; // DMA Channel 2 Registers
struct CH_REGS CH3; // DMA Channel 3 Registers
struct CH_REGS CH4; // DMA Channel 4 Registers
struct CH_REGS CH5; // DMA Channel 5 Registers
struct CH_REGS CH6; // DMA Channel 6 Registers
};
//---------------------------------------------------------------------------
// External References & Function Declarations:
//
extern volatile struct DMA_REGS DmaRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_DMA_H definition
//===========================================================================
// End of file.
//===========================================================================

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v120/DSP2833x_headers/include/DSP2833x_DevEmu.h Normal file
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// TI File $Revision: /main/3 $
// Checkin $Date: June 2, 2008 11:12:30 $
//###########################################################################
//
// FILE: DSP2833x_DevEmu.h
//
// TITLE: DSP2833x Device Emulation Register Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_DEV_EMU_H
#define DSP2833x_DEV_EMU_H
#ifdef __cplusplus
extern "C" {
#endif
//---------------------------------------------------------------------------
// Device Emulation Register Bit Definitions:
//
// Device Configuration Register Bit Definitions
struct DEVICECNF_BITS { // bits description
Uint16 rsvd1:3; // 2:0 reserved
Uint16 VMAPS:1; // 3 VMAP Status
Uint16 rsvd2:1; // 4 reserved
Uint16 XRSn:1; // 5 XRSn Signal Status
Uint16 rsvd3:10; // 15:6
Uint16 rsvd4:3; // 18:16
Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection
Uint16 MONPRIV:1; // 20 MONPRIV enable bit
Uint16 rsvd5:1; // 21 reserved
Uint16 EMU0SEL:2; // 23,22 EMU0 Mux select
Uint16 EMU1SEL:2; // 25,24 EMU1 Mux select
Uint16 MCBSPCON:1; // 26 McBSP-B to EMU0/EMU1 pins control
Uint16 rsvd6:5; // 31:27 reserved
};
union DEVICECNF_REG {
Uint32 all;
struct DEVICECNF_BITS bit;
};
// CLASSID
struct CLASSID_BITS { // bits description
Uint16 CLASSNO:8; // 7:0 Class Number
Uint16 PARTTYPE:8; // 15:8 Part Type
};
union CLASSID_REG {
Uint16 all;
struct CLASSID_BITS bit;
};
struct DEV_EMU_REGS {
union DEVICECNF_REG DEVICECNF; // device configuration
union CLASSID_REG CLASSID; // Class ID
Uint16 REVID; // Device ID
Uint16 PROTSTART; // Write-Read protection start
Uint16 PROTRANGE; // Write-Read protection range
Uint16 rsvd2[202];
};
// PARTID
struct PARTID_BITS { // bits description
Uint16 PARTNO:8; // 7:0 Part Number
Uint16 PARTTYPE:8; // 15:8 Part Type
};
union PARTID_REG {
Uint16 all;
struct PARTID_BITS bit;
};
struct PARTID_REGS {
union PARTID_REG PARTID; // Part ID
};
//---------------------------------------------------------------------------
// Device Emulation Register References & Function Declarations:
//
extern volatile struct DEV_EMU_REGS DevEmuRegs;
extern volatile struct PARTID_REGS PartIdRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_DEV_EMU_H definition
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/5 $
// Checkin $Date: January 22, 2008 16:55:35 $
//###########################################################################
//
// FILE: DSP2833x_Device.h
//
// TITLE: DSP2833x Device Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_DEVICE_H
#define DSP2833x_DEVICE_H
#ifdef __cplusplus
extern "C" {
#endif
#define TARGET 1
//---------------------------------------------------------------------------
// User To Select Target Device:
#define DSP28_28335 TARGET // Selects '28335/'28235
#define DSP28_28334 0 // Selects '28334/'28234
#define DSP28_28332 0 // Selects '28332/'28232
//---------------------------------------------------------------------------
// Common CPU Definitions:
//
extern cregister volatile unsigned int IFR;
extern cregister volatile unsigned int IER;
#define EINT asm(" clrc INTM")
#define DINT asm(" setc INTM")
#define ERTM asm(" clrc DBGM")
#define DRTM asm(" setc DBGM")
#define EALLOW asm(" EALLOW")
#define EDIS asm(" EDIS")
#define ESTOP0 asm(" ESTOP0")
#define M_INT1 0x0001
#define M_INT2 0x0002
#define M_INT3 0x0004
#define M_INT4 0x0008
#define M_INT5 0x0010
#define M_INT6 0x0020
#define M_INT7 0x0040
#define M_INT8 0x0080
#define M_INT9 0x0100
#define M_INT10 0x0200
#define M_INT11 0x0400
#define M_INT12 0x0800
#define M_INT13 0x1000
#define M_INT14 0x2000
#define M_DLOG 0x4000
#define M_RTOS 0x8000
#define BIT0 0x0001
#define BIT1 0x0002
#define BIT2 0x0004
#define BIT3 0x0008
#define BIT4 0x0010
#define BIT5 0x0020
#define BIT6 0x0040
#define BIT7 0x0080
#define BIT8 0x0100
#define BIT9 0x0200
#define BIT10 0x0400
#define BIT11 0x0800
#define BIT12 0x1000
#define BIT13 0x2000
#define BIT14 0x4000
#define BIT15 0x8000
//---------------------------------------------------------------------------
// For Portability, User Is Recommended To Use Following Data Type Size
// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers:
//
#ifndef DSP28_DATA_TYPES
#define DSP28_DATA_TYPES
typedef int int16;
typedef long int32;
typedef long long int64;
typedef unsigned int Uint16;
typedef unsigned long Uint32;
typedef unsigned long long Uint64;
typedef float float32;
typedef long double float64;
#endif
typedef union
{
struct
{
unsigned int bit0: 1;
unsigned int bit1: 1;
unsigned int bit2: 1;
unsigned int bit3: 1;
unsigned int bit4: 1;
unsigned int bit5: 1;
unsigned int bit6: 1;
unsigned int bit7: 1;
} bit;
struct
{
unsigned int quad_0 :4;
unsigned int quad_1 :4;
} qua;
unsigned short all;
} BAITE;
typedef union
{
struct
{
unsigned int bit0: 1;
unsigned int bit1: 1;
unsigned int bit2: 1;
unsigned int bit3: 1;
unsigned int bit4: 1;
unsigned int bit5: 1;
unsigned int bit6: 1;
unsigned int bit7: 1;
unsigned int bit8: 1;
unsigned int bit9: 1;
unsigned int bitA: 1;
unsigned int bitB: 1;
unsigned int bitC: 1;
unsigned int bitD: 1;
unsigned int bitE: 1;
unsigned int bitF: 1;
} bit;
struct
{
unsigned int quad_0 :4;
unsigned int quad_1 :4;
unsigned int quad_2 :4;
unsigned int quad_3 :4;
} qua;
struct
{
unsigned int byte_0 :8;
unsigned int byte_1 :8;
} byt;
int all;
} WORDE;
typedef union
{
struct
{
unsigned int bit00: 1;
unsigned int bit01: 1;
unsigned int bit02: 1;
unsigned int bit03: 1;
unsigned int bit04: 1;
unsigned int bit05: 1;
unsigned int bit06: 1;
unsigned int bit07: 1;
unsigned int bit08: 1;
unsigned int bit09: 1;
unsigned int bit0A: 1;
unsigned int bit0B: 1;
unsigned int bit0C: 1;
unsigned int bit0D: 1;
unsigned int bit0E: 1;
unsigned int bit0F: 1;
unsigned int bit10: 1;
unsigned int bit11: 1;
unsigned int bit12: 1;
unsigned int bit13: 1;
unsigned int bit14: 1;
unsigned int bit15: 1;
unsigned int bit16: 1;
unsigned int bit17: 1;
unsigned int bit18: 1;
unsigned int bit19: 1;
unsigned int bit1A: 1;
unsigned int bit1B: 1;
unsigned int bit1C: 1;
unsigned int bit1D: 1;
unsigned int bit1E: 1;
unsigned int bit1F: 1;
} bit;
struct
{
unsigned int quad_0 :4;
unsigned int quad_1 :4;
unsigned int quad_2 :4;
unsigned int quad_3 :4;
unsigned int quad_4 :4;
unsigned int quad_5 :4;
unsigned int quad_6 :4;
unsigned int quad_7 :4;
} qua;
struct
{
unsigned int byte_0 :8;
unsigned int byte_1 :8;
unsigned int byte_2 :8;
unsigned int byte_3 :8;
} byt;
struct
{
unsigned int word_0 :16;
unsigned int word_1 :16;
} wrd;
unsigned long all;
} LONGE;
#define XCLKIN 30000000 // external oscillator frequency
extern long SYSCLKOUT, LSPCLK, HSPCLK;
#define CLKMULT 2L // 1 to 5
#define LOWORD(l)((short int)( (long int)(l) &0xFFFF))
#define HIWORD(l)((short int)(((long int)(l)>>16)&0xFFFF))
#define LOBYTE(w)((char)( (short int)(w) &0xFF))
#define HIBYTE(w)((char)(((short int)(w)>>8)&0xFF))
#define BYTE3(l)((char)(((long int)(l)>>24)&0xFF))
#define BYTE2(l)((char)(((long int)(l)>>16)&0xFF))
#define BYTE1(l)((char)(((long int)(l)>> 8)&0xFF))
#define BYTE0(l)((char)( (long int)(l) &0xFF))
//---------------------------------------------------------------------------
// Include All Peripheral Header Files:
//
#include "DSP2833x_Adc.h" // ADC Registers
#include "DSP2833x_DevEmu.h" // Device Emulation Registers
#include "DSP2833x_CpuTimers.h" // 32-bit CPU Timers
#include "DSP2833x_ECan.h" // Enhanced eCAN Registers
#include "DSP2833x_ECap.h" // Enhanced Capture
#include "DSP2833x_DMA.h" // DMA Registers
#include "DSP2833x_EPwm.h" // Enhanced PWM
#include "DSP2833x_EQep.h" // Enhanced QEP
#include "DSP2833x_Gpio.h" // General Purpose I/O Registers
#include "DSP2833x_I2c.h" // I2C Registers
#include "DSP2833x_McBSP.h" // McBSP
#include "DSP2833x_PieCtrl.h" // PIE Control Registers
#include "DSP2833x_PieVect.h" // PIE Vector Table
#include "DSP2833x_Spi.h" // SPI Registers
#include "DSP2833x_Sci.h" // SCI Registers
#include "DSP2833x_SysCtrl.h" // System Control/Power Modes
#include "DSP2833x_XIntrupt.h" // External Interrupts
#include "DSP2833x_Xintf.h" // XINTF External Interface
#include "DSP2833x_GlobalPrototypes.h" // Prototypes for global functions within the
#if DSP28_28335
#define DSP28_EPWM1 1
#define DSP28_EPWM2 1
#define DSP28_EPWM3 1
#define DSP28_EPWM4 1
#define DSP28_EPWM5 1
#define DSP28_EPWM6 1
#define DSP28_ECAP1 1
#define DSP28_ECAP2 1
#define DSP28_ECAP3 1
#define DSP28_ECAP4 1
#define DSP28_ECAP5 1
#define DSP28_ECAP6 1
#define DSP28_EQEP1 1
#define DSP28_EQEP2 1
#define DSP28_ECANA 1
#define DSP28_ECANB 1
#define DSP28_MCBSPA 1
#define DSP28_MCBSPB 1
#define DSP28_SPIA 1
#define DSP28_SCIA 1
#define DSP28_SCIB 1
#define DSP28_SCIC 1
#define DSP28_I2CA 1
#endif // end DSP28_28335
#if DSP28_28334
#define DSP28_EPWM1 1
#define DSP28_EPWM2 1
#define DSP28_EPWM3 1
#define DSP28_EPWM4 1
#define DSP28_EPWM5 1
#define DSP28_EPWM6 1
#define DSP28_ECAP1 1
#define DSP28_ECAP2 1
#define DSP28_ECAP3 1
#define DSP28_ECAP4 1
#define DSP28_ECAP5 0
#define DSP28_ECAP6 0
#define DSP28_EQEP1 1
#define DSP28_EQEP2 1
#define DSP28_ECANA 1
#define DSP28_ECANB 1
#define DSP28_MCBSPA 1
#define DSP28_MCBSPB 1
#define DSP28_SPIA 1
#define DSP28_SCIA 1
#define DSP28_SCIB 1
#define DSP28_SCIC 1
#define DSP28_I2CA 1
#endif // end DSP28_28334
#if DSP28_28332
#define DSP28_EPWM1 1
#define DSP28_EPWM2 1
#define DSP28_EPWM3 1
#define DSP28_EPWM4 1
#define DSP28_EPWM5 1
#define DSP28_EPWM6 1
#define DSP28_ECAP1 1
#define DSP28_ECAP2 1
#define DSP28_ECAP3 1
#define DSP28_ECAP4 1
#define DSP28_ECAP5 0
#define DSP28_ECAP6 0
#define DSP28_EQEP1 1
#define DSP28_EQEP2 1
#define DSP28_ECANA 1
#define DSP28_ECANB 1
#define DSP28_MCBSPA 1
#define DSP28_MCBSPB 0
#define DSP28_SPIA 1
#define DSP28_SCIA 1
#define DSP28_SCIB 1
#define DSP28_SCIC 0
#define DSP28_I2CA 1
#endif // end DSP28_28332
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_DEVICE_H definition
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/2 $
// Checkin $Date: May 7, 2007 16:05:39 $
//###########################################################################
//
// FILE: DSP2833x_ECan.h
//
// TITLE: DSP2833x Device eCAN Register Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_ECAN_H
#define DSP2833x_ECAN_H
#ifdef __cplusplus
extern "C" {
#endif
/* --------------------------------------------------- */
/* eCAN Control & Status Registers */
/* ----------------------------------------------------*/
/* eCAN Mailbox enable register (CANME) bit definitions */
struct CANME_BITS { // bit description
Uint16 ME0:1; // 0 Enable Mailbox 0
Uint16 ME1:1; // 1 Enable Mailbox 1
Uint16 ME2:1; // 2 Enable Mailbox 2
Uint16 ME3:1; // 3 Enable Mailbox 3
Uint16 ME4:1; // 4 Enable Mailbox 4
Uint16 ME5:1; // 5 Enable Mailbox 5
Uint16 ME6:1; // 6 Enable Mailbox 6
Uint16 ME7:1; // 7 Enable Mailbox 7
Uint16 ME8:1; // 8 Enable Mailbox 8
Uint16 ME9:1; // 9 Enable Mailbox 9
Uint16 ME10:1; // 10 Enable Mailbox 10
Uint16 ME11:1; // 11 Enable Mailbox 11
Uint16 ME12:1; // 12 Enable Mailbox 12
Uint16 ME13:1; // 13 Enable Mailbox 13
Uint16 ME14:1; // 14 Enable Mailbox 14
Uint16 ME15:1; // 15 Enable Mailbox 15
Uint16 ME16:1; // 16 Enable Mailbox 16
Uint16 ME17:1; // 17 Enable Mailbox 17
Uint16 ME18:1; // 18 Enable Mailbox 18
Uint16 ME19:1; // 19 Enable Mailbox 19
Uint16 ME20:1; // 20 Enable Mailbox 20
Uint16 ME21:1; // 21 Enable Mailbox 21
Uint16 ME22:1; // 22 Enable Mailbox 22
Uint16 ME23:1; // 23 Enable Mailbox 23
Uint16 ME24:1; // 24 Enable Mailbox 24
Uint16 ME25:1; // 25 Enable Mailbox 25
Uint16 ME26:1; // 26 Enable Mailbox 26
Uint16 ME27:1; // 27 Enable Mailbox 27
Uint16 ME28:1; // 28 Enable Mailbox 28
Uint16 ME29:1; // 29 Enable Mailbox 29
Uint16 ME30:1; // 30 Enable Mailbox 30
Uint16 ME31:1; // 31 Enable Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANME_REG {
Uint32 all;
struct CANME_BITS bit;
};
/* eCAN Mailbox direction register (CANMD) bit definitions */
struct CANMD_BITS { // bit description
Uint16 MD0:1; // 0 0 -> Tx 1 -> Rx
Uint16 MD1:1; // 1 0 -> Tx 1 -> Rx
Uint16 MD2:1; // 2 0 -> Tx 1 -> Rx
Uint16 MD3:1; // 3 0 -> Tx 1 -> Rx
Uint16 MD4:1; // 4 0 -> Tx 1 -> Rx
Uint16 MD5:1; // 5 0 -> Tx 1 -> Rx
Uint16 MD6:1; // 6 0 -> Tx 1 -> Rx
Uint16 MD7:1; // 7 0 -> Tx 1 -> Rx
Uint16 MD8:1; // 8 0 -> Tx 1 -> Rx
Uint16 MD9:1; // 9 0 -> Tx 1 -> Rx
Uint16 MD10:1; // 10 0 -> Tx 1 -> Rx
Uint16 MD11:1; // 11 0 -> Tx 1 -> Rx
Uint16 MD12:1; // 12 0 -> Tx 1 -> Rx
Uint16 MD13:1; // 13 0 -> Tx 1 -> Rx
Uint16 MD14:1; // 14 0 -> Tx 1 -> Rx
Uint16 MD15:1; // 15 0 -> Tx 1 -> Rx
Uint16 MD16:1; // 16 0 -> Tx 1 -> Rx
Uint16 MD17:1; // 17 0 -> Tx 1 -> Rx
Uint16 MD18:1; // 18 0 -> Tx 1 -> Rx
Uint16 MD19:1; // 19 0 -> Tx 1 -> Rx
Uint16 MD20:1; // 20 0 -> Tx 1 -> Rx
Uint16 MD21:1; // 21 0 -> Tx 1 -> Rx
Uint16 MD22:1; // 22 0 -> Tx 1 -> Rx
Uint16 MD23:1; // 23 0 -> Tx 1 -> Rx
Uint16 MD24:1; // 24 0 -> Tx 1 -> Rx
Uint16 MD25:1; // 25 0 -> Tx 1 -> Rx
Uint16 MD26:1; // 26 0 -> Tx 1 -> Rx
Uint16 MD27:1; // 27 0 -> Tx 1 -> Rx
Uint16 MD28:1; // 28 0 -> Tx 1 -> Rx
Uint16 MD29:1; // 29 0 -> Tx 1 -> Rx
Uint16 MD30:1; // 30 0 -> Tx 1 -> Rx
Uint16 MD31:1; // 31 0 -> Tx 1 -> Rx
};
/* Allow access to the bit fields or entire register */
union CANMD_REG {
Uint32 all;
struct CANMD_BITS bit;
};
/* eCAN Transmit Request Set register (CANTRS) bit definitions */
struct CANTRS_BITS { // bit description
Uint16 TRS0:1; // 0 TRS for Mailbox 0
Uint16 TRS1:1; // 1 TRS for Mailbox 1
Uint16 TRS2:1; // 2 TRS for Mailbox 2
Uint16 TRS3:1; // 3 TRS for Mailbox 3
Uint16 TRS4:1; // 4 TRS for Mailbox 4
Uint16 TRS5:1; // 5 TRS for Mailbox 5
Uint16 TRS6:1; // 6 TRS for Mailbox 6
Uint16 TRS7:1; // 7 TRS for Mailbox 7
Uint16 TRS8:1; // 8 TRS for Mailbox 8
Uint16 TRS9:1; // 9 TRS for Mailbox 9
Uint16 TRS10:1; // 10 TRS for Mailbox 10
Uint16 TRS11:1; // 11 TRS for Mailbox 11
Uint16 TRS12:1; // 12 TRS for Mailbox 12
Uint16 TRS13:1; // 13 TRS for Mailbox 13
Uint16 TRS14:1; // 14 TRS for Mailbox 14
Uint16 TRS15:1; // 15 TRS for Mailbox 15
Uint16 TRS16:1; // 16 TRS for Mailbox 16
Uint16 TRS17:1; // 17 TRS for Mailbox 17
Uint16 TRS18:1; // 18 TRS for Mailbox 18
Uint16 TRS19:1; // 19 TRS for Mailbox 19
Uint16 TRS20:1; // 20 TRS for Mailbox 20
Uint16 TRS21:1; // 21 TRS for Mailbox 21
Uint16 TRS22:1; // 22 TRS for Mailbox 22
Uint16 TRS23:1; // 23 TRS for Mailbox 23
Uint16 TRS24:1; // 24 TRS for Mailbox 24
Uint16 TRS25:1; // 25 TRS for Mailbox 25
Uint16 TRS26:1; // 26 TRS for Mailbox 26
Uint16 TRS27:1; // 27 TRS for Mailbox 27
Uint16 TRS28:1; // 28 TRS for Mailbox 28
Uint16 TRS29:1; // 29 TRS for Mailbox 29
Uint16 TRS30:1; // 30 TRS for Mailbox 30
Uint16 TRS31:1; // 31 TRS for Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANTRS_REG {
Uint32 all;
struct CANTRS_BITS bit;
};
/* eCAN Transmit Request Reset register (CANTRR) bit definitions */
struct CANTRR_BITS { // bit description
Uint16 TRR0:1; // 0 TRR for Mailbox 0
Uint16 TRR1:1; // 1 TRR for Mailbox 1
Uint16 TRR2:1; // 2 TRR for Mailbox 2
Uint16 TRR3:1; // 3 TRR for Mailbox 3
Uint16 TRR4:1; // 4 TRR for Mailbox 4
Uint16 TRR5:1; // 5 TRR for Mailbox 5
Uint16 TRR6:1; // 6 TRR for Mailbox 6
Uint16 TRR7:1; // 7 TRR for Mailbox 7
Uint16 TRR8:1; // 8 TRR for Mailbox 8
Uint16 TRR9:1; // 9 TRR for Mailbox 9
Uint16 TRR10:1; // 10 TRR for Mailbox 10
Uint16 TRR11:1; // 11 TRR for Mailbox 11
Uint16 TRR12:1; // 12 TRR for Mailbox 12
Uint16 TRR13:1; // 13 TRR for Mailbox 13
Uint16 TRR14:1; // 14 TRR for Mailbox 14
Uint16 TRR15:1; // 15 TRR for Mailbox 15
Uint16 TRR16:1; // 16 TRR for Mailbox 16
Uint16 TRR17:1; // 17 TRR for Mailbox 17
Uint16 TRR18:1; // 18 TRR for Mailbox 18
Uint16 TRR19:1; // 19 TRR for Mailbox 19
Uint16 TRR20:1; // 20 TRR for Mailbox 20
Uint16 TRR21:1; // 21 TRR for Mailbox 21
Uint16 TRR22:1; // 22 TRR for Mailbox 22
Uint16 TRR23:1; // 23 TRR for Mailbox 23
Uint16 TRR24:1; // 24 TRR for Mailbox 24
Uint16 TRR25:1; // 25 TRR for Mailbox 25
Uint16 TRR26:1; // 26 TRR for Mailbox 26
Uint16 TRR27:1; // 27 TRR for Mailbox 27
Uint16 TRR28:1; // 28 TRR for Mailbox 28
Uint16 TRR29:1; // 29 TRR for Mailbox 29
Uint16 TRR30:1; // 30 TRR for Mailbox 30
Uint16 TRR31:1; // 31 TRR for Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANTRR_REG {
Uint32 all;
struct CANTRR_BITS bit;
};
/* eCAN Transmit Acknowledge register (CANTA) bit definitions */
struct CANTA_BITS { // bit description
Uint16 TA0:1; // 0 TA for Mailbox 0
Uint16 TA1:1; // 1 TA for Mailbox 1
Uint16 TA2:1; // 2 TA for Mailbox 2
Uint16 TA3:1; // 3 TA for Mailbox 3
Uint16 TA4:1; // 4 TA for Mailbox 4
Uint16 TA5:1; // 5 TA for Mailbox 5
Uint16 TA6:1; // 6 TA for Mailbox 6
Uint16 TA7:1; // 7 TA for Mailbox 7
Uint16 TA8:1; // 8 TA for Mailbox 8
Uint16 TA9:1; // 9 TA for Mailbox 9
Uint16 TA10:1; // 10 TA for Mailbox 10
Uint16 TA11:1; // 11 TA for Mailbox 11
Uint16 TA12:1; // 12 TA for Mailbox 12
Uint16 TA13:1; // 13 TA for Mailbox 13
Uint16 TA14:1; // 14 TA for Mailbox 14
Uint16 TA15:1; // 15 TA for Mailbox 15
Uint16 TA16:1; // 16 TA for Mailbox 16
Uint16 TA17:1; // 17 TA for Mailbox 17
Uint16 TA18:1; // 18 TA for Mailbox 18
Uint16 TA19:1; // 19 TA for Mailbox 19
Uint16 TA20:1; // 20 TA for Mailbox 20
Uint16 TA21:1; // 21 TA for Mailbox 21
Uint16 TA22:1; // 22 TA for Mailbox 22
Uint16 TA23:1; // 23 TA for Mailbox 23
Uint16 TA24:1; // 24 TA for Mailbox 24
Uint16 TA25:1; // 25 TA for Mailbox 25
Uint16 TA26:1; // 26 TA for Mailbox 26
Uint16 TA27:1; // 27 TA for Mailbox 27
Uint16 TA28:1; // 28 TA for Mailbox 28
Uint16 TA29:1; // 29 TA for Mailbox 29
Uint16 TA30:1; // 30 TA for Mailbox 30
Uint16 TA31:1; // 31 TA for Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANTA_REG {
Uint32 all;
struct CANTA_BITS bit;
};
/* eCAN Transmit Abort Acknowledge register (CANAA) bit definitions */
struct CANAA_BITS { // bit description
Uint16 AA0:1; // 0 AA for Mailbox 0
Uint16 AA1:1; // 1 AA for Mailbox 1
Uint16 AA2:1; // 2 AA for Mailbox 2
Uint16 AA3:1; // 3 AA for Mailbox 3
Uint16 AA4:1; // 4 AA for Mailbox 4
Uint16 AA5:1; // 5 AA for Mailbox 5
Uint16 AA6:1; // 6 AA for Mailbox 6
Uint16 AA7:1; // 7 AA for Mailbox 7
Uint16 AA8:1; // 8 AA for Mailbox 8
Uint16 AA9:1; // 9 AA for Mailbox 9
Uint16 AA10:1; // 10 AA for Mailbox 10
Uint16 AA11:1; // 11 AA for Mailbox 11
Uint16 AA12:1; // 12 AA for Mailbox 12
Uint16 AA13:1; // 13 AA for Mailbox 13
Uint16 AA14:1; // 14 AA for Mailbox 14
Uint16 AA15:1; // 15 AA for Mailbox 15
Uint16 AA16:1; // 16 AA for Mailbox 16
Uint16 AA17:1; // 17 AA for Mailbox 17
Uint16 AA18:1; // 18 AA for Mailbox 18
Uint16 AA19:1; // 19 AA for Mailbox 19
Uint16 AA20:1; // 20 AA for Mailbox 20
Uint16 AA21:1; // 21 AA for Mailbox 21
Uint16 AA22:1; // 22 AA for Mailbox 22
Uint16 AA23:1; // 23 AA for Mailbox 23
Uint16 AA24:1; // 24 AA for Mailbox 24
Uint16 AA25:1; // 25 AA for Mailbox 25
Uint16 AA26:1; // 26 AA for Mailbox 26
Uint16 AA27:1; // 27 AA for Mailbox 27
Uint16 AA28:1; // 28 AA for Mailbox 28
Uint16 AA29:1; // 29 AA for Mailbox 29
Uint16 AA30:1; // 30 AA for Mailbox 30
Uint16 AA31:1; // 31 AA for Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANAA_REG {
Uint32 all;
struct CANAA_BITS bit;
};
/* eCAN Received Message Pending register (CANRMP) bit definitions */
struct CANRMP_BITS { // bit description
Uint16 RMP0:1; // 0 RMP for Mailbox 0
Uint16 RMP1:1; // 1 RMP for Mailbox 1
Uint16 RMP2:1; // 2 RMP for Mailbox 2
Uint16 RMP3:1; // 3 RMP for Mailbox 3
Uint16 RMP4:1; // 4 RMP for Mailbox 4
Uint16 RMP5:1; // 5 RMP for Mailbox 5
Uint16 RMP6:1; // 6 RMP for Mailbox 6
Uint16 RMP7:1; // 7 RMP for Mailbox 7
Uint16 RMP8:1; // 8 RMP for Mailbox 8
Uint16 RMP9:1; // 9 RMP for Mailbox 9
Uint16 RMP10:1; // 10 RMP for Mailbox 10
Uint16 RMP11:1; // 11 RMP for Mailbox 11
Uint16 RMP12:1; // 12 RMP for Mailbox 12
Uint16 RMP13:1; // 13 RMP for Mailbox 13
Uint16 RMP14:1; // 14 RMP for Mailbox 14
Uint16 RMP15:1; // 15 RMP for Mailbox 15
Uint16 RMP16:1; // 16 RMP for Mailbox 16
Uint16 RMP17:1; // 17 RMP for Mailbox 17
Uint16 RMP18:1; // 18 RMP for Mailbox 18
Uint16 RMP19:1; // 19 RMP for Mailbox 19
Uint16 RMP20:1; // 20 RMP for Mailbox 20
Uint16 RMP21:1; // 21 RMP for Mailbox 21
Uint16 RMP22:1; // 22 RMP for Mailbox 22
Uint16 RMP23:1; // 23 RMP for Mailbox 23
Uint16 RMP24:1; // 24 RMP for Mailbox 24
Uint16 RMP25:1; // 25 RMP for Mailbox 25
Uint16 RMP26:1; // 26 RMP for Mailbox 26
Uint16 RMP27:1; // 27 RMP for Mailbox 27
Uint16 RMP28:1; // 28 RMP for Mailbox 28
Uint16 RMP29:1; // 29 RMP for Mailbox 29
Uint16 RMP30:1; // 30 RMP for Mailbox 30
Uint16 RMP31:1; // 31 RMP for Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANRMP_REG {
Uint32 all;
struct CANRMP_BITS bit;
};
/* eCAN Received Message Lost register (CANRML) bit definitions */
struct CANRML_BITS { // bit description
Uint16 RML0:1; // 0 RML for Mailbox 0
Uint16 RML1:1; // 1 RML for Mailbox 1
Uint16 RML2:1; // 2 RML for Mailbox 2
Uint16 RML3:1; // 3 RML for Mailbox 3
Uint16 RML4:1; // 4 RML for Mailbox 4
Uint16 RML5:1; // 5 RML for Mailbox 5
Uint16 RML6:1; // 6 RML for Mailbox 6
Uint16 RML7:1; // 7 RML for Mailbox 7
Uint16 RML8:1; // 8 RML for Mailbox 8
Uint16 RML9:1; // 9 RML for Mailbox 9
Uint16 RML10:1; // 10 RML for Mailbox 10
Uint16 RML11:1; // 11 RML for Mailbox 11
Uint16 RML12:1; // 12 RML for Mailbox 12
Uint16 RML13:1; // 13 RML for Mailbox 13
Uint16 RML14:1; // 14 RML for Mailbox 14
Uint16 RML15:1; // 15 RML for Mailbox 15
Uint16 RML16:1; // 16 RML for Mailbox 16
Uint16 RML17:1; // 17 RML for Mailbox 17
Uint16 RML18:1; // 18 RML for Mailbox 18
Uint16 RML19:1; // 19 RML for Mailbox 19
Uint16 RML20:1; // 20 RML for Mailbox 20
Uint16 RML21:1; // 21 RML for Mailbox 21
Uint16 RML22:1; // 22 RML for Mailbox 22
Uint16 RML23:1; // 23 RML for Mailbox 23
Uint16 RML24:1; // 24 RML for Mailbox 24
Uint16 RML25:1; // 25 RML for Mailbox 25
Uint16 RML26:1; // 26 RML for Mailbox 26
Uint16 RML27:1; // 27 RML for Mailbox 27
Uint16 RML28:1; // 28 RML for Mailbox 28
Uint16 RML29:1; // 29 RML for Mailbox 29
Uint16 RML30:1; // 30 RML for Mailbox 30
Uint16 RML31:1; // 31 RML for Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANRML_REG {
Uint32 all;
struct CANRML_BITS bit;
};
/* eCAN Remote Frame Pending register (CANRFP) bit definitions */
struct CANRFP_BITS { // bit description
Uint16 RFP0:1; // 0 RFP for Mailbox 0
Uint16 RFP1:1; // 1 RFP for Mailbox 1
Uint16 RFP2:1; // 2 RFP for Mailbox 2
Uint16 RFP3:1; // 3 RFP for Mailbox 3
Uint16 RFP4:1; // 4 RFP for Mailbox 4
Uint16 RFP5:1; // 5 RFP for Mailbox 5
Uint16 RFP6:1; // 6 RFP for Mailbox 6
Uint16 RFP7:1; // 7 RFP for Mailbox 7
Uint16 RFP8:1; // 8 RFP for Mailbox 8
Uint16 RFP9:1; // 9 RFP for Mailbox 9
Uint16 RFP10:1; // 10 RFP for Mailbox 10
Uint16 RFP11:1; // 11 RFP for Mailbox 11
Uint16 RFP12:1; // 12 RFP for Mailbox 12
Uint16 RFP13:1; // 13 RFP for Mailbox 13
Uint16 RFP14:1; // 14 RFP for Mailbox 14
Uint16 RFP15:1; // 15 RFP for Mailbox 15
Uint16 RFP16:1; // 16 RFP for Mailbox 16
Uint16 RFP17:1; // 17 RFP for Mailbox 17
Uint16 RFP18:1; // 18 RFP for Mailbox 18
Uint16 RFP19:1; // 19 RFP for Mailbox 19
Uint16 RFP20:1; // 20 RFP for Mailbox 20
Uint16 RFP21:1; // 21 RFP for Mailbox 21
Uint16 RFP22:1; // 22 RFP for Mailbox 22
Uint16 RFP23:1; // 23 RFP for Mailbox 23
Uint16 RFP24:1; // 24 RFP for Mailbox 24
Uint16 RFP25:1; // 25 RFP for Mailbox 25
Uint16 RFP26:1; // 26 RFP for Mailbox 26
Uint16 RFP27:1; // 27 RFP for Mailbox 27
Uint16 RFP28:1; // 28 RFP for Mailbox 28
Uint16 RFP29:1; // 29 RFP for Mailbox 29
Uint16 RFP30:1; // 30 RFP for Mailbox 30
Uint16 RFP31:1; // 31 RFP for Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANRFP_REG {
Uint32 all;
struct CANRFP_BITS bit;
};
/* eCAN Global Acceptance Mask register (CANGAM) bit definitions */
struct CANGAM_BITS { // bits description
Uint16 GAM150:16; // 15:0 Global acceptance mask bits 0-15
Uint16 GAM2816:13; // 28:16 Global acceptance mask bits 16-28
Uint16 rsvd:2; // 30:29 reserved
Uint16 AMI:1; // 31 AMI bit
};
/* Allow access to the bit fields or entire register */
union CANGAM_REG {
Uint32 all;
struct CANGAM_BITS bit;
};
/* eCAN Master Control register (CANMC) bit definitions */
struct CANMC_BITS { // bits description
Uint16 MBNR:5; // 4:0 MBX # for CDR bit
Uint16 SRES:1; // 5 Soft reset
Uint16 STM:1; // 6 Self-test mode
Uint16 ABO:1; // 7 Auto bus-on
Uint16 CDR:1; // 8 Change data request
Uint16 WUBA:1; // 9 Wake-up on bus activity
Uint16 DBO:1; // 10 Data-byte order
Uint16 PDR:1; // 11 Power-down mode request
Uint16 CCR:1; // 12 Change configuration request
Uint16 SCB:1; // 13 SCC compatibility bit
Uint16 TCC:1; // 14 TSC MSB clear bit
Uint16 MBCC:1; // 15 TSC clear bit thru mailbox 16
Uint16 SUSP:1; // 16 SUSPEND free/soft bit
Uint16 rsvd:15; // 31:17 reserved
};
/* Allow access to the bit fields or entire register */
union CANMC_REG {
Uint32 all;
struct CANMC_BITS bit;
};
/* eCAN Bit -timing configuration register (CANBTC) bit definitions */
struct CANBTC_BITS { // bits description
Uint16 TSEG2REG:3; // 2:0 TSEG2 register value
Uint16 TSEG1REG:4; // 6:3 TSEG1 register value
Uint16 SAM:1; // 7 Sample-point setting
Uint16 SJWREG:2; // 9:8 Synchroniztion Jump Width register value
Uint16 rsvd1:6; // 15:10 reserved
Uint16 BRPREG:8; // 23:16 Baudrate prescaler register value
Uint16 rsvd2:8; // 31:24 reserved
};
/* Allow access to the bit fields or entire register */
union CANBTC_REG {
Uint32 all;
struct CANBTC_BITS bit;
};
/* eCAN Error & Status register (CANES) bit definitions */
struct CANES_BITS { // bits description
Uint16 TM:1; // 0 Transmit Mode
Uint16 RM:1; // 1 Receive Mode
Uint16 rsvd1:1; // 2 reserved
Uint16 PDA:1; // 3 Power-down acknowledge
Uint16 CCE:1; // 4 Change Configuration Enable
Uint16 SMA:1; // 5 Suspend Mode Acknowledge
Uint16 rsvd2:10; // 15:6 reserved
Uint16 EW:1; // 16 Warning status
Uint16 EP:1; // 17 Error Passive status
Uint16 BO:1; // 18 Bus-off status
Uint16 ACKE:1; // 19 Acknowledge error
Uint16 SE:1; // 20 Stuff error
Uint16 CRCE:1; // 21 CRC error
Uint16 SA1:1; // 22 Stuck at Dominant error
Uint16 BE:1; // 23 Bit error
Uint16 FE:1; // 24 Framing error
Uint16 rsvd3:7; // 31:25 reserved
};
/* Allow access to the bit fields or entire register */
union CANES_REG {
Uint32 all;
struct CANES_BITS bit;
};
/* eCAN Transmit Error Counter register (CANTEC) bit definitions */
struct CANTEC_BITS { // bits description
Uint16 TEC:8; // 7:0 TEC
Uint16 rsvd1:8; // 15:8 reserved
Uint16 rsvd2:16; // 31:16 reserved
};
/* Allow access to the bit fields or entire register */
union CANTEC_REG {
Uint32 all;
struct CANTEC_BITS bit;
};
/* eCAN Receive Error Counter register (CANREC) bit definitions */
struct CANREC_BITS { // bits description
Uint16 REC:8; // 7:0 REC
Uint16 rsvd1:8; // 15:8 reserved
Uint16 rsvd2:16; // 31:16 reserved
};
/* Allow access to the bit fields or entire register */
union CANREC_REG {
Uint32 all;
struct CANREC_BITS bit;
};
/* eCAN Global Interrupt Flag 0 (CANGIF0) bit definitions */
struct CANGIF0_BITS { // bits description
Uint16 MIV0:5; // 4:0 Mailbox Interrupt Vector
Uint16 rsvd1:3; // 7:5 reserved
Uint16 WLIF0:1; // 8 Warning level interrupt flag
Uint16 EPIF0:1; // 9 Error-passive interrupt flag
Uint16 BOIF0:1; // 10 Bus-off interrupt flag
Uint16 RMLIF0:1; // 11 Received message lost interrupt flag
Uint16 WUIF0:1; // 12 Wakeup interrupt flag
Uint16 WDIF0:1; // 13 Write denied interrupt flag
Uint16 AAIF0:1; // 14 Abort Ack interrupt flag
Uint16 GMIF0:1; // 15 Global MBX interrupt flag
Uint16 TCOF0:1; // 16 TSC Overflow flag
Uint16 MTOF0:1; // 17 Mailbox Timeout flag
Uint16 rsvd2:14; // 31:18 reserved
};
/* Allow access to the bit fields or entire register */
union CANGIF0_REG {
Uint32 all;
struct CANGIF0_BITS bit;
};
/* eCAN Global Interrupt Mask register (CANGIM) bit definitions */
struct CANGIM_BITS { // bits description
Uint16 I0EN:1; // 0 Interrupt 0 enable
Uint16 I1EN:1; // 1 Interrupt 1 enable
Uint16 GIL:1; // 2 Global Interrupt Level
Uint16 rsvd1:5; // 7:3 reserved
Uint16 WLIM:1; // 8 Warning level interrupt mask
Uint16 EPIM:1; // 9 Error-passive interrupt mask
Uint16 BOIM:1; // 10 Bus-off interrupt mask
Uint16 RMLIM:1; // 11 Received message lost interrupt mask
Uint16 WUIM:1; // 12 Wakeup interrupt mask
Uint16 WDIM:1; // 13 Write denied interrupt mask
Uint16 AAIM:1; // 14 Abort Ack interrupt mask
Uint16 rsvd2:1; // 15 reserved
Uint16 TCOM:1; // 16 TSC overflow interrupt mask
Uint16 MTOM:1; // 17 MBX Timeout interrupt mask
Uint16 rsvd3:14; // 31:18 reserved
};
/* Allow access to the bit fields or entire register */
union CANGIM_REG {
Uint32 all;
struct CANGIM_BITS bit;
};
/* eCAN Global Interrupt Flag 1 (eCANGIF1) bit definitions */
struct CANGIF1_BITS { // bits description
Uint16 MIV1:5; // 4:0 Mailbox Interrupt Vector
Uint16 rsvd1:3; // 7:5 reserved
Uint16 WLIF1:1; // 8 Warning level interrupt flag
Uint16 EPIF1:1; // 9 Error-passive interrupt flag
Uint16 BOIF1:1; // 10 Bus-off interrupt flag
Uint16 RMLIF1:1; // 11 Received message lost interrupt flag
Uint16 WUIF1:1; // 12 Wakeup interrupt flag
Uint16 WDIF1:1; // 13 Write denied interrupt flag
Uint16 AAIF1:1; // 14 Abort Ack interrupt flag
Uint16 GMIF1:1; // 15 Global MBX interrupt flag
Uint16 TCOF1:1; // 16 TSC Overflow flag
Uint16 MTOF1:1; // 17 Mailbox Timeout flag
Uint16 rsvd2:14; // 31:18 reserved
};
/* Allow access to the bit fields or entire register */
union CANGIF1_REG {
Uint32 all;
struct CANGIF1_BITS bit;
};
/* eCAN Mailbox Interrupt Mask register (CANMIM) bit definitions */
struct CANMIM_BITS { // bit description
Uint16 MIM0:1; // 0 MIM for Mailbox 0
Uint16 MIM1:1; // 1 MIM for Mailbox 1
Uint16 MIM2:1; // 2 MIM for Mailbox 2
Uint16 MIM3:1; // 3 MIM for Mailbox 3
Uint16 MIM4:1; // 4 MIM for Mailbox 4
Uint16 MIM5:1; // 5 MIM for Mailbox 5
Uint16 MIM6:1; // 6 MIM for Mailbox 6
Uint16 MIM7:1; // 7 MIM for Mailbox 7
Uint16 MIM8:1; // 8 MIM for Mailbox 8
Uint16 MIM9:1; // 9 MIM for Mailbox 9
Uint16 MIM10:1; // 10 MIM for Mailbox 10
Uint16 MIM11:1; // 11 MIM for Mailbox 11
Uint16 MIM12:1; // 12 MIM for Mailbox 12
Uint16 MIM13:1; // 13 MIM for Mailbox 13
Uint16 MIM14:1; // 14 MIM for Mailbox 14
Uint16 MIM15:1; // 15 MIM for Mailbox 15
Uint16 MIM16:1; // 16 MIM for Mailbox 16
Uint16 MIM17:1; // 17 MIM for Mailbox 17
Uint16 MIM18:1; // 18 MIM for Mailbox 18
Uint16 MIM19:1; // 19 MIM for Mailbox 19
Uint16 MIM20:1; // 20 MIM for Mailbox 20
Uint16 MIM21:1; // 21 MIM for Mailbox 21
Uint16 MIM22:1; // 22 MIM for Mailbox 22
Uint16 MIM23:1; // 23 MIM for Mailbox 23
Uint16 MIM24:1; // 24 MIM for Mailbox 24
Uint16 MIM25:1; // 25 MIM for Mailbox 25
Uint16 MIM26:1; // 26 MIM for Mailbox 26
Uint16 MIM27:1; // 27 MIM for Mailbox 27
Uint16 MIM28:1; // 28 MIM for Mailbox 28
Uint16 MIM29:1; // 29 MIM for Mailbox 29
Uint16 MIM30:1; // 30 MIM for Mailbox 30
Uint16 MIM31:1; // 31 MIM for Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANMIM_REG {
Uint32 all;
struct CANMIM_BITS bit;
};
/* eCAN Mailbox Interrupt Level register (CANMIL) bit definitions */
struct CANMIL_BITS { // bit description
Uint16 MIL0:1; // 0 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL1:1; // 1 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL2:1; // 2 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL3:1; // 3 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL4:1; // 4 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL5:1; // 5 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL6:1; // 6 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL7:1; // 7 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL8:1; // 8 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL9:1; // 9 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL10:1; // 10 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL11:1; // 11 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL12:1; // 12 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL13:1; // 13 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL14:1; // 14 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL15:1; // 15 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL16:1; // 16 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL17:1; // 17 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL18:1; // 18 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL19:1; // 19 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL20:1; // 20 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL21:1; // 21 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL22:1; // 22 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL23:1; // 23 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL24:1; // 24 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL25:1; // 25 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL26:1; // 26 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL27:1; // 27 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL28:1; // 28 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL29:1; // 29 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL30:1; // 30 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL31:1; // 31 0 -> Int 9.5 1 -> Int 9.6
};
/* Allow access to the bit fields or entire register */
union CANMIL_REG {
Uint32 all;
struct CANMIL_BITS bit;
};
/* eCAN Overwrite Protection Control register (CANOPC) bit definitions */
struct CANOPC_BITS { // bit description
Uint16 OPC0:1; // 0 OPC for Mailbox 0
Uint16 OPC1:1; // 1 OPC for Mailbox 1
Uint16 OPC2:1; // 2 OPC for Mailbox 2
Uint16 OPC3:1; // 3 OPC for Mailbox 3
Uint16 OPC4:1; // 4 OPC for Mailbox 4
Uint16 OPC5:1; // 5 OPC for Mailbox 5
Uint16 OPC6:1; // 6 OPC for Mailbox 6
Uint16 OPC7:1; // 7 OPC for Mailbox 7
Uint16 OPC8:1; // 8 OPC for Mailbox 8
Uint16 OPC9:1; // 9 OPC for Mailbox 9
Uint16 OPC10:1; // 10 OPC for Mailbox 10
Uint16 OPC11:1; // 11 OPC for Mailbox 11
Uint16 OPC12:1; // 12 OPC for Mailbox 12
Uint16 OPC13:1; // 13 OPC for Mailbox 13
Uint16 OPC14:1; // 14 OPC for Mailbox 14
Uint16 OPC15:1; // 15 OPC for Mailbox 15
Uint16 OPC16:1; // 16 OPC for Mailbox 16
Uint16 OPC17:1; // 17 OPC for Mailbox 17
Uint16 OPC18:1; // 18 OPC for Mailbox 18
Uint16 OPC19:1; // 19 OPC for Mailbox 19
Uint16 OPC20:1; // 20 OPC for Mailbox 20
Uint16 OPC21:1; // 21 OPC for Mailbox 21
Uint16 OPC22:1; // 22 OPC for Mailbox 22
Uint16 OPC23:1; // 23 OPC for Mailbox 23
Uint16 OPC24:1; // 24 OPC for Mailbox 24
Uint16 OPC25:1; // 25 OPC for Mailbox 25
Uint16 OPC26:1; // 26 OPC for Mailbox 26
Uint16 OPC27:1; // 27 OPC for Mailbox 27
Uint16 OPC28:1; // 28 OPC for Mailbox 28
Uint16 OPC29:1; // 29 OPC for Mailbox 29
Uint16 OPC30:1; // 30 OPC for Mailbox 30
Uint16 OPC31:1; // 31 OPC for Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANOPC_REG {
Uint32 all;
struct CANOPC_BITS bit;
};
/* eCAN TX I/O Control Register (CANTIOC) bit definitions */
struct CANTIOC_BITS { // bits description
Uint16 rsvd1:3; // 2:0 reserved
Uint16 TXFUNC:1; // 3 TXFUNC
Uint16 rsvd2:12; // 15:4 reserved
Uint16 rsvd3:16; // 31:16 reserved
};
/* Allow access to the bit fields or entire register */
union CANTIOC_REG {
Uint32 all;
struct CANTIOC_BITS bit;
};
/* eCAN RX I/O Control Register (CANRIOC) bit definitions */
struct CANRIOC_BITS { // bits description
Uint16 rsvd1:3; // 2:0 reserved
Uint16 RXFUNC:1; // 3 RXFUNC
Uint16 rsvd2:12; // 15:4 reserved
Uint16 rsvd3:16; // 31:16 reserved
};
/* Allow access to the bit fields or entire register */
union CANRIOC_REG {
Uint32 all;
struct CANRIOC_BITS bit;
};
/* eCAN Time-out Control register (CANTOC) bit definitions */
struct CANTOC_BITS { // bit description
Uint16 TOC0:1; // 0 TOC for Mailbox 0
Uint16 TOC1:1; // 1 TOC for Mailbox 1
Uint16 TOC2:1; // 2 TOC for Mailbox 2
Uint16 TOC3:1; // 3 TOC for Mailbox 3
Uint16 TOC4:1; // 4 TOC for Mailbox 4
Uint16 TOC5:1; // 5 TOC for Mailbox 5
Uint16 TOC6:1; // 6 TOC for Mailbox 6
Uint16 TOC7:1; // 7 TOC for Mailbox 7
Uint16 TOC8:1; // 8 TOC for Mailbox 8
Uint16 TOC9:1; // 9 TOC for Mailbox 9
Uint16 TOC10:1; // 10 TOC for Mailbox 10
Uint16 TOC11:1; // 11 TOC for Mailbox 11
Uint16 TOC12:1; // 12 TOC for Mailbox 12
Uint16 TOC13:1; // 13 TOC for Mailbox 13
Uint16 TOC14:1; // 14 TOC for Mailbox 14
Uint16 TOC15:1; // 15 TOC for Mailbox 15
Uint16 TOC16:1; // 16 TOC for Mailbox 16
Uint16 TOC17:1; // 17 TOC for Mailbox 17
Uint16 TOC18:1; // 18 TOC for Mailbox 18
Uint16 TOC19:1; // 19 TOC for Mailbox 19
Uint16 TOC20:1; // 20 TOC for Mailbox 20
Uint16 TOC21:1; // 21 TOC for Mailbox 21
Uint16 TOC22:1; // 22 TOC for Mailbox 22
Uint16 TOC23:1; // 23 TOC for Mailbox 23
Uint16 TOC24:1; // 24 TOC for Mailbox 24
Uint16 TOC25:1; // 25 TOC for Mailbox 25
Uint16 TOC26:1; // 26 TOC for Mailbox 26
Uint16 TOC27:1; // 27 TOC for Mailbox 27
Uint16 TOC28:1; // 28 TOC for Mailbox 28
Uint16 TOC29:1; // 29 TOC for Mailbox 29
Uint16 TOC30:1; // 30 TOC for Mailbox 30
Uint16 TOC31:1; // 31 TOC for Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANTOC_REG {
Uint32 all;
struct CANTOC_BITS bit;
};
/* eCAN Time-out Status register (CANTOS) bit definitions */
struct CANTOS_BITS { // bit description
Uint16 TOS0:1; // 0 TOS for Mailbox 0
Uint16 TOS1:1; // 1 TOS for Mailbox 1
Uint16 TOS2:1; // 2 TOS for Mailbox 2
Uint16 TOS3:1; // 3 TOS for Mailbox 3
Uint16 TOS4:1; // 4 TOS for Mailbox 4
Uint16 TOS5:1; // 5 TOS for Mailbox 5
Uint16 TOS6:1; // 6 TOS for Mailbox 6
Uint16 TOS7:1; // 7 TOS for Mailbox 7
Uint16 TOS8:1; // 8 TOS for Mailbox 8
Uint16 TOS9:1; // 9 TOS for Mailbox 9
Uint16 TOS10:1; // 10 TOS for Mailbox 10
Uint16 TOS11:1; // 11 TOS for Mailbox 11
Uint16 TOS12:1; // 12 TOS for Mailbox 12
Uint16 TOS13:1; // 13 TOS for Mailbox 13
Uint16 TOS14:1; // 14 TOS for Mailbox 14
Uint16 TOS15:1; // 15 TOS for Mailbox 15
Uint16 TOS16:1; // 16 TOS for Mailbox 16
Uint16 TOS17:1; // 17 TOS for Mailbox 17
Uint16 TOS18:1; // 18 TOS for Mailbox 18
Uint16 TOS19:1; // 19 TOS for Mailbox 19
Uint16 TOS20:1; // 20 TOS for Mailbox 20
Uint16 TOS21:1; // 21 TOS for Mailbox 21
Uint16 TOS22:1; // 22 TOS for Mailbox 22
Uint16 TOS23:1; // 23 TOS for Mailbox 23
Uint16 TOS24:1; // 24 TOS for Mailbox 24
Uint16 TOS25:1; // 25 TOS for Mailbox 25
Uint16 TOS26:1; // 26 TOS for Mailbox 26
Uint16 TOS27:1; // 27 TOS for Mailbox 27
Uint16 TOS28:1; // 28 TOS for Mailbox 28
Uint16 TOS29:1; // 29 TOS for Mailbox 29
Uint16 TOS30:1; // 30 TOS for Mailbox 30
Uint16 TOS31:1; // 31 TOS for Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANTOS_REG {
Uint32 all;
struct CANTOS_BITS bit;
};
/**************************************/
/* eCAN Control & Status register file */
/**************************************/
struct ECAN_REGS {
union CANME_REG CANME; // Mailbox Enable
union CANMD_REG CANMD; // Mailbox Direction
union CANTRS_REG CANTRS; // Transmit Request Set
union CANTRR_REG CANTRR; // Transmit Request Reset
union CANTA_REG CANTA; // Transmit Acknowledge
union CANAA_REG CANAA; // Abort Acknowledge
union CANRMP_REG CANRMP; // Received Message Pending
union CANRML_REG CANRML; // Received Message Lost
union CANRFP_REG CANRFP; // Remote Frame Pending
union CANGAM_REG CANGAM; // Global Acceptance Mask
union CANMC_REG CANMC; // Master Control
union CANBTC_REG CANBTC; // Bit Timing
union CANES_REG CANES; // Error Status
union CANTEC_REG CANTEC; // Transmit Error Counter
union CANREC_REG CANREC; // Receive Error Counter
union CANGIF0_REG CANGIF0; // Global Interrupt Flag 0
union CANGIM_REG CANGIM; // Global Interrupt Mask 0
union CANGIF1_REG CANGIF1; // Global Interrupt Flag 1
union CANMIM_REG CANMIM; // Mailbox Interrupt Mask
union CANMIL_REG CANMIL; // Mailbox Interrupt Level
union CANOPC_REG CANOPC; // Overwrite Protection Control
union CANTIOC_REG CANTIOC; // TX I/O Control
union CANRIOC_REG CANRIOC; // RX I/O Control
Uint32 CANTSC; // Time-stamp counter
union CANTOC_REG CANTOC; // Time-out Control
union CANTOS_REG CANTOS; // Time-out Status
};
/* --------------------------------------------------- */
/* eCAN Mailbox Registers */
/* ----------------------------------------------------*/
/* eCAN Message ID (MSGID) bit definitions */
struct CANMSGID_BITS { // bits description
Uint16 EXTMSGID_L:16; // 0:15
Uint16 EXTMSGID_H:2; // 16:17
Uint16 STDMSGID:11; // 18:28
Uint16 AAM:1; // 29
Uint16 AME:1; // 30
Uint16 IDE:1; // 31
};
/* Allow access to the bit fields or entire register */
union CANMSGID_REG {
Uint32 all;
struct CANMSGID_BITS bit;
};
/* eCAN Message Control Register (MSGCTRL) bit definitions */
struct CANMSGCTRL_BITS { // bits description
Uint16 DLC:4; // 0:3
Uint16 RTR:1; // 4
Uint16 rsvd1:3; // 7:5 reserved
Uint16 TPL:5; // 12:8
Uint16 rsvd2:3; // 15:13 reserved
Uint16 rsvd3:16; // 31:16 reserved
};
/* Allow access to the bit fields or entire register */
union CANMSGCTRL_REG {
Uint32 all;
struct CANMSGCTRL_BITS bit;
};
/* eCAN Message Data Register low (MDR_L) word definitions */
struct CANMDL_WORDS { // bits description
Uint16 LOW_WORD:16; // 0:15
Uint16 HI_WORD:16; // 31:16
};
/* eCAN Message Data Register low (MDR_L) byte definitions */
struct CANMDL_BYTES { // bits description
Uint16 BYTE3:8; // 31:24
Uint16 BYTE2:8; // 23:16
Uint16 BYTE1:8; // 15:8
Uint16 BYTE0:8; // 7:0
};
/* Allow access to the bit fields or entire register */
union CANMDL_REG {
Uint32 all;
struct CANMDL_WORDS word;
struct CANMDL_BYTES byte;
};
/* eCAN Message Data Register high (MDR_H) word definitions */
struct CANMDH_WORDS { // bits description
Uint16 LOW_WORD:16; // 0:15
Uint16 HI_WORD:16; // 31:16
};
/* eCAN Message Data Register low (MDR_H) byte definitions */
struct CANMDH_BYTES { // bits description
Uint16 BYTE7:8; // 63:56
Uint16 BYTE6:8; // 55:48
Uint16 BYTE5:8; // 47:40
Uint16 BYTE4:8; // 39:32
};
/* Allow access to the bit fields or entire register */
union CANMDH_REG {
Uint32 all;
struct CANMDH_WORDS word;
struct CANMDH_BYTES byte;
};
struct MBOX {
union CANMSGID_REG MSGID;
union CANMSGCTRL_REG MSGCTRL;
union CANMDL_REG MDL;
union CANMDH_REG MDH;
};
/**************************************/
/* eCAN Mailboxes */
/**************************************/
struct ECAN_MBOXES {
struct MBOX MBOX0;
struct MBOX MBOX1;
struct MBOX MBOX2;
struct MBOX MBOX3;
struct MBOX MBOX4;
struct MBOX MBOX5;
struct MBOX MBOX6;
struct MBOX MBOX7;
struct MBOX MBOX8;
struct MBOX MBOX9;
struct MBOX MBOX10;
struct MBOX MBOX11;
struct MBOX MBOX12;
struct MBOX MBOX13;
struct MBOX MBOX14;
struct MBOX MBOX15;
struct MBOX MBOX16;
struct MBOX MBOX17;
struct MBOX MBOX18;
struct MBOX MBOX19;
struct MBOX MBOX20;
struct MBOX MBOX21;
struct MBOX MBOX22;
struct MBOX MBOX23;
struct MBOX MBOX24;
struct MBOX MBOX25;
struct MBOX MBOX26;
struct MBOX MBOX27;
struct MBOX MBOX28;
struct MBOX MBOX29;
struct MBOX MBOX30;
struct MBOX MBOX31;
};
/* eCAN Local Acceptance Mask (LAM) bit definitions */
struct CANLAM_BITS { // bits description
Uint16 LAM_L:16; // 0:15
Uint16 LAM_H:13; // 16:28
Uint16 rsvd1:2; // 29:30 reserved
Uint16 LAMI:1; // 31
};
/* Allow access to the bit fields or entire register */
union CANLAM_REG {
Uint32 all;
struct CANLAM_BITS bit;
};
/**************************************/
/* eCAN Local Acceptance Masks */
/**************************************/
/* eCAN LAM File */
struct LAM_REGS {
union CANLAM_REG LAM0;
union CANLAM_REG LAM1;
union CANLAM_REG LAM2;
union CANLAM_REG LAM3;
union CANLAM_REG LAM4;
union CANLAM_REG LAM5;
union CANLAM_REG LAM6;
union CANLAM_REG LAM7;
union CANLAM_REG LAM8;
union CANLAM_REG LAM9;
union CANLAM_REG LAM10;
union CANLAM_REG LAM11;
union CANLAM_REG LAM12;
union CANLAM_REG LAM13;
union CANLAM_REG LAM14;
union CANLAM_REG LAM15;
union CANLAM_REG LAM16;
union CANLAM_REG LAM17;
union CANLAM_REG LAM18;
union CANLAM_REG LAM19;
union CANLAM_REG LAM20;
union CANLAM_REG LAM21;
union CANLAM_REG LAM22;
union CANLAM_REG LAM23;
union CANLAM_REG LAM24;
union CANLAM_REG LAM25;
union CANLAM_REG LAM26;
union CANLAM_REG LAM27;
union CANLAM_REG LAM28;
union CANLAM_REG LAM29;
union CANLAM_REG LAM30;
union CANLAM_REG LAM31;
};
/* Mailbox MOTS File */
struct MOTS_REGS {
Uint32 MOTS0;
Uint32 MOTS1;
Uint32 MOTS2;
Uint32 MOTS3;
Uint32 MOTS4;
Uint32 MOTS5;
Uint32 MOTS6;
Uint32 MOTS7;
Uint32 MOTS8;
Uint32 MOTS9;
Uint32 MOTS10;
Uint32 MOTS11;
Uint32 MOTS12;
Uint32 MOTS13;
Uint32 MOTS14;
Uint32 MOTS15;
Uint32 MOTS16;
Uint32 MOTS17;
Uint32 MOTS18;
Uint32 MOTS19;
Uint32 MOTS20;
Uint32 MOTS21;
Uint32 MOTS22;
Uint32 MOTS23;
Uint32 MOTS24;
Uint32 MOTS25;
Uint32 MOTS26;
Uint32 MOTS27;
Uint32 MOTS28;
Uint32 MOTS29;
Uint32 MOTS30;
Uint32 MOTS31;
};
/* Mailbox MOTO File */
struct MOTO_REGS {
Uint32 MOTO0;
Uint32 MOTO1;
Uint32 MOTO2;
Uint32 MOTO3;
Uint32 MOTO4;
Uint32 MOTO5;
Uint32 MOTO6;
Uint32 MOTO7;
Uint32 MOTO8;
Uint32 MOTO9;
Uint32 MOTO10;
Uint32 MOTO11;
Uint32 MOTO12;
Uint32 MOTO13;
Uint32 MOTO14;
Uint32 MOTO15;
Uint32 MOTO16;
Uint32 MOTO17;
Uint32 MOTO18;
Uint32 MOTO19;
Uint32 MOTO20;
Uint32 MOTO21;
Uint32 MOTO22;
Uint32 MOTO23;
Uint32 MOTO24;
Uint32 MOTO25;
Uint32 MOTO26;
Uint32 MOTO27;
Uint32 MOTO28;
Uint32 MOTO29;
Uint32 MOTO30;
Uint32 MOTO31;
};
//---------------------------------------------------------------------------
// eCAN External References & Function Declarations:
//
extern volatile struct ECAN_REGS ECanaRegs;
extern volatile struct ECAN_MBOXES ECanaMboxes;
extern volatile struct LAM_REGS ECanaLAMRegs;
extern volatile struct MOTO_REGS ECanaMOTORegs;
extern volatile struct MOTS_REGS ECanaMOTSRegs;
extern volatile struct ECAN_REGS ECanbRegs;
extern volatile struct ECAN_MBOXES ECanbMboxes;
extern volatile struct LAM_REGS ECanbLAMRegs;
extern volatile struct MOTO_REGS ECanbMOTORegs;
extern volatile struct MOTS_REGS ECanbMOTSRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_ECAN.H definition
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:52:07 $
//###########################################################################
//
// FILE: DSP2833x_ECap.h
//
// TITLE: DSP2833x Enhanced Capture Module Register Bit Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_ECAP_H
#define DSP2833x_ECAP_H
#ifdef __cplusplus
extern "C" {
#endif
//----------------------------------------------------
// Capture control register 1 bit definitions */
struct ECCTL1_BITS { // bits description
Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select
Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1
Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select
Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2
Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select
Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3
Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select
Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4
Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap Event
Uint16 PRESCALE:5; // 13:9 Event Filter prescale select
Uint16 FREE_SOFT:2; // 15:14 Emulation mode
};
union ECCTL1_REG {
Uint16 all;
struct ECCTL1_BITS bit;
};
// In V1.1 the STOPVALUE bit field was changed to
// STOP_WRAP. This correlated to a silicon change from
// F2833x Rev 0 to Rev A.
//----------------------------------------------------
// Capture control register 2 bit definitions */
struct ECCTL2_BITS { // bits description
Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot
Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous
Uint16 REARM:1; // 3 One-shot re-arm
Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop
Uint16 SYNCI_EN:1; // 5 Counter sync-in select
Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode
Uint16 SWSYNC:1; // 8 SW forced counter sync
Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select
Uint16 APWMPOL:1; // 10 APWM output polarity select
Uint16 rsvd1:5; // 15:11
};
union ECCTL2_REG {
Uint16 all;
struct ECCTL2_BITS bit;
};
//----------------------------------------------------
// ECAP interrupt enable register bit definitions */
struct ECEINT_BITS { // bits description
Uint16 rsvd1:1; // 0 reserved
Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable
Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable
Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable
Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable
Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable
Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable
Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable
Uint16 rsvd2:8; // 15:8 reserved
};
union ECEINT_REG {
Uint16 all;
struct ECEINT_BITS bit;
};
//----------------------------------------------------
// ECAP interrupt flag register bit definitions */
struct ECFLG_BITS { // bits description
Uint16 INT:1; // 0 Global Flag
Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag
Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag
Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag
Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag
Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag
Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Flag
Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Flag
Uint16 rsvd2:8; // 15:8 reserved
};
union ECFLG_REG {
Uint16 all;
struct ECFLG_BITS bit;
};
//----------------------------------------------------
struct ECAP_REGS {
Uint32 TSCTR; // Time stamp counter
Uint32 CTRPHS; // Counter phase
Uint32 CAP1; // Capture 1
Uint32 CAP2; // Capture 2
Uint32 CAP3; // Capture 3
Uint32 CAP4; // Capture 4
Uint16 rsvd1[8]; // reserved
union ECCTL1_REG ECCTL1; // Capture Control Reg 1
union ECCTL2_REG ECCTL2; // Capture Control Reg 2
union ECEINT_REG ECEINT; // ECAP interrupt enable
union ECFLG_REG ECFLG; // ECAP interrupt flags
union ECFLG_REG ECCLR; // ECAP interrupt clear
union ECEINT_REG ECFRC; // ECAP interrupt force
Uint16 rsvd2[6]; // reserved
};
//---------------------------------------------------------------------------
// GPI/O External References & Function Declarations:
//
extern volatile struct ECAP_REGS ECap1Regs;
extern volatile struct ECAP_REGS ECap2Regs;
extern volatile struct ECAP_REGS ECap3Regs;
extern volatile struct ECAP_REGS ECap4Regs;
extern volatile struct ECAP_REGS ECap5Regs;
extern volatile struct ECAP_REGS ECap6Regs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_ECAP_H definition
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:52:10 $
//###########################################################################
//
// FILE: DSP2833x_EPwm.h
//
// TITLE: DSP2833x Enhanced PWM Module Register Bit Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_EPWM_H
#define DSP2833x_EPWM_H
#ifdef __cplusplus
extern "C" {
#endif
//----------------------------------------------------
// Time base control register bit definitions */
struct TBCTL_BITS { // bits description
Uint16 CTRMODE:2; // 1:0 Counter Mode
Uint16 PHSEN:1; // 2 Phase load enable
Uint16 PRDLD:1; // 3 Active period load
Uint16 SYNCOSEL:2; // 5:4 Sync output select
Uint16 SWFSYNC:1; // 6 Software force sync pulse
Uint16 HSPCLKDIV:3; // 9:7 High speed time pre-scale
Uint16 CLKDIV:3; // 12:10 Timebase clock pre-scale
Uint16 PHSDIR:1; // 13 Phase Direction
Uint16 FREE_SOFT:2; // 15:14 Emulation mode
};
union TBCTL_REG {
Uint16 all;
struct TBCTL_BITS bit;
};
//----------------------------------------------------
// Time base status register bit definitions */
struct TBSTS_BITS { // bits description
Uint16 CTRDIR:1; // 0 Counter direction status
Uint16 SYNCI:1; // 1 External input sync status
Uint16 CTRMAX:1; // 2 Counter max latched status
Uint16 rsvd1:13; // 15:3 reserved
};
union TBSTS_REG {
Uint16 all;
struct TBSTS_BITS bit;
};
//----------------------------------------------------
// Compare control register bit definitions */
struct CMPCTL_BITS { // bits description
Uint16 LOADAMODE:2; // 0:1 Active compare A
Uint16 LOADBMODE:2; // 3:2 Active compare B
Uint16 SHDWAMODE:1; // 4 Compare A block operating mode
Uint16 rsvd1:1; // 5 reserved
Uint16 SHDWBMODE:1; // 6 Compare B block operating mode
Uint16 rsvd2:1; // 7 reserved
Uint16 SHDWAFULL:1; // 8 Compare A Shadow registers full Status
Uint16 SHDWBFULL:1; // 9 Compare B Shadow registers full Status
Uint16 rsvd3:6; // 15:10 reserved
};
union CMPCTL_REG {
Uint16 all;
struct CMPCTL_BITS bit;
};
//----------------------------------------------------
// Action qualifier register bit definitions */
struct AQCTL_BITS { // bits description
Uint16 ZRO:2; // 1:0 Action Counter = Zero
Uint16 PRD:2; // 3:2 Action Counter = Period
Uint16 CAU:2; // 5:4 Action Counter = Compare A up
Uint16 CAD:2; // 7:6 Action Counter = Compare A down
Uint16 CBU:2; // 9:8 Action Counter = Compare B up
Uint16 CBD:2; // 11:10 Action Counter = Compare B down
Uint16 rsvd:4; // 15:12 reserved
};
union AQCTL_REG {
Uint16 all;
struct AQCTL_BITS bit;
};
//----------------------------------------------------
// Action qualifier SW force register bit definitions */
struct AQSFRC_BITS { // bits description
Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A invoked
Uint16 OTSFA:1; // 2 One-time SW Force A output
Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B invoked
Uint16 OTSFB:1; // 5 One-time SW Force A output
Uint16 RLDCSF:2; // 7:6 Reload from Shadow options
Uint16 rsvd1:8; // 15:8 reserved
};
union AQSFRC_REG {
Uint16 all;
struct AQSFRC_BITS bit;
};
//----------------------------------------------------
// Action qualifier continuous SW force register bit definitions */
struct AQCSFRC_BITS { // bits description
Uint16 CSFA:2; // 1:0 Continuous Software Force on output A
Uint16 CSFB:2; // 3:2 Continuous Software Force on output B
Uint16 rsvd1:12; // 15:4 reserved
};
union AQCSFRC_REG {
Uint16 all;
struct AQCSFRC_BITS bit;
};
// As of version 1.1
// Changed the MODE bit-field to OUT_MODE
// Added the bit-field IN_MODE
// This corresponds to changes in silicon as of F2833x devices
// Rev A silicon.
//----------------------------------------------------
// Dead-band generator control register bit definitions
struct DBCTL_BITS { // bits description
Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control
Uint16 POLSEL:2; // 3:2 Polarity Select Control
Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control
Uint16 rsvd1:10; // 15:4 reserved
};
union DBCTL_REG {
Uint16 all;
struct DBCTL_BITS bit;
};
//----------------------------------------------------
// Trip zone select register bit definitions
struct TZSEL_BITS { // bits description
Uint16 CBC1:1; // 0 TZ1 CBC select
Uint16 CBC2:1; // 1 TZ2 CBC select
Uint16 CBC3:1; // 2 TZ3 CBC select
Uint16 CBC4:1; // 3 TZ4 CBC select
Uint16 CBC5:1; // 4 TZ5 CBC select
Uint16 CBC6:1; // 5 TZ6 CBC select
Uint16 rsvd1:2; // 7:6 reserved
Uint16 OSHT1:1; // 8 One-shot TZ1 select
Uint16 OSHT2:1; // 9 One-shot TZ2 select
Uint16 OSHT3:1; // 10 One-shot TZ3 select
Uint16 OSHT4:1; // 11 One-shot TZ4 select
Uint16 OSHT5:1; // 12 One-shot TZ5 select
Uint16 OSHT6:1; // 13 One-shot TZ6 select
Uint16 rsvd2:2; // 15:14 reserved
};
union TZSEL_REG {
Uint16 all;
struct TZSEL_BITS bit;
};
//----------------------------------------------------
// Trip zone control register bit definitions */
struct TZCTL_BITS { // bits description
Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA
Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB
Uint16 rsvd:12; // 15:4 reserved
};
union TZCTL_REG {
Uint16 all;
struct TZCTL_BITS bit;
};
//----------------------------------------------------
// Trip zone control register bit definitions */
struct TZEINT_BITS { // bits description
Uint16 rsvd1:1; // 0 reserved
Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable
Uint16 OST:1; // 2 Trip Zones One Shot Int Enable
Uint16 rsvd2:13; // 15:3 reserved
};
union TZEINT_REG {
Uint16 all;
struct TZEINT_BITS bit;
};
//----------------------------------------------------
// Trip zone flag register bit definitions */
struct TZFLG_BITS { // bits description
Uint16 INT:1; // 0 Global status
Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int
Uint16 OST:1; // 2 Trip Zones One Shot Int
Uint16 rsvd2:13; // 15:3 reserved
};
union TZFLG_REG {
Uint16 all;
struct TZFLG_BITS bit;
};
//----------------------------------------------------
// Trip zone flag clear register bit definitions */
struct TZCLR_BITS { // bits description
Uint16 INT:1; // 0 Global status
Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int
Uint16 OST:1; // 2 Trip Zones One Shot Int
Uint16 rsvd2:13; // 15:3 reserved
};
union TZCLR_REG {
Uint16 all;
struct TZCLR_BITS bit;
};
//----------------------------------------------------
// Trip zone flag force register bit definitions */
struct TZFRC_BITS { // bits description
Uint16 rsvd1:1; // 0 reserved
Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int
Uint16 OST:1; // 2 Trip Zones One Shot Int
Uint16 rsvd2:13; // 15:3 reserved
};
union TZFRC_REG {
Uint16 all;
struct TZFRC_BITS bit;
};
//----------------------------------------------------
// Event trigger select register bit definitions */
struct ETSEL_BITS { // bits description
Uint16 INTSEL:3; // 2:0 EPWMxINTn Select
Uint16 INTEN:1; // 3 EPWMxINTn Enable
Uint16 rsvd1:4; // 7:4 reserved
Uint16 SOCASEL:3; // 10:8 Start of conversion A Select
Uint16 SOCAEN:1; // 11 Start of conversion A Enable
Uint16 SOCBSEL:3; // 14:12 Start of conversion B Select
Uint16 SOCBEN:1; // 15 Start of conversion B Enable
};
union ETSEL_REG {
Uint16 all;
struct ETSEL_BITS bit;
};
//----------------------------------------------------
// Event trigger pre-scale register bit definitions */
struct ETPS_BITS { // bits description
Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select
Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register
Uint16 rsvd1:4; // 7:4 reserved
Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select
Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register
Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select
Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter Register
};
union ETPS_REG {
Uint16 all;
struct ETPS_BITS bit;
};
//----------------------------------------------------
// Event trigger Flag register bit definitions */
struct ETFLG_BITS { // bits description
Uint16 INT:1; // 0 EPWMxINTn Flag
Uint16 rsvd1:1; // 1 reserved
Uint16 SOCA:1; // 2 EPWMxSOCA Flag
Uint16 SOCB:1; // 3 EPWMxSOCB Flag
Uint16 rsvd2:12; // 15:4 reserved
};
union ETFLG_REG {
Uint16 all;
struct ETFLG_BITS bit;
};
//----------------------------------------------------
// Event trigger Clear register bit definitions */
struct ETCLR_BITS { // bits description
Uint16 INT:1; // 0 EPWMxINTn Clear
Uint16 rsvd1:1; // 1 reserved
Uint16 SOCA:1; // 2 EPWMxSOCA Clear
Uint16 SOCB:1; // 3 EPWMxSOCB Clear
Uint16 rsvd2:12; // 15:4 reserved
};
union ETCLR_REG {
Uint16 all;
struct ETCLR_BITS bit;
};
//----------------------------------------------------
// Event trigger Force register bit definitions */
struct ETFRC_BITS { // bits description
Uint16 INT:1; // 0 EPWMxINTn Force
Uint16 rsvd1:1; // 1 reserved
Uint16 SOCA:1; // 2 EPWMxSOCA Force
Uint16 SOCB:1; // 3 EPWMxSOCB Force
Uint16 rsvd2:12; // 15:4 reserved
};
union ETFRC_REG {
Uint16 all;
struct ETFRC_BITS bit;
};
//----------------------------------------------------
// PWM chopper control register bit definitions */
struct PCCTL_BITS { // bits description
Uint16 CHPEN:1; // 0 PWM chopping enable
Uint16 OSHTWTH:4; // 4:1 One-shot pulse width
Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency
Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle
Uint16 rsvd1:5; // 15:11 reserved
};
union PCCTL_REG {
Uint16 all;
struct PCCTL_BITS bit;
};
struct HRCNFG_BITS { // bits description
Uint16 EDGMODE:2; // 1:0 Edge Mode select Bits
Uint16 CTLMODE:1; // 2 Control mode Select Bit
Uint16 HRLOAD:1; // 3 Shadow mode Select Bit
Uint16 rsvd1:12; // 15:4 reserved
};
union HRCNFG_REG {
Uint16 all;
struct HRCNFG_BITS bit;
};
struct TBPHS_HRPWM_REG { // bits description
Uint16 TBPHSHR; // 15:0 Extension register for HRPWM Phase (8 bits)
Uint16 TBPHS; // 31:16 Phase offset register
};
union TBPHS_HRPWM_GROUP {
Uint32 all;
struct TBPHS_HRPWM_REG half;
};
struct CMPA_HRPWM_REG { // bits description
Uint16 CMPAHR; // 15:0 Extension register for HRPWM compare (8 bits)
Uint16 CMPA; // 31:16 Compare A reg
};
union CMPA_HRPWM_GROUP {
Uint32 all;
struct CMPA_HRPWM_REG half;
};
struct EPWM_REGS {
union TBCTL_REG TBCTL; //
union TBSTS_REG TBSTS; //
union TBPHS_HRPWM_GROUP TBPHS; // Union of TBPHS:TBPHSHR
Uint16 TBCTR; // Counter
Uint16 TBPRD; // Period register set
Uint16 rsvd1; //
union CMPCTL_REG CMPCTL; // Compare control
union CMPA_HRPWM_GROUP CMPA; // Union of CMPA:CMPAHR
Uint16 CMPB; // Compare B reg
union AQCTL_REG AQCTLA; // Action qual output A
union AQCTL_REG AQCTLB; // Action qual output B
union AQSFRC_REG AQSFRC; // Action qual SW force
union AQCSFRC_REG AQCSFRC; // Action qualifier continuous SW force
union DBCTL_REG DBCTL; // Dead-band control
Uint16 DBRED; // Dead-band rising edge delay
Uint16 DBFED; // Dead-band falling edge delay
union TZSEL_REG TZSEL; // Trip zone select
Uint16 rsvd2;
union TZCTL_REG TZCTL; // Trip zone control
union TZEINT_REG TZEINT; // Trip zone interrupt enable
union TZFLG_REG TZFLG; // Trip zone interrupt flags
union TZCLR_REG TZCLR; // Trip zone clear
union TZFRC_REG TZFRC; // Trip zone force interrupt
union ETSEL_REG ETSEL; // Event trigger selection
union ETPS_REG ETPS; // Event trigger pre-scaler
union ETFLG_REG ETFLG; // Event trigger flags
union ETCLR_REG ETCLR; // Event trigger clear
union ETFRC_REG ETFRC; // Event trigger force
union PCCTL_REG PCCTL; // PWM chopper control
Uint16 rsvd3; //
union HRCNFG_REG HRCNFG; // HRPWM Config Reg
};
//---------------------------------------------------------------------------
// External References & Function Declarations:
//
extern volatile struct EPWM_REGS EPwm1Regs;
extern volatile struct EPWM_REGS EPwm2Regs;
extern volatile struct EPWM_REGS EPwm3Regs;
extern volatile struct EPWM_REGS EPwm4Regs;
extern volatile struct EPWM_REGS EPwm5Regs;
extern volatile struct EPWM_REGS EPwm6Regs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_EPWM_H definition
//===========================================================================
// End of file.
//===========================================================================