From 88ddb37225caa9b58824404915bff1371720060d Mon Sep 17 00:00:00 2001 From: Dimas Date: Thu, 9 Jul 2026 14:44:12 +0300 Subject: [PATCH] =?UTF-8?q?=D0=BD=D0=B0=D1=87=D0=B0=D0=BB=D0=BE?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .gitignore | 8 + ADC.c | 253 ++++ ADC.h | 6 + aaa/gel/DSP2833x_DualMap_EPWM.gel | 237 ++++ bin/create_rs.bat | 5 + bios.c | 450 +++++++ bios_dsp.h | 120 ++ cntrl_adr.c | 43 + cntrl_adr.h | 44 + crc16.c | 221 ++++ crc16.h | 10 + create_rs.bat | 5 + .../include/DSP2833x_DefaultIsr.h | 147 +++ .../include/DSP2833x_Dma_defines.h | 81 ++ v120/DSP2833x_common/include/DSP28x_Project.h | 22 + .../source/DSP2833x_ADC_cal.asm | 42 + v120/DSP2833x_common/source/DSP2833x_Adc.c | 65 + .../source/DSP2833x_CpuTimers.c | 115 ++ v120/DSP2833x_headers/include/DSP2833x_Adc.h | 264 ++++ .../include/DSP2833x_CpuTimers.h | 190 +++ v120/DSP2833x_headers/include/DSP2833x_DMA.h | 295 +++++ .../include/DSP2833x_DevEmu.h | 97 ++ .../include/DSP2833x_Device.h | 368 ++++++ v120/DSP2833x_headers/include/DSP2833x_ECan.h | 1161 +++++++++++++++++ v120/DSP2833x_headers/include/DSP2833x_ECap.h | 151 +++ v120/DSP2833x_headers/include/DSP2833x_EPwm.h | 423 ++++++ 26 files changed, 4823 insertions(+) create mode 100644 .gitignore create mode 100644 ADC.c create mode 100644 ADC.h create mode 100644 aaa/gel/DSP2833x_DualMap_EPWM.gel create mode 100644 bin/create_rs.bat create mode 100644 bios.c create mode 100644 bios_dsp.h create mode 100644 cntrl_adr.c create mode 100644 cntrl_adr.h create mode 100644 crc16.c create mode 100644 crc16.h create mode 100644 create_rs.bat create mode 100644 v120/DSP2833x_common/include/DSP2833x_DefaultIsr.h create mode 100644 v120/DSP2833x_common/include/DSP2833x_Dma_defines.h create mode 100644 v120/DSP2833x_common/include/DSP28x_Project.h create mode 100644 v120/DSP2833x_common/source/DSP2833x_ADC_cal.asm create mode 100644 v120/DSP2833x_common/source/DSP2833x_Adc.c create mode 100644 v120/DSP2833x_common/source/DSP2833x_CpuTimers.c create mode 100644 v120/DSP2833x_headers/include/DSP2833x_Adc.h create mode 100644 v120/DSP2833x_headers/include/DSP2833x_CpuTimers.h create mode 100644 v120/DSP2833x_headers/include/DSP2833x_DMA.h create mode 100644 v120/DSP2833x_headers/include/DSP2833x_DevEmu.h create mode 100644 v120/DSP2833x_headers/include/DSP2833x_Device.h create mode 100644 v120/DSP2833x_headers/include/DSP2833x_ECan.h create mode 100644 v120/DSP2833x_headers/include/DSP2833x_ECap.h create mode 100644 v120/DSP2833x_headers/include/DSP2833x_EPwm.h diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..0f3491d --- /dev/null +++ b/.gitignore @@ -0,0 +1,8 @@ +/Debug/ +/ice.CS_/ +/Debug.lkf +/cc_build_Debug.log +/ice.map +/ice.paf2 +/ice.sbl + diff --git a/ADC.c b/ADC.c new file mode 100644 index 0000000..9ff05c0 --- /dev/null +++ b/ADC.c @@ -0,0 +1,253 @@ +#include "DSP2833x_Device.h" // DSP281x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP281x Examples Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" + +#include "ADC.h" + +#include "log_to_mem.h" +#include "RS485.h" +#include "filter_bat2.h" + +#include "measure.h" +#include "message.h" +#include "package.h" + +#include "peripher.h" + +#define SIZE_ADC_BUF 1000 +Uint16 ADC_table[24]; +Uint16 raw_table[24]; +Uint16 ConversionCount; + +int MAY=0; + +// Prototype statements for functions found within this file. +interrupt void adc_isr(void); + +void setup_adc() +{ + long CLKdiv,HSPCLKdiv,Rate; + + #if (CPU_FRQ_150MHZ) // Default - 150 MHz SYSCLKOUT + #define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25.0 MHz + #endif + #if (CPU_FRQ_100MHZ) + #define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2) = 25.0 MHz + #endif + +// Specific clock setting for this example: +// EALLOW; +// SysCtrlRegs.HISPCP.all = ADC_MODCLK; // HSPCLK = SYSCLKOUT/ADC_MODCLK +// EDIS; + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected register + PieVectTable.ADCINT = &adc_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + + InitAdc(); // For this example, init the ADC + +// Enable ADCINT in PIE + PieCtrlRegs.PIEIER1.bit.INTx6 = 1; + IER |= M_INT1; // Enable CPU Interrupt 1 +// EINT; // Enable Global interrupt INTM +// ERTM; // Enable Global realtime interrupt DBGM + +// Configure ADC + + if(Desk==dsk_COMM) + { + AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 0x000F; // Setup 2 conv's on SEQ1 + + + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0B; // Дальше температуры + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x0A; + AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x09; + AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x08; + AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x00; + AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x01; + AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x04; + AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x03; + AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0x05; + AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0x02; + AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0x06; + AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0x07; + + AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0x0F; // Токи-напражениа + AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0x0D; + AdcRegs.ADCCHSELSEQ4.bit.CONV14 = 0x0E; + AdcRegs.ADCCHSELSEQ4.bit.CONV15 = 0x0C; + + } + + if(Desk==dsk_SHKF) + { + AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 0x000E; // Setup 2 conv's on SEQ1 + + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x6; // 380В Ф1 + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x7; // 380В Ф2 + AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // 220В Ф1 + AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; // 220В Ф2 ? + AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x5; // 31В + AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x4; // 31В UC + AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0xF; // 24В ПМ + AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0xD; // +24В Дт + AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0xB; // -24В Дт + AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0x8; // 24В ПК + AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0xE; // 24В ПМУ + AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0xA; // 24В ПУ + AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0x9; // 15В Др + AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0x1; // ДТ° 1 + AdcRegs.ADCCHSELSEQ4.bit.CONV14 = 0x0; // ДТ° 2 + } + + AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1;// Enable SOCA from ePWM to start SEQ1 + AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1; // Enable SEQ1 interrupt (every EOS) + AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear INT SEQ1 bit + + AdcRegs.ADCTRL1.bit.SEQ_CASC = 1; // 1 Cascaded mode + +//AdcRegs.ADCTRL1.bit.ACQ_PS=15; +//AdcRegs.ADCTRL1.bit.CPS=1; + + AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; // Reset SEQ1 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE + +// Assumes ePWM1 clock is already enabled in InitSysCtrl(); + EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group + EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC from from CPMA on upcount + EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event + EPwm1Regs.CMPA.half.CMPA = 0x0080; // Set compare A value + + EPwm1Regs.TBCTL.bit.HSPCLKDIV = CLKMULT; + EPwm1Regs.TBCTL.bit.CLKDIV=2; + + CLKdiv = 1<>4; + + if((sens_type[i]==POWER_380)||(sens_type[i]==POWER_220)) + { + if(Numb>200/*150*/) + { + if(prenumb[i]==0) zero_cownt[i]=0; + zero_cownt[i]+=2; + filtar[i] += ((float)Numb-filtar[i])/100.0; + Numb = filtar[i]; + prenumb[i]=1; + } + else + { + prenumb[i]=0; + if(zero_cownt[i]) + { + zero_cownt[i]--; + continue; + } + } + } + + raw_table[i] = Numb; Temper = Numb; + ADC_table[i] = filterbat(&filter[i],Temper); + + if(sens_type[i]==TERMO_AD) Temper_count(i); + else Power_count(i); + } + sig.all = chk.all; + chk.all = 0; + + if(/*Modbus[127].bit.bitE*/0) + { + Test_mem_limit(16); + for(i=0;i<8;i++) + { + Log_to_mem(raw_table[i]); + Log_to_mem(ADC_table[i]); + } } } +/* + if(Mode==adr_SHKF) + { + for(i=0;i<15;i++) + { + Temper= *((&AdcRegs.ADCRESULT0)+i) >>4; + adc_table_lem[i]=filterbat(&filter[i],Temper); + adc_table_tpl[i]=adc_table_lem[i]; + } + adc_table_lem[15] = ExtraCanal1; + adc_table_lem[16] = ExtraCanal2; + + measure_all(); + } +*/ + if(Desk==dsk_COMM) + { + for(i=0;i<24;i++) + if(sens_type[i]) + { + Temper = *((&AdcRegs.ADCRESULT0)+i) >>4; + + if(sens_type[i] != VOLTAGE) + Temper = filterbat(&filter[i],Temper); + + ADC_table[i]=(int)Temper; + + if(sens_type[i]==VOLTAGE) Current_count(i); + else Temper_count(i); + } + + sig.all = chk.all; + chk.all = 0; + } } + +// Reinitialize for next ADC sequence + AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; // Reset SEQ1 + AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear INT SEQ1 bit + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE + +// Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + return; +} diff --git a/ADC.h b/ADC.h new file mode 100644 index 0000000..7d2de8f --- /dev/null +++ b/ADC.h @@ -0,0 +1,6 @@ +extern int MAY; + +extern Uint16 ADC_table[]; + + +void setup_adc(void); diff --git a/aaa/gel/DSP2833x_DualMap_EPWM.gel b/aaa/gel/DSP2833x_DualMap_EPWM.gel new file mode 100644 index 0000000..e08455b --- /dev/null +++ b/aaa/gel/DSP2833x_DualMap_EPWM.gel @@ -0,0 +1,237 @@ +/* +/* TI File $Revision: /main/1 $ */ +/* Checkin $Date: May 7, 2008 13:07:07 $ */ +/***********************************************************************/ +/* File: DSP2833x_DualMap_EPWM.gel +/* +/* Description: +/* Adds dual-mapped EPWM registers to the GEL menu in +/* Code Composer Studio and allows user to enable dual-mapping of +/* EPWM registers to Peripheral Frame 3 (DMA-accessible) register +/* space +//##################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//##################################################################### +*/ + +/********************************************************************/ +/* Dual-Mapped Enhanced PWM Registers */ +/********************************************************************/ + +/* Add a space line to the GEL menu */ +menuitem "___________________________________"; +hotmenu ___() {} + +menuitem "Dual-Mapped ePWM Registers"; +hotmenu Enable_ePWM_Dual_Mapping () +{ + *0x702E = (*0x702E) | 0x0001; /* MAPCNF[MAPEPWM] = 1 */ +} +hotmenu ePWM1_DualMapped_All_Regs() +{ + GEL_WatchAdd("*0x5800,x","ePWM1 TBCTL"); + GEL_WatchAdd("*0x5801,x","ePWM1 TBSTS"); + GEL_WatchAdd("*0x5802,x","ePWM1 TBPHSHR"); + GEL_WatchAdd("*0x5803,x","ePWM1 TBPHS"); + GEL_WatchAdd("*0x5804,x","ePWM1 TBCTR"); + GEL_WatchAdd("*0x5805,x","ePWM1 TBPRD"); + GEL_WatchAdd("*0x5807,x","ePWM1 CMPCTL"); + GEL_WatchAdd("*0x5808,x","ePWM1 CMPAHR"); + GEL_WatchAdd("*0x5809,x","ePWM1 CMPA"); + GEL_WatchAdd("*0x580A,x","ePWM1 CMPB"); + GEL_WatchAdd("*0x580B,x","ePWM1 AQCTLA"); + GEL_WatchAdd("*0x580C,x","ePWM1 AQCTLB"); + GEL_WatchAdd("*0x580D,x","ePWM1 AQSFRC"); + GEL_WatchAdd("*0x580E,x","ePWM1 AQCSFRC"); + GEL_WatchAdd("*0x580F,x","ePWM1 DBCTL"); + GEL_WatchAdd("*0x5810,x","ePWM1 DBRED"); + GEL_WatchAdd("*0x5811,x","ePWM1 DBFED"); + GEL_WatchAdd("*0x5812,x","ePWM1 TZSEL"); + GEL_WatchAdd("*0x5813,x","ePWM1 TZDCSEL"); + GEL_WatchAdd("*0x5814,x","ePWM1 TZCTL"); + GEL_WatchAdd("*0x5815,x","ePWM1 TZEINT"); + GEL_WatchAdd("*0x5816,x","ePWM1 TZFLG"); + GEL_WatchAdd("*0x5817,x","ePWM1 TZCLR"); + GEL_WatchAdd("*0x5818,x","ePWM1 TZFRC"); + GEL_WatchAdd("*0x5819,x","ePWM1 ETSEL"); + GEL_WatchAdd("*0x581A,x","ePWM1 ETPS"); + GEL_WatchAdd("*0x581B,x","ePWM1 ETFLG"); + GEL_WatchAdd("*0x581C,x","ePWM1 ETCLR"); + GEL_WatchAdd("*0x581D,x","ePWM1 ETFRC"); + GEL_WatchAdd("*0x581E,x","ePWM1 PCCTL"); + GEL_WatchAdd("*0x5820,x","ePWM1 HRCNFG"); +} + +hotmenu ePWM2_DualMapped_All_Regs() +{ + GEL_WatchAdd("*0x5840,x","ePWM2 TBCTL"); + GEL_WatchAdd("*0x5841,x","ePWM2 TBSTS"); + GEL_WatchAdd("*0x5842,x","ePWM2 TBPHSHR"); + GEL_WatchAdd("*0x5843,x","ePWM2 TBPHS"); + GEL_WatchAdd("*0x5844,x","ePWM2 TBCTR"); + GEL_WatchAdd("*0x5845,x","ePWM2 TBPRD"); + GEL_WatchAdd("*0x5847,x","ePWM2 CMPCTL"); + GEL_WatchAdd("*0x5848,x","ePWM2 CMPAHR"); + GEL_WatchAdd("*0x5849,x","ePWM2 CMPA"); + GEL_WatchAdd("*0x584A,x","ePWM2 CMPB"); + GEL_WatchAdd("*0x584B,x","ePWM2 AQCTLA"); + GEL_WatchAdd("*0x584C,x","ePWM2 AQCTLB"); + GEL_WatchAdd("*0x584D,x","ePWM2 AQSFRC"); + GEL_WatchAdd("*0x584E,x","ePWM2 AQCSFRC"); + GEL_WatchAdd("*0x584F,x","ePWM2 DBCTL"); + GEL_WatchAdd("*0x5850,x","ePWM2 DBRED"); + GEL_WatchAdd("*0x5851,x","ePWM2 DBFED"); + GEL_WatchAdd("*0x5852,x","ePWM2 TZSEL"); + GEL_WatchAdd("*0x5853,x","ePWM2 TZDCSEL"); + GEL_WatchAdd("*0x5854,x","ePWM2 TZCTL"); + GEL_WatchAdd("*0x5855,x","ePWM2 TZEINT"); + GEL_WatchAdd("*0x5856,x","ePWM2 TZFLG"); + GEL_WatchAdd("*0x5857,x","ePWM2 TZCLR"); + GEL_WatchAdd("*0x5858,x","ePWM2 TZFRC"); + GEL_WatchAdd("*0x5859,x","ePWM2 ETSEL"); + GEL_WatchAdd("*0x585A,x","ePWM2 ETPS"); + GEL_WatchAdd("*0x585B,x","ePWM2 ETFLG"); + GEL_WatchAdd("*0x585C,x","ePWM2 ETCLR"); + GEL_WatchAdd("*0x585D,x","ePWM2 ETFRC"); + GEL_WatchAdd("*0x585E,x","ePWM2 PCCTL"); + GEL_WatchAdd("*0x5860,x","ePWM2 HRCNFG"); +} +hotmenu ePWM3_DualMapped_All_Regs() +{ + GEL_WatchAdd("*0x5880,x","ePWM3 TBCTL"); + GEL_WatchAdd("*0x5881,x","ePWM3 TBSTS"); + GEL_WatchAdd("*0x5882,x","ePWM3 TBPHSHR"); + GEL_WatchAdd("*0x5883,x","ePWM3 TBPHS"); + GEL_WatchAdd("*0x5884,x","ePWM3 TBCTR"); + GEL_WatchAdd("*0x5885,x","ePWM3 TBPRD"); + GEL_WatchAdd("*0x5887,x","ePWM3 CMPCTL"); + GEL_WatchAdd("*0x5888,x","ePWM3 CMPAHR"); + GEL_WatchAdd("*0x5889,x","ePWM3 CMPA"); + GEL_WatchAdd("*0x588A,x","ePWM3 CMPB"); + GEL_WatchAdd("*0x588B,x","ePWM3 AQCTLA"); + GEL_WatchAdd("*0x588C,x","ePWM3 AQCTLB"); + GEL_WatchAdd("*0x588D,x","ePWM3 AQSFRC"); + GEL_WatchAdd("*0x588E,x","ePWM3 AQCSFRC"); + GEL_WatchAdd("*0x588F,x","ePWM3 DBCTL"); + GEL_WatchAdd("*0x5890,x","ePWM3 DBRED"); + GEL_WatchAdd("*0x5891,x","ePWM3 DBFED"); + GEL_WatchAdd("*0x5892,x","ePWM3 TZSEL"); + GEL_WatchAdd("*0x5893,x","ePWM3 TZDCSEL"); + GEL_WatchAdd("*0x5894,x","ePWM3 TZCTL"); + GEL_WatchAdd("*0x5895,x","ePWM3 TZEINT"); + GEL_WatchAdd("*0x5896,x","ePWM3 TZFLG"); + GEL_WatchAdd("*0x5897,x","ePWM3 TZCLR"); + GEL_WatchAdd("*0x5898,x","ePWM3 TZFRC"); + GEL_WatchAdd("*0x5899,x","ePWM3 ETSEL"); + GEL_WatchAdd("*0x589A,x","ePWM3 ETPS"); + GEL_WatchAdd("*0x589B,x","ePWM3 ETFLG"); + GEL_WatchAdd("*0x589C,x","ePWM3 ETCLR"); + GEL_WatchAdd("*0x589D,x","ePWM3 ETFRC"); + GEL_WatchAdd("*0x589E,x","ePWM3 PCCTL"); + GEL_WatchAdd("*0x58A0,x","ePWM3 HRCNFG"); +} +hotmenu ePWM4_DualMapped_All_Regs() +{ + GEL_WatchAdd("*0x58C0,x","ePWM4 TBCTL"); + GEL_WatchAdd("*0x58C1,x","ePWM4 TBSTS"); + GEL_WatchAdd("*0x58C2,x","ePWM4 TBPHSHR"); + GEL_WatchAdd("*0x58C3,x","ePWM4 TBPHS"); + GEL_WatchAdd("*0x58C4,x","ePWM4 TBCTR"); + GEL_WatchAdd("*0x58C5,x","ePWM4 TBPRD"); + GEL_WatchAdd("*0x58C7,x","ePWM4 CMPCTL"); + GEL_WatchAdd("*0x58C8,x","ePWM4 CMPAHR"); + GEL_WatchAdd("*0x58C9,x","ePWM4 CMPA"); + GEL_WatchAdd("*0x58CA,x","ePWM4 CMPB"); + GEL_WatchAdd("*0x58CB,x","ePWM4 AQCTLA"); + GEL_WatchAdd("*0x58CC,x","ePWM4 AQCTLB"); + GEL_WatchAdd("*0x58CD,x","ePWM4 AQSFRC"); + GEL_WatchAdd("*0x58CE,x","ePWM4 AQCSFRC"); + GEL_WatchAdd("*0x58CF,x","ePWM4 DBCTL"); + GEL_WatchAdd("*0x58D0,x","ePWM4 DBRED"); + GEL_WatchAdd("*0x58D1,x","ePWM4 DBFED"); + GEL_WatchAdd("*0x58D2,x","ePWM4 TZSEL"); + GEL_WatchAdd("*0x58D3,x","ePWM4 TZDCSEL"); + GEL_WatchAdd("*0x58D4,x","ePWM4 TZCTL"); + GEL_WatchAdd("*0x58D5,x","ePWM4 TZEINT"); + GEL_WatchAdd("*0x58D6,x","ePWM4 TZFLG"); + GEL_WatchAdd("*0x58D7,x","ePWM4 TZCLR"); + GEL_WatchAdd("*0x58D8,x","ePWM4 TZFRC"); + GEL_WatchAdd("*0x58D9,x","ePWM4 ETSEL"); + GEL_WatchAdd("*0x58DA,x","ePWM4 ETPS"); + GEL_WatchAdd("*0x58DB,x","ePWM4 ETFLG"); + GEL_WatchAdd("*0x58DC,x","ePWM4 ETCLR"); + GEL_WatchAdd("*0x58DD,x","ePWM4 ETFRC"); + GEL_WatchAdd("*0x58DE,x","ePWM4 PCCTL"); + GEL_WatchAdd("*0x58E0,x","ePWM4 HRCNFG"); +} +hotmenu ePWM5_DualMapped_All_Regs() +{ + GEL_WatchAdd("*0x5900,x","ePWM5 TBCTL"); + GEL_WatchAdd("*0x5901,x","ePWM5 TBSTS"); + GEL_WatchAdd("*0x5902,x","ePWM5 TBPHSHR"); + GEL_WatchAdd("*0x5903,x","ePWM5 TBPHS"); + GEL_WatchAdd("*0x5904,x","ePWM5 TBCTR"); + GEL_WatchAdd("*0x5905,x","ePWM5 TBPRD"); + GEL_WatchAdd("*0x5907,x","ePWM5 CMPCTL"); + GEL_WatchAdd("*0x5908,x","ePWM5 CMPAHR"); + GEL_WatchAdd("*0x5909,x","ePWM5 CMPA"); + GEL_WatchAdd("*0x590A,x","ePWM5 CMPB"); + GEL_WatchAdd("*0x590B,x","ePWM5 AQCTLA"); + GEL_WatchAdd("*0x590C,x","ePWM5 AQCTLB"); + GEL_WatchAdd("*0x590D,x","ePWM5 AQSFRC"); + GEL_WatchAdd("*0x590E,x","ePWM5 AQCSFRC"); + GEL_WatchAdd("*0x590F,x","ePWM5 DBCTL"); + GEL_WatchAdd("*0x5910,x","ePWM5 DBRED"); + GEL_WatchAdd("*0x5911,x","ePWM5 DBFED"); + GEL_WatchAdd("*0x5912,x","ePWM5 TZSEL"); + GEL_WatchAdd("*0x5913,x","ePWM5 TZDCSEL"); + GEL_WatchAdd("*0x5914,x","ePWM5 TZCTL"); + GEL_WatchAdd("*0x5915,x","ePWM5 TZEINT"); + GEL_WatchAdd("*0x5916,x","ePWM5 TZFLG"); + GEL_WatchAdd("*0x5917,x","ePWM5 TZCLR"); + GEL_WatchAdd("*0x5918,x","ePWM5 TZFRC"); + GEL_WatchAdd("*0x5919,x","ePWM5 ETSEL"); + GEL_WatchAdd("*0x591A,x","ePWM5 ETPS"); + GEL_WatchAdd("*0x591B,x","ePWM5 ETFLG"); + GEL_WatchAdd("*0x591C,x","ePWM5 ETCLR"); + GEL_WatchAdd("*0x591D,x","ePWM5 ETFRC"); + GEL_WatchAdd("*0x591E,x","ePWM5 PCCTL"); + GEL_WatchAdd("*0x5920,x","ePWM5 HRCNFG"); +} +hotmenu ePWM6_DualMapped_All_Regs() +{ + GEL_WatchAdd("*0x5940,x","ePWM6 TBCTL"); + GEL_WatchAdd("*0x5941,x","ePWM6 TBSTS"); + GEL_WatchAdd("*0x5942,x","ePWM6 TBPHSHR"); + GEL_WatchAdd("*0x5943,x","ePWM6 TBPHS"); + GEL_WatchAdd("*0x5944,x","ePWM6 TBCTR"); + GEL_WatchAdd("*0x5945,x","ePWM6 TBPRD"); + GEL_WatchAdd("*0x5947,x","ePWM6 CMPCTL"); + GEL_WatchAdd("*0x5948,x","ePWM6 CMPAHR"); + GEL_WatchAdd("*0x5949,x","ePWM6 CMPA"); + GEL_WatchAdd("*0x594A,x","ePWM6 CMPB"); + GEL_WatchAdd("*0x594B,x","ePWM6 AQCTLA"); + GEL_WatchAdd("*0x594C,x","ePWM6 AQCTLB"); + GEL_WatchAdd("*0x594D,x","ePWM6 AQSFRC"); + GEL_WatchAdd("*0x594E,x","ePWM6 AQCSFRC"); + GEL_WatchAdd("*0x594F,x","ePWM6 DBCTL"); + GEL_WatchAdd("*0x5950,x","ePWM6 DBRED"); + GEL_WatchAdd("*0x5951,x","ePWM6 DBFED"); + GEL_WatchAdd("*0x5952,x","ePWM6 TZSEL"); + GEL_WatchAdd("*0x5953,x","ePWM6 TZDCSEL"); + GEL_WatchAdd("*0x5954,x","ePWM6 TZCTL"); + GEL_WatchAdd("*0x5955,x","ePWM6 TZEINT"); + GEL_WatchAdd("*0x5956,x","ePWM6 TZFLG"); + GEL_WatchAdd("*0x5957,x","ePWM6 TZCLR"); + GEL_WatchAdd("*0x5958,x","ePWM6 TZFRC"); + GEL_WatchAdd("*0x5959,x","ePWM6 ETSEL"); + GEL_WatchAdd("*0x595A,x","ePWM6 ETPS"); + GEL_WatchAdd("*0x595B,x","ePWM6 ETFLG"); + GEL_WatchAdd("*0x595C,x","ePWM6 ETCLR"); + GEL_WatchAdd("*0x595D,x","ePWM6 ETFRC"); + GEL_WatchAdd("*0x595E,x","ePWM6 PCCTL"); + GEL_WatchAdd("*0x5960,x","ePWM6 HRCNFG"); + +} + diff --git a/bin/create_rs.bat b/bin/create_rs.bat new file mode 100644 index 0000000..98959b3 --- /dev/null +++ b/bin/create_rs.bat @@ -0,0 +1,5 @@ +set iname=BalzamUMPLeonardTMS320F28335 +set oname=BalzamUMPLeonardTMS320F28335 + +hex2000 %iname%.out -boot -sci8 -map %iname%.map -o %oname%.hex -i +hex2bin %oname%.hex %oname%.bin diff --git a/bios.c b/bios.c new file mode 100644 index 0000000..42ffb72 --- /dev/null +++ b/bios.c @@ -0,0 +1,450 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, КЛАИН, КЛВСП ====== */ +/* ЦНИИ СЭТ (с) 1998-2000 г. */ +/**************************************************************** + Bios.c + ************************************************************** + Основные комманды BIOS * + дла работы с RS232 +****************************************************************/ +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "RS485.h" +#include "bios_dsp.h" +#include "crc16.h" +#include "spise2p.h" +#include "i2c.h" + +//#include "flash_tools.h" +//#include "spartan_tools.h" +//#include "big_dsp_module.h" + +int flag_DEBUG = false; /* Флаг отладочного режима */ + + +//static unsigned int *RecvPtr; +//static int BS_LoadOK = false; /** Флаг успешности приема блока */ + +/**********************************************************/ +/* Прототипы функций, используемых и определенных в файле */ +/**********************************************************/ +//static int _getbyte(int *addr, int offs); + +unsigned int read_memory(unsigned long addr) +{ + return (*(volatile int *)(addr)); +} + +void write_memory(unsigned long addr, unsigned int data) +{ + (*(volatile int *)( addr )) = data; +} + + +/** Возвращает номер комманды, если есть или -1 если транзакций не было */ +int get_command(RS_DATA *rs_arr) +{ + int cmd; + unsigned int crc, rcrc; + + if(rs_arr->RS_DataReady) // Данные по RS пришли + { + rs_arr->RS_DataReady = false; + cmd = rs_arr->RS_Header[1]; // Прочитали номер команды + + // Провераем длину команды дла считываниа CRC + if((RS_Len[cmd]<3) || (RS_Len[cmd]>MAX_RECEIVE_LENGTH)) + { + RS_Line_to_receive(rs_arr); // режим приема RS485 + RS_SetBitMode(rs_arr,9); + return -1; + } + + if(cmd == CMD_LOAD) // Если команда загрузки + { + rs_arr->RS_PrevCmd = cmd; + return cmd; // Нет проверки crc + } + else // Все остальные команды + { + // Считываем crc из посылки + crc = (rs_arr->RS_Header[RS_Len[cmd]-1] << 8) | + (rs_arr->RS_Header[RS_Len[cmd]-2]) ; + } + // Рассчитываем crc из посылки + rcrc = 0xffff; + rcrc = get_crc_16( rcrc, rs_arr->RS_Header, (RS_Len[cmd]-2) ); + + if(crc == rcrc) // Провераем crc + { + rs_arr->RS_PrevCmd = cmd; + return cmd; + } + else + { + RS_Line_to_receive(rs_arr); // режим приема RS485 + RS_SetBitMode(rs_arr,9); + } } + + return -1; +} + +/** Стандартный ответ, без параметров */ +void Answer(RS_DATA *rs_arr,int n) +{ + int crc; + + flag_DEBUG = true; // Флаг отладочного режима + + rs_arr->buffer[0] = rs_arr->addr_recive; //CNTRL_ADDR; + rs_arr->buffer[1] = n; + + crc = 0xffff; + crc = get_crc_16( crc, rs_arr->buffer, 2); + + rs_arr->buffer[2] = LOBYTE(crc); + rs_arr->buffer[3] = HIBYTE(crc); + + rs_arr->buffer[4] = 0; + rs_arr->buffer[5] = 0; + RS_Send(rs_arr,rs_arr->buffer, 6); +} + +/* Внутреннаа ф-циа */ +static char _getbyte(unsigned int *addr, int32 offs) +{ + unsigned int *address; + unsigned int byte; + + address = addr + offs/2; + byte = *address; + if(offs%2) return LOBYTE(byte); + else return HIBYTE(byte); +} + + +/* начальные установки (не работает)*/ +void init(RS_DATA *rs_arr) +{ +/* + if(rs_arr->RS_Header[2]==3) + { + if (rs_arr->curr_baud!=57600) + { RS_SetLineSpeed(rs_arr,57600); + rs_arr->curr_baud= 57600; + } } + + if(rs_arr->RS_Header[2]==4) + { + if (rs_arr->curr_baud!=115200) + { RS_SetLineSpeed(rs_arr,115200); + rs_arr->curr_baud= 115200; + } } + + Answer(rs_arr,CMD_INIT); + rs_arr->BS_LoadOK = false; +*/ +} + +/**@name Комманды +* Комманды, вызываемые через последовательный канал +*/ +//@{ + +/** Инициировать загрузку блока. + Настраивает прием блока данных */ +void initload(RS_DATA *rs_arr) +{ + unsigned long Address; + + Address = rs_arr->RS_Header[5] & 0xFF; + Address = (Address<<8) | (rs_arr->RS_Header[4] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[3] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[2] & 0xFF); + + rs_arr->RS_Length = rs_arr->RS_Header[9] & 0xFF; + rs_arr->RS_Length = (rs_arr->RS_Length<<8) | (rs_arr->RS_Header[8] & 0xFF); + rs_arr->RS_Length = (rs_arr->RS_Length<<8) | (rs_arr->RS_Header[7] & 0xFF); + rs_arr->RS_Length = (rs_arr->RS_Length<<8) | (rs_arr->RS_Header[6] & 0xFF); + + rs_arr->RS_Length += 2; + rs_arr->pRS_RecvPtr = (unsigned int *)Address; //(unsigned int *)Address; + rs_arr->pRecvPtr = (unsigned int *)Address; //(unsigned int *)Address; + + Answer(rs_arr,CMD_INITLOAD); +} + +/** Загрузка блока. + Вызываетса после загрузки блока через RS */ +void load(RS_DATA *rs_arr) +{ + unsigned int rcrc, crc; + + crc = (_getbyte(rs_arr->pRecvPtr, rs_arr->RS_Length-1) << 8) + + _getbyte(rs_arr->pRecvPtr, rs_arr->RS_Length-2); + + rs_arr->RS_Header[0] = rs_arr->addr_recive; + +// CNTRL_ADDR; + rs_arr->RS_Header[1]=CMD_LOAD; + + rcrc = 0xffff; + rcrc = get_crc_16( rcrc, rs_arr->RS_Header, 2); + rcrc = get_crc_16b( rcrc, rs_arr->pRecvPtr, rs_arr->RS_Length-2); + + if(rcrc == crc) + { + Answer(rs_arr,CMD_LOAD); + rs_arr->BS_LoadOK = true; + } + else + { + rs_arr->BS_LoadOK = false; + RS_Line_to_receive(rs_arr); // режим приема RS485 + RS_SetBitMode(rs_arr,9); +} } + +/** Выполнить программу в формате Serial Boot. + @precondition Должна быть произведена загрузка блока + Адрес программы беретса из заголовка и + сравниваетса с переменной RecvPtr, заполнаемой в ф-ции load + @see load */ +void run (RS_DATA *rs_arr) +{ + return; +} + +/** Прочитать ачейку памати */ +void peek(RS_DATA *rs_arr) +{ + unsigned long Address; + unsigned int Data, crc; + + flag_DEBUG = true; // Флаг отладочного режима + + Address = rs_arr->RS_Header[5] & 0xFF; + Address = (Address<<8) | (rs_arr->RS_Header[4] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[3] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[2] & 0xFF); + + + if(Address>=0x20000000) + { + Address&=0xFFFFFFF; + Data = I2CA_ReadData(Address); + } + else + if(Address>=0x10000000) + { + Address&=0xFFFFFFF; + Seeprom_read(Address,(unsigned int *)&Data,2); + } + else + { + Address&=0xFFFFFFF; + Data = read_memory(Address); + } + + rs_arr->buffer[0] = rs_arr->addr_recive; //CNTRL_ADDR; + rs_arr->buffer[1] = CMD_PEEK; + + rs_arr->buffer[2] = LOBYTE(Data); + rs_arr->buffer[3] = HIBYTE(Data); + + rs_arr->buffer[4] = 0;//LOBYTE(CpuTimer2.InterruptCount); + rs_arr->buffer[5] = 0;//HIBYTE(CpuTimer2.InterruptCount); + + crc = 0xffff; + crc = get_crc_16(crc, rs_arr->buffer, 6); + + rs_arr->buffer[6] = LOBYTE(crc); + rs_arr->buffer[7] = HIBYTE(crc); + rs_arr->buffer[8] = 0; + rs_arr->buffer[9] = 0; + + RS_Send(rs_arr,rs_arr->buffer, 10); + +} + +/** Записать в ачейку памати */ +void poke(RS_DATA *rs_arr) +{ + unsigned long Address; + unsigned int Data; + + Address = rs_arr->RS_Header[5] & 0xFF; + Address = (Address<<8) | (rs_arr->RS_Header[4] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[3] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[2] & 0xFF); + + Data = 0; + Data = (Data<<8) | (rs_arr->RS_Header[7] & 0xFF); + Data = (Data<<8) | (rs_arr->RS_Header[6] & 0xFF); + + if(Address>=0x2000000) + { + Address&=0xFFFFFF; + I2CA_WriteData(Address,Data); + } + else + if(Address>=0x1000000) + { + Address&=0xFFFFFF; + Seeprom_write(Address,(unsigned int *)&Data,2); + } + else + { + Address&=0xFFFFFF; + write_memory(Address,Data); + } + + Answer(rs_arr,CMD_POKE); +} + +/** Передать блок памати */ +void upload(RS_DATA *rs_arr) +{ + int32 Address, Length, crc; + + flag_DEBUG = true; // Флаг отладочного режима +// stopp=1; + + Address = rs_arr->RS_Header[5] & 0xFF; + Address = (Address<<8) | (rs_arr->RS_Header[4] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[3] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[2] & 0xFF); + + Length = rs_arr->RS_Header[9] & 0xFF; + Length = (Length<<8) | (rs_arr->RS_Header[8] & 0xFF); + Length = (Length<<8) | (rs_arr->RS_Header[7] & 0xFF); + Length = (Length<<8) | (rs_arr->RS_Header[6] & 0xFF); + + rs_arr->buffer[0] = rs_arr->addr_recive; //CNTRL_ADDR; + rs_arr->buffer[1] = CMD_UPLOAD; + + crc = 0xffff; + crc = get_crc_16( crc, rs_arr->buffer, 2); + crc = get_crc_16b( crc, (unsigned int *)Address, Length); + + RS_Send(rs_arr,rs_arr->buffer, 1); // <=2 байт по флагу + + rs_arr->buffer[0] = CMD_UPLOAD; + RS_Send(rs_arr,rs_arr->buffer, 1); // <=2 байт по флагу + + RS_Wait4OK(rs_arr); + RS_BSend(rs_arr,(unsigned int*)Address, Length); + RS_Wait4OK(rs_arr); + + rs_arr->buffer[0] = LOBYTE(crc); + rs_arr->buffer[1] = HIBYTE(crc); + rs_arr->buffer[2] = 0; + rs_arr->buffer[3] = 0; + RS_Send(rs_arr,rs_arr->buffer, 4+2); + +} + +/** Прошить XILINX. + @precondition Должна быть произведена загрузка блока + Адрес и длина прошивки беретса из заголовка и + сравниваетса с переменными RecvPtr и Length, заполнаемыми в ф-ции load, + так же смотрит магическое слово в начале прошивки + @see load */ +void xflash(RS_DATA *rs_arr) +{ + return; +} + +/** Прошить TMS. + @precondition Должна быть произведена загрузка блока + Адрес и длина прошивки беретса из заголовка и + сравниваетса с переменными RecvPtr и Length, заполнаемыми в ф-ции load + @see load */ +void tflash(RS_DATA *rs_arr) +{ +// volatile unsigned long Address1,Address2; +// volatile unsigned long Length, LengthW; +/* + if(!rs_arr->BS_LoadOK) + { + RS_Line_to_receive(rs_arr); // режим приема RS485 + RS_SetBitMode(rs_arr,9); + return; + } + + Address1 = rs_arr->RS_Header[5] & 0xFF; + Address1 = (Address1<<8) | (rs_arr->RS_Header[4] & 0xFF); + Address1 = (Address1<<8) | (rs_arr->RS_Header[3] & 0xFF); + Address1 = (Address1<<8) | (rs_arr->RS_Header[2] & 0xFF); + + Address2 = rs_arr->RS_Header[9] & 0xFF; + Address2 = (Address2<<8) | (rs_arr->RS_Header[8] & 0xFF); + Address2 = (Address2<<8) | (rs_arr->RS_Header[7] & 0xFF); + Address2 = (Address2<<8) | (rs_arr->RS_Header[6] & 0xFF); + + Length = rs_arr->RS_Header[13] & 0xFF; + Length = (Length<<8) | (rs_arr->RS_Header[12] & 0xFF); + Length = (Length<<8) | (rs_arr->RS_Header[11] & 0xFF); + Length = (Length<<8) | (rs_arr->RS_Header[10] & 0xFF); + + LengthW = Length/2; + if (LengthW*2 0x180000) || ((Address2+LengthW) > 0x180000) ) + { + RS_Line_to_receive(rs_arr); // режим приема RS485 + RS_SetBitMode(rs_arr,9); + return; + } + + run_flash_data(Address1,Address2, LengthW ); + + Answer(rs_arr,CMD_TFLASH); +*/ + return; +} + +/** Прошить TMS. + @precondition Должна быть произведена загрузка блока + Адрес и длина прошивки беретса из заголовка и + сравниваетса с переменными RecvPtr и Length, заполнаемыми в ф-ции load + @see load */ +void extendbios(RS_DATA *rs_arr) +{ + volatile unsigned long Address1,Address2,Length; + unsigned int code; + + Address1 = rs_arr->RS_Header[5] & 0xFF; + Address1 = (Address1<<8) | (rs_arr->RS_Header[4] & 0xFF); + Address1 = (Address1<<8) | (rs_arr->RS_Header[3] & 0xFF); + Address1 = (Address1<<8) | (rs_arr->RS_Header[2] & 0xFF); + + Address2 = rs_arr->RS_Header[9] & 0xFF; + Address2 = (Address2<<8) | (rs_arr->RS_Header[8] & 0xFF); + Address2 = (Address2<<8) | (rs_arr->RS_Header[7] & 0xFF); + Address2 = (Address2<<8) | (rs_arr->RS_Header[6] & 0xFF); + + Length = rs_arr->RS_Header[13] & 0xFF; + Length = (Length<<8) | (rs_arr->RS_Header[12] & 0xFF); + Length = (Length<<8) | (rs_arr->RS_Header[11] & 0xFF); + Length = (Length<<8) | (rs_arr->RS_Header[10] & 0xFF); + + code=rs_arr->RS_Header[14] & 0xFF; + + switch ( code ) + { + // Прошиваем EPROM Из RAM + case 4: Seeprom_write(Address1,(unsigned int*)Address2,Length); + break; + // Читаем из EPROM в RAM + case 5: Seeprom_read(Address1,(unsigned int*)Address2,Length); + break; + + default: + return; + } + + Answer(rs_arr,CMD_EXTEND); + return; +} + +//@} diff --git a/bios_dsp.h b/bios_dsp.h new file mode 100644 index 0000000..9ed9601 --- /dev/null +++ b/bios_dsp.h @@ -0,0 +1,120 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, КЛАИН, КЛВСП ====== */ +/* ЦНИИ СЭТ (с) 1998-2000 г. */ +/****************************************************************/ +/* Bios_dsp.h */ +/****************************************************************/ + /* Основные комманды BIOS */ +/****************************************************************/ +#ifndef _BIOS_DSP +#define _BIOS_DSP + +#ifdef __cplusplus + extern "C" { +#endif + +#define BM_PACKED 1 +#define BM_CHAR32 0 + +#define CHIEF 1 +#define SLAVE 0 + +#define ADR_FOR_SPECIAL 0x100 +#define CMD_MODBUS_3 3 +#define ANS_MODBUS_3 4 +#define CMD_MODBUS_15 5 +#define CMD_MODBUS_6 6 +#define ANS_MODBUS_6 7 +#define CMD_MODBUS_16 16 +/* + +CMD_MODBUS_3 = 3, + ANS_MODBUS_3 = 4, + CMD_MODBUS_15 = 5, + CMD_MODBUS_6 = 6, + ANS_MODBUS_6 = 7, + CMD_MODBUS_16 = 16, + */ +enum { + CMD_LOAD=51, CMD_UPLOAD, CMD_RUN, CMD_XFLASH, CMD_TFLASH, + CMD_PEEK, CMD_POKE, CMD_INITLOAD, CMD_INIT,CMD_EXTEND, + + CMD_VECTOR=61, + CMD_IMPULSE, + /* стандартные команды */ + CMD_STD=65, CMD_STD_ANS + }; + +enum {false=0, true}; + + +/** Возвращает номер комманды, если есть или -1 если транзакций не было */ +int get_command(RS_DATA *rs_arr); + +/** Стандартный ответ, без параметров */ +void Answer(RS_DATA *rs_arr,int n); + +/* начальные установки (не работает)*/ +void init(RS_DATA *rs_arr); + +/**@name Комманды +* Комманды, вызываемые через последовательный канал*/ +//@{ + +/** Инициировать загрузку блока. + Настраивает прием блока данных */ +void initload(RS_DATA *rs_arr); + +/** Загрузка блока. + Вызываетса после загрузки блока через RS */ +void load(RS_DATA *rs_arr); + +/** Выполнить программу в формате Serial Boot. + @precondition Должна быть произведена загрузка блока + Адрес программы беретса из заголовка и + сравниваетса с переменной RecvPtr, заполнаемой в ф-ции load + @see load */ +void run (RS_DATA *rs_arr); + +/** Прочитать ачейку памати */ +void peek(RS_DATA *rs_arr); + +/** Записать в ачейку памати */ +void poke(RS_DATA *rs_arr); + +/** Передать блок памати */ +void upload(RS_DATA *rs_arr); + +/** Прошить XILINX. + @precondition Должна быть произведена загрузка блока + Адрес и длина прошивки беретса из заголовка и + сравниваетса с переменными RecvPtr и Length, заполнаемыми в ф-ции load, + так же смотрит магическое слово в начале прошивки + @see load */ +void xflash(RS_DATA *rs_arr); + +/** Прошить TMS. + @precondition Должна быть произведена загрузка блока + Адрес и длина прошивки беретса из заголовка и + сравниваетса с переменными RecvPtr и Length, заполнаемыми в ф-ции load + @see load */ +void tflash(RS_DATA *rs_arr); + + +/* расширенные команды дла биоса */ +void extendbios(RS_DATA *rs_arr); + + +void write_memory(unsigned long addr, unsigned int data); +unsigned int read_memory(unsigned long addr); + + +//@} + + +#ifdef __cplusplus + } +#endif + +#endif/* _BIOS_DSP */ diff --git a/cntrl_adr.c b/cntrl_adr.c new file mode 100644 index 0000000..2f29cdb --- /dev/null +++ b/cntrl_adr.c @@ -0,0 +1,43 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, КЛАИН, КЛВСП ====== */ +/* ЦНИИ СЭТ (с) 1998-2000 г. */ +/**************************************************************** + cntrl_adr.c + **************************************************************** + * Адрес контроллера * + ****************************************************************/ + +#include "cntrl_adr.h" + +#define ADDR_FOR_ALL_DEF 10 +#define ADDR_ANSWER_DEF 0x33 +#define ADDR_TERMINAL_DEF 11 +#define ADDR_UNIVERSAL_DEF 10 + + +/** Установка адреса контроллера дла посылки всем АИНам */ +int ADDR_FOR_ALL = ADDR_FOR_ALL_DEF; + +/** Установка адреса контроллера дла посылки ответа */ +const int ADDR_ANSWER = ADDR_ANSWER_DEF; + +/** Установка адреса терминала дла посылки ответа */ +const int ADDR_TERMINAL = ADDR_TERMINAL_DEF; + +/* Универсальный адрес контроллера */ +const int CNTRL_ADDR_UNIVERSAL=ADDR_UNIVERSAL_DEF; + +/* Адрес контроллера */ +int CNTRL_ADDR=1; + +int cntr_addr_c; +int cntr_addr_c_all; + +/** Установка адреса контроллера дла прошивки */ +void set_cntrl_addr (int cntrl_addr,int cntrl_addr_for_all) +{ + CNTRL_ADDR = cntrl_addr; + ADDR_FOR_ALL = cntrl_addr_for_all; +} + diff --git a/cntrl_adr.h b/cntrl_adr.h new file mode 100644 index 0000000..100021f --- /dev/null +++ b/cntrl_adr.h @@ -0,0 +1,44 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, КЛАИН, КЛВСП ====== */ +/* ЦНИИ СЭТ (с) 1998-2000 г. */ +/**************************************************************** + cntrl_adr.h + **************************************************************** + * Адрес контроллера * + ****************************************************************/ + +#ifndef _CNTRL_ADR +#define _CNTRL_ADR + +#ifdef __cplusplus + extern "C" { +#endif + +/** адрес контроллера дла посылки всем АИНам */ +extern int ADDR_FOR_ALL; + +/** адрес контроллера дла посылки ответа */ +extern const int ADDR_ANSWER; + +/** адреса терминала дла посылки ответа */ +extern const int ADDR_TERMINAL; + +/* Адрес контроллера */ +extern int CNTRL_ADDR; + +/* Универсальный адрес контроллера */ +extern const int CNTRL_ADDR_UNIVERSAL; + +/** Установка адреса контроллера дла прошивки */ +void set_cntrl_addr (int cntrl_addr,int cntrl_addr_for_all); + + +extern int cntr_addr_c; +extern int cntr_addr_c_all; + +#ifdef __cplusplus + } +#endif + +#endif /* _CNTRL_ADR */ diff --git a/crc16.c b/crc16.c new file mode 100644 index 0000000..9fd6869 --- /dev/null +++ b/crc16.c @@ -0,0 +1,221 @@ +#include "crc16.h" +#define MAKE_TABS 0 /* Builds tables below */ +#define FAST_CRC 1 /* If fast CRC should be used */ +#define ONLY_CRC16 1 + +#define Poln 0xA001 + + +#if FAST_CRC & !MAKE_TABS + +#if !ONLY_CRC16 + +static WORD crc_ccitt_tab[] = { + 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, + 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, + 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, + 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, + 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, + 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, + 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, + 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, + 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, + 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, + 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, + 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, + 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, + 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, + 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, + 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, + 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, + 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, + 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, + 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, + 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, + 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, + 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, + 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, + 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, + 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, + 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, + 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, + 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, + 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, + 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, + 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0 +}; +#endif + +WORD crc_16_tab[] = { + 0x0000, 0xc0c1, 0xc181, 0x0140, 0xc301, 0x03c0, 0x0280, 0xc241, + 0xc601, 0x06c0, 0x0780, 0xc741, 0x0500, 0xc5c1, 0xc481, 0x0440, + 0xcc01, 0x0cc0, 0x0d80, 0xcd41, 0x0f00, 0xcfc1, 0xce81, 0x0e40, + 0x0a00, 0xcac1, 0xcb81, 0x0b40, 0xc901, 0x09c0, 0x0880, 0xc841, + 0xd801, 0x18c0, 0x1980, 0xd941, 0x1b00, 0xdbc1, 0xda81, 0x1a40, + 0x1e00, 0xdec1, 0xdf81, 0x1f40, 0xdd01, 0x1dc0, 0x1c80, 0xdc41, + 0x1400, 0xd4c1, 0xd581, 0x1540, 0xd701, 0x17c0, 0x1680, 0xd641, + 0xd201, 0x12c0, 0x1380, 0xd341, 0x1100, 0xd1c1, 0xd081, 0x1040, + 0xf001, 0x30c0, 0x3180, 0xf141, 0x3300, 0xf3c1, 0xf281, 0x3240, + 0x3600, 0xf6c1, 0xf781, 0x3740, 0xf501, 0x35c0, 0x3480, 0xf441, + 0x3c00, 0xfcc1, 0xfd81, 0x3d40, 0xff01, 0x3fc0, 0x3e80, 0xfe41, + 0xfa01, 0x3ac0, 0x3b80, 0xfb41, 0x3900, 0xf9c1, 0xf881, 0x3840, + 0x2800, 0xe8c1, 0xe981, 0x2940, 0xeb01, 0x2bc0, 0x2a80, 0xea41, + 0xee01, 0x2ec0, 0x2f80, 0xef41, 0x2d00, 0xedc1, 0xec81, 0x2c40, + 0xe401, 0x24c0, 0x2580, 0xe541, 0x2700, 0xe7c1, 0xe681, 0x2640, + 0x2200, 0xe2c1, 0xe381, 0x2340, 0xe101, 0x21c0, 0x2080, 0xe041, + 0xa001, 0x60c0, 0x6180, 0xa141, 0x6300, 0xa3c1, 0xa281, 0x6240, + 0x6600, 0xa6c1, 0xa781, 0x6740, 0xa501, 0x65c0, 0x6480, 0xa441, + 0x6c00, 0xacc1, 0xad81, 0x6d40, 0xaf01, 0x6fc0, 0x6e80, 0xae41, + 0xaa01, 0x6ac0, 0x6b80, 0xab41, 0x6900, 0xa9c1, 0xa881, 0x6840, + 0x7800, 0xb8c1, 0xb981, 0x7940, 0xbb01, 0x7bc0, 0x7a80, 0xba41, + 0xbe01, 0x7ec0, 0x7f80, 0xbf41, 0x7d00, 0xbdc1, 0xbc81, 0x7c40, + 0xb401, 0x74c0, 0x7580, 0xb541, 0x7700, 0xb7c1, 0xb681, 0x7640, + 0x7200, 0xb2c1, 0xb381, 0x7340, 0xb101, 0x71c0, 0x7080, 0xb041, + 0x5000, 0x90c1, 0x9181, 0x5140, 0x9301, 0x53c0, 0x5280, 0x9241, + 0x9601, 0x56c0, 0x5780, 0x9741, 0x5500, 0x95c1, 0x9481, 0x5440, + 0x9c01, 0x5cc0, 0x5d80, 0x9d41, 0x5f00, 0x9fc1, 0x9e81, 0x5e40, + 0x5a00, 0x9ac1, 0x9b81, 0x5b40, 0x9901, 0x59c0, 0x5880, 0x9841, + 0x8801, 0x48c0, 0x4980, 0x8941, 0x4b00, 0x8bc1, 0x8a81, 0x4a40, + 0x4e00, 0x8ec1, 0x8f81, 0x4f40, 0x8d01, 0x4dc0, 0x4c80, 0x8c41, + 0x4400, 0x84c1, 0x8581, 0x4540, 0x8701, 0x47c0, 0x4680, 0x8641, + 0x8201, 0x42c0, 0x4380, 0x8341, 0x4100, 0x81c1, 0x8081, 0x4040 +}; +#endif + + +#if !ONLY_CRC16 + +/* CRC-CCITT is based on the polynomial x^16 + x^12 + x^5 + 1. Bits */ +/* are sent MSB to LSB. */ +unsigned int get_crc_ccitt(unsigned int crc,unsigned int *buf,unsigned long size ) +{ +#if !(FAST_CRC & !MAKE_TABS) + register int i; +#endif + + while (size--) { +#if FAST_CRC & !MAKE_TABS + crc = (crc << 8) ^ crc_ccitt_tab[ (crc >> 8) ^ *buf++ ]; +#else + crc ^= (WORD)(*buf++) << 8; + for (i = 0; i < 8; i++) { + if (crc & 0x8000) + crc = (crc << 1) ^ 0x1021; + else + crc <<= 1; + } +#endif + } return crc; +} +#endif + + +/* CRC-16 is based on the polynomial x^16 + x^15 + x^2 + 1. Bits are */ +/* sent LSB to MSB. */ +unsigned int get_crc_16(unsigned int crc,unsigned int *buf,unsigned long size ) +{ +#if !(FAST_CRC & !MAKE_TABS) + register unsigned int i; + register unsigned int ch; +#endif + + while (size--) { +#if FAST_CRC & !MAKE_TABS + + crc = (crc >> 8) ^ crc_16_tab[ (crc ^ *buf++) & 0xff ]; + crc = crc & 0xffff; +#else + ch = *buf++; + for (i = 0; i < 8; i++) { + if ((crc ^ ch) & 1) + crc = (crc >> 1) ^ 0xa001; + else + crc >>= 1; + ch >>= 1; + } +#endif + } return (crc & 0xffff); +} + + + +unsigned int get_crc_16b(unsigned int crc,unsigned int *buf,unsigned long size ) +{ + +unsigned int x, dword, byte; +unsigned long i; + + + + for (i = 0; i < size; i++) + { + x = i % 2; + + dword = buf[i/2]; +// dword = *buf; + + + if (x == 0) + { + byte = ((dword >> 8)&0xFF); + } + + if (x == 1) + { + byte = (dword & 0xFF); + } + + crc = (crc >> 8) ^ crc_16_tab[ (crc ^ (byte) ) & 0xff ]; + crc = crc & 0xffff; + +// crc = crc + ((byte) & 0xff); + + } + + return (crc & 0xffff); +} + +int get_crc16(unsigned int *buf, int size ) +{ + unsigned int crc16,i,j; + + + crc16=0xFFFF; + for(i=0;i>1)^Poln; + else crc16=crc16>>1; + + crc16=crc16^((buf[i]>>8)&0xFF); + for (j=0;j<8;j++) + if(crc16&1) crc16=(crc16>>1)^Poln; + else crc16=crc16>>1; + } + return crc16; +} + +unsigned int get_crc32(unsigned long *num) +{ + int i; + volatile unsigned long crc32,key, num_vol; + num_vol = *num; + + + crc32 = 0xFF000000 | (num_vol >> 8); + + for(i=0;i<32;i++) + { + key = crc32 & 0x80000000; + if(key) key = 0x31000000; // 00110001 + + crc32 = (crc32<<1) ^key; + } + + crc32 = ((crc32 >> 24) & 0x000000FF) | (num_vol & 0xFFFFFF00); + + if (crc32 == num_vol) return 1; + return 0; +} + diff --git a/crc16.h b/crc16.h new file mode 100644 index 0000000..148c7d6 --- /dev/null +++ b/crc16.h @@ -0,0 +1,10 @@ +typedef unsigned short WORD; +typedef unsigned char byte; + + +unsigned int get_crc_ccitt(unsigned int crc, unsigned int *buf, unsigned long size ); +unsigned int get_crc_16(unsigned int crc,unsigned int *buf,unsigned long size ); +unsigned int get_crc_16b(unsigned int crc,unsigned int *buf,unsigned long size ); +int get_crc16(unsigned int *buf, int size ); + +unsigned int get_crc32(unsigned long *num); diff --git a/create_rs.bat b/create_rs.bat new file mode 100644 index 0000000..eaa0571 --- /dev/null +++ b/create_rs.bat @@ -0,0 +1,5 @@ +set iname=debug\lampa +set oname=bin\lampa + +d:\CCStudio_v3.3\C2000\cgtools\bin\hex2000 %iname%.out -boot -sci8 -map %iname%.map -o %oname%.hex -i +d:\CCStudio_v3.3\C2000\cgtools\bin\hex2bin %oname%.hex %oname%.bin diff --git a/v120/DSP2833x_common/include/DSP2833x_DefaultIsr.h b/v120/DSP2833x_common/include/DSP2833x_DefaultIsr.h new file mode 100644 index 0000000..8919b97 --- /dev/null +++ b/v120/DSP2833x_common/include/DSP2833x_DefaultIsr.h @@ -0,0 +1,147 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:37 $ +//########################################################################### +// +// FILE: DSP2833x_DefaultIsr.h +// +// TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_DEFAULT_ISR_H +#define DSP2833x_DEFAULT_ISR_H + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// Default Interrupt Service Routine Declarations: +// +// The following function prototypes are for the +// default ISR routines used with the default PIE vector table. +// This default vector table is found in the DSP2833x_PieVect.h +// file. +// + +// Non-Peripheral Interrupts: +interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1 +interrupt void INT14_ISR(void); // CPU-Timer2 +interrupt void DATALOG_ISR(void); // Datalogging interrupt +interrupt void RTOSINT_ISR(void); // RTOS interrupt +interrupt void EMUINT_ISR(void); // Emulation interrupt +interrupt void NMI_ISR(void); // Non-maskable interrupt +interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP +interrupt void USER1_ISR(void); // User Defined trap 1 +interrupt void USER2_ISR(void); // User Defined trap 2 +interrupt void USER3_ISR(void); // User Defined trap 3 +interrupt void USER4_ISR(void); // User Defined trap 4 +interrupt void USER5_ISR(void); // User Defined trap 5 +interrupt void USER6_ISR(void); // User Defined trap 6 +interrupt void USER7_ISR(void); // User Defined trap 7 +interrupt void USER8_ISR(void); // User Defined trap 8 +interrupt void USER9_ISR(void); // User Defined trap 9 +interrupt void USER10_ISR(void); // User Defined trap 10 +interrupt void USER11_ISR(void); // User Defined trap 11 +interrupt void USER12_ISR(void); // User Defined trap 12 + +// Group 1 PIE Interrupt Service Routines: +interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR +interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR +interrupt void XINT1_ISR(void); // External interrupt 1 +interrupt void XINT2_ISR(void); // External interrupt 2 +interrupt void ADCINT_ISR(void); // ADC +interrupt void TINT0_ISR(void); // Timer 0 +interrupt void WAKEINT_ISR(void); // WD + +// Group 2 PIE Interrupt Service Routines: +interrupt void EPWM1_TZINT_ISR(void); // EPWM-1 +interrupt void EPWM2_TZINT_ISR(void); // EPWM-2 +interrupt void EPWM3_TZINT_ISR(void); // EPWM-3 +interrupt void EPWM4_TZINT_ISR(void); // EPWM-4 +interrupt void EPWM5_TZINT_ISR(void); // EPWM-5 +interrupt void EPWM6_TZINT_ISR(void); // EPWM-6 + +// Group 3 PIE Interrupt Service Routines: +interrupt void EPWM1_INT_ISR(void); // EPWM-1 +interrupt void EPWM2_INT_ISR(void); // EPWM-2 +interrupt void EPWM3_INT_ISR(void); // EPWM-3 +interrupt void EPWM4_INT_ISR(void); // EPWM-4 +interrupt void EPWM5_INT_ISR(void); // EPWM-5 +interrupt void EPWM6_INT_ISR(void); // EPWM-6 + +// Group 4 PIE Interrupt Service Routines: +interrupt void ECAP1_INT_ISR(void); // ECAP-1 +interrupt void ECAP2_INT_ISR(void); // ECAP-2 +interrupt void ECAP3_INT_ISR(void); // ECAP-3 +interrupt void ECAP4_INT_ISR(void); // ECAP-4 +interrupt void ECAP5_INT_ISR(void); // ECAP-5 +interrupt void ECAP6_INT_ISR(void); // ECAP-6 + +// Group 5 PIE Interrupt Service Routines: +interrupt void EQEP1_INT_ISR(void); // EQEP-1 +interrupt void EQEP2_INT_ISR(void); // EQEP-2 + +// Group 6 PIE Interrupt Service Routines: +interrupt void SPIRXINTA_ISR(void); // SPI-A +interrupt void SPITXINTA_ISR(void); // SPI-A +interrupt void MRINTA_ISR(void); // McBSP-A +interrupt void MXINTA_ISR(void); // McBSP-A +interrupt void MRINTB_ISR(void); // McBSP-B +interrupt void MXINTB_ISR(void); // McBSP-B + +// Group 7 PIE Interrupt Service Routines: +interrupt void DINTCH1_ISR(void); // DMA-Channel 1 +interrupt void DINTCH2_ISR(void); // DMA-Channel 2 +interrupt void DINTCH3_ISR(void); // DMA-Channel 3 +interrupt void DINTCH4_ISR(void); // DMA-Channel 4 +interrupt void DINTCH5_ISR(void); // DMA-Channel 5 +interrupt void DINTCH6_ISR(void); // DMA-Channel 6 + +// Group 8 PIE Interrupt Service Routines: +interrupt void I2CINT1A_ISR(void); // I2C-A +interrupt void I2CINT2A_ISR(void); // I2C-A +interrupt void SCIRXINTC_ISR(void); // SCI-C +interrupt void SCITXINTC_ISR(void); // SCI-C + +// Group 9 PIE Interrupt Service Routines: +interrupt void SCIRXINTA_ISR(void); // SCI-A +interrupt void SCITXINTA_ISR(void); // SCI-A +interrupt void SCIRXINTB_ISR(void); // SCI-B +interrupt void SCITXINTB_ISR(void); // SCI-B +interrupt void ECAN0INTA_ISR(void); // eCAN-A +interrupt void ECAN1INTA_ISR(void); // eCAN-A +interrupt void ECAN0INTB_ISR(void); // eCAN-B +interrupt void ECAN1INTB_ISR(void); // eCAN-B + +// Group 10 PIE Interrupt Service Routines: + +// Group 11 PIE Interrupt Service Routines: + +// Group 12 PIE Interrupt Service Routines: +interrupt void XINT3_ISR(void); // External interrupt 3 +interrupt void XINT4_ISR(void); // External interrupt 4 +interrupt void XINT5_ISR(void); // External interrupt 5 +interrupt void XINT6_ISR(void); // External interrupt 6 +interrupt void XINT7_ISR(void); // External interrupt 7 +interrupt void LVF_ISR(void); // Latched overflow flag +interrupt void LUF_ISR(void); // Latched underflow flag + +// Catch-all for Reserved Locations For testing purposes: +interrupt void PIE_RESERVED(void); // Reserved for test +interrupt void rsvd_ISR(void); // for test +interrupt void INT_NOTUSED_ISR(void); // for unused interrupts + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEFAULT_ISR_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/include/DSP2833x_Dma_defines.h b/v120/DSP2833x_common/include/DSP2833x_Dma_defines.h new file mode 100644 index 0000000..7b8dfaf --- /dev/null +++ b/v120/DSP2833x_common/include/DSP2833x_Dma_defines.h @@ -0,0 +1,81 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: August 14, 2007 16:32:29 $ +//########################################################################### +// +// FILE: DSP2833x_Dma_defines.h +// +// TITLE: #defines used in DMA examples +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_DMA_DEFINES_H +#define DSP2833x_DMA_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// MODE +//========================== +// PERINTSEL bits +#define DMA_SEQ1INT 1 +#define DMA_SEQ2INT 2 +#define DMA_XINT1 3 +#define DMA_XINT2 4 +#define DMA_XINT3 5 +#define DMA_XINT4 6 +#define DMA_XINT5 7 +#define DMA_XINT6 8 +#define DMA_XINT7 9 +#define DMA_XINT13 10 +#define DMA_TINT0 11 +#define DMA_TINT1 12 +#define DMA_TINT2 13 +#define DMA_MXEVTA 14 +#define DMA_MREVTA 15 +#define DMA_MXREVTB 16 +#define DMA_MREVTB 17 +// OVERINTE bit +#define OVRFLOW_DISABLE 0x0 +#define OVEFLOW_ENABLE 0x1 +// PERINTE bit +#define PERINT_DISABLE 0x0 +#define PERINT_ENABLE 0x1 +// CHINTMODE bits +#define CHINT_BEGIN 0x0 +#define CHINT_END 0x1 +// ONESHOT bits +#define ONESHOT_DISABLE 0x0 +#define ONESHOT_ENABLE 0x1 +// CONTINOUS bit +#define CONT_DISABLE 0x0 +#define CONT_ENABLE 0x1 +// SYNCE bit +#define SYNC_DISABLE 0x0 +#define SYNC_ENABLE 0x1 +// SYNCSEL bit +#define SYNC_SRC 0x0 +#define SYNC_DST 0x1 +// DATASIZE bit +#define SIXTEEN_BIT 0x0 +#define THIRTYTWO_BIT 0x1 +// CHINTE bit +#define CHINT_DISABLE 0x0 +#define CHINT_ENABLE 0x1 + + + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/include/DSP28x_Project.h b/v120/DSP2833x_common/include/DSP28x_Project.h new file mode 100644 index 0000000..399c1db --- /dev/null +++ b/v120/DSP2833x_common/include/DSP28x_Project.h @@ -0,0 +1,22 @@ + +// TI File $Revision: /main/1 $ +// Checkin $Date: April 22, 2008 14:35:56 $ +//########################################################################### +// +// FILE: DSP28x_Project.h +// +// TITLE: DSP28x Project Headerfile and Examples Include File +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP28x_PROJECT_H +#define DSP28x_PROJECT_H + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +#endif // end of DSP28x_PROJECT_H definition + diff --git a/v120/DSP2833x_common/source/DSP2833x_ADC_cal.asm b/v120/DSP2833x_common/source/DSP2833x_ADC_cal.asm new file mode 100644 index 0000000..7108ffa --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_ADC_cal.asm @@ -0,0 +1,42 @@ +;; TI File $Revision: /main/1 $ +;; Checkin $Date: July 30, 2007 10:29:23 $ +;;########################################################################### +;; +;; FILE: ADC_cal.asm +;; +;; TITLE: 2833x Boot Rom ADC Cal routine. +;; +;; Functions: +;; +;; _ADC_cal - Copies device specific calibration data into ADCREFSEL and ADCOFFTRIM registers +;; Notes: +;; +;;########################################################################### +;; $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +;; $Release Date: August 1, 2008 $ +;;########################################################################### + + .def _ADC_cal + .asg "0x711C", ADCREFSEL_LOC + +;----------------------------------------------- +; _ADC_cal +;----------------------------------------------- +;----------------------------------------------- +; This is the ADC cal routine.This routine is programmed into +; reserved memory by the factory. 0xAAAA and 0xBBBB are place- +; holders for calibration data. +;The actual values programmed by TI are device specific. +; +; This function assumes that the clocks have been +; enabled to the ADC module. +;----------------------------------------------- + + .sect ".adc_cal" + +_ADC_cal + MOVW DP, #ADCREFSEL_LOC >> 6 + MOV @28, #0xAAAA ; actual value may not be 0xAAAA + MOV @29, #0xBBBB ; actual value may not be 0xBBBB + LRETR +;eof ---------- diff --git a/v120/DSP2833x_common/source/DSP2833x_Adc.c b/v120/DSP2833x_common/source/DSP2833x_Adc.c new file mode 100644 index 0000000..730415b --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_Adc.c @@ -0,0 +1,65 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: October 23, 2007 13:34:09 $ +//########################################################################### +// +// FILE: DSP2833x_Adc.c +// +// TITLE: DSP2833x ADC Initialization & Support Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +#define ADC_usDELAY 5000L + +//--------------------------------------------------------------------------- +// InitAdc: +//--------------------------------------------------------------------------- +// This function initializes ADC to a known state. +// +void InitAdc(void) +{ + extern void DSP28x_usDelay(Uint32 Count); + + + // *IMPORTANT* + // The ADC_cal function, which copies the ADC calibration values from TI reserved + // OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs automatically in the + // Boot ROM. If the boot ROM code is bypassed during the debug process, the + // following function MUST be called for the ADC to function according + // to specification. The clocks to the ADC MUST be enabled before calling this + // function. + // See the device data manual and/or the ADC Reference + // Manual for more information. + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; + ADC_cal(); + EDIS; + + + + + // To powerup the ADC the ADCENCLK bit should be set first to enable + // clocks, followed by powering up the bandgap, reference circuitry, and ADC core. + // Before the first conversion is performed a 5ms delay must be observed + // after power up to give all analog circuits time to power up and settle + + // Please note that for the delay function below to operate correctly the + // CPU_RATE define statement in the DSP2833x_Examples.h file must + // contain the correct CPU clock period in nanoseconds. + + AdcRegs.ADCREFSEL.bit.REF_SEL = 0x01; + AdcRegs.ADCTRL3.all = 0x00E0; // Power up bandgap/reference/ADC circuits + DELAY_US(ADC_usDELAY); // Delay before converting ADC channels +//pause_us(50L); +} + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_common/source/DSP2833x_CpuTimers.c b/v120/DSP2833x_common/source/DSP2833x_CpuTimers.c new file mode 100644 index 0000000..b0dfd76 --- /dev/null +++ b/v120/DSP2833x_common/source/DSP2833x_CpuTimers.c @@ -0,0 +1,115 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: March 16, 2007 08:37:30 $ +//########################################################################### +// +// FILE: DSP2833x_CpuTimers.c +// +// TITLE: CPU 32-bit Timers Initialization & Support Functions. +// +// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and +// other realtime operating systems. +// +// Do not use these two timers in your application if you ever plan +// on integrating DSP-BIOS or another realtime OS. +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // Headerfile Include File +#include "DSP2833x_Examples.h" // Examples Include File + +struct CPUTIMER_VARS CpuTimer0; + +// CpuTimer 1 and CpuTimer2 are used by DSP BIOS & other RTOS. Comment out if using DSP BIOS or other RTOS. +struct CPUTIMER_VARS CpuTimer1; +struct CPUTIMER_VARS CpuTimer2; + +//--------------------------------------------------------------------------- +// InitCpuTimers: +//--------------------------------------------------------------------------- +// This function initializes all three CPU timers to a known state. +// +void InitCpuTimers(void) +{ + // CPU Timer 0 + // Initialize address pointers to respective timer registers: + CpuTimer0.RegsAddr = &CpuTimer0Regs; + // Initialize timer period to maximum: + CpuTimer0Regs.PRD.all = 0xFFFFFFFF; + // Initialize pre-scale counter to divide by 1 (SYSCLKOUT): + CpuTimer0Regs.TPR.all = 0; + CpuTimer0Regs.TPRH.all = 0; + // Make sure timer is stopped: + CpuTimer0Regs.TCR.bit.TSS = 1; + // Reload all counter register with period value: + CpuTimer0Regs.TCR.bit.TRB = 1; + // Reset interrupt counters: + CpuTimer0.InterruptCount = 0; + + +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS +// Do not use these two timers if you ever plan on integrating +// DSP-BIOS or another realtime OS. +// +// Initialize address pointers to respective timer registers: + CpuTimer1.RegsAddr = &CpuTimer1Regs; + CpuTimer2.RegsAddr = &CpuTimer2Regs; + // Initialize timer period to maximum: + CpuTimer1Regs.PRD.all = 0xFFFFFFFF; + CpuTimer2Regs.PRD.all = 0xFFFFFFFF; + // Initialize pre-scale counter to divide by 1 (SYSCLKOUT): + CpuTimer1Regs.TPR.all = 0; + CpuTimer1Regs.TPRH.all = 0; + CpuTimer2Regs.TPR.all = 0; + CpuTimer2Regs.TPRH.all = 0; + // Make sure timers are stopped: + CpuTimer1Regs.TCR.bit.TSS = 1; + CpuTimer2Regs.TCR.bit.TSS = 1; + // Reload all counter register with period value: + CpuTimer1Regs.TCR.bit.TRB = 1; + CpuTimer2Regs.TCR.bit.TRB = 1; + // Reset interrupt counters: + CpuTimer1.InterruptCount = 0; + CpuTimer2.InterruptCount = 0; + +} + +//--------------------------------------------------------------------------- +// ConfigCpuTimer: +//--------------------------------------------------------------------------- +// This function initializes the selected timer to the period specified +// by the "Freq" and "Period" parameters. The "Freq" is entered as "MHz" +// and the period in "uSeconds". The timer is held in the stopped state +// after configuration. +// +void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period) +{ + Uint32 temp; + + // Initialize timer period: + Timer->CPUFreqInMHz = Freq; + Timer->PeriodInUSec = Period; + temp = (long) (Freq * Period); + Timer->RegsAddr->PRD.all = temp; + + // Set pre-scale counter to divide by 1 (SYSCLKOUT): + Timer->RegsAddr->TPR.all = 0; + Timer->RegsAddr->TPRH.all = 0; + + // Initialize timer control register: + Timer->RegsAddr->TCR.bit.TSS = 1; // 1 = Stop timer, 0 = Start/Restart Timer + Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer + Timer->RegsAddr->TCR.bit.SOFT = 0; + Timer->RegsAddr->TCR.bit.FREE = 0; // Timer Free Run Disabled + Timer->RegsAddr->TCR.bit.TIE = 1; // 0 = Disable/ 1 = Enable Timer Interrupt + + // Reset interrupt counter: + Timer->InterruptCount = 0; +} + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_Adc.h b/v120/DSP2833x_headers/include/DSP2833x_Adc.h new file mode 100644 index 0000000..5c8467a --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_Adc.h @@ -0,0 +1,264 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:51:50 $ +//########################################################################### +// +// FILE: DSP2833x_Adc.h +// +// TITLE: DSP2833x Device ADC Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_ADC_H +#define DSP2833x_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// ADC Individual Register Bit Definitions: + +struct ADCTRL1_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode + Uint16 SEQ_OVRD:1; // 5 Sequencer override + Uint16 CONT_RUN:1; // 6 Continuous run + Uint16 CPS:1; // 7 ADC core clock pre-scalar + Uint16 ACQ_PS:4; // 11:8 Acquisition window size + Uint16 SUSMOD:2; // 13:12 Emulation suspend mode + Uint16 RESET:1; // 14 ADC reset + Uint16 rsvd2:1; // 15 reserved +}; + + +union ADCTRL1_REG { + Uint16 all; + struct ADCTRL1_BITS bit; +}; + + +struct ADCTRL2_BITS { // bits description + Uint16 EPWM_SOCB_SEQ2:1; // 0 EPWM compare B SOC mask for SEQ2 + Uint16 rsvd1:1; // 1 reserved + Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode + Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable + Uint16 rsvd2:1; // 4 reserved + Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2 + Uint16 RST_SEQ2:1; // 6 Reset SEQ2 + Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1 + Uint16 EPWM_SOCA_SEQ1:1; // 8 EPWM compare B SOC mask for SEQ1 + Uint16 rsvd3:1; // 9 reserved + Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode + Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable + Uint16 rsvd4:1; // 12 reserved + Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1 + Uint16 RST_SEQ1:1; // 14 Restart sequencer 1 + Uint16 EPWM_SOCB_SEQ:1; // 15 EPWM compare B SOC enable +}; + + +union ADCTRL2_REG { + Uint16 all; + struct ADCTRL2_BITS bit; +}; + + +struct ADCASEQSR_BITS { // bits description + Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state + Uint16 SEQ2_STATE:3; // 6:4 SEQ2 state + Uint16 rsvd1:1; // 7 reserved + Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status + Uint16 rsvd2:4; // 15:12 reserved +}; + +union ADCASEQSR_REG { + Uint16 all; + struct ADCASEQSR_BITS bit; +}; + + +struct ADCMAXCONV_BITS { // bits description + Uint16 MAX_CONV1:4; // 3:0 Max number of conversions + Uint16 MAX_CONV2:3; // 6:4 Max number of conversions + Uint16 rsvd1:9; // 15:7 reserved +}; + +union ADCMAXCONV_REG { + Uint16 all; + struct ADCMAXCONV_BITS bit; +}; + + +struct ADCCHSELSEQ1_BITS { // bits description + Uint16 CONV00:4; // 3:0 Conversion selection 00 + Uint16 CONV01:4; // 7:4 Conversion selection 01 + Uint16 CONV02:4; // 11:8 Conversion selection 02 + Uint16 CONV03:4; // 15:12 Conversion selection 03 +}; + +union ADCCHSELSEQ1_REG{ + Uint16 all; + struct ADCCHSELSEQ1_BITS bit; +}; + +struct ADCCHSELSEQ2_BITS { // bits description + Uint16 CONV04:4; // 3:0 Conversion selection 04 + Uint16 CONV05:4; // 7:4 Conversion selection 05 + Uint16 CONV06:4; // 11:8 Conversion selection 06 + Uint16 CONV07:4; // 15:12 Conversion selection 07 +}; + +union ADCCHSELSEQ2_REG{ + Uint16 all; + struct ADCCHSELSEQ2_BITS bit; +}; + +struct ADCCHSELSEQ3_BITS { // bits description + Uint16 CONV08:4; // 3:0 Conversion selection 08 + Uint16 CONV09:4; // 7:4 Conversion selection 09 + Uint16 CONV10:4; // 11:8 Conversion selection 10 + Uint16 CONV11:4; // 15:12 Conversion selection 11 +}; + +union ADCCHSELSEQ3_REG{ + Uint16 all; + struct ADCCHSELSEQ3_BITS bit; +}; + +struct ADCCHSELSEQ4_BITS { // bits description + Uint16 CONV12:4; // 3:0 Conversion selection 12 + Uint16 CONV13:4; // 7:4 Conversion selection 13 + Uint16 CONV14:4; // 11:8 Conversion selection 14 + Uint16 CONV15:4; // 15:12 Conversion selection 15 +}; + +union ADCCHSELSEQ4_REG { + Uint16 all; + struct ADCCHSELSEQ4_BITS bit; +}; + +struct ADCTRL3_BITS { // bits description + Uint16 SMODE_SEL:1; // 0 Sampling mode select + Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider + Uint16 ADCPWDN:1; // 5 ADC powerdown + Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCTRL3_REG { + Uint16 all; + struct ADCTRL3_BITS bit; +}; + + +struct ADCST_BITS { // bits description + Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag + Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag + Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status + Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status + Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear + Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear + Uint16 EOS_BUF1:1; // 6 End of sequence buffer1 + Uint16 EOS_BUF2:1; // 7 End of sequence buffer2 + Uint16 rsvd1:8; // 15:8 reserved +}; + + +union ADCST_REG { + Uint16 all; + struct ADCST_BITS bit; +}; + +struct ADCREFSEL_BITS { // bits description + Uint16 rsvd1:14; // 13:0 reserved + Uint16 REF_SEL:2; // 15:14 Reference select +}; +union ADCREFSEL_REG { + Uint16 all; + struct ADCREFSEL_BITS bit; +}; + +struct ADCOFFTRIM_BITS{ // bits description + int16 OFFSET_TRIM:9; // 8:0 Offset Trim + Uint16 rsvd1:7; // 15:9 reserved +}; + +union ADCOFFTRIM_REG{ + Uint16 all; + struct ADCOFFTRIM_BITS bit; +}; +struct ADC_REGS { + union ADCTRL1_REG ADCTRL1; // ADC Control 1 + union ADCTRL2_REG ADCTRL2; // ADC Control 2 + union ADCMAXCONV_REG ADCMAXCONV; // Max conversions + union ADCCHSELSEQ1_REG ADCCHSELSEQ1; // Channel select sequencing control 1 + union ADCCHSELSEQ2_REG ADCCHSELSEQ2; // Channel select sequencing control 2 + union ADCCHSELSEQ3_REG ADCCHSELSEQ3; // Channel select sequencing control 3 + union ADCCHSELSEQ4_REG ADCCHSELSEQ4; // Channel select sequencing control 4 + union ADCASEQSR_REG ADCASEQSR; // Autosequence status register + Uint16 ADCRESULT0; // Conversion Result Buffer 0 + Uint16 ADCRESULT1; // Conversion Result Buffer 1 + Uint16 ADCRESULT2; // Conversion Result Buffer 2 + Uint16 ADCRESULT3; // Conversion Result Buffer 3 + Uint16 ADCRESULT4; // Conversion Result Buffer 4 + Uint16 ADCRESULT5; // Conversion Result Buffer 5 + Uint16 ADCRESULT6; // Conversion Result Buffer 6 + Uint16 ADCRESULT7; // Conversion Result Buffer 7 + Uint16 ADCRESULT8; // Conversion Result Buffer 8 + Uint16 ADCRESULT9; // Conversion Result Buffer 9 + Uint16 ADCRESULT10; // Conversion Result Buffer 10 + Uint16 ADCRESULT11; // Conversion Result Buffer 11 + Uint16 ADCRESULT12; // Conversion Result Buffer 12 + Uint16 ADCRESULT13; // Conversion Result Buffer 13 + Uint16 ADCRESULT14; // Conversion Result Buffer 14 + Uint16 ADCRESULT15; // Conversion Result Buffer 15 + union ADCTRL3_REG ADCTRL3; // ADC Control 3 + union ADCST_REG ADCST; // ADC Status Register + Uint16 rsvd1; + Uint16 rsvd2; + union ADCREFSEL_REG ADCREFSEL; // Reference Select Register + union ADCOFFTRIM_REG ADCOFFTRIM; // Offset Trim Register +}; + + +struct ADC_RESULT_MIRROR_REGS +{ + Uint16 ADCRESULT0; // Conversion Result Buffer 0 + Uint16 ADCRESULT1; // Conversion Result Buffer 1 + Uint16 ADCRESULT2; // Conversion Result Buffer 2 + Uint16 ADCRESULT3; // Conversion Result Buffer 3 + Uint16 ADCRESULT4; // Conversion Result Buffer 4 + Uint16 ADCRESULT5; // Conversion Result Buffer 5 + Uint16 ADCRESULT6; // Conversion Result Buffer 6 + Uint16 ADCRESULT7; // Conversion Result Buffer 7 + Uint16 ADCRESULT8; // Conversion Result Buffer 8 + Uint16 ADCRESULT9; // Conversion Result Buffer 9 + Uint16 ADCRESULT10; // Conversion Result Buffer 10 + Uint16 ADCRESULT11; // Conversion Result Buffer 11 + Uint16 ADCRESULT12; // Conversion Result Buffer 12 + Uint16 ADCRESULT13; // Conversion Result Buffer 13 + Uint16 ADCRESULT14; // Conversion Result Buffer 14 + Uint16 ADCRESULT15; // Conversion Result Buffer 15 +}; + +//--------------------------------------------------------------------------- +// ADC External References & Function Declarations: +// +extern volatile struct ADC_REGS AdcRegs; +extern volatile struct ADC_RESULT_MIRROR_REGS AdcMirror; + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + + +#endif // end of DSP2833x_ADC_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_CpuTimers.h b/v120/DSP2833x_headers/include/DSP2833x_CpuTimers.h new file mode 100644 index 0000000..3475801 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_CpuTimers.h @@ -0,0 +1,190 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: March 20, 2007 15:33:42 $ +//########################################################################### +// +// FILE: DSP2833x_CpuTimers.h +// +// TITLE: DSP2833x CPU 32-bit Timers Register Definitions. +// +// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and +// other realtime operating systems. +// +// Do not use these two timers in your application if you ever plan +// on integrating DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two timers +// if using DSP-BIOS or another realtime OS. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_CPU_TIMERS_H +#define DSP2833x_CPU_TIMERS_H + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------------- +// CPU Timer Register Bit Definitions: +// +// +// TCR: Control register bit definitions: +struct TCR_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 TSS:1; // 4 Timer Start/Stop + Uint16 TRB:1; // 5 Timer reload + Uint16 rsvd2:4; // 9:6 reserved + Uint16 SOFT:1; // 10 Emulation modes + Uint16 FREE:1; // 11 + Uint16 rsvd3:2; // 12:13 reserved + Uint16 TIE:1; // 14 Output enable + Uint16 TIF:1; // 15 Interrupt flag +}; + +union TCR_REG { + Uint16 all; + struct TCR_BITS bit; +}; + +// TPR: Pre-scale low bit definitions: +struct TPR_BITS { // bits description + Uint16 TDDR:8; // 7:0 Divide-down low + Uint16 PSC:8; // 15:8 Prescale counter low +}; + +union TPR_REG { + Uint16 all; + struct TPR_BITS bit; +}; + +// TPRH: Pre-scale high bit definitions: +struct TPRH_BITS { // bits description + Uint16 TDDRH:8; // 7:0 Divide-down high + Uint16 PSCH:8; // 15:8 Prescale counter high +}; + +union TPRH_REG { + Uint16 all; + struct TPRH_BITS bit; +}; + +// TIM, TIMH: Timer register definitions: +struct TIM_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union TIM_GROUP { + Uint32 all; + struct TIM_REG half; +}; + +// PRD, PRDH: Period register definitions: +struct PRD_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union PRD_GROUP { + Uint32 all; + struct PRD_REG half; +}; + +//--------------------------------------------------------------------------- +// CPU Timer Register File: +// +struct CPUTIMER_REGS { + union TIM_GROUP TIM; // Timer counter register + union PRD_GROUP PRD; // Period register + union TCR_REG TCR; // Timer control register + Uint16 rsvd1; // reserved + union TPR_REG TPR; // Timer pre-scale low + union TPRH_REG TPRH; // Timer pre-scale high +}; + +//--------------------------------------------------------------------------- +// CPU Timer Support Variables: +// +struct CPUTIMER_VARS { + volatile struct CPUTIMER_REGS *RegsAddr; + Uint32 InterruptCount; + float CPUFreqInMHz; + float PeriodInUSec; +}; + +//--------------------------------------------------------------------------- +// Function prototypes and external definitions: +// +void InitCpuTimers(void); +void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); + +extern volatile struct CPUTIMER_REGS CpuTimer0Regs; +extern struct CPUTIMER_VARS CpuTimer0; + +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS. Comment out CpuTimer1 and CpuTimer2 if using DSP BIOS or other RTOS +extern volatile struct CPUTIMER_REGS CpuTimer1Regs; +extern volatile struct CPUTIMER_REGS CpuTimer2Regs; + +extern struct CPUTIMER_VARS CpuTimer1; +extern struct CPUTIMER_VARS CpuTimer2; + +//--------------------------------------------------------------------------- +// Usefull Timer Operations: +// +// Start Timer: +#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 + +// Stop Timer: +#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 + +// Reload Timer With period Value: +#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 + +// Read 32-Bit Timer Value: +#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all + +// Read 32-Bit Period Value: +#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all + +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS +// Do not use these two timers if you ever plan on integrating +// DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two timers +// if using DSP-BIOS or another realtime OS. + +// Start Timer: +#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 +#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 + + +// Stop Timer: +#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 +#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 + +// Reload Timer With period Value: +#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 +#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 + +// Read 32-Bit Timer Value: +#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all +#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all + +// Read 32-Bit Period Value: +#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all +#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_CPU_TIMERS_H definition + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_DMA.h b/v120/DSP2833x_headers/include/DSP2833x_DMA.h new file mode 100644 index 0000000..e8b0d59 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_DMA.h @@ -0,0 +1,295 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: June 23, 2008 11:34:15 $ +//########################################################################### +// +// FILE: DSP2833x_DMA.h +// +// TITLE: DSP2833x DMA Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_DMA_H +#define DSP2833x_DMA_H + + +#ifdef __cplusplus +extern "C" { +#endif + +//---------------------------------------------------- +// Channel MODE register bit definitions: +struct MODE_BITS { // bits description + Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select Bits (R/W): + // 0 no interrupt + // 1 SEQ1INT & ADCSYNC + // 2 SEQ2INT + // 3 XINT1 + // 4 XINT2 + // 5 XINT3 + // 6 XINT4 + // 7 XINT5 + // 8 XINT6 + // 9 XINT7 + // 10 XINT13 + // 11 TINT0 + // 12 TINT1 + // 13 TINT2 + // 14 MXEVTA & MXSYNCA + // 15 MREVTA & MRSYNCA + // 16 MXEVTB & MXSYNCB + // 17 MREVTB & MRSYNCB + // 18 ePWM1SOCA + // 19 ePWM1SOCB + // 20 ePWM2SOCA + // 21 ePWM2SOCB + // 22 ePWM3SOCA + // 23 ePWM3SOCB + // 24 ePWM4SOCA + // 25 ePWM4SOCB + // 26 ePWM5SOCA + // 27 ePWM5SOCB + // 28 ePWM6SOCA + // 29 ePWM6SOCB + // 30:31 no interrupt + Uint16 rsvd1:2; // 6:5 (R=0:0) + Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable (R/W): + // 0 overflow interrupt disabled + // 1 overflow interrupt enabled + Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable Bit (R/W): + // 0 peripheral interrupt disabled + // 1 peripheral interrupt enabled + Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode Bit (R/W): + // 0 generate interrupt at beginning of new transfer + // 1 generate interrupt at end of transfer + Uint16 ONESHOT:1; // 10 One Shot Mode Bit (R/W): + // 0 only interrupt event triggers single burst transfer + // 1 first interrupt triggers burst, continue until transfer count is zero + Uint16 CONTINUOUS:1; // 11 Continous Mode Bit (R/W): + // 0 stop when transfer count is zero + // 1 re-initialize when transfer count is zero + Uint16 SYNCE:1; // 12 Sync Enable Bit (R/W): + // 0 ignore selected interrupt sync signal + // 1 enable selected interrupt sync signal + Uint16 SYNCSEL:1; // 13 Sync Select Bit (R/W): + // 0 sync signal controls source wrap counter + // 1 sync signal controls destination wrap counter + Uint16 DATASIZE:1; // 14 Data Size Mode Bit (R/W): + // 0 16-bit data transfer size + // 1 32-bit data transfer size + Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit (R/W): + // 0 channel interrupt disabled + // 1 channel interrupt enabled +}; + +union MODE_REG { + Uint16 all; + struct MODE_BITS bit; +}; + +//---------------------------------------------------- +// Channel CONTROL register bit definitions: +struct CONTROL_BITS { // bits description + Uint16 RUN:1; // 0 Run Bit (R=0/W=1) + Uint16 HALT:1; // 1 Halt Bit (R=0/W=1) + Uint16 SOFTRESET:1; // 2 Soft Reset Bit (R=0/W=1) + Uint16 PERINTFRC:1; // 3 Interrupt Force Bit (R=0/W=1) + Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit (R=0/W=1) + Uint16 SYNCFRC:1; // 5 Sync Force Bit (R=0/W=1) + Uint16 SYNCCLR:1; // 6 Sync Clear Bit (R=0/W=1) + Uint16 ERRCLR:1; // 7 Error Clear Bit (R=0/W=1) + Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit (R): + // 0 no interrupt pending + // 1 interrupt pending + Uint16 SYNCFLG:1; // 9 Sync Flag Bit (R): + // 0 no sync pending + // 1 sync pending + Uint16 SYNCERR:1; // 10 Sync Error Flag Bit (R): + // 0 no sync error + // 1 sync error detected + Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit (R): + // 0 no transfer in progress or pending + // 1 transfer in progress or pending + Uint16 BURSTSTS:1; // 12 Burst Status Bit (R): + // 0 no burst in progress or pending + // 1 burst in progress or pending + Uint16 RUNSTS:1; // 13 Run Status Bit (R): + // 0 channel not running or halted + // 1 channel running + Uint16 OVRFLG:1; // 14 Overflow Flag Bit(R) + // 0 no overflow event + // 1 overflow event + Uint16 rsvd1:1; // 15 (R=0) +}; + +union CONTROL_REG { + Uint16 all; + struct CONTROL_BITS bit; +}; + +//---------------------------------------------------- +// DMACTRL register bit definitions: +struct DMACTRL_BITS { // bits description + Uint16 HARDRESET:1; // 0 Hard Reset Bit (R=0/W=1) + Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit (R=0/W=1) + Uint16 rsvd1:14; // 15:2 (R=0:0) +}; + +union DMACTRL_REG { + Uint16 all; + struct DMACTRL_BITS bit; +}; + +//---------------------------------------------------- +// DEBUGCTRL register bit definitions: +struct DEBUGCTRL_BITS { // bits description + Uint16 rsvd1:15; // 14:0 (R=0:0) + Uint16 FREE:1; // 15 Debug Mode Bit (R/W): + // 0 halt after current read-write operation + // 1 continue running +}; + +union DEBUGCTRL_REG { + Uint16 all; + struct DEBUGCTRL_BITS bit; +}; + + +//---------------------------------------------------- +// PRIORITYCTRL1 register bit definitions: +struct PRIORITYCTRL1_BITS { // bits description + Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit (R/W): + // 0 same priority as all other channels + // 1 highest priority channel + Uint16 rsvd1:15; // 15:1 (R=0:0) +}; + +union PRIORITYCTRL1_REG { + Uint16 all; + struct PRIORITYCTRL1_BITS bit; +}; + + +//---------------------------------------------------- +// PRIORITYSTAT register bit definitions: +struct PRIORITYSTAT_BITS { // bits description + Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits (R): + // 0,0,0 no channel active + // 0,0,1 Ch1 channel active + // 0,1,0 Ch2 channel active + // 0,1,1 Ch3 channel active + // 1,0,0 Ch4 channel active + // 1,0,1 Ch5 channel active + // 1,1,0 Ch6 channel active + Uint16 rsvd1:1; // 3 (R=0) + Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits (R): + // 0,0,0 no channel active and interrupted by Ch1 + // 0,0,1 cannot occur + // 0,1,0 Ch2 was active and interrupted by Ch1 + // 0,1,1 Ch3 was active and interrupted by Ch1 + // 1,0,0 Ch4 was active and interrupted by Ch1 + // 1,0,1 Ch5 was active and interrupted by Ch1 + // 1,1,0 Ch6 was active and interrupted by Ch1 + Uint16 rsvd2:9; // 15:7 (R=0:0) +}; + +union PRIORITYSTAT_REG { + Uint16 all; + struct PRIORITYSTAT_BITS bit; +}; + +// Burst Size +struct BURST_SIZE_BITS { // bits description + Uint16 BURSTSIZE:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_SIZE_REG { + Uint16 all; + struct BURST_SIZE_BITS bit; +}; + +// Burst Count +struct BURST_COUNT_BITS { // bits description + Uint16 BURSTCOUNT:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_COUNT_REG { + Uint16 all; + struct BURST_COUNT_BITS bit; +}; + + + +//---------------------------------------------------- +// DMA Channel Registers: +struct CH_REGS { + union MODE_REG MODE; // Mode Register + union CONTROL_REG CONTROL; // Control Register + + union BURST_SIZE_REG BURST_SIZE; // Burst Size Register + union BURST_COUNT_REG BURST_COUNT; // Burst Count Register + int16 SRC_BURST_STEP; // Source Burst Step Register + int16 DST_BURST_STEP; // Destination Burst Step Register + + Uint16 TRANSFER_SIZE; // Transfer Size Register + Uint16 TRANSFER_COUNT; // Transfer Count Register + int16 SRC_TRANSFER_STEP; // Source Transfer Step Register + int16 DST_TRANSFER_STEP; // Destination Transfer Step Register + + Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register + Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register + int16 SRC_WRAP_STEP; // Source Wrap Step Register + + Uint16 DST_WRAP_SIZE; // Destination Wrap Size Register + Uint16 DST_WRAP_COUNT; // Destination Wrap Count Register + int16 DST_WRAP_STEP; // Destination Wrap Step Register + + Uint32 SRC_BEG_ADDR_SHADOW; // Source Begin Address Shadow Register + Uint32 SRC_ADDR_SHADOW; // Source Address Shadow Register + Uint32 SRC_BEG_ADDR_ACTIVE; // Source Begin Address Active Register + Uint32 SRC_ADDR_ACTIVE; // Source Address Active Register + + Uint32 DST_BEG_ADDR_SHADOW; // Destination Begin Address Shadow Register + Uint32 DST_ADDR_SHADOW; // Destination Address Shadow Register + Uint32 DST_BEG_ADDR_ACTIVE; // Destination Begin Address Active Register + Uint32 DST_ADDR_ACTIVE; // Destination Address Active Register +}; + +//---------------------------------------------------- +// DMA Registers: +struct DMA_REGS { + union DMACTRL_REG DMACTRL; // DMA Control Register + union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register + Uint16 rsvd0; // reserved + Uint16 rsvd1; // + union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register + Uint16 rsvd2; // + union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register + Uint16 rsvd3[25]; // + struct CH_REGS CH1; // DMA Channel 1 Registers + struct CH_REGS CH2; // DMA Channel 2 Registers + struct CH_REGS CH3; // DMA Channel 3 Registers + struct CH_REGS CH4; // DMA Channel 4 Registers + struct CH_REGS CH5; // DMA Channel 5 Registers + struct CH_REGS CH6; // DMA Channel 6 Registers +}; + + +//--------------------------------------------------------------------------- +// External References & Function Declarations: +// +extern volatile struct DMA_REGS DmaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DMA_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_DevEmu.h b/v120/DSP2833x_headers/include/DSP2833x_DevEmu.h new file mode 100644 index 0000000..3a765c6 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_DevEmu.h @@ -0,0 +1,97 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: June 2, 2008 11:12:30 $ +//########################################################################### +// +// FILE: DSP2833x_DevEmu.h +// +// TITLE: DSP2833x Device Emulation Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_DEV_EMU_H +#define DSP2833x_DEV_EMU_H + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------------- +// Device Emulation Register Bit Definitions: +// +// Device Configuration Register Bit Definitions +struct DEVICECNF_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 VMAPS:1; // 3 VMAP Status + Uint16 rsvd2:1; // 4 reserved + Uint16 XRSn:1; // 5 XRSn Signal Status + Uint16 rsvd3:10; // 15:6 + Uint16 rsvd4:3; // 18:16 + Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection + Uint16 MONPRIV:1; // 20 MONPRIV enable bit + Uint16 rsvd5:1; // 21 reserved + Uint16 EMU0SEL:2; // 23,22 EMU0 Mux select + Uint16 EMU1SEL:2; // 25,24 EMU1 Mux select + Uint16 MCBSPCON:1; // 26 McBSP-B to EMU0/EMU1 pins control + Uint16 rsvd6:5; // 31:27 reserved +}; + +union DEVICECNF_REG { + Uint32 all; + struct DEVICECNF_BITS bit; +}; + +// CLASSID +struct CLASSID_BITS { // bits description + Uint16 CLASSNO:8; // 7:0 Class Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union CLASSID_REG { + Uint16 all; + struct CLASSID_BITS bit; +}; + +struct DEV_EMU_REGS { + union DEVICECNF_REG DEVICECNF; // device configuration + union CLASSID_REG CLASSID; // Class ID + Uint16 REVID; // Device ID + Uint16 PROTSTART; // Write-Read protection start + Uint16 PROTRANGE; // Write-Read protection range + Uint16 rsvd2[202]; +}; + +// PARTID +struct PARTID_BITS { // bits description + Uint16 PARTNO:8; // 7:0 Part Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union PARTID_REG { + Uint16 all; + struct PARTID_BITS bit; +}; + +struct PARTID_REGS { + union PARTID_REG PARTID; // Part ID +}; + + + +//--------------------------------------------------------------------------- +// Device Emulation Register References & Function Declarations: +// +extern volatile struct DEV_EMU_REGS DevEmuRegs; +extern volatile struct PARTID_REGS PartIdRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEV_EMU_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_Device.h b/v120/DSP2833x_headers/include/DSP2833x_Device.h new file mode 100644 index 0000000..0cf9a3b --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_Device.h @@ -0,0 +1,368 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: January 22, 2008 16:55:35 $ +//########################################################################### +// +// FILE: DSP2833x_Device.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_DEVICE_H +#define DSP2833x_DEVICE_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +#define TARGET 1 +//--------------------------------------------------------------------------- +// User To Select Target Device: + +#define DSP28_28335 TARGET // Selects '28335/'28235 +#define DSP28_28334 0 // Selects '28334/'28234 +#define DSP28_28332 0 // Selects '28332/'28232 + + +//--------------------------------------------------------------------------- +// Common CPU Definitions: +// + +extern cregister volatile unsigned int IFR; +extern cregister volatile unsigned int IER; + +#define EINT asm(" clrc INTM") +#define DINT asm(" setc INTM") +#define ERTM asm(" clrc DBGM") +#define DRTM asm(" setc DBGM") +#define EALLOW asm(" EALLOW") +#define EDIS asm(" EDIS") +#define ESTOP0 asm(" ESTOP0") + +#define M_INT1 0x0001 +#define M_INT2 0x0002 +#define M_INT3 0x0004 +#define M_INT4 0x0008 +#define M_INT5 0x0010 +#define M_INT6 0x0020 +#define M_INT7 0x0040 +#define M_INT8 0x0080 +#define M_INT9 0x0100 +#define M_INT10 0x0200 +#define M_INT11 0x0400 +#define M_INT12 0x0800 +#define M_INT13 0x1000 +#define M_INT14 0x2000 +#define M_DLOG 0x4000 +#define M_RTOS 0x8000 + +#define BIT0 0x0001 +#define BIT1 0x0002 +#define BIT2 0x0004 +#define BIT3 0x0008 +#define BIT4 0x0010 +#define BIT5 0x0020 +#define BIT6 0x0040 +#define BIT7 0x0080 +#define BIT8 0x0100 +#define BIT9 0x0200 +#define BIT10 0x0400 +#define BIT11 0x0800 +#define BIT12 0x1000 +#define BIT13 0x2000 +#define BIT14 0x4000 +#define BIT15 0x8000 + + + +//--------------------------------------------------------------------------- +// For Portability, User Is Recommended To Use Following Data Type Size +// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: +// + +#ifndef DSP28_DATA_TYPES +#define DSP28_DATA_TYPES +typedef int int16; +typedef long int32; +typedef long long int64; +typedef unsigned int Uint16; +typedef unsigned long Uint32; +typedef unsigned long long Uint64; +typedef float float32; +typedef long double float64; +#endif + +typedef union +{ + struct + { + unsigned int bit0: 1; + unsigned int bit1: 1; + unsigned int bit2: 1; + unsigned int bit3: 1; + unsigned int bit4: 1; + unsigned int bit5: 1; + unsigned int bit6: 1; + unsigned int bit7: 1; + + } bit; + + struct + { + unsigned int quad_0 :4; + unsigned int quad_1 :4; + + } qua; + + unsigned short all; + +} BAITE; + +typedef union +{ + struct + { + unsigned int bit0: 1; + unsigned int bit1: 1; + unsigned int bit2: 1; + unsigned int bit3: 1; + unsigned int bit4: 1; + unsigned int bit5: 1; + unsigned int bit6: 1; + unsigned int bit7: 1; + unsigned int bit8: 1; + unsigned int bit9: 1; + unsigned int bitA: 1; + unsigned int bitB: 1; + unsigned int bitC: 1; + unsigned int bitD: 1; + unsigned int bitE: 1; + unsigned int bitF: 1; + + } bit; + + struct + { + unsigned int quad_0 :4; + unsigned int quad_1 :4; + unsigned int quad_2 :4; + unsigned int quad_3 :4; + + } qua; + + struct + { + unsigned int byte_0 :8; + unsigned int byte_1 :8; + + } byt; + + int all; + +} WORDE; + +typedef union +{ + struct + { + unsigned int bit00: 1; + unsigned int bit01: 1; + unsigned int bit02: 1; + unsigned int bit03: 1; + unsigned int bit04: 1; + unsigned int bit05: 1; + unsigned int bit06: 1; + unsigned int bit07: 1; + unsigned int bit08: 1; + unsigned int bit09: 1; + unsigned int bit0A: 1; + unsigned int bit0B: 1; + unsigned int bit0C: 1; + unsigned int bit0D: 1; + unsigned int bit0E: 1; + unsigned int bit0F: 1; + unsigned int bit10: 1; + unsigned int bit11: 1; + unsigned int bit12: 1; + unsigned int bit13: 1; + unsigned int bit14: 1; + unsigned int bit15: 1; + unsigned int bit16: 1; + unsigned int bit17: 1; + unsigned int bit18: 1; + unsigned int bit19: 1; + unsigned int bit1A: 1; + unsigned int bit1B: 1; + unsigned int bit1C: 1; + unsigned int bit1D: 1; + unsigned int bit1E: 1; + unsigned int bit1F: 1; + + } bit; + + struct + { + unsigned int quad_0 :4; + unsigned int quad_1 :4; + unsigned int quad_2 :4; + unsigned int quad_3 :4; + unsigned int quad_4 :4; + unsigned int quad_5 :4; + unsigned int quad_6 :4; + unsigned int quad_7 :4; + + } qua; + + struct + { + unsigned int byte_0 :8; + unsigned int byte_1 :8; + unsigned int byte_2 :8; + unsigned int byte_3 :8; + + } byt; + + struct + { + unsigned int word_0 :16; + unsigned int word_1 :16; + + } wrd; + + unsigned long all; + +} LONGE; + +#define XCLKIN 30000000 // external oscillator frequency +extern long SYSCLKOUT, LSPCLK, HSPCLK; + +#define CLKMULT 2L // 1 to 5 + +#define LOWORD(l)((short int)( (long int)(l) &0xFFFF)) +#define HIWORD(l)((short int)(((long int)(l)>>16)&0xFFFF)) + +#define LOBYTE(w)((char)( (short int)(w) &0xFF)) +#define HIBYTE(w)((char)(((short int)(w)>>8)&0xFF)) + +#define BYTE3(l)((char)(((long int)(l)>>24)&0xFF)) +#define BYTE2(l)((char)(((long int)(l)>>16)&0xFF)) +#define BYTE1(l)((char)(((long int)(l)>> 8)&0xFF)) +#define BYTE0(l)((char)( (long int)(l) &0xFF)) + +//--------------------------------------------------------------------------- +// Include All Peripheral Header Files: +// +#include "DSP2833x_Adc.h" // ADC Registers +#include "DSP2833x_DevEmu.h" // Device Emulation Registers +#include "DSP2833x_CpuTimers.h" // 32-bit CPU Timers +#include "DSP2833x_ECan.h" // Enhanced eCAN Registers +#include "DSP2833x_ECap.h" // Enhanced Capture +#include "DSP2833x_DMA.h" // DMA Registers +#include "DSP2833x_EPwm.h" // Enhanced PWM +#include "DSP2833x_EQep.h" // Enhanced QEP +#include "DSP2833x_Gpio.h" // General Purpose I/O Registers +#include "DSP2833x_I2c.h" // I2C Registers +#include "DSP2833x_McBSP.h" // McBSP +#include "DSP2833x_PieCtrl.h" // PIE Control Registers +#include "DSP2833x_PieVect.h" // PIE Vector Table +#include "DSP2833x_Spi.h" // SPI Registers +#include "DSP2833x_Sci.h" // SCI Registers +#include "DSP2833x_SysCtrl.h" // System Control/Power Modes +#include "DSP2833x_XIntrupt.h" // External Interrupts +#include "DSP2833x_Xintf.h" // XINTF External Interface + +#include "DSP2833x_GlobalPrototypes.h" // Prototypes for global functions within the + +#if DSP28_28335 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 1 +#define DSP28_ECAP6 1 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28335 + +#if DSP28_28334 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28334 + +#if DSP28_28332 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 0 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 0 +#define DSP28_I2CA 1 +#endif // end DSP28_28332 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEVICE_H definition + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_ECan.h b/v120/DSP2833x_headers/include/DSP2833x_ECan.h new file mode 100644 index 0000000..65988ca --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_ECan.h @@ -0,0 +1,1161 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: May 7, 2007 16:05:39 $ +//########################################################################### +// +// FILE: DSP2833x_ECan.h +// +// TITLE: DSP2833x Device eCAN Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_ECAN_H +#define DSP2833x_ECAN_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +/* --------------------------------------------------- */ +/* eCAN Control & Status Registers */ +/* ----------------------------------------------------*/ + +/* eCAN Mailbox enable register (CANME) bit definitions */ +struct CANME_BITS { // bit description + Uint16 ME0:1; // 0 Enable Mailbox 0 + Uint16 ME1:1; // 1 Enable Mailbox 1 + Uint16 ME2:1; // 2 Enable Mailbox 2 + Uint16 ME3:1; // 3 Enable Mailbox 3 + Uint16 ME4:1; // 4 Enable Mailbox 4 + Uint16 ME5:1; // 5 Enable Mailbox 5 + Uint16 ME6:1; // 6 Enable Mailbox 6 + Uint16 ME7:1; // 7 Enable Mailbox 7 + Uint16 ME8:1; // 8 Enable Mailbox 8 + Uint16 ME9:1; // 9 Enable Mailbox 9 + Uint16 ME10:1; // 10 Enable Mailbox 10 + Uint16 ME11:1; // 11 Enable Mailbox 11 + Uint16 ME12:1; // 12 Enable Mailbox 12 + Uint16 ME13:1; // 13 Enable Mailbox 13 + Uint16 ME14:1; // 14 Enable Mailbox 14 + Uint16 ME15:1; // 15 Enable Mailbox 15 + Uint16 ME16:1; // 16 Enable Mailbox 16 + Uint16 ME17:1; // 17 Enable Mailbox 17 + Uint16 ME18:1; // 18 Enable Mailbox 18 + Uint16 ME19:1; // 19 Enable Mailbox 19 + Uint16 ME20:1; // 20 Enable Mailbox 20 + Uint16 ME21:1; // 21 Enable Mailbox 21 + Uint16 ME22:1; // 22 Enable Mailbox 22 + Uint16 ME23:1; // 23 Enable Mailbox 23 + Uint16 ME24:1; // 24 Enable Mailbox 24 + Uint16 ME25:1; // 25 Enable Mailbox 25 + Uint16 ME26:1; // 26 Enable Mailbox 26 + Uint16 ME27:1; // 27 Enable Mailbox 27 + Uint16 ME28:1; // 28 Enable Mailbox 28 + Uint16 ME29:1; // 29 Enable Mailbox 29 + Uint16 ME30:1; // 30 Enable Mailbox 30 + Uint16 ME31:1; // 31 Enable Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANME_REG { + Uint32 all; + struct CANME_BITS bit; +}; + +/* eCAN Mailbox direction register (CANMD) bit definitions */ +struct CANMD_BITS { // bit description + Uint16 MD0:1; // 0 0 -> Tx 1 -> Rx + Uint16 MD1:1; // 1 0 -> Tx 1 -> Rx + Uint16 MD2:1; // 2 0 -> Tx 1 -> Rx + Uint16 MD3:1; // 3 0 -> Tx 1 -> Rx + Uint16 MD4:1; // 4 0 -> Tx 1 -> Rx + Uint16 MD5:1; // 5 0 -> Tx 1 -> Rx + Uint16 MD6:1; // 6 0 -> Tx 1 -> Rx + Uint16 MD7:1; // 7 0 -> Tx 1 -> Rx + Uint16 MD8:1; // 8 0 -> Tx 1 -> Rx + Uint16 MD9:1; // 9 0 -> Tx 1 -> Rx + Uint16 MD10:1; // 10 0 -> Tx 1 -> Rx + Uint16 MD11:1; // 11 0 -> Tx 1 -> Rx + Uint16 MD12:1; // 12 0 -> Tx 1 -> Rx + Uint16 MD13:1; // 13 0 -> Tx 1 -> Rx + Uint16 MD14:1; // 14 0 -> Tx 1 -> Rx + Uint16 MD15:1; // 15 0 -> Tx 1 -> Rx + Uint16 MD16:1; // 16 0 -> Tx 1 -> Rx + Uint16 MD17:1; // 17 0 -> Tx 1 -> Rx + Uint16 MD18:1; // 18 0 -> Tx 1 -> Rx + Uint16 MD19:1; // 19 0 -> Tx 1 -> Rx + Uint16 MD20:1; // 20 0 -> Tx 1 -> Rx + Uint16 MD21:1; // 21 0 -> Tx 1 -> Rx + Uint16 MD22:1; // 22 0 -> Tx 1 -> Rx + Uint16 MD23:1; // 23 0 -> Tx 1 -> Rx + Uint16 MD24:1; // 24 0 -> Tx 1 -> Rx + Uint16 MD25:1; // 25 0 -> Tx 1 -> Rx + Uint16 MD26:1; // 26 0 -> Tx 1 -> Rx + Uint16 MD27:1; // 27 0 -> Tx 1 -> Rx + Uint16 MD28:1; // 28 0 -> Tx 1 -> Rx + Uint16 MD29:1; // 29 0 -> Tx 1 -> Rx + Uint16 MD30:1; // 30 0 -> Tx 1 -> Rx + Uint16 MD31:1; // 31 0 -> Tx 1 -> Rx + +}; + +/* Allow access to the bit fields or entire register */ +union CANMD_REG { + Uint32 all; + struct CANMD_BITS bit; +}; + +/* eCAN Transmit Request Set register (CANTRS) bit definitions */ +struct CANTRS_BITS { // bit description + Uint16 TRS0:1; // 0 TRS for Mailbox 0 + Uint16 TRS1:1; // 1 TRS for Mailbox 1 + Uint16 TRS2:1; // 2 TRS for Mailbox 2 + Uint16 TRS3:1; // 3 TRS for Mailbox 3 + Uint16 TRS4:1; // 4 TRS for Mailbox 4 + Uint16 TRS5:1; // 5 TRS for Mailbox 5 + Uint16 TRS6:1; // 6 TRS for Mailbox 6 + Uint16 TRS7:1; // 7 TRS for Mailbox 7 + Uint16 TRS8:1; // 8 TRS for Mailbox 8 + Uint16 TRS9:1; // 9 TRS for Mailbox 9 + Uint16 TRS10:1; // 10 TRS for Mailbox 10 + Uint16 TRS11:1; // 11 TRS for Mailbox 11 + Uint16 TRS12:1; // 12 TRS for Mailbox 12 + Uint16 TRS13:1; // 13 TRS for Mailbox 13 + Uint16 TRS14:1; // 14 TRS for Mailbox 14 + Uint16 TRS15:1; // 15 TRS for Mailbox 15 + Uint16 TRS16:1; // 16 TRS for Mailbox 16 + Uint16 TRS17:1; // 17 TRS for Mailbox 17 + Uint16 TRS18:1; // 18 TRS for Mailbox 18 + Uint16 TRS19:1; // 19 TRS for Mailbox 19 + Uint16 TRS20:1; // 20 TRS for Mailbox 20 + Uint16 TRS21:1; // 21 TRS for Mailbox 21 + Uint16 TRS22:1; // 22 TRS for Mailbox 22 + Uint16 TRS23:1; // 23 TRS for Mailbox 23 + Uint16 TRS24:1; // 24 TRS for Mailbox 24 + Uint16 TRS25:1; // 25 TRS for Mailbox 25 + Uint16 TRS26:1; // 26 TRS for Mailbox 26 + Uint16 TRS27:1; // 27 TRS for Mailbox 27 + Uint16 TRS28:1; // 28 TRS for Mailbox 28 + Uint16 TRS29:1; // 29 TRS for Mailbox 29 + Uint16 TRS30:1; // 30 TRS for Mailbox 30 + Uint16 TRS31:1; // 31 TRS for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANTRS_REG { + Uint32 all; + struct CANTRS_BITS bit; +}; + +/* eCAN Transmit Request Reset register (CANTRR) bit definitions */ +struct CANTRR_BITS { // bit description + Uint16 TRR0:1; // 0 TRR for Mailbox 0 + Uint16 TRR1:1; // 1 TRR for Mailbox 1 + Uint16 TRR2:1; // 2 TRR for Mailbox 2 + Uint16 TRR3:1; // 3 TRR for Mailbox 3 + Uint16 TRR4:1; // 4 TRR for Mailbox 4 + Uint16 TRR5:1; // 5 TRR for Mailbox 5 + Uint16 TRR6:1; // 6 TRR for Mailbox 6 + Uint16 TRR7:1; // 7 TRR for Mailbox 7 + Uint16 TRR8:1; // 8 TRR for Mailbox 8 + Uint16 TRR9:1; // 9 TRR for Mailbox 9 + Uint16 TRR10:1; // 10 TRR for Mailbox 10 + Uint16 TRR11:1; // 11 TRR for Mailbox 11 + Uint16 TRR12:1; // 12 TRR for Mailbox 12 + Uint16 TRR13:1; // 13 TRR for Mailbox 13 + Uint16 TRR14:1; // 14 TRR for Mailbox 14 + Uint16 TRR15:1; // 15 TRR for Mailbox 15 + Uint16 TRR16:1; // 16 TRR for Mailbox 16 + Uint16 TRR17:1; // 17 TRR for Mailbox 17 + Uint16 TRR18:1; // 18 TRR for Mailbox 18 + Uint16 TRR19:1; // 19 TRR for Mailbox 19 + Uint16 TRR20:1; // 20 TRR for Mailbox 20 + Uint16 TRR21:1; // 21 TRR for Mailbox 21 + Uint16 TRR22:1; // 22 TRR for Mailbox 22 + Uint16 TRR23:1; // 23 TRR for Mailbox 23 + Uint16 TRR24:1; // 24 TRR for Mailbox 24 + Uint16 TRR25:1; // 25 TRR for Mailbox 25 + Uint16 TRR26:1; // 26 TRR for Mailbox 26 + Uint16 TRR27:1; // 27 TRR for Mailbox 27 + Uint16 TRR28:1; // 28 TRR for Mailbox 28 + Uint16 TRR29:1; // 29 TRR for Mailbox 29 + Uint16 TRR30:1; // 30 TRR for Mailbox 30 + Uint16 TRR31:1; // 31 TRR for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANTRR_REG { + Uint32 all; + struct CANTRR_BITS bit; +}; + +/* eCAN Transmit Acknowledge register (CANTA) bit definitions */ +struct CANTA_BITS { // bit description + Uint16 TA0:1; // 0 TA for Mailbox 0 + Uint16 TA1:1; // 1 TA for Mailbox 1 + Uint16 TA2:1; // 2 TA for Mailbox 2 + Uint16 TA3:1; // 3 TA for Mailbox 3 + Uint16 TA4:1; // 4 TA for Mailbox 4 + Uint16 TA5:1; // 5 TA for Mailbox 5 + Uint16 TA6:1; // 6 TA for Mailbox 6 + Uint16 TA7:1; // 7 TA for Mailbox 7 + Uint16 TA8:1; // 8 TA for Mailbox 8 + Uint16 TA9:1; // 9 TA for Mailbox 9 + Uint16 TA10:1; // 10 TA for Mailbox 10 + Uint16 TA11:1; // 11 TA for Mailbox 11 + Uint16 TA12:1; // 12 TA for Mailbox 12 + Uint16 TA13:1; // 13 TA for Mailbox 13 + Uint16 TA14:1; // 14 TA for Mailbox 14 + Uint16 TA15:1; // 15 TA for Mailbox 15 + Uint16 TA16:1; // 16 TA for Mailbox 16 + Uint16 TA17:1; // 17 TA for Mailbox 17 + Uint16 TA18:1; // 18 TA for Mailbox 18 + Uint16 TA19:1; // 19 TA for Mailbox 19 + Uint16 TA20:1; // 20 TA for Mailbox 20 + Uint16 TA21:1; // 21 TA for Mailbox 21 + Uint16 TA22:1; // 22 TA for Mailbox 22 + Uint16 TA23:1; // 23 TA for Mailbox 23 + Uint16 TA24:1; // 24 TA for Mailbox 24 + Uint16 TA25:1; // 25 TA for Mailbox 25 + Uint16 TA26:1; // 26 TA for Mailbox 26 + Uint16 TA27:1; // 27 TA for Mailbox 27 + Uint16 TA28:1; // 28 TA for Mailbox 28 + Uint16 TA29:1; // 29 TA for Mailbox 29 + Uint16 TA30:1; // 30 TA for Mailbox 30 + Uint16 TA31:1; // 31 TA for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANTA_REG { + Uint32 all; + struct CANTA_BITS bit; +}; + +/* eCAN Transmit Abort Acknowledge register (CANAA) bit definitions */ +struct CANAA_BITS { // bit description + Uint16 AA0:1; // 0 AA for Mailbox 0 + Uint16 AA1:1; // 1 AA for Mailbox 1 + Uint16 AA2:1; // 2 AA for Mailbox 2 + Uint16 AA3:1; // 3 AA for Mailbox 3 + Uint16 AA4:1; // 4 AA for Mailbox 4 + Uint16 AA5:1; // 5 AA for Mailbox 5 + Uint16 AA6:1; // 6 AA for Mailbox 6 + Uint16 AA7:1; // 7 AA for Mailbox 7 + Uint16 AA8:1; // 8 AA for Mailbox 8 + Uint16 AA9:1; // 9 AA for Mailbox 9 + Uint16 AA10:1; // 10 AA for Mailbox 10 + Uint16 AA11:1; // 11 AA for Mailbox 11 + Uint16 AA12:1; // 12 AA for Mailbox 12 + Uint16 AA13:1; // 13 AA for Mailbox 13 + Uint16 AA14:1; // 14 AA for Mailbox 14 + Uint16 AA15:1; // 15 AA for Mailbox 15 + Uint16 AA16:1; // 16 AA for Mailbox 16 + Uint16 AA17:1; // 17 AA for Mailbox 17 + Uint16 AA18:1; // 18 AA for Mailbox 18 + Uint16 AA19:1; // 19 AA for Mailbox 19 + Uint16 AA20:1; // 20 AA for Mailbox 20 + Uint16 AA21:1; // 21 AA for Mailbox 21 + Uint16 AA22:1; // 22 AA for Mailbox 22 + Uint16 AA23:1; // 23 AA for Mailbox 23 + Uint16 AA24:1; // 24 AA for Mailbox 24 + Uint16 AA25:1; // 25 AA for Mailbox 25 + Uint16 AA26:1; // 26 AA for Mailbox 26 + Uint16 AA27:1; // 27 AA for Mailbox 27 + Uint16 AA28:1; // 28 AA for Mailbox 28 + Uint16 AA29:1; // 29 AA for Mailbox 29 + Uint16 AA30:1; // 30 AA for Mailbox 30 + Uint16 AA31:1; // 31 AA for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANAA_REG { + Uint32 all; + struct CANAA_BITS bit; +}; + +/* eCAN Received Message Pending register (CANRMP) bit definitions */ +struct CANRMP_BITS { // bit description + Uint16 RMP0:1; // 0 RMP for Mailbox 0 + Uint16 RMP1:1; // 1 RMP for Mailbox 1 + Uint16 RMP2:1; // 2 RMP for Mailbox 2 + Uint16 RMP3:1; // 3 RMP for Mailbox 3 + Uint16 RMP4:1; // 4 RMP for Mailbox 4 + Uint16 RMP5:1; // 5 RMP for Mailbox 5 + Uint16 RMP6:1; // 6 RMP for Mailbox 6 + Uint16 RMP7:1; // 7 RMP for Mailbox 7 + Uint16 RMP8:1; // 8 RMP for Mailbox 8 + Uint16 RMP9:1; // 9 RMP for Mailbox 9 + Uint16 RMP10:1; // 10 RMP for Mailbox 10 + Uint16 RMP11:1; // 11 RMP for Mailbox 11 + Uint16 RMP12:1; // 12 RMP for Mailbox 12 + Uint16 RMP13:1; // 13 RMP for Mailbox 13 + Uint16 RMP14:1; // 14 RMP for Mailbox 14 + Uint16 RMP15:1; // 15 RMP for Mailbox 15 + Uint16 RMP16:1; // 16 RMP for Mailbox 16 + Uint16 RMP17:1; // 17 RMP for Mailbox 17 + Uint16 RMP18:1; // 18 RMP for Mailbox 18 + Uint16 RMP19:1; // 19 RMP for Mailbox 19 + Uint16 RMP20:1; // 20 RMP for Mailbox 20 + Uint16 RMP21:1; // 21 RMP for Mailbox 21 + Uint16 RMP22:1; // 22 RMP for Mailbox 22 + Uint16 RMP23:1; // 23 RMP for Mailbox 23 + Uint16 RMP24:1; // 24 RMP for Mailbox 24 + Uint16 RMP25:1; // 25 RMP for Mailbox 25 + Uint16 RMP26:1; // 26 RMP for Mailbox 26 + Uint16 RMP27:1; // 27 RMP for Mailbox 27 + Uint16 RMP28:1; // 28 RMP for Mailbox 28 + Uint16 RMP29:1; // 29 RMP for Mailbox 29 + Uint16 RMP30:1; // 30 RMP for Mailbox 30 + Uint16 RMP31:1; // 31 RMP for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANRMP_REG { + Uint32 all; + struct CANRMP_BITS bit; +}; + +/* eCAN Received Message Lost register (CANRML) bit definitions */ +struct CANRML_BITS { // bit description + Uint16 RML0:1; // 0 RML for Mailbox 0 + Uint16 RML1:1; // 1 RML for Mailbox 1 + Uint16 RML2:1; // 2 RML for Mailbox 2 + Uint16 RML3:1; // 3 RML for Mailbox 3 + Uint16 RML4:1; // 4 RML for Mailbox 4 + Uint16 RML5:1; // 5 RML for Mailbox 5 + Uint16 RML6:1; // 6 RML for Mailbox 6 + Uint16 RML7:1; // 7 RML for Mailbox 7 + Uint16 RML8:1; // 8 RML for Mailbox 8 + Uint16 RML9:1; // 9 RML for Mailbox 9 + Uint16 RML10:1; // 10 RML for Mailbox 10 + Uint16 RML11:1; // 11 RML for Mailbox 11 + Uint16 RML12:1; // 12 RML for Mailbox 12 + Uint16 RML13:1; // 13 RML for Mailbox 13 + Uint16 RML14:1; // 14 RML for Mailbox 14 + Uint16 RML15:1; // 15 RML for Mailbox 15 + Uint16 RML16:1; // 16 RML for Mailbox 16 + Uint16 RML17:1; // 17 RML for Mailbox 17 + Uint16 RML18:1; // 18 RML for Mailbox 18 + Uint16 RML19:1; // 19 RML for Mailbox 19 + Uint16 RML20:1; // 20 RML for Mailbox 20 + Uint16 RML21:1; // 21 RML for Mailbox 21 + Uint16 RML22:1; // 22 RML for Mailbox 22 + Uint16 RML23:1; // 23 RML for Mailbox 23 + Uint16 RML24:1; // 24 RML for Mailbox 24 + Uint16 RML25:1; // 25 RML for Mailbox 25 + Uint16 RML26:1; // 26 RML for Mailbox 26 + Uint16 RML27:1; // 27 RML for Mailbox 27 + Uint16 RML28:1; // 28 RML for Mailbox 28 + Uint16 RML29:1; // 29 RML for Mailbox 29 + Uint16 RML30:1; // 30 RML for Mailbox 30 + Uint16 RML31:1; // 31 RML for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANRML_REG { + Uint32 all; + struct CANRML_BITS bit; +}; + +/* eCAN Remote Frame Pending register (CANRFP) bit definitions */ +struct CANRFP_BITS { // bit description + Uint16 RFP0:1; // 0 RFP for Mailbox 0 + Uint16 RFP1:1; // 1 RFP for Mailbox 1 + Uint16 RFP2:1; // 2 RFP for Mailbox 2 + Uint16 RFP3:1; // 3 RFP for Mailbox 3 + Uint16 RFP4:1; // 4 RFP for Mailbox 4 + Uint16 RFP5:1; // 5 RFP for Mailbox 5 + Uint16 RFP6:1; // 6 RFP for Mailbox 6 + Uint16 RFP7:1; // 7 RFP for Mailbox 7 + Uint16 RFP8:1; // 8 RFP for Mailbox 8 + Uint16 RFP9:1; // 9 RFP for Mailbox 9 + Uint16 RFP10:1; // 10 RFP for Mailbox 10 + Uint16 RFP11:1; // 11 RFP for Mailbox 11 + Uint16 RFP12:1; // 12 RFP for Mailbox 12 + Uint16 RFP13:1; // 13 RFP for Mailbox 13 + Uint16 RFP14:1; // 14 RFP for Mailbox 14 + Uint16 RFP15:1; // 15 RFP for Mailbox 15 + Uint16 RFP16:1; // 16 RFP for Mailbox 16 + Uint16 RFP17:1; // 17 RFP for Mailbox 17 + Uint16 RFP18:1; // 18 RFP for Mailbox 18 + Uint16 RFP19:1; // 19 RFP for Mailbox 19 + Uint16 RFP20:1; // 20 RFP for Mailbox 20 + Uint16 RFP21:1; // 21 RFP for Mailbox 21 + Uint16 RFP22:1; // 22 RFP for Mailbox 22 + Uint16 RFP23:1; // 23 RFP for Mailbox 23 + Uint16 RFP24:1; // 24 RFP for Mailbox 24 + Uint16 RFP25:1; // 25 RFP for Mailbox 25 + Uint16 RFP26:1; // 26 RFP for Mailbox 26 + Uint16 RFP27:1; // 27 RFP for Mailbox 27 + Uint16 RFP28:1; // 28 RFP for Mailbox 28 + Uint16 RFP29:1; // 29 RFP for Mailbox 29 + Uint16 RFP30:1; // 30 RFP for Mailbox 30 + Uint16 RFP31:1; // 31 RFP for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANRFP_REG { + Uint32 all; + struct CANRFP_BITS bit; +}; + +/* eCAN Global Acceptance Mask register (CANGAM) bit definitions */ +struct CANGAM_BITS { // bits description + Uint16 GAM150:16; // 15:0 Global acceptance mask bits 0-15 + Uint16 GAM2816:13; // 28:16 Global acceptance mask bits 16-28 + Uint16 rsvd:2; // 30:29 reserved + Uint16 AMI:1; // 31 AMI bit +}; + +/* Allow access to the bit fields or entire register */ +union CANGAM_REG { + Uint32 all; + struct CANGAM_BITS bit; +}; + + +/* eCAN Master Control register (CANMC) bit definitions */ +struct CANMC_BITS { // bits description + Uint16 MBNR:5; // 4:0 MBX # for CDR bit + Uint16 SRES:1; // 5 Soft reset + Uint16 STM:1; // 6 Self-test mode + Uint16 ABO:1; // 7 Auto bus-on + Uint16 CDR:1; // 8 Change data request + Uint16 WUBA:1; // 9 Wake-up on bus activity + Uint16 DBO:1; // 10 Data-byte order + Uint16 PDR:1; // 11 Power-down mode request + Uint16 CCR:1; // 12 Change configuration request + Uint16 SCB:1; // 13 SCC compatibility bit + Uint16 TCC:1; // 14 TSC MSB clear bit + Uint16 MBCC:1; // 15 TSC clear bit thru mailbox 16 + Uint16 SUSP:1; // 16 SUSPEND free/soft bit + Uint16 rsvd:15; // 31:17 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANMC_REG { + Uint32 all; + struct CANMC_BITS bit; +}; + +/* eCAN Bit -timing configuration register (CANBTC) bit definitions */ +struct CANBTC_BITS { // bits description + Uint16 TSEG2REG:3; // 2:0 TSEG2 register value + Uint16 TSEG1REG:4; // 6:3 TSEG1 register value + Uint16 SAM:1; // 7 Sample-point setting + Uint16 SJWREG:2; // 9:8 Synchroniztion Jump Width register value + Uint16 rsvd1:6; // 15:10 reserved + Uint16 BRPREG:8; // 23:16 Baudrate prescaler register value + Uint16 rsvd2:8; // 31:24 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANBTC_REG { + Uint32 all; + struct CANBTC_BITS bit; +}; + +/* eCAN Error & Status register (CANES) bit definitions */ +struct CANES_BITS { // bits description + Uint16 TM:1; // 0 Transmit Mode + Uint16 RM:1; // 1 Receive Mode + Uint16 rsvd1:1; // 2 reserved + Uint16 PDA:1; // 3 Power-down acknowledge + Uint16 CCE:1; // 4 Change Configuration Enable + Uint16 SMA:1; // 5 Suspend Mode Acknowledge + Uint16 rsvd2:10; // 15:6 reserved + Uint16 EW:1; // 16 Warning status + Uint16 EP:1; // 17 Error Passive status + Uint16 BO:1; // 18 Bus-off status + Uint16 ACKE:1; // 19 Acknowledge error + Uint16 SE:1; // 20 Stuff error + Uint16 CRCE:1; // 21 CRC error + Uint16 SA1:1; // 22 Stuck at Dominant error + Uint16 BE:1; // 23 Bit error + Uint16 FE:1; // 24 Framing error + Uint16 rsvd3:7; // 31:25 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANES_REG { + Uint32 all; + struct CANES_BITS bit; +}; + + +/* eCAN Transmit Error Counter register (CANTEC) bit definitions */ +struct CANTEC_BITS { // bits description + Uint16 TEC:8; // 7:0 TEC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANTEC_REG { + Uint32 all; + struct CANTEC_BITS bit; +}; + +/* eCAN Receive Error Counter register (CANREC) bit definitions */ +struct CANREC_BITS { // bits description + Uint16 REC:8; // 7:0 REC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANREC_REG { + Uint32 all; + struct CANREC_BITS bit; +}; + +/* eCAN Global Interrupt Flag 0 (CANGIF0) bit definitions */ +struct CANGIF0_BITS { // bits description + Uint16 MIV0:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF0:1; // 8 Warning level interrupt flag + Uint16 EPIF0:1; // 9 Error-passive interrupt flag + Uint16 BOIF0:1; // 10 Bus-off interrupt flag + Uint16 RMLIF0:1; // 11 Received message lost interrupt flag + Uint16 WUIF0:1; // 12 Wakeup interrupt flag + Uint16 WDIF0:1; // 13 Write denied interrupt flag + Uint16 AAIF0:1; // 14 Abort Ack interrupt flag + Uint16 GMIF0:1; // 15 Global MBX interrupt flag + Uint16 TCOF0:1; // 16 TSC Overflow flag + Uint16 MTOF0:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANGIF0_REG { + Uint32 all; + struct CANGIF0_BITS bit; +}; + +/* eCAN Global Interrupt Mask register (CANGIM) bit definitions */ +struct CANGIM_BITS { // bits description + Uint16 I0EN:1; // 0 Interrupt 0 enable + Uint16 I1EN:1; // 1 Interrupt 1 enable + Uint16 GIL:1; // 2 Global Interrupt Level + Uint16 rsvd1:5; // 7:3 reserved + Uint16 WLIM:1; // 8 Warning level interrupt mask + Uint16 EPIM:1; // 9 Error-passive interrupt mask + Uint16 BOIM:1; // 10 Bus-off interrupt mask + Uint16 RMLIM:1; // 11 Received message lost interrupt mask + Uint16 WUIM:1; // 12 Wakeup interrupt mask + Uint16 WDIM:1; // 13 Write denied interrupt mask + Uint16 AAIM:1; // 14 Abort Ack interrupt mask + Uint16 rsvd2:1; // 15 reserved + Uint16 TCOM:1; // 16 TSC overflow interrupt mask + Uint16 MTOM:1; // 17 MBX Timeout interrupt mask + Uint16 rsvd3:14; // 31:18 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANGIM_REG { + Uint32 all; + struct CANGIM_BITS bit; +}; + + +/* eCAN Global Interrupt Flag 1 (eCANGIF1) bit definitions */ +struct CANGIF1_BITS { // bits description + Uint16 MIV1:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF1:1; // 8 Warning level interrupt flag + Uint16 EPIF1:1; // 9 Error-passive interrupt flag + Uint16 BOIF1:1; // 10 Bus-off interrupt flag + Uint16 RMLIF1:1; // 11 Received message lost interrupt flag + Uint16 WUIF1:1; // 12 Wakeup interrupt flag + Uint16 WDIF1:1; // 13 Write denied interrupt flag + Uint16 AAIF1:1; // 14 Abort Ack interrupt flag + Uint16 GMIF1:1; // 15 Global MBX interrupt flag + Uint16 TCOF1:1; // 16 TSC Overflow flag + Uint16 MTOF1:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANGIF1_REG { + Uint32 all; + struct CANGIF1_BITS bit; +}; + + +/* eCAN Mailbox Interrupt Mask register (CANMIM) bit definitions */ +struct CANMIM_BITS { // bit description + Uint16 MIM0:1; // 0 MIM for Mailbox 0 + Uint16 MIM1:1; // 1 MIM for Mailbox 1 + Uint16 MIM2:1; // 2 MIM for Mailbox 2 + Uint16 MIM3:1; // 3 MIM for Mailbox 3 + Uint16 MIM4:1; // 4 MIM for Mailbox 4 + Uint16 MIM5:1; // 5 MIM for Mailbox 5 + Uint16 MIM6:1; // 6 MIM for Mailbox 6 + Uint16 MIM7:1; // 7 MIM for Mailbox 7 + Uint16 MIM8:1; // 8 MIM for Mailbox 8 + Uint16 MIM9:1; // 9 MIM for Mailbox 9 + Uint16 MIM10:1; // 10 MIM for Mailbox 10 + Uint16 MIM11:1; // 11 MIM for Mailbox 11 + Uint16 MIM12:1; // 12 MIM for Mailbox 12 + Uint16 MIM13:1; // 13 MIM for Mailbox 13 + Uint16 MIM14:1; // 14 MIM for Mailbox 14 + Uint16 MIM15:1; // 15 MIM for Mailbox 15 + Uint16 MIM16:1; // 16 MIM for Mailbox 16 + Uint16 MIM17:1; // 17 MIM for Mailbox 17 + Uint16 MIM18:1; // 18 MIM for Mailbox 18 + Uint16 MIM19:1; // 19 MIM for Mailbox 19 + Uint16 MIM20:1; // 20 MIM for Mailbox 20 + Uint16 MIM21:1; // 21 MIM for Mailbox 21 + Uint16 MIM22:1; // 22 MIM for Mailbox 22 + Uint16 MIM23:1; // 23 MIM for Mailbox 23 + Uint16 MIM24:1; // 24 MIM for Mailbox 24 + Uint16 MIM25:1; // 25 MIM for Mailbox 25 + Uint16 MIM26:1; // 26 MIM for Mailbox 26 + Uint16 MIM27:1; // 27 MIM for Mailbox 27 + Uint16 MIM28:1; // 28 MIM for Mailbox 28 + Uint16 MIM29:1; // 29 MIM for Mailbox 29 + Uint16 MIM30:1; // 30 MIM for Mailbox 30 + Uint16 MIM31:1; // 31 MIM for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANMIM_REG { + Uint32 all; + struct CANMIM_BITS bit; +}; + +/* eCAN Mailbox Interrupt Level register (CANMIL) bit definitions */ +struct CANMIL_BITS { // bit description + Uint16 MIL0:1; // 0 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL1:1; // 1 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL2:1; // 2 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL3:1; // 3 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL4:1; // 4 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL5:1; // 5 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL6:1; // 6 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL7:1; // 7 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL8:1; // 8 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL9:1; // 9 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL10:1; // 10 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL11:1; // 11 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL12:1; // 12 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL13:1; // 13 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL14:1; // 14 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL15:1; // 15 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL16:1; // 16 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL17:1; // 17 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL18:1; // 18 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL19:1; // 19 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL20:1; // 20 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL21:1; // 21 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL22:1; // 22 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL23:1; // 23 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL24:1; // 24 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL25:1; // 25 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL26:1; // 26 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL27:1; // 27 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL28:1; // 28 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL29:1; // 29 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL30:1; // 30 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL31:1; // 31 0 -> Int 9.5 1 -> Int 9.6 + +}; + +/* Allow access to the bit fields or entire register */ +union CANMIL_REG { + Uint32 all; + struct CANMIL_BITS bit; +}; + + +/* eCAN Overwrite Protection Control register (CANOPC) bit definitions */ +struct CANOPC_BITS { // bit description + Uint16 OPC0:1; // 0 OPC for Mailbox 0 + Uint16 OPC1:1; // 1 OPC for Mailbox 1 + Uint16 OPC2:1; // 2 OPC for Mailbox 2 + Uint16 OPC3:1; // 3 OPC for Mailbox 3 + Uint16 OPC4:1; // 4 OPC for Mailbox 4 + Uint16 OPC5:1; // 5 OPC for Mailbox 5 + Uint16 OPC6:1; // 6 OPC for Mailbox 6 + Uint16 OPC7:1; // 7 OPC for Mailbox 7 + Uint16 OPC8:1; // 8 OPC for Mailbox 8 + Uint16 OPC9:1; // 9 OPC for Mailbox 9 + Uint16 OPC10:1; // 10 OPC for Mailbox 10 + Uint16 OPC11:1; // 11 OPC for Mailbox 11 + Uint16 OPC12:1; // 12 OPC for Mailbox 12 + Uint16 OPC13:1; // 13 OPC for Mailbox 13 + Uint16 OPC14:1; // 14 OPC for Mailbox 14 + Uint16 OPC15:1; // 15 OPC for Mailbox 15 + Uint16 OPC16:1; // 16 OPC for Mailbox 16 + Uint16 OPC17:1; // 17 OPC for Mailbox 17 + Uint16 OPC18:1; // 18 OPC for Mailbox 18 + Uint16 OPC19:1; // 19 OPC for Mailbox 19 + Uint16 OPC20:1; // 20 OPC for Mailbox 20 + Uint16 OPC21:1; // 21 OPC for Mailbox 21 + Uint16 OPC22:1; // 22 OPC for Mailbox 22 + Uint16 OPC23:1; // 23 OPC for Mailbox 23 + Uint16 OPC24:1; // 24 OPC for Mailbox 24 + Uint16 OPC25:1; // 25 OPC for Mailbox 25 + Uint16 OPC26:1; // 26 OPC for Mailbox 26 + Uint16 OPC27:1; // 27 OPC for Mailbox 27 + Uint16 OPC28:1; // 28 OPC for Mailbox 28 + Uint16 OPC29:1; // 29 OPC for Mailbox 29 + Uint16 OPC30:1; // 30 OPC for Mailbox 30 + Uint16 OPC31:1; // 31 OPC for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANOPC_REG { + Uint32 all; + struct CANOPC_BITS bit; +}; + + +/* eCAN TX I/O Control Register (CANTIOC) bit definitions */ +struct CANTIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 TXFUNC:1; // 3 TXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANTIOC_REG { + Uint32 all; + struct CANTIOC_BITS bit; +}; + +/* eCAN RX I/O Control Register (CANRIOC) bit definitions */ +struct CANRIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 RXFUNC:1; // 3 RXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANRIOC_REG { + Uint32 all; + struct CANRIOC_BITS bit; +}; + + +/* eCAN Time-out Control register (CANTOC) bit definitions */ +struct CANTOC_BITS { // bit description + Uint16 TOC0:1; // 0 TOC for Mailbox 0 + Uint16 TOC1:1; // 1 TOC for Mailbox 1 + Uint16 TOC2:1; // 2 TOC for Mailbox 2 + Uint16 TOC3:1; // 3 TOC for Mailbox 3 + Uint16 TOC4:1; // 4 TOC for Mailbox 4 + Uint16 TOC5:1; // 5 TOC for Mailbox 5 + Uint16 TOC6:1; // 6 TOC for Mailbox 6 + Uint16 TOC7:1; // 7 TOC for Mailbox 7 + Uint16 TOC8:1; // 8 TOC for Mailbox 8 + Uint16 TOC9:1; // 9 TOC for Mailbox 9 + Uint16 TOC10:1; // 10 TOC for Mailbox 10 + Uint16 TOC11:1; // 11 TOC for Mailbox 11 + Uint16 TOC12:1; // 12 TOC for Mailbox 12 + Uint16 TOC13:1; // 13 TOC for Mailbox 13 + Uint16 TOC14:1; // 14 TOC for Mailbox 14 + Uint16 TOC15:1; // 15 TOC for Mailbox 15 + Uint16 TOC16:1; // 16 TOC for Mailbox 16 + Uint16 TOC17:1; // 17 TOC for Mailbox 17 + Uint16 TOC18:1; // 18 TOC for Mailbox 18 + Uint16 TOC19:1; // 19 TOC for Mailbox 19 + Uint16 TOC20:1; // 20 TOC for Mailbox 20 + Uint16 TOC21:1; // 21 TOC for Mailbox 21 + Uint16 TOC22:1; // 22 TOC for Mailbox 22 + Uint16 TOC23:1; // 23 TOC for Mailbox 23 + Uint16 TOC24:1; // 24 TOC for Mailbox 24 + Uint16 TOC25:1; // 25 TOC for Mailbox 25 + Uint16 TOC26:1; // 26 TOC for Mailbox 26 + Uint16 TOC27:1; // 27 TOC for Mailbox 27 + Uint16 TOC28:1; // 28 TOC for Mailbox 28 + Uint16 TOC29:1; // 29 TOC for Mailbox 29 + Uint16 TOC30:1; // 30 TOC for Mailbox 30 + Uint16 TOC31:1; // 31 TOC for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANTOC_REG { + Uint32 all; + struct CANTOC_BITS bit; +}; + + +/* eCAN Time-out Status register (CANTOS) bit definitions */ +struct CANTOS_BITS { // bit description + Uint16 TOS0:1; // 0 TOS for Mailbox 0 + Uint16 TOS1:1; // 1 TOS for Mailbox 1 + Uint16 TOS2:1; // 2 TOS for Mailbox 2 + Uint16 TOS3:1; // 3 TOS for Mailbox 3 + Uint16 TOS4:1; // 4 TOS for Mailbox 4 + Uint16 TOS5:1; // 5 TOS for Mailbox 5 + Uint16 TOS6:1; // 6 TOS for Mailbox 6 + Uint16 TOS7:1; // 7 TOS for Mailbox 7 + Uint16 TOS8:1; // 8 TOS for Mailbox 8 + Uint16 TOS9:1; // 9 TOS for Mailbox 9 + Uint16 TOS10:1; // 10 TOS for Mailbox 10 + Uint16 TOS11:1; // 11 TOS for Mailbox 11 + Uint16 TOS12:1; // 12 TOS for Mailbox 12 + Uint16 TOS13:1; // 13 TOS for Mailbox 13 + Uint16 TOS14:1; // 14 TOS for Mailbox 14 + Uint16 TOS15:1; // 15 TOS for Mailbox 15 + Uint16 TOS16:1; // 16 TOS for Mailbox 16 + Uint16 TOS17:1; // 17 TOS for Mailbox 17 + Uint16 TOS18:1; // 18 TOS for Mailbox 18 + Uint16 TOS19:1; // 19 TOS for Mailbox 19 + Uint16 TOS20:1; // 20 TOS for Mailbox 20 + Uint16 TOS21:1; // 21 TOS for Mailbox 21 + Uint16 TOS22:1; // 22 TOS for Mailbox 22 + Uint16 TOS23:1; // 23 TOS for Mailbox 23 + Uint16 TOS24:1; // 24 TOS for Mailbox 24 + Uint16 TOS25:1; // 25 TOS for Mailbox 25 + Uint16 TOS26:1; // 26 TOS for Mailbox 26 + Uint16 TOS27:1; // 27 TOS for Mailbox 27 + Uint16 TOS28:1; // 28 TOS for Mailbox 28 + Uint16 TOS29:1; // 29 TOS for Mailbox 29 + Uint16 TOS30:1; // 30 TOS for Mailbox 30 + Uint16 TOS31:1; // 31 TOS for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANTOS_REG { + Uint32 all; + struct CANTOS_BITS bit; +}; + +/**************************************/ +/* eCAN Control & Status register file */ +/**************************************/ + +struct ECAN_REGS { + union CANME_REG CANME; // Mailbox Enable + union CANMD_REG CANMD; // Mailbox Direction + union CANTRS_REG CANTRS; // Transmit Request Set + union CANTRR_REG CANTRR; // Transmit Request Reset + union CANTA_REG CANTA; // Transmit Acknowledge + union CANAA_REG CANAA; // Abort Acknowledge + union CANRMP_REG CANRMP; // Received Message Pending + union CANRML_REG CANRML; // Received Message Lost + union CANRFP_REG CANRFP; // Remote Frame Pending + union CANGAM_REG CANGAM; // Global Acceptance Mask + union CANMC_REG CANMC; // Master Control + union CANBTC_REG CANBTC; // Bit Timing + union CANES_REG CANES; // Error Status + union CANTEC_REG CANTEC; // Transmit Error Counter + union CANREC_REG CANREC; // Receive Error Counter + union CANGIF0_REG CANGIF0; // Global Interrupt Flag 0 + union CANGIM_REG CANGIM; // Global Interrupt Mask 0 + union CANGIF1_REG CANGIF1; // Global Interrupt Flag 1 + union CANMIM_REG CANMIM; // Mailbox Interrupt Mask + union CANMIL_REG CANMIL; // Mailbox Interrupt Level + union CANOPC_REG CANOPC; // Overwrite Protection Control + union CANTIOC_REG CANTIOC; // TX I/O Control + union CANRIOC_REG CANRIOC; // RX I/O Control + Uint32 CANTSC; // Time-stamp counter + union CANTOC_REG CANTOC; // Time-out Control + union CANTOS_REG CANTOS; // Time-out Status + +}; + +/* --------------------------------------------------- */ +/* eCAN Mailbox Registers */ +/* ----------------------------------------------------*/ + +/* eCAN Message ID (MSGID) bit definitions */ +struct CANMSGID_BITS { // bits description + Uint16 EXTMSGID_L:16; // 0:15 + Uint16 EXTMSGID_H:2; // 16:17 + Uint16 STDMSGID:11; // 18:28 + Uint16 AAM:1; // 29 + Uint16 AME:1; // 30 + Uint16 IDE:1; // 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANMSGID_REG { + Uint32 all; + struct CANMSGID_BITS bit; +}; + +/* eCAN Message Control Register (MSGCTRL) bit definitions */ +struct CANMSGCTRL_BITS { // bits description + Uint16 DLC:4; // 0:3 + Uint16 RTR:1; // 4 + Uint16 rsvd1:3; // 7:5 reserved + Uint16 TPL:5; // 12:8 + Uint16 rsvd2:3; // 15:13 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANMSGCTRL_REG { + Uint32 all; + struct CANMSGCTRL_BITS bit; +}; + +/* eCAN Message Data Register low (MDR_L) word definitions */ +struct CANMDL_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +/* eCAN Message Data Register low (MDR_L) byte definitions */ +struct CANMDL_BYTES { // bits description + Uint16 BYTE3:8; // 31:24 + Uint16 BYTE2:8; // 23:16 + Uint16 BYTE1:8; // 15:8 + Uint16 BYTE0:8; // 7:0 +}; + + +/* Allow access to the bit fields or entire register */ + +union CANMDL_REG { + Uint32 all; + struct CANMDL_WORDS word; + struct CANMDL_BYTES byte; +}; + + + +/* eCAN Message Data Register high (MDR_H) word definitions */ +struct CANMDH_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +/* eCAN Message Data Register low (MDR_H) byte definitions */ +struct CANMDH_BYTES { // bits description + Uint16 BYTE7:8; // 63:56 + Uint16 BYTE6:8; // 55:48 + Uint16 BYTE5:8; // 47:40 + Uint16 BYTE4:8; // 39:32 +}; + +/* Allow access to the bit fields or entire register */ +union CANMDH_REG { + Uint32 all; + struct CANMDH_WORDS word; + struct CANMDH_BYTES byte; +}; + + +struct MBOX { + union CANMSGID_REG MSGID; + union CANMSGCTRL_REG MSGCTRL; + union CANMDL_REG MDL; + union CANMDH_REG MDH; +}; + +/**************************************/ +/* eCAN Mailboxes */ +/**************************************/ + +struct ECAN_MBOXES { + struct MBOX MBOX0; + struct MBOX MBOX1; + struct MBOX MBOX2; + struct MBOX MBOX3; + struct MBOX MBOX4; + struct MBOX MBOX5; + struct MBOX MBOX6; + struct MBOX MBOX7; + struct MBOX MBOX8; + struct MBOX MBOX9; + struct MBOX MBOX10; + struct MBOX MBOX11; + struct MBOX MBOX12; + struct MBOX MBOX13; + struct MBOX MBOX14; + struct MBOX MBOX15; + struct MBOX MBOX16; + struct MBOX MBOX17; + struct MBOX MBOX18; + struct MBOX MBOX19; + struct MBOX MBOX20; + struct MBOX MBOX21; + struct MBOX MBOX22; + struct MBOX MBOX23; + struct MBOX MBOX24; + struct MBOX MBOX25; + struct MBOX MBOX26; + struct MBOX MBOX27; + struct MBOX MBOX28; + struct MBOX MBOX29; + struct MBOX MBOX30; + struct MBOX MBOX31; +}; + +/* eCAN Local Acceptance Mask (LAM) bit definitions */ +struct CANLAM_BITS { // bits description + Uint16 LAM_L:16; // 0:15 + Uint16 LAM_H:13; // 16:28 + Uint16 rsvd1:2; // 29:30 reserved + Uint16 LAMI:1; // 31 +}; + +/* Allow access to the bit fields or entire register */ +union CANLAM_REG { + Uint32 all; + struct CANLAM_BITS bit; +}; + + +/**************************************/ +/* eCAN Local Acceptance Masks */ +/**************************************/ + +/* eCAN LAM File */ +struct LAM_REGS { + union CANLAM_REG LAM0; + union CANLAM_REG LAM1; + union CANLAM_REG LAM2; + union CANLAM_REG LAM3; + union CANLAM_REG LAM4; + union CANLAM_REG LAM5; + union CANLAM_REG LAM6; + union CANLAM_REG LAM7; + union CANLAM_REG LAM8; + union CANLAM_REG LAM9; + union CANLAM_REG LAM10; + union CANLAM_REG LAM11; + union CANLAM_REG LAM12; + union CANLAM_REG LAM13; + union CANLAM_REG LAM14; + union CANLAM_REG LAM15; + union CANLAM_REG LAM16; + union CANLAM_REG LAM17; + union CANLAM_REG LAM18; + union CANLAM_REG LAM19; + union CANLAM_REG LAM20; + union CANLAM_REG LAM21; + union CANLAM_REG LAM22; + union CANLAM_REG LAM23; + union CANLAM_REG LAM24; + union CANLAM_REG LAM25; + union CANLAM_REG LAM26; + union CANLAM_REG LAM27; + union CANLAM_REG LAM28; + union CANLAM_REG LAM29; + union CANLAM_REG LAM30; + union CANLAM_REG LAM31; +}; + +/* Mailbox MOTS File */ + +struct MOTS_REGS { + Uint32 MOTS0; + Uint32 MOTS1; + Uint32 MOTS2; + Uint32 MOTS3; + Uint32 MOTS4; + Uint32 MOTS5; + Uint32 MOTS6; + Uint32 MOTS7; + Uint32 MOTS8; + Uint32 MOTS9; + Uint32 MOTS10; + Uint32 MOTS11; + Uint32 MOTS12; + Uint32 MOTS13; + Uint32 MOTS14; + Uint32 MOTS15; + Uint32 MOTS16; + Uint32 MOTS17; + Uint32 MOTS18; + Uint32 MOTS19; + Uint32 MOTS20; + Uint32 MOTS21; + Uint32 MOTS22; + Uint32 MOTS23; + Uint32 MOTS24; + Uint32 MOTS25; + Uint32 MOTS26; + Uint32 MOTS27; + Uint32 MOTS28; + Uint32 MOTS29; + Uint32 MOTS30; + Uint32 MOTS31; +}; + +/* Mailbox MOTO File */ + +struct MOTO_REGS { + Uint32 MOTO0; + Uint32 MOTO1; + Uint32 MOTO2; + Uint32 MOTO3; + Uint32 MOTO4; + Uint32 MOTO5; + Uint32 MOTO6; + Uint32 MOTO7; + Uint32 MOTO8; + Uint32 MOTO9; + Uint32 MOTO10; + Uint32 MOTO11; + Uint32 MOTO12; + Uint32 MOTO13; + Uint32 MOTO14; + Uint32 MOTO15; + Uint32 MOTO16; + Uint32 MOTO17; + Uint32 MOTO18; + Uint32 MOTO19; + Uint32 MOTO20; + Uint32 MOTO21; + Uint32 MOTO22; + Uint32 MOTO23; + Uint32 MOTO24; + Uint32 MOTO25; + Uint32 MOTO26; + Uint32 MOTO27; + Uint32 MOTO28; + Uint32 MOTO29; + Uint32 MOTO30; + Uint32 MOTO31; +}; + + +//--------------------------------------------------------------------------- +// eCAN External References & Function Declarations: +// +extern volatile struct ECAN_REGS ECanaRegs; +extern volatile struct ECAN_MBOXES ECanaMboxes; +extern volatile struct LAM_REGS ECanaLAMRegs; +extern volatile struct MOTO_REGS ECanaMOTORegs; +extern volatile struct MOTS_REGS ECanaMOTSRegs; + +extern volatile struct ECAN_REGS ECanbRegs; +extern volatile struct ECAN_MBOXES ECanbMboxes; +extern volatile struct LAM_REGS ECanbLAMRegs; +extern volatile struct MOTO_REGS ECanbMOTORegs; +extern volatile struct MOTS_REGS ECanbMOTSRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAN.H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_ECap.h b/v120/DSP2833x_headers/include/DSP2833x_ECap.h new file mode 100644 index 0000000..b82bd7f --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_ECap.h @@ -0,0 +1,151 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:07 $ +//########################################################################### +// +// FILE: DSP2833x_ECap.h +// +// TITLE: DSP2833x Enhanced Capture Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_ECAP_H +#define DSP2833x_ECAP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +//---------------------------------------------------- +// Capture control register 1 bit definitions */ +struct ECCTL1_BITS { // bits description + Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select + Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 + Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select + Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 + Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select + Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 + Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select + Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 + Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap Event + Uint16 PRESCALE:5; // 13:9 Event Filter prescale select + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union ECCTL1_REG { + Uint16 all; + struct ECCTL1_BITS bit; +}; + + +// In V1.1 the STOPVALUE bit field was changed to +// STOP_WRAP. This correlated to a silicon change from +// F2833x Rev 0 to Rev A. +//---------------------------------------------------- +// Capture control register 2 bit definitions */ +struct ECCTL2_BITS { // bits description + Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot + Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous + Uint16 REARM:1; // 3 One-shot re-arm + Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop + Uint16 SYNCI_EN:1; // 5 Counter sync-in select + Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode + Uint16 SWSYNC:1; // 8 SW forced counter sync + Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select + Uint16 APWMPOL:1; // 10 APWM output polarity select + Uint16 rsvd1:5; // 15:11 +}; + + +union ECCTL2_REG { + Uint16 all; + struct ECCTL2_BITS bit; +}; + + +//---------------------------------------------------- +// ECAP interrupt enable register bit definitions */ +struct ECEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable + Uint16 rsvd2:8; // 15:8 reserved +}; + + +union ECEINT_REG { + Uint16 all; + struct ECEINT_BITS bit; +}; + +//---------------------------------------------------- +// ECAP interrupt flag register bit definitions */ +struct ECFLG_BITS { // bits description + Uint16 INT:1; // 0 Global Flag + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Flag + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Flag + Uint16 rsvd2:8; // 15:8 reserved +}; + + +union ECFLG_REG { + Uint16 all; + struct ECFLG_BITS bit; +}; + + +//---------------------------------------------------- + +struct ECAP_REGS { + Uint32 TSCTR; // Time stamp counter + Uint32 CTRPHS; // Counter phase + Uint32 CAP1; // Capture 1 + Uint32 CAP2; // Capture 2 + Uint32 CAP3; // Capture 3 + Uint32 CAP4; // Capture 4 + Uint16 rsvd1[8]; // reserved + union ECCTL1_REG ECCTL1; // Capture Control Reg 1 + union ECCTL2_REG ECCTL2; // Capture Control Reg 2 + union ECEINT_REG ECEINT; // ECAP interrupt enable + union ECFLG_REG ECFLG; // ECAP interrupt flags + union ECFLG_REG ECCLR; // ECAP interrupt clear + union ECEINT_REG ECFRC; // ECAP interrupt force + Uint16 rsvd2[6]; // reserved +}; + + + + +//--------------------------------------------------------------------------- +// GPI/O External References & Function Declarations: +// +extern volatile struct ECAP_REGS ECap1Regs; +extern volatile struct ECAP_REGS ECap2Regs; +extern volatile struct ECAP_REGS ECap3Regs; +extern volatile struct ECAP_REGS ECap4Regs; +extern volatile struct ECAP_REGS ECap5Regs; +extern volatile struct ECAP_REGS ECap6Regs; + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAP_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/v120/DSP2833x_headers/include/DSP2833x_EPwm.h b/v120/DSP2833x_headers/include/DSP2833x_EPwm.h new file mode 100644 index 0000000..9195752 --- /dev/null +++ b/v120/DSP2833x_headers/include/DSP2833x_EPwm.h @@ -0,0 +1,423 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:10 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm.h +// +// TITLE: DSP2833x Enhanced PWM Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_EPWM_H +#define DSP2833x_EPWM_H + + +#ifdef __cplusplus +extern "C" { +#endif + +//---------------------------------------------------- +// Time base control register bit definitions */ +struct TBCTL_BITS { // bits description + Uint16 CTRMODE:2; // 1:0 Counter Mode + Uint16 PHSEN:1; // 2 Phase load enable + Uint16 PRDLD:1; // 3 Active period load + Uint16 SYNCOSEL:2; // 5:4 Sync output select + Uint16 SWFSYNC:1; // 6 Software force sync pulse + Uint16 HSPCLKDIV:3; // 9:7 High speed time pre-scale + Uint16 CLKDIV:3; // 12:10 Timebase clock pre-scale + Uint16 PHSDIR:1; // 13 Phase Direction + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union TBCTL_REG { + Uint16 all; + struct TBCTL_BITS bit; +}; + +//---------------------------------------------------- +// Time base status register bit definitions */ +struct TBSTS_BITS { // bits description + Uint16 CTRDIR:1; // 0 Counter direction status + Uint16 SYNCI:1; // 1 External input sync status + Uint16 CTRMAX:1; // 2 Counter max latched status + Uint16 rsvd1:13; // 15:3 reserved +}; + +union TBSTS_REG { + Uint16 all; + struct TBSTS_BITS bit; +}; + +//---------------------------------------------------- +// Compare control register bit definitions */ +struct CMPCTL_BITS { // bits description + Uint16 LOADAMODE:2; // 0:1 Active compare A + Uint16 LOADBMODE:2; // 3:2 Active compare B + Uint16 SHDWAMODE:1; // 4 Compare A block operating mode + Uint16 rsvd1:1; // 5 reserved + Uint16 SHDWBMODE:1; // 6 Compare B block operating mode + Uint16 rsvd2:1; // 7 reserved + Uint16 SHDWAFULL:1; // 8 Compare A Shadow registers full Status + Uint16 SHDWBFULL:1; // 9 Compare B Shadow registers full Status + Uint16 rsvd3:6; // 15:10 reserved +}; + + +union CMPCTL_REG { + Uint16 all; + struct CMPCTL_BITS bit; +}; + +//---------------------------------------------------- +// Action qualifier register bit definitions */ +struct AQCTL_BITS { // bits description + Uint16 ZRO:2; // 1:0 Action Counter = Zero + Uint16 PRD:2; // 3:2 Action Counter = Period + Uint16 CAU:2; // 5:4 Action Counter = Compare A up + Uint16 CAD:2; // 7:6 Action Counter = Compare A down + Uint16 CBU:2; // 9:8 Action Counter = Compare B up + Uint16 CBD:2; // 11:10 Action Counter = Compare B down + Uint16 rsvd:4; // 15:12 reserved +}; + +union AQCTL_REG { + Uint16 all; + struct AQCTL_BITS bit; +}; + +//---------------------------------------------------- +// Action qualifier SW force register bit definitions */ +struct AQSFRC_BITS { // bits description + Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A invoked + Uint16 OTSFA:1; // 2 One-time SW Force A output + Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B invoked + Uint16 OTSFB:1; // 5 One-time SW Force A output + Uint16 RLDCSF:2; // 7:6 Reload from Shadow options + Uint16 rsvd1:8; // 15:8 reserved +}; + +union AQSFRC_REG { + Uint16 all; + struct AQSFRC_BITS bit; +}; + +//---------------------------------------------------- +// Action qualifier continuous SW force register bit definitions */ +struct AQCSFRC_BITS { // bits description + Uint16 CSFA:2; // 1:0 Continuous Software Force on output A + Uint16 CSFB:2; // 3:2 Continuous Software Force on output B + Uint16 rsvd1:12; // 15:4 reserved +}; + +union AQCSFRC_REG { + Uint16 all; + struct AQCSFRC_BITS bit; +}; + + +// As of version 1.1 +// Changed the MODE bit-field to OUT_MODE +// Added the bit-field IN_MODE +// This corresponds to changes in silicon as of F2833x devices +// Rev A silicon. +//---------------------------------------------------- +// Dead-band generator control register bit definitions +struct DBCTL_BITS { // bits description + Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control + Uint16 POLSEL:2; // 3:2 Polarity Select Control + Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control + Uint16 rsvd1:10; // 15:4 reserved +}; + +union DBCTL_REG { + Uint16 all; + struct DBCTL_BITS bit; +}; + + +//---------------------------------------------------- +// Trip zone select register bit definitions +struct TZSEL_BITS { // bits description + Uint16 CBC1:1; // 0 TZ1 CBC select + Uint16 CBC2:1; // 1 TZ2 CBC select + Uint16 CBC3:1; // 2 TZ3 CBC select + Uint16 CBC4:1; // 3 TZ4 CBC select + Uint16 CBC5:1; // 4 TZ5 CBC select + Uint16 CBC6:1; // 5 TZ6 CBC select + Uint16 rsvd1:2; // 7:6 reserved + Uint16 OSHT1:1; // 8 One-shot TZ1 select + Uint16 OSHT2:1; // 9 One-shot TZ2 select + Uint16 OSHT3:1; // 10 One-shot TZ3 select + Uint16 OSHT4:1; // 11 One-shot TZ4 select + Uint16 OSHT5:1; // 12 One-shot TZ5 select + Uint16 OSHT6:1; // 13 One-shot TZ6 select + Uint16 rsvd2:2; // 15:14 reserved +}; + +union TZSEL_REG { + Uint16 all; + struct TZSEL_BITS bit; +}; + + +//---------------------------------------------------- +// Trip zone control register bit definitions */ +struct TZCTL_BITS { // bits description + Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA + Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB + Uint16 rsvd:12; // 15:4 reserved +}; + +union TZCTL_REG { + Uint16 all; + struct TZCTL_BITS bit; +}; + + +//---------------------------------------------------- +// Trip zone control register bit definitions */ +struct TZEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable + Uint16 OST:1; // 2 Trip Zones One Shot Int Enable + Uint16 rsvd2:13; // 15:3 reserved +}; + + +union TZEINT_REG { + Uint16 all; + struct TZEINT_BITS bit; +}; + + +//---------------------------------------------------- +// Trip zone flag register bit definitions */ +struct TZFLG_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFLG_REG { + Uint16 all; + struct TZFLG_BITS bit; +}; + +//---------------------------------------------------- +// Trip zone flag clear register bit definitions */ +struct TZCLR_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZCLR_REG { + Uint16 all; + struct TZCLR_BITS bit; +}; + +//---------------------------------------------------- +// Trip zone flag force register bit definitions */ +struct TZFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFRC_REG { + Uint16 all; + struct TZFRC_BITS bit; +}; + +//---------------------------------------------------- +// Event trigger select register bit definitions */ +struct ETSEL_BITS { // bits description + Uint16 INTSEL:3; // 2:0 EPWMxINTn Select + Uint16 INTEN:1; // 3 EPWMxINTn Enable + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCASEL:3; // 10:8 Start of conversion A Select + Uint16 SOCAEN:1; // 11 Start of conversion A Enable + Uint16 SOCBSEL:3; // 14:12 Start of conversion B Select + Uint16 SOCBEN:1; // 15 Start of conversion B Enable +}; + +union ETSEL_REG { + Uint16 all; + struct ETSEL_BITS bit; +}; + + +//---------------------------------------------------- +// Event trigger pre-scale register bit definitions */ +struct ETPS_BITS { // bits description + Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select + Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select + Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register + Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select + Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter Register +}; + +union ETPS_REG { + Uint16 all; + struct ETPS_BITS bit; +}; + +//---------------------------------------------------- +// Event trigger Flag register bit definitions */ +struct ETFLG_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Flag + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Flag + Uint16 SOCB:1; // 3 EPWMxSOCB Flag + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFLG_REG { + Uint16 all; + struct ETFLG_BITS bit; +}; + + +//---------------------------------------------------- +// Event trigger Clear register bit definitions */ +struct ETCLR_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Clear + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Clear + Uint16 SOCB:1; // 3 EPWMxSOCB Clear + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETCLR_REG { + Uint16 all; + struct ETCLR_BITS bit; +}; + +//---------------------------------------------------- +// Event trigger Force register bit definitions */ +struct ETFRC_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Force + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Force + Uint16 SOCB:1; // 3 EPWMxSOCB Force + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFRC_REG { + Uint16 all; + struct ETFRC_BITS bit; +}; +//---------------------------------------------------- +// PWM chopper control register bit definitions */ +struct PCCTL_BITS { // bits description + Uint16 CHPEN:1; // 0 PWM chopping enable + Uint16 OSHTWTH:4; // 4:1 One-shot pulse width + Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency + Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle + Uint16 rsvd1:5; // 15:11 reserved +}; + + +union PCCTL_REG { + Uint16 all; + struct PCCTL_BITS bit; +}; + +struct HRCNFG_BITS { // bits description + Uint16 EDGMODE:2; // 1:0 Edge Mode select Bits + Uint16 CTLMODE:1; // 2 Control mode Select Bit + Uint16 HRLOAD:1; // 3 Shadow mode Select Bit + Uint16 rsvd1:12; // 15:4 reserved +}; + +union HRCNFG_REG { + Uint16 all; + struct HRCNFG_BITS bit; +}; + + +struct TBPHS_HRPWM_REG { // bits description + Uint16 TBPHSHR; // 15:0 Extension register for HRPWM Phase (8 bits) + Uint16 TBPHS; // 31:16 Phase offset register +}; + +union TBPHS_HRPWM_GROUP { + Uint32 all; + struct TBPHS_HRPWM_REG half; +}; + +struct CMPA_HRPWM_REG { // bits description + Uint16 CMPAHR; // 15:0 Extension register for HRPWM compare (8 bits) + Uint16 CMPA; // 31:16 Compare A reg +}; + +union CMPA_HRPWM_GROUP { + Uint32 all; + struct CMPA_HRPWM_REG half; +}; + + +struct EPWM_REGS { + union TBCTL_REG TBCTL; // + union TBSTS_REG TBSTS; // + union TBPHS_HRPWM_GROUP TBPHS; // Union of TBPHS:TBPHSHR + Uint16 TBCTR; // Counter + Uint16 TBPRD; // Period register set + Uint16 rsvd1; // + union CMPCTL_REG CMPCTL; // Compare control + union CMPA_HRPWM_GROUP CMPA; // Union of CMPA:CMPAHR + Uint16 CMPB; // Compare B reg + union AQCTL_REG AQCTLA; // Action qual output A + union AQCTL_REG AQCTLB; // Action qual output B + union AQSFRC_REG AQSFRC; // Action qual SW force + union AQCSFRC_REG AQCSFRC; // Action qualifier continuous SW force + union DBCTL_REG DBCTL; // Dead-band control + Uint16 DBRED; // Dead-band rising edge delay + Uint16 DBFED; // Dead-band falling edge delay + union TZSEL_REG TZSEL; // Trip zone select + Uint16 rsvd2; + union TZCTL_REG TZCTL; // Trip zone control + union TZEINT_REG TZEINT; // Trip zone interrupt enable + union TZFLG_REG TZFLG; // Trip zone interrupt flags + union TZCLR_REG TZCLR; // Trip zone clear + union TZFRC_REG TZFRC; // Trip zone force interrupt + union ETSEL_REG ETSEL; // Event trigger selection + union ETPS_REG ETPS; // Event trigger pre-scaler + union ETFLG_REG ETFLG; // Event trigger flags + union ETCLR_REG ETCLR; // Event trigger clear + union ETFRC_REG ETFRC; // Event trigger force + union PCCTL_REG PCCTL; // PWM chopper control + Uint16 rsvd3; // + union HRCNFG_REG HRCNFG; // HRPWM Config Reg +}; + + + +//--------------------------------------------------------------------------- +// External References & Function Declarations: +// +extern volatile struct EPWM_REGS EPwm1Regs; +extern volatile struct EPWM_REGS EPwm2Regs; +extern volatile struct EPWM_REGS EPwm3Regs; +extern volatile struct EPWM_REGS EPwm4Regs; +extern volatile struct EPWM_REGS EPwm5Regs; +extern volatile struct EPWM_REGS EPwm6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EPWM_H definition + +//=========================================================================== +// End of file. +//===========================================================================