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This commit is contained in:
147
v120/DSP2833x_common/include/DSP2833x_DefaultIsr.h
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147
v120/DSP2833x_common/include/DSP2833x_DefaultIsr.h
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@@ -0,0 +1,147 @@
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// TI File $Revision: /main/1 $
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// Checkin $Date: August 18, 2006 13:45:37 $
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//###########################################################################
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//
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// FILE: DSP2833x_DefaultIsr.h
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//
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// TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions.
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//
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//###########################################################################
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// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
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// $Release Date: August 1, 2008 $
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//###########################################################################
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#ifndef DSP2833x_DEFAULT_ISR_H
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#define DSP2833x_DEFAULT_ISR_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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//---------------------------------------------------------------------------
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// Default Interrupt Service Routine Declarations:
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//
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// The following function prototypes are for the
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// default ISR routines used with the default PIE vector table.
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// This default vector table is found in the DSP2833x_PieVect.h
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// file.
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//
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// Non-Peripheral Interrupts:
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interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1
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interrupt void INT14_ISR(void); // CPU-Timer2
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interrupt void DATALOG_ISR(void); // Datalogging interrupt
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interrupt void RTOSINT_ISR(void); // RTOS interrupt
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interrupt void EMUINT_ISR(void); // Emulation interrupt
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interrupt void NMI_ISR(void); // Non-maskable interrupt
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interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP
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interrupt void USER1_ISR(void); // User Defined trap 1
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interrupt void USER2_ISR(void); // User Defined trap 2
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interrupt void USER3_ISR(void); // User Defined trap 3
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interrupt void USER4_ISR(void); // User Defined trap 4
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interrupt void USER5_ISR(void); // User Defined trap 5
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interrupt void USER6_ISR(void); // User Defined trap 6
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interrupt void USER7_ISR(void); // User Defined trap 7
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interrupt void USER8_ISR(void); // User Defined trap 8
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interrupt void USER9_ISR(void); // User Defined trap 9
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interrupt void USER10_ISR(void); // User Defined trap 10
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interrupt void USER11_ISR(void); // User Defined trap 11
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interrupt void USER12_ISR(void); // User Defined trap 12
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// Group 1 PIE Interrupt Service Routines:
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interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR
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interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR
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interrupt void XINT1_ISR(void); // External interrupt 1
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interrupt void XINT2_ISR(void); // External interrupt 2
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interrupt void ADCINT_ISR(void); // ADC
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interrupt void TINT0_ISR(void); // Timer 0
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interrupt void WAKEINT_ISR(void); // WD
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// Group 2 PIE Interrupt Service Routines:
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interrupt void EPWM1_TZINT_ISR(void); // EPWM-1
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interrupt void EPWM2_TZINT_ISR(void); // EPWM-2
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interrupt void EPWM3_TZINT_ISR(void); // EPWM-3
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interrupt void EPWM4_TZINT_ISR(void); // EPWM-4
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interrupt void EPWM5_TZINT_ISR(void); // EPWM-5
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interrupt void EPWM6_TZINT_ISR(void); // EPWM-6
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// Group 3 PIE Interrupt Service Routines:
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interrupt void EPWM1_INT_ISR(void); // EPWM-1
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interrupt void EPWM2_INT_ISR(void); // EPWM-2
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interrupt void EPWM3_INT_ISR(void); // EPWM-3
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interrupt void EPWM4_INT_ISR(void); // EPWM-4
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interrupt void EPWM5_INT_ISR(void); // EPWM-5
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interrupt void EPWM6_INT_ISR(void); // EPWM-6
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// Group 4 PIE Interrupt Service Routines:
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interrupt void ECAP1_INT_ISR(void); // ECAP-1
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interrupt void ECAP2_INT_ISR(void); // ECAP-2
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interrupt void ECAP3_INT_ISR(void); // ECAP-3
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interrupt void ECAP4_INT_ISR(void); // ECAP-4
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interrupt void ECAP5_INT_ISR(void); // ECAP-5
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interrupt void ECAP6_INT_ISR(void); // ECAP-6
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// Group 5 PIE Interrupt Service Routines:
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interrupt void EQEP1_INT_ISR(void); // EQEP-1
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interrupt void EQEP2_INT_ISR(void); // EQEP-2
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// Group 6 PIE Interrupt Service Routines:
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interrupt void SPIRXINTA_ISR(void); // SPI-A
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interrupt void SPITXINTA_ISR(void); // SPI-A
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interrupt void MRINTA_ISR(void); // McBSP-A
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interrupt void MXINTA_ISR(void); // McBSP-A
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interrupt void MRINTB_ISR(void); // McBSP-B
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interrupt void MXINTB_ISR(void); // McBSP-B
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// Group 7 PIE Interrupt Service Routines:
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interrupt void DINTCH1_ISR(void); // DMA-Channel 1
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interrupt void DINTCH2_ISR(void); // DMA-Channel 2
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interrupt void DINTCH3_ISR(void); // DMA-Channel 3
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interrupt void DINTCH4_ISR(void); // DMA-Channel 4
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interrupt void DINTCH5_ISR(void); // DMA-Channel 5
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interrupt void DINTCH6_ISR(void); // DMA-Channel 6
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// Group 8 PIE Interrupt Service Routines:
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interrupt void I2CINT1A_ISR(void); // I2C-A
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interrupt void I2CINT2A_ISR(void); // I2C-A
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interrupt void SCIRXINTC_ISR(void); // SCI-C
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interrupt void SCITXINTC_ISR(void); // SCI-C
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// Group 9 PIE Interrupt Service Routines:
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interrupt void SCIRXINTA_ISR(void); // SCI-A
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interrupt void SCITXINTA_ISR(void); // SCI-A
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interrupt void SCIRXINTB_ISR(void); // SCI-B
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interrupt void SCITXINTB_ISR(void); // SCI-B
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interrupt void ECAN0INTA_ISR(void); // eCAN-A
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interrupt void ECAN1INTA_ISR(void); // eCAN-A
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interrupt void ECAN0INTB_ISR(void); // eCAN-B
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interrupt void ECAN1INTB_ISR(void); // eCAN-B
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// Group 10 PIE Interrupt Service Routines:
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// Group 11 PIE Interrupt Service Routines:
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// Group 12 PIE Interrupt Service Routines:
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interrupt void XINT3_ISR(void); // External interrupt 3
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interrupt void XINT4_ISR(void); // External interrupt 4
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interrupt void XINT5_ISR(void); // External interrupt 5
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interrupt void XINT6_ISR(void); // External interrupt 6
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interrupt void XINT7_ISR(void); // External interrupt 7
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interrupt void LVF_ISR(void); // Latched overflow flag
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interrupt void LUF_ISR(void); // Latched underflow flag
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// Catch-all for Reserved Locations For testing purposes:
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interrupt void PIE_RESERVED(void); // Reserved for test
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interrupt void rsvd_ISR(void); // for test
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interrupt void INT_NOTUSED_ISR(void); // for unused interrupts
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#ifdef __cplusplus
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}
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#endif /* extern "C" */
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#endif // end of DSP2833x_DEFAULT_ISR_H definition
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//===========================================================================
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// End of file.
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//===========================================================================
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81
v120/DSP2833x_common/include/DSP2833x_Dma_defines.h
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81
v120/DSP2833x_common/include/DSP2833x_Dma_defines.h
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@@ -0,0 +1,81 @@
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// TI File $Revision: /main/2 $
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// Checkin $Date: August 14, 2007 16:32:29 $
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//###########################################################################
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//
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// FILE: DSP2833x_Dma_defines.h
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//
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// TITLE: #defines used in DMA examples
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//
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//###########################################################################
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// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
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// $Release Date: August 1, 2008 $
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//###########################################################################
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#ifndef DSP2833x_DMA_DEFINES_H
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#define DSP2833x_DMA_DEFINES_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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// MODE
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//==========================
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// PERINTSEL bits
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#define DMA_SEQ1INT 1
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#define DMA_SEQ2INT 2
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#define DMA_XINT1 3
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#define DMA_XINT2 4
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#define DMA_XINT3 5
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#define DMA_XINT4 6
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#define DMA_XINT5 7
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#define DMA_XINT6 8
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#define DMA_XINT7 9
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#define DMA_XINT13 10
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#define DMA_TINT0 11
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#define DMA_TINT1 12
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#define DMA_TINT2 13
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#define DMA_MXEVTA 14
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#define DMA_MREVTA 15
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#define DMA_MXREVTB 16
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#define DMA_MREVTB 17
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// OVERINTE bit
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#define OVRFLOW_DISABLE 0x0
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#define OVEFLOW_ENABLE 0x1
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// PERINTE bit
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#define PERINT_DISABLE 0x0
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#define PERINT_ENABLE 0x1
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// CHINTMODE bits
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#define CHINT_BEGIN 0x0
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#define CHINT_END 0x1
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// ONESHOT bits
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#define ONESHOT_DISABLE 0x0
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#define ONESHOT_ENABLE 0x1
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// CONTINOUS bit
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#define CONT_DISABLE 0x0
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#define CONT_ENABLE 0x1
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// SYNCE bit
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#define SYNC_DISABLE 0x0
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#define SYNC_ENABLE 0x1
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// SYNCSEL bit
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#define SYNC_SRC 0x0
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#define SYNC_DST 0x1
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// DATASIZE bit
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#define SIXTEEN_BIT 0x0
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#define THIRTYTWO_BIT 0x1
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// CHINTE bit
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#define CHINT_DISABLE 0x0
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#define CHINT_ENABLE 0x1
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#ifdef __cplusplus
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}
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#endif /* extern "C" */
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#endif // - end of DSP2833x_EPWM_DEFINES_H
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//===========================================================================
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// End of file.
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//===========================================================================
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22
v120/DSP2833x_common/include/DSP28x_Project.h
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22
v120/DSP2833x_common/include/DSP28x_Project.h
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// TI File $Revision: /main/1 $
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// Checkin $Date: April 22, 2008 14:35:56 $
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//###########################################################################
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//
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// FILE: DSP28x_Project.h
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//
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// TITLE: DSP28x Project Headerfile and Examples Include File
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//
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//###########################################################################
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// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
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// $Release Date: August 1, 2008 $
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//###########################################################################
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#ifndef DSP28x_PROJECT_H
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#define DSP28x_PROJECT_H
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#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
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#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
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#endif // end of DSP28x_PROJECT_H definition
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42
v120/DSP2833x_common/source/DSP2833x_ADC_cal.asm
Normal file
42
v120/DSP2833x_common/source/DSP2833x_ADC_cal.asm
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;; TI File $Revision: /main/1 $
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;; Checkin $Date: July 30, 2007 10:29:23 $
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;;###########################################################################
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;;
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;; FILE: ADC_cal.asm
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;;
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;; TITLE: 2833x Boot Rom ADC Cal routine.
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;;
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;; Functions:
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;;
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;; _ADC_cal - Copies device specific calibration data into ADCREFSEL and ADCOFFTRIM registers
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;; Notes:
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;;
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;;###########################################################################
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;; $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
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;; $Release Date: August 1, 2008 $
|
||||
;;###########################################################################
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||||
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.def _ADC_cal
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.asg "0x711C", ADCREFSEL_LOC
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;-----------------------------------------------
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; _ADC_cal
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;-----------------------------------------------
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;-----------------------------------------------
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; This is the ADC cal routine.This routine is programmed into
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; reserved memory by the factory. 0xAAAA and 0xBBBB are place-
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; holders for calibration data.
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;The actual values programmed by TI are device specific.
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;
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; This function assumes that the clocks have been
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; enabled to the ADC module.
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;-----------------------------------------------
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||||
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.sect ".adc_cal"
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_ADC_cal
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MOVW DP, #ADCREFSEL_LOC >> 6
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MOV @28, #0xAAAA ; actual value may not be 0xAAAA
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MOV @29, #0xBBBB ; actual value may not be 0xBBBB
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LRETR
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;eof ----------
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65
v120/DSP2833x_common/source/DSP2833x_Adc.c
Normal file
65
v120/DSP2833x_common/source/DSP2833x_Adc.c
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@@ -0,0 +1,65 @@
|
||||
// TI File $Revision: /main/5 $
|
||||
// Checkin $Date: October 23, 2007 13:34:09 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Adc.c
|
||||
//
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// TITLE: DSP2833x ADC Initialization & Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
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||||
|
||||
#define ADC_usDELAY 5000L
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//---------------------------------------------------------------------------
|
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// InitAdc:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes ADC to a known state.
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||||
//
|
||||
void InitAdc(void)
|
||||
{
|
||||
extern void DSP28x_usDelay(Uint32 Count);
|
||||
|
||||
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// *IMPORTANT*
|
||||
// The ADC_cal function, which copies the ADC calibration values from TI reserved
|
||||
// OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs automatically in the
|
||||
// Boot ROM. If the boot ROM code is bypassed during the debug process, the
|
||||
// following function MUST be called for the ADC to function according
|
||||
// to specification. The clocks to the ADC MUST be enabled before calling this
|
||||
// function.
|
||||
// See the device data manual and/or the ADC Reference
|
||||
// Manual for more information.
|
||||
|
||||
EALLOW;
|
||||
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1;
|
||||
ADC_cal();
|
||||
EDIS;
|
||||
|
||||
|
||||
|
||||
|
||||
// To powerup the ADC the ADCENCLK bit should be set first to enable
|
||||
// clocks, followed by powering up the bandgap, reference circuitry, and ADC core.
|
||||
// Before the first conversion is performed a 5ms delay must be observed
|
||||
// after power up to give all analog circuits time to power up and settle
|
||||
|
||||
// Please note that for the delay function below to operate correctly the
|
||||
// CPU_RATE define statement in the DSP2833x_Examples.h file must
|
||||
// contain the correct CPU clock period in nanoseconds.
|
||||
|
||||
AdcRegs.ADCREFSEL.bit.REF_SEL = 0x01;
|
||||
AdcRegs.ADCTRL3.all = 0x00E0; // Power up bandgap/reference/ADC circuits
|
||||
DELAY_US(ADC_usDELAY); // Delay before converting ADC channels
|
||||
//pause_us(50L);
|
||||
}
|
||||
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
115
v120/DSP2833x_common/source/DSP2833x_CpuTimers.c
Normal file
115
v120/DSP2833x_common/source/DSP2833x_CpuTimers.c
Normal file
@@ -0,0 +1,115 @@
|
||||
// TI File $Revision: /main/3 $
|
||||
// Checkin $Date: March 16, 2007 08:37:30 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_CpuTimers.c
|
||||
//
|
||||
// TITLE: CPU 32-bit Timers Initialization & Support Functions.
|
||||
//
|
||||
// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and
|
||||
// other realtime operating systems.
|
||||
//
|
||||
// Do not use these two timers in your application if you ever plan
|
||||
// on integrating DSP-BIOS or another realtime OS.
|
||||
//
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
#include "DSP2833x_Device.h" // Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // Examples Include File
|
||||
|
||||
struct CPUTIMER_VARS CpuTimer0;
|
||||
|
||||
// CpuTimer 1 and CpuTimer2 are used by DSP BIOS & other RTOS. Comment out if using DSP BIOS or other RTOS.
|
||||
struct CPUTIMER_VARS CpuTimer1;
|
||||
struct CPUTIMER_VARS CpuTimer2;
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// InitCpuTimers:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes all three CPU timers to a known state.
|
||||
//
|
||||
void InitCpuTimers(void)
|
||||
{
|
||||
// CPU Timer 0
|
||||
// Initialize address pointers to respective timer registers:
|
||||
CpuTimer0.RegsAddr = &CpuTimer0Regs;
|
||||
// Initialize timer period to maximum:
|
||||
CpuTimer0Regs.PRD.all = 0xFFFFFFFF;
|
||||
// Initialize pre-scale counter to divide by 1 (SYSCLKOUT):
|
||||
CpuTimer0Regs.TPR.all = 0;
|
||||
CpuTimer0Regs.TPRH.all = 0;
|
||||
// Make sure timer is stopped:
|
||||
CpuTimer0Regs.TCR.bit.TSS = 1;
|
||||
// Reload all counter register with period value:
|
||||
CpuTimer0Regs.TCR.bit.TRB = 1;
|
||||
// Reset interrupt counters:
|
||||
CpuTimer0.InterruptCount = 0;
|
||||
|
||||
|
||||
// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS
|
||||
// Do not use these two timers if you ever plan on integrating
|
||||
// DSP-BIOS or another realtime OS.
|
||||
//
|
||||
// Initialize address pointers to respective timer registers:
|
||||
CpuTimer1.RegsAddr = &CpuTimer1Regs;
|
||||
CpuTimer2.RegsAddr = &CpuTimer2Regs;
|
||||
// Initialize timer period to maximum:
|
||||
CpuTimer1Regs.PRD.all = 0xFFFFFFFF;
|
||||
CpuTimer2Regs.PRD.all = 0xFFFFFFFF;
|
||||
// Initialize pre-scale counter to divide by 1 (SYSCLKOUT):
|
||||
CpuTimer1Regs.TPR.all = 0;
|
||||
CpuTimer1Regs.TPRH.all = 0;
|
||||
CpuTimer2Regs.TPR.all = 0;
|
||||
CpuTimer2Regs.TPRH.all = 0;
|
||||
// Make sure timers are stopped:
|
||||
CpuTimer1Regs.TCR.bit.TSS = 1;
|
||||
CpuTimer2Regs.TCR.bit.TSS = 1;
|
||||
// Reload all counter register with period value:
|
||||
CpuTimer1Regs.TCR.bit.TRB = 1;
|
||||
CpuTimer2Regs.TCR.bit.TRB = 1;
|
||||
// Reset interrupt counters:
|
||||
CpuTimer1.InterruptCount = 0;
|
||||
CpuTimer2.InterruptCount = 0;
|
||||
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// ConfigCpuTimer:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes the selected timer to the period specified
|
||||
// by the "Freq" and "Period" parameters. The "Freq" is entered as "MHz"
|
||||
// and the period in "uSeconds". The timer is held in the stopped state
|
||||
// after configuration.
|
||||
//
|
||||
void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period)
|
||||
{
|
||||
Uint32 temp;
|
||||
|
||||
// Initialize timer period:
|
||||
Timer->CPUFreqInMHz = Freq;
|
||||
Timer->PeriodInUSec = Period;
|
||||
temp = (long) (Freq * Period);
|
||||
Timer->RegsAddr->PRD.all = temp;
|
||||
|
||||
// Set pre-scale counter to divide by 1 (SYSCLKOUT):
|
||||
Timer->RegsAddr->TPR.all = 0;
|
||||
Timer->RegsAddr->TPRH.all = 0;
|
||||
|
||||
// Initialize timer control register:
|
||||
Timer->RegsAddr->TCR.bit.TSS = 1; // 1 = Stop timer, 0 = Start/Restart Timer
|
||||
Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer
|
||||
Timer->RegsAddr->TCR.bit.SOFT = 0;
|
||||
Timer->RegsAddr->TCR.bit.FREE = 0; // Timer Free Run Disabled
|
||||
Timer->RegsAddr->TCR.bit.TIE = 1; // 0 = Disable/ 1 = Enable Timer Interrupt
|
||||
|
||||
// Reset interrupt counter:
|
||||
Timer->InterruptCount = 0;
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
Reference in New Issue
Block a user