andrey
eb2ff79932
Фронты START/STOP обрабатываются при принятии командного слова CAN/RS, а окончание импульса обслуживается таймером. STOP имеет приоритет, перекрытие выходов исключено, сохранена защита от самопуска при включении. Загрузка параметров больше не подменяет живые команды нагрузки. Добавлены подробные русские комментарии во все собственные C-модули и основные заголовки, описание поведения и host-тест автомата. Обновлены файлы прошивки. Полная сборка TI 22.6.1.LTS и тесты пройдены; проверка на физической плате не выполнялась.
463 lines
12 KiB
C
463 lines
12 KiB
C
/* SPI EEPROM. Seeprom_read/write ðàçáèâàþò çàïðîñ íà ñòðàíèöû
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* è ñèíõðîííî æäóò spiSe2pFree. SPI-àâòîìàò ïðîäâèãàåò òàéìåð 2
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* êàæäûå 100 ìêñ. Ïðè çàïðåòå ýòîãî IRQ îæèäàíèå íå çàâåðøèòñÿ.
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* Òàéì-àóò â ñòàðîì äðàéâåðå îòñóòñòâóåò. Äèñêðåòû ÑÈÔÓ òåïåðü
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* íå çàâèñÿò îò òîãî, çàâåðøèëîñü ëè ýòî îæèäàíèå â main.
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*/
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#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
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#include "spise2p.h"
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//#include "pins.h"
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/* Instance the SPI bus serial EEPROM driver */
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static SPISE2P_DRV se2p=SPISE2P_DRV_DEFAULTS;
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/* Instance serial EEPROm data transfer structure */
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static SE2P_DATA writeData, readData;
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// Prototype statements for functions found within this file.
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interrupt void PRD_TICK(void);
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interrupt void cpu_timer2_isr(void);
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int ccc=0;
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/********************************************************************/
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/******* SPI bus Serial EEPROM driver Initialization routine ********/
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/********************************************************************/
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/* Áëîêèðóåò main äî çàâåðøåíèÿ ñòðàíèö. Çàïðåò IRQ îñòàíîâèò
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* SPI-àâòîìàò. CAN è òàéìåð ÑÈÔÓ äîëæíû ïðåðûâàòü ýòî îæèäàíèå.
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*/
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void Seeprom_write( unsigned int adres,
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unsigned int buf[],
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unsigned int size)
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{
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unsigned int len;
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CpuTimer2.InterruptCount=0;
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CpuTimer2Regs.TCR.all = 0x4020; // Use write-only instruction to set TSS bit = 0
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while(!spiSe2pFree(&se2p));
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size = (size / WORD_LEN) + (size % WORD_LEN);
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while(size)
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{
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len = PAGE_LEN - (adres % PAGE_LEN);
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if(len > size) len=size;
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writeData.dataPtr = buf;
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writeData.nrData = len;
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writeData.se2pAddr = adres * WORD_LEN;
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spiSe2pWrite(&se2p, &writeData);
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while(!spiSe2pFree(&se2p));
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buf += len;
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adres += len;
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size -= len;
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}
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CpuTimer2Regs.TCR.all = 0x4010; // Use write-only instruction to set TSS bit = 1
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}
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/* ×òåíèå òàêæå ñèíõðîííîå äëÿ main, òàéì-àóò íå ðåàëèçîâàí.
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* Ïðè çàâèñàíèè ïðîâåðèòü step/SPI è ðàáîòó òàéìåðà 2.
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*/
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void Seeprom_read( unsigned int adres,
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unsigned int buf[],
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unsigned int size)
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{
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unsigned int len;
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CpuTimer2.InterruptCount=0;
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CpuTimer2Regs.TCR.all = 0x4020; // Use write-only instruction to set TSS bit = 0
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while(!spiSe2pFree(&se2p));
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size = (size / WORD_LEN) + (size % WORD_LEN);
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while(size)
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{
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len = PAGE_LEN - (adres % PAGE_LEN);
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if(len > size) len=size;
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readData.dataPtr = buf;
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readData.nrData = len;
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readData.se2pAddr = adres * WORD_LEN;
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spiSe2pRead(&se2p, &readData);
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while(!spiSe2pFree(&se2p));
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buf += len;
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adres += len;
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size -= len;
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}
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CpuTimer2Regs.TCR.all = 0x4010; // Use write-only instruction to set TSS bit = 1
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}
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void InitSeeprom()
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{
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se2p.init(&se2p);
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EALLOW; // This is needed to write to EALLOW protected registers
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PieVectTable.TINT2 = &cpu_timer2_isr;
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EDIS; // This is needed to disable write to EALLOW protected registers
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InitCpuTimers(); // For this example, only initialize the Cpu Timers
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ConfigCpuTimer(&CpuTimer2, (SYSCLKOUT/1000000), 100);
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IER |= M_INT14;
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}
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void SPISE2P_DRV_init(SPISE2P_DRV *eeprom)
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{
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/* Configure SPI-A pins using GPIO regs*/
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// This specifies which of the possible GPIO pins will be SPI functional pins.
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// Comment out other unwanted lines.
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EALLOW;
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GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA
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GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA
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GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA
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GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0; // General purpose I/O 19 (default) (I/O)
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GpioCtrlRegs.GPADIR.bit.GPIO19 = 1; // Configures the GPIO pin as an output
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GpioDataRegs.GPADAT.bit.GPIO19 = 0;
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EDIS;
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/* Configure the SPI: 8-bit, Rising edge with delay */
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SpiaRegs.SPICCR.all=0x0007;
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SpiaRegs.SPICTL.all=0x001F;
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SpiaRegs.SPISTS.all=0x00;
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SpiaRegs.SPIBRR = CLKMULT * 6;
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SpiaRegs.SPIFFTX.all=0x8000;
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SpiaRegs.SPIFFRX.all=0x0000;
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SpiaRegs.SPIFFCT.all=0x00;
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SpiaRegs.SPIPRI.all=0x0010;
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/* Disable Chip Select of Serial EEPROM */
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eeprom->csr=0;
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eeprom->msgPtr=0;
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SpiaRegs.SPICCR.bit.SPISWRESET=1; // Enable SCI
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}
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void SPISE2P_DRV_csset()
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{
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GpioDataRegs.GPADAT.bit.GPIO19 = 1;
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}
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void SPISE2P_DRV_csclr()
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{
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GpioDataRegs.GPADAT.bit.GPIO19 = 0;
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}
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unsigned int spiSe2pFree(SPISE2P_DRV *se2p)
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{
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if(se2p->csr&0x3) return(0);
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else return(1);
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}
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void spiSe2pWrite(SPISE2P_DRV *se2p, SE2P_DATA *msgPtr)
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{
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se2p->msgPtr=msgPtr;
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se2p->csr|=0x1;
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}
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void spiSe2pRead(SPISE2P_DRV *se2p, SE2P_DATA *msgPtr)
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{
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se2p->msgPtr=msgPtr;
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se2p->csr|=0x2;
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}
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/********************************************************************/
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/******* SPI bus Serial EEPROM driver Tick function *****************/
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/********************************************************************/
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interrupt void cpu_timer2_isr(void)
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{ EALLOW;
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CpuTimer2.InterruptCount++;
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se2p.tick(&se2p);
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// The CPU acknowledges the interrupt.
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EDIS;
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}
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void SPISE2P_DRV_tick(SPISE2P_DRV *eeprom)
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{
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static unsigned int step=0;
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static unsigned int dataCount=0;
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static volatile unsigned int dummy=0;
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switch(step)
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{
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case 0:
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/* If write request is SET, then trigger the Write operation
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If read request is SET, then trigger the Read operation
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If Read request is also not SET, then continue to poll */
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if(eeprom->csr&SPISE2P_WRRQ)
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{ step=1;
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eeprom->csr|=SPISE2P_WRIP; /* Set Write in progress*/
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eeprom->csclr();
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}
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if(eeprom->csr&SPISE2P_RDRQ)
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{ step=13;
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eeprom->csr|=SPISE2P_RDIP; /* Set Read in progress */
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eeprom->csclr();
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}
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break;
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case 1:
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/************************************************************
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*********** SPI bus EEPROM Write Starts from here ***********
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*************************************************************
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Prier to any attempt to write data to SPI serial EEPROM
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Write Enable Latch must be set by issuing the WREN command */
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SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT;
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SpiaRegs.SPITXBUF=SPISE2P_WREN_CMD;
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SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1;
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step=2;
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break;
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case 2:
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/* Wait for VSPI State machine to send the WREN command and
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serial EEPROM Chip Select must be brought to HIGH to set
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the WREN latch */
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if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
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{
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dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */
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eeprom->csset();
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step=3;
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}
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break;
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case 3:
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/* Assert CS of Serial EEPROM and send WRITE command */
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eeprom->csclr();
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SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT;
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SpiaRegs.SPITXBUF=SPISE2P_WRITE_CMD;
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SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1;
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step=4;
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break;
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case 4:
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/* Wait for VSPI State machine to send the WRITE command */
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if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
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{ dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */
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step=5;
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}
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break;
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case 5:
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/* Send Address */
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#if(SPISE2P_ADDR_WIDTH==SIXTEEN_BIT)
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SpiaRegs.SPICCR.all= SPISE2P_TFR16BIT;
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SpiaRegs.SPITXBUF=eeprom->msgPtr->se2pAddr;
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#endif
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#if(SPISE2P_ADDR_WIDTH==EIGHT_BIT)
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SpiaRegs.SPICCR.all= SPISE2P_TFR8BIT;
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SpiaRegs.SPITXBUF=eeprom->msgPtr->se2pAddr<<8;
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#endif
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SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */
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step=6;
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break;
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case 6:
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/* Wait for VSPI State machine to send the Address */
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if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
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{ dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */
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step=7;
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}
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break;
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case 7:
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/* Send Data */
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#if(SPISE2P_DATA_WIDTH==SIXTEEN_BIT)
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SpiaRegs.SPICCR.all=SPISE2P_TFR16BIT;
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SpiaRegs.SPITXBUF=*(eeprom->msgPtr->dataPtr+dataCount);
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#endif
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#if(SPISE2P_DATA_WIDTH==EIGHT_BIT)
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SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT;
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SpiaRegs.SPITXBUF=*(eeprom->msgPtr->dataPtr+dataCount)<<8;
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#endif
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dataCount++;
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SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */
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step=8;
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break;
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case 8:
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/* Wait for VSPI State machine to send the Data.
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If all the data are sent, then set the CS pin to HIGH
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to program or write the data in EEPROM array */
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if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
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{ dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */
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if (dataCount==eeprom->msgPtr->nrData)
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{ eeprom->csset();
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step=9;}
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else
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step=7; /* Write next data */
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}
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break;
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case 9:
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/* Read the EEPROM status register to check whether the
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data sent are indeed programmed to the EEPROM array.
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Hence, send RDSR command to EEPROM to read status reg. */
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eeprom->csclr();
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SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT;
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SpiaRegs.SPITXBUF=SPISE2P_RDSR_CMD;
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SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */
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step=10;
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break;
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case 10:
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/* Wait for VSPI State machine to send RDSR command */
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if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
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{ dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */
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step=11;
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}
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break;
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case 11:
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/* Send dummy Data to read Status reg. */
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SpiaRegs.SPITXBUF=SPISE2P_DUMMY_DATA;
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SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */
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step=12;
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break;
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case 12:
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/* Wait for VSPI State machine to clock out status reg.
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Check, whether the data are written to the EEPROM array,
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If written, then reset the WRIP(write in progress) and
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WRRQ(Write request bit) and go back to STATE0 */
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if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
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{ eeprom->csset();
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if (SpiaRegs.SPIRXBUF & SPISE2P_BUSY_MASK )
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step=9;
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else
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{ eeprom->csr&=(~SPISE2P_WRIP);
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eeprom->csr&=(~SPISE2P_WRRQ);
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step=0;
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dataCount=0;
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}
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}
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break;
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case 13:
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/************************************************************
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*********** SPI bus EEPROM Read Starts from here ***********
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*************************************************************
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Send READ Command to SPI bus serail EEPROM */
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SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT;
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SpiaRegs.SPITXBUF=SPISE2P_READ_CMD;
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SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */
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step=14;
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break;
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case 14:
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/* Wait for VSPI State machine to send READ command */
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if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
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{ dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */
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step=15;
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}
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break;
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case 15:
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/* Send Address */
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#if(SPISE2P_ADDR_WIDTH==SIXTEEN_BIT)
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SpiaRegs.SPICCR.all= SPISE2P_TFR16BIT;
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SpiaRegs.SPITXBUF=eeprom->msgPtr->se2pAddr;
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#endif
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#if(SPISE2P_ADDR_WIDTH==EIGHT_BIT)
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SpiaRegs.SPICCR.all= SPISE2P_TFR8BIT;
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SpiaRegs.SPITXBUF=eeprom->msgPtr->se2pAddr<<8;
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#endif
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SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */
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step=16;
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break;
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case 16:
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/* Wait for VSPI State machine to send Address */
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if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
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{ dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */
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step=17;
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}
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break;
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case 17:
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/* Send Dummy value to clock out data from serial EEPROM */
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#if(SPISE2P_DATA_WIDTH==SIXTEEN_BIT)
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SpiaRegs.SPICCR.all= SPISE2P_TFR16BIT;
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SpiaRegs.SPITXBUF=SPISE2P_DUMMY_DATA;
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#endif
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#if(SPISE2P_DATA_WIDTH==EIGHT_BIT)
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SpiaRegs.SPICCR.all= SPISE2P_TFR8BIT;
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SpiaRegs.SPITXBUF=SPISE2P_DUMMY_DATA<<8;
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#endif
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SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */
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step=18;
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break;
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case 18:
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/* Wait for VSPI State machine to clk out data from EEPROM */
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if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */
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{
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#if(SPISE2P_DATA_WIDTH==SIXTEEN_BIT)
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*(eeprom->msgPtr->dataPtr+dataCount)=SpiaRegs.SPIRXBUF;
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#endif
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#if(SPISE2P_DATA_WIDTH==EIGHT_BIT)
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*(eeprom->msgPtr->dataPtr+dataCount)=SpiaRegs.SPIRXBUF&0xFF;
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#endif
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dataCount++;
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step=19;
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}
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break;
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case 19:
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/* If all the data are read, terminate the read operation by
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rising the CS. Then reset the RDIP (Read in progress) bit
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and reset the RDRQ(Read request) bit and go back to STATE0 */
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if (dataCount==eeprom->msgPtr->nrData)
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{ eeprom->csset();
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step=0;
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dataCount=0;
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eeprom->csr&=(~SPISE2P_RDIP);
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eeprom->csr&=(~SPISE2P_RDRQ);
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}
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else
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step=17;
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break;
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}
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}
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