Expose the existing registers through Modbus and service CAN using one GAS provider only in M95M02 builds. Include the EEPROM layout/driver, LOAD protection and calibration, firmware identity and shared CCS build workflow. Add transport/profile and SCI8 validation tests, documentation and the checked M95M02 firmware image.
48 lines
1.8 KiB
C
48 lines
1.8 KiB
C
/* Exercise the production Timer2 SPI state machine; no hardware writes. */
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#include <assert.h>
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#include "../../Source/Internal/spise2p.c"
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static unsigned trace[300], widths[300], used;
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static void transfer(unsigned long address, int write)
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{
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unsigned buf[2]={0x1234,0x5678}, i;
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SE2P_DATA message={buf,2,address};
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used=0;
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if(write) spiSe2pWrite(&se2p,&message); else spiSe2pRead(&se2p,&message);
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for(i=0;i<100 && !spiSe2pFree(&se2p);i++) {
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SpiaRegs.SPITXBUF=0xdead;
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SpiaRegs.SPIRXBUF=0; /* WIP clear for write, deterministic read data. */
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SpiaRegs.SPISTS.bit.INT_FLAG=1;
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SPISE2P_DRV_tick(&se2p);
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if(SpiaRegs.SPITXBUF!=0xdead) {
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assert(GpioDataRegs.GPADAT.bit.GPIO19==0);
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trace[used]=SpiaRegs.SPITXBUF;
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widths[used++]=(SpiaRegs.SPICCR.all&15)+1;
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}
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}
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assert(spiSe2pFree(&se2p) && GpioDataRegs.GPADAT.bit.GPIO19==1);
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i=0;
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if(write) { assert(trace[i]==0x0600 && widths[i++]==8); }
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assert(trace[i]==(write ? 0x0200 : 0x0300) && widths[i++]==8);
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#if EEPROM_M95M02
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assert(trace[i]==((address>>16)<<8) && widths[i++]==8);
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#endif
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assert(trace[i]==(address&65535) && widths[i++]==16);
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assert(trace[i]==(write ? 0x1234 : 0) && widths[i++]==16);
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assert(trace[i]==(write ? 0x5678 : 0) && widths[i++]==16);
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if(write) { assert(trace[i]==0x0500 && widths[i++]==8); assert(trace[i++]==0); }
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assert(i==used);
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}
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int main(void)
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{
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SPISE2P_DRV_init(&se2p);
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transfer(0x7ffc,0); transfer(0x7ffc,1);
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#if EEPROM_M95M02
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assert(BALSAM167_EEPROM_FIRMWARE_BYTES==261884UL);
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transfer(0xfffe,0); transfer(0x10000,0);
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transfer(0x20000,1); transfer(0x3fffc,0); transfer(0x3fffc,1);
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#else
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assert(BALSAM167_EEPROM_FIRMWARE_BYTES==32508);
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#endif
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return 0;
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}
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