51 lines
1.4 KiB
VHDL
51 lines
1.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity RAM9X8 is
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port(
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data : inout std_logic_vector(7 downto 0);
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address : in std_logic_vector(8 downto 0);
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we : in std_logic;
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oe : in std_logic;
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ce : in std_logic
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);
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end entity;
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architecture behavorial of RAM9X8 is
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type mem is array (511 downto 0) of std_logic_vector(7 downto 0);
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signal memory : mem;
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begin
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process (we, oe, ce)
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variable addr : integer range 0 to 511 := 0;
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begin
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if (ce = '0') then -- Если микросхема выбрана
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addr := conv_integer(address);
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if (oe = '0') then -- Если сигнал чтения активен
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case addr is
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when 0 => data <= x"AA";
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when 1 => data <= x"BB";
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when 2 => data <= x"CC";
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when 3 => data <= x"DD";
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when 4 => data <= x"EE";
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when 5 => data <= x"FF";
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when 6 => data <= x"01";
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when 7 => data <= x"23";
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when 8 => data <= x"45";
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when 9 => data <= x"67";
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when others => data <= not memory(addr);
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end case;
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elsif (we = '0') then -- Если сигнал записи активен
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memory(addr) <= data;
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else
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data <= (others => 'Z'); -- Запретить запись на шину
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end if;
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else
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data <= (others => 'Z'); -- Запретить запись на шину
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end if;
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end process;
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end behavorial; |