altera/MainController/RAM9X8.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
  
entity RAM9X8 is		
	port(
		data : inout std_logic_vector(7 downto 0);
		address : in std_logic_vector(8 downto 0);
		we : in std_logic;
		oe : in std_logic;
		ce : in std_logic
	);
end entity;

architecture behavorial of RAM9X8 is

type mem is array (511 downto 0) of std_logic_vector(7 downto 0);
signal memory : mem; 

begin
	
	process (we, oe, ce)
		variable addr : integer range 0 to 511 := 0;
	begin
		if (ce = '0') then  -- Если микросхема выбрана
			addr := conv_integer(address);
			if (oe = '0') then  -- Если сигнал чтения активен	
				case addr is
					when 0 => data <= x"AA";
               when 1 => data <= x"BB";
               when 2 => data <= x"CC";
               when 3 => data <= x"DD";
               when 4 => data <= x"EE";
               when 5 => data <= x"FF";
               when 6 => data <= x"01";
               when 7 => data <= x"23";
               when 8 => data <= x"45";
               when 9 => data <= x"67";
					when others => data <= not memory(addr);
				end case;		
			elsif (we = '0') then  -- Если сигнал записи активен
				memory(addr) <= data;
			else
				data <= (others => 'Z');  -- Запретить запись на шину
			end if;
		else
			data <= (others => 'Z');  -- Запретить запись на шину
		end if;
	end process;
	
end behavorial;