В работе модуля RAM9X8 сдвинули на один такт после спада CE проверку адреса.

MainController/DigitalFilter16.bsf

@@ -0,0 +1,50 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 160 96)
+	(text "DigitalFilter16" (rect 5 0 54 12)(font "Arial" ))
+	(text "inst" (rect 8 64 20 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 27 31 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "input" (rect 0 0 17 12)(font "Arial" ))
+		(text "input" (rect 21 43 38 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 144 32)
+		(output)
+		(text "output" (rect 0 0 23 12)(font "Arial" ))
+		(text "output" (rect 100 27 123 39)(font "Arial" ))
+		(line (pt 144 32)(pt 128 32)(line_width 1))
+	)
+	(drawing
+		(rectangle (rect 16 16 128 64)(line_width 1))
+	)
+)

MainController/DigitalFilter16.vhd

@@ -0,0 +1,48 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity DigitalFilter16 is
+	 port(
+		 clk : in STD_LOGIC;
+		 input : in STD_LOGIC;
+		 output : out STD_LOGIC
+	     );
+end DigitalFilter16;
+
+architecture Behavioral of DigitalFilter16 is
+	signal count : natural range 0 to 15 := 0;
+	signal latch : std_logic := '0';
+begin	
+	
+	process(clk)		
+	begin		
+		if rising_edge(clk) then 
+			if input = '1' then	
+				if latch = '0' then
+					latch <= '1';
+					count <= 0;
+				else
+					if count < 15 then 
+						count <= count + 1;
+					else 
+						output <= '1';
+						count <= 0;
+					end if;
+				end if;	
+			else
+				if latch = '1' then
+					latch <= '0';
+					count <= 0;
+				else
+					if count < 15 then 
+						count <= count + 1;
+					else 
+						output <= '0';
+						count <= 0;
+					end if;
+				end if;	
+			end if;
+		end if;
+	end process;
+	
+end Behavioral;

MainController/DigitalFilter8.bsf

@@ -0,0 +1,50 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 160 96)
+	(text "DigitalFilter8" (rect 5 0 51 12)(font "Arial" ))
+	(text "inst" (rect 8 64 20 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 27 31 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "input" (rect 0 0 17 12)(font "Arial" ))
+		(text "input" (rect 21 43 38 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 144 32)
+		(output)
+		(text "output" (rect 0 0 23 12)(font "Arial" ))
+		(text "output" (rect 100 27 123 39)(font "Arial" ))
+		(line (pt 144 32)(pt 128 32)(line_width 1))
+	)
+	(drawing
+		(rectangle (rect 16 16 128 64)(line_width 1))
+	)
+)

MainController/DigitalFilter8.vhd

@@ -0,0 +1,48 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity DigitalFilter8 is
+	 port(
+		 clk : in STD_LOGIC;
+		 input : in STD_LOGIC;
+		 output : out STD_LOGIC
+	     );
+end DigitalFilter8;
+
+architecture Behavioral of DigitalFilter8 is
+	signal count : natural range 0 to 7 := 0;
+	signal latch : std_logic := '0';
+begin	
+	
+	process(clk)		
+	begin		
+		if rising_edge(clk) then 
+			if input = '1' then	
+				if latch = '0' then
+					latch <= '1';
+					count <= 0;
+				else
+					if count < 7 then 
+						count <= count + 1;
+					else 
+						output <= '1';
+						count <= 0;
+					end if;
+				end if;	
+			else
+				if latch = '1' then
+					latch <= '0';
+					count <= 0;
+				else
+					if count < 7 then 
+						count <= count + 1;
+					else 
+						output <= '0';
+						count <= 0;
+					end if;
+				end if;	
+			end if;
+		end if;
+	end process;
+	
+end Behavioral;

MainController/RAM9X8.vhd

@@ -23,7 +23,7 @@ signal wePrev : std_logic := '0';
 signal oePrev : std_logic := '0';
 signal cePrev : std_logic := '0';
 
-type MemoryMachine is (Waiting, Writing, Reading);
+type MemoryMachine is (Waiting, Starting, Writing, Reading);
 signal stateMM : MemoryMachine := Waiting;
 
 begin	
@@ -35,15 +35,17 @@ begin
 			case stateMM is
 				when Waiting => 
 					if ce = '0' and cePrev = '1' then
-						addr := conv_integer(address);
+						stateMM <= Starting;
-						if oe = '0' then	-- этот if можно перенести на следующий такт, чтобы успела установиться ножка output enable
-							stateMM <= Reading;							
-						else 
-							stateMM <= Writing;
-						end if;
 					else
 						data <= (others => 'Z');
 					end if;
+				when Starting => 
+					addr := conv_integer(address);
+					if oe = '0' then
+						stateMM <= Reading;							
+					else 
+						stateMM <= Writing;
+					end if;	
 				when Reading =>
 					data <= memory(addr);
 					if oe = '1' and oePrev = '0' then