83 lines
1.8 KiB
VHDL
83 lines
1.8 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity RAM9X8 is
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port(
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clk : in std_logic;
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data : inout std_logic_vector(7 downto 0);
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address : in std_logic_vector(8 downto 0);
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we : in std_logic;
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oe : in std_logic;
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ce : in std_logic
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);
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end entity;
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architecture behavorial of RAM9X8 is
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type mem is array (511 downto 0) of std_logic_vector(7 downto 0);
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signal memory : mem;
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signal wePrev : std_logic := '0';
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signal oePrev : std_logic := '0';
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signal cePrev : std_logic := '0';
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type MemoryMachine is (Waiting, Starting, Writing, Reading);
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signal stateMM : MemoryMachine := Waiting;
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begin
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process(clk)
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variable addr : integer range 0 to 511 := 0;
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begin
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if rising_edge(clk) then
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case stateMM is
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when Waiting =>
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if ce = '0' and cePrev = '1' then
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stateMM <= Starting;
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else
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data <= (others => 'Z');
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end if;
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when Starting =>
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addr := conv_integer(address);
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if oe = '0' then
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stateMM <= Reading;
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else
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stateMM <= Writing;
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end if;
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when Reading =>
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data <= memory(addr);
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if oe = '1' and oePrev = '0' then
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stateMM <= Waiting;
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elsif ce = '1' then
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stateMM <= Waiting;
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end if;
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when Writing =>
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if we = '0' and wePrev = '1' then
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memory(addr) <= data;
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stateMM <= Waiting;
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elsif ce = '1' then
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stateMM <= Waiting;
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end if;
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when others =>
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end case;
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oePrev <= oe;
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cePrev <= ce;
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wePrev <= we;
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memory(0) <= x"AA";
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memory(1) <= x"BB";
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memory(2) <= x"CC";
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memory(3) <= x"DD";
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memory(4) <= x"EE";
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memory(5) <= x"FF";
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memory(6) <= x"01";
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memory(7) <= x"23";
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memory(8) <= x"45";
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memory(9) <= memory(9) + 1;
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end if;
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end process;
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end behavorial; |