Добавил в проект модуль ШИМ (регистры согласно описанию в адресном пространстве). Подключил модуль к портам вводы/вывода, кроме внешнего error. Его пока завел на константу. В каждый цифровой фильтр добавил библиотечный элемент D-тригера (dff), тем самым сместив вправо еще на один такт все сигналы. Такую прошивку надо еще раз тестировать.

This commit is contained in:
sokolovstanislav 2024-04-01 18:52:02 +03:00
parent 512359714c
commit da0eef977c
9 changed files with 3354 additions and 612 deletions

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@ -0,0 +1,846 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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View File

@ -0,0 +1,50 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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(text "inst" (rect 8 80 25 92)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "clk" (rect 21 27 36 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32))
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(line (pt 128 32)(pt 112 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 112 80))
)
)

View File

@ -0,0 +1,191 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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View File

@ -0,0 +1,50 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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(text "inst" (rect 8 80 25 92)(font "Arial" ))
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(line (pt 96 32)(pt 80 32))
)
(drawing
(rectangle (rect 16 16 80 80))
)
)

View File

@ -21,7 +21,7 @@ applicable agreement for further details.
(header "graphic" (version "1.4"))
(pin
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(rect 392 24 560 40)
(rect 376 24 544 40)
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(text "FPGA_CLK" (rect 5 0 61 12)(font "Arial" ))
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@ -34,7 +34,7 @@ applicable agreement for further details.
(line (pt 109 12)(pt 113 8))
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@ -142,7 +142,7 @@ applicable agreement for further details.
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@ -410,6 +427,40 @@ applicable agreement for further details.
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(output)
(text "q[5..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
(text "q[5..0]" (rect 72 27 107 41)(font "Arial" (font_size 8)))
(line (pt 128 32)(pt 112 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 112 80))
)
)
(symbol
(rect 896 1480 928 1496)
(text "VCC" (rect 7 0 27 10)(font "Arial" (font_size 6)))
(text "inst18" (rect 3 5 32 17)(font "Arial" )(invisible))
(port
(pt 16 16)
(output)
(text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible))
(text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible))
(line (pt 16 16)(pt 16 8))
)
(drawing
(line (pt 8 8)(pt 24 8))
)
)
(symbol
(rect 1048 1400 1376 1576)
(text "RAM9X8_PWM" (rect 5 0 78 12)(font "Arial" ))
(text "inst15" (rect 8 160 37 172)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 14 12)(font "Arial" ))
(text "clk" (rect 21 27 35 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "address[address_bus_width-1..0]" (rect 0 0 161 12)(font "Arial" ))
(text "address[address_bus_width-1..0]" (rect 21 43 182 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "we" (rect 0 0 12 12)(font "Arial" ))
(text "we" (rect 21 59 33 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 0 80)
(input)
(text "oe" (rect 0 0 11 12)(font "Arial" ))
(text "oe" (rect 21 75 32 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80))
)
(port
(pt 0 96)
(input)
(text "ce" (rect 0 0 11 12)(font "Arial" ))
(text "ce" (rect 21 91 32 103)(font "Arial" ))
(line (pt 0 96)(pt 16 96))
)
(port
(pt 0 112)
(input)
(text "pwm[5..0]" (rect 0 0 48 12)(font "Arial" ))
(text "pwm[5..0]" (rect 21 107 69 119)(font "Arial" ))
(line (pt 0 112)(pt 16 112)(line_width 3))
)
(port
(pt 0 128)
(input)
(text "error" (rect 0 0 22 12)(font "Arial" ))
(text "error" (rect 21 123 43 135)(font "Arial" ))
(line (pt 0 128)(pt 16 128))
)
(port
(pt 328 48)
(output)
(text "tk[31..0]" (rect 0 0 41 12)(font "Arial" ))
(text "tk[31..0]" (rect 273 43 307 55)(font "Arial" ))
(line (pt 328 48)(pt 312 48)(line_width 3))
)
(port
(pt 328 64)
(output)
(text "interrupt" (rect 0 0 40 12)(font "Arial" ))
(text "interrupt" (rect 274 59 307 71)(font "Arial" ))
(line (pt 328 64)(pt 312 64))
)
(port
(pt 328 32)
(bidir)
(text "data[data_bus_width-1..0]" (rect 0 0 126 12)(font "Arial" ))
(text "data[data_bus_width-1..0]" (rect 208 27 334 39)(font "Arial" ))
(line (pt 328 32)(pt 312 32)(line_width 3))
)
(parameter
"REG_ADDR_MODE_CONTROL_UPPER_BYTE"
"14"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_MODE_CONTROL_LOWER_BYTE"
"15"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_MASK_2_UPPER_BYTE"
"16"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_MASK_2_LOWER_BYTE"
"17"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_MASK_1_UPPER_BYTE"
"18"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_MASK_1_LOWER_BYTE"
"19"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_DIRECT_CONTROL_2_UPPER_BYTE"
"20"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_DIRECT_CONTROL_2_LOWER_BYTE"
"21"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_DIRECT_CONTROL_1_UPPER_BYTE"
"22"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_DIRECT_CONTROL_1_LOWER_BYTE"
"23"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_PERIOD_UPPER_BYTE"
"24"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_PERIOD_LOWER_BYTE"
"25"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_DIRECTION_2_UPPER_BYTE"
"26"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_DIRECTION_2_LOWER_BYTE"
"27"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_DIRECTION_1_UPPER_BYTE"
"28"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_DIRECTION_1_LOWER_BYTE"
"29"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_CHANNEL_UPPER_BYTE"
"30"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_CHANNEL_LOWER_BYTE"
"31"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_TIMING_UPPER_BYTE"
"32"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_TIMING_LOWER_BYTE"
"33"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_CMD_UPPER_BYTE"
"34"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_CMD_LOWER_BYTE"
"35"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_CONTROL_UPPER_BYTE"
"36"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_CONTROL_LOWER_BYTE"
"37"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"DATA_BUS_WIDTH"
"8"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"ADDRESS_BUS_WIDTH"
"9"
""
(type "PARAMETER_SIGNED_DEC") )
(drawing
(rectangle (rect 16 16 312 160))
)
(annotation_block (parameter)(rect 1024 1016 1400 1400))
)
(connector
(pt 488 136)
@ -1249,34 +1533,10 @@ applicable agreement for further details.
(pt 1368 288)
(bus)
)
(connector
(pt 712 656)
(pt 608 656)
)
(connector
(pt 544 672)
(pt 712 672)
)
(connector
(pt 856 656)
(pt 1040 656)
)
(connector
(pt 704 256)
(pt 544 256)
)
(connector
(pt 608 976)
(pt 712 976)
)
(connector
(pt 608 576)
(pt 608 656)
)
(connector
(pt 712 992)
(pt 536 992)
)
(connector
(pt 856 136)
(pt 936 136)
@ -1285,91 +1545,6 @@ applicable agreement for further details.
(pt 936 -16)
(pt 936 136)
)
(connector
(pt 1000 912)
(pt 1040 912)
(bus)
)
(connector
(pt 984 928)
(pt 1040 928)
)
(connector
(pt 968 944)
(pt 1040 944)
)
(connector
(pt 952 960)
(pt 1040 960)
)
(connector
(pt 608 896)
(pt 1040 896)
)
(connector
(pt 1848 912)
(pt 1368 912)
)
(connector
(pt 1848 928)
(pt 1368 928)
)
(connector
(pt 1848 944)
(pt 1368 944)
(bus)
)
(connector
(pt 1848 960)
(pt 1368 960)
(bus)
)
(connector
(pt 856 976)
(pt 1040 976)
)
(connector
(pt 608 656)
(pt 608 896)
)
(connector
(pt 608 896)
(pt 608 976)
)
(connector
(pt 1000 288)
(pt 1000 592)
(bus)
)
(connector
(pt 1000 592)
(pt 1000 912)
(bus)
)
(connector
(pt 984 304)
(pt 984 608)
)
(connector
(pt 984 608)
(pt 984 928)
)
(connector
(pt 968 320)
(pt 968 624)
)
(connector
(pt 968 624)
(pt 968 944)
)
(connector
(pt 952 336)
(pt 952 640)
)
(connector
(pt 952 640)
(pt 952 960)
)
(connector
(pt 1368 608)
(pt 1592 608)
@ -1488,6 +1663,200 @@ applicable agreement for further details.
(pt 1712 64)
(pt 1712 80)
)
(connector
(pt 1000 912)
(pt 1040 912)
(bus)
)
(connector
(pt 984 928)
(pt 1040 928)
)
(connector
(pt 968 944)
(pt 1040 944)
)
(connector
(pt 952 960)
(pt 1040 960)
)
(connector
(pt 608 896)
(pt 1040 896)
)
(connector
(pt 1848 912)
(pt 1368 912)
)
(connector
(pt 1848 928)
(pt 1368 928)
)
(connector
(pt 1848 944)
(pt 1368 944)
(bus)
)
(connector
(pt 1848 960)
(pt 1368 960)
(bus)
)
(connector
(pt 1000 288)
(pt 1000 592)
(bus)
)
(connector
(pt 984 304)
(pt 984 608)
)
(connector
(pt 968 320)
(pt 968 624)
)
(connector
(pt 952 336)
(pt 952 640)
)
(connector
(pt 608 656)
(pt 712 656)
)
(connector
(pt 1040 656)
(pt 808 656)
)
(connector
(pt 544 672)
(pt 712 672)
)
(connector
(pt 608 576)
(pt 608 656)
)
(connector
(pt 608 976)
(pt 712 976)
)
(connector
(pt 1040 976)
(pt 808 976)
)
(connector
(pt 536 992)
(pt 712 992)
)
(connector
(pt 608 656)
(pt 608 896)
)
(connector
(pt 608 32)
(pt 704 32)
)
(connector
(pt 544 32)
(pt 608 32)
)
(connector
(pt 608 896)
(pt 608 976)
)
(connector
(pt 736 1512)
(pt 608 1512)
)
(connector
(pt 736 1528)
(pt 536 1528)
(bus)
)
(connector
(pt 608 1432)
(pt 1048 1432)
)
(connector
(pt 1000 1448)
(pt 1048 1448)
(bus)
)
(connector
(pt 984 1464)
(pt 1048 1464)
)
(connector
(pt 968 1480)
(pt 1048 1480)
)
(connector
(pt 952 1496)
(pt 1048 1496)
)
(connector
(pt 1848 1448)
(pt 1376 1448)
(bus)
)
(connector
(pt 1848 1464)
(pt 1376 1464)
)
(connector
(pt 864 1512)
(pt 1048 1512)
(bus)
)
(connector
(pt 912 1528)
(pt 1048 1528)
)
(connector
(pt 912 1496)
(pt 912 1528)
)
(connector
(pt 608 976)
(pt 608 1432)
)
(connector
(pt 608 1432)
(pt 608 1512)
)
(connector
(pt 1000 592)
(pt 1000 912)
(bus)
)
(connector
(pt 1000 912)
(pt 1000 1448)
(bus)
)
(connector
(pt 984 608)
(pt 984 928)
)
(connector
(pt 984 928)
(pt 984 1464)
)
(connector
(pt 968 624)
(pt 968 944)
)
(connector
(pt 968 944)
(pt 968 1480)
)
(connector
(pt 952 640)
(pt 952 960)
)
(connector
(pt 952 960)
(pt 952 1496)
)
(junction (pt 608 32))
(junction (pt 1000 288))
(junction (pt 984 304))
@ -1506,3 +1875,9 @@ applicable agreement for further details.
(junction (pt 608 408))
(junction (pt 1712 0))
(junction (pt 1712 64))
(junction (pt 608 976))
(junction (pt 1000 912))
(junction (pt 984 928))
(junction (pt 968 944))
(junction (pt 952 960))
(junction (pt 608 1432))

View File

@ -198,4 +198,86 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name VHDL_FILE RAM9X8_PWM.vhd
set_global_assignment -name BDF_FILE DigitalFilterBlockSingle.bdf
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Error
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Interrupt
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[16]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[17]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[18]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[19]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[20]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[21]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[22]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[23]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[24]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[25]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[26]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[27]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[28]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[29]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[30]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[31]
set_location_assignment PIN_236 -to Interrupt
set_location_assignment PIN_202 -to PWM[0]
set_location_assignment PIN_201 -to PWM[1]
set_location_assignment PIN_203 -to PWM[2]
set_location_assignment PIN_216 -to PWM[3]
set_location_assignment PIN_214 -to PWM[4]
set_location_assignment PIN_207 -to PWM[5]
set_location_assignment PIN_134 -to TK[0]
set_location_assignment PIN_133 -to TK[1]
set_location_assignment PIN_128 -to TK[2]
set_location_assignment PIN_164 -to TK[3]
set_location_assignment PIN_162 -to TK[4]
set_location_assignment PIN_161 -to TK[5]
set_location_assignment PIN_160 -to TK[6]
set_location_assignment PIN_159 -to TK[7]
set_location_assignment PIN_146 -to TK[8]
set_location_assignment PIN_139 -to TK[9]
set_location_assignment PIN_145 -to TK[10]
set_location_assignment PIN_144 -to TK[11]
set_location_assignment PIN_137 -to TK[12]
set_location_assignment PIN_147 -to TK[13]
set_location_assignment PIN_135 -to TK[14]
set_location_assignment PIN_142 -to TK[15]
set_location_assignment PIN_181 -to TK[16]
set_location_assignment PIN_182 -to TK[17]
set_location_assignment PIN_183 -to TK[18]
set_location_assignment PIN_184 -to TK[19]
set_location_assignment PIN_132 -to TK[20]
set_location_assignment PIN_131 -to TK[21]
set_location_assignment PIN_112 -to TK[22]
set_location_assignment PIN_111 -to TK[23]
set_location_assignment PIN_117 -to TK[24]
set_location_assignment PIN_185 -to TK[25]
set_location_assignment PIN_186 -to TK[26]
set_location_assignment PIN_114 -to TK[27]
set_location_assignment PIN_120 -to TK[28]
set_location_assignment PIN_119 -to TK[29]
set_location_assignment PIN_113 -to TK[30]
set_location_assignment PIN_118 -to TK[31]
set_global_assignment -name BDF_FILE DigitalFilterBlock6.bdf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

View File

@ -0,0 +1,230 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 344 192)
(text "RAM9X8_PWM" (rect 5 0 75 12)(font "Arial" ))
(text "inst" (rect 8 160 20 172)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 10 12)(font "Arial" ))
(text "clk" (rect 21 27 31 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "address[address_bus_width-1..0]" (rect 0 0 129 12)(font "Arial" ))
(text "address[address_bus_width-1..0]" (rect 21 43 150 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "we" (rect 0 0 10 12)(font "Arial" ))
(text "we" (rect 21 59 31 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 0 80)
(input)
(text "oe" (rect 0 0 9 12)(font "Arial" ))
(text "oe" (rect 21 75 30 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "ce" (rect 0 0 9 12)(font "Arial" ))
(text "ce" (rect 21 91 30 103)(font "Arial" ))
(line (pt 0 96)(pt 16 96)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "pwm[5..0]" (rect 0 0 38 12)(font "Arial" ))
(text "pwm[5..0]" (rect 21 107 59 119)(font "Arial" ))
(line (pt 0 112)(pt 16 112)(line_width 3))
)
(port
(pt 0 128)
(input)
(text "error" (rect 0 0 20 12)(font "Arial" ))
(text "error" (rect 21 123 41 135)(font "Arial" ))
(line (pt 0 128)(pt 16 128)(line_width 1))
)
(port
(pt 328 48)
(output)
(text "tk[31..0]" (rect 0 0 30 12)(font "Arial" ))
(text "tk[31..0]" (rect 277 43 307 55)(font "Arial" ))
(line (pt 328 48)(pt 312 48)(line_width 3))
)
(port
(pt 328 64)
(output)
(text "interrupt" (rect 0 0 31 12)(font "Arial" ))
(text "interrupt" (rect 276 59 307 71)(font "Arial" ))
(line (pt 328 64)(pt 312 64)(line_width 1))
)
(port
(pt 328 32)
(bidir)
(text "data[data_bus_width-1..0]" (rect 0 0 99 12)(font "Arial" ))
(text "data[data_bus_width-1..0]" (rect 208 27 307 39)(font "Arial" ))
(line (pt 328 32)(pt 312 32)(line_width 3))
)
(parameter
"REG_ADDR_MODE_CONTROL_UPPER_BYTE"
"14"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_MODE_CONTROL_LOWER_BYTE"
"15"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_MASK_2_UPPER_BYTE"
"16"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_MASK_2_LOWER_BYTE"
"17"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_MASK_1_UPPER_BYTE"
"18"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_MASK_1_LOWER_BYTE"
"19"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_DIRECT_CONTROL_2_UPPER_BYTE"
"20"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_DIRECT_CONTROL_2_LOWER_BYTE"
"21"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_DIRECT_CONTROL_1_UPPER_BYTE"
"22"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_DIRECT_CONTROL_1_LOWER_BYTE"
"23"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_PERIOD_UPPER_BYTE"
"24"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_PERIOD_LOWER_BYTE"
"25"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_DIRECTION_2_UPPER_BYTE"
"26"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_DIRECTION_2_LOWER_BYTE"
"27"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_DIRECTION_1_UPPER_BYTE"
"28"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_DIRECTION_1_LOWER_BYTE"
"29"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_CHANNEL_UPPER_BYTE"
"30"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_CHANNEL_LOWER_BYTE"
"31"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_TIMING_UPPER_BYTE"
"32"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_TIMING_LOWER_BYTE"
"33"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_CMD_UPPER_BYTE"
"34"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_CMD_LOWER_BYTE"
"35"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_CONTROL_UPPER_BYTE"
"36"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_CONTROL_LOWER_BYTE"
"37"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"DATA_BUS_WIDTH"
"8"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"ADDRESS_BUS_WIDTH"
"9"
""
(type "PARAMETER_SIGNED_DEC") )
(drawing
(rectangle (rect 16 16 312 160)(line_width 1))
)
(annotation_block (parameter)(rect 344 -64 444 16))
)

View File

@ -1,3 +1,8 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity RAM9X8_PWM is
generic(
REG_ADDR_MODE_CONTROL_UPPER_BYTE : integer := 14;
@ -12,16 +17,18 @@ entity RAM9X8_PWM is
REG_ADDR_DIRECT_CONTROL_1_LOWER_BYTE : integer := 23;
REG_ADDR_PERIOD_UPPER_BYTE : integer := 24;
REG_ADDR_PERIOD_LOWER_BYTE : integer := 25;
REG_ADDR_DIRECTION_UPPER_BYTE : integer := 26;
REG_ADDR_DIRECTION_LOWER_BYTE : integer := 27;
REG_ADDR_CHANNEL_UPPER_BYTE : integer := 28;
REG_ADDR_CHANNEL_LOWER_BYTE : integer := 29;
REG_ADDR_TIMING_UPPER_BYTE : integer := 30;
REG_ADDR_TIMING_LOWER_BYTE : integer := 31;
REG_ADDR_CMD_UPPER_BYTE : integer := 32;
REG_ADDR_CMD_LOWER_BYTE : integer := 33;
REG_ADDR_CONTROL_UPPER_BYTE : integer := 34;
REG_ADDR_CONTROL_LOWER_BYTE : integer := 35;
REG_ADDR_DIRECTION_2_UPPER_BYTE : integer := 26;
REG_ADDR_DIRECTION_2_LOWER_BYTE : integer := 27;
REG_ADDR_DIRECTION_1_UPPER_BYTE : integer := 28;
REG_ADDR_DIRECTION_1_LOWER_BYTE : integer := 29;
REG_ADDR_CHANNEL_UPPER_BYTE : integer := 30;
REG_ADDR_CHANNEL_LOWER_BYTE : integer := 31;
REG_ADDR_TIMING_UPPER_BYTE : integer := 32;
REG_ADDR_TIMING_LOWER_BYTE : integer := 33;
REG_ADDR_CMD_UPPER_BYTE : integer := 34;
REG_ADDR_CMD_LOWER_BYTE : integer := 35;
REG_ADDR_CONTROL_UPPER_BYTE : integer := 36;
REG_ADDR_CONTROL_LOWER_BYTE : integer := 37;
DATA_BUS_WIDTH : integer := 8;
ADDRESS_BUS_WIDTH : integer := 9
@ -38,7 +45,8 @@ entity RAM9X8_PWM is
tk : out std_logic_vector(31 downto 0) := (others => '1');
interrupt : out std_logic := '1';
pwm : in std_logic_vector(5 downto 0)
pwm : in std_logic_vector(5 downto 0);
error : in std_logic
);
end entity;
@ -48,30 +56,38 @@ signal modeBuf : std_logic_vector(15 downto 0) := (others => '0');
signal maskBuf : std_logic_vector(31 downto 0) := (others => '1');
signal directControlBuf : std_logic_vector(31 downto 0) := (others => '1');
signal periodBuf : std_logic_vector(15 downto 0) := (others => '0');
signal directionBuf : std_logic_vector(15 downto 0) := (others => '0');
signal directionBuf : std_logic_vector(31 downto 0) := (others => '0');
signal channelBuf : std_logic_vector(15 downto 0) := (others => '0');
signal cmdBuf : std_logic_vector(15 downto 0) := (others => '0');
signal controlBuf : std_logic_vector(15 downto 0) := (others => '0');
type mem is array (15 downto 0) of std_logic_vector(15 downto 0);
signal memory : mem;
signal tkBuf : std_logic_vector(31 downto 0) := (others => '1');
signal lineBusy : std_logic := '1';
signal start : std_logic := '0';
signal startPrev : std_logic := '0';
type mem is array (31 downto 0) of std_logic_vector(15 downto 0);
signal memory : mem;
signal memoryBuf : mem;
signal pwm3level : std_logic_vector(31 downto 0) := (others => '1');
signal upDown : std_logic := '0';
signal upDownPrev : std_logic := '0';
signal interruptBuf : std_logic := '0';
signal period : std_logic_vector(15 downto 0) := (others => '0');
signal counter : std_logic_vector(15 downto 0) := (others => '0');
signal enableWriteControlBuf : std_logic := '1';
begin
process (we, oe, ce)
variable addr : integer range 0 to 2**ADDRESS_BUS_WIDTH - 1 := 0;
variable position : integer range 0 to ARRAY_LENGTH - 1 := 0;
begin
if (ce = '0') then -- Если микросхема выбрана
addr := conv_integer(address);
if (addr = REG_ADDR_MODE_CONTROL_UPPER_BYTE or addr = REG_ADDR_MODE_CONTROL_LOWER_BYTE
or addr = REG_ADDR_MASK_2_UPPER_BYTE or addr = REG_ADDR_MASK_2_LOWER_BYTE or addr = REG_ADDR_MASK_1_UPPER_BYTE or addr = REG_ADDR_MASK_1_LOWER_BYTE
or addr = REG_ADDR_DIRECT_CONTROL_2_UPPER_BYTE or addr = REG_ADDR_DIRECT_CONTROL_2_LOWER_BYTE or addr = REG_ADDR_DIRECT_CONTROL_1_UPPER_BYTE or addr = REG_ADDR_DIRECT_CONTROL_1_LOWER_BYTE
or addr = REG_ADDR_PERIOD_UPPER_BYTE or addr = REG_ADDR_PERIOD_LOWER_BYTE or addr = REG_ADDR_DIRECTION_UPPER_BYTE or addr = REG_ADDR_DIRECTION_LOWER_BYTE
or addr = REG_ADDR_PERIOD_UPPER_BYTE or addr = REG_ADDR_PERIOD_LOWER_BYTE
or addr = REG_ADDR_DIRECTION_2_UPPER_BYTE or addr = REG_ADDR_DIRECTION_2_LOWER_BYTE or addr = REG_ADDR_DIRECTION_1_UPPER_BYTE or addr = REG_ADDR_DIRECTION_1_LOWER_BYTE
or addr = REG_ADDR_CHANNEL_UPPER_BYTE or addr = REG_ADDR_CHANNEL_LOWER_BYTE or addr = REG_ADDR_TIMING_UPPER_BYTE or addr = REG_ADDR_TIMING_LOWER_BYTE
or addr = REG_ADDR_CMD_UPPER_BYTE or addr = REG_ADDR_CMD_LOWER_BYTE or addr = REG_ADDR_CONTROL_UPPER_BYTE or addr = REG_ADDR_CONTROL_LOWER_BYTE) then
if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет
@ -100,29 +116,39 @@ begin
data <= periodBuf(15 downto 8);
when REG_ADDR_PERIOD_LOWER_BYTE =>
data <= periodBuf(7 downto 0);
when REG_ADDR_DIRECTION_UPPER_BYTEE =>
when REG_ADDR_DIRECTION_2_UPPER_BYTE =>
data <= directionBuf(31 downto 24);
when REG_ADDR_DIRECTION_2_LOWER_BYTE =>
data <= directionBuf(23 downto 16);
when REG_ADDR_DIRECTION_1_UPPER_BYTE =>
data <= directionBuf(15 downto 8);
when REG_ADDR_DIRECTION_LOWER_BYTE =>
when REG_ADDR_DIRECTION_1_LOWER_BYTE =>
data <= directionBuf(7 downto 0);
when REG_ADDR_CHANNEL_UPPER_BYTE =>
data <= channelBuf(15 downto 8);
when REG_ADDR_CHANNEL_LOWER_BYTE =>
data <= channelBuf(7 downto 0);
when REG_ADDR_TIMING_UPPER_BYTE =>
data <= memory(conv_integer(channelBuf)(15 downto 8));
data <= memory(conv_integer(channelBuf))(15 downto 8);
when REG_ADDR_TIMING_LOWER_BYTE =>
data <= memory(conv_integer(channelBuf)(7 downto 0);
data <= memory(conv_integer(channelBuf))(7 downto 0);
when REG_ADDR_CMD_UPPER_BYTE =>
data <= cmdBuf(15 downto 8);
when REG_ADDR_CMD_LOWER_BYTE =>
data <= cmdBuf(7 downto 0);
when REG_ADDR_CONTROL_UPPER_BYTE =>
data <= controlBuf(15 downto 8);
data <= controlBuf(15 downto 8);
when REG_ADDR_CONTROL_LOWER_BYTE =>
data <= controlBuf(7 downto 0);
data <= controlBuf(7 downto 0);
when others =>
data <= (others => 'Z'); -- Запретить запись на шину
end case;
end case;
if addr /= REG_ADDR_CONTROL_UPPER_BYTE then
enableWriteControlBuf <= '1';
else
enableWriteControlBuf <= '0';
end if;
elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет
case addr is
when REG_ADDR_MODE_CONTROL_UPPER_BYTE =>
@ -149,32 +175,36 @@ begin
periodBuf(15 downto 8) <= data;
when REG_ADDR_PERIOD_LOWER_BYTE =>
periodBuf(7 downto 0) <= data;
when REG_ADDR_DIRECTION_UPPER_BYTEE =>
when REG_ADDR_DIRECTION_2_UPPER_BYTE =>
directionBuf(31 downto 24) <= data;
when REG_ADDR_DIRECTION_2_LOWER_BYTE =>
directionBuf(23 downto 16) <= data;
when REG_ADDR_DIRECTION_1_UPPER_BYTE =>
directionBuf(15 downto 8) <= data;
when REG_ADDR_DIRECTION_LOWER_BYTE =>
when REG_ADDR_DIRECTION_1_LOWER_BYTE =>
directionBuf(7 downto 0) <= data;
when REG_ADDR_CHANNEL_UPPER_BYTE =>
channelBuf(15 downto 8) <= data;
when REG_ADDR_CHANNEL_LOWER_BYTE =>
channelBuf(7 downto 0) <= data;
when REG_ADDR_TIMING_UPPER_BYTE =>
memory(conv_integer(channelBuf)(15 downto 8)) <= data;
memory(conv_integer(channelBuf))(15 downto 8) <= data;
when REG_ADDR_TIMING_LOWER_BYTE =>
memory(conv_integer(channelBuf)(7 downto 0) <= data;
memory(conv_integer(channelBuf))(7 downto 0) <= data;
when REG_ADDR_CMD_UPPER_BYTE =>
cmdBuf(15 downto 8) <= data;
when REG_ADDR_CMD_LOWER_BYTE =>
cmdBuf(7 downto 0) <= data;
when REG_ADDR_CONTROL_UPPER_BYTE =>
controlBuf(15 downto 8) <= data;
when REG_ADDR_CONTROL_LOWER_BYTE =>
controlBuf(7 downto 0) <= data;
-- when REG_ADDR_CONTROL_UPPER_BYTE =>
-- controlBuf(15 downto 8) <= data;
-- when REG_ADDR_CONTROL_LOWER_BYTE =>
-- controlBuf(7 downto 0) <= data;
when others =>
data <= (others => 'Z'); -- Запретить запись на шину
end case;
else
data <= (others => 'Z'); -- Запретить запись на шину
end if;;
end if;
else
data <= (others => 'Z'); -- Запретить запись на шину
end if;
@ -184,25 +214,153 @@ begin
end process;
process(clk) is
variable counter : integer range 0 to 65666 := 0;
begin
if(rising_edge clk) then
if(conv_integer(memory(0)) > counter) then
if(directionBuf(0) = '0') then
pwm3level(0) <= '0';
else
pwm3level(0) <= '1';
if rising_edge(clk) then
if upDown = '0' then
if conv_integer(counter) < conv_integer(period) then
counter <= counter + 1;
else
counter <= period;
updown <= '1';
end if;
else
if(directionBuf(0) = '0') then
pwm3level(0) <= '1';
else
pwm3level(0) <= '0';
if conv_integer(counter) > 0 then
counter <= counter - 1;
else
counter <= (others => '0');
upDown <= '0';
end if;
end if;
upDownPrev <= upDown;
end if;
end process;
process(clk) is
variable count : integer range 0 to 7 := 0;
begin
if rising_edge(clk) then
if upDown /= upDownPrev then
count := 0;
if cmdBuf(14) = '0' then
interrupt <= '1';
else
if updown = '0' then
interrupt <= '1';
interruptBuf <= '1';
period <= periodBuf; -- новый период грузится сразу во время начала подъема пилы
end if;
end if;
else
if count < 7 then
count := count + 1;
else
interrupt <= '0';
interruptBuf <= '0';
end if;
end if;
end if;
end process;
process(interruptBuf) is
begin
if interruptBuf = '0' then
for i in 0 to 31 loop
memoryBuf(i) <= memory(i); -- а вот новые значения таймингов загрузяться только после счетчика. Но зато могут грузиться дважды за период, если выбран соответствующий тип формирования прерывания
end loop;
end if;
end process;
process(clk) is
begin
if rising_edge(clk) then
for i in 0 to 11 loop
if(conv_integer(memoryBuf(i)) > counter) then
if(directionBuf(i) = '0') then
pwm3level(i) <= '0';
else
pwm3level(i) <= '1';
end if;
else
if(directionBuf(i) = '0') then
pwm3level(i) <= '1';
else
pwm3level(i) <= '0';
end if;
end if;
end loop;
for i in 12 to 15 loop
if(conv_integer(memoryBuf(i)) > counter) then
pwm3level(i) <= '0';
else
pwm3level(i) <= '1';
end if;
end loop;
end process;
for i in 16 to 27 loop
if(conv_integer(memoryBuf(i)) > counter) then
if(directionBuf(i) = '0') then
pwm3level(i) <= '0';
else
pwm3level(i) <= '1';
end if;
else
if(directionBuf(i) = '0') then
pwm3level(i) <= '1';
else
pwm3level(i) <= '0';
end if;
end if;
end loop;
for i in 28 to 31 loop
if(conv_integer(memoryBuf(i)) > counter) then
pwm3level(i) <= '0';
else
pwm3level(i) <= '1';
end if;
end loop;
end if;
end process;
process(clk) is
begin
if rising_edge(clk) then
case modeBuf is
when x"0000" =>
tkBuf <= pwm3level;
when x"0001" =>
tkBuf <= (others => '1');
tkBuf(5 downto 0) <= pwm;
when x"0002" =>
tkBuf <= pwm3level;
when x"0003" =>
tkBuf <= directControlBuf;
when others =>
tkBuf <= (others => '1');
end case;
end if;
end process;
process(clk) is
begin
if rising_edge(clk) then
if cmdBuf(15) = '1' and error = '1' then
tk <= tkBuf or maskBuf;
else
tk <= (others => '1');
end if;
end if;
end process;
process(clk) is
begin
if rising_edge(clk) then
if enableWriteControlBuf = '1' then
controlBuf <= counter;
end if;
end if;
end process;
end behavorial;