Начал писать SerialBusSlave для обмена данными по шине.
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@ -323,4 +323,5 @@ set_global_assignment -name VHDL_FILE RAM9X8_Service.vhd
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set_location_assignment PIN_43 -to S_RES
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to S_RES
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set_global_assignment -name VHDL_FILE TestLedsController.vhd
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_global_assignment -name VHDL_FILE TestSerialBusSlave.vhd
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@ -5,7 +5,7 @@ use ieee.std_logic_unsigned.all;
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entity TestLedsController is
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generic(
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ADDRESS_DEVICE_BUS_WIDTH : integer := 5;
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ADDRESS_DEVICE_BUS_WIDTH : integer := 4;
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COUNT_ASYNCLINE : integer := 15
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);
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247
MainController/TestSerialBusSlave.vhd
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247
MainController/TestSerialBusSlave.vhd
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@ -0,0 +1,247 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity TestSerialBusSlave is
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generic(
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ADDRESS_DEVICE_BUS_WIDTH : integer := 4;
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ADDRESS_REG_BUS_WIDTH : integer := 4;
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DATA_BUS_WIDTH : integer := 16;
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COUNT_RESET : integer := 180
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);
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port(
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clk : in std_logic;
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addressdevice : in std_logic_vector(ADDRESS_DEVICE_BUS_WIDTH - 1 downto 0);
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sbclk : in std_logic;
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sbdatain : in std_logic;
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sbdataout : out std_logic := '0';
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addressregister : out std_logic_vector(ADDRESS_REG_BUS_WIDTH - 1 downto 0);
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dataout : out std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
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datain : in std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
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rw : out std_logic;
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dataready : out std_logic
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);
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end entity;
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architecture behavorial of TestSerialBusSlave is
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signal address_received : std_logic_vector(ADDRESS_DEVICE_BUS_WIDTH - 1 downto 0) := (others => '0');
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signal sbclkPrev : std_logic := '0';
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signal sbReset : std_logic := '0';
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signal sbResetPrev : std_logic := '0';
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signal sbDataOutBuf : std_logic := '0';
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signal direction : std_logic := '0';
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signal addressDevBuf : std_logic_vector(ADDRESS_DEVICE_BUS_WIDTH - 1 downto 0) := (others => '0');
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signal addressRegBuf : std_logic_vector(ADDRESS_REG_BUS_WIDTH - 1 downto 0) := (others => '0');
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type CommunicationStateType is (Waiting, ReceiveAddress, ReceiveData, ReceiveCRC, ReceiveCheck, TransmitData, TransmitCRC, TransmitCheck, Timeout);
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signal CommunicationState : CommunicationStateType := Waiting;
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signal resetCRC : std_logic := '1';
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signal CRC : std_logic_vector(3 downto 0) := x"0";
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signal bufCRC : std_logic_vector(3 downto 0) := x"0";
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signal dataCRC : std_logic_vector(31 downto 0) := x"00000000"; -- переключает
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signal readyCRC : std_logic := '0';
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begin
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process(clk) is
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variable count : integer range 0 to COUNT_RESET := 0;
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begin
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if rising_edge(clk) then
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sbclkPrev <= sbclk;
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if sbclk = '0' then
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if count < COUNT_RESET then
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count := count + 1;
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else
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sbReset <= '1';
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end if;
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else
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count := 0;
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sbReset <= '0';
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end if;
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end if;
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end process;
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sbdataout <= sbDataOutBuf;
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process(clk)
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variable bitCnt : integer range -1 to ADDRESS_DEVICE_BUS_WIDTH + ADDRESS_REG_BUS_WIDTH + DATA_BUS_WIDTH - 1 := ADDRESS_DEVICE_BUS_WIDTH;
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begin
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if rising_edge(clk) then
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if sbReset = '1' and sbResetPrev = '0' then
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CommunicationState <= Waiting;
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resetCRC <= '1';
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else
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resetCRC <= '0';
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end if;
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sbResetPrev <= sbReset;
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case CommunicationState is
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when Waiting =>
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CRCData <= sbdatain;
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if sbclk = '1' and sbclkPrev = '0' then
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rw <= sbdatain;
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direction <= sbdatain;
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dataready <= '0';
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bitCnt := ADDRESS_DEVICE_BUS_WIDTH; -- на один больше из-за условия в ReceiveAddress, срабатывающего по спаду сигнала
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-- удалил обновление адреса в этом месте, но добавил сохранение направления передачи, по нему будем работать дальше
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CommunicationState <= ReceiveAddress;
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else
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if sbDataOutBuf = '0' then
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sbDataOutBuf <= '1'; --pull up
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else
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sbDataOutBuf <= 'Z';
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end if;
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end if;
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when ReceiveAddress =>
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CRCData <= sbdatain;
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if sbclk = '1' and sbclkPrev = '0' then
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address_register(bitCnt) <= sbdatain;
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if bitCnt = 0 then
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-- условие ниже пересмотреть и добавить буффер на адрес
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if bufAddr(7 downto 4) = AddrSlave then
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AddrUpdated <= '1';
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else
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CommunicationState <= Timeout;
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end if;
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end if;
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end if;
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if sbclk = '0' and sbclkPrev = '1' then
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BitCnt <= BitCnt -1;
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end if;
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if BitCnt = -1 then
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if Direction = '0' then
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BitCnt <= 15;
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Data_out_sig <= DataFromSlave(15);
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CommunicationState <= SData;
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else
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BitCnt <= 19;
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CommunicationState <= RData; --- 16 data + 4ñrc (19 to 0)
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end if;
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end if;
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when SData => -- îòïðàâêà ïî ñèíõðîêëîêó ïîä ñ÷åò
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CRCData <= Data_out_sig;
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if sclk = '0' and sclk_prev = '1' then
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Data_out_sig <= DataFromSlave (BitCnt);
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end if;
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if sclk = '1' and sclk_prev = '0' then
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if BitCnt > 0 then
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BitCnt <= BitCnt -1;
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else
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BitCnt <= 3;
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CommunicationState <= SCRC;
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end if;
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end if;
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when SCRC => -- îòïðàâêà ïî ñèíõðîêëîêó ïîä ñ÷åò
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if sclk = '0' and sclk_prev = '1' then
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Data_out_sig <= CRC_sign (BitCnt);
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end if;
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if sclk = '1' and sclk_prev = '0' then
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if BitCnt > 0 then
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BitCnt <= BitCnt -1;
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else
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CommunicationState <= Timeout;
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end if;
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end if;
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when RData =>
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CRCData <= BusIn;
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if sclk= '1' and sclk_prev = '0' then
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bufData(BitCnt) <= BusIn;
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end if;
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if sclk = '0' and sclk_prev = '1' then
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if BitCnt > 0 then
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BitCnt <= BitCnt -1;
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else
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if bufData(3 downto 0) = CRC_sign then
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DataUpdated_sig <= '1';
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Data_out_sig <= '0';
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led <= '0';
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else
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Data_out_sig <= '1';
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led <= '1';
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end if;
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CommunicationState <= Timeout;
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end if;
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end if;
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when Timeout =>
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-- CRCReset_sig <= '1';
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when others =>
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end case;
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end if;
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end process;
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process(clk)
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variable lacth : integer range 0 to 1 := 0;
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variable bitCnt : integer range -1 to 24 := 0;
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begin
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if rising_edge(clk) then
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if resetCRC = '1' then
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bitCnt := 24;
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CRC <= x"0";
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lacth := 0;
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readyCRC <= '0';
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else
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if readyCRC = '0' then
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if lacth = 0 then
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if bitCnt /= -1 then
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CRC(3) <= CRC(2) xor CRC(3);
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CRC(2) <= CRC(1) xor CRC(0);
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CRC(1) <= CRC(0);
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CRC(0) <= dataCRC(bitCnt) xor CRC(1);
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bitCnt := bitCnt - 1;
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else
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bitCnt := 3;
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lacth := 1;
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end if;
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else
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if bitCnt /= -1 then
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CRC(3) <= CRC(2) xor CRC(3);
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CRC(2) <= CRC(1) xor CRC(0);
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CRC(1) <= CRC(0);
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CRC(0) <= '1' xor CRC(1);
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bitCnt := bitCnt - 1;
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else
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readyCRC <= '1';
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--countreadyCRC <= countreadyCRC + 1;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end behavorial;
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