Добавил тестовый блок для периферийных устройств "TestLedsController". Здесь объеденины блоки "abus_led_slave" и "ledController". Блок имеет джинерики для настройки адреса устройства и счетчика работы с линией передачи. Теоритически адрес теперь может быть любым хоть и сделан для расширения с четырех бит всего до пяти. Значение первого джинерика заезжает в шину, которая идёт от джамперов на плате, и в адрес из посылки, передаваемой по аинхронной линии передачи из управляющего контроллера. Значение второго - это значение, до которыго считают счётчики автомата на приеме линии. Блок можно проверить в составе процессорного модуля, подавая на него необходимые сигналы.
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@ -2126,6 +2126,74 @@ applicable agreement for further details.
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(line (pt 263 112)(pt 215 112))
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)
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)
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(symbol
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(rect 2504 -8 2808 136)
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(text "TestLedsController" (rect 5 0 97 12)(font "Arial" ))
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(text "inst16" (rect 8 128 37 140)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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(text "clk" (rect 0 0 14 12)(font "Arial" ))
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(text "clk" (rect 21 27 35 39)(font "Arial" ))
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(line (pt 0 32)(pt 16 32))
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)
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(port
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(pt 0 48)
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(input)
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(text "address_device[address_device_bus_width-1..0]" (rect 21 43 260 55)(font "Arial" ))
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(line (pt 0 48)(pt 16 48)(line_width 3))
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)
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(port
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(pt 0 64)
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(input)
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(line (pt 0 64)(pt 16 64))
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)
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(port
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(pt 0 80)
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(input)
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(text "divclk" (rect 0 0 29 12)(font "Arial" ))
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(text "divclk" (rect 21 75 50 87)(font "Arial" ))
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(line (pt 0 80)(pt 16 80))
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)
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(port
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(pt 0 96)
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(input)
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(text "errors[1..0]" (rect 0 0 54 12)(font "Arial" ))
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(text "errors[1..0]" (rect 21 91 75 103)(font "Arial" ))
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(line (pt 0 96)(pt 16 96)(line_width 3))
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)
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(port
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(pt 0 112)
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(input)
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(text "done" (rect 0 0 23 12)(font "Arial" ))
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(text "done" (rect 21 107 44 119)(font "Arial" ))
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(line (pt 0 112)(pt 16 112))
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)
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(port
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(pt 304 32)
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(output)
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(text "led" (rect 0 0 14 12)(font "Arial" ))
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(text "led" (rect 272 27 286 39)(font "Arial" ))
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(line (pt 304 32)(pt 288 32))
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)
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(parameter
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"ADDRESS_DEVICE_BUS_WIDTH"
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"5"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(parameter
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"COUNT_ASYNCLINE"
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"15"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(drawing
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(rectangle (rect 16 16 288 128))
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(annotation_block (parameter)(rect 2512 -64 2800 -16))
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)
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(connector
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(pt 1592 624)
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(pt 1568 624)
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@ -2183,34 +2251,6 @@ applicable agreement for further details.
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(pt 1736 608)
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(pt 1848 608)
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)
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(connector
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(pt 1568 504)
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(pt 1592 504)
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)
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(connector
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(pt 1520 488)
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(pt 1592 488)
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)
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(connector
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(pt 1520 592)
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(pt 1520 488)
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)
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(connector
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(pt 1568 416)
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(pt 1568 504)
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)
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(connector
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(pt 1568 504)
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(pt 1568 624)
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)
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(connector
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(pt 1736 472)
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(pt 1848 472)
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)
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(connector
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(pt 1736 488)
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(pt 1848 488)
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)
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(connector
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(pt 552 656)
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(pt 712 656)
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@ -2273,14 +2313,6 @@ applicable agreement for further details.
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(pt 608 472)
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(pt 608 576)
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)
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(connector
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(pt 608 472)
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(pt 1544 472)
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)
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(connector
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(pt 1544 472)
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(pt 1592 472)
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)
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(connector
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(pt 1000 336)
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(pt 1048 336)
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@ -2816,35 +2848,6 @@ applicable agreement for further details.
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(pt 1656 -424)
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(pt 1840 -424)
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)
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(connector
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(pt 608 1256)
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(pt 1048 1256)
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)
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(connector
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(pt 1000 1272)
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(pt 1048 1272)
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(bus)
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)
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(connector
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(pt 984 1288)
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(pt 1048 1288)
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)
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(connector
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(pt 968 1304)
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(pt 1048 1304)
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)
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(connector
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(pt 952 1320)
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(pt 1048 1320)
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)
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(connector
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(pt 1376 1272)
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(pt 1856 1272)
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)
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(connector
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(pt 1376 1288)
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(pt 1856 1288)
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)
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(connector
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(pt 1392 1592)
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(pt 936 1592)
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@ -2986,48 +2989,6 @@ applicable agreement for further details.
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(pt 904 104)
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(pt 1048 104)
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)
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(connector
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(pt 608 1088)
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(pt 608 1256)
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)
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(connector
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(pt 608 1256)
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(pt 608 1464)
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)
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(connector
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(pt 1000 1024)
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(pt 1000 1272)
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(bus)
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)
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(connector
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(pt 1000 1272)
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(pt 1000 1480)
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(bus)
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)
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(connector
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(pt 984 1040)
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(pt 984 1288)
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)
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(connector
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(pt 984 1288)
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(pt 984 1496)
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)
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(connector
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(pt 968 1056)
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(pt 968 1304)
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)
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(connector
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(pt 968 1304)
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(pt 968 1512)
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)
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(connector
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(pt 952 1072)
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(pt 952 1320)
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)
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(connector
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(pt 952 1320)
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(pt 952 1528)
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)
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(connector
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(pt 1784 1480)
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(pt 1784 1552)
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@ -3112,6 +3073,113 @@ applicable agreement for further details.
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(pt 1016 -424)
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(pt 1536 -424)
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)
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(connector
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(pt 1848 472)
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(pt 1736 472)
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)
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(connector
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(pt 1848 488)
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(pt 1736 488)
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)
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(connector
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(pt 1568 504)
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(pt 1592 504)
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)
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(connector
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(pt 1520 488)
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(pt 1592 488)
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)
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(connector
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(pt 1520 592)
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(pt 1520 488)
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)
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(connector
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(pt 1568 416)
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(pt 1568 504)
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)
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(connector
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(pt 1568 504)
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(pt 1568 624)
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)
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(connector
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(pt 608 472)
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(pt 1544 472)
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)
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(connector
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(pt 1544 472)
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(pt 1592 472)
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)
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(connector
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(pt 608 1256)
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(pt 1048 1256)
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)
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(connector
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(pt 1000 1272)
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(pt 1048 1272)
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(bus)
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)
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(connector
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(pt 1856 1272)
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(pt 1376 1272)
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)
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(connector
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(pt 984 1288)
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(pt 1048 1288)
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)
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(connector
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(pt 1856 1288)
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(pt 1376 1288)
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)
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(connector
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(pt 968 1304)
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(pt 1048 1304)
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)
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(connector
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(pt 952 1320)
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(pt 1048 1320)
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)
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(connector
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(pt 608 1088)
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(pt 608 1256)
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)
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(connector
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(pt 608 1256)
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(pt 608 1464)
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)
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(connector
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(pt 1000 1024)
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(pt 1000 1272)
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(bus)
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)
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(connector
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(pt 1000 1272)
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(pt 1000 1480)
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(bus)
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)
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(connector
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(pt 984 1040)
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(pt 984 1288)
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)
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(connector
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(pt 984 1288)
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(pt 984 1496)
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)
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(connector
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(pt 968 1056)
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(pt 968 1304)
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)
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(connector
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(pt 968 1304)
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(pt 968 1512)
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)
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(connector
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(pt 952 1072)
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(pt 952 1320)
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)
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(connector
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(pt 952 1320)
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(pt 952 1528)
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)
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(junction (pt 608 576))
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(junction (pt 1000 592))
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(junction (pt 984 608))
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@ -322,4 +322,5 @@ set_global_assignment -name VHDL_FILE RAM9X8_Peripheral.vhd
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set_global_assignment -name VHDL_FILE RAM9X8_Service.vhd
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set_location_assignment PIN_43 -to S_RES
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to S_RES
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set_global_assignment -name VHDL_FILE TestLedsController.vhd
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@ -1,140 +0,0 @@
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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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||||
the Block Editor! File corruption is VERY likely to occur.
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||||
*/
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/*
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Copyright (C) 1991-2013 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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||||
(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
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||||
without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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||||
applicable agreement for further details.
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||||
*/
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(header "symbol" (version "1.1"))
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(symbol
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(rect 16 16 344 160)
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(text "RAM9X8_LedController" (rect 5 0 104 12)(font "Arial" ))
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(text "inst" (rect 8 128 20 140)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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(text "clk" (rect 0 0 10 12)(font "Arial" ))
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(text "clk" (rect 21 27 31 39)(font "Arial" ))
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(line (pt 0 32)(pt 16 32)(line_width 1))
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)
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(port
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(pt 0 48)
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(input)
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(text "address[address_bus_width-1..0]" (rect 0 0 129 12)(font "Arial" ))
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(text "address[address_bus_width-1..0]" (rect 21 43 150 55)(font "Arial" ))
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(line (pt 0 48)(pt 16 48)(line_width 3))
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)
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(port
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(pt 0 64)
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(input)
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(text "we" (rect 0 0 10 12)(font "Arial" ))
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(text "we" (rect 21 59 31 71)(font "Arial" ))
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(line (pt 0 64)(pt 16 64)(line_width 1))
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)
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(port
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(pt 0 80)
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(input)
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(text "oe" (rect 0 0 9 12)(font "Arial" ))
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(text "oe" (rect 21 75 30 87)(font "Arial" ))
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(line (pt 0 80)(pt 16 80)(line_width 1))
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)
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(port
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(pt 0 96)
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(input)
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(text "ce" (rect 0 0 9 12)(font "Arial" ))
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(text "ce" (rect 21 91 30 103)(font "Arial" ))
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(line (pt 0 96)(pt 16 96)(line_width 1))
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)
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(port
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(pt 0 112)
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(input)
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(text "error" (rect 0 0 20 12)(font "Arial" ))
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(text "error" (rect 21 107 41 119)(font "Arial" ))
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(line (pt 0 112)(pt 16 112)(line_width 1))
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)
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(port
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(pt 328 48)
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(output)
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(text "asyncline" (rect 0 0 36 12)(font "Arial" ))
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(text "asyncline" (rect 271 43 307 55)(font "Arial" ))
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(line (pt 328 48)(pt 312 48)(line_width 1))
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)
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(port
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(pt 328 64)
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(output)
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(text "divclk" (rect 0 0 22 12)(font "Arial" ))
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(text "divclk" (rect 285 59 307 71)(font "Arial" ))
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(line (pt 328 64)(pt 312 64)(line_width 1))
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)
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(port
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(pt 328 80)
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(output)
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(text "init" (rect 0 0 9 12)(font "Arial" ))
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(text "init" (rect 298 75 307 87)(font "Arial" ))
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(line (pt 328 80)(pt 312 80)(line_width 1))
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)
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(port
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(pt 328 32)
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(bidir)
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(text "data[data_bus_width-1..0]" (rect 0 0 99 12)(font "Arial" ))
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(text "data[data_bus_width-1..0]" (rect 208 27 307 39)(font "Arial" ))
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(line (pt 328 32)(pt 312 32)(line_width 3))
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)
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(parameter
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"REG_ADDR_ACTIVE_DEVICE_LOWER_BYTE"
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"38"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(parameter
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"REG_ADDR_ACTIVE_DEVICE_UPPER_BYTE"
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"39"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(parameter
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"REG_ADDR_TEST_LOWER_BYTE"
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"40"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(parameter
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"REG_ADDR_TEST_UPPER_BYTE"
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"41"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(parameter
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"REG_ADDR_VERSION_LOWER_BYTE"
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"42"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(parameter
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"REG_ADDR_VERSION_UPPER_BYTE"
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"43"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(parameter
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"DATA_BUS_WIDTH"
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"8"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(parameter
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"ADDRESS_BUS_WIDTH"
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"9"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(drawing
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(rectangle (rect 16 16 312 128)(line_width 1))
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)
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(annotation_block (parameter)(rect 344 -64 444 16))
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)
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@ -1,299 +0,0 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity RAM9X8_LedController is
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generic(
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REG_ADDR_ACTIVE_DEVICE_LOWER_BYTE : integer := 38;
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REG_ADDR_ACTIVE_DEVICE_UPPER_BYTE : integer := 39;
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REG_ADDR_TEST_LOWER_BYTE : integer := 40;
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REG_ADDR_TEST_UPPER_BYTE : integer := 41;
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REG_ADDR_VERSION_LOWER_BYTE : integer := 42;
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REG_ADDR_VERSION_UPPER_BYTE : integer := 43;
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DATA_BUS_WIDTH : integer := 8;
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ADDRESS_BUS_WIDTH : integer := 9
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);
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port(
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clk : in std_logic;
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data : inout std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
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address : in std_logic_vector(ADDRESS_BUS_WIDTH - 1 downto 0);
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we : in std_logic;
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oe : in std_logic;
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ce : in std_logic;
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asyncline : out std_logic := '1';
|
||||
divclk : out std_logic := '1';
|
||||
error : in std_logic;
|
||||
init : out std_logic := '0'
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture behavorial of RAM9X8_LedController is
|
||||
|
||||
signal activeDeviceBuf : std_logic_vector(15 downto 0) := (others => '0');
|
||||
signal testBuf : std_logic_vector(15 downto 0) := (others => '0');
|
||||
signal versionBuf : std_logic_vector(15 downto 0) := x"0004";
|
||||
|
||||
signal initBuf : std_logic := '0';
|
||||
signal divClkBuf : std_logic := '0';
|
||||
signal divClkBufPWM : std_logic := '0';
|
||||
|
||||
signal addrBuf : std_logic_vector(3 downto 0) := (others => '0');
|
||||
signal ledBuf : std_logic := '0';
|
||||
|
||||
signal LedState : std_logic_vector(1 downto 0) := (others => '0');
|
||||
|
||||
type BusSt is (Waiting, A3, A2, A1, A0, Dt, Finish);
|
||||
signal BusState : BusSt := Waiting;
|
||||
|
||||
signal countBuf : std_logic_vector(3 downto 0) := (others => '0');
|
||||
signal countBufPWM : std_logic_vector(3 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
|
||||
process (we, oe, ce)
|
||||
variable addr : integer range 0 to 2**ADDRESS_BUS_WIDTH - 1 := 0;
|
||||
begin
|
||||
if (ce = '0') then -- Если микросхема выбрана
|
||||
addr := conv_integer(address);
|
||||
if (addr = REG_ADDR_ACTIVE_DEVICE_UPPER_BYTE or addr = REG_ADDR_ACTIVE_DEVICE_LOWER_BYTE
|
||||
or addr = REG_ADDR_TEST_UPPER_BYTE or addr = REG_ADDR_TEST_LOWER_BYTE
|
||||
or addr = REG_ADDR_VERSION_UPPER_BYTE or addr = REG_ADDR_VERSION_LOWER_BYTE) then
|
||||
if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет
|
||||
case addr is
|
||||
when REG_ADDR_ACTIVE_DEVICE_UPPER_BYTE =>
|
||||
data <= activeDeviceBuf(15 downto 8);
|
||||
when REG_ADDR_ACTIVE_DEVICE_LOWER_BYTE =>
|
||||
data <= activeDeviceBuf(7 downto 0);
|
||||
when REG_ADDR_TEST_UPPER_BYTE =>
|
||||
data <= not testBuf(15 downto 8);
|
||||
when REG_ADDR_TEST_LOWER_BYTE =>
|
||||
data <= not testBuf(7 downto 0);
|
||||
when REG_ADDR_VERSION_UPPER_BYTE =>
|
||||
data <= versionBuf(15 downto 8);
|
||||
when REG_ADDR_VERSION_LOWER_BYTE =>
|
||||
data <= versionBuf(7 downto 0);
|
||||
when others =>
|
||||
data <= (others => 'Z'); -- Запретить запись на шину
|
||||
end case;
|
||||
elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет
|
||||
case addr is
|
||||
when REG_ADDR_ACTIVE_DEVICE_UPPER_BYTE =>
|
||||
activeDeviceBuf(15 downto 8) <= data;
|
||||
when REG_ADDR_ACTIVE_DEVICE_LOWER_BYTE =>
|
||||
activeDeviceBuf(7 downto 0) <= data;
|
||||
when REG_ADDR_TEST_UPPER_BYTE =>
|
||||
testBuf(15 downto 8) <= data;
|
||||
when REG_ADDR_TEST_LOWER_BYTE =>
|
||||
testBuf(7 downto 0) <= data;
|
||||
when others =>
|
||||
data <= (others => 'Z'); -- Запретить запись на шину
|
||||
end case;
|
||||
else
|
||||
data <= (others => 'Z'); -- Запретить запись на шину
|
||||
end if;
|
||||
else
|
||||
data <= (others => 'Z'); -- Запретить запись на шину
|
||||
end if;
|
||||
else
|
||||
data <= (others => 'Z'); -- Запретить запись на шину
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk) is
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if testBuf = x"5AA5" then
|
||||
initBuf <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
init <= initBuf;
|
||||
|
||||
process(clk) is
|
||||
variable count50000 : integer range 0 to 50000 := 0;
|
||||
variable count50 : integer range 0 to 50 := 0;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if count50000 < 50000 then
|
||||
count50000 := count50000 + 1;
|
||||
else
|
||||
divClkBufPWM <= not divClkBufPWM;
|
||||
count50000 := 0;
|
||||
if count50 < 50 then
|
||||
count50 := count50 + 1;
|
||||
else
|
||||
count50 := 0;
|
||||
divClkBuf <= not divClkBuf;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(divClkBufPWM) is
|
||||
begin
|
||||
if conv_integer(countBufPWM) < 15 then
|
||||
countBufPWM <= conv_std_logic_vector(conv_integer(countBufPWM) + 1, 4);
|
||||
else
|
||||
countBufPWM <= (others => '0');
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(divClkBuf) is
|
||||
variable direction : integer range 0 to 1 := 0;
|
||||
begin
|
||||
if direction = 0 then
|
||||
if conv_integer(countBuf) < 15 then
|
||||
countBuf <= conv_std_logic_vector(conv_integer(countBuf) + 1, 4);
|
||||
else
|
||||
direction := 1;
|
||||
end if;
|
||||
else
|
||||
if conv_integer(countBuf) > 0 then
|
||||
countBuf <= conv_std_logic_vector(conv_integer(countBuf) - 1, 4);
|
||||
else
|
||||
direction := 0;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(divClkBuf) is
|
||||
variable count15 : integer range 0 to 15 := 0;
|
||||
begin
|
||||
case LedState is
|
||||
when b"00" =>
|
||||
if count15 < 15 then
|
||||
count15 := count15 + 1;
|
||||
else
|
||||
count15 := 0;
|
||||
LedState <= b"01";
|
||||
end if;
|
||||
divclk <= '0';
|
||||
when b"01" =>
|
||||
if count15 < 7 then
|
||||
count15 := count15 + 1;
|
||||
else
|
||||
count15 := 0;
|
||||
LedState <= b"10";
|
||||
end if;
|
||||
divclk <= '1';
|
||||
when b"10" =>
|
||||
if count15 < 15 then
|
||||
count15 := count15 + 1;
|
||||
else
|
||||
count15 := 0;
|
||||
LedState <= b"11";
|
||||
end if;
|
||||
divclk <= '0';
|
||||
when b"11" =>
|
||||
if count15 < 4 then
|
||||
count15 := count15 + 1;
|
||||
else
|
||||
count15 := 0;
|
||||
LedState <= b"00";
|
||||
end if;
|
||||
divclk <= '1';
|
||||
when others =>
|
||||
LedState <= b"00";
|
||||
end case;
|
||||
end process;
|
||||
|
||||
process(clk) is
|
||||
variable count50 : integer range 0 to 50 := 0;
|
||||
variable count15 : integer range 0 to 15 := 15;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if initBuf = '0' then
|
||||
case BusState is
|
||||
when Waiting =>
|
||||
if count50 < 38 then
|
||||
count50 := count50 + 1;
|
||||
else
|
||||
if count15 < 15 then
|
||||
count15 := count15 + 1;
|
||||
else
|
||||
count15 := 0;
|
||||
end if;
|
||||
if activeDeviceBuf(count15) = '1' then
|
||||
addrBuf <= conv_std_logic_vector(count15, 4);
|
||||
asyncline <= '0';
|
||||
count50 := 0;
|
||||
BusState <= A3;
|
||||
end if;
|
||||
end if;
|
||||
when A3 =>
|
||||
if count50 < 18 then
|
||||
count50 := count50 + 1;
|
||||
else
|
||||
count50 := 0;
|
||||
asyncline <= addrBuf(3);
|
||||
BusState <= A2;
|
||||
end if;
|
||||
when A2 =>
|
||||
if count50 < 38 then
|
||||
count50 := count50 + 1;
|
||||
else
|
||||
count50 := 0;
|
||||
asyncline <= addrBuf(2);
|
||||
BusState <= A1;
|
||||
end if;
|
||||
when A1 =>
|
||||
if count50 < 38 then
|
||||
count50 := count50 + 1;
|
||||
else
|
||||
count50 := 0;
|
||||
asyncline <= addrBuf(1);
|
||||
BusState <= A0;
|
||||
end if;
|
||||
when A0 =>
|
||||
if count50 < 38 then
|
||||
count50 := count50 + 1;
|
||||
else
|
||||
count50 := 0;
|
||||
asyncline <= addrBuf(0);
|
||||
BusState <= Dt;
|
||||
end if;
|
||||
when Dt =>
|
||||
if count50 < 38 then
|
||||
count50 := count50 + 1;
|
||||
else
|
||||
count50 := 0;
|
||||
asyncline <= divClkBuf;
|
||||
BusState <= Finish;
|
||||
end if;
|
||||
when Finish =>
|
||||
if count50 < 38 then
|
||||
count50 := count50 + 1;
|
||||
else
|
||||
count50 := 0;
|
||||
asyncline <= '1';
|
||||
BusState <= Finish;
|
||||
end if;
|
||||
when others =>
|
||||
BusState <= Waiting;
|
||||
count50 := 0;
|
||||
count15 :=15;
|
||||
end case;
|
||||
else
|
||||
BusState <= Waiting;
|
||||
count50 := 0;
|
||||
count15 := 15;
|
||||
if error = '0' then
|
||||
if countBuf < countBufPWM then
|
||||
asyncline <= '1';
|
||||
else
|
||||
asyncline <= '0';
|
||||
end if;
|
||||
else
|
||||
asyncline <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end behavorial;
|
||||
@ -1,123 +0,0 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 16 16 344 160)
|
||||
(text "RAM9X8_TEST" (rect 5 0 75 12)(font "Arial" ))
|
||||
(text "inst" (rect 8 128 20 140)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "clk" (rect 0 0 10 12)(font "Arial" ))
|
||||
(text "clk" (rect 21 27 31 39)(font "Arial" ))
|
||||
(line (pt 0 32)(pt 16 32)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "address[address_bus_width-1..0]" (rect 0 0 129 12)(font "Arial" ))
|
||||
(text "address[address_bus_width-1..0]" (rect 21 43 150 55)(font "Arial" ))
|
||||
(line (pt 0 48)(pt 16 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "we" (rect 0 0 10 12)(font "Arial" ))
|
||||
(text "we" (rect 21 59 31 71)(font "Arial" ))
|
||||
(line (pt 0 64)(pt 16 64)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 80)
|
||||
(input)
|
||||
(text "oe" (rect 0 0 9 12)(font "Arial" ))
|
||||
(text "oe" (rect 21 75 30 87)(font "Arial" ))
|
||||
(line (pt 0 80)(pt 16 80)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "ce" (rect 0 0 9 12)(font "Arial" ))
|
||||
(text "ce" (rect 21 91 30 103)(font "Arial" ))
|
||||
(line (pt 0 96)(pt 16 96)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "er0_in" (rect 0 0 24 12)(font "Arial" ))
|
||||
(text "er0_in" (rect 21 107 45 119)(font "Arial" ))
|
||||
(line (pt 0 112)(pt 16 112)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 328 48)
|
||||
(output)
|
||||
(text "leds[3..0]" (rect 0 0 35 12)(font "Arial" ))
|
||||
(text "leds[3..0]" (rect 272 43 307 55)(font "Arial" ))
|
||||
(line (pt 328 48)(pt 312 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 328 64)
|
||||
(output)
|
||||
(text "er0_out" (rect 0 0 30 12)(font "Arial" ))
|
||||
(text "er0_out" (rect 277 59 307 71)(font "Arial" ))
|
||||
(line (pt 328 64)(pt 312 64)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 328 32)
|
||||
(bidir)
|
||||
(text "data[data_bus_width-1..0]" (rect 0 0 99 12)(font "Arial" ))
|
||||
(text "data[data_bus_width-1..0]" (rect 208 27 307 39)(font "Arial" ))
|
||||
(line (pt 328 32)(pt 312 32)(line_width 3))
|
||||
)
|
||||
(parameter
|
||||
"REG_ADDR_TEST_LOWER_BYTE"
|
||||
"72"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(parameter
|
||||
"REG_ADDR_TEST_UPPER_BYTE"
|
||||
"73"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(parameter
|
||||
"REG_ADDR_LEDS_LOWER_BYTE"
|
||||
"74"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(parameter
|
||||
"REG_ADDR_LEDS_UPPER_BYTE"
|
||||
"75"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(parameter
|
||||
"DATA_BUS_WIDTH"
|
||||
"8"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(parameter
|
||||
"ADDRESS_BUS_WIDTH"
|
||||
"9"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(drawing
|
||||
(rectangle (rect 16 16 312 128)(line_width 1))
|
||||
)
|
||||
(annotation_block (parameter)(rect 344 -64 444 16))
|
||||
)
|
||||
@ -1,87 +0,0 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity RAM9X8_TEST is
|
||||
generic(
|
||||
REG_ADDR_TEST_LOWER_BYTE : integer := 72;
|
||||
REG_ADDR_TEST_UPPER_BYTE : integer := 73;
|
||||
REG_ADDR_LEDS_LOWER_BYTE : integer := 74;
|
||||
REG_ADDR_LEDS_UPPER_BYTE : integer := 75;
|
||||
|
||||
DATA_BUS_WIDTH : integer := 8;
|
||||
ADDRESS_BUS_WIDTH : integer := 9
|
||||
);
|
||||
|
||||
port(
|
||||
clk : in std_logic;
|
||||
|
||||
data : inout std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
|
||||
address : in std_logic_vector(ADDRESS_BUS_WIDTH - 1 downto 0);
|
||||
we : in std_logic;
|
||||
oe : in std_logic;
|
||||
ce : in std_logic;
|
||||
|
||||
er0_in : in std_logic;
|
||||
leds : out std_logic_vector(3 downto 0);
|
||||
er0_out : out std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture behavorial of RAM9X8_TEST is
|
||||
|
||||
signal ledsBuf : std_logic_vector(15 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
|
||||
process (we, oe, ce)
|
||||
variable addr : integer range 0 to 2**ADDRESS_BUS_WIDTH - 1 := 0;
|
||||
begin
|
||||
if (ce = '0') then -- Если микросхема выбрана
|
||||
addr := conv_integer(address);
|
||||
if (addr = REG_ADDR_TEST_UPPER_BYTE or addr = REG_ADDR_TEST_LOWER_BYTE
|
||||
or addr = REG_ADDR_LEDS_LOWER_BYTE or addr = REG_ADDR_LEDS_UPPER_BYTE) then
|
||||
if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет
|
||||
case addr is
|
||||
when REG_ADDR_TEST_UPPER_BYTE =>
|
||||
data <= (others => '0');
|
||||
when REG_ADDR_TEST_LOWER_BYTE =>
|
||||
data(7 downto 1) <= (others => '0');
|
||||
data(0) <= er0_in;
|
||||
when REG_ADDR_LEDS_UPPER_BYTE =>
|
||||
data <= ledsBuf(15 downto 8);
|
||||
when REG_ADDR_LEDS_LOWER_BYTE =>
|
||||
data <= ledsBuf(7 downto 0);
|
||||
when others =>
|
||||
data <= (others => 'Z'); -- Запретить запись на шину
|
||||
end case;
|
||||
elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет
|
||||
case addr is
|
||||
when REG_ADDR_LEDS_UPPER_BYTE =>
|
||||
ledsBuf(15 downto 8) <= data;
|
||||
when REG_ADDR_LEDS_LOWER_BYTE =>
|
||||
ledsBuf(7 downto 0) <= data;
|
||||
when others =>
|
||||
data <= (others => 'Z'); -- Запретить запись на шину
|
||||
end case;
|
||||
else
|
||||
data <= (others => 'Z'); -- Запретить запись на шину
|
||||
end if;
|
||||
else
|
||||
data <= (others => 'Z'); -- Запретить запись на шину
|
||||
end if;
|
||||
else
|
||||
data <= (others => 'Z'); -- Запретить запись на шину
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
leds <= ledsBuf(3 downto 0);
|
||||
er0_out <= ledsBuf(15);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end behavorial;
|
||||
89
MainController/TestLedsController.bsf
Normal file
89
MainController/TestLedsController.bsf
Normal file
@ -0,0 +1,89 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 16 16 320 160)
|
||||
(text "TestLedsController" (rect 5 0 80 12)(font "Arial" ))
|
||||
(text "inst" (rect 8 128 20 140)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "clk" (rect 0 0 10 12)(font "Arial" ))
|
||||
(text "clk" (rect 21 27 31 39)(font "Arial" ))
|
||||
(line (pt 0 32)(pt 16 32)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "address_device[address_device_bus_width-1..0]" (rect 0 0 193 12)(font "Arial" ))
|
||||
(text "address_device[address_device_bus_width-1..0]" (rect 21 43 214 55)(font "Arial" ))
|
||||
(line (pt 0 48)(pt 16 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "asyncline" (rect 0 0 36 12)(font "Arial" ))
|
||||
(text "asyncline" (rect 21 59 57 71)(font "Arial" ))
|
||||
(line (pt 0 64)(pt 16 64)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 80)
|
||||
(input)
|
||||
(text "divclk" (rect 0 0 22 12)(font "Arial" ))
|
||||
(text "divclk" (rect 21 75 43 87)(font "Arial" ))
|
||||
(line (pt 0 80)(pt 16 80)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "errors[1..0]" (rect 0 0 43 12)(font "Arial" ))
|
||||
(text "errors[1..0]" (rect 21 91 64 103)(font "Arial" ))
|
||||
(line (pt 0 96)(pt 16 96)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "done" (rect 0 0 18 12)(font "Arial" ))
|
||||
(text "done" (rect 21 107 39 119)(font "Arial" ))
|
||||
(line (pt 0 112)(pt 16 112)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 304 32)
|
||||
(output)
|
||||
(text "led" (rect 0 0 10 12)(font "Arial" ))
|
||||
(text "led" (rect 273 27 283 39)(font "Arial" ))
|
||||
(line (pt 304 32)(pt 288 32)(line_width 1))
|
||||
)
|
||||
(parameter
|
||||
"ADDRESS_DEVICE_BUS_WIDTH"
|
||||
"5"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(parameter
|
||||
"COUNT_ASYNCLINE"
|
||||
"15"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(drawing
|
||||
(rectangle (rect 16 16 288 128)(line_width 1))
|
||||
)
|
||||
(annotation_block (parameter)(rect 320 -64 420 16))
|
||||
)
|
||||
128
MainController/TestLedsController.vhd
Normal file
128
MainController/TestLedsController.vhd
Normal file
@ -0,0 +1,128 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity TestLedsController is
|
||||
generic(
|
||||
ADDRESS_DEVICE_BUS_WIDTH : integer := 5;
|
||||
COUNT_ASYNCLINE : integer := 15
|
||||
);
|
||||
|
||||
port(
|
||||
clk : in std_logic;
|
||||
|
||||
address_device : in std_logic_vector(ADDRESS_DEVICE_BUS_WIDTH - 1 downto 0);
|
||||
asyncline : in std_logic;
|
||||
divclk : in std_logic;
|
||||
errors : in std_logic_vector(1 downto 0);
|
||||
done : in std_logic;
|
||||
led : out std_logic := '0'
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture behavorial of TestLedsController is
|
||||
|
||||
signal address_received : std_logic_vector(ADDRESS_DEVICE_BUS_WIDTH - 1 downto 0) := (others => '0');
|
||||
|
||||
signal ledBuf : std_logic := '0';
|
||||
|
||||
type CommunicationStateType is (Waiting, ReceiveData, CheckAddress, Timeout);
|
||||
signal CommunicationState: CommunicationStateType := Waiting;
|
||||
|
||||
type LedStateType is (Preparing, Ready, InternalError, ExternalError);
|
||||
signal LedState : LedStateType := Preparing;
|
||||
|
||||
begin
|
||||
|
||||
process(clk) is
|
||||
variable count : integer range 0 to COUNT_ASYNCLINE := 0;
|
||||
variable countbits : integer range -1 to ADDRESS_DEVICE_BUS_WIDTH - 1 := ADDRESS_DEVICE_BUS_WIDTH - 1;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
case CommunicationState is
|
||||
when Waiting =>
|
||||
if asyncline = '0' then
|
||||
CommunicationState <= ReceiveData;
|
||||
end if;
|
||||
count := 0;
|
||||
countbits := ADDRESS_DEVICE_BUS_WIDTH - 1;
|
||||
|
||||
when ReceiveData =>
|
||||
if countbits >= 0 then
|
||||
if count < COUNT_ASYNCLINE then
|
||||
count := count + 1;
|
||||
else
|
||||
count := 0;
|
||||
address_received(countbits) <= asyncline;
|
||||
countbits := countbits - 1;
|
||||
end if;
|
||||
else
|
||||
CommunicationState <= CheckAddress;
|
||||
countbits := ADDRESS_DEVICE_BUS_WIDTH - 1;
|
||||
end if;
|
||||
|
||||
when CheckAddress =>
|
||||
if count < COUNT_ASYNCLINE then
|
||||
count := count + 1;
|
||||
else
|
||||
if address_device = address_received then
|
||||
ledBuf <= asyncline;
|
||||
end if;
|
||||
count := 0;
|
||||
CommunicationState <= Timeout;
|
||||
end if;
|
||||
|
||||
when Timeout =>
|
||||
if count < COUNT_ASYNCLINE then
|
||||
count := count + 1;
|
||||
else
|
||||
CommunicationState <= Waiting;
|
||||
end if;
|
||||
|
||||
when others =>
|
||||
CommunicationState <= Waiting;
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk) is
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
case LedState is
|
||||
when Preparing =>
|
||||
led <= ledBuf;
|
||||
if Done = '1' then
|
||||
LedState <= Ready;
|
||||
end if;
|
||||
|
||||
when Ready =>
|
||||
led <= '1';
|
||||
if errors(1) = '1' then
|
||||
LedState <= InternalError;
|
||||
else
|
||||
if errors(0) = '1' then
|
||||
LedState <= ExternalError;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when InternalError =>
|
||||
led <= divclk;
|
||||
if errors(1) = '0' then
|
||||
LedState <= Ready;
|
||||
end if;
|
||||
|
||||
when ExternalError =>
|
||||
led <= asyncline;
|
||||
if errors(0) = '0' then
|
||||
LedState <= Ready;
|
||||
end if;
|
||||
|
||||
when others =>
|
||||
LedState <= Preparing;
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end behavorial;
|
||||
Loading…
Reference in New Issue
Block a user