Три блока на шине: PWM, LedController и TEST. В TEST можно прочитать линию Er0_in, а так же управлять светодиодами FPGA_LEDS с пятого по второй. Первый сетодиод остался как индикатор работы ПЛИС.
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@ -225,7 +225,7 @@ applicable agreement for further details.
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|
||||
(pt 1000 2184)
|
||||
(pt 1048 2184)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 984 2200)
|
||||
(pt 1048 2200)
|
||||
)
|
||||
(connector
|
||||
(pt 968 2216)
|
||||
(pt 1048 2216)
|
||||
)
|
||||
(connector
|
||||
(pt 952 2232)
|
||||
(pt 1048 2232)
|
||||
)
|
||||
(connector
|
||||
(pt 1496 2168)
|
||||
(pt 1376 2168)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 608 2168)
|
||||
(pt 1048 2168)
|
||||
)
|
||||
(connector
|
||||
(pt 904 -32)
|
||||
(pt 904 2248)
|
||||
)
|
||||
(connector
|
||||
(pt 904 2248)
|
||||
(pt 1048 2248)
|
||||
)
|
||||
(connector
|
||||
(pt 800 -32)
|
||||
(pt 904 -32)
|
||||
)
|
||||
(connector
|
||||
(pt 904 -32)
|
||||
(pt 1040 -32)
|
||||
)
|
||||
(connector
|
||||
(pt 1000 1448)
|
||||
(pt 1000 1928)
|
||||
@ -3127,7 +3281,7 @@ applicable agreement for further details.
|
||||
)
|
||||
(connector
|
||||
(pt 1000 1928)
|
||||
(pt 1000 2112)
|
||||
(pt 1000 2184)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
@ -3136,7 +3290,7 @@ applicable agreement for further details.
|
||||
)
|
||||
(connector
|
||||
(pt 984 1944)
|
||||
(pt 984 2128)
|
||||
(pt 984 2200)
|
||||
)
|
||||
(connector
|
||||
(pt 968 1480)
|
||||
@ -3144,7 +3298,7 @@ applicable agreement for further details.
|
||||
)
|
||||
(connector
|
||||
(pt 968 1960)
|
||||
(pt 968 2144)
|
||||
(pt 968 2216)
|
||||
)
|
||||
(connector
|
||||
(pt 952 1496)
|
||||
@ -3152,16 +3306,67 @@ applicable agreement for further details.
|
||||
)
|
||||
(connector
|
||||
(pt 952 1976)
|
||||
(pt 952 2160)
|
||||
(pt 952 2232)
|
||||
)
|
||||
(connector
|
||||
(pt 608 1432)
|
||||
(pt 608 1512)
|
||||
(pt 1496 1432)
|
||||
(pt 1496 2112)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 1496 2112)
|
||||
(pt 1496 2168)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 608 1512)
|
||||
(pt 608 1912)
|
||||
)
|
||||
(connector
|
||||
(pt 608 1912)
|
||||
(pt 608 2168)
|
||||
)
|
||||
(connector
|
||||
(text "leds[3..0]" (rect 1386 2168 1432 2180)(font "Arial" ))
|
||||
(pt 1376 2184)
|
||||
(pt 1784 2184)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "leds[0]" (rect 1794 2168 1827 2180)(font "Arial" ))
|
||||
(pt 1784 2184)
|
||||
(pt 1856 2184)
|
||||
)
|
||||
(connector
|
||||
(pt 1784 2184)
|
||||
(pt 1784 2200)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "leds[1]" (rect 1794 2184 1827 2196)(font "Arial" ))
|
||||
(pt 1784 2200)
|
||||
(pt 1856 2200)
|
||||
)
|
||||
(connector
|
||||
(text "leds[2]" (rect 1794 2200 1827 2212)(font "Arial" ))
|
||||
(pt 1784 2216)
|
||||
(pt 1856 2216)
|
||||
)
|
||||
(connector
|
||||
(pt 1784 2200)
|
||||
(pt 1784 2216)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 1784 2216)
|
||||
(pt 1784 2232)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "leds[3]" (rect 1794 2216 1827 2228)(font "Arial" ))
|
||||
(pt 1856 2232)
|
||||
(pt 1784 2232)
|
||||
)
|
||||
(junction (pt 1000 288))
|
||||
(junction (pt 984 304))
|
||||
(junction (pt 968 320))
|
||||
@ -3213,3 +3418,10 @@ applicable agreement for further details.
|
||||
(junction (pt 968 1480))
|
||||
(junction (pt 952 1496))
|
||||
(junction (pt 608 1512))
|
||||
(junction (pt 1496 1432))
|
||||
(junction (pt 1496 2112))
|
||||
(junction (pt 608 1912))
|
||||
(junction (pt 904 -32))
|
||||
(junction (pt 1784 2184))
|
||||
(junction (pt 1784 2200))
|
||||
(junction (pt 1784 2216))
|
||||
|
||||
@ -313,4 +313,9 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HWPdatain[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HWPdatain[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OBclk
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OBdata
|
||||
set_global_assignment -name VHDL_FILE RAM9X8_TEST.vhd
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_LED_4
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_LED_5
|
||||
set_location_assignment PIN_169 -to FPGA_LED_4
|
||||
set_location_assignment PIN_171 -to FPGA_LED_5
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
116
MainController/RAM9X8_TEST.bsf
Normal file
116
MainController/RAM9X8_TEST.bsf
Normal file
@ -0,0 +1,116 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 16 16 344 160)
|
||||
(text "RAM9X8_TEST" (rect 5 0 75 12)(font "Arial" ))
|
||||
(text "inst" (rect 8 128 20 140)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "clk" (rect 0 0 10 12)(font "Arial" ))
|
||||
(text "clk" (rect 21 27 31 39)(font "Arial" ))
|
||||
(line (pt 0 32)(pt 16 32)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "address[address_bus_width-1..0]" (rect 0 0 129 12)(font "Arial" ))
|
||||
(text "address[address_bus_width-1..0]" (rect 21 43 150 55)(font "Arial" ))
|
||||
(line (pt 0 48)(pt 16 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "we" (rect 0 0 10 12)(font "Arial" ))
|
||||
(text "we" (rect 21 59 31 71)(font "Arial" ))
|
||||
(line (pt 0 64)(pt 16 64)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 80)
|
||||
(input)
|
||||
(text "oe" (rect 0 0 9 12)(font "Arial" ))
|
||||
(text "oe" (rect 21 75 30 87)(font "Arial" ))
|
||||
(line (pt 0 80)(pt 16 80)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "ce" (rect 0 0 9 12)(font "Arial" ))
|
||||
(text "ce" (rect 21 91 30 103)(font "Arial" ))
|
||||
(line (pt 0 96)(pt 16 96)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "er0_in" (rect 0 0 24 12)(font "Arial" ))
|
||||
(text "er0_in" (rect 21 107 45 119)(font "Arial" ))
|
||||
(line (pt 0 112)(pt 16 112)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 328 48)
|
||||
(output)
|
||||
(text "leds[3..0]" (rect 0 0 35 12)(font "Arial" ))
|
||||
(text "leds[3..0]" (rect 272 43 307 55)(font "Arial" ))
|
||||
(line (pt 328 48)(pt 312 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 328 32)
|
||||
(bidir)
|
||||
(text "data[data_bus_width-1..0]" (rect 0 0 99 12)(font "Arial" ))
|
||||
(text "data[data_bus_width-1..0]" (rect 208 27 307 39)(font "Arial" ))
|
||||
(line (pt 328 32)(pt 312 32)(line_width 3))
|
||||
)
|
||||
(parameter
|
||||
"REG_ADDR_TEST_LOWER_BYTE"
|
||||
"72"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(parameter
|
||||
"REG_ADDR_TEST_UPPER_BYTE"
|
||||
"73"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(parameter
|
||||
"REG_ADDR_LEDS_LOWER_BYTE"
|
||||
"74"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(parameter
|
||||
"REG_ADDR_LEDS_UPPER_BYTE"
|
||||
"75"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(parameter
|
||||
"DATA_BUS_WIDTH"
|
||||
"8"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(parameter
|
||||
"ADDRESS_BUS_WIDTH"
|
||||
"9"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(drawing
|
||||
(rectangle (rect 16 16 312 128)(line_width 1))
|
||||
)
|
||||
(annotation_block (parameter)(rect 344 -64 444 16))
|
||||
)
|
||||
84
MainController/RAM9X8_TEST.vhd
Normal file
84
MainController/RAM9X8_TEST.vhd
Normal file
@ -0,0 +1,84 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity RAM9X8_TEST is
|
||||
generic(
|
||||
REG_ADDR_TEST_LOWER_BYTE : integer := 72;
|
||||
REG_ADDR_TEST_UPPER_BYTE : integer := 73;
|
||||
REG_ADDR_LEDS_LOWER_BYTE : integer := 74;
|
||||
REG_ADDR_LEDS_UPPER_BYTE : integer := 75;
|
||||
|
||||
DATA_BUS_WIDTH : integer := 8;
|
||||
ADDRESS_BUS_WIDTH : integer := 9
|
||||
);
|
||||
|
||||
port(
|
||||
clk : in std_logic;
|
||||
|
||||
data : inout std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
|
||||
address : in std_logic_vector(ADDRESS_BUS_WIDTH - 1 downto 0);
|
||||
we : in std_logic;
|
||||
oe : in std_logic;
|
||||
ce : in std_logic;
|
||||
|
||||
er0_in : in std_logic;
|
||||
leds : out std_logic_vector(3 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture behavorial of RAM9X8_TEST is
|
||||
|
||||
signal ledsBuf : std_logic_vector(15 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
|
||||
process (we, oe, ce)
|
||||
variable addr : integer range 0 to 2**ADDRESS_BUS_WIDTH - 1 := 0;
|
||||
begin
|
||||
if (ce = '0') then -- Если микросхема выбрана
|
||||
addr := conv_integer(address);
|
||||
if (addr = REG_ADDR_TEST_UPPER_BYTE or addr = REG_ADDR_TEST_LOWER_BYTE) then
|
||||
if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет
|
||||
case addr is
|
||||
when REG_ADDR_TEST_UPPER_BYTE =>
|
||||
data <= (others => '0');
|
||||
when REG_ADDR_TEST_LOWER_BYTE =>
|
||||
data(7 downto 1) <= (others => '0');
|
||||
data(0) <= er0_in;
|
||||
when REG_ADDR_LEDS_UPPER_BYTE =>
|
||||
data <= ledsBuf(15 downto 8);
|
||||
when REG_ADDR_LEDS_LOWER_BYTE =>
|
||||
data <= ledsBuf(7 downto 0);
|
||||
when others =>
|
||||
data <= (others => 'Z'); -- Запретить запись на шину
|
||||
end case;
|
||||
elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет
|
||||
case addr is
|
||||
when REG_ADDR_LEDS_UPPER_BYTE =>
|
||||
ledsBuf(15 downto 8) <= data;
|
||||
when REG_ADDR_LEDS_LOWER_BYTE =>
|
||||
ledsBuf(7 downto 0) <= data;
|
||||
when others =>
|
||||
data <= (others => 'Z'); -- Запретить запись на шину
|
||||
end case;
|
||||
else
|
||||
data <= (others => 'Z'); -- Запретить запись на шину
|
||||
end if;
|
||||
else
|
||||
data <= (others => 'Z'); -- Запретить запись на шину
|
||||
end if;
|
||||
else
|
||||
data <= (others => 'Z'); -- Запретить запись на шину
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
leds <= ledsBuf(3 downto 0);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end behavorial;
|
||||
Binary file not shown.
Loading…
Reference in New Issue
Block a user