118 lines
3.3 KiB
VHDL
118 lines
3.3 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity RAM9X8_Loader is
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generic(
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REG_ADDR_LOADER_UPPER_BYTE : integer := 42;
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REG_ADDR_LOADER_LOWER_BYTE : integer := 43;
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DATA_BUS_WIDTH : integer := 8;
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ADDRESS_BUS_WIDTH : integer := 9
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);
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port(
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clk : in std_logic;
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data : inout std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
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address : in std_logic_vector(ADDRESS_BUS_WIDTH - 1 downto 0);
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we : in std_logic;
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oe : in std_logic;
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ce : in std_logic;
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addrDevice : out std_logic_vector(3 downto 0) := (others => '0');
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clkLoader : out std_logic := '0';
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rwLoader : out std_logic := '0';
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resetLoader : out std_logic := '0';
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dataOutLoader : out std_logic := '0';
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loadMode : out std_logic := '0';
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dataInLoader : in std_logic;
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error : in std_logic;
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hwpclk : in std_logic;
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hwpdata : in std_logic;
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pbclk : in std_logic
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);
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end entity;
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architecture behavorial of RAM9X8_Loader is
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signal loaderBuf : std_logic_vector(15 downto 0) := (others => '1');
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signal sel : std_logic := '0';
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begin
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process (we, oe, ce)
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variable addr : integer range 0 to 2**ADDRESS_BUS_WIDTH - 1 := 0;
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begin
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if (ce = '0') then -- Если микросхема выбрана
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addr := conv_integer(address);
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if (addr = REG_ADDR_LOADER_UPPER_BYTE or addr = REG_ADDR_LOADER_LOWER_BYTE) then
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if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет
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case addr is
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when REG_ADDR_LOADER_UPPER_BYTE =>
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data(7) <= dataInLoader;
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data(6 downto 0) <= loaderBuf(14 downto 8);
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when REG_ADDR_LOADER_LOWER_BYTE =>
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data <= loaderBuf(7 downto 0);
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when others =>
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data <= (others => 'Z'); -- Запретить запись на шину
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end case;
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elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет
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case addr is
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when REG_ADDR_LOADER_UPPER_BYTE =>
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loaderBuf(15 downto 8) <= data;
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when REG_ADDR_LOADER_LOWER_BYTE =>
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loaderBuf(7 downto 0) <= data;
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when others =>
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data <= (others => 'Z'); -- Запретить запись на шину
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end case;
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else
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data <= (others => 'Z'); -- Запретить запись на шину
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end if;
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else
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data <= (others => 'Z'); -- Запретить запись на шину
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end if;
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else
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data <= (others => 'Z'); -- Запретить запись на шину
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end if;
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end process;
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process(clk) is
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begin
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if rising_edge(clk) then
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loadMode <= loaderBuf(0);
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if loaderBuf(4) = '1' and loaderBuf(0) = '1' then
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sel <= '0';
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else
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sel <= '1';
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end if;
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end if;
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end process;
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process(clk) is
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begin
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if rising_edge(clk) then
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case sel is
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when '0' =>
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addrDevice(3) <= pbclk;
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addrDevice(2) <= '1';
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addrDevice(1) <= '1';
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addrDevice(0) <= hwpdata;
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clkLoader <= hwpclk;
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dataOutLoader <= error;
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rwLoader <= '1';
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resetLoader <= '1';
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when '1' =>
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addrDevice <= loaderBuf(14 downto 11);
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clkLoader <= not loaderBuf(9);
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dataOutLoader <= not loaderBuf(7);
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rwLoader <= loaderBuf(4);
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resetLoader <= loaderBuf(1);
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when others =>
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end case;
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end if;
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end process;
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end behavorial;
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