Добавил в проект RAM9X8_Loader.

This commit is contained in:
sokolovstanislav 2024-04-03 15:17:28 +03:00
parent 51ae2e64a4
commit 6840fdc8d8
4 changed files with 908 additions and 119 deletions

View File

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(pt 608 -16)
)
(connector
(pt 608 -16)
(pt 608 32)
)
(connector
(pt 1040 -32)
(pt 800 -32)
)
(connector
(pt 544 -32)
(pt 704 -32)
)
(connector
(pt 1040 32)
(pt 1032 32)
)
(connector
(pt 1440 80)
(pt 1032 80)
)
(connector
(pt 1440 912)
(pt 1440 80)
)
(connector
(pt 1032 32)
(pt 1032 80)
)
(junction (pt 1000 288))
(junction (pt 984 304))
(junction (pt 968 320))
@ -2095,8 +2569,6 @@ applicable agreement for further details.
(junction (pt 1568 504))
(junction (pt 1544 472))
(junction (pt 608 408))
(junction (pt 1712 0))
(junction (pt 1712 64))
(junction (pt 608 976))
(junction (pt 1000 912))
(junction (pt 984 928))
@ -2108,3 +2580,14 @@ applicable agreement for further details.
(junction (pt 984 1464))
(junction (pt 968 1480))
(junction (pt 952 1496))
(junction (pt 608 32))
(junction (pt 984 272))
(junction (pt 968 256))
(junction (pt 952 240))
(junction (pt 1712 16))
(junction (pt 1472 -96))
(junction (pt 608 -112))
(junction (pt 1768 -96))
(junction (pt 1768 -112))
(junction (pt 1712 72))
(junction (pt 608 -16))

View File

@ -284,4 +284,23 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AsyncLine
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DivClk
set_location_assignment PIN_70 -to DivClk
set_location_assignment PIN_69 -to AsyncLine
set_global_assignment -name VHDL_FILE RAM9X8_Loader.vhd
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AddrDevice_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AddrDevice_2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HWPCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Error0In
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Error0Out
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HWPDATA
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LoadMode
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Reset
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RW
set_location_assignment PIN_50 -to HWPCLK
set_location_assignment PIN_45 -to Error0In
set_location_assignment PIN_41 -to Error0Out
set_location_assignment PIN_12 -to LoadMode
set_location_assignment PIN_65 -to RW
set_location_assignment PIN_64 -to Reset
set_location_assignment PIN_9 -to HWPDATA
set_location_assignment PIN_6 -to AddrDevice_1
set_location_assignment PIN_5 -to AddrDevice_2
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

View File

@ -0,0 +1,169 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 344 224)
(text "RAM9X8_Loader" (rect 5 0 79 12)(font "Arial" ))
(text "inst" (rect 8 192 20 204)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 10 12)(font "Arial" ))
(text "clk" (rect 21 27 31 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "address[address_bus_width-1..0]" (rect 0 0 129 12)(font "Arial" ))
(text "address[address_bus_width-1..0]" (rect 21 43 150 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "we" (rect 0 0 10 12)(font "Arial" ))
(text "we" (rect 21 59 31 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 0 80)
(input)
(text "oe" (rect 0 0 9 12)(font "Arial" ))
(text "oe" (rect 21 75 30 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "ce" (rect 0 0 9 12)(font "Arial" ))
(text "ce" (rect 21 91 30 103)(font "Arial" ))
(line (pt 0 96)(pt 16 96)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "dataInLoader" (rect 0 0 51 12)(font "Arial" ))
(text "dataInLoader" (rect 21 107 72 119)(font "Arial" ))
(line (pt 0 112)(pt 16 112)(line_width 1))
)
(port
(pt 0 128)
(input)
(text "error" (rect 0 0 20 12)(font "Arial" ))
(text "error" (rect 21 123 41 135)(font "Arial" ))
(line (pt 0 128)(pt 16 128)(line_width 1))
)
(port
(pt 0 144)
(input)
(text "hwpclk" (rect 0 0 25 12)(font "Arial" ))
(text "hwpclk" (rect 21 139 46 151)(font "Arial" ))
(line (pt 0 144)(pt 16 144)(line_width 1))
)
(port
(pt 0 160)
(input)
(text "hwpdata" (rect 0 0 31 12)(font "Arial" ))
(text "hwpdata" (rect 21 155 52 167)(font "Arial" ))
(line (pt 0 160)(pt 16 160)(line_width 1))
)
(port
(pt 0 176)
(input)
(text "pbclk" (rect 0 0 20 12)(font "Arial" ))
(text "pbclk" (rect 21 171 41 183)(font "Arial" ))
(line (pt 0 176)(pt 16 176)(line_width 1))
)
(port
(pt 328 48)
(output)
(text "addrDevice[3..0]" (rect 0 0 66 12)(font "Arial" ))
(text "addrDevice[3..0]" (rect 241 43 307 55)(font "Arial" ))
(line (pt 328 48)(pt 312 48)(line_width 3))
)
(port
(pt 328 64)
(output)
(text "clkLoader" (rect 0 0 38 12)(font "Arial" ))
(text "clkLoader" (rect 269 59 307 71)(font "Arial" ))
(line (pt 328 64)(pt 312 64)(line_width 1))
)
(port
(pt 328 80)
(output)
(text "rwLoader" (rect 0 0 37 12)(font "Arial" ))
(text "rwLoader" (rect 270 75 307 87)(font "Arial" ))
(line (pt 328 80)(pt 312 80)(line_width 1))
)
(port
(pt 328 96)
(output)
(text "resetLoader" (rect 0 0 48 12)(font "Arial" ))
(text "resetLoader" (rect 259 91 307 103)(font "Arial" ))
(line (pt 328 96)(pt 312 96)(line_width 1))
)
(port
(pt 328 112)
(output)
(text "dataOutLoader" (rect 0 0 59 12)(font "Arial" ))
(text "dataOutLoader" (rect 248 107 307 119)(font "Arial" ))
(line (pt 328 112)(pt 312 112)(line_width 1))
)
(port
(pt 328 128)
(output)
(text "loadMode" (rect 0 0 37 12)(font "Arial" ))
(text "loadMode" (rect 270 123 307 135)(font "Arial" ))
(line (pt 328 128)(pt 312 128)(line_width 1))
)
(port
(pt 328 32)
(bidir)
(text "data[data_bus_width-1..0]" (rect 0 0 99 12)(font "Arial" ))
(text "data[data_bus_width-1..0]" (rect 208 27 307 39)(font "Arial" ))
(line (pt 328 32)(pt 312 32)(line_width 3))
)
(parameter
"REG_ADDR_LOADER_UPPER_BYTE"
"42"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_LOADER_LOWER_BYTE"
"43"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"DATA_BUS_WIDTH"
"8"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"ADDRESS_BUS_WIDTH"
"9"
""
(type "PARAMETER_SIGNED_DEC") )
(drawing
(rectangle (rect 16 16 312 192)(line_width 1))
)
(annotation_block (parameter)(rect 344 -64 444 16))
)

View File

@ -0,0 +1,118 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity RAM9X8_Loader is
generic(
REG_ADDR_LOADER_UPPER_BYTE : integer := 42;
REG_ADDR_LOADER_LOWER_BYTE : integer := 43;
DATA_BUS_WIDTH : integer := 8;
ADDRESS_BUS_WIDTH : integer := 9
);
port(
clk : in std_logic;
data : inout std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
address : in std_logic_vector(ADDRESS_BUS_WIDTH - 1 downto 0);
we : in std_logic;
oe : in std_logic;
ce : in std_logic;
addrDevice : out std_logic_vector(3 downto 0) := (others => '0');
clkLoader : out std_logic := '0';
rwLoader : out std_logic := '0';
resetLoader : out std_logic := '0';
dataOutLoader : out std_logic := '0';
loadMode : out std_logic := '0';
dataInLoader : in std_logic;
error : in std_logic;
hwpclk : in std_logic;
hwpdata : in std_logic;
pbclk : in std_logic
);
end entity;
architecture behavorial of RAM9X8_Loader is
signal loaderBuf : std_logic_vector(15 downto 0) := (others => '1');
signal sel : std_logic := '0';
begin
process (we, oe, ce)
variable addr : integer range 0 to 2**ADDRESS_BUS_WIDTH - 1 := 0;
begin
if (ce = '0') then -- Если микросхема выбрана
addr := conv_integer(address);
if (addr = REG_ADDR_LOADER_UPPER_BYTE or addr = REG_ADDR_LOADER_LOWER_BYTE) then
if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет
case addr is
when REG_ADDR_LOADER_UPPER_BYTE =>
data(7) <= dataInLoader;
data(6 downto 0) <= loaderBuf(14 downto 8);
when REG_ADDR_LOADER_LOWER_BYTE =>
data <= loaderBuf(7 downto 0);
when others =>
data <= (others => 'Z'); -- Запретить запись на шину
end case;
elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет
case addr is
when REG_ADDR_LOADER_UPPER_BYTE =>
loaderBuf(15 downto 8) <= data;
when REG_ADDR_LOADER_LOWER_BYTE =>
loaderBuf(7 downto 0) <= data;
when others =>
data <= (others => 'Z'); -- Запретить запись на шину
end case;
else
data <= (others => 'Z'); -- Запретить запись на шину
end if;
else
data <= (others => 'Z'); -- Запретить запись на шину
end if;
else
data <= (others => 'Z'); -- Запретить запись на шину
end if;
end process;
process(clk) is
begin
if rising_edge(clk) then
loadMode <= loaderBuf(0);
if loaderBuf(4) = '1' and loaderBuf(0) = '1' then
sel <= '0';
else
sel <= '1';
end if;
end if;
end process;
process(clk) is
begin
if rising_edge(clk) then
case sel is
when '0' =>
addrDevice(3) <= pbclk;
addrDevice(2) <= '1';
addrDevice(1) <= '1';
addrDevice(0) <= hwpdata;
clkLoader <= hwpclk;
dataOutLoader <= error;
rwLoader <= '1';
resetLoader <= '1';
when '1' =>
addrDevice <= loaderBuf(14 downto 11);
clkLoader <= not loaderBuf(9);
dataOutLoader <= not loaderBuf(7);
rwLoader <= loaderBuf(4);
resetLoader <= loaderBuf(1);
when others =>
end case;
end if;
end process;
end behavorial;