altera/MainController/RAM9X8_TEST.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
  
entity RAM9X8_TEST is	
	generic(
		REG_ADDR_TEST_LOWER_BYTE : integer := 72;
		REG_ADDR_TEST_UPPER_BYTE : integer := 73;
		REG_ADDR_LEDS_LOWER_BYTE : integer := 74;
		REG_ADDR_LEDS_UPPER_BYTE : integer := 75;
		
		DATA_BUS_WIDTH : integer := 8;
		ADDRESS_BUS_WIDTH : integer := 9
	);
	
	port(
		clk : in std_logic;
		
		data : inout std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
		address : in std_logic_vector(ADDRESS_BUS_WIDTH - 1 downto 0);
		we : in std_logic;
		oe : in std_logic;
		ce : in std_logic;
		
		er0_in : in std_logic;
		leds : out std_logic_vector(3 downto 0);
		er0_out : out std_logic
	); 
end entity;

architecture behavorial of RAM9X8_TEST is

signal ledsBuf : std_logic_vector(15 downto 0) := (others => '0');

begin	

	process (we, oe, ce)
		variable addr : integer range 0 to 2**ADDRESS_BUS_WIDTH - 1 := 0;
	begin
		if (ce = '0') then  -- Если микросхема выбрана
			addr := conv_integer(address);
			if (addr = REG_ADDR_TEST_UPPER_BYTE or addr = REG_ADDR_TEST_LOWER_BYTE
				or addr = REG_ADDR_LEDS_LOWER_BYTE or addr = REG_ADDR_LEDS_UPPER_BYTE) then
				if (oe = '0' and we = '1') then  -- Если сигнал чтения активен, а записи нет	
					case addr is
						when REG_ADDR_TEST_UPPER_BYTE =>
							data <= (others => '0');
						when REG_ADDR_TEST_LOWER_BYTE =>
							data(7 downto 1) <= (others => '0');
							data(0) <= er0_in;
						when REG_ADDR_LEDS_UPPER_BYTE =>
							data <= ledsBuf(15 downto 8);
						when REG_ADDR_LEDS_LOWER_BYTE =>
							data <= ledsBuf(7 downto 0);	
						when others => 
							data <= (others => 'Z');  -- Запретить запись на шину
					end case;				
				elsif (oe = '1' and we = '0') then  -- Если сигнал записи активен, а чтения нет
					case addr is
						when REG_ADDR_LEDS_UPPER_BYTE =>
							ledsBuf(15 downto 8) <= data;
						when REG_ADDR_LEDS_LOWER_BYTE =>	
							ledsBuf(7 downto 0) <= data;
						when others =>
							data <= (others => 'Z');  -- Запретить запись на шину
					end case;
				else
					data <= (others => 'Z');  -- Запретить запись на шину
				end if;
			else 
				data <= (others => 'Z');  -- Запретить запись на шину
			end if;	
		else
			data <= (others => 'Z');  -- Запретить запись на шину
		end if;
	end process;
	
	process(clk)
	begin
		if rising_edge(clk) then	
			leds <= ledsBuf(3 downto 0);
			er0_out <= ledsBuf(15);
		end if;
	end process;
	
end behavorial;