43 lines
1.1 KiB
VHDL
43 lines
1.1 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity RAM is
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port(
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clk : in std_logic;
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data : in std_logic_vector(15 downto 0);
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address : in std_logic_vector(7 downto 0);
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clkMCU : in std_logic;
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dataMCU : inout std_logic_vector(15 downto 0);
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addressMCU : inout std_logic_vector(7 downto 0);
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-- write when 0, read when 1
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wr : in std_logic
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);
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end entity;
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architecture behavorial of RAM is
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type mem is array (255 downto 0) of std_logic_vector(15 downto 0);
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signal memory : mem;
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signal clkMCUPrev : std_logic := '0';
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begin
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process(clk)
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variable addr : integer range 0 to 255;
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begin
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if rising_edge(clk) then
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if clkMCU = '1' and clkMCUPrev = '0' then
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addr := conv_integer(addressMCU); -- переменной addr присваивается новое значение сразу. Удобно для преобразования типов.
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if (wr = '0') then
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memory(addr) <= dataMCU; -- тут уже новое значение переменной addr
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else
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dataMCU <= memory(addr);
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end if;
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end if;
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clkMCUPrev <= clkMCU;
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end if;
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end process;
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end behavorial;
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