36 lines
597 B
VHDL
36 lines
597 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity DigitalInversion is
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port(
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clk : in STD_LOGIC;
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input : in STD_LOGIC;
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ce : in STD_LOGIC;
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output : out STD_LOGIC;
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noutput : out STD_LOGIC
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);
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end DigitalInversion;
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architecture Behavioral of DigitalInversion is
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begin
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process(clk)
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begin
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if rising_edge(clk) then
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if (ce = '1') then
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if input = '1' then
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output <= '1';
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noutput <= '0';
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else
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output <= '0';
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noutput <= '1';
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end if;
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else
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output <= 'Z';
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noutput <= 'Z';
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end if;
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end if;
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end process;
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end Behavioral;
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