Collaboration diagram for Peripheral_declaration:
Detailed Description
Macro Definition Documentation
◆ TIM2
| #define TIM2 ((TIM_TypeDef *) TIM2_BASE) |
◆ TIM3
| #define TIM3 ((TIM_TypeDef *) TIM3_BASE) |
◆ TIM4
| #define TIM4 ((TIM_TypeDef *) TIM4_BASE) |
◆ TIM5
| #define TIM5 ((TIM_TypeDef *) TIM5_BASE) |
◆ TIM6
| #define TIM6 ((TIM_TypeDef *) TIM6_BASE) |
◆ TIM7
| #define TIM7 ((TIM_TypeDef *) TIM7_BASE) |
◆ TIM12
| #define TIM12 ((TIM_TypeDef *) TIM12_BASE) |
◆ TIM13
| #define TIM13 ((TIM_TypeDef *) TIM13_BASE) |
◆ TIM14
| #define TIM14 ((TIM_TypeDef *) TIM14_BASE) |
◆ RTC
| #define RTC ((RTC_TypeDef *) RTC_BASE) |
◆ WWDG
| #define WWDG ((WWDG_TypeDef *) WWDG_BASE) |
◆ IWDG
| #define IWDG ((IWDG_TypeDef *) IWDG_BASE) |
◆ I2S2ext
| #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) |
◆ SPI2
| #define SPI2 ((SPI_TypeDef *) SPI2_BASE) |
◆ SPI3
| #define SPI3 ((SPI_TypeDef *) SPI3_BASE) |
◆ I2S3ext
| #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) |
◆ USART2
| #define USART2 ((USART_TypeDef *) USART2_BASE) |
◆ USART3
| #define USART3 ((USART_TypeDef *) USART3_BASE) |
◆ UART4
| #define UART4 ((USART_TypeDef *) UART4_BASE) |
◆ UART5
| #define UART5 ((USART_TypeDef *) UART5_BASE) |
◆ I2C1
| #define I2C1 ((I2C_TypeDef *) I2C1_BASE) |
◆ I2C2
| #define I2C2 ((I2C_TypeDef *) I2C2_BASE) |
◆ I2C3
| #define I2C3 ((I2C_TypeDef *) I2C3_BASE) |
◆ CAN1
| #define CAN1 ((CAN_TypeDef *) CAN1_BASE) |
◆ CAN2
| #define CAN2 ((CAN_TypeDef *) CAN2_BASE) |
◆ PWR
| #define PWR ((PWR_TypeDef *) PWR_BASE) |
◆ DAC1
| #define DAC1 ((DAC_TypeDef *) DAC_BASE) |
◆ DAC
| #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */ |
◆ TIM1
| #define TIM1 ((TIM_TypeDef *) TIM1_BASE) |
◆ TIM8
| #define TIM8 ((TIM_TypeDef *) TIM8_BASE) |
◆ USART1
| #define USART1 ((USART_TypeDef *) USART1_BASE) |
◆ USART6
| #define USART6 ((USART_TypeDef *) USART6_BASE) |
◆ ADC1
| #define ADC1 ((ADC_TypeDef *) ADC1_BASE) |
◆ ADC2
| #define ADC2 ((ADC_TypeDef *) ADC2_BASE) |
◆ ADC3
| #define ADC3 ((ADC_TypeDef *) ADC3_BASE) |
◆ ADC123_COMMON
| #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE) |
◆ ADC
| #define ADC ADC123_COMMON |
◆ SDIO
| #define SDIO ((SDIO_TypeDef *) SDIO_BASE) |
◆ SPI1
| #define SPI1 ((SPI_TypeDef *) SPI1_BASE) |
◆ SYSCFG
| #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) |
◆ EXTI
| #define EXTI ((EXTI_TypeDef *) EXTI_BASE) |
◆ TIM9
| #define TIM9 ((TIM_TypeDef *) TIM9_BASE) |
◆ TIM10
| #define TIM10 ((TIM_TypeDef *) TIM10_BASE) |
◆ TIM11
| #define TIM11 ((TIM_TypeDef *) TIM11_BASE) |
◆ GPIOA
| #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) |
◆ GPIOB
| #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) |
◆ GPIOC
| #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) |
◆ GPIOD
| #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) |
◆ GPIOE
| #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) |
◆ GPIOF
| #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) |
◆ GPIOG
| #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) |
◆ GPIOH
| #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) |
◆ GPIOI
| #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) |
◆ CRC
| #define CRC ((CRC_TypeDef *) CRC_BASE) |
◆ RCC
| #define RCC ((RCC_TypeDef *) RCC_BASE) |
◆ FLASH
| #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) |
◆ DMA1
| #define DMA1 ((DMA_TypeDef *) DMA1_BASE) |
◆ DMA1_Stream0
| #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) |
◆ DMA1_Stream1
| #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) |
◆ DMA1_Stream2
| #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) |
◆ DMA1_Stream3
| #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) |
◆ DMA1_Stream4
| #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) |
◆ DMA1_Stream5
| #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) |
◆ DMA1_Stream6
| #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) |
◆ DMA1_Stream7
| #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) |
◆ DMA2
| #define DMA2 ((DMA_TypeDef *) DMA2_BASE) |
◆ DMA2_Stream0
| #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) |
◆ DMA2_Stream1
| #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) |
◆ DMA2_Stream2
| #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) |
◆ DMA2_Stream3
| #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) |
◆ DMA2_Stream4
| #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) |
◆ DMA2_Stream5
| #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) |
◆ DMA2_Stream6
| #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) |
◆ DMA2_Stream7
| #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) |
◆ ETH
| #define ETH ((ETH_TypeDef *) ETH_BASE) |
◆ DCMI
| #define DCMI ((DCMI_TypeDef *) DCMI_BASE) |
◆ RNG
| #define RNG ((RNG_TypeDef *) RNG_BASE) |
◆ FSMC_Bank1
| #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) |
◆ FSMC_Bank1E
| #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) |
◆ FSMC_Bank2_3
| #define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE) |
◆ FSMC_Bank4
| #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) |
◆ DBGMCU
| #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) |
◆ USB_OTG_FS
| #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) |
◆ USB_OTG_HS
| #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) |
