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Всякие фиксы модели и заготовки для АЦП

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И почему то все равно MATLAB намертво блокирует mingw64.... Приходится перезапускать матлаб для перекомпиляции
This commit is contained in:
Razvalyaev
2025-11-09 21:04:52 +03:00
parent be84043f18
commit 79ff2667c4
74 changed files with 2371 additions and 609 deletions
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6
MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f401xc_matlab.h
View File

@@ -223,9 +223,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

6
MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f401xe_matlab.h
View File

@@ -223,9 +223,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

6
MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f405xx_matlab.h
View File

@@ -334,9 +334,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

6
MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f407xx_matlab.h
View File

@@ -358,9 +358,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

6
MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f410cx_matlab.h
View File

@@ -241,9 +241,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

6
MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f410rx_matlab.h
View File

@@ -241,9 +241,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

6
MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f410tx_matlab.h
View File

@@ -238,9 +238,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

6
MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f411xe_matlab.h
View File

@@ -224,9 +224,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

6
MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f412cx_matlab.h
View File

@@ -344,9 +344,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

6
MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f412rx_matlab.h
View File

@@ -345,9 +345,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

6
MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f412vx_matlab.h
View File

@@ -345,9 +345,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

6
MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f412zx_matlab.h
View File

@@ -345,9 +345,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

6
MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f413xx_matlab.h
View File

@@ -383,9 +383,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

6
MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f415xx_matlab.h
View File

@@ -333,9 +333,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

6
MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f417xx_matlab.h
View File

@@ -354,9 +354,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

6
MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f423xx_matlab.h
View File

@@ -384,9 +384,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

6
MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f427xx_matlab.h
View File

@@ -360,9 +360,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

6
MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f429xx_matlab.h
View File

@@ -362,9 +362,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

6
MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f437xx_matlab.h
View File

@@ -361,9 +361,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

6
MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f439xx_matlab.h
View File

@@ -363,9 +363,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

6
MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f446xx_matlab.h
View File

@@ -372,9 +372,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

6
MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f469xx_matlab.h
View File

@@ -364,9 +364,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

6
MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f479xx_matlab.h
View File

@@ -365,9 +365,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;