фикс прошивки под c3

This commit is contained in:
2026-09-23 16:42:50 +03:00
parent 1d62691973
commit ad33d0de79
4 changed files with 16 additions and 5 deletions

View File

@@ -5,6 +5,7 @@
// ------------------------- Hardware configuration ------------------------- // ------------------------- Hardware configuration -------------------------
// Enabled for the hand-wired prototype. Comment out for the production PCB. // Enabled for the hand-wired prototype. Comment out for the production PCB.
// Both profiles map S3 signals by physical header position with 5V/GND aligned. // Both profiles map S3 signals by physical header position with 5V/GND aligned.
//#define MAKETKA //#define MAKETKA
// Select exactly one populated receiver circuit. Use // Select exactly one populated receiver circuit. Use
@@ -12,7 +13,7 @@
#define BOARD_RX_INTERFACE_ADC 1 #define BOARD_RX_INTERFACE_ADC 1
#define BOARD_RX_INTERFACE_DIGITAL 2 #define BOARD_RX_INTERFACE_DIGITAL 2
#ifndef BOARD_RX_INTERFACE #ifndef BOARD_RX_INTERFACE
#define BOARD_RX_INTERFACE BOARD_RX_INTERFACE_DIGITAL #define BOARD_RX_INTERFACE BOARD_RX_INTERFACE_ADC
#endif #endif
#if BOARD_RX_INTERFACE != BOARD_RX_INTERFACE_ADC && \ #if BOARD_RX_INTERFACE != BOARD_RX_INTERFACE_ADC && \

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@@ -10,15 +10,26 @@
#include <esp32-hal-cpu.h> #include <esp32-hal-cpu.h>
#include <soc/gpio_struct.h> #include <soc/gpio_struct.h>
#include <string.h> #include <string.h>
#if CONFIG_IDF_TARGET_ESP32C3
#include <riscv/rv_utils.h>
#endif
static inline uint32_t IRAM_ATTR maskAllInterrupts() { static inline uint32_t IRAM_ATTR maskAllInterrupts() {
#if CONFIG_IDF_TARGET_ESP32C3
return RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
#else
uint32_t state; uint32_t state;
asm volatile("rsil %0, 15" : "=a"(state) :: "memory"); asm volatile("rsil %0, 15" : "=a"(state) :: "memory");
return state; return state;
#endif
} }
static inline void IRAM_ATTR restoreInterrupts(uint32_t state) { static inline void IRAM_ATTR restoreInterrupts(uint32_t state) {
#if CONFIG_IDF_TARGET_ESP32C3
RV_SET_CSR(mstatus, state & MSTATUS_MIE);
#else
asm volatile("wsr %0, ps\nrsync" :: "a"(state) : "memory"); asm volatile("wsr %0, ps\nrsync" :: "a"(state) : "memory");
#endif
} }
void DriverEdgeStats::reset() { void DriverEdgeStats::reset() {
@@ -193,7 +204,7 @@ void IRAM_ATTR DriverTest::pollTaskLoop() {
constexpr uint32_t PIN_MASK = (1UL << GPIO_PWM) | (1UL << GPIO_RX); constexpr uint32_t PIN_MASK = (1UL << GPIO_PWM) | (1UL << GPIO_RX);
for (;;) { for (;;) {
ulTaskNotifyTake(pdTRUE, portMAX_DELAY); ulTaskNotifyTake(pdTRUE, portMAX_DELAY);
uint32_t levels = GPIO.in & PIN_MASK; uint32_t levels = GPIO.in.val & PIN_MASK;
uint32_t nextStart = 0; uint32_t nextStart = 0;
uint32_t windowEnd = 0; uint32_t windowEnd = 0;
uint32_t lastTxStart = 0; uint32_t lastTxStart = 0;
@@ -205,7 +216,7 @@ void IRAM_ATTR DriverTest::pollTaskLoop() {
uint32_t interruptState = 0; uint32_t interruptState = 0;
auto sampleOnce = [&]() { auto sampleOnce = [&]() {
const uint32_t current = GPIO.in & PIN_MASK; const uint32_t current = GPIO.in.val & PIN_MASK;
if (current == levels) return; if (current == levels) return;
const uint32_t now = esp_cpu_get_cycle_count(); const uint32_t now = esp_cpu_get_cycle_count();
const uint32_t changed = current ^ levels; const uint32_t changed = current ^ levels;
@@ -636,8 +647,7 @@ void IRAM_ATTR DriverTest::recordRaw(uint32_t tick, bool rising,
return; return;
} }
ring_[write] = {tick, rising, source}; ring_[write] = {tick, rising, source};
asm volatile("memw" ::: "memory"); __atomic_store_n(&ringWrite_, next, __ATOMIC_RELEASE);
ringWrite_ = next;
} }
size_t DriverTest::readRaw(TimedEvent *events, size_t capacity, size_t DriverTest::readRaw(TimedEvent *events, size_t capacity,

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