Razvalyaev
7e0063eee0
Все основные файлы подтянуты без изменений Изменены (только папка main_matlab): - заглушки для ненужных функций (main_matlab.c) - iq библиотека (IQmathLib_matlab.c) - библиотеки DSP281x
281 lines
9.5 KiB
C
281 lines
9.5 KiB
C
#include "x_serial_bus.h"
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#include "xp_cds_tk.h"
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#include "xp_tools.h"
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///////////////////////////////////////////////
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///////////////////////////////////////////////
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///////////////////////////////////////////////
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// 10510
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///////////////////////////////////////////////
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///////////////////////////////////////////////
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int cds_tk_write_sbus_10510(T_cds_tk_10510 *v)
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{
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unsigned int old_err, err = 0, err_ready = 0;
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if (v->useit == 0)
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return 0;
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old_err = v->status_serial_bus.count_write_error;
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x_serial_bus_project.slave_addr = v->plane_address; // number plate
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//3 mask_protect_tk
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x_serial_bus_project.reg_addr = 3; // adr memory in plate
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x_serial_bus_project.write_data = v->write.sbus.mask_protect_tk.all; // write data
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if (x_serial_bus_project.write(&x_serial_bus_project)) // make write
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v->status_serial_bus.count_write_error++;
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//4 protect_error
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// if (v->read.type_cds_xilinx == TYPE_CDS_XILINX_SP6)
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// v->write.sbus.protect_error.bit.enable_err_switch = 0; // äëÿ SP6 îòêëþ÷àåì îøèáêó ïî ðàçúåìó, ò.ê. åå íåò ïîêà
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x_serial_bus_project.reg_addr = 4; // adr memory in plate
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x_serial_bus_project.write_data = v->write.sbus.protect_error.all; // write data
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if (x_serial_bus_project.write(&x_serial_bus_project)) // make write
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v->status_serial_bus.count_write_error++;
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//0 mask_tk_out_40pin
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x_serial_bus_project.reg_addr = 0; // adr memory in plate
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x_serial_bus_project.write_data = v->write.sbus.mask_tk_out_40pin.all; // write data
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if (x_serial_bus_project.write(&x_serial_bus_project)) // make write
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v->status_serial_bus.count_write_error++;
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//1 deadtime
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x_serial_bus_project.reg_addr = 1; // adr memory in plate
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x_serial_bus_project.write_data = v->write.sbus.deadtime.all; // write data
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if (x_serial_bus_project.write(&x_serial_bus_project)) // make write
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v->status_serial_bus.count_write_error++;
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//2 ack_time
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x_serial_bus_project.reg_addr = 2; // adr memory in plate
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x_serial_bus_project.write_data = v->write.sbus.ack_time.all; // write data
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if (x_serial_bus_project.write(&x_serial_bus_project)) // make write
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v->status_serial_bus.count_write_error++;
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//7 cmd_reset_error
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/*
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x_serial_bus_project.reg_addr = 7; // adr memory in plate
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x_serial_bus_project.write_data = v->write.sbus.cmd_reset_error; // write data
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if (x_serial_bus_project.write(&x_serial_bus_project)) // make write
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v->status_serial_bus.count_error++;
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*/
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//9 mintime
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x_serial_bus_project.reg_addr = 9; // adr memory in plate
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x_serial_bus_project.write_data = v->write.sbus.mintime.all; // write data
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if (x_serial_bus_project.write(&x_serial_bus_project)) // make write
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v->status_serial_bus.count_write_error++;
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if (old_err == v->status_serial_bus.count_write_error)// no errors
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{
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v->status_serial_bus.count_write_ok++;
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err = 0; // no errors
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}
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else
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err = 1; // !errors!
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err_ready = check_cds_ready_sbus( err, ITS_WRITE_BUS, &v->status_serial_bus);
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set_status_cds(err_ready, &v->status);
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return err_ready;
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}
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///////////////////////////////////////////////
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///////////////////////////////////////////////
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///////////////////////////////////////////////
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int cds_tk_read_sbus_10510(T_cds_tk_10510 *v)
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{
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unsigned int old_err, err = 0, err_ready = 0;
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if (v->useit == 0)
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return 0;
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old_err = v->status_serial_bus.count_read_error;
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x_serial_bus_project.slave_addr = v->plane_address; // number plate
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//0 mask_tk_out_40pin
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x_serial_bus_project.reg_addr = 0; // adr memory in plate
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x_serial_bus_project.read(&x_serial_bus_project); // read
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if (x_serial_bus_project.flags.bit.read_error == 0) // check error
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v->read.sbus.mask_tk_out_40pin.all = x_serial_bus_project.read_data;
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else
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v->status_serial_bus.count_read_error++;
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//1 deadtime
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x_serial_bus_project.reg_addr = 1; // adr memory in plate
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x_serial_bus_project.read(&x_serial_bus_project); // read
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if (x_serial_bus_project.flags.bit.read_error == 0) // check error
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v->read.sbus.deadtime.all = x_serial_bus_project.read_data;
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else
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v->status_serial_bus.count_read_error++;
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//2 ack_time
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x_serial_bus_project.reg_addr = 2; // adr memory in plate
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x_serial_bus_project.read(&x_serial_bus_project); // read
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if (x_serial_bus_project.flags.bit.read_error == 0) // check error
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v->read.sbus.ack_time.all = x_serial_bus_project.read_data;
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else
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v->status_serial_bus.count_read_error++;
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//3 mask_protect_tk
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x_serial_bus_project.reg_addr = 3; // adr memory in plate
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x_serial_bus_project.read(&x_serial_bus_project); // read
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if (x_serial_bus_project.flags.bit.read_error == 0) // check error
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v->read.sbus.mask_protect_tk.all = x_serial_bus_project.read_data;
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else
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v->status_serial_bus.count_read_error++;
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//4 protect_error
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x_serial_bus_project.reg_addr = 4; // adr memory in plate
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x_serial_bus_project.read(&x_serial_bus_project); // read
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if (x_serial_bus_project.flags.bit.read_error == 0) // check error
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v->read.sbus.protect_error.all = x_serial_bus_project.read_data;
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else
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v->status_serial_bus.count_read_error++;
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//5 status_tk_40pin
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x_serial_bus_project.reg_addr = 5; // adr memory in plate
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x_serial_bus_project.read(&x_serial_bus_project); // read
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if (x_serial_bus_project.flags.bit.read_error == 0) // check error
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v->read.sbus.status_tk_40pin.all = x_serial_bus_project.read_data;
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else
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v->status_serial_bus.count_read_error++;
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//6 status_tk_96pin
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x_serial_bus_project.reg_addr = 6; // adr memory in plate
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x_serial_bus_project.read(&x_serial_bus_project); // read
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if (x_serial_bus_project.flags.bit.read_error == 0) // check error
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v->read.sbus.status_tk_96pin.all = x_serial_bus_project.read_data;
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else
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v->status_serial_bus.count_read_error++;
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//7 lock_status_error
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x_serial_bus_project.reg_addr = 7; // adr memory in plate
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x_serial_bus_project.read(&x_serial_bus_project); // read
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if (x_serial_bus_project.flags.bit.read_error == 0) // check error
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v->read.sbus.lock_status_error.all = x_serial_bus_project.read_data;
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else
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v->status_serial_bus.count_read_error++;
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//8 status_protect_current_ack
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x_serial_bus_project.reg_addr = 8; // adr memory in plate
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x_serial_bus_project.read(&x_serial_bus_project); // read
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if (x_serial_bus_project.flags.bit.read_error == 0) // check error
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v->read.sbus.status_protect_current_ack.all = x_serial_bus_project.read_data;
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else
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v->status_serial_bus.count_read_error++;
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//9 mintime
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x_serial_bus_project.reg_addr = 9; // adr memory in plate
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x_serial_bus_project.read(&x_serial_bus_project); // read
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if (x_serial_bus_project.flags.bit.read_error == 0) // check error
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v->read.sbus.mintime.all = x_serial_bus_project.read_data;
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else
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v->status_serial_bus.count_read_error++;
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//10 status_protect_deadtime_mintime
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x_serial_bus_project.reg_addr = 10; // adr memory in plate
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x_serial_bus_project.read(&x_serial_bus_project); // read
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if (x_serial_bus_project.flags.bit.read_error == 0) // check error
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v->read.sbus.status_protect_deadtime_mintime.all = x_serial_bus_project.read_data;
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else
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v->status_serial_bus.count_read_error++;
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//11 time_err_tk0_tk1
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x_serial_bus_project.reg_addr = 11; // adr memory in plate
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x_serial_bus_project.read(&x_serial_bus_project); // read
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if (x_serial_bus_project.flags.bit.read_error == 0) // check error
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v->read.sbus.time_err_tk0_tk1 = x_serial_bus_project.read_data;
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else
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v->status_serial_bus.count_read_error++;
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//12 time_err_tk2_tk3
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x_serial_bus_project.reg_addr = 12; // adr memory in plate
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x_serial_bus_project.read(&x_serial_bus_project); // read
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if (x_serial_bus_project.flags.bit.read_error == 0) // check error
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v->read.sbus.time_err_tk2_tk3 = x_serial_bus_project.read_data;
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else
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v->status_serial_bus.count_read_error++;
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//13 time_err_tk4_tk5
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x_serial_bus_project.reg_addr = 13; // adr memory in plate
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x_serial_bus_project.read(&x_serial_bus_project); // read
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if (x_serial_bus_project.flags.bit.read_error == 0) // check error
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v->read.sbus.time_err_tk4_tk5 = x_serial_bus_project.read_data;
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else
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v->status_serial_bus.count_read_error++;
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//14 time_err_tk6_tk7
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x_serial_bus_project.reg_addr = 14; // adr memory in plate
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x_serial_bus_project.read(&x_serial_bus_project); // read
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if (x_serial_bus_project.flags.bit.read_error == 0) // check error
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v->read.sbus.time_err_tk6_tk7 = x_serial_bus_project.read_data;
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else
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v->status_serial_bus.count_read_error++;
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//15 current_status_error
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x_serial_bus_project.reg_addr = 15; // adr memory in plate
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x_serial_bus_project.read(&x_serial_bus_project); // read
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if (x_serial_bus_project.flags.bit.read_error == 0) // check error
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{
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v->read.type_cds_xilinx = x_serial_bus_project.read_data & 0x1;
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v->read.sbus.current_status_error.all = x_serial_bus_project.read_data & 0xfffe;
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}
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else
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v->status_serial_bus.count_read_error++;
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///////////
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if (old_err == v->status_serial_bus.count_read_error)// no errors
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{
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v->status_serial_bus.count_read_ok++;
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err = 0; // no errors
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}
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else
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err = 1; // !errors!
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err_ready = check_cds_ready_sbus( err, ITS_READ_BUS, &v->status_serial_bus);
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set_status_cds(err_ready, &v->status);
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return err_ready;
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}
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///////////////////////////////////////////////
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///////////////////////////////////////////////
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///////////////////////////////////////////////
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