#include "x_serial_bus.h" #include "xp_cds_tk.h" #include "xp_tools.h" /////////////////////////////////////////////// /////////////////////////////////////////////// /////////////////////////////////////////////// // 10510 /////////////////////////////////////////////// /////////////////////////////////////////////// int cds_tk_write_sbus_10510(T_cds_tk_10510 *v) { unsigned int old_err, err = 0, err_ready = 0; if (v->useit == 0) return 0; old_err = v->status_serial_bus.count_write_error; x_serial_bus_project.slave_addr = v->plane_address; // number plate //3 mask_protect_tk x_serial_bus_project.reg_addr = 3; // adr memory in plate x_serial_bus_project.write_data = v->write.sbus.mask_protect_tk.all; // write data if (x_serial_bus_project.write(&x_serial_bus_project)) // make write v->status_serial_bus.count_write_error++; //4 protect_error // if (v->read.type_cds_xilinx == TYPE_CDS_XILINX_SP6) // v->write.sbus.protect_error.bit.enable_err_switch = 0; // для SP6 отключаем ошибку по разъему, т.к. ее нет пока x_serial_bus_project.reg_addr = 4; // adr memory in plate x_serial_bus_project.write_data = v->write.sbus.protect_error.all; // write data if (x_serial_bus_project.write(&x_serial_bus_project)) // make write v->status_serial_bus.count_write_error++; //0 mask_tk_out_40pin x_serial_bus_project.reg_addr = 0; // adr memory in plate x_serial_bus_project.write_data = v->write.sbus.mask_tk_out_40pin.all; // write data if (x_serial_bus_project.write(&x_serial_bus_project)) // make write v->status_serial_bus.count_write_error++; //1 deadtime x_serial_bus_project.reg_addr = 1; // adr memory in plate x_serial_bus_project.write_data = v->write.sbus.deadtime.all; // write data if (x_serial_bus_project.write(&x_serial_bus_project)) // make write v->status_serial_bus.count_write_error++; //2 ack_time x_serial_bus_project.reg_addr = 2; // adr memory in plate x_serial_bus_project.write_data = v->write.sbus.ack_time.all; // write data if (x_serial_bus_project.write(&x_serial_bus_project)) // make write v->status_serial_bus.count_write_error++; //7 cmd_reset_error /* x_serial_bus_project.reg_addr = 7; // adr memory in plate x_serial_bus_project.write_data = v->write.sbus.cmd_reset_error; // write data if (x_serial_bus_project.write(&x_serial_bus_project)) // make write v->status_serial_bus.count_error++; */ //9 mintime x_serial_bus_project.reg_addr = 9; // adr memory in plate x_serial_bus_project.write_data = v->write.sbus.mintime.all; // write data if (x_serial_bus_project.write(&x_serial_bus_project)) // make write v->status_serial_bus.count_write_error++; if (old_err == v->status_serial_bus.count_write_error)// no errors { v->status_serial_bus.count_write_ok++; err = 0; // no errors } else err = 1; // !errors! err_ready = check_cds_ready_sbus( err, ITS_WRITE_BUS, &v->status_serial_bus); set_status_cds(err_ready, &v->status); return err_ready; } /////////////////////////////////////////////// /////////////////////////////////////////////// /////////////////////////////////////////////// int cds_tk_read_sbus_10510(T_cds_tk_10510 *v) { unsigned int old_err, err = 0, err_ready = 0; if (v->useit == 0) return 0; old_err = v->status_serial_bus.count_read_error; x_serial_bus_project.slave_addr = v->plane_address; // number plate //0 mask_tk_out_40pin x_serial_bus_project.reg_addr = 0; // adr memory in plate x_serial_bus_project.read(&x_serial_bus_project); // read if (x_serial_bus_project.flags.bit.read_error == 0) // check error v->read.sbus.mask_tk_out_40pin.all = x_serial_bus_project.read_data; else v->status_serial_bus.count_read_error++; //1 deadtime x_serial_bus_project.reg_addr = 1; // adr memory in plate x_serial_bus_project.read(&x_serial_bus_project); // read if (x_serial_bus_project.flags.bit.read_error == 0) // check error v->read.sbus.deadtime.all = x_serial_bus_project.read_data; else v->status_serial_bus.count_read_error++; //2 ack_time x_serial_bus_project.reg_addr = 2; // adr memory in plate x_serial_bus_project.read(&x_serial_bus_project); // read if (x_serial_bus_project.flags.bit.read_error == 0) // check error v->read.sbus.ack_time.all = x_serial_bus_project.read_data; else v->status_serial_bus.count_read_error++; //3 mask_protect_tk x_serial_bus_project.reg_addr = 3; // adr memory in plate x_serial_bus_project.read(&x_serial_bus_project); // read if (x_serial_bus_project.flags.bit.read_error == 0) // check error v->read.sbus.mask_protect_tk.all = x_serial_bus_project.read_data; else v->status_serial_bus.count_read_error++; //4 protect_error x_serial_bus_project.reg_addr = 4; // adr memory in plate x_serial_bus_project.read(&x_serial_bus_project); // read if (x_serial_bus_project.flags.bit.read_error == 0) // check error v->read.sbus.protect_error.all = x_serial_bus_project.read_data; else v->status_serial_bus.count_read_error++; //5 status_tk_40pin x_serial_bus_project.reg_addr = 5; // adr memory in plate x_serial_bus_project.read(&x_serial_bus_project); // read if (x_serial_bus_project.flags.bit.read_error == 0) // check error v->read.sbus.status_tk_40pin.all = x_serial_bus_project.read_data; else v->status_serial_bus.count_read_error++; //6 status_tk_96pin x_serial_bus_project.reg_addr = 6; // adr memory in plate x_serial_bus_project.read(&x_serial_bus_project); // read if (x_serial_bus_project.flags.bit.read_error == 0) // check error v->read.sbus.status_tk_96pin.all = x_serial_bus_project.read_data; else v->status_serial_bus.count_read_error++; //7 lock_status_error x_serial_bus_project.reg_addr = 7; // adr memory in plate x_serial_bus_project.read(&x_serial_bus_project); // read if (x_serial_bus_project.flags.bit.read_error == 0) // check error v->read.sbus.lock_status_error.all = x_serial_bus_project.read_data; else v->status_serial_bus.count_read_error++; //8 status_protect_current_ack x_serial_bus_project.reg_addr = 8; // adr memory in plate x_serial_bus_project.read(&x_serial_bus_project); // read if (x_serial_bus_project.flags.bit.read_error == 0) // check error v->read.sbus.status_protect_current_ack.all = x_serial_bus_project.read_data; else v->status_serial_bus.count_read_error++; //9 mintime x_serial_bus_project.reg_addr = 9; // adr memory in plate x_serial_bus_project.read(&x_serial_bus_project); // read if (x_serial_bus_project.flags.bit.read_error == 0) // check error v->read.sbus.mintime.all = x_serial_bus_project.read_data; else v->status_serial_bus.count_read_error++; //10 status_protect_deadtime_mintime x_serial_bus_project.reg_addr = 10; // adr memory in plate x_serial_bus_project.read(&x_serial_bus_project); // read if (x_serial_bus_project.flags.bit.read_error == 0) // check error v->read.sbus.status_protect_deadtime_mintime.all = x_serial_bus_project.read_data; else v->status_serial_bus.count_read_error++; //11 time_err_tk0_tk1 x_serial_bus_project.reg_addr = 11; // adr memory in plate x_serial_bus_project.read(&x_serial_bus_project); // read if (x_serial_bus_project.flags.bit.read_error == 0) // check error v->read.sbus.time_err_tk0_tk1 = x_serial_bus_project.read_data; else v->status_serial_bus.count_read_error++; //12 time_err_tk2_tk3 x_serial_bus_project.reg_addr = 12; // adr memory in plate x_serial_bus_project.read(&x_serial_bus_project); // read if (x_serial_bus_project.flags.bit.read_error == 0) // check error v->read.sbus.time_err_tk2_tk3 = x_serial_bus_project.read_data; else v->status_serial_bus.count_read_error++; //13 time_err_tk4_tk5 x_serial_bus_project.reg_addr = 13; // adr memory in plate x_serial_bus_project.read(&x_serial_bus_project); // read if (x_serial_bus_project.flags.bit.read_error == 0) // check error v->read.sbus.time_err_tk4_tk5 = x_serial_bus_project.read_data; else v->status_serial_bus.count_read_error++; //14 time_err_tk6_tk7 x_serial_bus_project.reg_addr = 14; // adr memory in plate x_serial_bus_project.read(&x_serial_bus_project); // read if (x_serial_bus_project.flags.bit.read_error == 0) // check error v->read.sbus.time_err_tk6_tk7 = x_serial_bus_project.read_data; else v->status_serial_bus.count_read_error++; //15 current_status_error x_serial_bus_project.reg_addr = 15; // adr memory in plate x_serial_bus_project.read(&x_serial_bus_project); // read if (x_serial_bus_project.flags.bit.read_error == 0) // check error { v->read.type_cds_xilinx = x_serial_bus_project.read_data & 0x1; v->read.sbus.current_status_error.all = x_serial_bus_project.read_data & 0xfffe; } else v->status_serial_bus.count_read_error++; /////////// if (old_err == v->status_serial_bus.count_read_error)// no errors { v->status_serial_bus.count_read_ok++; err = 0; // no errors } else err = 1; // !errors! err_ready = check_cds_ready_sbus( err, ITS_READ_BUS, &v->status_serial_bus); set_status_cds(err_ready, &v->status); return err_ready; } /////////////////////////////////////////////// /////////////////////////////////////////////// ///////////////////////////////////////////////