61 lines
3.2 KiB
Markdown
61 lines
3.2 KiB
Markdown
# 1SP0635 / 1SD536F2 timing decoder for DSView
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This decoder checks driver control and status responses:
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- `Vin1`: optional control sent to the first gate driver (legacy channel ID `vin`);
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- `Vstat`: edge acknowledgement and fault feedback returned by the driver.
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Built-in data-sheet profiles:
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| Profile | ACK delay (typ.) | ACK width (specified) | Long pulse |
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|---|---:|---:|---:|
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| 1SP0635 | 250 ns | 400...1050 ns | fault above 1.5 us |
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| 1SD536F2 | 380 ns | 600...1800 ns | fault above 1.8 us* |
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`*` The 1.8 us fault threshold is a project classification choice based on the
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data-sheet ACK maximum, not a verified universal manufacturer fault threshold.
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The previously stated 1.5 us manual threshold could not be verified.
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Correlated pulses within the ACK width limits pass. Uncorrelated pulses up to
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the fault threshold are warnings; pulses above it are faults. Width and fault
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annotations are emitted only when the pulse ends.
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The data sheets specify only a *typical* ACK delay, not minimum and maximum
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limits. DSView therefore emits a warning outside the configurable tolerance
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(default +/-100 ns). The ACK-width check uses the published min/max values.
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## Use in SETGUI
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The DSView build recipe packages this adapter together with the canonical
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`python/logic_analyzer/decoders/gate_timing.py` core. In the DSView tab,
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choose **Анализаторы SET → IGBT · 1SP0635 / 1SD536F2** (or search Decode for
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`IGBT 1SP/1SD`). Assign Vstat and, if available, Vin1, choose the driver profile, and set `Vstat acknowledge/fault level`
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to match the receiver circuit. The diagrams in the application manual show
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the logical event; some optical receiver circuits invert it.
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Use at least 50 MS/s; 100 MS/s or more is recommended. Never connect a DSLogic
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digital input directly to the IGBT gate (+15/-10 V) or to a power-stage node.
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Use the isolated optical receiver logic signals and a common logic ground.
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## Separate transistor pair analyzer
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This decoder analyzes only Vin1/Vstat driver responses. Vin1 is optional;
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Vstat alone retains pulse/fault classification, while Vin1 enables ACK timing
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and full-cycle results. Vstat is required. The channel ID `vin` remains stable.
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Pair analysis was moved to **Transistor pair** in the **Пользовательские**
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section. Add that decoder separately and assign Vin1/Vin2. Old pair settings
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on IGBT instances must be recreated in the new decoder. The pair checkbox,
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Vin2 assignment and pulse limits are no longer part of the driver decoder.
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## Full pulse cycle result
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The **Vin1 / ACK full cycle** waveform row displays OK, WARNING or FAULT
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across each complete sequence **Vin1 ON -> ACK -> Vin1 OFF -> ACK**.
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The annotation starts at Vin1 ON and ends at the end of the OFF acknowledgment.
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It is emitted only after both ACKs have been classified. A delay warning makes
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that cycle WARNING; missing ACK, invalid width or fault feedback makes it FAULT.
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A later normal cycle can be OK independently of previous cycles.
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Unfinished cycles are never marked OK. Active-low Vin1 is supported.
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The results panel retains its original layout without a large summary banner.
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Deadtime and mintime are provided by the separate Transistor pair analyzer.
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