feat(hdl): добавь двухтактовый буфер логического анализатора

hdl/logic-analyzer/rtl/la_capture_buffer.v

@@ -0,0 +1,29 @@
+// Portable dual-clock capture RAM for FPGA logic analyzers.
+// The module intentionally contains no vendor primitives: Quartus infers M9K
+// blocks on Cyclone IV, while other tools may infer their native block RAM.
+module la_capture_buffer #(
+    parameter SAMPLE_WIDTH = 16,
+    parameter ADDR_WIDTH   = 12
+) (
+    input  wire                    wr_clk,
+    input  wire                    wr_en,
+    input  wire [ADDR_WIDTH-1:0]   wr_addr,
+    input  wire [SAMPLE_WIDTH-1:0] wr_data,
+
+    input  wire                    rd_clk,
+    input  wire [ADDR_WIDTH-1:0]   rd_addr,
+    output reg  [SAMPLE_WIDTH-1:0] rd_data
+);
+    localparam DEPTH = (1 << ADDR_WIDTH);
+
+    reg [SAMPLE_WIDTH-1:0] memory [0:DEPTH-1];
+
+    always @(posedge wr_clk) begin
+        if (wr_en)
+            memory[wr_addr] <= wr_data;
+    end
+
+    // Registered read is supported directly by Cyclone IV M9K blocks.
+    always @(posedge rd_clk)
+        rd_data <= memory[rd_addr];
+endmodule