30 lines
960 B
Verilog
30 lines
960 B
Verilog
// Portable dual-clock capture RAM for FPGA logic analyzers.
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// The module intentionally contains no vendor primitives: Quartus infers M9K
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// blocks on Cyclone IV, while other tools may infer their native block RAM.
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module la_capture_buffer #(
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parameter SAMPLE_WIDTH = 16,
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parameter ADDR_WIDTH = 12
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) (
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input wire wr_clk,
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input wire wr_en,
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input wire [ADDR_WIDTH-1:0] wr_addr,
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input wire [SAMPLE_WIDTH-1:0] wr_data,
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input wire rd_clk,
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input wire [ADDR_WIDTH-1:0] rd_addr,
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output reg [SAMPLE_WIDTH-1:0] rd_data
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);
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localparam DEPTH = (1 << ADDR_WIDTH);
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reg [SAMPLE_WIDTH-1:0] memory [0:DEPTH-1];
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always @(posedge wr_clk) begin
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if (wr_en)
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memory[wr_addr] <= wr_data;
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end
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// Registered read is supported directly by Cyclone IV M9K blocks.
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always @(posedge rd_clk)
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rd_data <= memory[rd_addr];
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endmodule
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