377 lines
14 KiB
C
377 lines
14 KiB
C
// TI File $Revision: /main/14 $
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// Checkin $Date: May 5, 2008 15:25:53 $
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//###########################################################################
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//
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// FILE: Example_2833xHRPWM.c
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//
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// TITLE: DSP2833x Device HRPWM example
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//
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// ASSUMPTIONS:
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//
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//
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// This program requires the DSP2833x header files.
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//
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// Monitor ePWM1-ePWM4 pins on an oscilloscope as described
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// below.
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//
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// EPWM1A is on GPIO0
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// EPWM1B is on GPIO1
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//
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// EPWM2A is on GPIO2
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// EPWM2B is on GPIO3
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//
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// EPWM3A is on GPIO4
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// EPWM3B is on GPIO5
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//
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// As supplied, this project is configured for "boot to SARAM"
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// operation. The 2833x Boot Mode table is shown below.
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// For information on configuring the boot mode of an eZdsp,
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// please refer to the documentation included with the eZdsp,
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//
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// $Boot_Table:
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//
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// GPIO87 GPIO86 GPIO85 GPIO84
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// XA15 XA14 XA13 XA12
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// PU PU PU PU
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// ==========================================
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// 1 1 1 1 Jump to Flash
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// 1 1 1 0 SCI-A boot
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// 1 1 0 1 SPI-A boot
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// 1 1 0 0 I2C-A boot
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// 1 0 1 1 eCAN-A boot
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// 1 0 1 0 McBSP-A boot
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// 1 0 0 1 Jump to XINTF x16
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// 1 0 0 0 Jump to XINTF x32
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// 0 1 1 1 Jump to OTP
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// 0 1 1 0 Parallel GPIO I/O boot
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// 0 1 0 1 Parallel XINTF boot
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// 0 1 0 0 Jump to SARAM <- "boot to SARAM"
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// 0 0 1 1 Branch to check boot mode
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// 0 0 1 0 Boot to flash, bypass ADC cal
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// 0 0 0 1 Boot to SARAM, bypass ADC cal
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// 0 0 0 0 Boot to SCI-A, bypass ADC cal
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// Boot_Table_End$
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//
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// DESCRIPTION:
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//
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// This example modifies the MEP control registers to show edge displacement
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// due to the HRPWM control extension of the respective ePWM module
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// All ePWM1A,2A,3A,4A channels (GPIO0, GPIO2, GPIO4, GPIO6) will have fine edge movement
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// due to HRPWM logic
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//
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// 1. 15MHz PWM (for 150 MHz SYSCLKOUT) or 10MHz PWM (for 100MHz SYSCLKOUT),
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// ePWM1A toggle low/high with MEP control on rising edge
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// 15MHz PWM (for 150 MHz SYSCLKOUT) or 10MHz PWM (for 100MHz SYSCLKOUT),
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// ePWM1B toggle low/high with NO HRPWM control
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//
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// 2. 7.5MHz PWM (for 150 MHz SYSCLKOUT) or 5MHz PWM (for 100MHz SYSCLKOUT),
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// ePWM2A toggle low/high with MEP control on rising edge
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// 7.5MHz PWM (for 150 MHz SYSCLKOUT) or 5MHz PWM (for 100MHz SYSCLKOUT),
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// ePWM2B toggle low/high with NO HRPWM control
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//
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// 3. 15MHz PWM (for 150 MHz SYSCLKOUT) or 10MHz PWM (for 100MHz SYSCLKOUT),
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// ePWM3A toggle as high/low with MEP control on falling edge
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// 15MHz PWM (for 150 MHz SYSCLKOUT) or 10MHz PWM (for 100MHz SYSCLKOUT),
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// ePWM3B toggle low/high with NO HRPWM control
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//
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// 4. 7.5MHz PWM (for 150 MHz SYSCLKOUT) or 5MHz PWM (for 100MHz SYSCLKOUT),
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// ePWM4A toggle as high/low with MEP control on falling edge
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// 7.5MHz PWM (for 150 MHz SYSCLKOUT) or 5MHz PWM (for 100MHz SYSCLKOUT),
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// ePWM4B toggle low/high with NO HRPWM control
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//
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//
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//###########################################################################
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// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
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// $Release Date: August 1, 2008 $
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//###########################################################################
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#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
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#include "DSP2833x_EPwm_defines.h" // useful defines for initialization
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// Declare your function prototypes here
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//---------------------------------------------------------------
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void HRPWM1_Config(int);
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void HRPWM2_Config(int);
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void HRPWM3_Config(int);
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void HRPWM4_Config(int);
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// General System nets - Useful for debug
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Uint16 i,j, DutyFine, n,update;
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Uint32 temp;
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void main(void)
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{
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// Step 1. Initialize System Control:
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// PLL, WatchDog, enable Peripheral Clocks
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// This example function is found in the DSP2833x_SysCtrl.c file.
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InitSysCtrl();
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// Step 2. Initalize GPIO:
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// This example function is found in the DSP2833x_Gpio.c file and
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// illustrates how to set the GPIO to it's default state.
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// InitGpio(); // Skipped for this example
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// For this case, just init GPIO for ePWM1-ePWM4
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// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3, ePWM4
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// These functions are in the DSP2833x_EPwm.c file
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InitEPwm1Gpio();
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InitEPwm2Gpio();
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InitEPwm3Gpio();
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InitEPwm4Gpio();
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// Step 3. Clear all interrupts and initialize PIE vector table:
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// Disable CPU interrupts
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DINT;
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// Initialize the PIE control registers to their default state.
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// The default state is all PIE interrupts disabled and flags
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// are cleared.
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// This function is found in the DSP2833x_PieCtrl.c file.
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InitPieCtrl();
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// Disable CPU interrupts and clear all CPU interrupt flags:
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IER = 0x0000;
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IFR = 0x0000;
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// Initialize the PIE vector table with pointers to the shell Interrupt
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// Service Routines (ISR).
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// This will populate the entire table, even if the interrupt
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// is not used in this example. This is useful for debug purposes.
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// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
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// This function is found in DSP2833x_PieVect.c.
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InitPieVectTable();
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// Step 4. Initialize all the Device Peripherals:
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// This function is found in DSP2833x_InitPeripherals.c
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// InitPeripherals(); // Not required for this example
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// For this example, only initialize the ePWM
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// Step 5. User specific code, enable interrupts:
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update =1;
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DutyFine =0;
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EALLOW;
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SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
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EDIS;
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// Some useful Period vs Frequency values
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// SYSCLKOUT = 150MHz 100 MHz
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// -----------------------------------------
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// Period Frequency Frequency
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// 1000 150 kHz 100 KHz
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// 800 187 kHz 125 KHz
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// 600 250 kHz 167 KHz
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// 500 300 kHz 200 KHz
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// 250 600 kHz 400 KHz
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// 200 750 kHz 500 KHz
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// 100 1.5 MHz 1.0 MHz
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// 50 3.0 MHz 2.0 MHz
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// 25 6.0 MHz 4.0 MHz
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// 20 7.5 MHz 5.0 MHz
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// 12 12.5 MHz 8.33 MHz
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// 10 15.0 MHz 10.0 MHz
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// 9 16.7 MHz 11.1 MHz
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// 8 18.8 MHz 12.5 MHz
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// 7 21.4 MHz 14.3 MHz
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// 6 25.0 MHz 16.7 MHz
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// 5 30.0 MHz 20.0 MHz
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//====================================================================
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// ePWM and HRPWM register initializaition
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//====================================================================
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HRPWM1_Config(10); // ePWM1 target, 15 MHz PWM (SYSCLK=150MHz) or 10 MHz PWM (SYSCLK=100MHz)
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HRPWM2_Config(20); // ePWM2 target, 7.5 MHz PWM (SYSCLK=150MHz) or 5 MHz PWM (SYSCLK=100MHz)
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HRPWM3_Config(10); // ePWM3 target, 15 MHz PWM (SYSCLK=150MHz) or 10 MHz PWM (SYSCLK=100MHz)
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HRPWM4_Config(20); // ePWM4 target, 7.5 MHz PWM (SYSCLK=150MHz) or 5 MHz PWM (SYSCLK=100MHz)
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EALLOW;
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SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
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EDIS;
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while (update ==1)
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{
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for(DutyFine =1; DutyFine <256 ;DutyFine ++)
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{
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// Example, write to the HRPWM extension of CMPA
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EPwm1Regs.CMPA.half.CMPAHR = DutyFine << 8; // Left shift by 8 to write into MSB bits
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EPwm2Regs.CMPA.half.CMPAHR = DutyFine << 8; // Left shift by 8 to write into MSB bits
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// Example, 32-bit write to CMPA:CMPAHR
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EPwm3Regs.CMPA.all = ((Uint32)EPwm3Regs.CMPA.half.CMPA << 16) + (DutyFine << 8);
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EPwm4Regs.CMPA.all = ((Uint32)EPwm4Regs.CMPA.half.CMPA << 16) + (DutyFine << 8);
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for (i=0;i<10000;i++){} // Dummy delay between MEP changes
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}
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}
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}
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void HRPWM1_Config(period)
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{
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// ePWM1 register configuration with HRPWM
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// ePWM1A toggle low/high with MEP control on Rising edge
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EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load
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EPwm1Regs.TBPRD = period-1; // PWM frequency = 1 / period
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EPwm1Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially
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EPwm1Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension
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EPwm1Regs.CMPB = period / 2; // set duty 50% initially
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EPwm1Regs.TBPHS.all = 0;
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EPwm1Regs.TBCTR = 0;
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EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
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EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // EPWM1 is the Master
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EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
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EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
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EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
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EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
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EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
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EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
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EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
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EPwm1Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // PWM toggle low/high
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EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;
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EPwm1Regs.AQCTLB.bit.ZRO = AQ_CLEAR;
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EPwm1Regs.AQCTLB.bit.CBU = AQ_SET;
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EALLOW;
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EPwm1Regs.HRCNFG.all = 0x0;
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EPwm1Regs.HRCNFG.bit.EDGMODE = HR_REP; //MEP control on Rising edge
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EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP;
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EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO;
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EDIS;
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}
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void HRPWM2_Config(period)
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{
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// ePWM2 register configuration with HRPWM
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// ePWM2A toggle low/high with MEP control on Rising edge
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EPwm2Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load
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EPwm2Regs.TBPRD = period-1; // PWM frequency = 1 / period
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EPwm2Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially
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EPwm2Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension
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EPwm2Regs.CMPB = period / 2; // set duty 50% initially
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EPwm2Regs.TBPHS.all = 0;
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EPwm2Regs.TBCTR = 0;
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EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
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EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM2 is the Master
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EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
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EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
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EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
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EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
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EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
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EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
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EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
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EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // PWM toggle low/high
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EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;
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EPwm2Regs.AQCTLB.bit.ZRO = AQ_CLEAR;
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EPwm2Regs.AQCTLB.bit.CBU = AQ_SET;
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EALLOW;
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EPwm2Regs.HRCNFG.all = 0x0;
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EPwm2Regs.HRCNFG.bit.EDGMODE = HR_REP; //MEP control on Rising edge
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EPwm2Regs.HRCNFG.bit.CTLMODE = HR_CMP;
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EPwm2Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO;
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EDIS;
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}
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void HRPWM3_Config(period)
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{
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// ePWM3 register configuration with HRPWM
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// ePWM3A toggle high/low with MEP control on falling edge
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EPwm3Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load
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EPwm3Regs.TBPRD = period-1; // PWM frequency = 1 / period
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EPwm3Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially
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EPwm3Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension
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EPwm3Regs.CMPB = period / 2; // set duty 50% initially
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EPwm3Regs.TBPHS.all = 0;
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EPwm3Regs.TBCTR = 0;
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EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
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EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM3 is the Master
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EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
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EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
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EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
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EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
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EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
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EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
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EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
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EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low
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EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR;
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EPwm3Regs.AQCTLB.bit.ZRO = AQ_SET;
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EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR;
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EALLOW;
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EPwm3Regs.HRCNFG.all = 0x0;
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EPwm3Regs.HRCNFG.bit.EDGMODE = HR_FEP; //MEP control on falling edge
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EPwm3Regs.HRCNFG.bit.CTLMODE = HR_CMP;
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EPwm3Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO;
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EDIS;
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}
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void HRPWM4_Config(period)
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{
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// ePWM4 register configuration with HRPWM
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// ePWM4A toggle high/low with MEP control on falling edge
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EPwm4Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load
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EPwm4Regs.TBPRD = period-1; // PWM frequency = 1 / period
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EPwm4Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially
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EPwm4Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension
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EPwm4Regs.CMPB = period / 2; // set duty 50% initially
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EPwm4Regs.TBPHS.all = 0;
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EPwm4Regs.TBCTR = 0;
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EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
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EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM4 is the Master
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EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
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EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
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EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;
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EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
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EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
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EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
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EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
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EPwm4Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low
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EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR;
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EPwm4Regs.AQCTLB.bit.ZRO = AQ_SET;
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EPwm4Regs.AQCTLB.bit.CBU = AQ_CLEAR;
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EALLOW;
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EPwm4Regs.HRCNFG.all = 0x0;
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EPwm4Regs.HRCNFG.bit.EDGMODE = HR_FEP; // MEP control on falling edge
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EPwm4Regs.HRCNFG.bit.CTLMODE = HR_CMP;
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EPwm4Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO;
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EDIS;
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}
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