236 lines
7.7 KiB
C
236 lines
7.7 KiB
C
// TI File $Revision: /main/2 $
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// Checkin $Date: March 1, 2007 15:57:02 $
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//###########################################################################
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//
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// FILE: DSP2833x_Sci.h
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//
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// TITLE: DSP2833x Device SCI Register Definitions.
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//
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//###########################################################################
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// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
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// $Release Date: August 1, 2008 $
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//###########################################################################
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#ifndef DSP2833x_SCI_H
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#define DSP2833x_SCI_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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//---------------------------------------------------------------------------
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// SCI Individual Register Bit Definitions
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//----------------------------------------------------------
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// SCICCR communication control register bit definitions:
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//
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struct SCICCR_BITS { // bit description
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Uint16 SCICHAR:3; // 2:0 Character length control
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Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control
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Uint16 LOOPBKENA:1; // 4 Loop Back enable
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Uint16 PARITYENA:1; // 5 Parity enable
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Uint16 PARITY:1; // 6 Even or Odd Parity
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Uint16 STOPBITS:1; // 7 Number of Stop Bits
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Uint16 rsvd1:8; // 15:8 reserved
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};
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union SCICCR_REG {
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Uint16 all;
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struct SCICCR_BITS bit;
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};
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//-------------------------------------------
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// SCICTL1 control register 1 bit definitions:
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//
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struct SCICTL1_BITS { // bit description
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Uint16 RXENA:1; // 0 SCI receiver enable
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Uint16 TXENA:1; // 1 SCI transmitter enable
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Uint16 SLEEP:1; // 2 SCI sleep
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Uint16 TXWAKE:1; // 3 Transmitter wakeup method
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Uint16 rsvd:1; // 4 reserved
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Uint16 SWRESET:1; // 5 Software reset
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Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable
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Uint16 rsvd1:9; // 15:7 reserved
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};
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union SCICTL1_REG {
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Uint16 all;
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struct SCICTL1_BITS bit;
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};
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//---------------------------------------------
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// SCICTL2 control register 2 bit definitions:
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//
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struct SCICTL2_BITS { // bit description
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Uint16 TXINTENA:1; // 0 Transmit interrupt enable
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Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable
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Uint16 rsvd:4; // 5:2 reserved
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Uint16 TXEMPTY:1; // 6 Transmitter empty flag
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Uint16 TXRDY:1; // 7 Transmitter ready flag
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Uint16 rsvd1:8; // 15:8 reserved
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};
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union SCICTL2_REG {
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Uint16 all;
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struct SCICTL2_BITS bit;
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};
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//---------------------------------------------------
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// SCIRXST Receiver status register bit definitions:
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//
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struct SCIRXST_BITS { // bit description
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Uint16 rsvd:1; // 0 reserved
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Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag
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Uint16 PE:1; // 2 Parity error flag
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Uint16 OE:1; // 3 Overrun error flag
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Uint16 FE:1; // 4 Framing error flag
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Uint16 BRKDT:1; // 5 Break-detect flag
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Uint16 RXRDY:1; // 6 Receiver ready flag
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Uint16 RXERROR:1; // 7 Receiver error flag
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};
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union SCIRXST_REG {
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Uint16 all;
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struct SCIRXST_BITS bit;
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};
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//----------------------------------------------------
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// SCIRXBUF Receiver Data Buffer with FIFO bit definitions:
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//
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struct SCIRXBUF_BITS { // bits description
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Uint16 RXDT:8; // 7:0 Receive word
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Uint16 rsvd:6; // 13:8 reserved
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Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode
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Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode
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};
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union SCIRXBUF_REG {
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Uint16 all;
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struct SCIRXBUF_BITS bit;
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};
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//--------------------------------------------------
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// SCIPRI Priority control register bit definitions:
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//
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//
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struct SCIPRI_BITS { // bit description
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Uint16 rsvd:3; // 2:0 reserved
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Uint16 FREE:1; // 3 Free emulation suspend mode
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Uint16 SOFT:1; // 4 Soft emulation suspend mode
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Uint16 rsvd1:3; // 7:5 reserved
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};
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union SCIPRI_REG {
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Uint16 all;
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struct SCIPRI_BITS bit;
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};
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//-------------------------------------------------
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// SCI FIFO Transmit register bit definitions:
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//
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//
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struct SCIFFTX_BITS { // bit description
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Uint16 TXFFIL:5; // 4:0 Interrupt level
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Uint16 TXFFIENA:1; // 5 Interrupt enable
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Uint16 TXFFINTCLR:1; // 6 Clear INT flag
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Uint16 TXFFINT:1; // 7 INT flag
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Uint16 TXFFST:5; // 12:8 FIFO status
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Uint16 TXFIFOXRESET:1; // 13 FIFO reset
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Uint16 SCIFFENA:1; // 14 Enhancement enable
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Uint16 SCIRST:1; // 15 SCI reset rx/tx channels
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};
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union SCIFFTX_REG {
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Uint16 all;
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struct SCIFFTX_BITS bit;
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};
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//------------------------------------------------
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// SCI FIFO recieve register bit definitions:
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//
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//
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struct SCIFFRX_BITS { // bits description
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Uint16 RXFFIL:5; // 4:0 Interrupt level
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Uint16 RXFFIENA:1; // 5 Interrupt enable
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Uint16 RXFFINTCLR:1; // 6 Clear INT flag
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Uint16 RXFFINT:1; // 7 INT flag
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Uint16 RXFFST:5; // 12:8 FIFO status
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Uint16 RXFIFORESET:1; // 13 FIFO reset
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Uint16 RXFFOVRCLR:1; // 14 Clear overflow
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Uint16 RXFFOVF:1; // 15 FIFO overflow
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};
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union SCIFFRX_REG {
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Uint16 all;
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struct SCIFFRX_BITS bit;
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};
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// SCI FIFO control register bit definitions:
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struct SCIFFCT_BITS { // bits description
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Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay
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Uint16 rsvd:5; // 12:8 reserved
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Uint16 CDC:1; // 13 Auto baud mode enable
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Uint16 ABDCLR:1; // 14 Auto baud clear
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Uint16 ABD:1; // 15 Auto baud detect
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};
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union SCIFFCT_REG {
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Uint16 all;
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struct SCIFFCT_BITS bit;
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};
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//---------------------------------------------------------------------------
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// SCI Register File:
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//
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struct SCI_REGS {
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union SCICCR_REG SCICCR; // Communications control register
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union SCICTL1_REG SCICTL1; // Control register 1
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Uint16 SCIHBAUD; // Baud rate (high) register
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Uint16 SCILBAUD; // Baud rate (low) register
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union SCICTL2_REG SCICTL2; // Control register 2
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union SCIRXST_REG SCIRXST; // Recieve status register
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Uint16 SCIRXEMU; // Recieve emulation buffer register
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union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer
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Uint16 rsvd1; // reserved
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Uint16 SCITXBUF; // Transmit data buffer
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union SCIFFTX_REG SCIFFTX; // FIFO transmit register
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union SCIFFRX_REG SCIFFRX; // FIFO recieve register
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union SCIFFCT_REG SCIFFCT; // FIFO control register
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Uint16 rsvd2; // reserved
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Uint16 rsvd3; // reserved
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union SCIPRI_REG SCIPRI; // FIFO Priority control
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};
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//---------------------------------------------------------------------------
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// SCI External References & Function Declarations:
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//
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extern volatile struct SCI_REGS SciaRegs;
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extern volatile struct SCI_REGS ScibRegs;
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extern volatile struct SCI_REGS ScicRegs;
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#ifdef __cplusplus
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}
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#endif /* extern "C" */
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#endif // end of DSP2833x_SCI_H definition
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//===========================================================================
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// End of file.
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//===========================================================================
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